Searched refs:InsElt (Results 1 – 7 of 7) sorted by relevance
/freebsd/contrib/llvm-project/llvm/lib/Transforms/InstCombine/ |
H A D | InstCombineVectorOps.cpp | 694 static bool replaceExtractElements(InsertElementInst *InsElt, in replaceExtractElements() argument 697 auto *InsVecType = cast<FixedVectorType>(InsElt->getType()); in replaceExtractElements() 732 if (InsertionBlock != InsElt->getParent()) in replaceExtractElements() 740 if (InsElt->hasOneUse() && isa<InsertElementInst>(InsElt->user_back())) in replaceExtractElements() 1213 static Instruction *foldInsSequenceIntoSplat(InsertElementInst &InsElt) { in foldInsSequenceIntoSplat() argument 1216 if (InsElt.hasOneUse() && isa<InsertElementInst>(InsElt.user_back())) in foldInsSequenceIntoSplat() 1219 VectorType *VecTy = InsElt.getType(); in foldInsSequenceIntoSplat() 1231 Value *SplatVal = InsElt.getOperand(1); in foldInsSequenceIntoSplat() 1232 InsertElementInst *CurrIE = &InsElt; in foldInsSequenceIntoSplat() 1247 if (CurrIE != &InsElt && in foldInsSequenceIntoSplat() [all …]
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H A D | InstCombineCasts.cpp | 656 auto *InsElt = dyn_cast<InsertElementInst>(Trunc.getOperand(0)); in shrinkInsertElt() local 657 if (!InsElt || !InsElt->hasOneUse()) in shrinkInsertElt() 662 Value *VecOp = InsElt->getOperand(0); in shrinkInsertElt() 663 Value *ScalarOp = InsElt->getOperand(1); in shrinkInsertElt() 664 Value *Index = InsElt->getOperand(2); in shrinkInsertElt() 2724 if (auto *InsElt = dyn_cast<InsertElementInst>(Src)) in visitBitCast() local 2725 return new BitCastInst(InsElt->getOperand(1), DestTy); in visitBitCast()
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/freebsd/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/ |
H A D | MachineIRBuilder.cpp | 756 auto InsElt = buildInsertVectorElement(DstTy, UndefVec, Src, Zero); in buildShuffleSplat() local 758 return buildShuffleVector(DstTy, InsElt, UndefVec, ZeroMask); in buildShuffleSplat()
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/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/GISel/ |
H A D | AArch64InstructionSelector.cpp | 4536 auto InsElt = in emitVectorConcat() local 4542 constrainSelectedInstRegOperands(*InsElt, TII, TRI, RBI); in emitVectorConcat() 4543 return &*InsElt; in emitVectorConcat() 5146 MachineInstr *InsElt = nullptr; in emitLaneInsert() local 5159 InsElt = MIRBuilder.buildInstr(Opc, {*DstReg}, {SrcReg}) in emitLaneInsert() 5164 InsElt = MIRBuilder.buildInstr(Opc, {*DstReg}, {SrcReg}) in emitLaneInsert() 5169 constrainSelectedInstRegOperands(*InsElt, TII, TRI, RBI); in emitLaneInsert() 5170 return InsElt; in emitLaneInsert()
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/freebsd/contrib/llvm-project/llvm/lib/Transforms/Vectorize/ |
H A D | SLPVectorizer.cpp | 11637 auto *InsElt = dyn_cast<InsertElementInst>(Vec); in gather() local 11638 if (!InsElt) in gather() 11640 GatherShuffleExtractSeq.insert(InsElt); in gather() 11641 CSEBlocks.insert(InsElt->getParent()); in gather() 11651 UserOp = InsElt; in gather()
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/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/ |
H A D | ARMISelLowering.cpp | 15503 SDValue InsElt = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, FloatVT, in PerformInsertEltCombine() local 15505 return DAG.getNode(ISD::BITCAST, dl, VT, InsElt); in PerformInsertEltCombine()
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/freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
H A D | DAGCombiner.cpp | 25789 if (SDValue InsElt = replaceShuffleOfInsert(SVN, DAG)) in visitVECTOR_SHUFFLE() local 25790 return InsElt; in visitVECTOR_SHUFFLE()
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