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Searched refs:Ins (Results 1 – 25 of 122) sorted by relevance

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/freebsd/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMipsCCState.h47 void PreAnalyzeCallResultForF128(const SmallVectorImpl<ISD::InputArg> &Ins,
64 PreAnalyzeFormalArgumentsForF128(const SmallVectorImpl<ISD::InputArg> &Ins);
67 PreAnalyzeCallResultForVectorFloat(const SmallVectorImpl<ISD::InputArg> &Ins,
71 const SmallVectorImpl<ISD::InputArg> &Ins);
131 void PreAnalyzeFormalArguments(const SmallVectorImpl<ISD::InputArg> &Ins, in PreAnalyzeFormalArguments() argument
136 PreAnalyzeFormalArgumentsForF128(Ins); in PreAnalyzeFormalArguments()
139 void AnalyzeFormalArguments(const SmallVectorImpl<ISD::InputArg> &Ins, in AnalyzeFormalArguments() argument
141 PreAnalyzeFormalArguments(Ins, Fn); in AnalyzeFormalArguments()
142 CCState::AnalyzeFormalArguments(Ins, Fn); in AnalyzeFormalArguments()
151 void PreAnalyzeCallResult(const SmallVectorImpl<ISD::InputArg> &Ins, in PreAnalyzeCallResult() argument
[all …]
H A DMipsCCState.cpp86 const SmallVectorImpl<ISD::InputArg> &Ins, in PreAnalyzeCallResultForF128() argument
88 for (unsigned i = 0; i < Ins.size(); ++i) { in PreAnalyzeCallResultForF128()
110 const SmallVectorImpl<ISD::InputArg> &Ins, const Type *RetTy) { in PreAnalyzeCallResultForVectorFloat() argument
111 for (unsigned i = 0; i < Ins.size(); ++i) { in PreAnalyzeCallResultForVectorFloat()
179 const SmallVectorImpl<ISD::InputArg> &Ins) { in PreAnalyzeFormalArgumentsForF128() argument
181 for (unsigned i = 0; i < Ins.size(); ++i) { in PreAnalyzeFormalArgumentsForF128()
187 if (Ins[i].Flags.isSRet()) { in PreAnalyzeFormalArgumentsForF128()
194 assert(Ins[i].getOrigArgIndex() < MF.getFunction().arg_size()); in PreAnalyzeFormalArgumentsForF128()
195 std::advance(FuncArg, Ins[i].getOrigArgIndex()); in PreAnalyzeFormalArgumentsForF128()
/freebsd/contrib/llvm-project/llvm/lib/Transforms/Scalar/
H A DStraightLineStrengthReduce.cpp148 : CandidateKind(CT), Base(B), Index(Idx), Stride(S), Ins(I) {} in Candidate()
175 Instruction *Ins = nullptr; member
274 return (Basis.Ins != C.Ins && // skip the same instruction in isBasisFor()
277 Basis.Ins->getType() == C.Ins->getType() && in isBasisFor()
279 DT->dominates(Basis.Ins->getParent(), C.Ins->getParent()) && in isBasisFor()
307 return isGEPFoldable(cast<GetElementPtrInst>(C.Ins), TTI); in isFoldable()
334 hasOnlyOneNonZeroIndex(cast<GetElementPtrInst>(C.Ins))); in isSimplestForm()
598 IntegerType::get(Basis.Ins->getContext(), IndexOffset.getBitWidth()); in emitBump()
624 assert(Basis.Ins->getParent() != nullptr && "the basis is unlinked"); in rewriteCandidateWithBasis()
630 if (!C.Ins->getParent()) in rewriteCandidateWithBasis()
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/freebsd/contrib/llvm-project/llvm/lib/CodeGen/
H A DCallingConvLower.cpp85 CCState::AnalyzeFormalArguments(const SmallVectorImpl<ISD::InputArg> &Ins, in AnalyzeFormalArguments() argument
87 unsigned NumArgs = Ins.size(); in AnalyzeFormalArguments()
90 MVT ArgVT = Ins[i].VT; in AnalyzeFormalArguments()
91 ISD::ArgFlagsTy ArgFlags = Ins[i].Flags; in AnalyzeFormalArguments()
162 void CCState::AnalyzeCallResult(const SmallVectorImpl<ISD::InputArg> &Ins, in AnalyzeCallResult() argument
164 for (unsigned i = 0, e = Ins.size(); i != e; ++i) { in AnalyzeCallResult()
165 MVT VT = Ins[i].VT; in AnalyzeCallResult()
166 ISD::ArgFlagsTy Flags = Ins[i].Flags; in AnalyzeCallResult()
264 const SmallVectorImpl<ISD::InputArg> &Ins, in resultsCompatible() argument
270 CCInfo1.AnalyzeCallResult(Ins, CalleeFn); in resultsCompatible()
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/freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCCCState.h25 PreAnalyzeFormalArguments(const SmallVectorImpl<ISD::InputArg> &Ins);
50 void AnalyzeFormalArguments(const SmallVectorImpl<ISD::InputArg> &Ins, in AnalyzeFormalArguments() argument
53 IsFixed.resize(Ins.size(), true); in AnalyzeFormalArguments()
54 CCState::AnalyzeFormalArguments(Ins, Fn); in AnalyzeFormalArguments()
H A DPPCCCState.cpp25 const SmallVectorImpl<ISD::InputArg> &Ins) { in PreAnalyzeFormalArguments() argument
26 for (const auto &I : Ins) { in PreAnalyzeFormalArguments()
H A DPPCISelLowering.h1262 const SmallVectorImpl<ISD::InputArg> &Ins) const;
1268 const SmallVectorImpl<ISD::InputArg> &Ins, const Function *CallerFunc,
1275 const SmallVectorImpl<ISD::InputArg> &Ins,
1365 const SmallVectorImpl<ISD::InputArg> &Ins,
1373 const SmallVectorImpl<ISD::InputArg> &Ins,
1379 const SmallVectorImpl<ISD::InputArg> &Ins,
1402 const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl,
1406 const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl,
1410 const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl,
1421 const SmallVectorImpl<ISD::InputArg> &Ins,
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H A DPPCRegisterInfo.cpp1065 MachineBasicBlock::reverse_iterator Ins = MI; in lowerCRBitSpilling() local
1067 ++Ins; in lowerCRBitSpilling()
1070 for (; Ins != Rend; ++Ins) { in lowerCRBitSpilling()
1072 if (Ins->modifiesRegister(SrcReg, TRI)) in lowerCRBitSpilling()
1075 if (Ins->readsRegister(SrcReg, TRI)) in lowerCRBitSpilling()
1079 Ins = MI; in lowerCRBitSpilling()
1083 if (!Ins->isDebugInstr()) in lowerCRBitSpilling()
1088 if (Ins == MBB.rend()) in lowerCRBitSpilling()
1089 Ins = MI; in lowerCRBitSpilling()
1093 switch (Ins->getOpcode()) { in lowerCRBitSpilling()
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/freebsd/contrib/llvm-project/llvm/lib/Target/SystemZ/
H A DSystemZCallingConv.h51 void AnalyzeFormalArguments(const SmallVectorImpl<ISD::InputArg> &Ins, in AnalyzeFormalArguments() argument
55 for (unsigned i = 0; i < Ins.size(); ++i) in AnalyzeFormalArguments()
59 for (unsigned i = 0; i < Ins.size(); ++i) in AnalyzeFormalArguments()
60 ArgIsShortVector.push_back(IsShortVectorType(Ins[i].ArgVT)); in AnalyzeFormalArguments()
62 CCState::AnalyzeFormalArguments(Ins, Fn); in AnalyzeFormalArguments()
/freebsd/contrib/llvm-project/llvm/lib/Target/Lanai/
H A DLanaiISelLowering.h78 const SmallVectorImpl<ISD::InputArg> &Ins,
84 const SmallVectorImpl<ISD::InputArg> &Ins,
90 const SmallVectorImpl<ISD::InputArg> &Ins,
99 const SmallVectorImpl<ISD::InputArg> &Ins,
/freebsd/contrib/llvm-project/llvm/lib/Transforms/Instrumentation/
H A DPGOCtxProfFlattening.cpp97 const InstrProfCallsite &Ins) { in annotateIndirectCall() argument
98 auto Idx = Ins.getIndex()->getZExtValue(); in annotateIndirectCall()
138 if (auto *Ins = CtxProfAnalysis::getCallsiteInstrumentation(*CB)) in annotateIndirectCalls() local
139 annotateIndirectCall(M, *CB, FlatProf, *Ins); in annotateIndirectCalls()
/freebsd/contrib/llvm-project/llvm/lib/Target/MSP430/
H A DMSP430ISelLowering.h91 const SmallVectorImpl<ISD::InputArg> &Ins,
97 const SmallVectorImpl<ISD::InputArg> &Ins,
103 const SmallVectorImpl<ISD::InputArg> &Ins,
109 const SmallVectorImpl<ISD::InputArg> &Ins,
H A DMSP430ISelLowering.cpp326 const SmallVectorImpl<ISD::InputArg> &Ins) { in AnalyzeVarArgs() argument
327 State.AnalyzeFormalArguments(Ins, CC_MSP430_AssignStack); in AnalyzeVarArgs()
430 const SmallVectorImpl<ISD::InputArg> &Ins) { in AnalyzeRetResult() argument
431 State.AnalyzeCallResult(Ins, RetCC_MSP430); in AnalyzeRetResult()
448 const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl, in LowerFormalArguments() argument
456 return LowerCCCArguments(Chain, CallConv, isVarArg, Ins, dl, DAG, InVals); in LowerFormalArguments()
458 if (Ins.empty()) in LowerFormalArguments()
471 SmallVectorImpl<ISD::InputArg> &Ins = CLI.Ins; in LowerCall() local
488 Outs, OutVals, Ins, dl, DAG, InVals); in LowerCall()
499 const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl, in LowerCCCArguments() argument
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/freebsd/contrib/llvm-project/llvm/lib/Analysis/
H A DCtxProfAnalysis.cpp319 if (auto *Ins = CtxProfAnalysis::getBBInstrumentation( in ProfileAnnotatorImpl() local
321 auto Index = Ins->getIndex()->getZExtValue(); in ProfileAnnotatorImpl()
327 Count = Counters[Ins->getIndex()->getZExtValue()]; in ProfileAnnotatorImpl()
332 auto [It, Ins] = in ProfileAnnotatorImpl()
334 (void)Ins; in ProfileAnnotatorImpl()
335 assert(Ins && "We iterate through the function's BBs, no reason to " in ProfileAnnotatorImpl()
536 auto [It, Ins] = Result.FuncInfo.insert( in run()
538 (void)Ins; in run()
539 assert(Ins); in run()
/freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DCallingConvLower.h264 AnalyzeFormalArguments(const SmallVectorImpl<ISD::InputArg> &Ins,
268 void AnalyzeArguments(const SmallVectorImpl<ISD::InputArg> &Ins, in AnalyzeArguments() argument
270 AnalyzeFormalArguments(Ins, Fn); in AnalyzeArguments()
303 LLVM_ABI void AnalyzeCallResult(const SmallVectorImpl<ISD::InputArg> &Ins,
512 const SmallVectorImpl<ISD::InputArg> &Ins,
/freebsd/contrib/llvm-project/llvm/lib/Target/XCore/
H A DXCoreISelLowering.h82 const SmallVectorImpl<ISD::InputArg> &Ins,
90 const SmallVectorImpl<ISD::InputArg> &Ins,
141 const SmallVectorImpl<ISD::InputArg> &Ins,
/freebsd/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86ISelLoweringCall.cpp1122 const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl, in LowerCallResult() argument
1131 CCInfo.AnalyzeCallResult(Ins, RetCC_X86); in LowerCallResult()
1325 const SmallVectorImpl<ISD::InputArg> &Ins, in LowerMemArgument() argument
1330 ISD::ArgFlagsTy Flags = Ins[i].Flags; in LowerMemArgument()
1364 EVT ArgVT = Ins[i].ArgVT; in LowerMemArgument()
1379 if (Ins[i].PartOffset == 0) { in LowerMemArgument()
1408 DAG.getIntPtrConstant(Ins[i].PartOffset, dl)); in LowerMemArgument()
1411 DAG.getMachineFunction(), FI, Ins[i].PartOffset)); in LowerMemArgument()
1703 const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl, in LowerFormalArguments() argument
1729 CCInfo.AnalyzeArguments(Ins, CC_X86); in LowerFormalArguments()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/ARC/
H A DARCISelLowering.h53 const SmallVectorImpl<ISD::InputArg> &Ins,
67 const SmallVectorImpl<ISD::InputArg> &Ins,
H A DARCISelLowering.cpp252 SmallVectorImpl<ISD::InputArg> &Ins = CLI.Ins; in LowerCall() local
272 RetCCInfo.AnalyzeCallResult(Ins, RetCC_ARC); in LowerCall()
454 const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl, in LowerFormalArguments() argument
461 return LowerCallArguments(Chain, CallConv, IsVarArg, Ins, dl, DAG, InVals); in LowerFormalArguments()
469 const SmallVectorImpl<ISD::InputArg> &Ins, SDLoc dl, SelectionDAG &DAG, in LowerCallArguments() argument
481 CCInfo.AnalyzeFormalArguments(Ins, CC_ARC); in LowerCallArguments()
535 const ArgDataPair ADP = {ArgIn, Ins[i].Flags}; in LowerCallArguments()
/freebsd/contrib/llvm-project/llvm/lib/Transforms/Vectorize/
H A DVPlanUnroll.cpp96 auto Ins = VPV2Parts.insert({VPV, {}}); in addRecipeForPart() local
97 assert(Ins.first->second.size() == Part - 1 && "earlier parts not set"); in addRecipeForPart()
98 Ins.first->second.push_back(CopyR->getVPValue(Idx)); in addRecipeForPart()
104 auto Ins = VPV2Parts.insert({R, {}}); in addUniformForAllParts() local
105 assert(Ins.second && "uniform value already added"); in addUniformForAllParts()
107 Ins.first->second.push_back(R); in addUniformForAllParts()
/freebsd/contrib/llvm-project/llvm/lib/Target/Sparc/
H A DSparcISelLowering.h88 const SmallVectorImpl<ISD::InputArg> &Ins,
93 const SmallVectorImpl<ISD::InputArg> &Ins,
98 const SmallVectorImpl<ISD::InputArg> &Ins,
/freebsd/contrib/llvm-project/llvm/lib/Target/BPF/
H A DBPFISelLowering.cpp343 const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &DL, in LowerFormalArguments() argument
359 CCInfo.AnalyzeFormalArguments(Ins, getHasAlu32() ? CC_BPF32 : CC_BPF64); in LowerFormalArguments()
441 auto &Ins = CLI.Ins; in LowerCall() local
579 return LowerCallResult(Chain, InGlue, CallConv, IsVarArg, Ins, CLI.DL, DAG, in LowerCall()
634 const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &DL, in LowerCallResult() argument
642 if (Ins.size() > 1) { in LowerCallResult()
644 for (auto &In : Ins) in LowerCallResult()
646 return DAG.getCopyFromReg(Chain, DL, 1, Ins[0].VT, InGlue).getValue(1); in LowerCallResult()
649 CCInfo.AnalyzeCallResult(Ins, getHasAlu32() ? RetCC_BPF32 : RetCC_BPF64); in LowerCallResult()
H A DBPFISelLowering.h91 const SmallVectorImpl<ISD::InputArg> &Ins,
105 const SmallVectorImpl<ISD::InputArg> &Ins,
/freebsd/contrib/llvm-project/llvm/lib/Target/M68k/
H A DM68kISelLowering.h186 const SmallVectorImpl<ISD::InputArg> &Ins,
195 const SmallVectorImpl<ISD::InputArg> &Ins,
253 const SmallVectorImpl<ISD::InputArg> &Ins, SelectionDAG &DAG) const;
/freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonCommonGEP.cpp561 std::pair<NodeSymRel::iterator, bool> Ins = EqRel.insert(C); in common() local
562 (void)Ins; in common()
563 assert(Ins.second && "Cannot add a class"); in common()
590 std::pair<ProjMap::iterator,bool> Ins = PM.insert(std::make_pair(&S, Min)); in common() local
591 (void)Ins; in common()
592 assert(Ins.second && "Cannot add minimal element"); in common()
1234 ValueVect Ins; in removeDeadCode() local
1236 Ins.push_back(&I); in removeDeadCode()
1237 for (Value *I : Ins) { in removeDeadCode()

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