| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/ |
| H A D | UnreachableBlockElim.cpp | 169 Register InputReg = Input.getReg(); in runOnMachineFunction() local
174 if (InputReg != OutputReg) { in runOnMachineFunction()
178 MRI.constrainRegClass(InputReg, MRI.getRegClass(OutputReg)) && in runOnMachineFunction()
180 MRI.replaceRegWith(OutputReg, InputReg); in runOnMachineFunction()
189 .addReg(InputReg, getRegState(Input), InputSub); in runOnMachineFunction()
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| H A D | TargetInstrInfo.cpp | 1680 RegSubRegPairAndIdx &InputReg) const { in getExtractSubregInputs()
1685 return getExtractSubregLikeInputs(MI, DefIdx, InputReg); in getExtractSubregInputs()
1697 InputReg.Reg = MOReg.getReg(); in getExtractSubregInputs()
1698 InputReg.SubReg = MOReg.getSubReg(); in getExtractSubregInputs()
1699 InputReg.SubIdx = (unsigned)MOSubIdx.getImm(); in getExtractSubregInputs()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | AMDGPUCallLowering.cpp | 820 Register InputReg = MRI.createGenericVirtualRegister(ArgTy); in passSpecialInputs() local
823 LI->loadInputValue(InputReg, MIRBuilder, IncomingArg, ArgRC, ArgTy); in passSpecialInputs()
825 LI->getImplicitArgPtr(InputReg, MRI, MIRBuilder); in passSpecialInputs()
830 MIRBuilder.buildConstant(InputReg, *Id); in passSpecialInputs()
832 MIRBuilder.buildUndef(InputReg); in passSpecialInputs()
837 MIRBuilder.buildUndef(InputReg); in passSpecialInputs()
841 ArgRegs.emplace_back(OutgoingArg->getRegister(), InputReg); in passSpecialInputs()
885 Register InputReg; in passSpecialInputs() local
889 InputReg = MRI.createGenericVirtualRegister(S32); in passSpecialInputs()
890 LI->loadInputValue(InputReg, MIRBuilder, IncomingArgX, in passSpecialInputs()
[all …]
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| H A D | SIWholeQuadMode.cpp | 1551 Register InputReg = MI.getOperand(0).getReg(); in lowerInitExec() local
1553 if (InputReg.isVirtual()) { in lowerInitExec()
1554 MachineInstr *DefInstr = MRI->getVRegDef(InputReg); in lowerInitExec()
1577 .addReg(InputReg) in lowerInitExec()
1606 LIS->removeInterval(InputReg); in lowerInitExec()
1607 LIS->createAndComputeVirtRegInterval(InputReg); in lowerInitExec()
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| H A D | SIISelLowering.cpp | 3381 SDValue InputReg; in passSpecialInputs() local
3384 InputReg = loadInputValue(DAG, ArgRC, ArgVT, DL, *IncomingArg); in passSpecialInputs()
3388 InputReg = getImplicitArgPtr(DAG, DL); in passSpecialInputs()
3393 InputReg = DAG.getConstant(*Id, DL, ArgVT); in passSpecialInputs()
3395 InputReg = DAG.getUNDEF(ArgVT); in passSpecialInputs()
3400 InputReg = DAG.getUNDEF(ArgVT); in passSpecialInputs()
3404 RegsToPass.emplace_back(OutgoingArg->getRegister(), InputReg); in passSpecialInputs()
3410 SDValue ArgStore = storeStackInputValue(DAG, DL, Chain, InputReg, in passSpecialInputs()
3440 SDValue InputReg; in passSpecialInputs() local
3451 InputReg = loadInputValue(DAG, ArgRC, MVT::i32, DL, *IncomingArgX); in passSpecialInputs()
[all …]
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64MIPeepholeOpt.cpp | 698 Register InputReg = MI.getOperand(1).getReg(); in visitCopy() local
700 !MRI->hasOneNonDBGUse(InputReg)) in visitCopy()
703 MachineInstr *SrcMI = MRI->getUniqueVRegDef(InputReg); in visitCopy()
717 MRI->constrainRegClass(SrcReg, MRI->getRegClass(InputReg)); in visitCopy()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86FastISel.cpp | 2524 Register InputReg = getRegForValue(I->getOperand(0)); in X86SelectTrunc() local
2525 if (!InputReg) in X86SelectTrunc()
2531 updateValueMap(I, InputReg); in X86SelectTrunc()
2536 Register ResultReg = fastEmitInst_extractsubreg(MVT::i8, InputReg, in X86SelectTrunc()
2595 Register InputReg = getRegForValue(Op); in fastLowerIntrinsicCall() local
2596 if (InputReg == 0) in fastLowerIntrinsicCall()
2621 InputReg = fastEmitInst_ri(Opc, RC, InputReg, 4); in fastLowerIntrinsicCall()
2628 .addReg(InputReg, RegState::Kill); in fastLowerIntrinsicCall()
2636 InputReg = fastEmit_r(MVT::i16, MVT::i32, ISD::ZERO_EXTEND, InputReg); in fastLowerIntrinsicCall()
2639 InputReg = fastEmit_r(MVT::i32, MVT::v4i32, ISD::SCALAR_TO_VECTOR, in fastLowerIntrinsicCall()
[all …]
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| /freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/ |
| H A D | TargetInstrInfo.h | 567 RegSubRegPairAndIdx &InputReg) const;
1393 RegSubRegPairAndIdx &InputReg) const { in getExtractSubregLikeInputs() argument
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| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | FastISel.cpp | 1518 Register InputReg = getRegForValue(I->getOperand(0)); in selectCast() local
1519 if (!InputReg) in selectCast()
1524 Opcode, InputReg); in selectCast()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/ARM/ |
| H A D | ARMBaseInstrInfo.h | 80 RegSubRegPairAndIdx &InputReg) const override;
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| H A D | ARMBaseInstrInfo.cpp | 5481 RegSubRegPairAndIdx &InputReg) const { in getExtractSubregLikeInputs()
5494 InputReg.Reg = MOReg.getReg(); in getExtractSubregLikeInputs()
5495 InputReg.SubReg = MOReg.getSubReg(); in getExtractSubregLikeInputs()
5496 InputReg.SubIdx = DefIdx == 0 ? ARM::ssub_0 : ARM::ssub_1; in getExtractSubregLikeInputs()
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| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/ |
| H A D | IRTranslator.cpp | 2141 Register InputReg = in translateConvergenceControlIntrinsic() local
2143 MIB.addUse(InputReg); in translateConvergenceControlIntrinsic()
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