| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/ |
| H A D | UnreachableBlockElim.cpp | 202 Register InputReg = Input.getReg(); in run() local
207 if (InputReg != OutputReg) { in run()
211 MRI.constrainRegClass(InputReg, MRI.getRegClass(OutputReg)) && in run()
213 MRI.replaceRegWith(OutputReg, InputReg); in run()
222 .addReg(InputReg, getRegState(Input), InputSub); in run()
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| H A D | TargetInstrInfo.cpp | 1990 RegSubRegPairAndIdx &InputReg) const { in getExtractSubregInputs()
1995 return getExtractSubregLikeInputs(MI, DefIdx, InputReg); in getExtractSubregInputs()
2007 InputReg.Reg = MOReg.getReg(); in getExtractSubregInputs()
2008 InputReg.SubReg = MOReg.getSubReg(); in getExtractSubregInputs()
2009 InputReg.SubIdx = (unsigned)MOSubIdx.getImm(); in getExtractSubregInputs()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | AMDGPUCallLowering.cpp | 822 Register InputReg = MRI.createGenericVirtualRegister(ArgTy); in passSpecialInputs() local
825 LI->buildLoadInputValue(InputReg, MIRBuilder, IncomingArg, ArgRC, ArgTy); in passSpecialInputs()
827 LI->getImplicitArgPtr(InputReg, MRI, MIRBuilder); in passSpecialInputs()
832 MIRBuilder.buildConstant(InputReg, *Id); in passSpecialInputs()
834 MIRBuilder.buildUndef(InputReg); in passSpecialInputs()
839 MIRBuilder.buildUndef(InputReg); in passSpecialInputs()
843 ArgRegs.emplace_back(OutgoingArg->getRegister(), InputReg); in passSpecialInputs()
887 Register InputReg; in passSpecialInputs() local
891 InputReg = MRI.createGenericVirtualRegister(S32); in passSpecialInputs()
892 LI->buildLoadInputValue(InputReg, MIRBuilder, IncomingArgX, in passSpecialInputs()
[all …]
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| H A D | SIWholeQuadMode.cpp | 1619 Register InputReg = MI.getOperand(0).getReg(); in lowerInitExec() local
1621 if (InputReg.isVirtual()) { in lowerInitExec()
1622 MachineInstr *DefInstr = MRI->getVRegDef(InputReg); in lowerInitExec()
1645 .addReg(InputReg) in lowerInitExec()
1674 LIS->removeInterval(InputReg); in lowerInitExec()
1675 LIS->createAndComputeVirtRegInterval(InputReg); in lowerInitExec()
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| H A D | SIISelLowering.cpp | 3494 SDValue InputReg; in passSpecialInputs() local
3497 InputReg = loadInputValue(DAG, ArgRC, ArgVT, DL, *IncomingArg); in passSpecialInputs()
3501 InputReg = getImplicitArgPtr(DAG, DL); in passSpecialInputs()
3506 InputReg = DAG.getConstant(*Id, DL, ArgVT); in passSpecialInputs()
3508 InputReg = DAG.getPOISON(ArgVT); in passSpecialInputs()
3513 InputReg = DAG.getPOISON(ArgVT); in passSpecialInputs()
3517 RegsToPass.emplace_back(OutgoingArg->getRegister(), InputReg); in passSpecialInputs()
3524 storeStackInputValue(DAG, DL, Chain, InputReg, SpecialArgOffset); in passSpecialInputs()
3550 SDValue InputReg; in passSpecialInputs() local
3561 InputReg = loadInputValue(DAG, ArgRC, MVT::i32, DL, *IncomingArgX); in passSpecialInputs()
[all …]
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64MIPeepholeOpt.cpp | 778 Register InputReg = MI.getOperand(1).getReg(); in visitCopy() local
780 !MRI->hasOneNonDBGUse(InputReg)) in visitCopy()
783 MachineInstr *SrcMI = MRI->getUniqueVRegDef(InputReg); in visitCopy()
828 MRI->constrainRegClass(SrcReg, MRI->getRegClass(InputReg)); in visitCopy()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86FastISel.cpp | 2530 Register InputReg = getRegForValue(I->getOperand(0)); in X86SelectTrunc() local
2531 if (!InputReg) in X86SelectTrunc()
2537 updateValueMap(I, InputReg); in X86SelectTrunc()
2542 Register ResultReg = fastEmitInst_extractsubreg(MVT::i8, InputReg, in X86SelectTrunc()
2631 Register InputReg = getRegForValue(Op); in fastLowerIntrinsicCall() local
2632 if (!InputReg) in fastLowerIntrinsicCall()
2657 InputReg = fastEmitInst_ri(Opc, RC, InputReg, 4); in fastLowerIntrinsicCall()
2664 .addReg(InputReg, RegState::Kill); in fastLowerIntrinsicCall()
2672 InputReg = fastEmit_r(MVT::i16, MVT::i32, ISD::ZERO_EXTEND, InputReg); in fastLowerIntrinsicCall()
2675 InputReg = fastEmit_r(MVT::i32, MVT::v4i32, ISD::SCALAR_TO_VECTOR, in fastLowerIntrinsicCall()
[all …]
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| /freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/ |
| H A D | TargetInstrInfo.h | 590 RegSubRegPairAndIdx &InputReg) const;
1459 RegSubRegPairAndIdx &InputReg) const { in getExtractSubregLikeInputs() argument
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| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | FastISel.cpp | 1458 Register InputReg = getRegForValue(I->getOperand(0)); in selectCast() local
1459 if (!InputReg) in selectCast()
1464 Opcode, InputReg); in selectCast()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/ARM/ |
| H A D | ARMBaseInstrInfo.h | 80 RegSubRegPairAndIdx &InputReg) const override;
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| H A D | ARMBaseInstrInfo.cpp | 5328 RegSubRegPairAndIdx &InputReg) const { in getExtractSubregLikeInputs()
5341 InputReg.Reg = MOReg.getReg(); in getExtractSubregLikeInputs()
5342 InputReg.SubReg = MOReg.getSubReg(); in getExtractSubregLikeInputs()
5343 InputReg.SubIdx = DefIdx == 0 ? ARM::ssub_0 : ARM::ssub_1; in getExtractSubregLikeInputs()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/SPIRV/ |
| H A D | SPIRVModuleAnalysis.cpp | 1200 Register InputReg = Input->getOperand(1).getReg(); in AddDotProductRequirements() local
1202 SPIRVType *TypeDef = MRI.getVRegDef(InputReg); in AddDotProductRequirements()
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| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/ |
| H A D | IRTranslator.cpp | 2155 Register InputReg = in translateConvergenceControlIntrinsic() local
2157 MIB.addUse(InputReg); in translateConvergenceControlIntrinsic()
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