Searched refs:Inp0 (Results 1 – 2 of 2) sorted by relevance
| /freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
| H A D | HexagonISelLoweringHVX.cpp | 3323 SDValue Inp0 = Op.getOperand(0); in LegalizeHvxResize() local
3324 MVT InpTy = ty(Inp0); in LegalizeHvxResize()
3338 SDValue W = appendUndef(Inp0, WInpTy, DAG); in LegalizeHvxResize()
3362 SDValue Inp0; // Optional first argument. in LowerHvxOperationWrapper() local
3364 Inp0 = Op.getOperand(0); in LowerHvxOperationWrapper()
3372 Subtarget.isHVXElementType(ty(Inp0))) { in LowerHvxOperationWrapper()
3377 if (shouldWidenToHvx(ty(Inp0), DAG)) { in LowerHvxOperationWrapper()
3407 if (ty(Op).getSizeInBits() != ty(Inp0).getSizeInBits()) { in LowerHvxOperationWrapper()
3428 SDValue Inp0; // Optional first argument. in ReplaceHvxNodeResults() local
3430 Inp0 in ReplaceHvxNodeResults()
[all...] |
| /freebsd/contrib/llvm-project/llvm/lib/Target/ARM/ |
| H A D | ARMISelLowering.cpp | 13397 SDValue Inp0 = in PerformVQDMULHCombine() local
13401 Inp0 = DAG.getNode(ARMISD::VECTOR_REG_CAST, DL, LegalVecVT, Inp0); in PerformVQDMULHCombine()
13403 SDValue VQDMULH = DAG.getNode(ARMISD::VQDMULH, DL, LegalVecVT, Inp0, Inp1); in PerformVQDMULHCombine()
13414 SDValue Inp0 = in PerformVQDMULHCombine() local
13420 SDValue VQDMULH = DAG.getNode(ARMISD::VQDMULH, DL, LegalVecVT, Inp0, Inp1); in PerformVQDMULHCombine()
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