Searched refs:Inp0 (Results 1 – 2 of 2) sorted by relevance
| /freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
| H A D | HexagonISelLoweringHVX.cpp | 3360 SDValue Inp0 = Op.getOperand(0); in LegalizeHvxResize() local
3361 MVT InpTy = ty(Inp0); in LegalizeHvxResize()
3375 SDValue W = appendUndef(Inp0, WInpTy, DAG); in LegalizeHvxResize()
3399 SDValue Inp0; // Optional first argument. in LowerHvxOperationWrapper() local
3401 Inp0 = Op.getOperand(0); in LowerHvxOperationWrapper()
3409 Subtarget.isHVXElementType(ty(Inp0))) { in LowerHvxOperationWrapper()
3414 if (shouldWidenToHvx(ty(Inp0), DAG)) { in LowerHvxOperationWrapper()
3444 if (ty(Op).getSizeInBits() != ty(Inp0).getSizeInBits()) { in LowerHvxOperationWrapper()
3465 SDValue Inp0; // Optional first argument. in ReplaceHvxNodeResults() local
3467 Inp0 = Op.getOperand(0); in ReplaceHvxNodeResults()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/ARM/ |
| H A D | ARMISelLowering.cpp | 13464 SDValue Inp0 = in PerformVQDMULHCombine() local
13468 Inp0 = DAG.getNode(ARMISD::VECTOR_REG_CAST, DL, LegalVecVT, Inp0); in PerformVQDMULHCombine()
13470 SDValue VQDMULH = DAG.getNode(ARMISD::VQDMULH, DL, LegalVecVT, Inp0, Inp1); in PerformVQDMULHCombine()
13481 SDValue Inp0 = in PerformVQDMULHCombine() local
13487 SDValue VQDMULH = DAG.getNode(ARMISD::VQDMULH, DL, LegalVecVT, Inp0, Inp1); in PerformVQDMULHCombine()
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