| /freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64ISelLowering.cpp | 1394 for (MVT InnerVT : MVT::fixedlen_vector_valuetypes()) { in AArch64TargetLowering() local
1395 setTruncStoreAction(VT, InnerVT, Expand); in AArch64TargetLowering()
1396 setLoadExtAction(ISD::SEXTLOAD, VT, InnerVT, Expand); in AArch64TargetLowering()
1397 setLoadExtAction(ISD::ZEXTLOAD, VT, InnerVT, Expand); in AArch64TargetLowering()
1398 setLoadExtAction(ISD::EXTLOAD, VT, InnerVT, Expand); in AArch64TargetLowering()
1479 for (MVT InnerVT : MVT::fixedlen_vector_valuetypes()) { in AArch64TargetLowering() local
1480 setTruncStoreAction(VT, InnerVT, Expand); in AArch64TargetLowering()
1481 setLoadExtAction(ISD::SEXTLOAD, VT, InnerVT, Expand); in AArch64TargetLowering()
1482 setLoadExtAction(ISD::ZEXTLOAD, VT, InnerVT, Expand); in AArch64TargetLowering()
1483 setLoadExtAction(ISD::EXTLOAD, VT, InnerVT, Expand); in AArch64TargetLowering()
[all …]
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| /freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/ |
| H A D | RISCVISelLowering.cpp | 1408 for (MVT InnerVT : MVT::fp_fixedlen_vector_valuetypes()) { in RISCVTargetLowering() local
1409 setLoadExtAction(ISD::EXTLOAD, VT, InnerVT, Expand); in RISCVTargetLowering()
1410 setTruncStoreAction(VT, InnerVT, Expand); in RISCVTargetLowering()
5157 MVT InnerVT = ContainerVT; in lowerVZIP() local
5158 auto [Mask, VL] = getDefaultVLOps(IntVT, InnerVT, DL, DAG, Subtarget); in lowerVZIP()
5162 InnerVT = ContainerVT.getHalfNumVectorElementsVT(); in lowerVZIP()
5165 Mask = getAllOnesMask(InnerVT, VL, DL, DAG); in lowerVZIP()
5166 unsigned HighIdx = InnerVT.getVectorElementCount().getKnownMinValue(); in lowerVZIP()
5167 Op1 = DAG.getExtractSubvector(DL, InnerVT, Op0, HighIdx); in lowerVZIP()
5168 Op0 = DAG.getExtractSubvector(DL, InnerVT, Op0, 0); in lowerVZIP()
[all …]
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| /freebsd/contrib/llvm-project/llvm/lib/Target/LoongArch/ |
| H A D | LoongArchISelLowering.cpp | 270 for (MVT InnerVT : MVT::fixedlen_vector_valuetypes()) { in LoongArchTargetLowering() local
271 setTruncStoreAction(VT, InnerVT, Expand); in LoongArchTargetLowering()
272 setLoadExtAction(ISD::SEXTLOAD, VT, InnerVT, Expand); in LoongArchTargetLowering()
273 setLoadExtAction(ISD::ZEXTLOAD, VT, InnerVT, Expand); in LoongArchTargetLowering()
274 setLoadExtAction(ISD::EXTLOAD, VT, InnerVT, Expand); in LoongArchTargetLowering()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/SystemZ/ |
| H A D | SystemZISelLowering.cpp | 418 for (MVT InnerVT : MVT::fixedlen_vector_valuetypes()) { in SystemZTargetLowering() local
419 setTruncStoreAction(VT, InnerVT, Expand); in SystemZTargetLowering()
420 setLoadExtAction(ISD::SEXTLOAD, VT, InnerVT, Expand); in SystemZTargetLowering()
421 setLoadExtAction(ISD::ZEXTLOAD, VT, InnerVT, Expand); in SystemZTargetLowering()
422 setLoadExtAction(ISD::EXTLOAD, VT, InnerVT, Expand); in SystemZTargetLowering()
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| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | TargetLowering.cpp | 1817 EVT InnerVT = InnerOp.getValueType(); in SimplifyDemandedBits() local
1818 unsigned InnerBits = InnerVT.getScalarSizeInBits(); in SimplifyDemandedBits()
1820 isTypeDesirableForOp(ISD::SHL, InnerVT)) { in SimplifyDemandedBits()
1822 ISD::SHL, dl, InnerVT, InnerOp, in SimplifyDemandedBits()
1823 TLO.DAG.getShiftAmountConstant(ShAmt, InnerVT, dl)); in SimplifyDemandedBits()
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| H A D | DAGCombiner.cpp | 10407 EVT InnerVT = N0Op0.getValueType(); in visitSHL() local
10408 uint64_t InnerBitwidth = InnerVT.getScalarSizeInBits(); in visitSHL()
27175 EVT InnerVT = BC0->getValueType(0); in visitVECTOR_SHUFFLE() local
27176 EVT InnerSVT = InnerVT.getScalarType(); in visitVECTOR_SHUFFLE()
27179 EVT ScaleVT = SVT.bitsLT(InnerSVT) ? VT : InnerVT; in visitVECTOR_SHUFFLE()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86ISelLowering.cpp | 1028 for (MVT InnerVT : MVT::fixedlen_vector_valuetypes()) { in X86TargetLowering() local
1029 setTruncStoreAction(InnerVT, VT, Expand); in X86TargetLowering()
1031 setLoadExtAction(ISD::SEXTLOAD, InnerVT, VT, Expand); in X86TargetLowering()
1032 setLoadExtAction(ISD::ZEXTLOAD, InnerVT, VT, Expand); in X86TargetLowering()
1039 setLoadExtAction(ISD::EXTLOAD, InnerVT, VT, Expand); in X86TargetLowering()
1045 setLoadExtAction(ISD::EXTLOAD, InnerVT, VT, Expand); in X86TargetLowering()
23282 EVT InnerVT = Inner.getValueType(); in MatchVectorAllEqualTest() local
23283 if (llvm::has_single_bit<uint32_t>(InnerVT.getSizeInBits())) { in MatchVectorAllEqualTest()
23284 unsigned BW = InnerVT.getScalarSizeInBits(); in MatchVectorAllEqualTest()
23288 DAG.getConstant(Cmp, DL, InnerVT), CC, in MatchVectorAllEqualTest()
[all …]
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| /freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/ |
| H A D | PPCISelLowering.cpp | 895 for (MVT InnerVT : MVT::fixedlen_vector_valuetypes()) { in PPCTargetLowering() local
896 setTruncStoreAction(VT, InnerVT, Expand); in PPCTargetLowering()
897 setLoadExtAction(ISD::SEXTLOAD, VT, InnerVT, Expand); in PPCTargetLowering()
898 setLoadExtAction(ISD::ZEXTLOAD, VT, InnerVT, Expand); in PPCTargetLowering()
899 setLoadExtAction(ISD::EXTLOAD, VT, InnerVT, Expand); in PPCTargetLowering()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/ARM/ |
| H A D | ARMISelLowering.cpp | 799 for (MVT InnerVT : MVT::fixedlen_vector_valuetypes()) { in ARMTargetLowering() local
800 setTruncStoreAction(VT, InnerVT, Expand); in ARMTargetLowering()
801 addAllExtLoads(VT, InnerVT, Expand); in ARMTargetLowering()
|