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Searched refs:InVT (Results 1 – 19 of 19) sorted by relevance

/freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DLegalizeVectorTypes.cpp1485 EVT InVT = InOp.getValueType(); in SplitVecRes_BITCAST()
1488 switch (getTypeAction(InVT)) { in SplitVecRes_BITCAST()
1776 EVT InVT = Op.getValueType(); in SplitVecRes_StrictFPOp()
1777 if (InVT.isVector()) { in SplitVecRes_StrictFPOp()
1780 if (getTypeAction(InVT) == TargetLowering::TypeSplitVector) in SplitVecRes_StrictFPOp()
2470 EVT InVT = N->getOperand(0).getValueType(); in SplitVecRes_UnaryOp()
2471 if (getTypeAction(InVT) == TargetLowering::TypeSplitVector) in SplitVecRes_UnaryOp()
2510 EVT InVT = N->getOperand(0).getValueType(); in SplitVecRes_ADDRSPACECAST()
2511 if (getTypeAction(InVT) == TargetLowering::TypeSplitVector) in SplitVecRes_ADDRSPACECAST()
2531 EVT InVT in SplitVecRes_FFREXP()
1481 EVT InVT = InOp.getValueType(); SplitVecRes_BITCAST() local
1772 EVT InVT = Op.getValueType(); SplitVecRes_StrictFPOp() local
2466 EVT InVT = N->getOperand(0).getValueType(); SplitVecRes_UnaryOp() local
2506 EVT InVT = N->getOperand(0).getValueType(); SplitVecRes_ADDRSPACECAST() local
2527 EVT InVT = N->getOperand(0).getValueType(); SplitVecRes_FFREXP() local
3392 EVT InVT = Lo.getValueType(); SplitVecOp_UnaryOp() local
4015 EVT InVT = InVec->getValueType(0); SplitVecOp_TruncateHelper() local
4157 EVT InVT = Lo.getValueType(); SplitVecOp_FP_ROUND() local
4238 EVT InVT = Lo.getValueType(); SplitVecOp_FP_TO_XINT_SAT() local
5023 EVT InVT = InOp.getValueType(); WidenVecRes_Convert() local
5176 EVT InVT = InOp.getValueType(); WidenVecRes_Convert_StrictFP() local
5212 EVT InVT = InOp.getValueType(); WidenVecRes_EXTEND_VECTOR_INREG() local
5339 EVT InVT = InOp.getValueType(); WidenVecRes_BITCAST() local
5474 EVT InVT = N->getOperand(0).getValueType(); WidenVecRes_CONCAT_VECTORS() local
5573 EVT InVT = InOp.getValueType(); WidenVecRes_EXTRACT_SUBVECTOR() local
6263 EVT InVT = InOp1.getValueType(); WidenVecRes_SETCC() local
6511 EVT InVT = InOp.getValueType(); WidenVecOp_EXTEND() local
6626 EVT InVT = InOp.getValueType(); WidenVecOp_Convert() local
6750 EVT InVT = N->getOperand(0).getValueType(); WidenVecOp_CONCAT_VECTORS() local
7720 EVT InVT = InOp.getValueType(); ModifyToType() local
[all...]
H A DLegalizeTypesGeneric.cpp44 EVT InVT = InOp.getValueType(); in ExpandRes_BITCAST() local
48 switch (getTypeAction(InVT)) { in ExpandRes_BITCAST()
66 if (TLI.hasBigEndianPartOrdering(InVT, DL) != in ExpandRes_BITCAST()
89 assert(!(InVT.getVectorNumElements() & 1) && "Unsupported BITCAST"); in ExpandRes_BITCAST()
92 std::tie(LoVT, HiVT) = DAG.GetSplitDestVTs(InVT); in ExpandRes_BITCAST()
102 if (InVT.isVector() && OutVT.isInteger()) { in ExpandRes_BITCAST()
162 Align InAlign = DAG.getReducedAlign(InVT, /*UseABI=*/false); in ExpandRes_BITCAST()
165 SDValue StackPtr = DAG.CreateStackTemporary(InVT.getStoreSize(), Align); in ExpandRes_BITCAST()
H A DLegalizeIntegerTypes.cpp464 EVT InVT = InOp.getValueType(); in PromoteIntRes_BITCAST() local
465 EVT NInVT = TLI.getTypeToTransformTo(*DAG.getContext(), InVT); in PromoteIntRes_BITCAST()
470 switch (getTypeAction(InVT)) { in PromoteIntRes_BITCAST()
532 unsigned ShiftAmt = NInVT.getSizeInBits() - InVT.getSizeInBits(); in PromoteIntRes_BITCAST()
1336 EVT InVT = N->getOperand(OpNo).getValueType(); in PromoteIntRes_SETCC() local
1339 EVT SVT = getSetCCResultType(InVT); in PromoteIntRes_SETCC()
1345 if (getTypeAction(InVT) == TargetLowering::TypePromoteInteger) { in PromoteIntRes_SETCC()
1346 InVT = TLI.getTypeToTransformTo(*DAG.getContext(), InVT); in PromoteIntRes_SETCC()
1347 SVT = getSetCCResultType(InVT); in PromoteIntRes_SETCC()
1647 EVT InVT = InOp.getValueType(); in PromoteIntRes_TRUNCATE() local
[all …]
H A DDAGCombiner.cpp23400 EVT InVT = Vec.getValueType(); in reduceBuildVecToShuffle() local
23412 if (InVT.isSimple() && NearestPow2 > 2 && MaxIndex < NearestPow2 && in reduceBuildVecToShuffle()
23416 InVT.getVectorElementType(), SplitSize); in reduceBuildVecToShuffle()
23419 InVT.getVectorNumElements()) { in reduceBuildVecToShuffle()
23603 EVT InVT = EVT::getVectorVT(*DAG.getContext(), InSVT, NumElems); in convertBuildVecZextToZext() local
23606 if (LegalTypes && !TLI.isTypeLegal(InVT)) in convertBuildVecZextToZext()
23616 In = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, InVT, In, in convertBuildVecZextToZext()
24905 EVT InVT = V.getValueType(); in visitEXTRACT_SUBVECTOR() local
24907 unsigned EltSize = InVT.getScalarSizeInBits(); in visitEXTRACT_SUBVECTOR()
24911 EVT EltVT = InVT.getVectorElementType(); in visitEXTRACT_SUBVECTOR()
[all …]
H A DSelectionDAG.cpp3807 EVT InVT = Op.getOperand(0).getValueType(); in computeKnownBits() local
3808 APInt InDemandedElts = DemandedElts.zext(InVT.getVectorNumElements()); in computeKnownBits()
3821 EVT InVT = Op.getOperand(0).getValueType(); in computeKnownBits() local
3822 APInt InDemandedElts = DemandedElts.zext(InVT.getVectorNumElements()); in computeKnownBits()
3839 EVT InVT = Op.getOperand(0).getValueType(); in computeKnownBits() local
3840 APInt InDemandedElts = DemandedElts.zext(InVT.getVectorNumElements()); in computeKnownBits()
H A DSelectionDAGBuilder.cpp12458 EVT InVT = getValue(I.getOperand(0)).getValueType(); in visitVectorInterleave() local
12467 unsigned NumElts = InVT.getVectorMinNumElements(); in visitVectorInterleave()
12475 DAG.getVTList(InVT, InVT), InVec0, InVec1); in visitVectorInterleave()
H A DLegalizeDAG.cpp2240 EVT InVT = Node->getOperand(Node->isStrictFPOpcode() ? 1 : 0).getValueType(); in ExpandArgFPLibCall() local
2241 RTLIB::Libcall LC = RTLIB::getFPLibCall(InVT.getSimpleVT(), in ExpandArgFPLibCall()
/freebsd/contrib/llvm-project/llvm/lib/Target/WebAssembly/
H A DWebAssemblyISelLowering.cpp2511 EVT InVT = N->getOperand(0)->getValueType(0); in performVectorExtendToFPCombine() local
2514 if (ResVT == MVT::v4f32 && (InVT == MVT::v4i16 || InVT == MVT::v4i8)) in performVectorExtendToFPCombine()
2516 else if (ResVT == MVT::v2f64 && (InVT == MVT::v2i16 || InVT == MVT::v2i8)) in performVectorExtendToFPCombine()
2745 EVT InVT = MVT::i16, OutVT = MVT::i8; in truncateVectorWithNARROW() local
2747 InVT = MVT::i32; in truncateVectorWithNARROW()
2751 InVT = EVT::getVectorVT(Ctx, InVT, SubSizeInBits / InVT.getSizeInBits()); in truncateVectorWithNARROW()
2760 Lo = DAG.getBitcast(InVT, Lo); in truncateVectorWithNARROW()
2761 Hi = DAG.getBitcast(InVT, Hi); in truncateVectorWithNARROW()
2781 EVT InVT = In.getValueType(); in performTruncateCombine() local
2782 if (!InVT.isSimple()) in performTruncateCombine()
[all …]
/freebsd/contrib/llvm-project/llvm/utils/TableGen/Common/
H A DCodeGenDAGPatterns.h264 bool MergeInTypeInfo(TypeSetByHwMode &Out, MVT::SimpleValueType InVT) const { in MergeInTypeInfo()
265 return MergeInTypeInfo(Out, TypeSetByHwMode(InVT)); in MergeInTypeInfo()
267 bool MergeInTypeInfo(TypeSetByHwMode &Out, ValueTypeByHwMode InVT) const { in MergeInTypeInfo()
268 return MergeInTypeInfo(Out, TypeSetByHwMode(InVT)); in MergeInTypeInfo()
/freebsd/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86ISelLowering.cpp4515 EVT InVT = In.getValueType(); in getEXTEND_VECTOR_INREG() local
4516 assert(VT.isVector() && InVT.isVector() && "Expected vector VTs."); in getEXTEND_VECTOR_INREG()
4523 if (InVT.getSizeInBits() > 128) { in getEXTEND_VECTOR_INREG()
4524 assert(VT.getSizeInBits() == InVT.getSizeInBits() && in getEXTEND_VECTOR_INREG()
4526 unsigned Scale = VT.getScalarSizeInBits() / InVT.getScalarSizeInBits(); in getEXTEND_VECTOR_INREG()
4529 InVT = In.getValueType(); in getEXTEND_VECTOR_INREG()
4532 if (VT.getVectorNumElements() != InVT.getVectorNumElements()) in getEXTEND_VECTOR_INREG()
20154 MVT InVT = In.getSimpleValueType(); in LowerAVXExtend() local
20157 assert(VT.isVector() && InVT.isVector() && "Expected vector type"); in LowerAVXExtend()
20160 assert(VT.getVectorNumElements() == InVT.getVectorNumElements() && in LowerAVXExtend()
[all …]
H A DX86InstrAVX512.td162 X86VectorVTInfo InVT,
167 !con((ins InVT.RC:$src1), NonTiedIns),
168 !con((ins InVT.RC:$src1, InVT.KRCWM:$mask), NonTiedIns),
169 !con((ins InVT.RC:$src1, InVT.KRCWM:$mask), NonTiedIns),
171 (vselect_mask InVT.KRCWM:$mask, RHS,
172 (bitconvert InVT.RC:$src1)),
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64ISelLowering.cpp4372 EVT InVT = Op.getOperand(IsStrict ? 1 : 0).getValueType(); in LowerVectorFP_TO_INT() local
4383 useSVEForFixedLengthVectorVT(InVT, !Subtarget->isNeonAvailable())) in LowerVectorFP_TO_INT()
4386 unsigned NumElts = InVT.getVectorNumElements(); in LowerVectorFP_TO_INT()
4389 if ((InVT.getVectorElementType() == MVT::f16 && !Subtarget->hasFullFP16()) || in LowerVectorFP_TO_INT()
4390 InVT.getVectorElementType() == MVT::bf16) { in LowerVectorFP_TO_INT()
4405 uint64_t InVTSize = InVT.getFixedSizeInBits(); in LowerVectorFP_TO_INT()
4409 InVT = InVT.changeVectorElementTypeToInteger(); in LowerVectorFP_TO_INT()
4410 SDValue Cv = DAG.getNode(Op.getOpcode(), dl, {InVT, MVT::Other}, in LowerVectorFP_TO_INT()
4416 DAG.getNode(Op.getOpcode(), dl, InVT.changeVectorElementTypeToInteger(), in LowerVectorFP_TO_INT()
4441 ISD::EXTRACT_VECTOR_ELT, dl, InVT.getScalarType(), in LowerVectorFP_TO_INT()
[all …]
H A DAArch64ISelDAGToDAG.cpp4429 EVT InVT = N->getOperand(1).getValueType(); in trySelectCastFixedLengthToScalableVector() local
4430 if (VT.isFixedLengthVector() || InVT.isScalableVector()) in trySelectCastFixedLengthToScalableVector()
4432 if (InVT.getSizeInBits() <= 128) in trySelectCastFixedLengthToScalableVector()
4458 EVT InVT = N->getOperand(0).getValueType(); in trySelectCastScalableToFixedLengthVector() local
4459 if (VT.isScalableVector() || InVT.isFixedLengthVector()) in trySelectCastScalableToFixedLengthVector()
4468 assert(InVT.getSizeInBits().getKnownMinValue() == AArch64::SVEBitsPerBlock && in trySelectCastScalableToFixedLengthVector()
H A DSVEInstrFormats.td2790 ValueType OutVT, ValueType InVT,
2793 …def : SVE_4_Op_Imm_Pat<OutVT, op, OutVT, InVT, InVT, i32, VectorIndexH32b_timm, !cast<Instruction>…
2827 ValueType InVT, SDPatternOperator op> {
2829 def : SVE_3_Op_Pat<OutVT, op, OutVT, InVT, InVT, !cast<Instruction>(NAME)>;
8707 string asm, ValueType InVT, SDPatternOperator op> {
8709 def : SVE_3_Op_Pat<nxv4f32, op, nxv4f32, InVT, InVT, !cast<Instruction>(NAME)>;
8734 ZPRRegOp src2_ty, string asm, ValueType InVT,
8741 …def : SVE_4_Op_Imm_Pat<nxv4f32, op, nxv4f32, InVT, InVT, i32, VectorIndexS32b_timm, !cast<Instruct…
/freebsd/contrib/llvm-project/llvm/lib/Target/SystemZ/
H A DSystemZISelLowering.cpp3833 EVT InVT = In.getValueType(); in lowerBITCAST() local
3848 if (InVT == MVT::i32 && ResVT == MVT::f32) { in lowerBITCAST()
3864 if (InVT == MVT::f32 && ResVT == MVT::i32) { in lowerBITCAST()
5170 MVT InVT = MVT::getVectorVT(MVT::getIntegerVT(InBytes * 8), in getPermuteNode() local
5172 Op0 = DAG.getNode(ISD::BITCAST, DL, InVT, Op0); in getPermuteNode()
5173 Op1 = DAG.getNode(ISD::BITCAST, DL, InVT, Op1); in getPermuteNode()
5177 Op = DAG.getNode(SystemZISD::PERMUTE_DWORDS, DL, InVT, Op0, Op1, Op2); in getPermuteNode()
5183 Op = DAG.getNode(P.Opcode, DL, InVT, Op0, Op1); in getPermuteNode()
5555 EVT InVT = MVT::getVectorVT(MVT::getIntegerVT(InBits), in insertUnpackIfPrepared() local
5557 SDValue PackedOp = DAG.getNode(ISD::BITCAST, DL, InVT, Op); in insertUnpackIfPrepared()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCISelDAGToDAG.cpp3099 EVT InVT = InputOp.getValueType(); in computeLogicOpInGPR() local
3100 return SDValue(CurDAG->getMachineNode(InVT == MVT::i32 ? PPC::RLDICL_32 : in computeLogicOpInGPR()
3101 PPC::RLDICL, dl, InVT, InputOp, in computeLogicOpInGPR()
3244 EVT InVT = LHS.getValueType(); in getCompoundZeroComparisonInGPR() local
3245 bool Is32Bit = InVT == MVT::i32; in getCompoundZeroComparisonInGPR()
3253 dl, InVT, LHS, LHS), 0); in getCompoundZeroComparisonInGPR()
5807 EVT InVT = N->getOperand(0).getValueType(); in Select() local
5808 assert((InVT == MVT::i64 || InVT == MVT::i32) && in Select()
5811 unsigned Opcode = (InVT == MVT::i64) ? PPC::ANDI8_rec : PPC::ANDI_rec; in Select()
5812 SDValue AndI(CurDAG->getMachineNode(Opcode, dl, InVT, MVT::Glue, in Select()
[all …]
H A DPPCISelLowering.cpp8783 EVT InVT = Src.getValueType(); in LowerINT_TO_FP() local
8786 isOperationCustom(Op.getOpcode(), InVT)) in LowerINT_TO_FP()
/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVISelDAGToDAG.cpp2237 MVT InVT = V.getSimpleValueType(); in Select() local
2247 if (InVT.isFixedLengthVector()) in Select()
2248 InVT = TLI.getContainerForFixedLengthVector(InVT); in Select()
2254 InVT, SubVecContainerVT, Idx, TRI); in Select()
2265 unsigned InRegClassID = RISCVTargetLowering::getRegClassIDForVecVT(InVT); in Select()
H A DRISCVISelLowering.cpp10990 MVT InVT = Op.getOperand(0).getSimpleValueType(); in lowerFixedLengthVectorSetccToRVV()
10991 MVT ContainerVT = getContainerForFixedLengthVector(InVT); in lowerFixedLengthVectorSetccToRVV()
11022 MVT InVT = Op1.getSimpleValueType(); in lowerVectorStrictFSetcc()
11054 MVT ContainerInVT = InVT; in lowerVectorStrictFSetcc()
11055 if (InVT.isFixedLengthVector()) { in lowerVectorStrictFSetcc()
11056 ContainerInVT = getContainerForFixedLengthVector(InVT); in lowerVectorStrictFSetcc()
11062 auto [Mask, VL] = getDefaultVLOps(InVT, ContainerInVT, DL, DAG, Subtarget); in lowerVectorStrictFSetcc()
10988 MVT InVT = Op.getOperand(0).getSimpleValueType(); lowerFixedLengthVectorSetccToRVV() local
11020 MVT InVT = Op1.getSimpleValueType(); lowerVectorStrictFSetcc() local