xref: /freebsd/contrib/llvm-project/llvm/lib/TargetParser/X86TargetParser.cpp (revision c80e69b00d976a5a3b3e84527f270fa7e72a8205) 
1 //===-- X86TargetParser - Parser for X86 features ---------------*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file implements a target parser to recognise X86 hardware features.
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #include "llvm/TargetParser/X86TargetParser.h"
14 #include "llvm/ADT/Bitset.h"
15 #include "llvm/ADT/StringSwitch.h"
16 #include <numeric>
17 
18 using namespace llvm;
19 using namespace llvm::X86;
20 
21 namespace {
22 
23 using FeatureBitset = Bitset<X86::CPU_FEATURE_MAX>;
24 
25 struct ProcInfo {
26   StringLiteral Name;
27   X86::CPUKind Kind;
28   unsigned KeyFeature;
29   FeatureBitset Features;
30   char Mangling;
31   bool OnlyForCPUDispatchSpecific;
32 };
33 
34 struct FeatureInfo {
35   StringLiteral NameWithPlus;
36   FeatureBitset ImpliedFeatures;
37 
getName__anon54b81fad0111::FeatureInfo38   StringRef getName(bool WithPlus = false) const {
39     assert(NameWithPlus[0] == '+' && "Expected string to start with '+'");
40     if (WithPlus)
41       return NameWithPlus;
42     return NameWithPlus.drop_front();
43   }
44 };
45 
46 } // end anonymous namespace
47 
48 #define X86_FEATURE(ENUM, STRING)                                              \
49   constexpr FeatureBitset Feature##ENUM = {X86::FEATURE_##ENUM};
50 #include "llvm/TargetParser/X86TargetParser.def"
51 
52 // Pentium with MMX.
53 constexpr FeatureBitset FeaturesPentiumMMX =
54     FeatureX87 | FeatureCMPXCHG8B | FeatureMMX;
55 
56 // Pentium 2 and 3.
57 constexpr FeatureBitset FeaturesPentium2 =
58     FeatureX87 | FeatureCMPXCHG8B | FeatureMMX | FeatureFXSR | FeatureCMOV;
59 constexpr FeatureBitset FeaturesPentium3 = FeaturesPentium2 | FeatureSSE;
60 
61 // Pentium 4 CPUs
62 constexpr FeatureBitset FeaturesPentium4 = FeaturesPentium3 | FeatureSSE2;
63 constexpr FeatureBitset FeaturesPrescott = FeaturesPentium4 | FeatureSSE3;
64 constexpr FeatureBitset FeaturesNocona =
65     FeaturesPrescott | Feature64BIT | FeatureCMPXCHG16B;
66 
67 // Basic 64-bit capable CPU.
68 constexpr FeatureBitset FeaturesX86_64 = FeaturesPentium4 | Feature64BIT;
69 constexpr FeatureBitset FeaturesX86_64_V2 = FeaturesX86_64 | FeatureSAHF |
70                                             FeaturePOPCNT | FeatureCRC32 |
71                                             FeatureSSE4_2 | FeatureCMPXCHG16B;
72 constexpr FeatureBitset FeaturesX86_64_V3 =
73     FeaturesX86_64_V2 | FeatureAVX2 | FeatureBMI | FeatureBMI2 | FeatureF16C |
74     FeatureFMA | FeatureLZCNT | FeatureMOVBE | FeatureXSAVE;
75 constexpr FeatureBitset FeaturesX86_64_V4 = FeaturesX86_64_V3 | FeatureEVEX512 |
76                                             FeatureAVX512BW | FeatureAVX512CD |
77                                             FeatureAVX512DQ | FeatureAVX512VL;
78 
79 // Intel Core CPUs
80 constexpr FeatureBitset FeaturesCore2 =
81     FeaturesNocona | FeatureSAHF | FeatureSSSE3;
82 constexpr FeatureBitset FeaturesPenryn = FeaturesCore2 | FeatureSSE4_1;
83 constexpr FeatureBitset FeaturesNehalem =
84     FeaturesPenryn | FeaturePOPCNT | FeatureCRC32 | FeatureSSE4_2;
85 constexpr FeatureBitset FeaturesWestmere = FeaturesNehalem | FeaturePCLMUL;
86 constexpr FeatureBitset FeaturesSandyBridge =
87     FeaturesWestmere | FeatureAVX | FeatureXSAVE | FeatureXSAVEOPT;
88 constexpr FeatureBitset FeaturesIvyBridge =
89     FeaturesSandyBridge | FeatureF16C | FeatureFSGSBASE | FeatureRDRND;
90 constexpr FeatureBitset FeaturesHaswell =
91     FeaturesIvyBridge | FeatureAVX2 | FeatureBMI | FeatureBMI2 | FeatureFMA |
92     FeatureINVPCID | FeatureLZCNT | FeatureMOVBE;
93 constexpr FeatureBitset FeaturesBroadwell =
94     FeaturesHaswell | FeatureADX | FeaturePRFCHW | FeatureRDSEED;
95 
96 // Intel Knights Landing and Knights Mill
97 // Knights Landing has feature parity with Broadwell.
98 constexpr FeatureBitset FeaturesKNL = FeaturesBroadwell | FeatureAES |
99                                       FeatureAVX512F | FeatureEVEX512 |
100                                       FeatureAVX512CD;
101 constexpr FeatureBitset FeaturesKNM = FeaturesKNL | FeatureAVX512VPOPCNTDQ;
102 
103 // Intel Skylake processors.
104 constexpr FeatureBitset FeaturesSkylakeClient =
105     FeaturesBroadwell | FeatureAES | FeatureCLFLUSHOPT | FeatureXSAVEC |
106     FeatureXSAVES | FeatureSGX;
107 // SkylakeServer inherits all SkylakeClient features except SGX.
108 // FIXME: That doesn't match gcc.
109 constexpr FeatureBitset FeaturesSkylakeServer =
110     (FeaturesSkylakeClient & ~FeatureSGX) | FeatureAVX512F | FeatureEVEX512 |
111     FeatureAVX512CD | FeatureAVX512DQ | FeatureAVX512BW | FeatureAVX512VL |
112     FeatureCLWB | FeaturePKU;
113 constexpr FeatureBitset FeaturesCascadeLake =
114     FeaturesSkylakeServer | FeatureAVX512VNNI;
115 constexpr FeatureBitset FeaturesCooperLake =
116     FeaturesCascadeLake | FeatureAVX512BF16;
117 
118 // Intel 10nm processors.
119 constexpr FeatureBitset FeaturesCannonlake =
120     FeaturesSkylakeClient | FeatureAVX512F | FeatureEVEX512 | FeatureAVX512CD |
121     FeatureAVX512DQ | FeatureAVX512BW | FeatureAVX512VL | FeatureAVX512IFMA |
122     FeatureAVX512VBMI | FeaturePKU | FeatureSHA;
123 constexpr FeatureBitset FeaturesICLClient =
124     FeaturesCannonlake | FeatureAVX512BITALG | FeatureAVX512VBMI2 |
125     FeatureAVX512VNNI | FeatureAVX512VPOPCNTDQ | FeatureGFNI | FeatureRDPID |
126     FeatureVAES | FeatureVPCLMULQDQ;
127 constexpr FeatureBitset FeaturesRocketlake = FeaturesICLClient & ~FeatureSGX;
128 constexpr FeatureBitset FeaturesICLServer =
129     FeaturesICLClient | FeatureCLWB | FeaturePCONFIG | FeatureWBNOINVD;
130 constexpr FeatureBitset FeaturesTigerlake =
131     FeaturesICLClient | FeatureAVX512VP2INTERSECT | FeatureMOVDIR64B |
132     FeatureCLWB | FeatureMOVDIRI | FeatureSHSTK | FeatureKL | FeatureWIDEKL;
133 constexpr FeatureBitset FeaturesSapphireRapids =
134     FeaturesICLServer | FeatureAMX_BF16 | FeatureAMX_INT8 | FeatureAMX_TILE |
135     FeatureAVX512BF16 | FeatureAVX512FP16 | FeatureAVXVNNI | FeatureCLDEMOTE |
136     FeatureENQCMD | FeatureMOVDIR64B | FeatureMOVDIRI | FeaturePTWRITE |
137     FeatureSERIALIZE | FeatureSHSTK | FeatureTSXLDTRK | FeatureUINTR |
138     FeatureWAITPKG;
139 constexpr FeatureBitset FeaturesGraniteRapids =
140     FeaturesSapphireRapids | FeatureAMX_FP16 | FeaturePREFETCHI;
141 
142 // Intel Atom processors.
143 // Bonnell has feature parity with Core2 and adds MOVBE.
144 constexpr FeatureBitset FeaturesBonnell = FeaturesCore2 | FeatureMOVBE;
145 // Silvermont has parity with Westmere and Bonnell plus PRFCHW and RDRND.
146 constexpr FeatureBitset FeaturesSilvermont =
147     FeaturesBonnell | FeaturesWestmere | FeaturePRFCHW | FeatureRDRND;
148 constexpr FeatureBitset FeaturesGoldmont =
149     FeaturesSilvermont | FeatureAES | FeatureCLFLUSHOPT | FeatureFSGSBASE |
150     FeatureRDSEED | FeatureSHA | FeatureXSAVE | FeatureXSAVEC |
151     FeatureXSAVEOPT | FeatureXSAVES;
152 constexpr FeatureBitset FeaturesGoldmontPlus =
153     FeaturesGoldmont | FeaturePTWRITE | FeatureRDPID | FeatureSGX;
154 constexpr FeatureBitset FeaturesTremont =
155     FeaturesGoldmontPlus | FeatureCLWB | FeatureGFNI;
156 constexpr FeatureBitset FeaturesAlderlake =
157     FeaturesTremont | FeatureADX | FeatureBMI | FeatureBMI2 | FeatureF16C |
158     FeatureFMA | FeatureINVPCID | FeatureLZCNT | FeaturePCONFIG | FeaturePKU |
159     FeatureSERIALIZE | FeatureSHSTK | FeatureVAES | FeatureVPCLMULQDQ |
160     FeatureCLDEMOTE | FeatureMOVDIR64B | FeatureMOVDIRI | FeatureWAITPKG |
161     FeatureAVXVNNI | FeatureHRESET | FeatureWIDEKL;
162 constexpr FeatureBitset FeaturesSierraforest =
163     FeaturesAlderlake | FeatureCMPCCXADD | FeatureAVXIFMA | FeatureUINTR |
164     FeatureENQCMD | FeatureAVXNECONVERT | FeatureAVXVNNIINT8;
165 constexpr FeatureBitset FeaturesArrowlakeS = FeaturesSierraforest |
166     FeatureAVXVNNIINT16 | FeatureSHA512 | FeatureSM3 | FeatureSM4;
167 constexpr FeatureBitset FeaturesPantherlake =
168     FeaturesArrowlakeS | FeaturePREFETCHI;
169 constexpr FeatureBitset FeaturesClearwaterforest =
170     FeaturesArrowlakeS | FeatureUSERMSR | FeaturePREFETCHI;
171 
172 // Geode Processor.
173 constexpr FeatureBitset FeaturesGeode =
174     FeatureX87 | FeatureCMPXCHG8B | FeatureMMX | FeaturePRFCHW;
175 
176 // K6 processor.
177 constexpr FeatureBitset FeaturesK6 = FeatureX87 | FeatureCMPXCHG8B | FeatureMMX;
178 
179 // K7 and K8 architecture processors.
180 constexpr FeatureBitset FeaturesAthlon =
181     FeatureX87 | FeatureCMPXCHG8B | FeatureMMX | FeaturePRFCHW;
182 constexpr FeatureBitset FeaturesAthlonXP =
183     FeaturesAthlon | FeatureFXSR | FeatureSSE;
184 constexpr FeatureBitset FeaturesK8 =
185     FeaturesAthlonXP | FeatureSSE2 | Feature64BIT;
186 constexpr FeatureBitset FeaturesK8SSE3 = FeaturesK8 | FeatureSSE3;
187 constexpr FeatureBitset FeaturesAMDFAM10 =
188     FeaturesK8SSE3 | FeatureCMPXCHG16B | FeatureLZCNT | FeaturePOPCNT |
189     FeaturePRFCHW | FeatureSAHF | FeatureSSE4_A;
190 
191 // Bobcat architecture processors.
192 constexpr FeatureBitset FeaturesBTVER1 =
193     FeatureX87 | FeatureCMPXCHG8B | FeatureCMPXCHG16B | Feature64BIT |
194     FeatureFXSR | FeatureLZCNT | FeatureMMX | FeaturePOPCNT | FeaturePRFCHW |
195     FeatureSSE | FeatureSSE2 | FeatureSSE3 | FeatureSSSE3 | FeatureSSE4_A |
196     FeatureSAHF;
197 constexpr FeatureBitset FeaturesBTVER2 =
198     FeaturesBTVER1 | FeatureAES | FeatureAVX | FeatureBMI | FeatureCRC32 |
199     FeatureF16C | FeatureMOVBE | FeaturePCLMUL | FeatureXSAVE | FeatureXSAVEOPT;
200 
201 // AMD Bulldozer architecture processors.
202 constexpr FeatureBitset FeaturesBDVER1 =
203     FeatureX87 | FeatureAES | FeatureAVX | FeatureCMPXCHG8B |
204     FeatureCMPXCHG16B | FeatureCRC32 | Feature64BIT | FeatureFMA4 |
205     FeatureFXSR | FeatureLWP | FeatureLZCNT | FeatureMMX | FeaturePCLMUL |
206     FeaturePOPCNT | FeaturePRFCHW | FeatureSAHF | FeatureSSE | FeatureSSE2 |
207     FeatureSSE3 | FeatureSSSE3 | FeatureSSE4_1 | FeatureSSE4_2 | FeatureSSE4_A |
208     FeatureXOP | FeatureXSAVE;
209 constexpr FeatureBitset FeaturesBDVER2 =
210     FeaturesBDVER1 | FeatureBMI | FeatureFMA | FeatureF16C | FeatureTBM;
211 constexpr FeatureBitset FeaturesBDVER3 =
212     FeaturesBDVER2 | FeatureFSGSBASE | FeatureXSAVEOPT;
213 constexpr FeatureBitset FeaturesBDVER4 = FeaturesBDVER3 | FeatureAVX2 |
214                                          FeatureBMI2 | FeatureMOVBE |
215                                          FeatureMWAITX | FeatureRDRND;
216 
217 // AMD Zen architecture processors.
218 constexpr FeatureBitset FeaturesZNVER1 =
219     FeatureX87 | FeatureADX | FeatureAES | FeatureAVX | FeatureAVX2 |
220     FeatureBMI | FeatureBMI2 | FeatureCLFLUSHOPT | FeatureCLZERO |
221     FeatureCMPXCHG8B | FeatureCMPXCHG16B | FeatureCRC32 | Feature64BIT |
222     FeatureF16C | FeatureFMA | FeatureFSGSBASE | FeatureFXSR | FeatureLZCNT |
223     FeatureMMX | FeatureMOVBE | FeatureMWAITX | FeaturePCLMUL | FeaturePOPCNT |
224     FeaturePRFCHW | FeatureRDRND | FeatureRDSEED | FeatureSAHF | FeatureSHA |
225     FeatureSSE | FeatureSSE2 | FeatureSSE3 | FeatureSSSE3 | FeatureSSE4_1 |
226     FeatureSSE4_2 | FeatureSSE4_A | FeatureXSAVE | FeatureXSAVEC |
227     FeatureXSAVEOPT | FeatureXSAVES;
228 constexpr FeatureBitset FeaturesZNVER2 = FeaturesZNVER1 | FeatureCLWB |
229                                          FeatureRDPID | FeatureRDPRU |
230                                          FeatureWBNOINVD;
231 static constexpr FeatureBitset FeaturesZNVER3 = FeaturesZNVER2 |
232                                                 FeatureINVPCID | FeaturePKU |
233                                                 FeatureVAES | FeatureVPCLMULQDQ;
234 static constexpr FeatureBitset FeaturesZNVER4 =
235     FeaturesZNVER3 | FeatureAVX512F | FeatureEVEX512 | FeatureAVX512CD |
236     FeatureAVX512DQ | FeatureAVX512BW | FeatureAVX512VL | FeatureAVX512IFMA |
237     FeatureAVX512VBMI | FeatureAVX512VBMI2 | FeatureAVX512VNNI |
238     FeatureAVX512BITALG | FeatureAVX512VPOPCNTDQ | FeatureAVX512BF16 |
239     FeatureGFNI | FeatureSHSTK;
240 
241 static constexpr FeatureBitset FeaturesZNVER5 =
242     FeaturesZNVER4 | FeatureAVXVNNI | FeatureMOVDIRI | FeatureMOVDIR64B |
243     FeatureAVX512VP2INTERSECT | FeaturePREFETCHI | FeatureAVXVNNI;
244 
245 // D151696 tranplanted Mangling and OnlyForCPUDispatchSpecific from
246 // X86TargetParser.def to here. They are assigned by following ways:
247 // 1. Copy the mangling from the original CPU_SPEICIFC MACROs. If no, assign
248 // to '\0' by default, which means not support cpu_specific/dispatch feature.
249 // 2. set OnlyForCPUDispatchSpecific as true if this cpu name was not
250 // listed here before, which means it doesn't support -march, -mtune and so on.
251 // FIXME: Remove OnlyForCPUDispatchSpecific after all CPUs here support both
252 // cpu_dispatch/specific() feature and -march, -mtune, and so on.
253 // clang-format off
254 constexpr ProcInfo Processors[] = {
255  // Empty processor. Include X87 and CMPXCHG8 for backwards compatibility.
256   { {""}, CK_None, ~0U, FeatureX87 | FeatureCMPXCHG8B, '\0', false },
257   { {"generic"}, CK_None, ~0U, FeatureX87 | FeatureCMPXCHG8B | Feature64BIT, 'A', true },
258   // i386-generation processors.
259   { {"i386"}, CK_i386, ~0U, FeatureX87, '\0', false },
260   // i486-generation processors.
261   { {"i486"}, CK_i486, ~0U, FeatureX87, '\0', false },
262   { {"winchip-c6"}, CK_WinChipC6, ~0U, FeaturesPentiumMMX, '\0', false },
263   { {"winchip2"}, CK_WinChip2, ~0U, FeaturesPentiumMMX | FeaturePRFCHW, '\0', false },
264   { {"c3"}, CK_C3, ~0U, FeaturesPentiumMMX | FeaturePRFCHW, '\0', false },
265   // i586-generation processors, P5 microarchitecture based.
266   { {"i586"}, CK_i586, ~0U, FeatureX87 | FeatureCMPXCHG8B, '\0', false },
267   { {"pentium"}, CK_Pentium, ~0U, FeatureX87 | FeatureCMPXCHG8B, 'B', false },
268   { {"pentium-mmx"}, CK_PentiumMMX, ~0U, FeaturesPentiumMMX, '\0', false },
269   { {"pentium_mmx"}, CK_PentiumMMX, ~0U, FeaturesPentiumMMX, 'D', true },
270   // i686-generation processors, P6 / Pentium M microarchitecture based.
271   { {"pentiumpro"}, CK_PentiumPro, ~0U, FeatureCMOV | FeatureX87 | FeatureCMPXCHG8B, 'C', false },
272   { {"pentium_pro"}, CK_PentiumPro, ~0U, FeatureCMOV | FeatureX87 | FeatureCMPXCHG8B, 'C', true },
273   { {"i686"}, CK_i686, ~0U, FeatureCMOV | FeatureX87 | FeatureCMPXCHG8B, '\0', false },
274   { {"pentium2"}, CK_Pentium2, ~0U, FeaturesPentium2, 'E', false },
275   { {"pentium_ii"}, CK_Pentium2, ~0U, FeaturesPentium2, 'E', true },
276   { {"pentium3"}, CK_Pentium3, ~0U, FeaturesPentium3, 'H', false },
277   { {"pentium3m"}, CK_Pentium3, ~0U, FeaturesPentium3, 'H', false },
278   { {"pentium_iii"}, CK_Pentium3, ~0U, FeaturesPentium3, 'H', true },
279   { {"pentium_iii_no_xmm_regs"}, CK_Pentium3, ~0U, FeaturesPentium3, 'H', true },
280   { {"pentium-m"}, CK_PentiumM, ~0U, FeaturesPentium4, '\0', false },
281   { {"pentium_m"}, CK_PentiumM, ~0U, FeaturesPentium4, 'K', true },
282   { {"c3-2"}, CK_C3_2, ~0U, FeaturesPentium3, '\0', false },
283   { {"yonah"}, CK_Yonah, ~0U, FeaturesPrescott, 'L', false },
284   // Netburst microarchitecture based processors.
285   { {"pentium4"}, CK_Pentium4, ~0U, FeaturesPentium4, 'J', false },
286   { {"pentium4m"}, CK_Pentium4, ~0U, FeaturesPentium4, 'J', false },
287   { {"pentium_4"}, CK_Pentium4, ~0U, FeaturesPentium4, 'J', true },
288   { {"pentium_4_sse3"}, CK_Prescott, ~0U, FeaturesPrescott, 'L', true },
289   { {"prescott"}, CK_Prescott, ~0U, FeaturesPrescott, 'L', false },
290   { {"nocona"}, CK_Nocona, ~0U, FeaturesNocona, 'L', false },
291   // Core microarchitecture based processors.
292   { {"core2"}, CK_Core2, FEATURE_SSSE3, FeaturesCore2, 'M', false },
293   { {"core_2_duo_ssse3"}, CK_Core2, ~0U, FeaturesCore2, 'M', true },
294   { {"penryn"}, CK_Penryn, ~0U, FeaturesPenryn, 'N', false },
295   { {"core_2_duo_sse4_1"}, CK_Penryn, ~0U, FeaturesPenryn, 'N', true },
296   // Atom processors
297   { {"bonnell"}, CK_Bonnell, FEATURE_SSSE3, FeaturesBonnell, 'O', false },
298   { {"atom"}, CK_Bonnell, FEATURE_SSSE3, FeaturesBonnell, 'O', false },
299   { {"silvermont"}, CK_Silvermont, FEATURE_SSE4_2, FeaturesSilvermont, 'c', false },
300   { {"slm"}, CK_Silvermont, FEATURE_SSE4_2, FeaturesSilvermont, 'c', false },
301   { {"atom_sse4_2"}, CK_Nehalem, FEATURE_SSE4_2, FeaturesNehalem, 'c', true },
302   { {"atom_sse4_2_movbe"}, CK_Goldmont, FEATURE_SSE4_2, FeaturesGoldmont, 'd', true },
303   { {"goldmont"}, CK_Goldmont, FEATURE_SSE4_2, FeaturesGoldmont, 'i', false },
304   { {"goldmont-plus"}, CK_GoldmontPlus, FEATURE_SSE4_2, FeaturesGoldmontPlus, '\0', false },
305   { {"goldmont_plus"}, CK_GoldmontPlus, FEATURE_SSE4_2, FeaturesGoldmontPlus, 'd', true },
306   { {"tremont"}, CK_Tremont, FEATURE_SSE4_2, FeaturesTremont, 'd', false },
307   // Nehalem microarchitecture based processors.
308   { {"nehalem"}, CK_Nehalem, FEATURE_SSE4_2, FeaturesNehalem, 'P', false },
309   { {"core_i7_sse4_2"}, CK_Nehalem, FEATURE_SSE4_2, FeaturesNehalem, 'P', true },
310   { {"corei7"}, CK_Nehalem, FEATURE_SSE4_2, FeaturesNehalem, 'P', false },
311   // Westmere microarchitecture based processors.
312   { {"westmere"}, CK_Westmere, FEATURE_PCLMUL, FeaturesWestmere, 'Q', false },
313   { {"core_aes_pclmulqdq"}, CK_Nehalem, FEATURE_SSE4_2, FeaturesNehalem, 'Q', true },
314   // Sandy Bridge microarchitecture based processors.
315   { {"sandybridge"}, CK_SandyBridge, FEATURE_AVX, FeaturesSandyBridge, 'R', false },
316   { {"core_2nd_gen_avx"}, CK_SandyBridge, FEATURE_AVX, FeaturesSandyBridge, 'R', true },
317   { {"corei7-avx"}, CK_SandyBridge, FEATURE_AVX, FeaturesSandyBridge, '\0', false },
318   // Ivy Bridge microarchitecture based processors.
319   { {"ivybridge"}, CK_IvyBridge, FEATURE_AVX, FeaturesIvyBridge, 'S', false },
320   { {"core_3rd_gen_avx"}, CK_IvyBridge, FEATURE_AVX, FeaturesIvyBridge, 'S', true },
321   { {"core-avx-i"}, CK_IvyBridge, FEATURE_AVX, FeaturesIvyBridge, '\0', false },
322   // Haswell microarchitecture based processors.
323   { {"haswell"}, CK_Haswell, FEATURE_AVX2, FeaturesHaswell, 'V', false },
324   { {"core-avx2"}, CK_Haswell, FEATURE_AVX2, FeaturesHaswell, '\0', false },
325   { {"core_4th_gen_avx"}, CK_Haswell, FEATURE_AVX2, FeaturesHaswell, 'V', true },
326   { {"core_4th_gen_avx_tsx"}, CK_Haswell, FEATURE_AVX2, FeaturesHaswell, 'W', true },
327   // Broadwell microarchitecture based processors.
328   { {"broadwell"}, CK_Broadwell, FEATURE_AVX2, FeaturesBroadwell, 'X', false },
329   { {"core_5th_gen_avx"}, CK_Broadwell, FEATURE_AVX2, FeaturesBroadwell, 'X', true },
330   { {"core_5th_gen_avx_tsx"}, CK_Broadwell, FEATURE_AVX2, FeaturesBroadwell, 'Y', true },
331   // Skylake client microarchitecture based processors.
332   { {"skylake"}, CK_SkylakeClient, FEATURE_AVX2, FeaturesSkylakeClient, 'b', false },
333   // Skylake server microarchitecture based processors.
334   { {"skylake-avx512"}, CK_SkylakeServer, FEATURE_AVX512F, FeaturesSkylakeServer, '\0', false },
335   { {"skx"}, CK_SkylakeServer, FEATURE_AVX512F, FeaturesSkylakeServer, 'a', false },
336   { {"skylake_avx512"}, CK_SkylakeServer, FEATURE_AVX512F, FeaturesSkylakeServer, 'a', true },
337   // Cascadelake Server microarchitecture based processors.
338   { {"cascadelake"}, CK_Cascadelake, FEATURE_AVX512VNNI, FeaturesCascadeLake, 'o', false },
339   // Cooperlake Server microarchitecture based processors.
340   { {"cooperlake"}, CK_Cooperlake, FEATURE_AVX512BF16, FeaturesCooperLake, 'f', false },
341   // Cannonlake client microarchitecture based processors.
342   { {"cannonlake"}, CK_Cannonlake, FEATURE_AVX512VBMI, FeaturesCannonlake, 'e', false },
343   // Icelake client microarchitecture based processors.
344   { {"icelake-client"}, CK_IcelakeClient, FEATURE_AVX512VBMI2, FeaturesICLClient, '\0', false },
345   { {"icelake_client"}, CK_IcelakeClient, FEATURE_AVX512VBMI2, FeaturesICLClient, 'k', true },
346   // Rocketlake microarchitecture based processors.
347   { {"rocketlake"}, CK_Rocketlake, FEATURE_AVX512VBMI2, FeaturesRocketlake, 'k', false },
348   // Icelake server microarchitecture based processors.
349   { {"icelake-server"}, CK_IcelakeServer, FEATURE_AVX512VBMI2, FeaturesICLServer, '\0', false },
350   { {"icelake_server"}, CK_IcelakeServer, FEATURE_AVX512VBMI2, FeaturesICLServer, 'k', true },
351   // Tigerlake microarchitecture based processors.
352   { {"tigerlake"}, CK_Tigerlake, FEATURE_AVX512VP2INTERSECT, FeaturesTigerlake, 'l', false },
353   // Sapphire Rapids microarchitecture based processors.
354   { {"sapphirerapids"}, CK_SapphireRapids, FEATURE_AVX512FP16, FeaturesSapphireRapids, 'n', false },
355   // Alderlake microarchitecture based processors.
356   { {"alderlake"}, CK_Alderlake, FEATURE_AVX2, FeaturesAlderlake, 'p', false },
357   // Raptorlake microarchitecture based processors.
358   { {"raptorlake"}, CK_Raptorlake, FEATURE_AVX2, FeaturesAlderlake, 'p', false },
359   // Meteorlake microarchitecture based processors.
360   { {"meteorlake"}, CK_Meteorlake, FEATURE_AVX2, FeaturesAlderlake, 'p', false },
361   // Arrowlake microarchitecture based processors.
362   { {"arrowlake"}, CK_Arrowlake, FEATURE_AVX2, FeaturesSierraforest, 'p', false },
363   { {"arrowlake-s"}, CK_ArrowlakeS, FEATURE_AVX2, FeaturesArrowlakeS, '\0', false },
364   { {"arrowlake_s"}, CK_ArrowlakeS, FEATURE_AVX2, FeaturesArrowlakeS, 'p', true },
365   // Lunarlake microarchitecture based processors.
366   { {"lunarlake"}, CK_Lunarlake, FEATURE_AVX2, FeaturesArrowlakeS, 'p', false },
367   // Gracemont microarchitecture based processors.
368   { {"gracemont"}, CK_Gracemont, FEATURE_AVX2, FeaturesAlderlake, 'p', false },
369   // Pantherlake microarchitecture based processors.
370   { {"pantherlake"}, CK_Lunarlake, FEATURE_AVX2, FeaturesPantherlake, 'p', false },
371   // Sierraforest microarchitecture based processors.
372   { {"sierraforest"}, CK_Sierraforest, FEATURE_AVX2, FeaturesSierraforest, 'p', false },
373   // Grandridge microarchitecture based processors.
374   { {"grandridge"}, CK_Grandridge, FEATURE_AVX2, FeaturesSierraforest, 'p', false },
375   // Granite Rapids microarchitecture based processors.
376   { {"graniterapids"}, CK_Graniterapids, FEATURE_AVX512FP16, FeaturesGraniteRapids, 'n', false },
377   // Granite Rapids D microarchitecture based processors.
378   { {"graniterapids-d"}, CK_GraniterapidsD, FEATURE_AVX512FP16, FeaturesGraniteRapids | FeatureAMX_COMPLEX, '\0', false },
379   { {"graniterapids_d"}, CK_GraniterapidsD, FEATURE_AVX512FP16, FeaturesGraniteRapids | FeatureAMX_COMPLEX, 'n', true },
380   // Emerald Rapids microarchitecture based processors.
381   { {"emeraldrapids"}, CK_Emeraldrapids, FEATURE_AVX512FP16, FeaturesSapphireRapids, 'n', false },
382   // Clearwaterforest microarchitecture based processors.
383   { {"clearwaterforest"}, CK_Lunarlake, FEATURE_AVX2, FeaturesClearwaterforest, 'p', false },
384   // Knights Landing processor.
385   { {"knl"}, CK_KNL, FEATURE_AVX512F, FeaturesKNL, 'Z', false },
386   { {"mic_avx512"}, CK_KNL, FEATURE_AVX512F, FeaturesKNL, 'Z', true },
387   // Knights Mill processor.
388   { {"knm"}, CK_KNM, FEATURE_AVX5124FMAPS, FeaturesKNM, 'j', false },
389   // Lakemont microarchitecture based processors.
390   { {"lakemont"}, CK_Lakemont, ~0U, FeatureCMPXCHG8B, '\0', false },
391   // K6 architecture processors.
392   { {"k6"}, CK_K6, ~0U, FeaturesK6, '\0', false },
393   { {"k6-2"}, CK_K6_2, ~0U, FeaturesK6 | FeaturePRFCHW, '\0', false },
394   { {"k6-3"}, CK_K6_3, ~0U, FeaturesK6 | FeaturePRFCHW, '\0', false },
395   // K7 architecture processors.
396   { {"athlon"}, CK_Athlon, ~0U, FeaturesAthlon, '\0', false },
397   { {"athlon-tbird"}, CK_Athlon, ~0U, FeaturesAthlon, '\0', false },
398   { {"athlon-xp"}, CK_AthlonXP, ~0U, FeaturesAthlonXP, '\0', false },
399   { {"athlon-mp"}, CK_AthlonXP, ~0U, FeaturesAthlonXP, '\0', false },
400   { {"athlon-4"}, CK_AthlonXP, ~0U, FeaturesAthlonXP, '\0', false },
401   // K8 architecture processors.
402   { {"k8"}, CK_K8, ~0U, FeaturesK8, '\0', false },
403   { {"athlon64"}, CK_K8, ~0U, FeaturesK8, '\0', false },
404   { {"athlon-fx"}, CK_K8, ~0U, FeaturesK8, '\0', false },
405   { {"opteron"}, CK_K8, ~0U, FeaturesK8, '\0', false },
406   { {"k8-sse3"}, CK_K8SSE3, ~0U, FeaturesK8SSE3, '\0', false },
407   { {"athlon64-sse3"}, CK_K8SSE3, ~0U, FeaturesK8SSE3, '\0', false },
408   { {"opteron-sse3"}, CK_K8SSE3, ~0U, FeaturesK8SSE3, '\0', false },
409   { {"amdfam10"}, CK_AMDFAM10, FEATURE_SSE4_A, FeaturesAMDFAM10, '\0', false },
410   { {"barcelona"}, CK_AMDFAM10, FEATURE_SSE4_A, FeaturesAMDFAM10, '\0', false },
411   // Bobcat architecture processors.
412   { {"btver1"}, CK_BTVER1, FEATURE_SSE4_A, FeaturesBTVER1, '\0', false },
413   { {"btver2"}, CK_BTVER2, FEATURE_BMI, FeaturesBTVER2, '\0', false },
414   // Bulldozer architecture processors.
415   { {"bdver1"}, CK_BDVER1, FEATURE_XOP, FeaturesBDVER1, '\0', false },
416   { {"bdver2"}, CK_BDVER2, FEATURE_FMA, FeaturesBDVER2, '\0', false },
417   { {"bdver3"}, CK_BDVER3, FEATURE_FMA, FeaturesBDVER3, '\0', false },
418   { {"bdver4"}, CK_BDVER4, FEATURE_AVX2, FeaturesBDVER4, '\0', false },
419   // Zen architecture processors.
420   { {"znver1"}, CK_ZNVER1, FEATURE_AVX2, FeaturesZNVER1, '\0', false },
421   { {"znver2"}, CK_ZNVER2, FEATURE_AVX2, FeaturesZNVER2, '\0', false },
422   { {"znver3"}, CK_ZNVER3, FEATURE_AVX2, FeaturesZNVER3, '\0', false },
423   { {"znver4"}, CK_ZNVER4, FEATURE_AVX512VBMI2, FeaturesZNVER4, '\0', false },
424   { {"znver5"}, CK_ZNVER5, FEATURE_AVX512VP2INTERSECT, FeaturesZNVER5, '\0', false },
425   // Generic 64-bit processor.
426   { {"x86-64"}, CK_x86_64, FEATURE_SSE2 , FeaturesX86_64, '\0', false },
427   { {"x86-64-v2"}, CK_x86_64_v2, FEATURE_SSE4_2 , FeaturesX86_64_V2, '\0', false },
428   { {"x86-64-v3"}, CK_x86_64_v3, FEATURE_AVX2, FeaturesX86_64_V3, '\0', false },
429   { {"x86-64-v4"}, CK_x86_64_v4, FEATURE_AVX512VL, FeaturesX86_64_V4, '\0', false },
430   // Geode processors.
431   { {"geode"}, CK_Geode, ~0U, FeaturesGeode, '\0', false },
432 };
433 // clang-format on
434 
435 constexpr const char *NoTuneList[] = {"x86-64-v2", "x86-64-v3", "x86-64-v4"};
436 
parseArchX86(StringRef CPU,bool Only64Bit)437 X86::CPUKind llvm::X86::parseArchX86(StringRef CPU, bool Only64Bit) {
438   for (const auto &P : Processors)
439     if (!P.OnlyForCPUDispatchSpecific && P.Name == CPU &&
440         (P.Features[FEATURE_64BIT] || !Only64Bit))
441       return P.Kind;
442 
443   return CK_None;
444 }
445 
parseTuneCPU(StringRef CPU,bool Only64Bit)446 X86::CPUKind llvm::X86::parseTuneCPU(StringRef CPU, bool Only64Bit) {
447   if (llvm::is_contained(NoTuneList, CPU))
448     return CK_None;
449   return parseArchX86(CPU, Only64Bit);
450 }
451 
fillValidCPUArchList(SmallVectorImpl<StringRef> & Values,bool Only64Bit)452 void llvm::X86::fillValidCPUArchList(SmallVectorImpl<StringRef> &Values,
453                                      bool Only64Bit) {
454   for (const auto &P : Processors)
455     if (!P.OnlyForCPUDispatchSpecific && !P.Name.empty() &&
456         (P.Features[FEATURE_64BIT] || !Only64Bit))
457       Values.emplace_back(P.Name);
458 }
459 
fillValidTuneCPUList(SmallVectorImpl<StringRef> & Values,bool Only64Bit)460 void llvm::X86::fillValidTuneCPUList(SmallVectorImpl<StringRef> &Values,
461                                      bool Only64Bit) {
462   for (const ProcInfo &P : Processors)
463     if (!P.OnlyForCPUDispatchSpecific && !P.Name.empty() &&
464         (P.Features[FEATURE_64BIT] || !Only64Bit) &&
465         !llvm::is_contained(NoTuneList, P.Name))
466       Values.emplace_back(P.Name);
467 }
468 
getKeyFeature(X86::CPUKind Kind)469 ProcessorFeatures llvm::X86::getKeyFeature(X86::CPUKind Kind) {
470   // FIXME: Can we avoid a linear search here? The table might be sorted by
471   // CPUKind so we could binary search?
472   for (const auto &P : Processors) {
473     if (P.Kind == Kind) {
474       assert(P.KeyFeature != ~0U && "Processor does not have a key feature.");
475       return static_cast<ProcessorFeatures>(P.KeyFeature);
476     }
477   }
478 
479   llvm_unreachable("Unable to find CPU kind!");
480 }
481 
482 // Features with no dependencies.
483 constexpr FeatureBitset ImpliedFeatures64BIT = {};
484 constexpr FeatureBitset ImpliedFeaturesADX = {};
485 constexpr FeatureBitset ImpliedFeaturesBMI = {};
486 constexpr FeatureBitset ImpliedFeaturesBMI2 = {};
487 constexpr FeatureBitset ImpliedFeaturesCLDEMOTE = {};
488 constexpr FeatureBitset ImpliedFeaturesCLFLUSHOPT = {};
489 constexpr FeatureBitset ImpliedFeaturesCLWB = {};
490 constexpr FeatureBitset ImpliedFeaturesCLZERO = {};
491 constexpr FeatureBitset ImpliedFeaturesCMOV = {};
492 constexpr FeatureBitset ImpliedFeaturesCMPXCHG16B = {};
493 constexpr FeatureBitset ImpliedFeaturesCMPXCHG8B = {};
494 constexpr FeatureBitset ImpliedFeaturesCRC32 = {};
495 constexpr FeatureBitset ImpliedFeaturesENQCMD = {};
496 constexpr FeatureBitset ImpliedFeaturesFSGSBASE = {};
497 constexpr FeatureBitset ImpliedFeaturesFXSR = {};
498 constexpr FeatureBitset ImpliedFeaturesINVPCID = {};
499 constexpr FeatureBitset ImpliedFeaturesLWP = {};
500 constexpr FeatureBitset ImpliedFeaturesLZCNT = {};
501 constexpr FeatureBitset ImpliedFeaturesMMX = {};
502 constexpr FeatureBitset ImpliedFeaturesMWAITX = {};
503 constexpr FeatureBitset ImpliedFeaturesMOVBE = {};
504 constexpr FeatureBitset ImpliedFeaturesMOVDIR64B = {};
505 constexpr FeatureBitset ImpliedFeaturesMOVDIRI = {};
506 constexpr FeatureBitset ImpliedFeaturesPCONFIG = {};
507 constexpr FeatureBitset ImpliedFeaturesPOPCNT = {};
508 constexpr FeatureBitset ImpliedFeaturesPKU = {};
509 constexpr FeatureBitset ImpliedFeaturesPRFCHW = {};
510 constexpr FeatureBitset ImpliedFeaturesPTWRITE = {};
511 constexpr FeatureBitset ImpliedFeaturesRDPID = {};
512 constexpr FeatureBitset ImpliedFeaturesRDPRU = {};
513 constexpr FeatureBitset ImpliedFeaturesRDRND = {};
514 constexpr FeatureBitset ImpliedFeaturesRDSEED = {};
515 constexpr FeatureBitset ImpliedFeaturesRTM = {};
516 constexpr FeatureBitset ImpliedFeaturesSAHF = {};
517 constexpr FeatureBitset ImpliedFeaturesSERIALIZE = {};
518 constexpr FeatureBitset ImpliedFeaturesSGX = {};
519 constexpr FeatureBitset ImpliedFeaturesSHSTK = {};
520 constexpr FeatureBitset ImpliedFeaturesTBM = {};
521 constexpr FeatureBitset ImpliedFeaturesTSXLDTRK = {};
522 constexpr FeatureBitset ImpliedFeaturesUINTR = {};
523 constexpr FeatureBitset ImpliedFeaturesUSERMSR = {};
524 constexpr FeatureBitset ImpliedFeaturesWAITPKG = {};
525 constexpr FeatureBitset ImpliedFeaturesWBNOINVD = {};
526 constexpr FeatureBitset ImpliedFeaturesVZEROUPPER = {};
527 constexpr FeatureBitset ImpliedFeaturesX87 = {};
528 constexpr FeatureBitset ImpliedFeaturesXSAVE = {};
529 constexpr FeatureBitset ImpliedFeaturesDUMMYFEATURE1 = {};
530 constexpr FeatureBitset ImpliedFeaturesDUMMYFEATURE2 = {};
531 
532 // Not really CPU features, but need to be in the table because clang uses
533 // target features to communicate them to the backend.
534 constexpr FeatureBitset ImpliedFeaturesRETPOLINE_EXTERNAL_THUNK = {};
535 constexpr FeatureBitset ImpliedFeaturesRETPOLINE_INDIRECT_BRANCHES = {};
536 constexpr FeatureBitset ImpliedFeaturesRETPOLINE_INDIRECT_CALLS = {};
537 constexpr FeatureBitset ImpliedFeaturesLVI_CFI = {};
538 constexpr FeatureBitset ImpliedFeaturesLVI_LOAD_HARDENING = {};
539 
540 // XSAVE features are dependent on basic XSAVE.
541 constexpr FeatureBitset ImpliedFeaturesXSAVEC = FeatureXSAVE;
542 constexpr FeatureBitset ImpliedFeaturesXSAVEOPT = FeatureXSAVE;
543 constexpr FeatureBitset ImpliedFeaturesXSAVES = FeatureXSAVE;
544 
545 // SSE/AVX/AVX512F chain.
546 constexpr FeatureBitset ImpliedFeaturesSSE = {};
547 constexpr FeatureBitset ImpliedFeaturesSSE2 = FeatureSSE;
548 constexpr FeatureBitset ImpliedFeaturesSSE3 = FeatureSSE2;
549 constexpr FeatureBitset ImpliedFeaturesSSSE3 = FeatureSSE3;
550 constexpr FeatureBitset ImpliedFeaturesSSE4_1 = FeatureSSSE3;
551 constexpr FeatureBitset ImpliedFeaturesSSE4_2 = FeatureSSE4_1;
552 constexpr FeatureBitset ImpliedFeaturesAVX = FeatureSSE4_2;
553 constexpr FeatureBitset ImpliedFeaturesAVX2 = FeatureAVX;
554 constexpr FeatureBitset ImpliedFeaturesEVEX512 = {};
555 constexpr FeatureBitset ImpliedFeaturesAVX512F =
556     FeatureAVX2 | FeatureF16C | FeatureFMA;
557 
558 // Vector extensions that build on SSE or AVX.
559 constexpr FeatureBitset ImpliedFeaturesAES = FeatureSSE2;
560 constexpr FeatureBitset ImpliedFeaturesF16C = FeatureAVX;
561 constexpr FeatureBitset ImpliedFeaturesFMA = FeatureAVX;
562 constexpr FeatureBitset ImpliedFeaturesGFNI = FeatureSSE2;
563 constexpr FeatureBitset ImpliedFeaturesPCLMUL = FeatureSSE2;
564 constexpr FeatureBitset ImpliedFeaturesSHA = FeatureSSE2;
565 constexpr FeatureBitset ImpliedFeaturesVAES = FeatureAES | FeatureAVX2;
566 constexpr FeatureBitset ImpliedFeaturesVPCLMULQDQ = FeatureAVX | FeaturePCLMUL;
567 constexpr FeatureBitset ImpliedFeaturesSM3 = FeatureAVX;
568 constexpr FeatureBitset ImpliedFeaturesSM4 = FeatureAVX2;
569 
570 // AVX512 features.
571 constexpr FeatureBitset ImpliedFeaturesAVX512CD = FeatureAVX512F;
572 constexpr FeatureBitset ImpliedFeaturesAVX512BW = FeatureAVX512F;
573 constexpr FeatureBitset ImpliedFeaturesAVX512DQ = FeatureAVX512F;
574 constexpr FeatureBitset ImpliedFeaturesAVX512VL = FeatureAVX512F;
575 
576 constexpr FeatureBitset ImpliedFeaturesAVX512BF16 = FeatureAVX512BW;
577 constexpr FeatureBitset ImpliedFeaturesAVX512BITALG = FeatureAVX512BW;
578 constexpr FeatureBitset ImpliedFeaturesAVX512IFMA = FeatureAVX512F;
579 constexpr FeatureBitset ImpliedFeaturesAVX512VNNI = FeatureAVX512F;
580 constexpr FeatureBitset ImpliedFeaturesAVX512VPOPCNTDQ = FeatureAVX512F;
581 constexpr FeatureBitset ImpliedFeaturesAVX512VBMI = FeatureAVX512BW;
582 constexpr FeatureBitset ImpliedFeaturesAVX512VBMI2 = FeatureAVX512BW;
583 constexpr FeatureBitset ImpliedFeaturesAVX512VP2INTERSECT = FeatureAVX512F;
584 
585 // FIXME: These two aren't really implemented and just exist in the feature
586 // list for __builtin_cpu_supports. So omit their dependencies.
587 constexpr FeatureBitset ImpliedFeaturesAVX5124FMAPS = {};
588 constexpr FeatureBitset ImpliedFeaturesAVX5124VNNIW = {};
589 
590 // SSE4_A->FMA4->XOP chain.
591 constexpr FeatureBitset ImpliedFeaturesSSE4_A = FeatureSSE3;
592 constexpr FeatureBitset ImpliedFeaturesFMA4 = FeatureAVX | FeatureSSE4_A;
593 constexpr FeatureBitset ImpliedFeaturesXOP = FeatureFMA4;
594 
595 // AMX Features
596 constexpr FeatureBitset ImpliedFeaturesAMX_TILE = {};
597 constexpr FeatureBitset ImpliedFeaturesAMX_BF16 = FeatureAMX_TILE;
598 constexpr FeatureBitset ImpliedFeaturesAMX_FP16 = FeatureAMX_TILE;
599 constexpr FeatureBitset ImpliedFeaturesAMX_INT8 = FeatureAMX_TILE;
600 constexpr FeatureBitset ImpliedFeaturesAMX_COMPLEX = FeatureAMX_TILE;
601 constexpr FeatureBitset ImpliedFeaturesHRESET = {};
602 
603 constexpr FeatureBitset ImpliedFeaturesPREFETCHI = {};
604 constexpr FeatureBitset ImpliedFeaturesCMPCCXADD = {};
605 constexpr FeatureBitset ImpliedFeaturesRAOINT = {};
606 constexpr FeatureBitset ImpliedFeaturesAVXVNNIINT16 = FeatureAVX2;
607 constexpr FeatureBitset ImpliedFeaturesAVXVNNIINT8 = FeatureAVX2;
608 constexpr FeatureBitset ImpliedFeaturesAVXIFMA = FeatureAVX2;
609 constexpr FeatureBitset ImpliedFeaturesAVXNECONVERT = FeatureAVX2;
610 constexpr FeatureBitset ImpliedFeaturesSHA512 = FeatureAVX2;
611 constexpr FeatureBitset ImpliedFeaturesAVX512FP16 =
612     FeatureAVX512BW | FeatureAVX512DQ | FeatureAVX512VL;
613 // Key Locker Features
614 constexpr FeatureBitset ImpliedFeaturesKL = FeatureSSE2;
615 constexpr FeatureBitset ImpliedFeaturesWIDEKL = FeatureKL;
616 
617 // AVXVNNI Features
618 constexpr FeatureBitset ImpliedFeaturesAVXVNNI = FeatureAVX2;
619 
620 // AVX10 Features
621 constexpr FeatureBitset ImpliedFeaturesAVX10_1 =
622     FeatureAVX512CD | FeatureAVX512VBMI | FeatureAVX512IFMA |
623     FeatureAVX512VNNI | FeatureAVX512BF16 | FeatureAVX512VPOPCNTDQ |
624     FeatureAVX512VBMI2 | FeatureAVX512BITALG | FeatureVAES | FeatureVPCLMULQDQ |
625     FeatureAVX512FP16;
626 constexpr FeatureBitset ImpliedFeaturesAVX10_1_512 =
627     FeatureAVX10_1 | FeatureEVEX512;
628 
629 // APX Features
630 constexpr FeatureBitset ImpliedFeaturesEGPR = {};
631 constexpr FeatureBitset ImpliedFeaturesPush2Pop2 = {};
632 constexpr FeatureBitset ImpliedFeaturesPPX = {};
633 constexpr FeatureBitset ImpliedFeaturesNDD = {};
634 constexpr FeatureBitset ImpliedFeaturesCCMP = {};
635 constexpr FeatureBitset ImpliedFeaturesNF = {};
636 constexpr FeatureBitset ImpliedFeaturesCF = {};
637 constexpr FeatureBitset ImpliedFeaturesZU = {};
638 
639 constexpr FeatureInfo FeatureInfos[X86::CPU_FEATURE_MAX] = {
640 #define X86_FEATURE(ENUM, STR) {{"+" STR}, ImpliedFeatures##ENUM},
641 #include "llvm/TargetParser/X86TargetParser.def"
642 };
643 
getFeaturesForCPU(StringRef CPU,SmallVectorImpl<StringRef> & EnabledFeatures,bool NeedPlus)644 void llvm::X86::getFeaturesForCPU(StringRef CPU,
645                                   SmallVectorImpl<StringRef> &EnabledFeatures,
646                                   bool NeedPlus) {
647   auto I = llvm::find_if(Processors,
648                          [&](const ProcInfo &P) { return P.Name == CPU; });
649   assert(I != std::end(Processors) && "Processor not found!");
650 
651   FeatureBitset Bits = I->Features;
652 
653   // Remove the 64-bit feature which we only use to validate if a CPU can
654   // be used with 64-bit mode.
655   Bits &= ~Feature64BIT;
656 
657   // Add the string version of all set bits.
658   for (unsigned i = 0; i != CPU_FEATURE_MAX; ++i)
659     if (Bits[i] && !FeatureInfos[i].getName(NeedPlus).empty())
660       EnabledFeatures.push_back(FeatureInfos[i].getName(NeedPlus));
661 }
662 
663 // For each feature that is (transitively) implied by this feature, set it.
getImpliedEnabledFeatures(FeatureBitset & Bits,const FeatureBitset & Implies)664 static void getImpliedEnabledFeatures(FeatureBitset &Bits,
665                                       const FeatureBitset &Implies) {
666   // Fast path: Implies is often empty.
667   if (!Implies.any())
668     return;
669   FeatureBitset Prev;
670   Bits |= Implies;
671   do {
672     Prev = Bits;
673     for (unsigned i = CPU_FEATURE_MAX; i;)
674       if (Bits[--i])
675         Bits |= FeatureInfos[i].ImpliedFeatures;
676   } while (Prev != Bits);
677 }
678 
679 /// Create bit vector of features that are implied disabled if the feature
680 /// passed in Value is disabled.
getImpliedDisabledFeatures(FeatureBitset & Bits,unsigned Value)681 static void getImpliedDisabledFeatures(FeatureBitset &Bits, unsigned Value) {
682   // Check all features looking for any dependent on this feature. If we find
683   // one, mark it and recursively find any feature that depend on it.
684   FeatureBitset Prev;
685   Bits.set(Value);
686   do {
687     Prev = Bits;
688     for (unsigned i = 0; i != CPU_FEATURE_MAX; ++i)
689       if ((FeatureInfos[i].ImpliedFeatures & Bits).any())
690         Bits.set(i);
691   } while (Prev != Bits);
692 }
693 
updateImpliedFeatures(StringRef Feature,bool Enabled,StringMap<bool> & Features)694 void llvm::X86::updateImpliedFeatures(
695     StringRef Feature, bool Enabled,
696     StringMap<bool> &Features) {
697   auto I = llvm::find_if(FeatureInfos, [&](const FeatureInfo &FI) {
698     return FI.getName() == Feature;
699   });
700   if (I == std::end(FeatureInfos)) {
701     // FIXME: This shouldn't happen, but may not have all features in the table
702     // yet.
703     return;
704   }
705 
706   FeatureBitset ImpliedBits;
707   if (Enabled)
708     getImpliedEnabledFeatures(ImpliedBits, I->ImpliedFeatures);
709   else
710     getImpliedDisabledFeatures(ImpliedBits,
711                                std::distance(std::begin(FeatureInfos), I));
712 
713   // Update the map entry for all implied features.
714   for (unsigned i = 0; i != CPU_FEATURE_MAX; ++i)
715     if (ImpliedBits[i] && !FeatureInfos[i].getName().empty())
716       Features[FeatureInfos[i].getName()] = Enabled;
717 }
718 
getCPUDispatchMangling(StringRef CPU)719 char llvm::X86::getCPUDispatchMangling(StringRef CPU) {
720   auto I = llvm::find_if(Processors,
721                          [&](const ProcInfo &P) { return P.Name == CPU; });
722   assert(I != std::end(Processors) && "Processor not found!");
723   assert(I->Mangling != '\0' && "Processor dooesn't support function multiversion!");
724   return I->Mangling;
725 }
726 
validateCPUSpecificCPUDispatch(StringRef Name)727 bool llvm::X86::validateCPUSpecificCPUDispatch(StringRef Name) {
728   auto I = llvm::find_if(Processors,
729                          [&](const ProcInfo &P) { return P.Name == Name; });
730   return I != std::end(Processors);
731 }
732 
733 std::array<uint32_t, 4>
getCpuSupportsMask(ArrayRef<StringRef> FeatureStrs)734 llvm::X86::getCpuSupportsMask(ArrayRef<StringRef> FeatureStrs) {
735   // Processor features and mapping to processor feature value.
736   std::array<uint32_t, 4> FeatureMask{};
737   for (StringRef FeatureStr : FeatureStrs) {
738     unsigned Feature = StringSwitch<unsigned>(FeatureStr)
739 #define X86_FEATURE_COMPAT(ENUM, STR, PRIORITY)                                \
740   .Case(STR, llvm::X86::FEATURE_##ENUM)
741 #define X86_MICROARCH_LEVEL(ENUM, STR, PRIORITY)                               \
742   .Case(STR, llvm::X86::FEATURE_##ENUM)
743 #include "llvm/TargetParser/X86TargetParser.def"
744         ;
745     assert(Feature / 32 < FeatureMask.size());
746     FeatureMask[Feature / 32] |= 1U << (Feature % 32);
747   }
748   return FeatureMask;
749 }
750 
getFeaturePriority(ProcessorFeatures Feat)751 unsigned llvm::X86::getFeaturePriority(ProcessorFeatures Feat) {
752 #ifndef NDEBUG
753   // Check that priorities are set properly in the .def file. We expect that
754   // "compat" features are assigned non-duplicate consecutive priorities
755   // starting from one (1, ..., 37) and multiple zeros.
756 #define X86_FEATURE_COMPAT(ENUM, STR, PRIORITY) PRIORITY,
757   unsigned Priorities[] = {
758 #include "llvm/TargetParser/X86TargetParser.def"
759   };
760   std::array<unsigned, std::size(Priorities)> HelperList;
761   const size_t MaxPriority = 37;
762   std::iota(HelperList.begin(), HelperList.begin() + MaxPriority + 1, 0);
763   for (size_t i = MaxPriority + 1; i != std::size(Priorities); ++i)
764     HelperList[i] = 0;
765   assert(std::is_permutation(HelperList.begin(), HelperList.end(),
766                              std::begin(Priorities), std::end(Priorities)) &&
767          "Priorities don't form consecutive range!");
768 #endif
769 
770   switch (Feat) {
771 #define X86_FEATURE_COMPAT(ENUM, STR, PRIORITY)                                \
772   case X86::FEATURE_##ENUM:                                                    \
773     return PRIORITY;
774 #include "llvm/TargetParser/X86TargetParser.def"
775   default:
776     llvm_unreachable("No Feature Priority for non-CPUSupports Features");
777   }
778 }
779