| /freebsd/contrib/llvm-project/llvm/lib/MC/ |
| H A D | MCInstrDesc.cpp | 34 for (MCPhysReg ImpDef : implicit_defs()) in hasImplicitDefOfPhysReg() local
35 if (ImpDef == Reg || (MRI && MRI->isSubRegister(Reg, ImpDef))) in hasImplicitDefOfPhysReg()
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| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/ |
| H A D | RenameIndependentSubregs.cpp | 333 MachineInstrBuilder ImpDef = BuildMI(*PredMBB, InsertPos, in computeMainRangesFixFlags() local
335 SlotIndex DefIdx = LIS->InsertMachineInstrInMaps(*ImpDef); in computeMainRangesFixFlags()
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| H A D | RegisterCoalescer.cpp | 2523 const MachineInstr &ImpDef) { in mustKeepImplicitDef()
2524 assert(ImpDef.isImplicitDef()); in mustKeepImplicitDef()
2526 ValidLanes = TRI.getSubRegIndexLaneMask(ImpDef.getOperand(0).getSubReg()); in mustKeepImplicitDef()
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| H A D | MachineInstr.cpp | 89 for (MCPhysReg ImpDef : MCID->implicit_defs()) in addImplicitDefUseOperands() local
90 addOperand(MF, MachineOperand::CreateReg(ImpDef, true, true)); in addImplicitDefUseOperands()
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| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | ScheduleDAGFast.cpp | 428 for (MCPhysReg ImpDef : MCID.implicit_defs()) { in getPhysicalRegisterVT() local
429 if (Reg == ImpDef) in getPhysicalRegisterVT()
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| H A D | ScheduleDAGRRList.cpp | 1284 for (MCPhysReg ImpDef : MCID.implicit_defs()) { in getPhysicalRegisterVT() local
1285 if (Reg == ImpDef) in getPhysicalRegisterVT()
2877 for (MCPhysReg ImpDef : ImpDefs) { in canClobberReachingPhysRegUse() local
2881 if (TRI->regsOverlap(ImpDef, SuccPred.getReg()) && in canClobberReachingPhysRegUse()
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| /freebsd/contrib/llvm-project/llvm/utils/TableGen/ |
| H A D | DAGISelMatcherGen.cpp | 693 Record *ImpDef = Def->getRecords().getDef("IMPLICIT_DEF"); in EmitResultLeafAsOperand() local
694 CodeGenInstruction &II = CGP.getTargetInfo().getInstruction(ImpDef); in EmitResultLeafAsOperand()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/ARM/ |
| H A D | ARMLoadStoreOptimizer.cpp | 960 for (unsigned ImpDef : ImpDefs) in MergeOpsUpdate() local
961 MIB.addReg(ImpDef, RegState::ImplicitDefine); in MergeOpsUpdate()
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| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/MIRParser/ |
| H A D | MIParser.cpp | 1439 for (MCPhysReg ImpDef : MCID.implicit_defs()) in verifyImplicitOperands() local
1440 ImplicitOperands.push_back(MachineOperand::CreateReg(ImpDef, true, true)); in verifyImplicitOperands()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/ |
| H A D | PPCInstrInfo.cpp | 2734 for (MCPhysReg ImpDef : NewDesc.implicit_defs()) { in optimizeCompareInstr() local
2735 if (!MI->definesRegister(ImpDef, /*TRI=*/nullptr)) { in optimizeCompareInstr()
2737 MachineOperand::CreateReg(ImpDef, true, true)); in optimizeCompareInstr()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | AMDGPUISelDAGToDAG.cpp | 480 MachineSDNode *ImpDef = CurDAG->getMachineNode(TargetOpcode::IMPLICIT_DEF, in SelectBuildVector() local
485 RegSeqArgs[1 + (2 * i)] = SDValue(ImpDef, 0); in SelectBuildVector()
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| H A D | SIInstrInfo.cpp | 6247 bool ImpDef = Def->isImplicitDef(); in legalizeGenericOperand() local
6248 while (!ImpDef && Def && Def->isCopy()) { in legalizeGenericOperand()
6252 ImpDef = Def && Def->isImplicitDef(); in legalizeGenericOperand()
6255 !ImpDef) in legalizeGenericOperand()
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| H A D | SIISelLowering.cpp | 15080 SDValue ImpDef = DAG.getCopyToReg(DAG.getEntryNode(), SDLoc(Node), in PostISelFolding() local
15105 Ops.push_back(ImpDef.getValue(1)); in PostISelFolding()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64ISelDAGToDAG.cpp | 1193 SDValue ImpDef = SDValue( in Widen() local
1195 return CurDAG->getTargetInsertSubreg(AArch64::sub_32, dl, MVT::i64, ImpDef, in Widen()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86InstrInfo.cpp | 1267 MachineInstr *ImpDef = in convertToThreeAddressWithLEA() local
1355 LIS->InsertMachineInstrInMaps(*ImpDef); in convertToThreeAddressWithLEA()
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