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Searched refs:ImmArg (Results 1 – 25 of 36) sorted by relevance

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/freebsd/contrib/llvm-project/llvm/include/llvm/IR/
H A DIntrinsicsX86.td16 def int_x86_int : Intrinsic<[], [llvm_i8_ty], [ImmArg<ArgIndex<0>>]>;
68 [ImmArg<ArgIndex<1>>]>;
70 [ImmArg<ArgIndex<1>>]>;
72 [ImmArg<ArgIndex<1>>]>;
86 [ImmArg<ArgIndex<2>>]>;
88 [ImmArg<ArgIndex<2>>]>;
90 [ImmArg<ArgIndex<2>>]>;
92 [ImmArg<ArgIndex<2>>]>;
94 [ImmArg<ArgIndex<2>>]>;
168 [IntrNoMem, ImmArg<ArgIndex<2>>]>;
[all …]
H A DIntrinsicsRISCVXsf.td19 … !listconcat([IntrNoMem, ImmArg<ArgIndex<0>>, ImmArg<ArgIndex<1>>], // bit<27-26> and bit<24-20>
20 … !if(ImmScalar, [ImmArg<ArgIndex<2>>], []), // ScalarOperand
33 !listconcat([IntrNoMem, IntrHasSideEffects, ImmArg<ArgIndex<0>>,
34 ImmArg<ArgIndex<1>>, ImmArg<ArgIndex<2>>,
35 … ImmArg<ArgIndex<4>>, ImmArg<ArgIndex<5>>], // bit<27-26>, bit<24-20>, bit<11-7>, sew, log2lmul
36 !if(ImmScalar, [ImmArg<ArgIndex<3>>], []))>, // ScalarOperand
50 … !listconcat([IntrNoMem, ImmArg<ArgIndex<0>>], // bit<27-26>
51 … !if(HasDst, [], [ImmArg<ArgIndex<1>>]), // Vd or bit<11-7>
52 !if(ImmScalar, !if(HasDst, [ImmArg<ArgIndex<2>>],
53 … [ImmArg<ArgIndex<3>>]), []), // ScalarOperand
[all …]
H A DIntrinsicsLoongArch.td21 [IntrArgMemOnly, NoCapture<ArgIndex<0>>, ImmArg<ArgIndex<3>>]>;
60 def int_loongarch_break : BaseInt<[], [llvm_i32_ty], [ImmArg<ArgIndex<0>>]>;
62 [ImmArg<ArgIndex<0>>, ImmArg<ArgIndex<2>>]>;
64 [ImmArg<ArgIndex<0>>, ImmArg<ArgIndex<2>>]>;
65 def int_loongarch_dbar : BaseInt<[], [llvm_i32_ty], [ImmArg<ArgIndex<0>>]>;
67 def int_loongarch_ibar : BaseInt<[], [llvm_i32_ty], [ImmArg<ArgIndex<0>>]>;
69 [ImmArg<ArgIndex<0>>]>;
71 [ImmArg<ArgIndex<0>>]>;
72 def int_loongarch_syscall : BaseInt<[], [llvm_i32_ty], [ImmArg<ArgIndex<0>>]>;
93 [ImmArg<ArgIndex<0>>]>;
[all …]
H A DIntrinsicsBPF.td25 [IntrNoMem, ImmArg<ArgIndex<1>>]>;
53 ImmArg <ArgIndex<1>>, // volatile
54 ImmArg <ArgIndex<2>>, // atomic order
55 ImmArg <ArgIndex<3>>, // synscope id
56 ImmArg <ArgIndex<4>>, // alignment
57 ImmArg <ArgIndex<5>>, // inbounds
73 ImmArg <ArgIndex<2>>, // volatile
74 ImmArg <ArgIndex<3>>, // atomic order
75 ImmArg <ArgIndex<4>>, // syncscope id
76 ImmArg <ArgIndex<5>>, // alignment
[all …]
H A DIntrinsicsHexagonDep.td1112 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_addi", [IntrNoMem, ImmArg<ArgIndex<1>>]>;
1130 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_andir", [IntrNoMem, ImmArg<ArgIndex<1>>]>;
1154 Hexagon_i64_i32i32_Intrinsic<"HEXAGON_A2_combineii", [IntrNoMem, ImmArg<ArgIndex<0>>, ImmArg<ArgInd…
1202 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_orir", [IntrNoMem, ImmArg<ArgIndex<1>>]>;
1268 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_subri", [IntrNoMem, ImmArg<ArgIndex<0>>]>;
1316 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_tfrih", [IntrNoMem, ImmArg<ArgIndex<1>>]>;
1319 Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_tfril", [IntrNoMem, ImmArg<ArgIndex<1>>]>;
1325 Hexagon_i64_i32_Intrinsic<"HEXAGON_A2_tfrpi", [IntrNoMem, ImmArg<ArgIndex<0>>]>;
1328 Hexagon_i32_i32_Intrinsic<"HEXAGON_A2_tfrsi", [IntrNoMem, ImmArg<ArgIndex<0>>]>;
1541 Hexagon_i64_i32i32_Intrinsic<"HEXAGON_A4_bitspliti", [IntrNoMem, ImmArg<ArgIndex<1>>]>;
[all …]
H A DIntrinsicsMips.td237 Intrinsic<[], [llvm_i32_ty, llvm_i32_ty], [ImmArg<ArgIndex<1>>]>;
239 DefaultAttrsIntrinsic<[llvm_i32_ty], [llvm_i32_ty], [IntrReadMem, ImmArg<ArgIndex<0>>]>;
305 [IntrNoMem, ImmArg<ArgIndex<2>>]>;
308 [IntrNoMem, ImmArg<ArgIndex<2>>]>;
358 [IntrNoMem, ImmArg<ArgIndex<2>>]>;
361 [IntrNoMem, ImmArg<ArgIndex<2>>]>;
365 [IntrNoMem, ImmArg<ArgIndex<2>>]>;
466 [Commutative, IntrNoMem, ImmArg<ArgIndex<1>>]>;
469 [Commutative, IntrNoMem, ImmArg<ArgIndex<1>>]>;
472 [Commutative, IntrNoMem, ImmArg<ArgIndex<1>>]>;
[all …]
H A DIntrinsicsWebAssembly.td129 [Throws, IntrNoReturn, ImmArg<ArgIndex<0>>]>;
145 [IntrHasSideEffects, ImmArg<ArgIndex<0>>]>;
152 [IntrNoMem, ImmArg<ArgIndex<1>>]>;
197 ImmArg<ArgIndex<2>>, ImmArg<ArgIndex<3>>,
198 ImmArg<ArgIndex<4>>, ImmArg<ArgIndex<5>>,
199 ImmArg<ArgIndex<6>>, ImmArg<ArgIndex<7>>,
200 ImmArg<ArgIndex<8>>, ImmArg<ArgIndex<9>>,
201 ImmArg<ArgIndex<10>>, ImmArg<ArgIndex<11>>,
202 ImmArg<ArgIndex<12>>, ImmArg<ArgIndex<13>>,
203 ImmArg<ArgIndex<14>>, ImmArg<ArgIndex<15>>,
[all …]
H A DIntrinsicsARM.td22 def int_arm_space : Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], [ImmArg<ArgIndex<0>>]>;
327 …Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_ptr_ty], [ImmArg<ArgIndex<0>>, ImmArg<ArgIndex<1>>]>;
329 …Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_ptr_ty], [ImmArg<ArgIndex<0>>, ImmArg<ArgIndex<1>>]>;
331 …Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_ptr_ty], [ImmArg<ArgIndex<0>>, ImmArg<ArgIndex<1>>]>;
333 …Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_ptr_ty], [ImmArg<ArgIndex<0>>, ImmArg<ArgIndex<1>>]>;
336 …Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_ptr_ty], [ImmArg<ArgIndex<0>>, ImmArg<ArgIndex<1>>]>;
338 …Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_ptr_ty], [ImmArg<ArgIndex<0>>, ImmArg<ArgIndex<1>>]>;
340 …Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_ptr_ty], [ImmArg<ArgIndex<0>>, ImmArg<ArgIndex<1>>]>;
342 …Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_ptr_ty], [ImmArg<ArgIndex<0>>, ImmArg<ArgIndex<1>>]>;
347 …y, llvm_i32_ty, llvm_i32_ty], [ImmArg<ArgIndex<0>>, ImmArg<ArgIndex<1>>, ImmArg<ArgIndex<3>>, ImmA…
[all …]
H A DIntrinsicsAMDGPU.td214 IntrNoFree, IntrWillReturn, ImmArg<ArgIndex<0>>]>;
225 IntrNoFree, IntrWillReturn, ImmArg<ArgIndex<1>>]>;
257 [ImmArg<ArgIndex<0>>, IntrNoMem, IntrHasSideEffects, IntrWillReturn, IntrNoCallback]>;
260 [ImmArg<ArgIndex<0>>, IntrNoMem, IntrHasSideEffects, IntrNoCallback]>;
266 [ImmArg<ArgIndex<0>>, IntrNoMem, IntrHasSideEffects, IntrWillReturn, IntrNoCallback]>;
277 …Intrinsic<[], [llvm_i32_ty], [ImmArg<ArgIndex<0>>, IntrNoMem, IntrHasSideEffects, IntrConvergent, …
289 …Intrinsic<[llvm_i1_ty], [llvm_i32_ty], [ImmArg<ArgIndex<0>>, IntrNoMem, IntrHasSideEffects, IntrCo…
294 Intrinsic<[], [llvm_i16_ty], [ImmArg<ArgIndex<0>>, IntrNoMem, IntrHasSideEffects, IntrConvergent,
327 Intrinsic<[], [llvm_i32_ty], [ImmArg<ArgIndex<0>>, IntrNoMem, IntrHasSideEffects, IntrConvergent,
340 [ImmArg<ArgIndex<0>>, ImmArg<ArgIndex<1>>, ImmArg<ArgIndex<2>>, IntrNoMem, IntrHasSideEffects,
[all …]
H A DIntrinsicsRISCV.td31 [IntrArgMemOnly, NoCapture<ArgIndex<0>>, ImmArg<ArgIndex<3>>]>;
35 [IntrArgMemOnly, NoCapture<ArgIndex<0>>, ImmArg<ArgIndex<4>>]>;
120 [IntrNoMem, IntrSpeculatable, ImmArg<ArgIndex<1>>]>;
124 [IntrNoMem, IntrSpeculatable, ImmArg<ArgIndex<2>>]>;
152 ImmArg<ArgIndex<1>>,
153 ImmArg<ArgIndex<2>>]>;
158 ImmArg<ArgIndex<0>>,
159 ImmArg<ArgIndex<1>>]>;
198 [NoCapture<ArgIndex<1>>, ImmArg<ArgIndex<4>>, IntrReadMem,
213 [NoCapture<ArgIndex<1>>, ImmArg<ArgIndex<4>>]>, RISCVVIntrinsic {
[all …]
H A DIntrinsicsSystemZ.td38 [IntrNoMem, ImmArg<ArgIndex<1>>]>;
55 Intrinsic<[type], [type, type, llvm_i32_ty], [IntrNoMem, ImmArg<ArgIndex<2>>]>;
59 [IntrNoMem, ImmArg<ArgIndex<2>>]>;
64 [IntrNoMem, ImmArg<ArgIndex<3>>]>;
68 [IntrNoMem, ImmArg<ArgIndex<3>>]>;
230 [IntrNoMem, ImmArg<ArgIndex<1>>]>;
234 [IntrReadMem, IntrArgMemOnly, ImmArg<ArgIndex<1>>]>;
243 [IntrNoMem, ImmArg<ArgIndex<2>>]>;
307 [IntrNoMem, ImmArg<ArgIndex<2>>]>;
366 [IntrNoMem, ImmArg<ArgIndex<1>>, ImmArg<ArgIndex<2>>]>;
[all …]
H A DIntrinsicsSPIRV.td17 …def int_spv_assign_ptr_type : Intrinsic<[], [llvm_any_ty, llvm_metadata_ty, llvm_i32_ty], [ImmArg<…
26 …def int_spv_gep : Intrinsic<[llvm_anyptr_ty], [llvm_i1_ty, llvm_any_ty, llvm_vararg_ty], [ImmArg<A…
27 …sic<[llvm_i32_ty], [llvm_anyptr_ty, llvm_i16_ty, llvm_i8_ty], [ImmArg<ArgIndex<1>>, ImmArg<ArgInde…
28 …c<[], [llvm_any_ty, llvm_anyptr_ty, llvm_i16_ty, llvm_i8_ty], [ImmArg<ArgIndex<2>>, ImmArg<ArgInde…
35 …st : Intrinsic<[llvm_any_ty], [llvm_any_ty, llvm_metadata_ty, llvm_i32_ty], [ImmArg<ArgIndex<2>>]>;
38 def int_spv_selection_merge : Intrinsic<[], [llvm_any_ty, llvm_i32_ty], [ImmArg<ArgIndex<1>>]>;
41 def int_spv_alloca : Intrinsic<[llvm_any_ty], [llvm_i8_ty], [ImmArg<ArgIndex<0>>]>;
42 …def int_spv_alloca_array : Intrinsic<[llvm_any_ty], [llvm_anyint_ty, llvm_i8_ty], [ImmArg<ArgIndex…
55 ImmArg<ArgIndex<0>>]>;
60 ImmArg<ArgIndex<0>>]>;
[all …]
H A DIntrinsics.td114 // ImmArg - The specified argument must be an immediate.
115 class ImmArg<ArgIndex idx> : IntrinsicProperty {
851 [IntrNoMem, ImmArg<ArgIndex<0>>]>;
854 [IntrNoMem, ImmArg<ArgIndex<0>>]>;
875 [IntrNoMem, ImmArg<ArgIndex<2>>]>;
913 ImmArg<ArgIndex<1>>, ImmArg<ArgIndex<2>>, ImmArg<ArgIndex<3>>]>;
1000 ImmArg<ArgIndex<3>>]>;
1012 ImmArg<ArgIndex<3>>]>;
1021 ImmArg<ArgIndex<3>>]>;
1028 ImmArg<ArgIndex<3>>]>;
[all …]
H A DIntrinsicsAArch64.td67 [IntrNoMem, IntrHasSideEffects, IntrNoReturn, IntrCold, ImmArg<ArgIndex<0>>]>;
70 [IntrNoMem, IntrHasSideEffects, IntrNoReturn, IntrCold, ImmArg<ArgIndex<0>>]>;
75 ImmArg<ArgIndex<1>>, ImmArg<ArgIndex<2>>, ImmArg<ArgIndex<3>>, ImmArg<ArgIndex<4>>
568 [IntrNoMem, ImmArg<ArgIndex<2>>]>;
573 [IntrNoMem, ImmArg<ArgIndex<2>>]>;
578 [IntrNoMem, ImmArg<ArgIndex<2>>]>;
583 [IntrNoMem, ImmArg<ArgIndex<2>>]>;
590 [IntrNoMem, ImmArg<ArgIndex<3>>]>;
596 [IntrNoMem, ImmArg<ArgIndex<3>>]>;
833 [IntrNoMem, ImmArg<ArgIndex<2>>]>;
[all …]
H A DIntrinsicsPowerPC.td27 [IntrArgMemOnly, NoCapture<ArgIndex<0>>, ImmArg<ArgIndex<1>>]>;
29 [IntrArgMemOnly, NoCapture<ArgIndex<0>>, ImmArg<ArgIndex<1>>]>;
151 Intrinsic <[], [llvm_i64_ty, llvm_i64_ty, llvm_i32_ty], [ImmArg<ArgIndex<2>>]>;
154 Intrinsic <[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [ImmArg<ArgIndex<2>>]>;
188 [IntrNoMem, ImmArg<ArgIndex<2>>, ImmArg<ArgIndex<3>>]>;
192 [IntrNoMem, ImmArg<ArgIndex<2>>]>;
195 [IntrNoMem, ImmArg<ArgIndex<2>>, ImmArg<ArgIndex<3>>]>;
236 [IntrInaccessibleMemOnly, ImmArg<ArgIndex<0>>]>;
659 …DefaultAttrsIntrinsic<[llvm_v16i8_ty],[llvm_v16i8_ty, llvm_i32_ty], [IntrNoMem, ImmArg<ArgIndex<1>…
663 …DefaultAttrsIntrinsic<[llvm_v16i8_ty],[llvm_v16i8_ty, llvm_i32_ty], [IntrNoMem, ImmArg<ArgIndex<1>…
[all …]
H A DIntrinsicsRISCVXCV.td39 [IntrNoMem, IntrWillReturn, IntrSpeculatable, ImmArg<ArgIndex<2>>]>;
43 [IntrNoMem, IntrWillReturn, IntrSpeculatable, ImmArg<ArgIndex<3>>]>;
60 ImmArg<ArgIndex<1>>, ImmArg<ArgIndex<2>>]>;
H A DIntrinsicsHexagon.td54 [IntrArgMemOnly, ImmArg<ArgIndex<3>>]>;
60 [IntrWriteMem, ImmArg<ArgIndex<3>>]>;
66 [IntrWriteMem, ImmArg<ArgIndex<3>>]>;
268 ImmArg<ArgIndex<2>>]>;
288 ImmArg<ArgIndex<2>>],
320 ImmArg<ArgIndex<2>>]>;
344 ImmArg<ArgIndex<2>>],
H A DIntrinsicsRISCVXTHead.td20 [ImmArg<ArgIndex<5>>, IntrNoMem]>, RISCVVIntrinsic {
H A DIntrinsicsNVVM.td45 // 3. Annotate all flag arguments with ImmArg<ArgIdx<>>.
775 ImmArg<ArgIndex<0>>]>;
1083 [IntrNoMem, IntrSpeculatable, ImmArg<ArgIndex<2>>]>;
1103 [IntrNoMem, IntrSpeculatable, ImmArg<ArgIndex<1>>]>;
1347 [IntrNoCallback, IntrArgMemOnly, ImmArg<ArgIndex<1>>,
1381 Intrinsic<[], [llvm_i32_ty], [ImmArg<ArgIndex<0>>]>;
1391 Intrinsic<[], [llvm_i32_ty], [ImmArg<ArgIndex<0>>]>;
1394 Intrinsic<[], [llvm_i32_ty], [ImmArg<ArgIndex<0>>]>;
1881 …: Intrinsic<[], [llvm_i64_ty], [IntrConvergent, ImmArg<ArgIndex<0>>], "llvm.nvvm.wgmma.wait_group.…
1999 ImmArg<ArgIndex<0>>, Range<ArgIndex<0>, 24, 257>]>;
[all …]
/freebsd/contrib/llvm-project/llvm/utils/TableGen/Basic/
H A DCodeGenIntrinsics.h129 ImmArg, enumerator
H A DCodeGenIntrinsics.cpp433 addArgAttribute(ArgNo, ImmArg); in setProperty()
464 ArgAttribute Val{ImmArg, 0, 0}; in isParamImmArg()
H A DIntrinsicEmitter.cpp490 case CodeGenIntrinsic::ImmArg: in getArgAttrEnumName()
/freebsd/contrib/llvm-project/llvm/lib/Target/BPF/
H A DBPFPreserveStaticOffset.cpp237 Call->addParamAttr(I, Attribute::ImmArg); in makeGEPAndLoad()
260 Call->addParamAttr(I, Attribute::ImmArg); in makeGEPAndStore()
/freebsd/contrib/llvm-project/clang/lib/Sema/
H A DSemaARM.cpp745 unsigned ImmArg = TheCall->getNumArgs() - 1; in CheckNeonBuiltinFunctionCall() local
747 if (SemaRef.BuiltinConstantArg(TheCall, ImmArg, Result)) in CheckNeonBuiltinFunctionCall()
753 << TheCall->getArg(ImmArg)->getSourceRange(); in CheckNeonBuiltinFunctionCall()
/freebsd/contrib/llvm-project/llvm/lib/FuzzMutate/
H A DRandomIRBuilder.cpp333 return !Callee->hasParamAttribute(OperandNo, Attribute::ImmArg); in isCompatibleReplacement()

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