| /freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64MIPeepholeOpt.cpp | 212 T &Imm1) -> std::optional<OpcodePair> { in visitAND() argument
213 if (splitBitmaskImm(Imm, RegSize, Imm0, Imm1)) in visitAND()
218 unsigned Imm1, Register SrcReg, Register NewTmpReg, in visitAND()
227 .addImm(Imm1); in visitAND()
361 static bool splitAddSubImm(T Imm, unsigned RegSize, T &Imm0, T &Imm1) { in splitAddSubImm() argument
376 Imm1 = Imm & 0xfff; in splitAddSubImm()
406 T &Imm1) -> std::optional<OpcodePair> { in visitADDSUB() argument
407 if (splitAddSubImm(Imm, RegSize, Imm0, Imm1)) in visitADDSUB()
409 if (splitAddSubImm(-Imm, RegSize, Imm0, Imm1)) in visitADDSUB()
414 unsigned Imm1, Register SrcReg, Register NewTmpReg, in visitADDSUB()
[all …]
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| H A D | AArch64ExpandImm.cpp | 321 uint64_t Imm1 = MaybeDecomposition->first; in tryOrrOfLogicalImmediates() local
325 bool Imm1Success = AArch64_AM::processLogicalImmediate(Imm1, 64, Encoding1); in tryOrrOfLogicalImmediates()
347 uint64_t Imm1 = MaybeDecomposition->first; in tryAndOfLogicalImmediates() local
351 bool Imm1Success = AArch64_AM::processLogicalImmediate(~Imm1, 64, Encoding1); in tryAndOfLogicalImmediates()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Mips/MCTargetDesc/ |
| H A D | MipsTargetStreamer.h | 130 void emitII(unsigned Opcode, int16_t Imm1, int16_t Imm2, SMLoc IDLoc,
148 int16_t Imm0, int16_t Imm1, int16_t Imm2, SMLoc IDLoc,
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| H A D | MipsTargetStreamer.cpp | 215 void MipsTargetStreamer::emitII(unsigned Opcode, int16_t Imm1, int16_t Imm2, in emitII() argument
219 TmpInst.addOperand(MCOperand::createImm(Imm1)); in emitII()
264 MCRegister Reg1, int16_t Imm0, int16_t Imm1, in emitRRIII() argument
272 TmpInst.addOperand(MCOperand::createImm(Imm1)); in emitRRIII()
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| /freebsd/contrib/llvm-project/llvm/lib/ExecutionEngine/JITLink/ |
| H A D | aarch32.cpp | 112 uint32_t Imm1 = (Value >> 11) & 0x01; in encodeImmMovtT1MovwT3() local
115 return HalfWords{Imm1 << 10 | Imm4, Imm3 << 12 | Imm8}; in encodeImmMovtT1MovwT3()
125 uint32_t Imm1 = (Hi >> 10) & 0x01; in decodeImmMovtT1MovwT3() local
128 uint32_t Imm16 = Imm4 << 12 | Imm1 << 11 | Imm3 << 8 | Imm8; in decodeImmMovtT1MovwT3()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/ |
| H A D | PPCMIPeephole.cpp | 1684 int16_t Imm1 = 0, NewImm1 = 0, Imm2 = 0, NewImm2 = 0; in eliminateRedundantCompare() local
1748 NewImm1 = Imm1 = (int16_t)CMPI1->getOperand(2).getImm(); in eliminateRedundantCompare()
1753 if (Imm1 != Imm2 && (!isEqOrNe(BI2) || !isEqOrNe(BI1))) { in eliminateRedundantCompare()
1754 int Diff = Imm1 - Imm2; in eliminateRedundantCompare()
1827 if (NewImm1 != Imm1) { in eliminateRedundantCompare()
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| H A D | PPCInstrInfo.cpp | 3284 static unsigned selectReg(int64_t Imm1, int64_t Imm2, unsigned CompareOpc, in selectReg() argument
3292 return Imm1 < Imm2 ? TrueReg : FalseReg; in selectReg()
3294 return Imm1 > Imm2 ? TrueReg : FalseReg; in selectReg()
3296 return Imm1 == Imm2 ? TrueReg : FalseReg; in selectReg()
3304 return (uint64_t)Imm1 < (uint64_t)Imm2 ? TrueReg : FalseReg; in selectReg()
3306 return (uint64_t)Imm1 > (uint64_t)Imm2 ? TrueReg : FalseReg; in selectReg()
3308 return Imm1 == Imm2 ? TrueReg : FalseReg; in selectReg()
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| /freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/ |
| H A D | FastISel.h | 418 uint64_t Imm1, uint64_t Imm2);
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| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | FastISel.cpp | 2092 uint64_t Imm1, uint64_t Imm2) { in fastEmitInst_rii() argument
2101 .addImm(Imm1) in fastEmitInst_rii()
2106 .addImm(Imm1) in fastEmitInst_rii()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
| H A D | HexagonConstPropagation.cpp | 2603 bool Imm1 = Src1.isImm(), Imm2 = Src2.isImm(); in evaluateHexCompare2() local
2613 } else if (Imm1) { in evaluateHexCompare2()
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| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/ |
| H A D | CombinerHelper.cpp | 1781 Register Imm1 = MI.getOperand(2).getReg(); in matchPtrAddImmedChain() local
1782 auto MaybeImmVal = getIConstantVRegValWithLookThrough(Imm1, MRI); in matchPtrAddImmedChain()
1860 Register Imm1 = MI.getOperand(2).getReg(); in matchShiftImmedChain() local
1861 auto MaybeImmVal = getIConstantVRegValWithLookThrough(Imm1, MRI); in matchShiftImmedChain()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/ARM/AsmParser/ |
| H A D | ARMAsmParser.cpp | 5530 int64_t Imm1, Imm2; in parseModImm() local
5568 Imm1 = CE->getValue(); in parseModImm()
5569 int Enc = ARM_AM::getSOImmVal(Imm1); in parseModImm()
5599 if (Imm1 & ~0xFF) in parseModImm()
5624 Operands.push_back(ARMOperand::CreateModImm(Imm1, Imm2, S, Ex2, *this)); in parseModImm()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/LoongArch/ |
| H A D | LoongArchISelLowering.cpp | 3544 unsigned Imm1 = Op2->getAsZExtVal(); in lowerINTRINSIC_VOID() local
3546 if (!isUInt<5>(Imm1) || !isInt<12>(Imm2)) in lowerINTRINSIC_VOID()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86ISelLowering.cpp | 58658 unsigned Imm1 = Ops[1].getConstantOperandVal(2); in combineConcatVectorOps() local
58660 if ((Imm0 & 0x88) == 0 && (Imm1 & 0x88) == 0) { in combineConcatVectorOps()
58661 int Mask[4] = {(int)(Imm0 & 0x03), (int)((Imm0 >> 4) & 0x3), (int)(Imm1 & 0x03), in combineConcatVectorOps()
58662 (int)((Imm1 >> 4) & 0x3)}; in combineConcatVectorOps()
58680 unsigned Imm1 = Ops[1].getConstantOperandVal(2); in combineConcatVectorOps() local
58682 ((Imm1 & 1) << 4) | ((Imm1 & 2) << 5) | 0x80; in combineConcatVectorOps()
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