| /freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64MIPeepholeOpt.cpp | 206 T &Imm1) -> std::optional<OpcodePair> { in visitAND() argument
207 if (splitBitmaskImm(Imm, RegSize, Imm0, Imm1)) in visitAND()
212 unsigned Imm1, Register SrcReg, Register NewTmpReg, in visitAND()
221 .addImm(Imm1); in visitAND()
332 static bool splitAddSubImm(T Imm, unsigned RegSize, T &Imm0, T &Imm1) { in splitAddSubImm() argument
347 Imm1 = Imm & 0xfff; in splitAddSubImm()
377 T &Imm1) -> std::optional<OpcodePair> { in visitADDSUB() argument
378 if (splitAddSubImm(Imm, RegSize, Imm0, Imm1)) in visitADDSUB()
380 if (splitAddSubImm(-Imm, RegSize, Imm0, Imm1)) in visitADDSUB()
385 unsigned Imm1, Register SrcReg, Register NewTmpReg, in visitADDSUB()
[all …]
|
| H A D | AArch64ExpandImm.cpp | 321 uint64_t Imm1 = MaybeDecomposition->first; in tryOrrOfLogicalImmediates() local
325 bool Imm1Success = AArch64_AM::processLogicalImmediate(Imm1, 64, Encoding1); in tryOrrOfLogicalImmediates()
347 uint64_t Imm1 = MaybeDecomposition->first; in tryAndOfLogicalImmediates() local
351 bool Imm1Success = AArch64_AM::processLogicalImmediate(~Imm1, 64, Encoding1); in tryAndOfLogicalImmediates()
|
| /freebsd/contrib/llvm-project/llvm/lib/ExecutionEngine/JITLink/ |
| H A D | aarch32.cpp | 109 /// Imm4:Imm1:Imm3:Imm8 -> [ 00000:i:000000:Imm4, 0:Imm3:0000:Imm8 ]
113 uint32_t Imm1 = (Value >> 11) & 0x01; in encodeRegMovtT1MovwT3()
116 return HalfWords{Imm1 << 10 | Imm4, Imm3 << 12 | Imm8}; in encodeRegMovtT1MovwT3()
122 /// [ 00000:i:000000:Imm4, 0:Imm3:0000:Imm8 ] -> Imm4:Imm1:Imm3:Imm8 in decodeRegMovtT1MovwT3()
126 uint32_t Imm1 = (Hi >> 10) & 0x01;
129 uint32_t Imm16 = Imm4 << 12 | Imm1 << 11 | Imm3 << 8 | Imm8;
88 uint32_t Imm1 = (Value >> 11) & 0x01; encodeImmMovtT1MovwT3() local
101 uint32_t Imm1 = (Hi >> 10) & 0x01; decodeImmMovtT1MovwT3() local
|
| /freebsd/contrib/llvm-project/llvm/lib/Target/Mips/ |
| H A D | MipsTargetStreamer.h | 123 void emitII(unsigned Opcode, int16_t Imm1, int16_t Imm2, SMLoc IDLoc,
140 int16_t Imm1, int16_t Imm2, SMLoc IDLoc,
|
| /freebsd/contrib/llvm-project/llvm/lib/Target/Mips/MCTargetDesc/ |
| H A D | MipsTargetStreamer.cpp | 204 void MipsTargetStreamer::emitII(unsigned Opcode, int16_t Imm1, int16_t Imm2, in emitII() argument
208 TmpInst.addOperand(MCOperand::createImm(Imm1)); in emitII()
252 unsigned Reg1, int16_t Imm0, int16_t Imm1, in emitRRIII() argument
260 TmpInst.addOperand(MCOperand::createImm(Imm1)); in emitRRIII()
|
| /freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/ |
| H A D | PPCMIPeephole.cpp | 1680 int16_t Imm1 = 0, NewImm1 = 0, Imm2 = 0, NewImm2 = 0; in eliminateRedundantCompare() local
1744 NewImm1 = Imm1 = (int16_t)CMPI1->getOperand(2).getImm(); in eliminateRedundantCompare()
1749 if (Imm1 != Imm2 && (!isEqOrNe(BI2) || !isEqOrNe(BI1))) { in eliminateRedundantCompare()
1750 int Diff = Imm1 - Imm2; in eliminateRedundantCompare()
1823 if (NewImm1 != Imm1) { in eliminateRedundantCompare()
|
| H A D | PPCInstrInfo.cpp | 3253 static unsigned selectReg(int64_t Imm1, int64_t Imm2, unsigned CompareOpc, in selectReg() argument
3261 return Imm1 < Imm2 ? TrueReg : FalseReg; in selectReg()
3263 return Imm1 > Imm2 ? TrueReg : FalseReg; in selectReg()
3265 return Imm1 == Imm2 ? TrueReg : FalseReg; in selectReg()
3273 return (uint64_t)Imm1 < (uint64_t)Imm2 ? TrueReg : FalseReg; in selectReg()
3275 return (uint64_t)Imm1 > (uint64_t)Imm2 ? TrueReg : FalseReg; in selectReg()
3277 return Imm1 == Imm2 ? TrueReg : FalseReg; in selectReg()
|
| /freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/ |
| H A D | FastISel.h | 421 uint64_t Imm1, uint64_t Imm2);
|
| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | FastISel.cpp | 2147 uint64_t Imm1, uint64_t Imm2) { in fastEmitInst_rii() argument
2156 .addImm(Imm1) in fastEmitInst_rii()
2161 .addImm(Imm1) in fastEmitInst_rii()
|
| /freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
| H A D | HexagonConstPropagation.cpp | 2602 bool Imm1 = Src1.isImm(), Imm2 = Src2.isImm(); in evaluateHexCompare2() local
2612 } else if (Imm1) { in evaluateHexCompare2()
|
| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/ |
| H A D | CombinerHelper.cpp | 1713 Register Imm1 = MI.getOperand(2).getReg(); in matchPtrAddImmedChain() local
1714 auto MaybeImmVal = getIConstantVRegValWithLookThrough(Imm1, MRI); in matchPtrAddImmedChain()
1792 Register Imm1 = MI.getOperand(2).getReg(); in matchShiftImmedChain() local
1793 auto MaybeImmVal = getIConstantVRegValWithLookThrough(Imm1, MRI); in matchShiftImmedChain()
|
| /freebsd/contrib/llvm-project/llvm/lib/Target/ARM/AsmParser/ |
| H A D | ARMAsmParser.cpp | 5499 int64_t Imm1, Imm2; in parseModImm() local
5537 Imm1 = CE->getValue(); in parseModImm()
5538 int Enc = ARM_AM::getSOImmVal(Imm1); in parseModImm()
5568 if (Imm1 & ~0xFF) in parseModImm()
5593 Operands.push_back(ARMOperand::CreateModImm(Imm1, Imm2, S, Ex2, *this)); in parseModImm()
|
| /freebsd/contrib/llvm-project/llvm/lib/Target/LoongArch/ |
| H A D | LoongArchISelLowering.cpp | 2381 unsigned Imm1 = Op2->getAsZExtVal(); in lowerINTRINSIC_VOID() local
2383 if (!isUInt<5>(Imm1) || !isInt<12>(Imm2)) in lowerINTRINSIC_VOID()
|
| /freebsd/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86ISelLowering.cpp | 56369 unsigned Imm1 = Ops[1].getConstantOperandVal(2); in combineConcatVectorOps() local
56371 if ((Imm0 & 0x88) == 0 && (Imm1 & 0x88) == 0) { in combineConcatVectorOps()
56372 int Mask[4] = {(int)(Imm0 & 0x03), (int)((Imm0 >> 4) & 0x3), (int)(Imm1 & 0x03), in combineConcatVectorOps()
56373 (int)((Imm1 >> 4) & 0x3)}; in combineConcatVectorOps()
56391 unsigned Imm1 = Ops[1].getConstantOperandVal(2); in combineConcatVectorOps() local
56393 ((Imm1 & 1) << 4) | ((Imm1 & 2) << 5) | 0x80; in combineConcatVectorOps()
|