| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | FastISel.cpp | 391 EVT IdxVT = EVT::getEVT(Idx->getType(), /*HandleUnknown=*/false); in getRegForGEPIndex() local
392 if (IdxVT.bitsLT(PtrVT)) { in getRegForGEPIndex()
393 IdxN = fastEmit_r(IdxVT.getSimpleVT(), PtrVT, ISD::SIGN_EXTEND, IdxN); in getRegForGEPIndex()
394 } else if (IdxVT.bitsGT(PtrVT)) { in getRegForGEPIndex()
396 fastEmit_r(IdxVT.getSimpleVT(), PtrVT, ISD::TRUNCATE, IdxN); in getRegForGEPIndex()
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| H A D | SelectionDAGBuilder.cpp | 4992 EVT IdxVT = Index.getValueType(); in visitMaskedScatter() local
4993 EVT EltTy = IdxVT.getVectorElementType(); in visitMaskedScatter()
4994 if (TLI.shouldExtendGSIndex(IdxVT, EltTy)) { in visitMaskedScatter()
4995 EVT NewIdxVT = IdxVT.changeVectorElementType(EltTy); in visitMaskedScatter()
5111 EVT IdxVT = Index.getValueType(); in visitMaskedGather() local
5112 EVT EltTy = IdxVT.getVectorElementType(); in visitMaskedGather()
5113 if (TLI.shouldExtendGSIndex(IdxVT, EltTy)) { in visitMaskedGather()
5114 EVT NewIdxVT = IdxVT.changeVectorElementType(EltTy); in visitMaskedGather()
6453 EVT IdxVT = Index.getValueType(); in visitVectorHistogram() local
6454 EVT EltTy = IdxVT.getVectorElementType(); in visitVectorHistogram()
[all …]
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| H A D | LegalizeDAG.cpp | 5906 EVT IdxVT = Idx.getValueType(); in PromoteNode() local
5908 SDValue Factor = DAG.getConstant(NewEltsPerOldElt, SL, IdxVT); in PromoteNode()
5909 SDValue NewBaseIdx = DAG.getNode(ISD::MUL, SL, IdxVT, Idx, Factor); in PromoteNode()
5915 SDValue IdxOffset = DAG.getConstant(I, SL, IdxVT); in PromoteNode()
5916 SDValue TmpIdx = DAG.getNode(ISD::ADD, SL, IdxVT, NewBaseIdx, IdxOffset); in PromoteNode()
5953 EVT IdxVT = Idx.getValueType(); in PromoteNode() local
5956 SDValue Factor = DAG.getConstant(NewEltsPerOldElt, SDLoc(), IdxVT); in PromoteNode()
5957 SDValue NewBaseIdx = DAG.getNode(ISD::MUL, SL, IdxVT, Idx, Factor); in PromoteNode()
5964 SDValue IdxOffset = DAG.getConstant(I, SL, IdxVT); in PromoteNode()
5965 SDValue InEltIdx = DAG.getNode(ISD::ADD, SL, IdxVT, NewBaseIdx, IdxOffset); in PromoteNode()
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| H A D | TargetLowering.cpp | 10604 EVT IdxVT = Idx.getValueType(); in clampDynamicVectorIndex() local
10614 DAG.getVScale(dl, IdxVT, APInt(IdxVT.getFixedSizeInBits(), NElts)); in clampDynamicVectorIndex()
10616 SDValue Sub = DAG.getNode(SubOpcode, dl, IdxVT, VS, in clampDynamicVectorIndex()
10617 DAG.getConstant(NumSubElts, dl, IdxVT)); in clampDynamicVectorIndex()
10618 return DAG.getNode(ISD::UMIN, dl, IdxVT, Idx, Sub); in clampDynamicVectorIndex()
10621 APInt Imm = APInt::getLowBitsSet(IdxVT.getSizeInBits(), Log2_32(NElts)); in clampDynamicVectorIndex()
10622 return DAG.getNode(ISD::AND, dl, IdxVT, Idx, in clampDynamicVectorIndex()
10623 DAG.getConstant(Imm, dl, IdxVT)); in clampDynamicVectorIndex()
10626 return DAG.getNode(ISD::UMIN, dl, IdxVT, Idx, in clampDynamicVectorIndex()
10627 DAG.getConstant(MaxIndex, dl, IdxVT)); in clampDynamicVectorIndex()
[all …]
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64FastISel.cpp | 4967 EVT IdxVT = EVT::getEVT(Idx->getType(), /*HandleUnknown=*/false); in getRegForGEPIndex() local
4968 if (IdxVT.bitsLT(PtrVT)) { in getRegForGEPIndex()
4969 IdxN = emitIntExt(IdxVT.getSimpleVT(), IdxN, PtrVT, /*isZExt=*/false); in getRegForGEPIndex()
4970 } else if (IdxVT.bitsGT(PtrVT)) in getRegForGEPIndex()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86InstrAVX512.td | 1620 X86VectorVTInfo _, X86VectorVTInfo IdxVT> {
1623 defm rr: AVX512_maskable_3src_cast<opc, MRMSrcReg, _, IdxVT, (outs _.RC:$dst),
1626 (_.VT (X86VPermt2 _.RC:$src2, IdxVT.RC:$src1, _.RC:$src3)), 1>,
1630 defm rm: AVX512_maskable_3src_cast<opc, MRMSrcMem, _, IdxVT, (outs _.RC:$dst),
1633 (_.VT (X86VPermt2 _.RC:$src2, IdxVT.RC:$src1,
1641 X86VectorVTInfo _, X86VectorVTInfo IdxVT> {
1644 defm rmb: AVX512_maskable_3src_cast<opc, MRMSrcMem, _, IdxVT, (outs _.RC:$dst),
1649 IdxVT.RC:$src1,(_.VT (_.BroadcastLdFrag addr:$src3)))), 1>,
1708 X86VectorVTInfo IdxVT,
1712 (IdxVT.VT (bitconvert
[all …]
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| H A D | X86ISelLowering.cpp | 18919 MVT IdxVT = MVT::getVectorVT(IdxSVT, NumElts); in LowerINSERT_VECTOR_ELT() local
18920 if (!isTypeLegal(IdxSVT) || !isTypeLegal(IdxVT)) in LowerINSERT_VECTOR_ELT()
18924 SDValue IdxSplat = DAG.getSplatBuildVector(IdxVT, dl, IdxExt); in LowerINSERT_VECTOR_ELT()
18930 SDValue Indices = DAG.getBuildVector(IdxVT, dl, RawIndices); in LowerINSERT_VECTOR_ELT()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/ |
| H A D | RISCVISelLowering.cpp | 12171 MVT IdxVT = ConcatVT.changeVectorElementType(MVT::i16); in lowerVECTOR_INTERLEAVE() local
12174 SDValue StepVec = DAG.getStepVector(DL, IdxVT); in lowerVECTOR_INTERLEAVE()
12177 SDValue Ones = DAG.getSplatVector(IdxVT, DL, DAG.getConstant(1, DL, XLenVT)); in lowerVECTOR_INTERLEAVE()
12180 SDValue OddMask = DAG.getNode(ISD::AND, DL, IdxVT, StepVec, Ones); in lowerVECTOR_INTERLEAVE()
12182 DL, IdxVT.changeVectorElementType(MVT::i1), OddMask, in lowerVECTOR_INTERLEAVE()
12183 DAG.getSplatVector(IdxVT, DL, DAG.getConstant(0, DL, XLenVT)), in lowerVECTOR_INTERLEAVE()
12186 SDValue VLMax = DAG.getSplatVector(IdxVT, DL, computeVLMax(VecVT, DL, DAG)); in lowerVECTOR_INTERLEAVE()
12190 SDValue Idx = DAG.getNode(ISD::SRL, DL, IdxVT, StepVec, Ones); in lowerVECTOR_INTERLEAVE()
12193 DAG.getNode(RISCVISD::ADD_VL, DL, IdxVT, Idx, VLMax, Idx, OddMask, VL); in lowerVECTOR_INTERLEAVE()
12197 SDValue TrueMask = getAllOnesMask(IdxVT, VL, DL, DAG); in lowerVECTOR_INTERLEAVE()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | SIISelLowering.cpp | 7880 EVT IdxVT = Idx.getValueType(); in lowerEXTRACT_VECTOR_ELT() local
7883 SDValue IdxMask = DAG.getConstant(NElem / 2 - 1, SL, IdxVT); in lowerEXTRACT_VECTOR_ELT()
7884 SDValue NewIdx = DAG.getNode(ISD::AND, SL, IdxVT, Idx, IdxMask); in lowerEXTRACT_VECTOR_ELT()
14319 EVT IdxVT = Idx.getValueType(); in performInsertVectorEltCombine() local
14323 SDValue IC = DAG.getConstant(I, SL, IdxVT); in performInsertVectorEltCombine()
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