| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/ |
| H A D | TargetInstrInfo.cpp | 184 unsigned Idx2) const { in commuteInstructionImpl() 192 unsigned CommutableOpIdx2 = Idx2; (void)CommutableOpIdx2; in commuteInstructionImpl() 194 CommutableOpIdx1 == Idx1 && CommutableOpIdx2 == Idx2 && in commuteInstructionImpl() 196 assert(MI.getOperand(Idx1).isReg() && MI.getOperand(Idx2).isReg() && in commuteInstructionImpl() 201 Register Reg2 = MI.getOperand(Idx2).getReg(); in commuteInstructionImpl() 204 unsigned SubReg2 = MI.getOperand(Idx2).getSubReg(); in commuteInstructionImpl() 206 bool Reg2IsKill = MI.getOperand(Idx2).isKill(); in commuteInstructionImpl() 208 bool Reg2IsUndef = MI.getOperand(Idx2).isUndef(); in commuteInstructionImpl() 210 bool Reg2IsInternal = MI.getOperand(Idx2).isInternalRead(); in commuteInstructionImpl() 216 Reg2.isPhysical() ? MI.getOperand(Idx2).isRenamable() : false; in commuteInstructionImpl() [all …]
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| H A D | ShadowStackGCLowering.cpp | 83 Type *Ty, Value *BasePtr, int Idx1, int Idx2, 304 int Idx2, const char *Name) { in CreateGEP() argument 307 ConstantInt::get(Type::getInt32Ty(Context), Idx2)}; in CreateGEP()
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| H A D | PeepholeOptimizer.cpp | 594 RecurrenceInstr(MachineInstr *MI, unsigned Idx1, unsigned Idx2) in RecurrenceInstr() argument 595 : MI(MI), CommutePair(std::make_pair(Idx1, Idx2)) {} in RecurrenceInstr()
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| /freebsd/contrib/llvm-project/compiler-rt/lib/fuzzer/ |
| H A D | FuzzerCorpus.h | 376 uint32_t Idx2 = RareFeatures[i]; in AddRareFeature() 377 if (GlobalFeatureFreqs[Idx2] >= in AddRareFeature() 380 MostAbundantRareFeatureIndices[0] = Idx2; in AddRareFeature() 375 uint32_t Idx2 = RareFeatures[i]; AddRareFeature() local
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| /freebsd/contrib/llvm-project/llvm/utils/TableGen/Common/ |
| H A D | CodeGenRegisters.cpp | 1466 CodeGenSubRegIndex *Idx2 = I2.first; in computeComposites() local 1477 Idx1->addComposite(Idx2, Idx3, getHwModes())) { in computeComposites() 1479 if (!UserDefined.contains({Idx1, Idx2}) || in computeComposites() 1480 agree(compose(Idx1, Idx2), SubRegAction.at(Idx3))) in computeComposites() 1482 " and " + Idx2->getQualifiedName() + in computeComposites() 1543 for (CodeGenSubRegIndex &Idx2 : SubRegIndices) { in computeSubRegLaneMasks() 1545 if (!Idx2.getComposites().empty()) in computeSubRegLaneMasks() 1552 assert(Idx2.LaneMask == SrcMask); in computeSubRegLaneMasks() 1555 auto C = Composites.find(&Idx2); in computeSubRegLaneMasks()
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| /freebsd/contrib/llvm-project/llvm/lib/Transforms/AggressiveInstCombine/ |
| H A D | AggressiveInstCombine.cpp | 572 Value *Idx2 = std::next(GEP->idx_begin())->get(); in tryToRecognizeTableBasedCttz() local 577 if (!match(Idx2, m_ZExtOrSelf( in tryToRecognizeTableBasedCttz()
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| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | LegalizeVectorTypes.cpp | 3093 unsigned Idx2, bool /*Unused*/) { in SplitVecRes_VECTOR_SHUFFLE() argument 3096 Inputs[Idx2]->getOpcode() == ISD::BUILD_VECTOR) in SplitVecRes_VECTOR_SHUFFLE() 3097 Output = BuildVector(Inputs[Idx1], Inputs[Idx2], Mask); in SplitVecRes_VECTOR_SHUFFLE() 3100 Inputs[Idx2], Mask); in SplitVecRes_VECTOR_SHUFFLE() 3103 TmpInputs[Idx2]->getOpcode() == ISD::BUILD_VECTOR) in SplitVecRes_VECTOR_SHUFFLE() 3104 Output = BuildVector(TmpInputs[Idx1], TmpInputs[Idx2], Mask); in SplitVecRes_VECTOR_SHUFFLE() 3107 TmpInputs[Idx2], Mask); in SplitVecRes_VECTOR_SHUFFLE()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/ |
| H A D | RISCVTargetTransformInfo.cpp | 460 [&](ArrayRef<int> RegMask, unsigned Idx1, unsigned Idx2, bool NewReg) { in costShuffleViaSplitting() argument 535 [&](ArrayRef<int> RegMask, unsigned Idx1, unsigned Idx2, bool NewReg) { in costShuffleViaVRegSplitting() argument
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| H A D | RISCVISelLowering.cpp | 5447 [&](ArrayRef<int> SrcSubMask, unsigned Idx1, unsigned Idx2, bool NewReg) { in lowerShuffleViaVRegSplitting() argument 5450 Operands.back().emplace_back(Idx1, Idx2, SmallVector<int>(SrcSubMask)); in lowerShuffleViaVRegSplitting() 5465 unsigned Idx2 = std::get<1>(P); in lowerShuffleViaVRegSplitting() local 5467 if (Idx2 != UINT_MAX) in lowerShuffleViaVRegSplitting() 5493 const auto &[Idx1, Idx2, _] = Data[I]; in lowerShuffleViaVRegSplitting() 5503 if (Idx2 != UINT_MAX) { in lowerShuffleViaVRegSplitting() 5504 SDValue &V = Values.try_emplace(Idx2).first->getSecond(); in lowerShuffleViaVRegSplitting() 5506 V = ExtractValue(Idx2 >= NumOfSrcRegs ? V2 : V1, in lowerShuffleViaVRegSplitting() 5507 (Idx2 % NumOfSrcRegs) * NumOpElts); in lowerShuffleViaVRegSplitting() 5511 for (const auto &[Idx1, Idx2, Mask] : Data) { in lowerShuffleViaVRegSplitting() [all …]
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| /freebsd/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86InstrInfo.cpp | 7404 unsigned Idx2 = CommuteAnyOperandIndex; in commuteOperandsForFold() local 7405 if (!findCommutedOpIndices(MI, Idx1, Idx2)) in commuteOperandsForFold() 7411 Register Reg2 = MI.getOperand(Idx2).getReg(); in commuteOperandsForFold() 7413 bool Tied2 = 0 == MI.getDesc().getOperandConstraint(Idx2, MCOI::TIED_TO); in commuteOperandsForFold() 7420 return commuteInstruction(MI, false, Idx1, Idx2) ? Idx2 : Idx1; in commuteOperandsForFold()
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| /freebsd/contrib/llvm-project/llvm/lib/Transforms/InstCombine/ |
| H A D | InstructionCombining.cpp | 3330 Value *Idx1, *Idx2; in visitGetElementPtrInst() local 3332 m_OneUse(m_AddLike(m_Value(Idx1), m_Value(Idx2))))) { in visitGetElementPtrInst() 3345 NewPtr, Idx2, "", NWFlags)); in visitGetElementPtrInst()
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| /freebsd/contrib/llvm-project/clang/lib/AST/ |
| H A D | Expr.cpp | 4278 auto Idx2 = Array2->getIdx(); in isSameComparisonOperand() local 4280 const auto Integer2 = dyn_cast<IntegerLiteral>(Idx2); in isSameComparisonOperand() 4286 if (!isSameComparisonOperand(Idx1, Idx2)) in isSameComparisonOperand()
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| /freebsd/contrib/llvm-project/llvm/lib/Transforms/Vectorize/ |
| H A D | SLPVectorizer.cpp | 2293 int Idx2 = Ex2Idx->getZExtValue(); in getShallowScore() local 2294 int Dist = Idx2 - Idx1; in getShallowScore() 6562 std::optional<unsigned> Idx2 = getElementIndex(IE2); in areTwoInsertFromSameBuildVector() local 6563 if (Idx1 == std::nullopt || Idx2 == std::nullopt) in areTwoInsertFromSameBuildVector() 6577 unsigned Idx1 = getElementIndex(IE1).value_or(*Idx2); in areTwoInsertFromSameBuildVector() 6586 unsigned Idx2 = getElementIndex(IE2).value_or(*Idx1); in areTwoInsertFromSameBuildVector() local 6587 IsReusedIdx |= ReusedIdx.test(Idx2); in areTwoInsertFromSameBuildVector() 6588 ReusedIdx.set(Idx2); in areTwoInsertFromSameBuildVector() 14408 unsigned Idx2 = *getElementIndex(IE2); in isFirstInsertElement() local 14417 getElementIndex(I1).value_or(Idx2) != Idx2) in isFirstInsertElement()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | SIISelLowering.cpp | 15481 SDValue Idx2 = FMAOp1.getOperand(1); in performFMACombine() local 15483 if (Idx1 != Op2.getOperand(1) || Idx2 != FMAOp2.getOperand(1) || in performFMACombine() 15485 Idx1 == Idx2) in performFMACombine()
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