| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | LegalizeFloatTypes.cpp | 2657 EVT IVT = EVT::getIntegerVT(*DAG.getContext(), OpVT.getSizeInBits()); in PromoteFloatOp_BITCAST() local
2659 IVT, Promoted); in PromoteFloatOp_BITCAST()
2766 EVT IVT = EVT::getIntegerVT(*DAG.getContext(), VT.getSizeInBits()); in PromoteFloatOp_STORE() local
2770 IVT, Promoted); in PromoteFloatOp_STORE()
2784 EVT IVT = EVT::getIntegerVT(*DAG.getContext(), VT.getSizeInBits()); in PromoteFloatOp_ATOMIC_STORE() local
2787 DL, IVT, Promoted); in PromoteFloatOp_ATOMIC_STORE()
2789 return DAG.getAtomic(ISD::ATOMIC_STORE, DL, IVT, ST->getChain(), NewVal, in PromoteFloatOp_ATOMIC_STORE()
2935 EVT IVT = EVT::getIntegerVT(*DAG.getContext(), in PromoteFloatRes_BITCAST() local
2937 SDValue Cast = DAG.getBitcast(IVT, N->getOperand(0)); in PromoteFloatRes_BITCAST()
2946 EVT IVT = EVT::getIntegerVT(*DAG.getContext(), in PromoteFloatRes_FREEZE() local
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| H A D | LegalizeDAG.cpp | 1638 EVT IVT = EVT::getIntegerVT(*DAG.getContext(), NumBits); in getSignAsIntValue() local
1640 if (TLI.isTypeLegal(IVT)) { in getSignAsIntValue()
1641 State.IntValue = DAG.getNode(ISD::BITCAST, DL, IVT, Value); in getSignAsIntValue()
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| /freebsd/stand/i386/btx/btx/ |
| H A D | btx.S | 274 lidt ivtdesc # Set IVT
577 lidt ivtdesc # Set IVT
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| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/ |
| H A D | TargetLoweringBase.cpp | 1381 MVT IVT = (MVT::SimpleValueType)IntReg; in computeRegisterProperties() local
1382 if (isTypeLegal(IVT)) { in computeRegisterProperties()
1387 ValueTypeActions.setTypeAction(IVT, TypePromoteInteger); in computeRegisterProperties()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/NVPTX/ |
| H A D | NVPTXISelLowering.cpp | 5659 MVT IVT = MVT::getIntegerVT(VectorBits); in PerformEXTRACTCombine() local
5667 ISD::SRA, DL, IVT, DCI.DAG.getNode(ISD::BITCAST, DL, IVT, Vector), in PerformEXTRACTCombine()
5668 DCI.DAG.getConstant(Index->getZExtValue() * EltBits, DL, IVT))); in PerformEXTRACTCombine()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/WebAssembly/ |
| H A D | WebAssemblyISelLowering.cpp | 2447 MVT IVT = VT.changeVectorElementType(MVT::i16); in LowerBUILD_VECTOR() local
2451 SDValue Res = DAG.getNode(ISD::BUILD_VECTOR, SDLoc(), IVT, NewOps); in LowerBUILD_VECTOR()
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| /freebsd/contrib/llvm-project/clang/lib/Sema/ |
| H A D | SemaInit.cpp | 2023 const VectorType *IVT = IType->castAs<VectorType>(); in CheckVectorType() local
2024 unsigned numIElts = IVT->getNumElements(); in CheckVectorType()
2030 IVT->getVectorKind()); in CheckVectorType()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/ |
| H A D | RISCVISelLowering.cpp | 4265 MVT IVT = VT.changeVectorElementType(MVT::i16); in lowerBUILD_VECTOR() local
4287 SDValue Res = DAG.getNode(ISD::BUILD_VECTOR, DL, IVT, NewOps); in lowerBUILD_VECTOR()
4597 MVT IVT = VT.changeVectorElementType(MVT::i16); in lowerScalarSplat() local
4598 Passthru = DAG.getNode(ISD::BITCAST, DL, IVT, Passthru); in lowerScalarSplat()
4600 lowerScalarSplat(Passthru, Scalar, VL, IVT, DL, DAG, Subtarget); in lowerScalarSplat()
7832 MVT IVT = VT.changeVectorElementType(MVT::i16); in LowerOperation() local
7834 DAG.getNode(ISD::SPLAT_VECTOR, DL, IVT, Elt)); in LowerOperation()
19781 MVT IVT = MVT::getIntegerVT(Op0.getValueSizeInBits()); in PerformDAGCombine() local
19785 LN0->getBasePtr(), IVT, LN0->getMemOperand()); in PerformDAGCombine()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64ISelLowering.cpp | 14152 EVT IVT = VT.changeVectorElementTypeToInteger(); in LowerVECTOR_SHUFFLE() local
14153 SDValue MaskConst = DAG.getBuildVector(IVT, DL, MaskElts); in LowerVECTOR_SHUFFLE()
14154 return DAG.getBitcast(VT, DAG.getNode(AArch64ISD::BSP, DL, IVT, MaskConst, in LowerVECTOR_SHUFFLE()
14155 DAG.getBitcast(IVT, V1), in LowerVECTOR_SHUFFLE()
14156 DAG.getBitcast(IVT, V2))); in LowerVECTOR_SHUFFLE()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/ARM/ |
| H A D | ARMISelLowering.cpp | 8146 MVT IVT = (FVT == MVT::f32) ? MVT::i32 : MVT::i16; in LowerBUILD_VECTOR() local
8148 Ops.push_back(DAG.getNode(ISD::BITCAST, dl, IVT, in LowerBUILD_VECTOR()
8150 EVT VecVT = EVT::getVectorVT(*DAG.getContext(), IVT, NumElts); in LowerBUILD_VECTOR()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86ISelLowering.cpp | 7985 MVT IVT = in LowerBUILD_VECTORvXbf16() local
7991 SDValue Res = DAG.getNode(ISD::BUILD_VECTOR, SDLoc(), IVT, NewOps); in LowerBUILD_VECTORvXbf16()
18902 MVT IVT = VT.changeVectorElementTypeToInteger(); in LowerINSERT_VECTOR_ELT() local
18903 SDValue Res = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, IVT, in LowerINSERT_VECTOR_ELT()
18904 DAG.getBitcast(IVT, N0), in LowerINSERT_VECTOR_ELT()
29323 EVT IVT = VT.changeTypeToInteger(); in LowerFMINIMUM_FMAXIMUM() local
29415 SDValue XInt = DAG.getNode(ISD::BITCAST, DL, IVT, X); in LowerFMINIMUM_FMAXIMUM()
29416 SDValue ZeroCst = DAG.getConstant(0, DL, IVT); in LowerFMINIMUM_FMAXIMUM()
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