| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | FastISel.cpp | 444 bool FastISel::selectBinaryOp(const User *I, unsigned ISDOpcode) { in selectBinaryOp() argument
457 if (VT == MVT::i1 && ISD::isBitwiseLogicOp(ISDOpcode)) in selectBinaryOp()
472 fastEmit_ri_(VT.getSimpleVT(), ISDOpcode, Op1, CI->getZExtValue(), in selectBinaryOp()
491 if (ISDOpcode == ISD::SDIV && isa<BinaryOperator>(I) && in selectBinaryOp()
494 ISDOpcode = ISD::SRA; in selectBinaryOp()
498 if (ISDOpcode == ISD::UREM && isa<BinaryOperator>(I) && in selectBinaryOp()
501 ISDOpcode = ISD::AND; in selectBinaryOp()
504 Register ResultReg = fastEmit_ri_(VT.getSimpleVT(), ISDOpcode, Op0, Imm, in selectBinaryOp()
520 ISDOpcode, Op0, Op1); in selectBinaryOp()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Mips/ |
| H A D | MipsFastISel.cpp | 167 bool selectDivRem(const Instruction *I, unsigned ISDOpcode);
1921 bool MipsFastISel::selectDivRem(const Instruction *I, unsigned ISDOpcode) { in selectDivRem() argument
1931 switch (ISDOpcode) { in selectDivRem()
1959 unsigned MFOpc = (ISDOpcode == ISD::SREM || ISDOpcode == ISD::UREM) in selectDivRem()
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| /freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/ |
| H A D | FastISel.h | 510 bool selectBinaryOp(const User *I, unsigned ISDOpcode);
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| /freebsd/contrib/llvm-project/llvm/lib/Target/ARM/ |
| H A D | ARMFastISel.cpp | 194 bool SelectBinaryIntOp(const Instruction *I, unsigned ISDOpcode);
195 bool SelectBinaryFPOp(const Instruction *I, unsigned ISDOpcode);
1794 bool ARMFastISel::SelectBinaryIntOp(const Instruction *I, unsigned ISDOpcode) { in SelectBinaryIntOp() argument
1803 switch (ISDOpcode) { in SelectBinaryIntOp()
1836 bool ARMFastISel::SelectBinaryFPOp(const Instruction *I, unsigned ISDOpcode) { in SelectBinaryFPOp() argument
1857 switch (ISDOpcode) { in SelectBinaryFPOp()
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| H A D | ARMTargetTransformInfo.cpp | 1360 int ISDOpcode = TLI->InstructionOpcodeToISD(Opcode); in getArithmeticInstrCost() local
1365 switch (ISDOpcode) { in getArithmeticInstrCost()
1422 if (const auto *Entry = CostTableLookup(CostTbl, ISDOpcode, LT.second)) in getArithmeticInstrCost()
1535 if (TLI->isOperationLegalOrCustomOrPromote(ISDOpcode, LT.second)) in getArithmeticInstrCost()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/ |
| H A D | PPCFastISel.cpp | 128 bool SelectBinaryIntOp(const Instruction *I, unsigned ISDOpcode);
1256 bool PPCFastISel::SelectBinaryIntOp(const Instruction *I, unsigned ISDOpcode) { in SelectBinaryIntOp() argument
1274 switch (ISDOpcode) { in SelectBinaryIntOp()
1352 if (ISDOpcode == ISD::SUB) in SelectBinaryIntOp()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/ |
| H A D | RISCVTargetTransformInfo.cpp | 2385 unsigned ISDOpcode = TLI->InstructionOpcodeToISD(Opcode); in getArithmeticInstrCost() local
2389 TLI->getOperationAction(ISDOpcode, LT.second) == in getArithmeticInstrCost()
2391 MVT PromotedVT = TLI->getTypeToPromoteTo(ISDOpcode, LT.second); in getArithmeticInstrCost()
2427 switch (ISDOpcode) { in getArithmeticInstrCost()
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| H A D | RISCVISelLowering.cpp | 11061 static unsigned getRVVReductionOp(unsigned ISDOpcode) { in getRVVReductionOp() argument
11062 switch (ISDOpcode) { in getRVVReductionOp()
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| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/ |
| H A D | CodeGenPrepare.cpp | 2361 int ISDOpcode = TLI.InstructionOpcodeToISD(TruncUser->getOpcode()); in SinkShiftAndTruncate() local
2362 if (!ISDOpcode) in SinkShiftAndTruncate()
2371 ISDOpcode, TLI.getValueType(DL, TruncUser->getType(), true))) in SinkShiftAndTruncate()
4698 int ISDOpcode = TLI.InstructionOpcodeToISD(PromotedInst->getOpcode()); in isPromotedInstructionLegal() local
4700 if (!ISDOpcode) in isPromotedInstructionLegal()
4704 ISDOpcode, TLI.getValueType(DL, PromotedInst->getType())); in isPromotedInstructionLegal()
8181 int ISDOpcode = TLI.InstructionOpcodeToISD(ToBePromoted->getOpcode()); in shouldPromote() local
8182 if (!ISDOpcode) in shouldPromote()
8186 ISDOpcode, TLI.getValueType(DL, getTransitionType(), true)); in shouldPromote()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64FastISel.cpp | 167 bool selectRem(const Instruction *I, unsigned ISDOpcode);
4616 bool AArch64FastISel::selectRem(const Instruction *I, unsigned ISDOpcode) { in selectRem() argument
4627 switch (ISDOpcode) { in selectRem()
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| H A D | AArch64ISelLowering.cpp | 27560 static unsigned getAtomicLoad128Opcode(unsigned ISDOpcode, in getAtomicLoad128Opcode() argument
27566 assert(ISDOpcode != ISD::ATOMIC_LOAD_CLR && in getAtomicLoad128Opcode()
27568 assert(ISDOpcode != ISD::ATOMIC_LOAD_ADD && "There is no 128 bit LDADD"); in getAtomicLoad128Opcode()
27569 assert(ISDOpcode != ISD::ATOMIC_LOAD_SUB && "There is no 128 bit LDSUB"); in getAtomicLoad128Opcode()
27571 if (ISDOpcode == ISD::ATOMIC_LOAD_AND) { in getAtomicLoad128Opcode()
27592 if (ISDOpcode == ISD::ATOMIC_LOAD_OR) { in getAtomicLoad128Opcode()
27612 if (ISDOpcode == ISD::ATOMIC_SWAP) { in getAtomicLoad128Opcode()
27660 const unsigned ISDOpcode = N->getOpcode(); in ReplaceATOMIC_LOAD_128Results() local
27662 getAtomicLoad128Opcode(ISDOpcode, MemOp->getMergedOrdering()); in ReplaceATOMIC_LOAD_128Results()
27664 if (ISDOpcode == ISD::ATOMIC_LOAD_AND) { in ReplaceATOMIC_LOAD_128Results()
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