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Searched refs:IRO (Results 1 – 5 of 5) sorted by relevance

/freebsd/sys/dev/qlnx/qlnxe/
H A Decore_iro.h33 #define YSTORM_FLOW_CONTROL_MODE_OFFSET (IRO[0].base)
34 #define YSTORM_FLOW_CONTROL_MODE_SIZE (IRO[0].size)
36 #define TSTORM_PORT_STAT_OFFSET(port_id) (IRO[1].base + ((port_id) * IRO…
37 #define TSTORM_PORT_STAT_SIZE (IRO[1].size)
39 #define TSTORM_LL2_PORT_STAT_OFFSET(port_id) (IRO[2].base + ((port_id) * IRO…
40 #define TSTORM_LL2_PORT_STAT_SIZE (IRO[2].size)
42 #define USTORM_VF_PF_CHANNEL_READY_OFFSET(vf_id) (IRO[3].base + ((vf_id) * IRO[3…
43 #define USTORM_VF_PF_CHANNEL_READY_SIZE (IRO[3].size)
45 #define USTORM_FLR_FINAL_ACK_OFFSET(pf_id) (IRO[4].base + ((pf_id) * IRO[4…
46 #define USTORM_FLR_FINAL_ACK_SIZE (IRO[4].size)
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H A Decore.h902 #define IRO (p_hwfn->p_dev->iro_arr) macro
/freebsd/sys/dev/bxe/
H A Decore_fw_defs.h34 #define CSTORM_ASSERT_LIST_INDEX_OFFSET (IRO[152].base)
36 (IRO[151].base + ((assertListEntry) * IRO[151].m1))
38 (IRO[157].base + (((pfId)>>1) * IRO[157].m1) + (((pfId)&1) * \
39 IRO[157].m2))
41 (IRO[158].base + (((pfId)>>1) * IRO[158].m1) + (((pfId)&1) * \
42 IRO[158].m2))
44 (IRO[163].base + ((funcId) * IRO[163].m1))
46 (IRO[153].base + ((funcId) * IRO[153].m1))
48 (IRO[143].base + ((hcIndex) * IRO[143].m1) + ((sbId) * IRO[143].m2))
50 (IRO[142].base + (((hcIndex)>>2) * IRO[142].m1) + (((hcIndex)&3) \
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/freebsd/contrib/llvm-project/llvm/lib/Object/
H A DMachOUniversalWriter.cpp96 Slice::Slice(const IRObjectFile &IRO, uint32_t CPUType, uint32_t CPUSubType, in Slice() argument
98 : B(&IRO), CPUType(CPUType), CPUSubType(CPUSubType), in Slice()
226 Expected<Slice> Slice::create(const IRObjectFile &IRO, uint32_t Align) { in create()
227 Expected<MachoCPUTy> CPUOrErr = getMachoCPUFromTriple(IRO.getTargetTriple()); in create()
236 return Slice{IRO, CPUType, CPUSubType, std::move(ArchName), Align}; in create()
230 create(const IRObjectFile & IRO,uint32_t Align) create() argument
/freebsd/contrib/llvm-project/llvm/include/llvm/Object/
H A DMachOUniversalWriter.h45 Slice(const IRObjectFile &IRO, uint32_t CPUType, uint32_t CPUSubType,
62 static Expected<Slice> create(const IRObjectFile &IRO, uint32_t Align);