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/freebsd/contrib/llvm-project/llvm/lib/MCA/Stages/
H A DExecuteStage.cpp43 bool ExecuteStage::isAvailable(const InstRef &IR) const { in isAvailable()
44 if (Scheduler::Status S = HWS.isAvailable(IR)) { in isAvailable()
46 notifyEvent<HWStallEvent>(HWStallEvent(ET, IR)); in isAvailable()
53 Error ExecuteStage::issueInstruction(InstRef &IR) { in issueInstruction() argument
58 HWS.issueInstruction(IR, Used, Pending, Ready); in issueInstruction()
59 Instruction &IS = *IR.getInstruction(); in issueInstruction()
62 notifyReservedOrReleasedBuffers(IR, /* Reserved */ false); in issueInstruction()
64 notifyInstructionIssued(IR, Used); in issueInstruction()
66 notifyInstructionExecuted(IR); in issueInstruction()
68 if (Error S = moveToTheNextStage(IR)) in issueInstruction()
81 InstRef IR = HWS.select(); issueReadyInstructions() local
113 for (const InstRef &IR : Pending) cycleStart() local
116 for (const InstRef &IR : Ready) cycleStart() local
161 verifyInstructionEliminated(const InstRef & IR) verifyInstructionEliminated() argument
173 handleInstructionEliminated(InstRef & IR) handleInstructionEliminated() argument
186 execute(InstRef & IR) execute() argument
253 notifyInstructionIssued(const InstRef & IR,MutableArrayRef<ResourceUse> Used) const notifyInstructionIssued() argument
271 notifyReservedOrReleasedBuffers(const InstRef & IR,bool Reserved) const notifyReservedOrReleasedBuffers() argument
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H A DInOrderIssueStage.cpp25 IR.invalidate(); in clear()
31 IR = Inst; in update()
60 bool InOrderIssueStage::isAvailable(const InstRef &IR) const { in isAvailable()
64 const Instruction &Inst = *IR.getInstruction(); in isAvailable()
79 static bool hasResourceHazard(const ResourceManager &RM, const InstRef &IR) { in hasResourceHazard() argument
80 if (RM.checkAvailability(IR.getInstruction()->getDesc())) { in hasResourceHazard()
81 LLVM_DEBUG(dbgs() << "[E] Stall #" << IR << '\n'); in hasResourceHazard()
88 static unsigned findFirstWriteBackCycle(const InstRef &IR) { in findFirstWriteBackCycle() argument
89 unsigned FirstWBCycle = IR.getInstruction()->getLatency(); in findFirstWriteBackCycle()
90 for (const WriteState &WS : IR.getInstruction()->getDefs()) { in findFirstWriteBackCycle()
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H A DDispatchStage.cpp38 void DispatchStage::notifyInstructionDispatched(const InstRef &IR, in notifyInstructionDispatched() argument
41 LLVM_DEBUG(dbgs() << "[E] Instruction Dispatched: #" << IR << '\n'); in notifyInstructionDispatched()
43 HWInstructionDispatchedEvent(IR, UsedRegs, UOps)); in notifyInstructionDispatched()
46 bool DispatchStage::checkPRF(const InstRef &IR) const { in checkPRF()
48 for (const WriteState &RegDef : IR.getInstruction()->getDefs()) in checkPRF()
55 HWStallEvent(HWStallEvent::RegisterFileStall, IR)); in checkPRF()
62 bool DispatchStage::checkRCU(const InstRef &IR) const { in checkRCU()
63 const unsigned NumMicroOps = IR.getInstruction()->getNumMicroOps(); in checkRCU()
67 HWStallEvent(HWStallEvent::RetireControlUnitStall, IR)); in checkRCU()
71 bool DispatchStage::canDispatch(const InstRef &IR) const { in canDispatch()
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H A DMicroOpQueueStage.cpp22 InstRef IR = Buffer[CurrentInstructionSlotIdx]; in moveInstructions() local
23 while (IR && checkNextStage(IR)) { in moveInstructions()
24 if (llvm::Error Val = moveToTheNextStage(IR)) in moveInstructions()
28 unsigned NormalizedOpcodes = getNormalizedOpcodes(IR); in moveInstructions()
32 IR = Buffer[CurrentInstructionSlotIdx]; in moveInstructions()
46 Error MicroOpQueueStage::execute(InstRef &IR) { in execute() argument
47 Buffer[NextAvailableSlotIdx] = IR; in execute()
48 unsigned NormalizedOpcodes = getNormalizedOpcodes(IR); in execute()
H A DRetireStage.cpp36 notifyInstructionRetired(Current.IR); in cycleStart()
49 llvm::Error RetireStage::execute(InstRef &IR) { in execute() argument
50 Instruction &IS = *IR.getInstruction(); in execute()
60 void RetireStage::notifyInstructionRetired(const InstRef &IR) const { in notifyInstructionRetired()
61 LLVM_DEBUG(llvm::dbgs() << "[E] Instruction Retired: #" << IR << '\n'); in notifyInstructionRetired()
63 const Instruction &Inst = *IR.getInstruction(); in notifyInstructionRetired()
67 LSU.onInstructionRetired(IR); in notifyInstructionRetired()
71 notifyEvent<HWInstructionEvent>(HWInstructionRetiredEvent(IR, FreedRegs)); in notifyInstructionRetired()
/freebsd/contrib/llvm-project/llvm/lib/MCA/HardwareUnits/
H A DScheduler.cpp40 Scheduler::Status Scheduler::isAvailable(const InstRef &IR) { in isAvailable() argument
42 Resources->canBeDispatched(IR.getInstruction()->getUsedBuffers()); in isAvailable()
55 LSUnit::Status LSS = LSU.isAvailable(IR); in isAvailable()
71 InstRef &IR, in issueInstructionImpl() argument
73 Instruction *IS = IR.getInstruction(); in issueInstructionImpl()
82 IS->execute(IR.getSourceIndex()); in issueInstructionImpl()
87 LSU.onInstructionIssued(IR); in issueInstructionImpl()
93 IssuedSet.emplace_back(IR); in issueInstructionImpl()
95 LSU.onInstructionExecuted(IR); in issueInstructionImpl()
100 InstRef &IR, in issueInstruction() argument
124 InstRef &IR = *I; promoteToReadySet() local
160 InstRef &IR = *I; promoteToPendingSet() local
195 InstRef &IR = ReadySet[I]; select() local
212 InstRef IR = ReadySet[QueueIndex]; select() local
221 InstRef &IR = *I; updateIssuedSet() local
251 for (const InstRef &IR : make_range(PendingSet.begin(), EndIt)) { analyzeDataDependencies() local
300 dispatch(InstRef & IR) dispatch() argument
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H A DLSUnit.cpp69 unsigned LSUnit::dispatch(const InstRef &IR) { in dispatch() argument
70 const Instruction &IS = *IR.getInstruction(); in dispatch()
196 LSUnit::Status LSUnit::isAvailable(const InstRef &IR) const { in isAvailable()
197 const Instruction &IS = *IR.getInstruction(); in isAvailable()
205 void LSUnitBase::onInstructionExecuted(const InstRef &IR) { in onInstructionExecuted() argument
206 unsigned GroupID = IR.getInstruction()->getLSUTokenID(); in onInstructionExecuted()
209 It->second->onInstructionExecuted(IR); in onInstructionExecuted()
214 void LSUnitBase::onInstructionRetired(const InstRef &IR) { in onInstructionRetired() argument
215 const Instruction &IS = *IR.getInstruction(); in onInstructionRetired()
222 LLVM_DEBUG(dbgs() << "[LSUnit]: Instruction idx=" << IR.getSourceIndex() in onInstructionRetired()
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H A DRetireControlUnit.cpp43 unsigned RetireControlUnit::dispatch(const InstRef &IR) { in dispatch() argument
44 const Instruction &Inst = *IR.getInstruction(); in dispatch()
49 Queue[NextAvailableSlotIdx] = {IR, Entries, false}; in dispatch()
61 const Instruction *Inst = Current.IR.getInstruction(); in getCurrentToken()
79 Current.IR.getInstruction()->retire(); in consumeCurrentToken()
90 assert(Queue[TokenID].IR.getInstruction() && "Instruction was not dispatched!"); in onInstructionExecuted()
/freebsd/contrib/llvm-project/llvm/include/llvm/IR/
H A DPassManagerImpl.h30 IRUnitT &IR, AnalysisManagerT &AM, ExtraArgTs... ExtraArgs) { in run() argument
33 IRUnitT &IR; in run() local
37 explicit StackTraceEntry(const PassInstrumentation &PI, IRUnitT &IR) in run()
38 : PI(PI), IR(IR) {} in run()
52 printIRUnitNameForStackTrace(OS, IR); in run()
65 AM, IR, std::tuple<ExtraArgTs...>(ExtraArgs...)); in run()
69 ScopedDbgInfoFormatSetter FormatSetter(IR, UseNewDbgInfoFormat); in run()
71 StackTraceEntry Entry(PI, IR); in run()
78 if (!PI.runBeforePass<IRUnitT>(*Pass, IR)) in run()
81 PreservedAnalyses PassPA = Pass->run(IR, AM, ExtraArgs...); in run()
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H A DPassManager.h122 getAnalysisResultUnpackTuple(AnalysisManagerT &AM, IRUnitT &IR, in getAnalysisResultUnpackTuple() argument
126 return AM.template getResult<PassT>(IR, std::get<Ns>(Args)...); in getAnalysisResultUnpackTuple()
137 getAnalysisResult(AnalysisManager<IRUnitT, AnalysisArgTs...> &AM, IRUnitT &IR, in getAnalysisResult() argument
140 PassT, IRUnitT>)(AM, IR, Args, in getAnalysisResult()
190 PreservedAnalyses run(IRUnitT &IR, AnalysisManagerT &AM,
229 void printIRUnitNameForStackTrace(raw_ostream &OS, const IRUnitT &IR);
232 void printIRUnitNameForStackTrace<Module>(raw_ostream &OS, const Module &IR);
241 const Function &IR);
310 bool invalidate(IRUnitT &IR, const PreservedAnalyses &PA) { in invalidate() argument
315 return invalidateImpl<ResultModelT>(PassT::ID(), IR, PA); in invalidate()
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H A DPassInstrumentation.h236 bool runBeforePass(const PassT &Pass, const IRUnitT &IR) const { in runBeforePass() argument
243 ShouldRun &= C(Pass.name(), llvm::Any(&IR)); in runBeforePass()
248 C(Pass.name(), llvm::Any(&IR)); in runBeforePass()
251 C(Pass.name(), llvm::Any(&IR)); in runBeforePass()
261 void runAfterPass(const PassT &Pass, const IRUnitT &IR, in runAfterPass() argument
265 C(Pass.name(), llvm::Any(&IR), PA); in runAfterPass()
282 void runBeforeAnalysis(const PassT &Analysis, const IRUnitT &IR) const { in runBeforeAnalysis() argument
285 C(Analysis.name(), llvm::Any(&IR)); in runBeforeAnalysis()
291 void runAfterAnalysis(const PassT &Analysis, const IRUnitT &IR) const { in runAfterAnalysis() argument
294 C(Analysis.name(), llvm::Any(&IR)); in runAfterAnalysis()
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H A DPassManagerInternal.h48 virtual PreservedAnalyses run(IRUnitT &IR, AnalysisManagerT &AM,
88 PreservedAnalyses run(IRUnitT &IR, AnalysisManagerT &AM, in run()
90 return Pass.run(IR, AM, ExtraArgs...); in run()
143 virtual bool invalidate(IRUnitT &IR, const PreservedAnalyses &PA,
257 bool invalidate(IRUnitT &IR, const PreservedAnalyses &PA,
259 return Result.invalidate(IR, PA, Inv);
277 run(IRUnitT &IR, AnalysisManager<IRUnitT, ExtraArgTs...> &AM,
317 run(IRUnitT &IR, AnalysisManager<IRUnitT, ExtraArgTs...> &AM,
320 Pass.run(IR, AM, std::forward<ExtraArgTs>(ExtraArgs)...));
/freebsd/contrib/llvm-project/llvm/include/llvm/MCA/HardwareUnits/
H A DLSUnit.h112 void onGroupIssued(const InstRef &IR, bool ShouldUpdateCriticalDep) { in onGroupIssued() argument
119 unsigned Cycles = IR.getInstruction()->getCyclesLeft(); in onGroupIssued()
121 CriticalPredecessor.IID = IR.getSourceIndex(); in onGroupIssued()
132 void onInstructionIssued(const InstRef &IR) { in onInstructionIssued() argument
137 const Instruction &IS = *IR.getInstruction(); in onInstructionIssued()
141 CriticalMemoryInstruction = IR; in onInstructionIssued()
143 CriticalMemoryInstruction = IR; in onInstructionIssued()
160 void onInstructionExecuted(const InstRef &IR) { in onInstructionExecuted() argument
166 CriticalMemoryInstruction.getSourceIndex() == IR.getSourceIndex()) { in onInstructionExecuted()
253 virtual Status isAvailable(const InstRef &IR) const = 0;
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H A DScheduler.h138 InstRef &IR,
181 /// Check if the instruction in 'IR' can be dispatched during this cycle.
185 /// IR cannot be dispatched to the Scheduler due to unavailable resources.
186 Status isAvailable(const InstRef &IR);
191 /// Returns true if instruction IR is ready to be issued to the underlying
193 /// previous call to method `isAvailable(IR)` returned `SC_AVAILABLE`.
195 /// If IR is a memory operation, then the Scheduler queries the LS unit to
198 bool dispatch(InstRef &IR);
204 InstRef &IR,
209 /// Returns true if IR ha
270 instructionCheck(const InstRef & IR) instructionCheck() argument
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/freebsd/contrib/llvm-project/llvm/lib/Passes/
H A DStandardInstrumentations.cpp141 template <typename IRUnitT> static const IRUnitT *unwrapIR(Any IR) { in unwrapIR() argument
142 const IRUnitT **IRPtr = llvm::any_cast<const IRUnitT *>(&IR); in unwrapIR()
162 const Module *unwrapModule(Any IR, bool Force = false) { in unwrapModule() argument
163 if (const auto *M = unwrapIR<Module>(IR)) in unwrapModule()
166 if (const auto *F = unwrapIR<Function>(IR)) { in unwrapModule()
173 if (const auto *C = unwrapIR<LazyCallGraph::SCC>(IR)) { in unwrapModule()
184 if (const auto *L = unwrapIR<Loop>(IR)) { in unwrapModule()
191 if (const auto *MF = unwrapIR<MachineFunction>(IR)) { in unwrapModule()
238 std::string getIRName(Any IR) { in getIRName() argument
239 if (unwrapIR<Module>(IR)) in getIRName()
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/freebsd/contrib/llvm-project/llvm/include/llvm/MCA/Stages/
H A DInOrderIssueStage.h37 InstRef IR; member
45 const InstRef &getInstruction() const { return IR; } in getInstruction()
46 InstRef &getInstruction() { return IR; } in getInstruction()
48 bool isValid() const { return (bool)IR; } in isValid()
88 bool canExecute(const InstRef &IR);
91 Error tryIssue(InstRef &IR);
103 void notifyInstructionIssued(const InstRef &IR,
105 void notifyInstructionDispatched(const InstRef &IR, unsigned Ops,
107 void notifyInstructionExecuted(const InstRef &IR);
108 void notifyInstructionRetired(const InstRef &IR,
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H A DExecuteStage.h37 Error issueInstruction(InstRef &IR);
44 Error handleInstructionEliminated(InstRef &IR);
62 bool isAvailable(const InstRef &IR) const override;
73 Error execute(InstRef &IR) override;
75 void notifyInstructionIssued(const InstRef &IR,
77 void notifyInstructionExecuted(const InstRef &IR) const;
78 void notifyInstructionPending(const InstRef &IR) const;
79 void notifyInstructionReady(const InstRef &IR) const;
83 void notifyReservedOrReleasedBuffers(const InstRef &IR, bool Reserved) const;
H A DDispatchStage.h58 bool checkRCU(const InstRef &IR) const;
59 bool checkPRF(const InstRef &IR) const;
60 bool canDispatch(const InstRef &IR) const;
61 Error dispatch(InstRef IR);
63 void notifyInstructionDispatched(const InstRef &IR,
72 bool isAvailable(const InstRef &IR) const override;
78 Error execute(InstRef &IR) override;
H A DStage.h42 virtual bool isAvailable(const InstRef &IR) const { return true; } in isAvailable() argument
58 virtual Error execute(InstRef &IR) = 0;
65 bool checkNextStage(const InstRef &IR) const { in checkNextStage() argument
66 return NextInSequence && NextInSequence->isAvailable(IR); in checkNextStage()
73 Error moveToTheNextStage(InstRef &IR) { in moveToTheNextStage() argument
74 assert(checkNextStage(IR) && "Next stage is not ready!"); in moveToTheNextStage()
75 return NextInSequence->execute(IR); in moveToTheNextStage()
H A DMicroOpQueueStage.h54 unsigned getNormalizedOpcodes(const InstRef &IR) const { in getNormalizedOpcodes() argument
57 IR.getInstruction()->getDesc().NumMicroOps); in getNormalizedOpcodes()
67 bool isAvailable(const InstRef &IR) const override { in isAvailable() argument
70 unsigned NormalizedOpcodes = getNormalizedOpcodes(IR); in isAvailable()
80 Error execute(InstRef &IR) override;
/freebsd/contrib/llvm-project/llvm/include/llvm/MCA/
H A DHWEventListener.h53 : Type(type), IR(Inst) {} in HWInstructionEvent()
59 const InstRef &IR; variable
70 HWInstructionIssuedEvent(const InstRef &IR, ArrayRef<ResourceUse> UR) in HWInstructionIssuedEvent() argument
71 : HWInstructionEvent(HWInstructionEvent::Issued, IR), UsedResources(UR) {} in HWInstructionIssuedEvent()
78 HWInstructionDispatchedEvent(const InstRef &IR, ArrayRef<unsigned> Regs, in HWInstructionDispatchedEvent() argument
80 : HWInstructionEvent(HWInstructionEvent::Dispatched, IR), in HWInstructionDispatchedEvent()
87 // the instruction descriptor of IR.
88 // The only exception is when IR declares a number of micro opcodes
99 HWInstructionRetiredEvent(const InstRef &IR, ArrayRef<unsigned> Regs) in HWInstructionRetiredEvent() argument
100 : HWInstructionEvent(HWInstructionEvent::Retired, IR), in HWInstructionRetiredEvent()
131 const InstRef &IR; global() variable
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/freebsd/contrib/llvm-project/llvm/include/llvm/Passes/
H A DStandardInstrumentations.h64 void printBeforePass(StringRef PassID, Any IR);
65 void printAfterPass(StringRef PassID, Any IR);
76 void pushPassRunDescriptor(StringRef PassID, Any IR,
79 std::string fetchDumpFilename(StringRef PassId, Any IR);
97 bool shouldRun(StringRef PassID, Any IR);
105 bool shouldRun(StringRef PassName, Any IR);
206 void saveIRBeforePass(Any IR, StringRef PassID, StringRef PassName);
208 void handleIRAfterPass(Any IR, StringRef PassID, StringRef PassName);
217 virtual void handleInitialIR(Any IR) = 0;
219 virtual void generateIRRepresentation(Any IR, StringRef PassID,
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/freebsd/share/i18n/csmapper/GB/
H A Dmapper.dir.GB.src12 ISO-IR-165EXT/UCS mapper_std GB/ISO-IR-165EXT%UCS.mps
19 ISO-IR-165/UCS mapper_parallel ISO-IR-165EXT/UCS,GB2312/UCS
28 UCS/ISO-IR-165EXT mapper_std GB/UCS%ISO-IR-165EXT.mps
36 UCS/ISO-IR-165 mapper_parallel UCS/ISO-IR-165EXT,UCS/GB2312
/freebsd/contrib/llvm-project/llvm/include/
H A Dmodule.install.modulemap15 textual header "llvm/IR/Attributes.gen"
16 textual header "llvm/IR/Attributes.inc"
20 textual header "llvm/IR/Intrinsics.gen"
21 textual header "llvm/IR/Intrinsics.inc"
25 textual header "llvm/IR/IntrinsicEnums.inc"
/freebsd/sys/contrib/device-tree/Bindings/media/
H A Dtango-ir.txt1 Sigma Designs Tango IR NEC/RC-5/RC-6 decoder (SMP86xx and SMP87xx)
7 - interrupts: spec for IR IRQ
8 - clocks: spec for IR clock (typically the crystal oscillator)

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