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Searched refs:INSERT_SUBVECTOR (Results 1 – 23 of 23) sorted by relevance

/freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DISDOpcodes.h573 INSERT_SUBVECTOR, enumerator
/freebsd/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86ISelLowering.h1262 (Op.getOpcode() == ISD::INSERT_SUBVECTOR && in isTargetCanonicalConstantNode()
1264 Op = Op.getOperand(Op.getOpcode() == ISD::INSERT_SUBVECTOR ? 1 : 0); in isTargetCanonicalConstantNode()
H A DX86ISelLowering.cpp984 setOperationAction(ISD::INSERT_SUBVECTOR, VT,Expand); in X86TargetLowering()
1650 setOperationAction(ISD::INSERT_SUBVECTOR, VT, Legal); in X86TargetLowering()
1750 setOperationAction(ISD::INSERT_SUBVECTOR, VT, Custom); in X86TargetLowering()
2005 setOperationAction(ISD::INSERT_SUBVECTOR, VT, Legal); in X86TargetLowering()
2145 setOperationAction(ISD::INSERT_SUBVECTOR, VT, Custom); in X86TargetLowering()
2271 setOperationAction(ISD::INSERT_SUBVECTOR, MVT::v32f16, Legal); in X86TargetLowering()
2309 setOperationAction(ISD::INSERT_SUBVECTOR, MVT::v16f16, Legal); in X86TargetLowering()
2338 setOperationAction(ISD::INSERT_SUBVECTOR, VT, Legal); in X86TargetLowering()
2357 setOperationAction(ISD::INSERT_SUBVECTOR, MVT::v32bf16, Legal); in X86TargetLowering()
2512 ISD::INSERT_SUBVECTOR, in X86TargetLowering()
[all …]
H A DX86ISelDAGToDAG.cpp775 if (Root->getOpcode() == ISD::INSERT_SUBVECTOR && in IsProfitableToFold()
1009 CurDAG->getNode(ISD::INSERT_SUBVECTOR, dl, VT, CurDAG->getUNDEF(VT), in PreprocessISelDAG()
1012 Res = CurDAG->getNode(ISD::INSERT_SUBVECTOR, dl, VT, Res, NarrowBCast, in PreprocessISelDAG()
1037 CurDAG->getNode(ISD::INSERT_SUBVECTOR, dl, VT, CurDAG->getUNDEF(VT), in PreprocessISelDAG()
1040 Res = CurDAG->getNode(ISD::INSERT_SUBVECTOR, dl, VT, Res, NarrowBCast, in PreprocessISelDAG()
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DLegalizeVectorTypes.cpp1086 case ISD::INSERT_SUBVECTOR: SplitVecRes_INSERT_SUBVECTOR(N, Lo, Hi); break; in SplitVectorResult()
1613 Lo = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, LoVT, Lo, SubVec, Idx); in SplitVecRes_INSERT_SUBVECTOR()
1621 Hi = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, Hi.getValueType(), Hi, SubVec, in SplitVecRes_INSERT_SUBVECTOR()
3142 case ISD::INSERT_SUBVECTOR: Res = SplitVecOp_INSERT_SUBVECTOR(N, OpNo); break; in SplitVectorOperand()
3474 DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResVT, Vec, Lo, Idx); in SplitVecOp_INSERT_SUBVECTOR()
3476 DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResVT, FirstInsertion, Hi, in SplitVecOp_INSERT_SUBVECTOR()
4322 case ISD::INSERT_SUBVECTOR: in WidenVectorResult()
4888 Oper = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, WideOpVT, in WidenVecRes_StrictFP()
4993 ISD::INSERT_SUBVECTOR, DL, WideResVT, DAG.getUNDEF(WideResVT), in WidenVecRes_OverflowOp()
4996 ISD::INSERT_SUBVECTOR, D in WidenVecRes_OverflowOp()
[all...]
H A DSelectionDAGDumper.cpp327 case ISD::INSERT_SUBVECTOR: return "insert_subvector"; in getOperationName()
H A DLegalizeVectorOps.cpp1236 Src = DAG.getNode(ISD::INSERT_SUBVECTOR, DL, SrcVT, DAG.getUNDEF(SrcVT), in ExpandANY_EXTEND_VECTOR_INREG()
1295 Src = DAG.getNode(ISD::INSERT_SUBVECTOR, DL, SrcVT, DAG.getUNDEF(SrcVT), in ExpandZERO_EXTEND_VECTOR_INREG()
H A DDAGCombiner.cpp1961 case ISD::INSERT_SUBVECTOR: return visitINSERT_SUBVECTOR(N); in visit()
23151 VecIn2 = DAG.getNode(ISD::INSERT_SUBVECTOR, DL, InVT1, in createBuildVecShuffle()
23179 VecIn2 = DAG.getNode(ISD::INSERT_SUBVECTOR, DL, InVT1, in createBuildVecShuffle()
24368 if (V.getOpcode() == ISD::INSERT_SUBVECTOR && in getSubVectorSrc()
24797 if (V.getOpcode() == ISD::INSERT_SUBVECTOR) { in visitEXTRACT_SUBVECTOR()
24936 if (V.getOpcode() == ISD::INSERT_SUBVECTOR) { in visitEXTRACT_SUBVECTOR()
25954 TLI.isOperationLegalOrCustom(ISD::INSERT_SUBVECTOR, VT)) { in visitVECTOR_SHUFFLE()
25994 return DAG.getNode(ISD::INSERT_SUBVECTOR, SDLoc(N), VT, LHS, in visitVECTOR_SHUFFLE()
26520 return DAG.getNode(ISD::INSERT_SUBVECTOR, SDLoc(N), in visitINSERT_SUBVECTOR()
26568 SDValue NewINSERT = DAG.getNode(ISD::INSERT_SUBVECTOR, SDLoc(N), in visitINSERT_SUBVECTOR()
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H A DLegalizeIntegerTypes.cpp124 case ISD::INSERT_SUBVECTOR: in PromoteIntegerResult()
1971 case ISD::INSERT_SUBVECTOR: Res = PromoteIntOp_INSERT_SUBVECTOR(N); break; in PromoteIntegerOperand()
5823 return DAG.getNode(ISD::INSERT_SUBVECTOR, dl, NOutVT, Vec, SubVec, Idx); in PromoteIntRes_INSERT_SUBVECTOR()
6096 SDValue Ext = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, PromVT, V0, V1, Idx); in PromoteIntOp_INSERT_SUBVECTOR()
6122 ResVec = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResVT, ResVec, Op, in PromoteIntOp_CONCAT_VECTORS()
H A DSelectionDAG.cpp3303 case ISD::INSERT_SUBVECTOR: { in computeKnownBits()
4955 case ISD::INSERT_SUBVECTOR: { in ComputeNumSignBits()
5256 case ISD::INSERT_SUBVECTOR: in canCreateUndefOrPoison()
7320 if (N1.getOpcode() == ISD::INSERT_SUBVECTOR && N2 == N1.getOperand(2) && in getNode()
7509 case ISD::INSERT_SUBVECTOR: { in getNode()
12694 return getNode(ISD::INSERT_SUBVECTOR, DL, WideVT, getUNDEF(WideVT), N, in WidenVector()
H A DTargetLowering.cpp877 case ISD::INSERT_SUBVECTOR: { in SimplifyMultipleUseDemandedBits()
1253 case ISD::INSERT_SUBVECTOR: { in SimplifyDemandedBits()
1424 if (Op0.getOpcode() == ISD::INSERT_SUBVECTOR && !VT.isScalableVector() && in SimplifyDemandedBits()
1439 TLO.DAG.getNode(ISD::INSERT_SUBVECTOR, dl, VT, NewAnd, in SimplifyDemandedBits()
3307 case ISD::INSERT_SUBVECTOR: { in SimplifyDemandedVectorElts()
3325 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::INSERT_SUBVECTOR, DL, VT, in SimplifyDemandedVectorElts()
H A DSelectionDAGBuilder.cpp674 return DAG.getNode(ISD::INSERT_SUBVECTOR, DL, PartVT, DAG.getUNDEF(PartVT), in widenVectorToPartType()
8083 setValue(&I, DAG.getNode(ISD::INSERT_SUBVECTOR, sdl, ResultVT, Vec, SubVec, in visitIntrinsicCall()
H A DLegalizeDAG.cpp3462 case ISD::INSERT_SUBVECTOR: in ExpandNode()
/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVISelLowering.cpp753 ISD::INSERT_SUBVECTOR, ISD::EXTRACT_SUBVECTOR, in RISCVTargetLowering()
878 setOperationAction({ISD::CONCAT_VECTORS, ISD::INSERT_SUBVECTOR, in RISCVTargetLowering()
1020 setOperationAction({ISD::CONCAT_VECTORS, ISD::INSERT_SUBVECTOR, in RISCVTargetLowering()
1073 setOperationAction({ISD::CONCAT_VECTORS, ISD::INSERT_SUBVECTOR, in RISCVTargetLowering()
1103 setOperationAction({ISD::CONCAT_VECTORS, ISD::INSERT_SUBVECTOR, in RISCVTargetLowering()
1154 setOperationAction({ISD::INSERT_SUBVECTOR, ISD::EXTRACT_SUBVECTOR}, VT, in RISCVTargetLowering()
1303 setOperationAction({ISD::CONCAT_VECTORS, ISD::INSERT_SUBVECTOR, in RISCVTargetLowering()
2736 return DAG.getNode(ISD::INSERT_SUBVECTOR, DL, VT, DAG.getUNDEF(VT), V, Zero); in convertToScalableVector()
4094 Vec = DAG.getNode(ISD::INSERT_SUBVECTOR, DL, ContainerVT, Vec, SubBV, in lowerBUILD_VECTOR()
4367 return DAG.getNode(ISD::INSERT_SUBVECTOR, D in lowerScalarInsert()
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H A DRISCVISelDAGToDAG.cpp2170 case ISD::INSERT_SUBVECTOR: { in Select()
3307 if (N.getOpcode() == ISD::INSERT_SUBVECTOR) { in findVSplat()
/freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonISelLoweringHVX.cpp133 setOperationAction(ISD::INSERT_SUBVECTOR, T, Custom); in initializeHVXLowering()
232 setOperationAction(ISD::INSERT_SUBVECTOR, T, Custom); in initializeHVXLowering()
389 setOperationAction(ISD::INSERT_SUBVECTOR, BoolV, Custom); in initializeHVXLowering()
3206 case ISD::INSERT_SUBVECTOR: return LowerHvxInsertSubvector(Op, DAG); in LowerHvxOperation()
H A DHexagonISelLowering.cpp1664 ISD::EXTRACT_SUBVECTOR, ISD::INSERT_SUBVECTOR, in HexagonTargetLowering()
1714 setOperationAction(ISD::INSERT_SUBVECTOR, NativeVT, Custom); in HexagonTargetLowering()
3365 case ISD::INSERT_SUBVECTOR: return LowerINSERT_SUBVECTOR(Op, DAG); in LowerOperation()
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64ISelLowering.cpp1102 ISD::EXTRACT_SUBVECTOR, ISD::INSERT_SUBVECTOR, in AArch64TargetLowering()
1436 setOperationAction(ISD::INSERT_SUBVECTOR, VT, Custom); in AArch64TargetLowering()
1504 setOperationAction(ISD::INSERT_SUBVECTOR, VT, Custom); in AArch64TargetLowering()
1529 setOperationAction(ISD::INSERT_SUBVECTOR, VT, Custom); in AArch64TargetLowering()
1584 setOperationAction(ISD::INSERT_SUBVECTOR, VT, Custom); in AArch64TargetLowering()
1662 setOperationAction(ISD::INSERT_SUBVECTOR, VT, Custom); in AArch64TargetLowering()
6870 case ISD::INSERT_SUBVECTOR: in LowerOperation()
11939 return DAG.getNode(ISD::INSERT_SUBVECTOR, DL, WideTy, DAG.getUNDEF(WideTy), in WidenVector()
14544 SDValue Container = DAG.getNode(ISD::INSERT_SUBVECTOR, DL, PackedVT, in LowerEXTRACT_SUBVECTOR()
14591 Lo = DAG.getNode(ISD::INSERT_SUBVECTOR, DL, HalfVT, Lo, Vec1, in LowerINSERT_SUBVECTOR()
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H A DAArch64ISelDAGToDAG.cpp4419 assert(N->getOpcode() == ISD::INSERT_SUBVECTOR && "Invalid Node!"); in trySelectCastFixedLengthToScalableVector()
4639 case ISD::INSERT_SUBVECTOR: { in Select()
/freebsd/contrib/llvm-project/llvm/include/llvm/Target/
H A DTargetSelectionDAG.td805 def vector_insert_subvec : SDNode<"ISD::INSERT_SUBVECTOR",
811 def insert_subvector : SDNode<"ISD::INSERT_SUBVECTOR", SDTSubVecInsert, []>;
/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DSIISelLowering.cpp334 case ISD::INSERT_SUBVECTOR: in SITargetLowering()
437 setOperationAction(ISD::INSERT_SUBVECTOR, in SITargetLowering()
441 setOperationAction(ISD::INSERT_SUBVECTOR, in SITargetLowering()
631 case ISD::INSERT_SUBVECTOR: in SITargetLowering()
5789 case ISD::INSERT_SUBVECTOR: in LowerOperation()
H A DAMDGPUISelLowering.cpp1813 Join = DAG.getNode(ISD::INSERT_SUBVECTOR, SL, VT, DAG.getUNDEF(VT), LoLoad, in SplitVectorLoad()
1816 HiVT.isVector() ? ISD::INSERT_SUBVECTOR : ISD::INSERT_VECTOR_ELT, SL, in SplitVectorLoad()
/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMISelLowering.cpp1033 {ISD::BUILD_VECTOR, ISD::VECTOR_SHUFFLE, ISD::INSERT_SUBVECTOR, in ARMTargetLowering()
18912 case ISD::INSERT_SUBVECTOR: return PerformInsertSubvectorCombine(N, DCI); in PerformDAGCombine()