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Searched refs:INSERT_SUBVECTOR (Results 1 – 25 of 26) sorted by relevance

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/freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DISDOpcodes.h587 INSERT_SUBVECTOR, enumerator
H A DSDPatternMatch.h578 return TernaryOpc_match<LHS, RHS, IDX>(ISD::INSERT_SUBVECTOR, Base, Sub, Idx);
H A DSelectionDAG.h962 return getNode(ISD::INSERT_SUBVECTOR, DL, Vec.getValueType(), Vec, SubVec,
/freebsd/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86ISelLowering.h1348 (Op.getOpcode() == ISD::INSERT_SUBVECTOR && in isTargetCanonicalConstantNode()
1350 Op = Op.getOperand(Op.getOpcode() == ISD::INSERT_SUBVECTOR ? 1 : 0); in isTargetCanonicalConstantNode()
H A DX86ISelLowering.cpp997 setOperationAction(ISD::INSERT_SUBVECTOR, VT,Expand); in X86TargetLowering()
1674 setOperationAction(ISD::INSERT_SUBVECTOR, VT, Legal); in X86TargetLowering()
1779 setOperationAction(ISD::INSERT_SUBVECTOR, VT, Custom); in X86TargetLowering()
2038 setOperationAction(ISD::INSERT_SUBVECTOR, VT, Legal); in X86TargetLowering()
2208 setOperationAction(ISD::INSERT_SUBVECTOR, VT, Custom); in X86TargetLowering()
2339 setOperationAction(ISD::INSERT_SUBVECTOR, MVT::v32f16, Legal); in X86TargetLowering()
2385 setOperationAction(ISD::INSERT_SUBVECTOR, MVT::v16f16, Legal); in X86TargetLowering()
2428 setOperationAction(ISD::INSERT_SUBVECTOR, VT, Legal); in X86TargetLowering()
2451 setOperationAction(ISD::INSERT_SUBVECTOR, MVT::v32bf16, Legal); in X86TargetLowering()
2642 ISD::INSERT_SUBVECTOR, in X86TargetLowering()
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H A DX86ISelDAGToDAG.cpp819 if (Root->getOpcode() == ISD::INSERT_SUBVECTOR && in IsProfitableToFold()
1053 CurDAG->getNode(ISD::INSERT_SUBVECTOR, dl, VT, CurDAG->getUNDEF(VT), in PreprocessISelDAG()
1056 Res = CurDAG->getNode(ISD::INSERT_SUBVECTOR, dl, VT, Res, NarrowBCast, in PreprocessISelDAG()
1081 CurDAG->getNode(ISD::INSERT_SUBVECTOR, dl, VT, CurDAG->getUNDEF(VT), in PreprocessISelDAG()
1084 Res = CurDAG->getNode(ISD::INSERT_SUBVECTOR, dl, VT, Res, NarrowBCast, in PreprocessISelDAG()
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DLegalizeVectorTypes.cpp780 case ISD::INSERT_SUBVECTOR: in ScalarizeVectorOperand()
1134 case ISD::INSERT_SUBVECTOR: SplitVecRes_INSERT_SUBVECTOR(N, Lo, Hi); break; in SplitVectorResult()
1681 Lo = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, LoVT, Lo, SubVec, Idx); in SplitVecRes_INSERT_SUBVECTOR()
1689 Hi = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, Hi.getValueType(), Hi, SubVec, in SplitVecRes_INSERT_SUBVECTOR()
3414 case ISD::INSERT_SUBVECTOR: Res = SplitVecOp_INSERT_SUBVECTOR(N, OpNo); break; in SplitVectorOperand()
3785 DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResVT, Vec, Lo, Idx); in SplitVecOp_INSERT_SUBVECTOR()
3787 DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResVT, FirstInsertion, Hi, in SplitVecOp_INSERT_SUBVECTOR()
4682 case ISD::INSERT_SUBVECTOR: in WidenVectorResult()
5281 Oper = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, WideOpVT, in WidenVecRes_StrictFP()
5384 ISD::INSERT_SUBVECTOR, DL, WideResVT, DAG.getUNDEF(WideResVT), in WidenVecRes_OverflowOp()
[all …]
H A DSelectionDAGDumper.cpp344 case ISD::INSERT_SUBVECTOR: return "insert_subvector"; in getOperationName()
H A DLegalizeIntegerTypes.cpp128 case ISD::INSERT_SUBVECTOR: in PromoteIntegerResult()
591 SDValue Inserted = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, WideVecVT, in PromoteIntRes_BITCAST()
2022 case ISD::INSERT_SUBVECTOR: Res = PromoteIntOp_INSERT_SUBVECTOR(N); break; in PromoteIntegerOperand()
6066 return DAG.getNode(ISD::INSERT_SUBVECTOR, dl, NOutVT, Vec, SubVec, Idx); in PromoteIntRes_INSERT_SUBVECTOR()
6360 SDValue Ext = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, PromVT, V0, V1, Idx); in PromoteIntOp_INSERT_SUBVECTOR()
6399 ResVec = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResVT, ResVec, Op, in PromoteIntOp_CONCAT_VECTORS()
H A DDAGCombiner.cpp2024 case ISD::INSERT_SUBVECTOR: return visitINSERT_SUBVECTOR(N); in visit()
25442 if (V.getOpcode() == ISD::INSERT_SUBVECTOR && in getSubVectorSrc()
25851 if (V.getOpcode() == ISD::INSERT_SUBVECTOR) { in visitEXTRACT_SUBVECTOR()
25994 if (V.getOpcode() == ISD::INSERT_SUBVECTOR) { in visitEXTRACT_SUBVECTOR()
27047 TLI.isOperationLegalOrCustom(ISD::INSERT_SUBVECTOR, VT)) { in visitVECTOR_SHUFFLE()
27612 return DAG.getNode(ISD::INSERT_SUBVECTOR, SDLoc(N), in visitINSERT_SUBVECTOR()
27665 SDValue NewINSERT = DAG.getNode(ISD::INSERT_SUBVECTOR, SDLoc(N), in visitINSERT_SUBVECTOR()
27674 if (N0.getOpcode() == ISD::INSERT_SUBVECTOR && in visitINSERT_SUBVECTOR()
27677 return DAG.getNode(ISD::INSERT_SUBVECTOR, SDLoc(N), VT, N0.getOperand(0), in visitINSERT_SUBVECTOR()
27683 if (N0.isUndef() && N1.getOpcode() == ISD::INSERT_SUBVECTOR && in visitINSERT_SUBVECTOR()
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H A DSelectionDAG.cpp3546 case ISD::INSERT_SUBVECTOR: { in computeKnownBits()
5230 case ISD::INSERT_SUBVECTOR: { in ComputeNumSignBits()
5539 case ISD::INSERT_SUBVECTOR: in canCreateUndefOrPoison()
5846 case ISD::INSERT_SUBVECTOR: { in isKnownNeverNaN()
7841 if (N1.getOpcode() == ISD::INSERT_SUBVECTOR && N2 == N1.getOperand(2) && in getNode()
8052 case ISD::INSERT_SUBVECTOR: { in getNode()
H A DTargetLowering.cpp932 case ISD::INSERT_SUBVECTOR: { in SimplifyMultipleUseDemandedBits()
1308 case ISD::INSERT_SUBVECTOR: { in SimplifyDemandedBits()
1479 if (Op0.getOpcode() == ISD::INSERT_SUBVECTOR && !VT.isScalableVector() && in SimplifyDemandedBits()
1494 TLO.DAG.getNode(ISD::INSERT_SUBVECTOR, dl, VT, NewAnd, in SimplifyDemandedBits()
3448 case ISD::INSERT_SUBVECTOR: { in SimplifyDemandedVectorElts()
3466 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::INSERT_SUBVECTOR, DL, VT, in SimplifyDemandedVectorElts()
H A DSelectionDAGBuilder.cpp671 return DAG.getNode(ISD::INSERT_SUBVECTOR, DL, PartVT, DAG.getUNDEF(PartVT), in widenVectorToPartType()
8167 setValue(&I, DAG.getNode(ISD::INSERT_SUBVECTOR, sdl, ResultVT, Vec, SubVec, in visitIntrinsicCall()
H A DLegalizeDAG.cpp3529 case ISD::INSERT_SUBVECTOR: in ExpandNode()
/freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonISelLoweringHVX.cpp135 setOperationAction(ISD::INSERT_SUBVECTOR, T, Custom); in initializeHVXLowering()
236 setOperationAction(ISD::INSERT_SUBVECTOR, T, Custom); in initializeHVXLowering()
399 setOperationAction(ISD::INSERT_SUBVECTOR, BoolV, Custom); in initializeHVXLowering()
3243 case ISD::INSERT_SUBVECTOR: return LowerHvxInsertSubvector(Op, DAG); in LowerHvxOperation()
H A DHexagonISelLowering.cpp1734 ISD::EXTRACT_SUBVECTOR, ISD::INSERT_SUBVECTOR, in HexagonTargetLowering()
1788 setOperationAction(ISD::INSERT_SUBVECTOR, NativeVT, Custom); in HexagonTargetLowering()
3387 case ISD::INSERT_SUBVECTOR: return LowerINSERT_SUBVECTOR(Op, DAG); in LowerOperation()
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64ISelLowering.cpp1144 ISD::EXTRACT_SUBVECTOR, ISD::INSERT_SUBVECTOR, in AArch64TargetLowering()
1528 setOperationAction(ISD::INSERT_SUBVECTOR, VT, Custom); in AArch64TargetLowering()
1596 setOperationAction(ISD::INSERT_SUBVECTOR, VT, Custom); in AArch64TargetLowering()
1620 setOperationAction(ISD::INSERT_SUBVECTOR, VT, Custom); in AArch64TargetLowering()
1678 setOperationAction(ISD::INSERT_SUBVECTOR, VT, Custom); in AArch64TargetLowering()
1760 setOperationAction(ISD::INSERT_SUBVECTOR, VT, Custom); in AArch64TargetLowering()
6952 Vec = DAG.getNode(ISD::INSERT_SUBVECTOR, DL, ScalableVecVT, in LowerVECTOR_COMPRESS()
6955 Mask = DAG.getNode(ISD::INSERT_SUBVECTOR, DL, ScalableMaskVT, in LowerVECTOR_COMPRESS()
6960 Passthru = DAG.getNode(ISD::INSERT_SUBVECTOR, DL, ScalableVecVT, in LowerVECTOR_COMPRESS()
7338 case ISD::INSERT_SUBVECTOR: in LowerOperation()
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H A DAArch64ISelDAGToDAG.cpp4521 assert(N->getOpcode() == ISD::INSERT_SUBVECTOR && "Invalid Node!"); in trySelectCastFixedLengthToScalableVector()
4868 case ISD::INSERT_SUBVECTOR: { in Select()
/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVISelDAGToDAG.cpp2519 case ISD::INSERT_SUBVECTOR: in Select()
3827 if (N.getOpcode() == ISD::INSERT_SUBVECTOR) { in findVSplat()
H A DRISCVISelLowering.cpp800 ISD::INSERT_SUBVECTOR, ISD::EXTRACT_SUBVECTOR, in RISCVTargetLowering()
928 setOperationAction({ISD::CONCAT_VECTORS, ISD::INSERT_SUBVECTOR, in RISCVTargetLowering()
1109 setOperationAction({ISD::CONCAT_VECTORS, ISD::INSERT_SUBVECTOR, in RISCVTargetLowering()
1160 ISD::INSERT_SUBVECTOR, ISD::EXTRACT_SUBVECTOR, in RISCVTargetLowering()
1262 setOperationAction({ISD::INSERT_SUBVECTOR, ISD::EXTRACT_SUBVECTOR}, VT, in RISCVTargetLowering()
1425 ISD::CONCAT_VECTORS, ISD::INSERT_SUBVECTOR, in RISCVTargetLowering()
7798 case ISD::INSERT_SUBVECTOR: in LowerOperation()
9601 if (ScalableOnes.getOpcode() == ISD::INSERT_SUBVECTOR && in lowerVectorMaskExt()
11439 Vec = DAG.getNode(ISD::INSERT_SUBVECTOR, DL, ExtVecVT, Vec, SubVec, in lowerINSERT_SUBVECTOR()
14986 if (ScalarV.getOpcode() == ISD::INSERT_SUBVECTOR && in combineBinOpToReduce()
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H A DRISCVInstrInfoVVLPatterns.td36 // RISC-V vector tuple type version of INSERT_SUBVECTOR/EXTRACT_SUBVECTOR.
/freebsd/contrib/llvm-project/llvm/include/llvm/Target/
H A DTargetSelectionDAG.td853 def vector_insert_subvec : SDNode<"ISD::INSERT_SUBVECTOR",
859 def insert_subvector : SDNode<"ISD::INSERT_SUBVECTOR", SDTSubVecInsert, []>;
/freebsd/contrib/llvm-project/llvm/lib/Target/LoongArch/
H A DLoongArchISelLowering.cpp357 setOperationAction(ISD::INSERT_SUBVECTOR, VT, Legal); in LoongArchTargetLowering()
2591 Vec = DAG.getNode(ISD::INSERT_SUBVECTOR, DL, ResVT, Vec, Op.getOperand(i), in lowerCONCAT_VECTORS()
4362 DAG.getNode(ISD::INSERT_SUBVECTOR, DL, VT, DAG.getUNDEF(VT), In, in ReplaceNodeResults()
/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DSIISelLowering.cpp341 case ISD::INSERT_SUBVECTOR: in SITargetLowering()
452 setOperationAction(ISD::INSERT_SUBVECTOR, in SITargetLowering()
456 setOperationAction(ISD::INSERT_SUBVECTOR, in SITargetLowering()
647 case ISD::INSERT_SUBVECTOR: in SITargetLowering()
6148 case ISD::INSERT_SUBVECTOR: in LowerOperation()
H A DAMDGPUISelLowering.cpp1870 Join = DAG.getNode(ISD::INSERT_SUBVECTOR, SL, VT, DAG.getPOISON(VT), LoLoad, in SplitVectorLoad()
1873 HiVT.isVector() ? ISD::INSERT_SUBVECTOR : ISD::INSERT_VECTOR_ELT, SL, in SplitVectorLoad()

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