1 /* 2 * Copyright (c) 2017-2018 Cavium, Inc. 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 16 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 19 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 20 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 21 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 22 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 23 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 24 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 25 * POSSIBILITY OF SUCH DAMAGE. 26 * 27 */ 28 29 #ifndef __ECORE_HSI_INIT_TOOL__ 30 #define __ECORE_HSI_INIT_TOOL__ 31 /**************************************/ 32 /* Init Tool HSI constants and macros */ 33 /**************************************/ 34 35 /* Width of GRC address in bits (addresses are specified in dwords) */ 36 #define GRC_ADDR_BITS 23 37 #define MAX_GRC_ADDR ((1 << GRC_ADDR_BITS) - 1) 38 39 /* indicates an init that should be applied to any phase ID */ 40 #define ANY_PHASE_ID 0xffff 41 42 /* Max size in dwords of a zipped array */ 43 #define MAX_ZIPPED_SIZE 8192 44 45 enum chip_ids 46 { 47 CHIP_BB, 48 CHIP_K2, 49 CHIP_E5, 50 MAX_CHIP_IDS 51 }; 52 53 enum init_modes 54 { 55 MODE_BB_A0_DEPRECATED, 56 MODE_BB, 57 MODE_K2, 58 MODE_ASIC, 59 MODE_EMUL_REDUCED, 60 MODE_EMUL_FULL, 61 MODE_FPGA, 62 MODE_CHIPSIM, 63 MODE_SF, 64 MODE_MF_SD, 65 MODE_MF_SI, 66 MODE_PORTS_PER_ENG_1, 67 MODE_PORTS_PER_ENG_2, 68 MODE_PORTS_PER_ENG_4, 69 MODE_100G, 70 MODE_E5, 71 MAX_INIT_MODES 72 }; 73 74 enum init_phases 75 { 76 PHASE_ENGINE, 77 PHASE_PORT, 78 PHASE_PF, 79 PHASE_VF, 80 PHASE_QM_PF, 81 MAX_INIT_PHASES 82 }; 83 84 enum init_split_types 85 { 86 SPLIT_TYPE_NONE, 87 SPLIT_TYPE_PORT, 88 SPLIT_TYPE_PF, 89 SPLIT_TYPE_PORT_PF, 90 SPLIT_TYPE_VF, 91 MAX_INIT_SPLIT_TYPES 92 }; 93 94 /* 95 * Binary buffer header 96 */ 97 struct bin_buffer_hdr 98 { 99 u32 offset /* buffer offset in bytes from the beginning of the binary file */; 100 u32 length /* buffer length in bytes */; 101 }; 102 103 /* 104 * binary init buffer types 105 */ 106 enum bin_init_buffer_type 107 { 108 BIN_BUF_INIT_FW_VER_INFO /* fw_ver_info struct */, 109 BIN_BUF_INIT_CMD /* init commands */, 110 BIN_BUF_INIT_VAL /* init data */, 111 BIN_BUF_INIT_MODE_TREE /* init modes tree */, 112 BIN_BUF_INIT_IRO /* internal RAM offsets */, 113 MAX_BIN_INIT_BUFFER_TYPE 114 }; 115 116 /* 117 * init array header: raw 118 */ 119 struct init_array_raw_hdr 120 { 121 u32 data; 122 #define INIT_ARRAY_RAW_HDR_TYPE_MASK 0xF /* Init array type, from init_array_types enum */ 123 #define INIT_ARRAY_RAW_HDR_TYPE_SHIFT 0 124 #define INIT_ARRAY_RAW_HDR_PARAMS_MASK 0xFFFFFFF /* init array params */ 125 #define INIT_ARRAY_RAW_HDR_PARAMS_SHIFT 4 126 }; 127 128 /* 129 * init array header: standard 130 */ 131 struct init_array_standard_hdr 132 { 133 u32 data; 134 #define INIT_ARRAY_STANDARD_HDR_TYPE_MASK 0xF /* Init array type, from init_array_types enum */ 135 #define INIT_ARRAY_STANDARD_HDR_TYPE_SHIFT 0 136 #define INIT_ARRAY_STANDARD_HDR_SIZE_MASK 0xFFFFFFF /* Init array size (in dwords) */ 137 #define INIT_ARRAY_STANDARD_HDR_SIZE_SHIFT 4 138 }; 139 140 /* 141 * init array header: zipped 142 */ 143 struct init_array_zipped_hdr 144 { 145 u32 data; 146 #define INIT_ARRAY_ZIPPED_HDR_TYPE_MASK 0xF /* Init array type, from init_array_types enum */ 147 #define INIT_ARRAY_ZIPPED_HDR_TYPE_SHIFT 0 148 #define INIT_ARRAY_ZIPPED_HDR_ZIPPED_SIZE_MASK 0xFFFFFFF /* Init array zipped size (in bytes) */ 149 #define INIT_ARRAY_ZIPPED_HDR_ZIPPED_SIZE_SHIFT 4 150 }; 151 152 /* 153 * init array header: pattern 154 */ 155 struct init_array_pattern_hdr 156 { 157 u32 data; 158 #define INIT_ARRAY_PATTERN_HDR_TYPE_MASK 0xF /* Init array type, from init_array_types enum */ 159 #define INIT_ARRAY_PATTERN_HDR_TYPE_SHIFT 0 160 #define INIT_ARRAY_PATTERN_HDR_PATTERN_SIZE_MASK 0xF /* pattern size in dword */ 161 #define INIT_ARRAY_PATTERN_HDR_PATTERN_SIZE_SHIFT 4 162 #define INIT_ARRAY_PATTERN_HDR_REPETITIONS_MASK 0xFFFFFF /* pattern repetitions */ 163 #define INIT_ARRAY_PATTERN_HDR_REPETITIONS_SHIFT 8 164 }; 165 166 /* 167 * init array header union 168 */ 169 union init_array_hdr 170 { 171 struct init_array_raw_hdr raw /* raw init array header */; 172 struct init_array_standard_hdr standard /* standard init array header */; 173 struct init_array_zipped_hdr zipped /* zipped init array header */; 174 struct init_array_pattern_hdr pattern /* pattern init array header */; 175 }; 176 177 /* 178 * init array types 179 */ 180 enum init_array_types 181 { 182 INIT_ARR_STANDARD /* standard init array */, 183 INIT_ARR_ZIPPED /* zipped init array */, 184 INIT_ARR_PATTERN /* a repeated pattern */, 185 MAX_INIT_ARRAY_TYPES 186 }; 187 188 /* 189 * init operation: callback 190 */ 191 struct init_callback_op 192 { 193 u32 op_data; 194 #define INIT_CALLBACK_OP_OP_MASK 0xF /* Init operation, from init_op_types enum */ 195 #define INIT_CALLBACK_OP_OP_SHIFT 0 196 #define INIT_CALLBACK_OP_RESERVED_MASK 0xFFFFFFF 197 #define INIT_CALLBACK_OP_RESERVED_SHIFT 4 198 u16 callback_id /* Callback ID */; 199 u16 block_id /* Blocks ID */; 200 }; 201 202 /* 203 * init operation: delay 204 */ 205 struct init_delay_op 206 { 207 u32 op_data; 208 #define INIT_DELAY_OP_OP_MASK 0xF /* Init operation, from init_op_types enum */ 209 #define INIT_DELAY_OP_OP_SHIFT 0 210 #define INIT_DELAY_OP_RESERVED_MASK 0xFFFFFFF 211 #define INIT_DELAY_OP_RESERVED_SHIFT 4 212 u32 delay /* delay in us */; 213 }; 214 215 /* 216 * init operation: if_mode 217 */ 218 struct init_if_mode_op 219 { 220 u32 op_data; 221 #define INIT_IF_MODE_OP_OP_MASK 0xF /* Init operation, from init_op_types enum */ 222 #define INIT_IF_MODE_OP_OP_SHIFT 0 223 #define INIT_IF_MODE_OP_RESERVED1_MASK 0xFFF 224 #define INIT_IF_MODE_OP_RESERVED1_SHIFT 4 225 #define INIT_IF_MODE_OP_CMD_OFFSET_MASK 0xFFFF /* Commands to skip if the modes dont match */ 226 #define INIT_IF_MODE_OP_CMD_OFFSET_SHIFT 16 227 u16 reserved2; 228 u16 modes_buf_offset /* offset (in bytes) in modes expression buffer */; 229 }; 230 231 /* 232 * init operation: if_phase 233 */ 234 struct init_if_phase_op 235 { 236 u32 op_data; 237 #define INIT_IF_PHASE_OP_OP_MASK 0xF /* Init operation, from init_op_types enum */ 238 #define INIT_IF_PHASE_OP_OP_SHIFT 0 239 #define INIT_IF_PHASE_OP_DMAE_ENABLE_MASK 0x1 /* Indicates if DMAE is enabled in this phase */ 240 #define INIT_IF_PHASE_OP_DMAE_ENABLE_SHIFT 4 241 #define INIT_IF_PHASE_OP_RESERVED1_MASK 0x7FF 242 #define INIT_IF_PHASE_OP_RESERVED1_SHIFT 5 243 #define INIT_IF_PHASE_OP_CMD_OFFSET_MASK 0xFFFF /* Commands to skip if the phases dont match */ 244 #define INIT_IF_PHASE_OP_CMD_OFFSET_SHIFT 16 245 u32 phase_data; 246 #define INIT_IF_PHASE_OP_PHASE_MASK 0xFF /* Init phase */ 247 #define INIT_IF_PHASE_OP_PHASE_SHIFT 0 248 #define INIT_IF_PHASE_OP_RESERVED2_MASK 0xFF 249 #define INIT_IF_PHASE_OP_RESERVED2_SHIFT 8 250 #define INIT_IF_PHASE_OP_PHASE_ID_MASK 0xFFFF /* Init phase ID */ 251 #define INIT_IF_PHASE_OP_PHASE_ID_SHIFT 16 252 }; 253 254 /* 255 * init mode operators 256 */ 257 enum init_mode_ops 258 { 259 INIT_MODE_OP_NOT /* init mode not operator */, 260 INIT_MODE_OP_OR /* init mode or operator */, 261 INIT_MODE_OP_AND /* init mode and operator */, 262 MAX_INIT_MODE_OPS 263 }; 264 265 /* 266 * init operation: raw 267 */ 268 struct init_raw_op 269 { 270 u32 op_data; 271 #define INIT_RAW_OP_OP_MASK 0xF /* Init operation, from init_op_types enum */ 272 #define INIT_RAW_OP_OP_SHIFT 0 273 #define INIT_RAW_OP_PARAM1_MASK 0xFFFFFFF /* init param 1 */ 274 #define INIT_RAW_OP_PARAM1_SHIFT 4 275 u32 param2 /* Init param 2 */; 276 }; 277 278 /* 279 * init array params 280 */ 281 struct init_op_array_params 282 { 283 u16 size /* array size in dwords */; 284 u16 offset /* array start offset in dwords */; 285 }; 286 287 /* 288 * Write init operation arguments 289 */ 290 union init_write_args 291 { 292 u32 inline_val /* value to write, used when init source is INIT_SRC_INLINE */; 293 u32 zeros_count /* number of zeros to write, used when init source is INIT_SRC_ZEROS */; 294 u32 array_offset /* array offset to write, used when init source is INIT_SRC_ARRAY */; 295 struct init_op_array_params runtime /* runtime array params to write, used when init source is INIT_SRC_RUNTIME */; 296 }; 297 298 /* 299 * init operation: write 300 */ 301 struct init_write_op 302 { 303 u32 data; 304 #define INIT_WRITE_OP_OP_MASK 0xF /* init operation, from init_op_types enum */ 305 #define INIT_WRITE_OP_OP_SHIFT 0 306 #define INIT_WRITE_OP_SOURCE_MASK 0x7 /* init source type, taken from init_source_types enum */ 307 #define INIT_WRITE_OP_SOURCE_SHIFT 4 308 #define INIT_WRITE_OP_RESERVED_MASK 0x1 309 #define INIT_WRITE_OP_RESERVED_SHIFT 7 310 #define INIT_WRITE_OP_WIDE_BUS_MASK 0x1 /* indicates if the register is wide-bus */ 311 #define INIT_WRITE_OP_WIDE_BUS_SHIFT 8 312 #define INIT_WRITE_OP_ADDRESS_MASK 0x7FFFFF /* internal (absolute) GRC address, in dwords */ 313 #define INIT_WRITE_OP_ADDRESS_SHIFT 9 314 union init_write_args args /* Write init operation arguments */; 315 }; 316 317 /* 318 * init operation: read 319 */ 320 struct init_read_op 321 { 322 u32 op_data; 323 #define INIT_READ_OP_OP_MASK 0xF /* init operation, from init_op_types enum */ 324 #define INIT_READ_OP_OP_SHIFT 0 325 #define INIT_READ_OP_POLL_TYPE_MASK 0xF /* polling type, from init_poll_types enum */ 326 #define INIT_READ_OP_POLL_TYPE_SHIFT 4 327 #define INIT_READ_OP_RESERVED_MASK 0x1 328 #define INIT_READ_OP_RESERVED_SHIFT 8 329 #define INIT_READ_OP_ADDRESS_MASK 0x7FFFFF /* internal (absolute) GRC address, in dwords */ 330 #define INIT_READ_OP_ADDRESS_SHIFT 9 331 u32 expected_val /* expected polling value, used only when polling is done */; 332 }; 333 334 /* 335 * Init operations union 336 */ 337 union init_op 338 { 339 struct init_raw_op raw /* raw init operation */; 340 struct init_write_op write /* write init operation */; 341 struct init_read_op read /* read init operation */; 342 struct init_if_mode_op if_mode /* if_mode init operation */; 343 struct init_if_phase_op if_phase /* if_phase init operation */; 344 struct init_callback_op callback /* callback init operation */; 345 struct init_delay_op delay /* delay init operation */; 346 }; 347 348 /* 349 * Init command operation types 350 */ 351 enum init_op_types 352 { 353 INIT_OP_READ /* GRC read init command */, 354 INIT_OP_WRITE /* GRC write init command */, 355 INIT_OP_IF_MODE /* Skip init commands if the init modes expression doesnt match */, 356 INIT_OP_IF_PHASE /* Skip init commands if the init phase doesnt match */, 357 INIT_OP_DELAY /* delay init command */, 358 INIT_OP_CALLBACK /* callback init command */, 359 MAX_INIT_OP_TYPES 360 }; 361 362 /* 363 * init polling types 364 */ 365 enum init_poll_types 366 { 367 INIT_POLL_NONE /* No polling */, 368 INIT_POLL_EQ /* init value is included in the init command */, 369 INIT_POLL_OR /* init value is all zeros */, 370 INIT_POLL_AND /* init value is an array of values */, 371 MAX_INIT_POLL_TYPES 372 }; 373 374 /* 375 * init source types 376 */ 377 enum init_source_types 378 { 379 INIT_SRC_INLINE /* init value is included in the init command */, 380 INIT_SRC_ZEROS /* init value is all zeros */, 381 INIT_SRC_ARRAY /* init value is an array of values */, 382 INIT_SRC_RUNTIME /* init value is provided during runtime */, 383 MAX_INIT_SOURCE_TYPES 384 }; 385 386 /* 387 * Internal RAM Offsets macro data 388 */ 389 struct iro 390 { 391 u32 base /* RAM field offset */; 392 u16 m1 /* multiplier 1 */; 393 u16 m2 /* multiplier 2 */; 394 u16 m3 /* multiplier 3 */; 395 u16 size /* RAM field size */; 396 }; 397 398 #endif /* __ECORE_HSI_INIT_TOOL__ */ 399