1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
3 *
4 * Copyright (c) 2009-2013 Chelsio, Inc. All rights reserved.
5 *
6 * This software is available to you under a choice of one of two
7 * licenses. You may choose to be licensed under the terms of the GNU
8 * General Public License (GPL) Version 2, available from the file
9 * COPYING in the main directory of this source tree, or the
10 * OpenIB.org BSD license below:
11 *
12 * Redistribution and use in source and binary forms, with or
13 * without modification, are permitted provided that the following
14 * conditions are met:
15 *
16 * - Redistributions of source code must retain the above
17 * copyright notice, this list of conditions and the following
18 * disclaimer.
19 * - Redistributions in binary form must reproduce the above
20 * copyright notice, this list of conditions and the following
21 * disclaimer in the documentation and/or other materials
22 * provided with the distribution.
23 *
24 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
25 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
26 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
27 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
28 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
29 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
30 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
31 * SOFTWARE.
32 */
33 #ifndef __T4_H__
34 #define __T4_H__
35
36 #include "common/t4_regs_values.h"
37 #include "common/t4_regs.h"
38 /*
39 * Fixme: Adding missing defines
40 */
41 #define SGE_PF_KDOORBELL 0x0
42 #define QID_MASK 0xffff8000U
43 #define QID_SHIFT 15
44 #define QID(x) ((x) << QID_SHIFT)
45 #define DBPRIO 0x00004000U
46 #define PIDX_MASK 0x00003fffU
47 #define PIDX_SHIFT 0
48 #define PIDX(x) ((x) << PIDX_SHIFT)
49
50 #define SGE_PF_GTS 0x4
51 #define INGRESSQID_MASK 0xffff0000U
52 #define INGRESSQID_SHIFT 16
53 #define INGRESSQID(x) ((x) << INGRESSQID_SHIFT)
54 #define TIMERREG_MASK 0x0000e000U
55 #define TIMERREG_SHIFT 13
56 #define TIMERREG(x) ((x) << TIMERREG_SHIFT)
57 #define SEINTARM_MASK 0x00001000U
58 #define SEINTARM_SHIFT 12
59 #define SEINTARM(x) ((x) << SEINTARM_SHIFT)
60 #define CIDXINC_MASK 0x00000fffU
61 #define CIDXINC_SHIFT 0
62 #define CIDXINC(x) ((x) << CIDXINC_SHIFT)
63
64 #define T4_MAX_NUM_PD 65536
65 #define T4_MAX_MR_SIZE (~0ULL)
66 #define T4_PAGESIZE_MASK 0xffffffff000 /* 4KB-8TB */
67 #define T4_FW_MAJ 0
68 #define A_PCIE_MA_SYNC 0x30b4
69
70 struct t4_status_page {
71 __be32 rsvd1; /* flit 0 - hw owns */
72 __be16 rsvd2;
73 __be16 qid;
74 __be16 cidx;
75 __be16 pidx;
76 u8 qp_err; /* flit 1 - sw owns */
77 u8 db_off;
78 u8 pad;
79 u16 host_wq_pidx;
80 u16 host_cidx;
81 u16 host_pidx;
82 };
83
84 #define T4_EQ_ENTRY_SIZE 64
85
86 #define T4_SQ_NUM_SLOTS 5
87 #define T4_SQ_NUM_BYTES (T4_EQ_ENTRY_SIZE * T4_SQ_NUM_SLOTS)
88 #define T4_MAX_SEND_SGE ((T4_SQ_NUM_BYTES - sizeof(struct fw_ri_send_wr) - \
89 sizeof(struct fw_ri_isgl)) / sizeof(struct fw_ri_sge))
90 #define T4_MAX_SEND_INLINE ((T4_SQ_NUM_BYTES - sizeof(struct fw_ri_send_wr) - \
91 sizeof(struct fw_ri_immd)))
92 #define T4_MAX_WRITE_INLINE ((T4_SQ_NUM_BYTES - \
93 sizeof(struct fw_ri_rdma_write_wr) - \
94 sizeof(struct fw_ri_immd)))
95 #define T4_MAX_WRITE_SGE ((T4_SQ_NUM_BYTES - \
96 sizeof(struct fw_ri_rdma_write_wr) - \
97 sizeof(struct fw_ri_isgl)) / sizeof(struct fw_ri_sge))
98 #define T4_MAX_FR_IMMD ((T4_SQ_NUM_BYTES - sizeof(struct fw_ri_fr_nsmr_wr) - \
99 sizeof(struct fw_ri_immd)) & ~31UL)
100 #define T4_MAX_FR_IMMD_DEPTH (T4_MAX_FR_IMMD / sizeof(u64))
101 #define T4_MAX_FR_DSGL 1024
102 #define T4_MAX_FR_DSGL_DEPTH (T4_MAX_FR_DSGL / sizeof(u64))
103 #define T4_MAX_FR_FW_DSGL 4096
104 #define T4_MAX_FR_FW_DSGL_DEPTH (T4_MAX_FR_FW_DSGL / sizeof(u64))
105
106 #define T4_RQ_NUM_SLOTS 2
107 #define T4_RQ_NUM_BYTES (T4_EQ_ENTRY_SIZE * T4_RQ_NUM_SLOTS)
108 #define T4_MAX_RECV_SGE 4
109
110 #define T4_WRITE_CMPL_MAX_SGL 4
111
112 union t4_wr {
113 struct fw_ri_res_wr res;
114 struct fw_ri_wr ri;
115 struct fw_ri_rdma_write_wr write;
116 struct fw_ri_send_wr send;
117 struct fw_ri_rdma_read_wr read;
118 struct fw_ri_bind_mw_wr bind;
119 struct fw_ri_fr_nsmr_wr fr;
120 struct fw_ri_fr_nsmr_tpte_wr fr_tpte;
121 struct fw_ri_inv_lstag_wr inv;
122 struct fw_ri_rdma_write_cmpl_wr write_cmpl;
123 struct t4_status_page status;
124 __be64 flits[T4_EQ_ENTRY_SIZE / sizeof(__be64) * T4_SQ_NUM_SLOTS];
125 };
126
127 union t4_recv_wr {
128 struct fw_ri_recv_wr recv;
129 struct t4_status_page status;
130 __be64 flits[T4_EQ_ENTRY_SIZE / sizeof(__be64) * T4_RQ_NUM_SLOTS];
131 };
132
init_wr_hdr(union t4_wr * wqe,u16 wrid,enum fw_wr_opcodes opcode,u8 flags,u8 len16)133 static inline void init_wr_hdr(union t4_wr *wqe, u16 wrid,
134 enum fw_wr_opcodes opcode, u8 flags, u8 len16)
135 {
136 wqe->send.opcode = (u8)opcode;
137 wqe->send.flags = flags;
138 wqe->send.wrid = wrid;
139 wqe->send.r1[0] = 0;
140 wqe->send.r1[1] = 0;
141 wqe->send.r1[2] = 0;
142 wqe->send.len16 = len16;
143 }
144
145 /* CQE/AE status codes */
146 #define T4_ERR_SUCCESS 0x0
147 #define T4_ERR_STAG 0x1 /* STAG invalid: either the */
148 /* STAG is offlimt, being 0, */
149 /* or STAG_key mismatch */
150 #define T4_ERR_PDID 0x2 /* PDID mismatch */
151 #define T4_ERR_QPID 0x3 /* QPID mismatch */
152 #define T4_ERR_ACCESS 0x4 /* Invalid access right */
153 #define T4_ERR_WRAP 0x5 /* Wrap error */
154 #define T4_ERR_BOUND 0x6 /* base and bounds voilation */
155 #define T4_ERR_INVALIDATE_SHARED_MR 0x7 /* attempt to invalidate a */
156 /* shared memory region */
157 #define T4_ERR_INVALIDATE_MR_WITH_MW_BOUND 0x8 /* attempt to invalidate a */
158 /* shared memory region */
159 #define T4_ERR_ECC 0x9 /* ECC error detected */
160 #define T4_ERR_ECC_PSTAG 0xA /* ECC error detected when */
161 /* reading PSTAG for a MW */
162 /* Invalidate */
163 #define T4_ERR_PBL_ADDR_BOUND 0xB /* pbl addr out of bounds: */
164 /* software error */
165 #define T4_ERR_SWFLUSH 0xC /* SW FLUSHED */
166 #define T4_ERR_CRC 0x10 /* CRC error */
167 #define T4_ERR_MARKER 0x11 /* Marker error */
168 #define T4_ERR_PDU_LEN_ERR 0x12 /* invalid PDU length */
169 #define T4_ERR_OUT_OF_RQE 0x13 /* out of RQE */
170 #define T4_ERR_DDP_VERSION 0x14 /* wrong DDP version */
171 #define T4_ERR_RDMA_VERSION 0x15 /* wrong RDMA version */
172 #define T4_ERR_OPCODE 0x16 /* invalid rdma opcode */
173 #define T4_ERR_DDP_QUEUE_NUM 0x17 /* invalid ddp queue number */
174 #define T4_ERR_MSN 0x18 /* MSN error */
175 #define T4_ERR_TBIT 0x19 /* tag bit not set correctly */
176 #define T4_ERR_MO 0x1A /* MO not 0 for TERMINATE */
177 /* or READ_REQ */
178 #define T4_ERR_MSN_GAP 0x1B
179 #define T4_ERR_MSN_RANGE 0x1C
180 #define T4_ERR_IRD_OVERFLOW 0x1D
181 #define T4_ERR_RQE_ADDR_BOUND 0x1E /* RQE addr out of bounds: */
182 /* software error */
183 #define T4_ERR_INTERNAL_ERR 0x1F /* internal error (opcode */
184 /* mismatch) */
185 /*
186 * CQE defs
187 */
188
189 /*
190 * 64B CQE entries.
191 */
192 struct t4_cqe {
193 struct rss_header rss;
194 __be32 header;
195 __be32 len;
196 union {
197 struct {
198 __be32 stag;
199 __be32 msn;
200 } rcqe;
201 struct {
202 u32 stag;
203 u16 nada2;
204 u16 cidx;
205 } scqe;
206 struct {
207 __be32 wrid_hi;
208 __be32 wrid_low;
209 } gen;
210 u64 drain_cookie;
211 struct {
212 __be32 mo;
213 __be32 msn;
214 __u64 imm_data;
215 } imm_data_rcqe;
216 } u;
217 __be64 reserved[3];
218 __be64 bits_type_ts;
219 };
220
221 /* macros for flit 0 of the cqe */
222
223 #define S_CQE_QPID 12
224 #define M_CQE_QPID 0xFFFFF
225 #define G_CQE_QPID(x) ((((x) >> S_CQE_QPID)) & M_CQE_QPID)
226 #define V_CQE_QPID(x) ((x)<<S_CQE_QPID)
227
228 #define S_CQE_SWCQE 11
229 #define M_CQE_SWCQE 0x1
230 #define G_CQE_SWCQE(x) ((((x) >> S_CQE_SWCQE)) & M_CQE_SWCQE)
231 #define V_CQE_SWCQE(x) ((x)<<S_CQE_SWCQE)
232
233 #define S_CQE_DRAIN 10
234 #define M_CQE_DRAIN 0x1
235 #define G_CQE_DRAIN(x) ((((x) >> S_CQE_DRAIN)) & M_CQE_DRAIN)
236 #define V_CQE_DRAIN(x) ((x)<<S_CQE_DRAIN)
237
238 #define S_CQE_STATUS 5
239 #define M_CQE_STATUS 0x1F
240 #define G_CQE_STATUS(x) ((((x) >> S_CQE_STATUS)) & M_CQE_STATUS)
241 #define V_CQE_STATUS(x) ((x)<<S_CQE_STATUS)
242
243 #define S_CQE_TYPE 4
244 #define M_CQE_TYPE 0x1
245 #define G_CQE_TYPE(x) ((((x) >> S_CQE_TYPE)) & M_CQE_TYPE)
246 #define V_CQE_TYPE(x) ((x)<<S_CQE_TYPE)
247
248 #define S_CQE_OPCODE 0
249 #define M_CQE_OPCODE 0xF
250 #define G_CQE_OPCODE(x) ((((x) >> S_CQE_OPCODE)) & M_CQE_OPCODE)
251 #define V_CQE_OPCODE(x) ((x)<<S_CQE_OPCODE)
252
253 #define SW_CQE(x) (G_CQE_SWCQE(be32_to_cpu((x)->header)))
254 #define DRAIN_CQE(x) (G_CQE_DRAIN(be32_to_cpu((x)->header)))
255 #define CQE_QPID(x) (G_CQE_QPID(be32_to_cpu((x)->header)))
256 #define CQE_TYPE(x) (G_CQE_TYPE(be32_to_cpu((x)->header)))
257 #define SQ_TYPE(x) (CQE_TYPE((x)))
258 #define RQ_TYPE(x) (!CQE_TYPE((x)))
259 #define CQE_STATUS(x) (G_CQE_STATUS(be32_to_cpu((x)->header)))
260 #define CQE_OPCODE(x) (G_CQE_OPCODE(be32_to_cpu((x)->header)))
261
262 #define CQE_SEND_OPCODE(x)(\
263 (G_CQE_OPCODE(be32_to_cpu((x)->header)) == FW_RI_SEND) || \
264 (G_CQE_OPCODE(be32_to_cpu((x)->header)) == FW_RI_SEND_WITH_SE) || \
265 (G_CQE_OPCODE(be32_to_cpu((x)->header)) == FW_RI_SEND_WITH_INV) || \
266 (G_CQE_OPCODE(be32_to_cpu((x)->header)) == FW_RI_SEND_WITH_SE_INV))
267
268 #define CQE_LEN(x) (be32_to_cpu((x)->len))
269
270 /* used for RQ completion processing */
271 #define CQE_WRID_STAG(x) (be32_to_cpu((x)->u.rcqe.stag))
272 #define CQE_WRID_MSN(x) (be32_to_cpu((x)->u.rcqe.msn))
273 #define CQE_IMM_DATA(x) ((x)->u.imm_data_rcqe.imm_data)
274
275 /* used for SQ completion processing */
276 #define CQE_WRID_SQ_IDX(x) ((x)->u.scqe.cidx)
277 #define CQE_WRID_FR_STAG(x) (be32_to_cpu((x)->u.scqe.stag))
278
279 /* generic accessor macros */
280 #define CQE_WRID_HI(x) ((x)->u.gen.wrid_hi)
281 #define CQE_WRID_LOW(x) ((x)->u.gen.wrid_low)
282 #define CQE_DRAIN_COOKIE(x) (x)->u.drain_cookie;
283
284 /* macros for flit 3 of the cqe */
285 #define S_CQE_GENBIT 63
286 #define M_CQE_GENBIT 0x1
287 #define G_CQE_GENBIT(x) (((x) >> S_CQE_GENBIT) & M_CQE_GENBIT)
288 #define V_CQE_GENBIT(x) ((x)<<S_CQE_GENBIT)
289
290 #define S_CQE_OVFBIT 62
291 #define M_CQE_OVFBIT 0x1
292 #define G_CQE_OVFBIT(x) ((((x) >> S_CQE_OVFBIT)) & M_CQE_OVFBIT)
293
294 #define S_CQE_IQTYPE 60
295 #define M_CQE_IQTYPE 0x3
296 #define G_CQE_IQTYPE(x) ((((x) >> S_CQE_IQTYPE)) & M_CQE_IQTYPE)
297
298 #define M_CQE_TS 0x0fffffffffffffffULL
299 #define G_CQE_TS(x) ((x) & M_CQE_TS)
300
301 #define CQE_OVFBIT(x) ((unsigned)G_CQE_OVFBIT(be64_to_cpu((x)->bits_type_ts)))
302 #define CQE_GENBIT(x) ((unsigned)G_CQE_GENBIT(be64_to_cpu((x)->bits_type_ts)))
303 #define CQE_TS(x) (G_CQE_TS(be64_to_cpu((x)->bits_type_ts)))
304
305 struct t4_swsqe {
306 u64 wr_id;
307 struct t4_cqe cqe;
308 int read_len;
309 int opcode;
310 int complete;
311 int signaled;
312 u16 idx;
313 int flushed;
314 ktime_t host_time;
315 u64 sge_ts;
316 };
317
t4_pgprot_wc(pgprot_t prot)318 static inline pgprot_t t4_pgprot_wc(pgprot_t prot)
319 {
320 #if defined(__i386__) || defined(__x86_64__) || defined(CONFIG_PPC64)
321 return pgprot_writecombine(prot);
322 #else
323 return pgprot_noncached(prot);
324 #endif
325 }
326
327 enum {
328 T4_SQ_ONCHIP = (1<<0),
329 };
330
331 struct t4_sq {
332 union t4_wr *queue;
333 bus_addr_t dma_addr;
334 DEFINE_DMA_UNMAP_ADDR(mapping);
335 unsigned long phys_addr;
336 struct t4_swsqe *sw_sq;
337 struct t4_swsqe *oldest_read;
338 void __iomem *bar2_va;
339 u64 bar2_pa;
340 size_t memsize;
341 u32 bar2_qid;
342 u32 qid;
343 u16 in_use;
344 u16 size;
345 u16 cidx;
346 u16 pidx;
347 u16 wq_pidx;
348 u16 wq_pidx_inc;
349 u16 flags;
350 short flush_cidx;
351 };
352
353 struct t4_swrqe {
354 u64 wr_id;
355 };
356
357 struct t4_rq {
358 union t4_recv_wr *queue;
359 bus_addr_t dma_addr;
360 DEFINE_DMA_UNMAP_ADDR(mapping);
361 unsigned long phys_addr;
362 struct t4_swrqe *sw_rq;
363 void __iomem *bar2_va;
364 u64 bar2_pa;
365 size_t memsize;
366 u32 bar2_qid;
367 u32 qid;
368 u32 msn;
369 u32 rqt_hwaddr;
370 u16 rqt_size;
371 u16 in_use;
372 u16 size;
373 u16 cidx;
374 u16 pidx;
375 u16 wq_pidx;
376 u16 wq_pidx_inc;
377 };
378
379 struct t4_wq {
380 struct t4_sq sq;
381 struct t4_rq rq;
382 struct c4iw_rdev *rdev;
383 int flushed;
384 };
385
t4_rqes_posted(struct t4_wq * wq)386 static inline int t4_rqes_posted(struct t4_wq *wq)
387 {
388 return wq->rq.in_use;
389 }
390
t4_rq_empty(struct t4_wq * wq)391 static inline int t4_rq_empty(struct t4_wq *wq)
392 {
393 return wq->rq.in_use == 0;
394 }
395
t4_rq_full(struct t4_wq * wq)396 static inline int t4_rq_full(struct t4_wq *wq)
397 {
398 return wq->rq.in_use == (wq->rq.size - 1);
399 }
400
t4_rq_avail(struct t4_wq * wq)401 static inline u32 t4_rq_avail(struct t4_wq *wq)
402 {
403 return wq->rq.size - 1 - wq->rq.in_use;
404 }
405
t4_rq_produce(struct t4_wq * wq,u8 len16)406 static inline void t4_rq_produce(struct t4_wq *wq, u8 len16)
407 {
408 wq->rq.in_use++;
409 if (++wq->rq.pidx == wq->rq.size)
410 wq->rq.pidx = 0;
411 wq->rq.wq_pidx += DIV_ROUND_UP(len16*16, T4_EQ_ENTRY_SIZE);
412 if (wq->rq.wq_pidx >= wq->rq.size * T4_RQ_NUM_SLOTS)
413 wq->rq.wq_pidx %= wq->rq.size * T4_RQ_NUM_SLOTS;
414 }
415
t4_rq_consume(struct t4_wq * wq)416 static inline void t4_rq_consume(struct t4_wq *wq)
417 {
418 wq->rq.in_use--;
419 wq->rq.msn++;
420 if (++wq->rq.cidx == wq->rq.size)
421 wq->rq.cidx = 0;
422 }
423
t4_rq_host_wq_pidx(struct t4_wq * wq)424 static inline u16 t4_rq_host_wq_pidx(struct t4_wq *wq)
425 {
426 return wq->rq.queue[wq->rq.size].status.host_wq_pidx;
427 }
428
t4_rq_wq_size(struct t4_wq * wq)429 static inline u16 t4_rq_wq_size(struct t4_wq *wq)
430 {
431 return wq->rq.size * T4_RQ_NUM_SLOTS;
432 }
433
t4_sq_onchip(struct t4_sq * sq)434 static inline int t4_sq_onchip(struct t4_sq *sq)
435 {
436 return sq->flags & T4_SQ_ONCHIP;
437 }
438
t4_sq_empty(struct t4_wq * wq)439 static inline int t4_sq_empty(struct t4_wq *wq)
440 {
441 return wq->sq.in_use == 0;
442 }
443
t4_sq_full(struct t4_wq * wq)444 static inline int t4_sq_full(struct t4_wq *wq)
445 {
446 return wq->sq.in_use == (wq->sq.size - 1);
447 }
448
t4_sq_avail(struct t4_wq * wq)449 static inline u32 t4_sq_avail(struct t4_wq *wq)
450 {
451 return wq->sq.size - 1 - wq->sq.in_use;
452 }
453
t4_sq_produce(struct t4_wq * wq,u8 len16)454 static inline void t4_sq_produce(struct t4_wq *wq, u8 len16)
455 {
456 wq->sq.in_use++;
457 if (++wq->sq.pidx == wq->sq.size)
458 wq->sq.pidx = 0;
459 wq->sq.wq_pidx += DIV_ROUND_UP(len16*16, T4_EQ_ENTRY_SIZE);
460 if (wq->sq.wq_pidx >= wq->sq.size * T4_SQ_NUM_SLOTS)
461 wq->sq.wq_pidx %= wq->sq.size * T4_SQ_NUM_SLOTS;
462 }
463
t4_sq_consume(struct t4_wq * wq)464 static inline void t4_sq_consume(struct t4_wq *wq)
465 {
466 BUG_ON(wq->sq.in_use < 1);
467 if (wq->sq.cidx == wq->sq.flush_cidx)
468 wq->sq.flush_cidx = -1;
469 wq->sq.in_use--;
470 if (++wq->sq.cidx == wq->sq.size)
471 wq->sq.cidx = 0;
472 }
473
t4_sq_host_wq_pidx(struct t4_wq * wq)474 static inline u16 t4_sq_host_wq_pidx(struct t4_wq *wq)
475 {
476 return wq->sq.queue[wq->sq.size].status.host_wq_pidx;
477 }
478
t4_sq_wq_size(struct t4_wq * wq)479 static inline u16 t4_sq_wq_size(struct t4_wq *wq)
480 {
481 return wq->sq.size * T4_SQ_NUM_SLOTS;
482 }
483
484 /* This function copies 64 byte coalesced work request to memory
485 * mapped BAR2 space. For coalesced WRs, the SGE fetches data
486 * from the FIFO instead of from Host.
487 */
pio_copy(u64 __iomem * dst,u64 * src)488 static inline void pio_copy(u64 __iomem *dst, u64 *src)
489 {
490 int count = 8;
491
492 while (count) {
493 __raw_writeq(*src, dst);
494 src++;
495 dst++;
496 count--;
497 }
498 }
499
500 static inline void
t4_ring_sq_db(struct t4_wq * wq,u16 inc,union t4_wr * wqe,u8 wc)501 t4_ring_sq_db(struct t4_wq *wq, u16 inc, union t4_wr *wqe, u8 wc)
502 {
503
504 /* Flush host queue memory writes. */
505 wmb();
506 if (wc && inc == 1 && wq->sq.bar2_qid == 0 && wqe) {
507 CTR2(KTR_IW_CXGBE, "%s: WC wq->sq.pidx = %d",
508 __func__, wq->sq.pidx);
509 pio_copy((u64 __iomem *)
510 ((u64)wq->sq.bar2_va + SGE_UDB_WCDOORBELL),
511 (u64 *)wqe);
512 } else {
513 CTR2(KTR_IW_CXGBE, "%s: DB wq->sq.pidx = %d",
514 __func__, wq->sq.pidx);
515 __raw_writel(V_PIDX_T5(inc) | V_QID(wq->sq.bar2_qid),
516 (char __iomem *)wq->sq.bar2_va + SGE_UDB_KDOORBELL);
517 }
518
519 /* Flush user doorbell area writes. */
520 wmb();
521 return;
522 }
523
524 static inline void
t4_ring_rq_db(struct t4_wq * wq,u16 inc,union t4_recv_wr * wqe,u8 wc)525 t4_ring_rq_db(struct t4_wq *wq, u16 inc, union t4_recv_wr *wqe, u8 wc)
526 {
527
528 /* Flush host queue memory writes. */
529 wmb();
530 if (wc && inc == 1 && wq->rq.bar2_qid == 0 && wqe) {
531 CTR2(KTR_IW_CXGBE, "%s: WC wq->rq.pidx = %d",
532 __func__, wq->rq.pidx);
533 pio_copy((u64 __iomem *)((u64)wq->rq.bar2_va +
534 SGE_UDB_WCDOORBELL), (u64 *)wqe);
535 } else {
536 CTR2(KTR_IW_CXGBE, "%s: DB wq->rq.pidx = %d",
537 __func__, wq->rq.pidx);
538 __raw_writel(V_PIDX_T5(inc) | V_QID(wq->rq.bar2_qid),
539 (char __iomem *)wq->rq.bar2_va + SGE_UDB_KDOORBELL);
540 }
541
542 /* Flush user doorbell area writes. */
543 wmb();
544 return;
545 }
546
t4_wq_in_error(struct t4_wq * wq)547 static inline int t4_wq_in_error(struct t4_wq *wq)
548 {
549 return wq->rq.queue[wq->rq.size].status.qp_err;
550 }
551
t4_set_wq_in_error(struct t4_wq * wq)552 static inline void t4_set_wq_in_error(struct t4_wq *wq)
553 {
554 wq->rq.queue[wq->rq.size].status.qp_err = 1;
555 }
556
557 enum t4_cq_flags {
558 CQ_ARMED = 1,
559 };
560
561 struct t4_cq {
562 struct t4_cqe *queue;
563 bus_addr_t dma_addr;
564 DEFINE_DMA_UNMAP_ADDR(mapping);
565 struct t4_cqe *sw_queue;
566 void __iomem *bar2_va;
567 u64 bar2_pa;
568 u32 bar2_qid;
569 struct c4iw_rdev *rdev;
570 size_t memsize;
571 __be64 bits_type_ts;
572 u32 cqid;
573 u32 qid_mask;
574 int vector;
575 u16 size; /* including status page */
576 u16 cidx;
577 u16 sw_pidx;
578 u16 sw_cidx;
579 u16 sw_in_use;
580 u16 cidx_inc;
581 u8 gen;
582 u8 error;
583 unsigned long flags;
584 };
585
write_gts(struct t4_cq * cq,u32 val)586 static inline void write_gts(struct t4_cq *cq, u32 val)
587 {
588 writel(val | V_INGRESSQID(cq->bar2_qid),
589 (void __iomem *)((u64)cq->bar2_va + SGE_UDB_GTS));
590 }
591
t4_clear_cq_armed(struct t4_cq * cq)592 static inline int t4_clear_cq_armed(struct t4_cq *cq)
593 {
594 return test_and_clear_bit(CQ_ARMED, &cq->flags);
595 }
596
t4_arm_cq(struct t4_cq * cq,int se)597 static inline int t4_arm_cq(struct t4_cq *cq, int se)
598 {
599 u32 val;
600
601 set_bit(CQ_ARMED, &cq->flags);
602 while (cq->cidx_inc > CIDXINC_MASK) {
603 val = SEINTARM(0) | CIDXINC(CIDXINC_MASK) | TIMERREG(7);
604 writel(val | V_INGRESSQID(cq->bar2_qid),
605 (void __iomem *)((u64)cq->bar2_va + SGE_UDB_GTS));
606 cq->cidx_inc -= CIDXINC_MASK;
607 }
608 val = SEINTARM(se) | CIDXINC(cq->cidx_inc) | TIMERREG(6);
609 writel(val | V_INGRESSQID(cq->bar2_qid),
610 (void __iomem *)((u64)cq->bar2_va + SGE_UDB_GTS));
611 cq->cidx_inc = 0;
612 return 0;
613 }
614
t4_swcq_produce(struct t4_cq * cq)615 static inline void t4_swcq_produce(struct t4_cq *cq)
616 {
617 cq->sw_in_use++;
618 if (cq->sw_in_use == cq->size) {
619 CTR2(KTR_IW_CXGBE, "%s cxgb4 sw cq overflow cqid %u",
620 __func__, cq->cqid);
621 cq->error = 1;
622 BUG_ON(1);
623 }
624 if (++cq->sw_pidx == cq->size)
625 cq->sw_pidx = 0;
626 }
627
t4_swcq_consume(struct t4_cq * cq)628 static inline void t4_swcq_consume(struct t4_cq *cq)
629 {
630 BUG_ON(cq->sw_in_use < 1);
631 cq->sw_in_use--;
632 if (++cq->sw_cidx == cq->size)
633 cq->sw_cidx = 0;
634 }
635
t4_hwcq_consume(struct t4_cq * cq)636 static inline void t4_hwcq_consume(struct t4_cq *cq)
637 {
638 cq->bits_type_ts = cq->queue[cq->cidx].bits_type_ts;
639 if (++cq->cidx_inc == (cq->size >> 4) || cq->cidx_inc == M_CIDXINC) {
640 u32 val;
641
642 val = SEINTARM(0) | CIDXINC(cq->cidx_inc) | TIMERREG(7);
643 write_gts(cq, val);
644 cq->cidx_inc = 0;
645 }
646 if (++cq->cidx == cq->size) {
647 cq->cidx = 0;
648 cq->gen ^= 1;
649 }
650 }
651
t4_valid_cqe(struct t4_cq * cq,struct t4_cqe * cqe)652 static inline int t4_valid_cqe(struct t4_cq *cq, struct t4_cqe *cqe)
653 {
654 return (CQE_GENBIT(cqe) == cq->gen);
655 }
656
t4_cq_notempty(struct t4_cq * cq)657 static inline int t4_cq_notempty(struct t4_cq *cq)
658 {
659 return cq->sw_in_use || t4_valid_cqe(cq, &cq->queue[cq->cidx]);
660 }
661
t4_next_hw_cqe(struct t4_cq * cq,struct t4_cqe ** cqe)662 static inline int t4_next_hw_cqe(struct t4_cq *cq, struct t4_cqe **cqe)
663 {
664 int ret;
665 u16 prev_cidx;
666
667 if (cq->cidx == 0)
668 prev_cidx = cq->size - 1;
669 else
670 prev_cidx = cq->cidx - 1;
671
672 if (cq->queue[prev_cidx].bits_type_ts != cq->bits_type_ts) {
673 ret = -EOVERFLOW;
674 cq->error = 1;
675 printk(KERN_ERR MOD "cq overflow cqid %u\n", cq->cqid);
676 BUG_ON(1);
677 } else if (t4_valid_cqe(cq, &cq->queue[cq->cidx])) {
678
679 /* Ensure CQE is flushed to memory */
680 rmb();
681 *cqe = &cq->queue[cq->cidx];
682 ret = 0;
683 } else
684 ret = -ENODATA;
685 return ret;
686 }
687
t4_next_sw_cqe(struct t4_cq * cq)688 static inline struct t4_cqe *t4_next_sw_cqe(struct t4_cq *cq)
689 {
690 if (cq->sw_in_use == cq->size) {
691 CTR2(KTR_IW_CXGBE, "%s cxgb4 sw cq overflow cqid %u",
692 __func__, cq->cqid);
693 cq->error = 1;
694 BUG_ON(1);
695 return NULL;
696 }
697 if (cq->sw_in_use)
698 return &cq->sw_queue[cq->sw_cidx];
699 return NULL;
700 }
701
t4_next_cqe(struct t4_cq * cq,struct t4_cqe ** cqe)702 static inline int t4_next_cqe(struct t4_cq *cq, struct t4_cqe **cqe)
703 {
704 int ret = 0;
705
706 if (cq->error)
707 ret = -ENODATA;
708 else if (cq->sw_in_use)
709 *cqe = &cq->sw_queue[cq->sw_cidx];
710 else
711 ret = t4_next_hw_cqe(cq, cqe);
712 return ret;
713 }
714
t4_cq_in_error(struct t4_cq * cq)715 static inline int t4_cq_in_error(struct t4_cq *cq)
716 {
717 return ((struct t4_status_page *)&cq->queue[cq->size])->qp_err;
718 }
719
t4_set_cq_in_error(struct t4_cq * cq)720 static inline void t4_set_cq_in_error(struct t4_cq *cq)
721 {
722 ((struct t4_status_page *)&cq->queue[cq->size])->qp_err = 1;
723 }
724 struct t4_dev_status_page {
725 u8 db_off;
726 u8 wc_supported;
727 u8 write_cmpl_supported;
728 u8 pad2;
729 u32 fid_base;
730 u64 qp_start;
731 u64 qp_size;
732 u64 cq_start;
733 u64 cq_size;
734 };
735 #endif
736