xref: /freebsd/sys/contrib/device-tree/include/dt-bindings/firmware/imx/rsrc.h (revision 8bab661a3316d8bd9b9fbd11a3b4371b91507bd2)
1 /* SPDX-License-Identifier: GPL-2.0+ */
2 /*
3  * Copyright (C) 2016 Freescale Semiconductor, Inc.
4  * Copyright 2017-2018 NXP
5  */
6 
7 #ifndef __DT_BINDINGS_RSCRC_IMX_H
8 #define __DT_BINDINGS_RSCRC_IMX_H
9 
10 /*
11  * These defines are used to indicate a resource. Resources include peripherals
12  * and bus masters (but not memory regions). Note items from list should
13  * never be changed or removed (only added to at the end of the list).
14  */
15 
16 #define IMX_SC_R_AP_0			0
17 #define IMX_SC_R_AP_0_0			1
18 #define IMX_SC_R_AP_0_1			2
19 #define IMX_SC_R_AP_0_2			3
20 #define IMX_SC_R_AP_0_3			4
21 #define IMX_SC_R_AP_1			5
22 #define IMX_SC_R_AP_1_0			6
23 #define IMX_SC_R_AP_1_1			7
24 #define IMX_SC_R_AP_1_2			8
25 #define IMX_SC_R_AP_1_3			9
26 #define IMX_SC_R_CCI			10
27 #define IMX_SC_R_DB			11
28 #define IMX_SC_R_DRC_0			12
29 #define IMX_SC_R_DRC_1			13
30 #define IMX_SC_R_GIC_SMMU		14
31 #define IMX_SC_R_IRQSTR_MCU_0		15
32 #define IMX_SC_R_IRQSTR_MCU_1		16
33 #define IMX_SC_R_SMMU_0			17
34 #define IMX_SC_R_GIC_0			18
35 #define IMX_SC_R_DC_0_BLIT0		19
36 #define IMX_SC_R_DC_0_BLIT1		20
37 #define IMX_SC_R_DC_0_BLIT2		21
38 #define IMX_SC_R_DC_0_BLIT_OUT		22
39 #define IMX_SC_R_PERF_0			23
40 #define IMX_SC_R_USB_1_PHY		24
41 #define IMX_SC_R_DC_0_WARP		25
42 #define IMX_SC_R_V2X_MU_0		26
43 #define IMX_SC_R_V2X_MU_1		27
44 #define IMX_SC_R_DC_0_VIDEO0		28
45 #define IMX_SC_R_DC_0_VIDEO1		29
46 #define IMX_SC_R_DC_0_FRAC0		30
47 #define IMX_SC_R_V2X_MU_2		31
48 #define IMX_SC_R_DC_0			32
49 #define IMX_SC_R_GPU_2_PID0		33
50 #define IMX_SC_R_DC_0_PLL_0		34
51 #define IMX_SC_R_DC_0_PLL_1		35
52 #define IMX_SC_R_DC_1_BLIT0		36
53 #define IMX_SC_R_DC_1_BLIT1		37
54 #define IMX_SC_R_DC_1_BLIT2		38
55 #define IMX_SC_R_DC_1_BLIT_OUT		39
56 #define IMX_SC_R_V2X_MU_3		40
57 #define IMX_SC_R_V2X_MU_4		41
58 #define IMX_SC_R_DC_1_WARP		42
59 #define IMX_SC_R_STM			43
60 #define IMX_SC_R_SECVIO			44
61 #define IMX_SC_R_DC_1_VIDEO0		45
62 #define IMX_SC_R_DC_1_VIDEO1		46
63 #define IMX_SC_R_DC_1_FRAC0		47
64 #define IMX_SC_R_V2X			48
65 #define IMX_SC_R_DC_1			49
66 #define IMX_SC_R_UNUSED14		50
67 #define IMX_SC_R_DC_1_PLL_0		51
68 #define IMX_SC_R_DC_1_PLL_1		52
69 #define IMX_SC_R_SPI_0			53
70 #define IMX_SC_R_SPI_1			54
71 #define IMX_SC_R_SPI_2			55
72 #define IMX_SC_R_SPI_3			56
73 #define IMX_SC_R_UART_0			57
74 #define IMX_SC_R_UART_1			58
75 #define IMX_SC_R_UART_2			59
76 #define IMX_SC_R_UART_3			60
77 #define IMX_SC_R_UART_4			61
78 #define IMX_SC_R_EMVSIM_0		62
79 #define IMX_SC_R_EMVSIM_1		63
80 #define IMX_SC_R_DMA_0_CH0		64
81 #define IMX_SC_R_DMA_0_CH1		65
82 #define IMX_SC_R_DMA_0_CH2		66
83 #define IMX_SC_R_DMA_0_CH3		67
84 #define IMX_SC_R_DMA_0_CH4		68
85 #define IMX_SC_R_DMA_0_CH5		69
86 #define IMX_SC_R_DMA_0_CH6		70
87 #define IMX_SC_R_DMA_0_CH7		71
88 #define IMX_SC_R_DMA_0_CH8		72
89 #define IMX_SC_R_DMA_0_CH9		73
90 #define IMX_SC_R_DMA_0_CH10		74
91 #define IMX_SC_R_DMA_0_CH11		75
92 #define IMX_SC_R_DMA_0_CH12		76
93 #define IMX_SC_R_DMA_0_CH13		77
94 #define IMX_SC_R_DMA_0_CH14		78
95 #define IMX_SC_R_DMA_0_CH15		79
96 #define IMX_SC_R_DMA_0_CH16		80
97 #define IMX_SC_R_DMA_0_CH17		81
98 #define IMX_SC_R_DMA_0_CH18		82
99 #define IMX_SC_R_DMA_0_CH19		83
100 #define IMX_SC_R_DMA_0_CH20		84
101 #define IMX_SC_R_DMA_0_CH21		85
102 #define IMX_SC_R_DMA_0_CH22		86
103 #define IMX_SC_R_DMA_0_CH23		87
104 #define IMX_SC_R_DMA_0_CH24		88
105 #define IMX_SC_R_DMA_0_CH25		89
106 #define IMX_SC_R_DMA_0_CH26		90
107 #define IMX_SC_R_DMA_0_CH27		91
108 #define IMX_SC_R_DMA_0_CH28		92
109 #define IMX_SC_R_DMA_0_CH29		93
110 #define IMX_SC_R_DMA_0_CH30		94
111 #define IMX_SC_R_DMA_0_CH31		95
112 #define IMX_SC_R_I2C_0			96
113 #define IMX_SC_R_I2C_1			97
114 #define IMX_SC_R_I2C_2			98
115 #define IMX_SC_R_I2C_3			99
116 #define IMX_SC_R_I2C_4			100
117 #define IMX_SC_R_ADC_0			101
118 #define IMX_SC_R_ADC_1			102
119 #define IMX_SC_R_FTM_0			103
120 #define IMX_SC_R_FTM_1			104
121 #define IMX_SC_R_CAN_0			105
122 #define IMX_SC_R_CAN_1			106
123 #define IMX_SC_R_CAN_2			107
124 #define IMX_SC_R_CAN(x)			(IMX_SC_R_CAN_0 + (x))
125 #define IMX_SC_R_DMA_1_CH0		108
126 #define IMX_SC_R_DMA_1_CH1		109
127 #define IMX_SC_R_DMA_1_CH2		110
128 #define IMX_SC_R_DMA_1_CH3		111
129 #define IMX_SC_R_DMA_1_CH4		112
130 #define IMX_SC_R_DMA_1_CH5		113
131 #define IMX_SC_R_DMA_1_CH6		114
132 #define IMX_SC_R_DMA_1_CH7		115
133 #define IMX_SC_R_DMA_1_CH8		116
134 #define IMX_SC_R_DMA_1_CH9		117
135 #define IMX_SC_R_DMA_1_CH10		118
136 #define IMX_SC_R_DMA_1_CH11		119
137 #define IMX_SC_R_DMA_1_CH12		120
138 #define IMX_SC_R_DMA_1_CH13		121
139 #define IMX_SC_R_DMA_1_CH14		122
140 #define IMX_SC_R_DMA_1_CH15		123
141 #define IMX_SC_R_DMA_1_CH16		124
142 #define IMX_SC_R_DMA_1_CH17		125
143 #define IMX_SC_R_DMA_1_CH18		126
144 #define IMX_SC_R_DMA_1_CH19		127
145 #define IMX_SC_R_DMA_1_CH20		128
146 #define IMX_SC_R_DMA_1_CH21		129
147 #define IMX_SC_R_DMA_1_CH22		130
148 #define IMX_SC_R_DMA_1_CH23		131
149 #define IMX_SC_R_DMA_1_CH24		132
150 #define IMX_SC_R_DMA_1_CH25		133
151 #define IMX_SC_R_DMA_1_CH26		134
152 #define IMX_SC_R_DMA_1_CH27		135
153 #define IMX_SC_R_DMA_1_CH28		136
154 #define IMX_SC_R_DMA_1_CH29		137
155 #define IMX_SC_R_DMA_1_CH30		138
156 #define IMX_SC_R_DMA_1_CH31		139
157 #define IMX_SC_R_V2X_PID0		140
158 #define IMX_SC_R_V2X_PID1		141
159 #define IMX_SC_R_V2X_PID2		142
160 #define IMX_SC_R_V2X_PID3		143
161 #define IMX_SC_R_GPU_0_PID0		144
162 #define IMX_SC_R_GPU_0_PID1		145
163 #define IMX_SC_R_GPU_0_PID2		146
164 #define IMX_SC_R_GPU_0_PID3		147
165 #define IMX_SC_R_GPU_1_PID0		148
166 #define IMX_SC_R_GPU_1_PID1		149
167 #define IMX_SC_R_GPU_1_PID2		150
168 #define IMX_SC_R_GPU_1_PID3		151
169 #define IMX_SC_R_PCIE_A			152
170 #define IMX_SC_R_SERDES_0		153
171 #define IMX_SC_R_MATCH_0		154
172 #define IMX_SC_R_MATCH_1		155
173 #define IMX_SC_R_MATCH_2		156
174 #define IMX_SC_R_MATCH_3		157
175 #define IMX_SC_R_MATCH_4		158
176 #define IMX_SC_R_MATCH_5		159
177 #define IMX_SC_R_MATCH_6		160
178 #define IMX_SC_R_MATCH_7		161
179 #define IMX_SC_R_MATCH_8		162
180 #define IMX_SC_R_MATCH_9		163
181 #define IMX_SC_R_MATCH_10		164
182 #define IMX_SC_R_MATCH_11		165
183 #define IMX_SC_R_MATCH_12		166
184 #define IMX_SC_R_MATCH_13		167
185 #define IMX_SC_R_MATCH_14		168
186 #define IMX_SC_R_PCIE_B			169
187 #define IMX_SC_R_SATA_0			170
188 #define IMX_SC_R_SERDES_1		171
189 #define IMX_SC_R_HSIO_GPIO_0		172
190 #define IMX_SC_R_MATCH_15		173
191 #define IMX_SC_R_MATCH_16		174
192 #define IMX_SC_R_MATCH_17		175
193 #define IMX_SC_R_MATCH_18		176
194 #define IMX_SC_R_MATCH_19		177
195 #define IMX_SC_R_MATCH_20		178
196 #define IMX_SC_R_MATCH_21		179
197 #define IMX_SC_R_MATCH_22		180
198 #define IMX_SC_R_MATCH_23		181
199 #define IMX_SC_R_MATCH_24		182
200 #define IMX_SC_R_MATCH_25		183
201 #define IMX_SC_R_MATCH_26		184
202 #define IMX_SC_R_MATCH_27		185
203 #define IMX_SC_R_MATCH_28		186
204 #define IMX_SC_R_LCD_0			187
205 #define IMX_SC_R_LCD_0_PWM_0		188
206 #define IMX_SC_R_LCD_0_I2C_0		189
207 #define IMX_SC_R_LCD_0_I2C_1		190
208 #define IMX_SC_R_PWM_0			191
209 #define IMX_SC_R_PWM_1			192
210 #define IMX_SC_R_PWM_2			193
211 #define IMX_SC_R_PWM_3			194
212 #define IMX_SC_R_PWM_4			195
213 #define IMX_SC_R_PWM_5			196
214 #define IMX_SC_R_PWM_6			197
215 #define IMX_SC_R_PWM_7			198
216 #define IMX_SC_R_GPIO_0			199
217 #define IMX_SC_R_GPIO_1			200
218 #define IMX_SC_R_GPIO_2			201
219 #define IMX_SC_R_GPIO_3			202
220 #define IMX_SC_R_GPIO_4			203
221 #define IMX_SC_R_GPIO_5			204
222 #define IMX_SC_R_GPIO_6			205
223 #define IMX_SC_R_GPIO_7			206
224 #define IMX_SC_R_GPT_0			207
225 #define IMX_SC_R_GPT_1			208
226 #define IMX_SC_R_GPT_2			209
227 #define IMX_SC_R_GPT_3			210
228 #define IMX_SC_R_GPT_4			211
229 #define IMX_SC_R_KPP			212
230 #define IMX_SC_R_MU_0A			213
231 #define IMX_SC_R_MU_1A			214
232 #define IMX_SC_R_MU_2A			215
233 #define IMX_SC_R_MU_3A			216
234 #define IMX_SC_R_MU_4A			217
235 #define IMX_SC_R_MU_5A			218
236 #define IMX_SC_R_MU_6A			219
237 #define IMX_SC_R_MU_7A			220
238 #define IMX_SC_R_MU_8A			221
239 #define IMX_SC_R_MU_9A			222
240 #define IMX_SC_R_MU_10A			223
241 #define IMX_SC_R_MU_11A			224
242 #define IMX_SC_R_MU_12A			225
243 #define IMX_SC_R_MU_13A			226
244 #define IMX_SC_R_MU_5B			227
245 #define IMX_SC_R_MU_6B			228
246 #define IMX_SC_R_MU_7B			229
247 #define IMX_SC_R_MU_8B			230
248 #define IMX_SC_R_MU_9B			231
249 #define IMX_SC_R_MU_10B			232
250 #define IMX_SC_R_MU_11B			233
251 #define IMX_SC_R_MU_12B			234
252 #define IMX_SC_R_MU_13B			235
253 #define IMX_SC_R_ROM_0			236
254 #define IMX_SC_R_FSPI_0			237
255 #define IMX_SC_R_FSPI_1			238
256 #define IMX_SC_R_IEE_0			239
257 #define IMX_SC_R_IEE_0_R0		240
258 #define IMX_SC_R_IEE_0_R1		241
259 #define IMX_SC_R_IEE_0_R2		242
260 #define IMX_SC_R_IEE_0_R3		243
261 #define IMX_SC_R_IEE_0_R4		244
262 #define IMX_SC_R_IEE_0_R5		245
263 #define IMX_SC_R_IEE_0_R6		246
264 #define IMX_SC_R_IEE_0_R7		247
265 #define IMX_SC_R_SDHC_0			248
266 #define IMX_SC_R_SDHC_1			249
267 #define IMX_SC_R_SDHC_2			250
268 #define IMX_SC_R_ENET_0			251
269 #define IMX_SC_R_ENET_1			252
270 #define IMX_SC_R_MLB_0			253
271 #define IMX_SC_R_DMA_2_CH0		254
272 #define IMX_SC_R_DMA_2_CH1		255
273 #define IMX_SC_R_DMA_2_CH2		256
274 #define IMX_SC_R_DMA_2_CH3		257
275 #define IMX_SC_R_DMA_2_CH4		258
276 #define IMX_SC_R_USB_0			259
277 #define IMX_SC_R_USB_1			260
278 #define IMX_SC_R_USB_0_PHY		261
279 #define IMX_SC_R_USB_2			262
280 #define IMX_SC_R_USB_2_PHY		263
281 #define IMX_SC_R_DTCP			264
282 #define IMX_SC_R_NAND			265
283 #define IMX_SC_R_LVDS_0			266
284 #define IMX_SC_R_LVDS_0_PWM_0		267
285 #define IMX_SC_R_LVDS_0_I2C_0		268
286 #define IMX_SC_R_LVDS_0_I2C_1		269
287 #define IMX_SC_R_LVDS_1			270
288 #define IMX_SC_R_LVDS_1_PWM_0		271
289 #define IMX_SC_R_LVDS_1_I2C_0		272
290 #define IMX_SC_R_LVDS_1_I2C_1		273
291 #define IMX_SC_R_LVDS_2			274
292 #define IMX_SC_R_LVDS_2_PWM_0		275
293 #define IMX_SC_R_LVDS_2_I2C_0		276
294 #define IMX_SC_R_LVDS_2_I2C_1		277
295 #define IMX_SC_R_MCU_0_PID0		278
296 #define IMX_SC_R_MCU_0_PID1		279
297 #define IMX_SC_R_MCU_0_PID2		280
298 #define IMX_SC_R_MCU_0_PID3		281
299 #define IMX_SC_R_MCU_0_PID4		282
300 #define IMX_SC_R_MCU_0_RGPIO		283
301 #define IMX_SC_R_MCU_0_SEMA42		284
302 #define IMX_SC_R_MCU_0_TPM		285
303 #define IMX_SC_R_MCU_0_PIT		286
304 #define IMX_SC_R_MCU_0_UART		287
305 #define IMX_SC_R_MCU_0_I2C		288
306 #define IMX_SC_R_MCU_0_INTMUX		289
307 #define IMX_SC_R_ENET_0_A0		290
308 #define IMX_SC_R_ENET_0_A1		291
309 #define IMX_SC_R_MCU_0_MU_0B		292
310 #define IMX_SC_R_MCU_0_MU_0A0		293
311 #define IMX_SC_R_MCU_0_MU_0A1		294
312 #define IMX_SC_R_MCU_0_MU_0A2		295
313 #define IMX_SC_R_MCU_0_MU_0A3		296
314 #define IMX_SC_R_MCU_0_MU_1A		297
315 #define IMX_SC_R_MCU_1_PID0		298
316 #define IMX_SC_R_MCU_1_PID1		299
317 #define IMX_SC_R_MCU_1_PID2		300
318 #define IMX_SC_R_MCU_1_PID3		301
319 #define IMX_SC_R_MCU_1_PID4		302
320 #define IMX_SC_R_MCU_1_RGPIO		303
321 #define IMX_SC_R_MCU_1_SEMA42		304
322 #define IMX_SC_R_MCU_1_TPM		305
323 #define IMX_SC_R_MCU_1_PIT		306
324 #define IMX_SC_R_MCU_1_UART		307
325 #define IMX_SC_R_MCU_1_I2C		308
326 #define IMX_SC_R_MCU_1_INTMUX		309
327 #define IMX_SC_R_UNUSED17		310
328 #define IMX_SC_R_UNUSED18		311
329 #define IMX_SC_R_MCU_1_MU_0B		312
330 #define IMX_SC_R_MCU_1_MU_0A0		313
331 #define IMX_SC_R_MCU_1_MU_0A1		314
332 #define IMX_SC_R_MCU_1_MU_0A2		315
333 #define IMX_SC_R_MCU_1_MU_0A3		316
334 #define IMX_SC_R_MCU_1_MU_1A		317
335 #define IMX_SC_R_SAI_0			318
336 #define IMX_SC_R_SAI_1			319
337 #define IMX_SC_R_SAI_2			320
338 #define IMX_SC_R_IRQSTR_AP_0		321
339 #define IMX_SC_R_IRQSTR_DSP		322
340 #define IMX_SC_R_ELCDIF_PLL		323
341 #define IMX_SC_R_OCRAM			324
342 #define IMX_SC_R_AUDIO_PLL_0		325
343 #define IMX_SC_R_PI_0			326
344 #define IMX_SC_R_PI_0_PWM_0		327
345 #define IMX_SC_R_PI_0_PWM_1		328
346 #define IMX_SC_R_PI_0_I2C_0		329
347 #define IMX_SC_R_PI_0_PLL		330
348 #define IMX_SC_R_PI_1			331
349 #define IMX_SC_R_PI_1_PWM_0		332
350 #define IMX_SC_R_PI_1_PWM_1		333
351 #define IMX_SC_R_PI_1_I2C_0		334
352 #define IMX_SC_R_PI_1_PLL		335
353 #define IMX_SC_R_SC_PID0		336
354 #define IMX_SC_R_SC_PID1		337
355 #define IMX_SC_R_SC_PID2		338
356 #define IMX_SC_R_SC_PID3		339
357 #define IMX_SC_R_SC_PID4		340
358 #define IMX_SC_R_SC_SEMA42		341
359 #define IMX_SC_R_SC_TPM			342
360 #define IMX_SC_R_SC_PIT			343
361 #define IMX_SC_R_SC_UART		344
362 #define IMX_SC_R_SC_I2C			345
363 #define IMX_SC_R_SC_MU_0B		346
364 #define IMX_SC_R_SC_MU_0A0		347
365 #define IMX_SC_R_SC_MU_0A1		348
366 #define IMX_SC_R_SC_MU_0A2		349
367 #define IMX_SC_R_SC_MU_0A3		350
368 #define IMX_SC_R_SC_MU_1A		351
369 #define IMX_SC_R_SYSCNT_RD		352
370 #define IMX_SC_R_SYSCNT_CMP		353
371 #define IMX_SC_R_DEBUG			354
372 #define IMX_SC_R_SYSTEM			355
373 #define IMX_SC_R_SNVS			356
374 #define IMX_SC_R_OTP			357
375 #define IMX_SC_R_VPU_PID0		358
376 #define IMX_SC_R_VPU_PID1		359
377 #define IMX_SC_R_VPU_PID2		360
378 #define IMX_SC_R_VPU_PID3		361
379 #define IMX_SC_R_VPU_PID4		362
380 #define IMX_SC_R_VPU_PID5		363
381 #define IMX_SC_R_VPU_PID6		364
382 #define IMX_SC_R_VPU_PID7		365
383 #define IMX_SC_R_ENET_0_A2		366
384 #define IMX_SC_R_ENET_1_A0		367
385 #define IMX_SC_R_ENET_1_A1		368
386 #define IMX_SC_R_ENET_1_A2		369
387 #define IMX_SC_R_ENET_1_A3		370
388 #define IMX_SC_R_ENET_1_A4		371
389 #define IMX_SC_R_DMA_4_CH0		372
390 #define IMX_SC_R_DMA_4_CH1		373
391 #define IMX_SC_R_DMA_4_CH2		374
392 #define IMX_SC_R_DMA_4_CH3		375
393 #define IMX_SC_R_DMA_4_CH4		376
394 #define IMX_SC_R_ISI_0_CH0		377
395 #define IMX_SC_R_ISI_0_CH1		378
396 #define IMX_SC_R_ISI_0_CH2		379
397 #define IMX_SC_R_ISI_0_CH3		380
398 #define IMX_SC_R_ISI_0_CH4		381
399 #define IMX_SC_R_ISI_0_CH5		382
400 #define IMX_SC_R_ISI_0_CH6		383
401 #define IMX_SC_R_ISI_0_CH7		384
402 #define IMX_SC_R_MJPEG_0_DEC_S0		385
403 #define IMX_SC_R_MJPEG_0_DEC_S1		386
404 #define IMX_SC_R_MJPEG_0_DEC_S2		387
405 #define IMX_SC_R_MJPEG_0_DEC_S3		388
406 #define IMX_SC_R_MJPEG_0_ENC_S0		389
407 #define IMX_SC_R_MJPEG_0_ENC_S1		390
408 #define IMX_SC_R_MJPEG_0_ENC_S2		391
409 #define IMX_SC_R_MJPEG_0_ENC_S3		392
410 #define IMX_SC_R_MIPI_0			393
411 #define IMX_SC_R_MIPI_0_PWM_0		394
412 #define IMX_SC_R_MIPI_0_I2C_0		395
413 #define IMX_SC_R_MIPI_0_I2C_1		396
414 #define IMX_SC_R_MIPI_1			397
415 #define IMX_SC_R_MIPI_1_PWM_0		398
416 #define IMX_SC_R_MIPI_1_I2C_0		399
417 #define IMX_SC_R_MIPI_1_I2C_1		400
418 #define IMX_SC_R_CSI_0			401
419 #define IMX_SC_R_CSI_0_PWM_0		402
420 #define IMX_SC_R_CSI_0_I2C_0		403
421 #define IMX_SC_R_CSI_1			404
422 #define IMX_SC_R_CSI_1_PWM_0		405
423 #define IMX_SC_R_CSI_1_I2C_0		406
424 #define IMX_SC_R_HDMI			407
425 #define IMX_SC_R_HDMI_I2S		408
426 #define IMX_SC_R_HDMI_I2C_0		409
427 #define IMX_SC_R_HDMI_PLL_0		410
428 #define IMX_SC_R_HDMI_RX		411
429 #define IMX_SC_R_HDMI_RX_BYPASS		412
430 #define IMX_SC_R_HDMI_RX_I2C_0		413
431 #define IMX_SC_R_ASRC_0			414
432 #define IMX_SC_R_ESAI_0			415
433 #define IMX_SC_R_SPDIF_0		416
434 #define IMX_SC_R_SPDIF_1		417
435 #define IMX_SC_R_SAI_3			418
436 #define IMX_SC_R_SAI_4			419
437 #define IMX_SC_R_SAI_5			420
438 #define IMX_SC_R_GPT_5			421
439 #define IMX_SC_R_GPT_6			422
440 #define IMX_SC_R_GPT_7			423
441 #define IMX_SC_R_GPT_8			424
442 #define IMX_SC_R_GPT_9			425
443 #define IMX_SC_R_GPT_10			426
444 #define IMX_SC_R_DMA_2_CH5		427
445 #define IMX_SC_R_DMA_2_CH6		428
446 #define IMX_SC_R_DMA_2_CH7		429
447 #define IMX_SC_R_DMA_2_CH8		430
448 #define IMX_SC_R_DMA_2_CH9		431
449 #define IMX_SC_R_DMA_2_CH10		432
450 #define IMX_SC_R_DMA_2_CH11		433
451 #define IMX_SC_R_DMA_2_CH12		434
452 #define IMX_SC_R_DMA_2_CH13		435
453 #define IMX_SC_R_DMA_2_CH14		436
454 #define IMX_SC_R_DMA_2_CH15		437
455 #define IMX_SC_R_DMA_2_CH16		438
456 #define IMX_SC_R_DMA_2_CH17		439
457 #define IMX_SC_R_DMA_2_CH18		440
458 #define IMX_SC_R_DMA_2_CH19		441
459 #define IMX_SC_R_DMA_2_CH20		442
460 #define IMX_SC_R_DMA_2_CH21		443
461 #define IMX_SC_R_DMA_2_CH22		444
462 #define IMX_SC_R_DMA_2_CH23		445
463 #define IMX_SC_R_DMA_2_CH24		446
464 #define IMX_SC_R_DMA_2_CH25		447
465 #define IMX_SC_R_DMA_2_CH26		448
466 #define IMX_SC_R_DMA_2_CH27		449
467 #define IMX_SC_R_DMA_2_CH28		450
468 #define IMX_SC_R_DMA_2_CH29		451
469 #define IMX_SC_R_DMA_2_CH30		452
470 #define IMX_SC_R_DMA_2_CH31		453
471 #define IMX_SC_R_ASRC_1			454
472 #define IMX_SC_R_ESAI_1			455
473 #define IMX_SC_R_SAI_6			456
474 #define IMX_SC_R_SAI_7			457
475 #define IMX_SC_R_AMIX			458
476 #define IMX_SC_R_MQS_0			459
477 #define IMX_SC_R_DMA_3_CH0		460
478 #define IMX_SC_R_DMA_3_CH1		461
479 #define IMX_SC_R_DMA_3_CH2		462
480 #define IMX_SC_R_DMA_3_CH3		463
481 #define IMX_SC_R_DMA_3_CH4		464
482 #define IMX_SC_R_DMA_3_CH5		465
483 #define IMX_SC_R_DMA_3_CH6		466
484 #define IMX_SC_R_DMA_3_CH7		467
485 #define IMX_SC_R_DMA_3_CH8		468
486 #define IMX_SC_R_DMA_3_CH9		469
487 #define IMX_SC_R_DMA_3_CH10		470
488 #define IMX_SC_R_DMA_3_CH11		471
489 #define IMX_SC_R_DMA_3_CH12		472
490 #define IMX_SC_R_DMA_3_CH13		473
491 #define IMX_SC_R_DMA_3_CH14		474
492 #define IMX_SC_R_DMA_3_CH15		475
493 #define IMX_SC_R_DMA_3_CH16		476
494 #define IMX_SC_R_DMA_3_CH17		477
495 #define IMX_SC_R_DMA_3_CH18		478
496 #define IMX_SC_R_DMA_3_CH19		479
497 #define IMX_SC_R_DMA_3_CH20		480
498 #define IMX_SC_R_DMA_3_CH21		481
499 #define IMX_SC_R_DMA_3_CH22		482
500 #define IMX_SC_R_DMA_3_CH23		483
501 #define IMX_SC_R_DMA_3_CH24		484
502 #define IMX_SC_R_DMA_3_CH25		485
503 #define IMX_SC_R_DMA_3_CH26		486
504 #define IMX_SC_R_DMA_3_CH27		487
505 #define IMX_SC_R_DMA_3_CH28		488
506 #define IMX_SC_R_DMA_3_CH29		489
507 #define IMX_SC_R_DMA_3_CH30		490
508 #define IMX_SC_R_DMA_3_CH31		491
509 #define IMX_SC_R_AUDIO_PLL_1		492
510 #define IMX_SC_R_AUDIO_CLK_0		493
511 #define IMX_SC_R_AUDIO_CLK_1		494
512 #define IMX_SC_R_MCLK_OUT_0		495
513 #define IMX_SC_R_MCLK_OUT_1		496
514 #define IMX_SC_R_PMIC_0			497
515 #define IMX_SC_R_PMIC_1			498
516 #define IMX_SC_R_SECO			499
517 #define IMX_SC_R_CAAM_JR1		500
518 #define IMX_SC_R_CAAM_JR2		501
519 #define IMX_SC_R_CAAM_JR3		502
520 #define IMX_SC_R_SECO_MU_2		503
521 #define IMX_SC_R_SECO_MU_3		504
522 #define IMX_SC_R_SECO_MU_4		505
523 #define IMX_SC_R_HDMI_RX_PWM_0		506
524 #define IMX_SC_R_AP_2			507
525 #define IMX_SC_R_AP_2_0			508
526 #define IMX_SC_R_AP_2_1			509
527 #define IMX_SC_R_AP_2_2			510
528 #define IMX_SC_R_AP_2_3			511
529 #define IMX_SC_R_DSP			512
530 #define IMX_SC_R_DSP_RAM		513
531 #define IMX_SC_R_CAAM_JR1_OUT		514
532 #define IMX_SC_R_CAAM_JR2_OUT		515
533 #define IMX_SC_R_CAAM_JR3_OUT		516
534 #define IMX_SC_R_VPU_DEC_0		517
535 #define IMX_SC_R_VPU_ENC_0		518
536 #define IMX_SC_R_CAAM_JR0		519
537 #define IMX_SC_R_CAAM_JR0_OUT		520
538 #define IMX_SC_R_PMIC_2			521
539 #define IMX_SC_R_DBLOGIC		522
540 #define IMX_SC_R_HDMI_PLL_1		523
541 #define IMX_SC_R_BOARD_R0		524
542 #define IMX_SC_R_BOARD_R1		525
543 #define IMX_SC_R_BOARD_R2		526
544 #define IMX_SC_R_BOARD_R3		527
545 #define IMX_SC_R_BOARD_R4		528
546 #define IMX_SC_R_BOARD_R5		529
547 #define IMX_SC_R_BOARD_R6		530
548 #define IMX_SC_R_BOARD_R7		531
549 #define IMX_SC_R_MJPEG_0_DEC_MP		532
550 #define IMX_SC_R_MJPEG_0_ENC_MP		533
551 #define IMX_SC_R_VPU_TS_0		534
552 #define IMX_SC_R_VPU_MU_0		535
553 #define IMX_SC_R_VPU_MU_1		536
554 #define IMX_SC_R_VPU_MU_2		537
555 #define IMX_SC_R_VPU_MU_3		538
556 #define IMX_SC_R_VPU_ENC_1		539
557 #define IMX_SC_R_VPU			540
558 #define IMX_SC_R_DMA_5_CH0		541
559 #define IMX_SC_R_DMA_5_CH1		542
560 #define IMX_SC_R_DMA_5_CH2		543
561 #define IMX_SC_R_DMA_5_CH3		544
562 #define IMX_SC_R_ATTESTATION		545
563 #define IMX_SC_R_LAST			546
564 
565 /*
566  * Defines for SC PM CLK
567  */
568 #define IMX_SC_PM_CLK_SLV_BUS		0	/* Slave bus clock */
569 #define IMX_SC_PM_CLK_MST_BUS		1	/* Master bus clock */
570 #define IMX_SC_PM_CLK_PER		2	/* Peripheral clock */
571 #define IMX_SC_PM_CLK_PHY		3	/* Phy clock */
572 #define IMX_SC_PM_CLK_MISC		4	/* Misc clock */
573 #define IMX_SC_PM_CLK_MISC0		0	/* Misc 0 clock */
574 #define IMX_SC_PM_CLK_MISC1		1	/* Misc 1 clock */
575 #define IMX_SC_PM_CLK_MISC2		2	/* Misc 2 clock */
576 #define IMX_SC_PM_CLK_MISC3		3	/* Misc 3 clock */
577 #define IMX_SC_PM_CLK_MISC4		4	/* Misc 4 clock */
578 #define IMX_SC_PM_CLK_CPU		2	/* CPU clock */
579 #define IMX_SC_PM_CLK_PLL		4	/* PLL */
580 #define IMX_SC_PM_CLK_BYPASS		4	/* Bypass clock */
581 
582 /*
583  * Compatibility defines for sc_rsrc_t
584  */
585 #define IMX_SC_R_A35			IMX_SC_R_AP_2
586 #define IMX_SC_R_A35_0			IMX_SC_R_AP_2_0
587 #define IMX_SC_R_A35_1			IMX_SC_R_AP_2_1
588 #define IMX_SC_R_A35_2			IMX_SC_R_AP_2_2
589 #define IMX_SC_R_A35_3			IMX_SC_R_AP_2_3
590 #define IMX_SC_R_A53			IMX_SC_R_AP_0
591 #define IMX_SC_R_A53_0			IMX_SC_R_AP_0_0
592 #define IMX_SC_R_A53_1			IMX_SC_R_AP_0_1
593 #define IMX_SC_R_A53_2			IMX_SC_R_AP_0_2
594 #define IMX_SC_R_A53_3			IMX_SC_R_AP_0_3
595 #define IMX_SC_R_A72			IMX_SC_R_AP_1
596 #define IMX_SC_R_A72_0			IMX_SC_R_AP_1_0
597 #define IMX_SC_R_A72_1			IMX_SC_R_AP_1_1
598 #define IMX_SC_R_A72_2			IMX_SC_R_AP_1_2
599 #define IMX_SC_R_A72_3			IMX_SC_R_AP_1_3
600 #define IMX_SC_R_GIC			IMX_SC_R_GIC_0
601 #define IMX_SC_R_HSIO_GPIO		IMX_SC_R_HSIO_GPIO_0
602 #define IMX_SC_R_IEE			IMX_SC_R_IEE_0
603 #define IMX_SC_R_IEE_R0			IMX_SC_R_IEE_0_R0
604 #define IMX_SC_R_IEE_R1			IMX_SC_R_IEE_0_R1
605 #define IMX_SC_R_IEE_R2			IMX_SC_R_IEE_0_R2
606 #define IMX_SC_R_IEE_R3			IMX_SC_R_IEE_0_R3
607 #define IMX_SC_R_IEE_R4			IMX_SC_R_IEE_0_R4
608 #define IMX_SC_R_IEE_R5			IMX_SC_R_IEE_0_R5
609 #define IMX_SC_R_IEE_R6			IMX_SC_R_IEE_0_R6
610 #define IMX_SC_R_IEE_R7			IMX_SC_R_IEE_0_R7
611 #define IMX_SC_R_IRQSTR_M4_0		IMX_SC_R_IRQSTR_MCU_0
612 #define IMX_SC_R_IRQSTR_M4_1		IMX_SC_R_IRQSTR_MCU_1
613 #define IMX_SC_R_IRQSTR_SCU2		IMX_SC_R_IRQSTR_AP_0
614 #define IMX_SC_R_ISI_CH0		IMX_SC_R_ISI_0_CH0
615 #define IMX_SC_R_ISI_CH1		IMX_SC_R_ISI_0_CH1
616 #define IMX_SC_R_ISI_CH2		IMX_SC_R_ISI_0_CH2
617 #define IMX_SC_R_ISI_CH3		IMX_SC_R_ISI_0_CH3
618 #define IMX_SC_R_ISI_CH4		IMX_SC_R_ISI_0_CH4
619 #define IMX_SC_R_ISI_CH5		IMX_SC_R_ISI_0_CH5
620 #define IMX_SC_R_ISI_CH6		IMX_SC_R_ISI_0_CH6
621 #define IMX_SC_R_ISI_CH7		IMX_SC_R_ISI_0_CH7
622 #define IMX_SC_R_M4_0_I2C		IMX_SC_R_MCU_0_I2C
623 #define IMX_SC_R_M4_0_INTMUX		IMX_SC_R_MCU_0_INTMUX
624 #define IMX_SC_R_M4_0_MU_0A0		IMX_SC_R_MCU_0_MU_0A0
625 #define IMX_SC_R_M4_0_MU_0A1		IMX_SC_R_MCU_0_MU_0A1
626 #define IMX_SC_R_M4_0_MU_0A2		IMX_SC_R_MCU_0_MU_0A2
627 #define IMX_SC_R_M4_0_MU_0A3		IMX_SC_R_MCU_0_MU_0A3
628 #define IMX_SC_R_M4_0_MU_0B		IMX_SC_R_MCU_0_MU_0B
629 #define IMX_SC_R_M4_0_MU_1A		IMX_SC_R_MCU_0_MU_1A
630 #define IMX_SC_R_M4_0_PID0		IMX_SC_R_MCU_0_PID0
631 #define IMX_SC_R_M4_0_PID1		IMX_SC_R_MCU_0_PID1
632 #define IMX_SC_R_M4_0_PID2		IMX_SC_R_MCU_0_PID2
633 #define IMX_SC_R_M4_0_PID3		IMX_SC_R_MCU_0_PID3
634 #define IMX_SC_R_M4_0_PID4		IMX_SC_R_MCU_0_PID4
635 #define IMX_SC_R_M4_0_PIT		IMX_SC_R_MCU_0_PIT
636 #define IMX_SC_R_M4_0_RGPIO		IMX_SC_R_MCU_0_RGPIO
637 #define IMX_SC_R_M4_0_SEMA42		IMX_SC_R_MCU_0_SEMA42
638 #define IMX_SC_R_M4_0_TPM		IMX_SC_R_MCU_0_TPM
639 #define IMX_SC_R_M4_0_UART		IMX_SC_R_MCU_0_UART
640 #define IMX_SC_R_M4_1_I2C		IMX_SC_R_MCU_1_I2C
641 #define IMX_SC_R_M4_1_INTMUX		IMX_SC_R_MCU_1_INTMUX
642 #define IMX_SC_R_M4_1_MU_0A0		IMX_SC_R_MCU_1_MU_0A0
643 #define IMX_SC_R_M4_1_MU_0A1		IMX_SC_R_MCU_1_MU_0A1
644 #define IMX_SC_R_M4_1_MU_0A2		IMX_SC_R_MCU_1_MU_0A2
645 #define IMX_SC_R_M4_1_MU_0A3		IMX_SC_R_MCU_1_MU_0A3
646 #define IMX_SC_R_M4_1_MU_0B		IMX_SC_R_MCU_1_MU_0B
647 #define IMX_SC_R_M4_1_MU_1A		IMX_SC_R_MCU_1_MU_1A
648 #define IMX_SC_R_M4_1_PID0		IMX_SC_R_MCU_1_PID0
649 #define IMX_SC_R_M4_1_PID1		IMX_SC_R_MCU_1_PID1
650 #define IMX_SC_R_M4_1_PID2		IMX_SC_R_MCU_1_PID2
651 #define IMX_SC_R_M4_1_PID3		IMX_SC_R_MCU_1_PID3
652 #define IMX_SC_R_M4_1_PID4		IMX_SC_R_MCU_1_PID4
653 #define IMX_SC_R_M4_1_PIT		IMX_SC_R_MCU_1_PIT
654 #define IMX_SC_R_M4_1_RGPIO		IMX_SC_R_MCU_1_RGPIO
655 #define IMX_SC_R_M4_1_SEMA42		IMX_SC_R_MCU_1_SEMA42
656 #define IMX_SC_R_M4_1_TPM		IMX_SC_R_MCU_1_TPM
657 #define IMX_SC_R_M4_1_UART		IMX_SC_R_MCU_1_UART
658 #define IMX_SC_R_MJPEG_DEC_MP		IMX_SC_R_MJPEG_0_DEC_MP
659 #define IMX_SC_R_MJPEG_DEC_S0		IMX_SC_R_MJPEG_0_DEC_S0
660 #define IMX_SC_R_MJPEG_DEC_S1		IMX_SC_R_MJPEG_0_DEC_S1
661 #define IMX_SC_R_MJPEG_DEC_S2		IMX_SC_R_MJPEG_0_DEC_S2
662 #define IMX_SC_R_MJPEG_DEC_S3		IMX_SC_R_MJPEG_0_DEC_S3
663 #define IMX_SC_R_MJPEG_ENC_MP		IMX_SC_R_MJPEG_0_ENC_MP
664 #define IMX_SC_R_MJPEG_ENC_S0		IMX_SC_R_MJPEG_0_ENC_S0
665 #define IMX_SC_R_MJPEG_ENC_S1		IMX_SC_R_MJPEG_0_ENC_S1
666 #define IMX_SC_R_MJPEG_ENC_S2		IMX_SC_R_MJPEG_0_ENC_S2
667 #define IMX_SC_R_MJPEG_ENC_S3		IMX_SC_R_MJPEG_0_ENC_S3
668 #define IMX_SC_R_PERF			IMX_SC_R_PERF_0
669 #define IMX_SC_R_SMMU			IMX_SC_R_SMMU_0
670 #define IMX_SC_R_VPU_UART		IMX_SC_R_ENET_0_A2
671 #define IMX_SC_R_VPUCORE		IMX_SC_R_ENET_1_A0
672 #define IMX_SC_R_VPUCORE_0		IMX_SC_R_ENET_1_A1
673 #define IMX_SC_R_VPUCORE_1		IMX_SC_R_ENET_1_A2
674 #define IMX_SC_R_VPUCORE_2		IMX_SC_R_ENET_1_A3
675 #define IMX_SC_R_VPUCORE_3		IMX_SC_R_ENET_1_A4
676 #define IMX_SC_R_UNUSED1		IMX_SC_R_V2X_PID0
677 #define IMX_SC_R_UNUSED2		IMX_SC_R_V2X_PID1
678 #define IMX_SC_R_UNUSED3		IMX_SC_R_V2X_PID2
679 #define IMX_SC_R_UNUSED4		IMX_SC_R_V2X_PID3
680 
681 /*
682  * Defines for SC CONTROL
683  */
684 #define IMX_SC_C_TEMP				0
685 #define IMX_SC_C_TEMP_HI			1
686 #define IMX_SC_C_TEMP_LOW			2
687 #define IMX_SC_C_PXL_LINK_MST1_ADDR		3
688 #define IMX_SC_C_PXL_LINK_MST2_ADDR		4
689 #define IMX_SC_C_PXL_LINK_MST_ENB		5
690 #define IMX_SC_C_PXL_LINK_MST1_ENB		6
691 #define IMX_SC_C_PXL_LINK_MST2_ENB		7
692 #define IMX_SC_C_PXL_LINK_SLV1_ADDR		8
693 #define IMX_SC_C_PXL_LINK_SLV2_ADDR		9
694 #define IMX_SC_C_PXL_LINK_MST_VLD		10
695 #define IMX_SC_C_PXL_LINK_MST1_VLD		11
696 #define IMX_SC_C_PXL_LINK_MST2_VLD		12
697 #define IMX_SC_C_SINGLE_MODE			13
698 #define IMX_SC_C_ID				14
699 #define IMX_SC_C_PXL_CLK_POLARITY		15
700 #define IMX_SC_C_LINESTATE			16
701 #define IMX_SC_C_PCIE_G_RST			17
702 #define IMX_SC_C_PCIE_BUTTON_RST		18
703 #define IMX_SC_C_PCIE_PERST			19
704 #define IMX_SC_C_PHY_RESET			20
705 #define IMX_SC_C_PXL_LINK_RATE_CORRECTION	21
706 #define IMX_SC_C_PANIC				22
707 #define IMX_SC_C_PRIORITY_GROUP			23
708 #define IMX_SC_C_TXCLK				24
709 #define IMX_SC_C_CLKDIV				25
710 #define IMX_SC_C_DISABLE_50			26
711 #define IMX_SC_C_DISABLE_125			27
712 #define IMX_SC_C_SEL_125			28
713 #define IMX_SC_C_MODE				29
714 #define IMX_SC_C_SYNC_CTRL0			30
715 #define IMX_SC_C_KACHUNK_CNT			31
716 #define IMX_SC_C_KACHUNK_SEL			32
717 #define IMX_SC_C_SYNC_CTRL1			33
718 #define IMX_SC_C_DPI_RESET			34
719 #define IMX_SC_C_MIPI_RESET			35
720 #define IMX_SC_C_DUAL_MODE			36
721 #define IMX_SC_C_VOLTAGE			37
722 #define IMX_SC_C_PXL_LINK_SEL			38
723 #define IMX_SC_C_OFS_SEL			39
724 #define IMX_SC_C_OFS_AUDIO			40
725 #define IMX_SC_C_OFS_PERIPH			41
726 #define IMX_SC_C_OFS_IRQ			42
727 #define IMX_SC_C_RST0				43
728 #define IMX_SC_C_RST1				44
729 #define IMX_SC_C_SEL0				45
730 #define IMX_SC_C_CALIB0				46
731 #define IMX_SC_C_CALIB1				47
732 #define IMX_SC_C_CALIB2				48
733 #define IMX_SC_C_IPG_DEBUG			49
734 #define IMX_SC_C_IPG_DOZE			50
735 #define IMX_SC_C_IPG_WAIT			51
736 #define IMX_SC_C_IPG_STOP			52
737 #define IMX_SC_C_IPG_STOP_MODE			53
738 #define IMX_SC_C_IPG_STOP_ACK			54
739 #define IMX_SC_C_SYNC_CTRL			55
740 #define IMX_SC_C_OFS_AUDIO_ALT			56
741 #define IMX_SC_C_DSP_BYP			57
742 #define IMX_SC_C_CLK_GEN_EN			58
743 #define IMX_SC_C_INTF_SEL			59
744 #define IMX_SC_C_RXC_DLY			60
745 #define IMX_SC_C_TIMER_SEL			61
746 #define IMX_SC_C_MISC0				62
747 #define IMX_SC_C_MISC1				63
748 #define IMX_SC_C_MISC2				64
749 #define IMX_SC_C_MISC3				65
750 #define IMX_SC_C_LAST				66
751 
752 #endif /* __DT_BINDINGS_RSCRC_IMX_H */
753