Searched refs:IMX95_CLK_SYSPLL1_PFD1_DIV2 (Results 1 – 2 of 2) sorted by relevance
724 assigned-clock-parents = <&scmi_clk IMX95_CLK_SYSPLL1_PFD1_DIV2>;738 assigned-clock-parents = <&scmi_clk IMX95_CLK_SYSPLL1_PFD1_DIV2>;971 assigned-clock-parents = <&scmi_clk IMX95_CLK_SYSPLL1_PFD1_DIV2>;985 assigned-clock-parents = <&scmi_clk IMX95_CLK_SYSPLL1_PFD1_DIV2>;1272 assigned-clock-parents = <&scmi_clk IMX95_CLK_SYSPLL1_PFD1_DIV2>;1510 <&scmi_clk IMX95_CLK_SYSPLL1_PFD1_DIV2>;1538 <&scmi_clk IMX95_CLK_SYSPLL1_PFD1_DIV2>;1577 <&scmi_clk IMX95_CLK_SYSPLL1_PFD1_DIV2>;1605 <&scmi_clk IMX95_CLK_SYSPLL1_PFD1_DIV2>;1616 assigned-clock-parents = <&scmi_clk IMX95_CLK_SYSPLL1_PFD1_DIV2>;
19 #define IMX95_CLK_SYSPLL1_PFD1_DIV2 10 macro