| /freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
| H A D | HexagonCopyToCombine.cpp | 799 Register HiReg = HiOperand.getReg(); in emitCombineRI() local
807 .addReg(HiReg, HiRegKillFlag) in emitCombineRI()
815 .addReg(HiReg, HiRegKillFlag) in emitCombineRI()
839 .addReg(HiReg, HiRegKillFlag) in emitCombineRI()
850 Register HiReg = HiOperand.getReg(); in emitCombineRR() local
867 .addReg(HiReg, HiRegKillFlag) in emitCombineRR()
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| H A D | HexagonPatterns.td | 129 def HiReg: OutPatFrag<(ops node:$Rs), (EXTRACT_SUBREG $Rs, isub_hi)>;
552 (Combinew (A2_sxtb (HiReg $Rs)), (A2_sxtb (LoReg $Rs)))>;
555 (Combinew (A2_sxth (HiReg $Rs)), (A2_sxth (LoReg $Rs)))>;
571 (A2_combine_ll (HiReg $Rs), (LoReg $Rs))>;
578 (A4_vcmpheqi (Combinew (A2_andir (HiReg $Rs), (i32 0x00010001)),
582 (A4_vcmpbeqi (Combinew (A2_andir (HiReg $Rs), (i32 0x01010101)),
586 (A4_vcmpheqi (Combinew (A2_andir (HiReg (S2_vzxtbh $Rs)), 0x00010001),
603 (C2_mux (C2_cmpeqi (HiReg $Rs), (i32 0)), (LoReg $Rs), (i32 -1))>;
963 (Combinew (C2_mux I1:$Pu, (HiReg $Rs), (HiReg $Rt)),
967 (Combinew (C2_mux I1:$Pu, (HiReg $Rs), (HiReg $Rt)),
[all …]
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| H A D | HexagonIntrinsics.td | 95 (A2_combinew (HiReg I64:$Rs), (LoReg I64:$Rs))>;
97 (A2_combinew (HiReg I64:$Rs), (LoReg I64:$Rs))>;
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| H A D | HexagonFrameLowering.cpp | 1118 Register HiReg = HRI.getSubReg(Reg, Hexagon::isub_hi); in insertCFIInstructionsAt() local
1120 unsigned HiDwarfReg = HRI.getDwarfRegNum(HiReg, true); in insertCFIInstructionsAt()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AVR/ |
| H A D | AVRRegisterInfo.h | 52 void splitReg(Register Reg, Register &LoReg, Register &HiReg) const;
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| H A D | AVRRegisterInfo.cpp | 301 Register &HiReg) const { in splitReg()
305 HiReg = getSubReg(Reg, AVR::sub_hi); in splitReg()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Sparc/ |
| H A D | SparcAsmPrinter.cpp | 443 Register HiReg, LoReg; in PrintAsmOperand() local
463 HiReg = RegisterInfo->getSubReg(MOReg, SP::sub_even); in PrintAsmOperand()
472 Reg = HiReg; in PrintAsmOperand()
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| H A D | SparcISelLowering.cpp | 1315 Register HiReg = VA.getLocReg(); in LowerCall_64() local
1318 HiReg = toCallerWindow(HiReg); in LowerCall_64()
1322 RegsToPass.push_back(std::make_pair(HiReg, Hi64)); in LowerCall_64()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | AMDGPUInstructionSelector.cpp | 1643 Register HiReg = MRI->createVirtualRegister(&AMDGPU::SReg_32RegClass); in selectBallot() local
1644 BuildMI(*BB, &I, DL, TII.get(AMDGPU::S_MOV_B32), HiReg).addImm(0); in selectBallot()
1648 .addReg(HiReg) in selectBallot()
2477 Register HiReg = MRI->createVirtualRegister(DstRC); in selectG_TRUNC() local
2480 BuildMI(*MBB, I, DL, TII.get(AMDGPU::COPY), HiReg) in selectG_TRUNC()
2489 .addReg(HiReg) // $src0 in selectG_TRUNC()
2503 .addReg(HiReg); in selectG_TRUNC()
2506 .addReg(HiReg) in selectG_TRUNC()
2669 Register HiReg = MRI->createVirtualRegister(&AMDGPU::SReg_32RegClass); in selectG_SZA_EXT() local
2672 BuildMI(MBB, I, DL, TII.get(AMDGPU::S_ASHR_I32), HiReg) in selectG_SZA_EXT()
[all …]
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| H A D | SILoadStoreOptimizer.cpp | 189 Register HiReg; member
2007 assert((TRI->getRegSizeInBits(Addr.Base.HiReg, *MRI) == 32 || in computeBase()
2034 .addReg(Addr.Base.HiReg, 0, Addr.Base.HiSubReg) in computeBase()
2143 Addr.Base.HiReg = BaseHi.getReg(); in processBaseWithConstOffset()
2190 LLVM_DEBUG(dbgs() << " BASE: {" << printReg(MAddr.Base.HiReg, TRI) << ", " in promoteConstantOffsetToImm()
2250 MAddrNext.Base.HiReg != MAddr.Base.HiReg || in promoteConstantOffsetToImm()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Mips/ |
| H A D | MipsSEFrameLowering.cpp | 307 Register HiReg = I->getOperand(2).getReg(); in expandBuildPairF64() local
323 std::swap(LoReg, HiReg); in expandBuildPairF64()
326 TII.storeRegToStack(MBB, I, HiReg, I->getOperand(2).isKill(), FI, RC, in expandBuildPairF64()
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| H A D | MipsSEInstrInfo.cpp | 798 unsigned LoReg = I->getOperand(1).getReg(), HiReg = I->getOperand(2).getReg(); in expandBuildPairF64() local
846 .addReg(HiReg); in expandBuildPairF64()
851 .addReg(HiReg); in expandBuildPairF64()
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| H A D | MipsISelLowering.cpp | 3131 MCRegister HiReg = State.AllocateReg(IntRegs); in CC_MipsO32() local
3132 assert(HiReg); in CC_MipsO32()
3134 CCValAssign::getCustomReg(ValNo, ValVT, HiReg, LocVT, LocInfo)); in CC_MipsO32()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/ |
| H A D | RISCVCallingConv.cpp | 501 MCRegister HiReg = State.AllocateReg(ArgGPRs); in CC_RISCV() local
502 if (HiReg) { in CC_RISCV()
504 CCValAssign::getCustomReg(ValNo, ValVT, HiReg, LocVT, LocInfo)); in CC_RISCV()
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| H A D | RISCVISelLowering.cpp | 21296 Register HiReg = MI.getOperand(1).getReg(); in emitReadCounterWidePseudo() local
21302 BuildMI(LoopMBB, DL, TII->get(RISCV::CSRRS), HiReg) in emitReadCounterWidePseudo()
21313 .addReg(HiReg) in emitReadCounterWidePseudo()
21335 Register HiReg = MI.getOperand(1).getReg(); in emitSplitF64Pseudo() local
21352 BuildMI(*BB, MI, DL, TII.get(RISCV::LW), HiReg) in emitSplitF64Pseudo()
21372 Register HiReg = MI.getOperand(2).getReg(); in emitBuildPairF64Pseudo() local
21388 .addReg(HiReg, getKillRegState(MI.getOperand(2).isKill())) in emitBuildPairF64Pseudo()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86ISelDAGToDAG.cpp | 5779 unsigned LoReg, HiReg; in Select() local
5795 HiReg = X86::EDX; in Select()
5807 HiReg = X86::RDX; in Select()
5883 assert(HiReg && "Register for high half is not defined!"); in Select()
5884 ResHi = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), dl, HiReg, in Select()
5922 unsigned LoReg, HiReg, ClrReg; in Select() local
5927 LoReg = X86::AL; ClrReg = HiReg = X86::AH; in Select()
5931 LoReg = X86::AX; HiReg = X86::DX; in Select()
5936 LoReg = X86::EAX; ClrReg = HiReg = X86::EDX; in Select()
5940 LoReg = X86::RAX; ClrReg = HiReg = X86::RDX; in Select()
[all …]
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| /freebsd/contrib/llvm-project/llvm/lib/Target/ARM/ |
| H A D | ARMExpandPseudoInsts.cpp | 2103 for (unsigned LoReg = ARM::R7, HiReg = ARM::R11; LoReg >= ARM::R4; in CMSEPushCalleeSaves() local
2108 .addReg(HiReg, LiveRegs.contains(HiReg) ? 0 : RegState::Undef) in CMSEPushCalleeSaves()
2110 --HiReg; in CMSEPushCalleeSaves()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/LoongArch/ |
| H A D | LoongArchISelLowering.cpp | 6232 Register HiReg = MI.getOperand(1).getReg(); in emitSplitPairF64Pseudo() local
6236 BuildMI(*BB, MI, DL, TII.get(LoongArch::MOVFRH2GR_S), HiReg) in emitSplitPairF64Pseudo()
6255 Register HiReg = MI.getOperand(2).getReg(); in emitBuildPairF64Pseudo() local
6261 .addReg(HiReg, getKillRegState(MI.getOperand(2).isKill())); in emitBuildPairF64Pseudo()
6776 MCRegister HiReg = State.AllocateReg(ArgGPRs); in CC_LoongArch() local
6777 if (HiReg) { in CC_LoongArch()
6779 CCValAssign::getCustomReg(ValNo, ValVT, HiReg, LocVT, LocInfo)); in CC_LoongArch()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/ARM/AsmParser/ |
| H A D | ARMAsmParser.cpp | 7495 MCRegister Reg, MCRegister HiReg, in checkLowRegisterList() argument
7503 if (!isARMLowRegister(OpReg) && (!HiReg || OpReg != HiReg)) in checkLowRegisterList()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/ |
| H A D | PPCISelLowering.cpp | 13872 Register HiReg = MI.getOperand(1).getReg(); in EmitInstrWithCustomInserter() local
13874 BuildMI(BB, dl, TII->get(PPC::MFSPR), HiReg).addImm(269); in EmitInstrWithCustomInserter()
13881 .addReg(HiReg) in EmitInstrWithCustomInserter()
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