| /freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
| H A D | HexagonCopyToCombine.cpp | 806 Register HiReg = HiOperand.getReg(); in emitCombineRI() local
814 .addReg(HiReg, HiRegKillFlag) in emitCombineRI()
822 .addReg(HiReg, HiRegKillFlag) in emitCombineRI()
846 .addReg(HiReg, HiRegKillFlag) in emitCombineRI()
857 Register HiReg = HiOperand.getReg(); in emitCombineRR() local
874 .addReg(HiReg, HiRegKillFlag) in emitCombineRR()
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| H A D | HexagonPatterns.td | 121 def HiReg: OutPatFrag<(ops node:$Rs), (EXTRACT_SUBREG $Rs, isub_hi)>;
544 (Combinew (A2_sxtb (HiReg $Rs)), (A2_sxtb (LoReg $Rs)))>;
547 (Combinew (A2_sxth (HiReg $Rs)), (A2_sxth (LoReg $Rs)))>;
563 (A2_combine_ll (HiReg $Rs), (LoReg $Rs))>;
570 (A4_vcmpheqi (Combinew (A2_andir (HiReg $Rs), (i32 0x00010001)),
574 (A4_vcmpbeqi (Combinew (A2_andir (HiReg $Rs), (i32 0x01010101)),
588 (C2_mux (C2_cmpeqi (HiReg $Rs), (i32 0)), (LoReg $Rs), (i32 -1))>;
938 (Combinew (C2_mux I1:$Pu, (HiReg $Rs), (HiReg $Rt)),
942 (Combinew (C2_mux I1:$Pu, (HiReg $Rs), (HiReg $Rt)),
952 (Combinew (C2_mux I1:$Pu, (HiReg $Rs), (HiReg $Rt)),
[all …]
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| H A D | HexagonIntrinsics.td | 95 (A2_combinew (HiReg I64:$Rs), (LoReg I64:$Rs))>;
97 (A2_combinew (HiReg I64:$Rs), (LoReg I64:$Rs))>;
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| H A D | HexagonFrameLowering.cpp | 1128 Register HiReg = HRI.getSubReg(Reg, Hexagon::isub_hi); in insertCFIInstructionsAt() local
1130 unsigned HiDwarfReg = HRI.getDwarfRegNum(HiReg, true); in insertCFIInstructionsAt()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AVR/ |
| H A D | AVRRegisterInfo.h | 52 void splitReg(Register Reg, Register &LoReg, Register &HiReg) const;
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| H A D | AVRRegisterInfo.cpp | 306 Register &HiReg) const { in splitReg()
310 HiReg = getSubReg(Reg, AVR::sub_hi); in splitReg()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Sparc/ |
| H A D | SparcAsmPrinter.cpp | 394 Register HiReg, LoReg; in PrintAsmOperand() local
414 HiReg = RegisterInfo->getSubReg(MOReg, SP::sub_even); in PrintAsmOperand()
423 Reg = HiReg; in PrintAsmOperand()
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| H A D | SparcISelLowering.cpp | 1320 Register HiReg = VA.getLocReg(); in LowerCall_64() local
1323 HiReg = toCallerWindow(HiReg); in LowerCall_64()
1327 RegsToPass.push_back(std::make_pair(HiReg, Hi64)); in LowerCall_64()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | AMDGPUInstructionSelector.cpp | 1425 Register HiReg = MRI->createVirtualRegister(&AMDGPU::SReg_32RegClass); in selectBallot() local
1426 BuildMI(*BB, &I, DL, TII.get(AMDGPU::S_MOV_B32), HiReg).addImm(0); in selectBallot()
1430 .addReg(HiReg) in selectBallot()
2235 Register HiReg = MRI->createVirtualRegister(DstRC); in selectG_TRUNC() local
2238 BuildMI(*MBB, I, DL, TII.get(AMDGPU::COPY), HiReg) in selectG_TRUNC()
2247 .addReg(HiReg) // $src0 in selectG_TRUNC()
2261 .addReg(HiReg); in selectG_TRUNC()
2264 .addReg(HiReg) in selectG_TRUNC()
2425 Register HiReg = MRI->createVirtualRegister(&AMDGPU::SReg_32RegClass); in selectG_SZA_EXT() local
2428 BuildMI(MBB, I, DL, TII.get(AMDGPU::S_ASHR_I32), HiReg) in selectG_SZA_EXT()
[all …]
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| H A D | SILoadStoreOptimizer.cpp | 188 Register HiReg; member
1946 assert((TRI->getRegSizeInBits(Addr.Base.HiReg, *MRI) == 32 || in computeBase()
1973 .addReg(Addr.Base.HiReg, 0, Addr.Base.HiSubReg) in computeBase()
2076 Addr.Base.HiReg = BaseHi.getReg(); in processBaseWithConstOffset()
2122 LLVM_DEBUG(dbgs() << " BASE: {" << MAddr.Base.HiReg << ", " in promoteConstantOffsetToImm()
2180 MAddrNext.Base.HiReg != MAddr.Base.HiReg || in promoteConstantOffsetToImm()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Mips/ |
| H A D | MipsSEFrameLowering.cpp | 309 Register HiReg = I->getOperand(2).getReg(); in expandBuildPairF64() local
325 std::swap(LoReg, HiReg); in expandBuildPairF64()
328 TII.storeRegToStack(MBB, I, HiReg, I->getOperand(2).isKill(), FI, RC, in expandBuildPairF64()
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| H A D | MipsSEInstrInfo.cpp | 798 unsigned LoReg = I->getOperand(1).getReg(), HiReg = I->getOperand(2).getReg(); in expandBuildPairF64() local
846 .addReg(HiReg); in expandBuildPairF64()
851 .addReg(HiReg); in expandBuildPairF64()
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| H A D | MipsISelLowering.cpp | 2979 MCRegister HiReg = State.AllocateReg(IntRegs); in CC_MipsO32() local
2980 assert(HiReg); in CC_MipsO32()
2982 CCValAssign::getCustomReg(ValNo, ValVT, HiReg, LocVT, LocInfo)); in CC_MipsO32()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86ISelDAGToDAG.cpp | 5622 unsigned LoReg, HiReg; in Select() local
5638 HiReg = X86::EDX; in Select()
5650 HiReg = X86::RDX; in Select()
5726 assert(HiReg && "Register for high half is not defined!"); in Select()
5727 ResHi = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), dl, HiReg, in Select()
5765 unsigned LoReg, HiReg, ClrReg; in Select() local
5770 LoReg = X86::AL; ClrReg = HiReg = X86::AH; in Select()
5774 LoReg = X86::AX; HiReg = X86::DX; in Select()
5779 LoReg = X86::EAX; ClrReg = HiReg = X86::EDX; in Select()
5783 LoReg = X86::RAX; ClrReg = HiReg = X86::RDX; in Select()
[all …]
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| /freebsd/contrib/llvm-project/llvm/lib/Target/ARM/ |
| H A D | ARMExpandPseudoInsts.cpp | 2062 for (int LoReg = ARM::R7, HiReg = ARM::R11; LoReg >= ARM::R4; --LoReg) { in CMSEPushCalleeSaves() local
2066 .addReg(HiReg, LiveRegs.contains(HiReg) ? 0 : RegState::Undef) in CMSEPushCalleeSaves()
2068 --HiReg; in CMSEPushCalleeSaves()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/ |
| H A D | RISCVISelLowering.cpp | 18135 Register HiReg = MI.getOperand(1).getReg(); in emitReadCounterWidePseudo()
18141 BuildMI(LoopMBB, DL, TII->get(RISCV::CSRRS), HiReg) in emitReadCounterWidePseudo()
18152 .addReg(HiReg) in emitReadCounterWidePseudo()
18174 Register HiReg = MI.getOperand(1).getReg(); in emitSplitF64Pseudo()
18191 BuildMI(*BB, MI, DL, TII.get(RISCV::LW), HiReg) in emitSplitF64Pseudo()
18211 Register HiReg = MI.getOperand(2).getReg(); in emitBuildPairF64Pseudo()
18227 .addReg(HiReg, getKillRegState(MI.getOperand(2).isKill())) in emitBuildPairF64Pseudo()
19108 Register HiReg = State.AllocateReg(ArgGPRs); in CC_RISCV()
19109 if (HiReg) { in CC_RISCV()
19111 CCValAssign::getCustomReg(ValNo, ValVT, HiReg, LocV in CC_RISCV()
18132 Register HiReg = MI.getOperand(1).getReg(); emitReadCounterWidePseudo() local
18171 Register HiReg = MI.getOperand(1).getReg(); emitSplitF64Pseudo() local
18208 Register HiReg = MI.getOperand(2).getReg(); emitBuildPairF64Pseudo() local
19105 Register HiReg = State.AllocateReg(ArgGPRs); CC_RISCV() local
[all...] |
| /freebsd/contrib/llvm-project/llvm/lib/Target/ARM/AsmParser/ |
| H A D | ARMAsmParser.cpp | 7463 unsigned Reg, unsigned HiReg, in checkLowRegisterList() argument
7471 if (!isARMLowRegister(OpReg) && (!HiReg || OpReg != HiReg)) in checkLowRegisterList()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/ |
| H A D | PPCISelLowering.cpp | 13039 Register HiReg = MI.getOperand(1).getReg(); in EmitInstrWithCustomInserter() local
13041 BuildMI(BB, dl, TII->get(PPC::MFSPR), HiReg).addImm(269); in EmitInstrWithCustomInserter()
13048 .addReg(HiReg) in EmitInstrWithCustomInserter()
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