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Searched refs:HiLHS (Results 1 – 4 of 4) sorted by relevance

/freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DTargetLowering.cpp11010 SDValue HiLHS, SDValue HiRHS) const { in forceExpandMultiply() argument
11014 assert((HiLHS && HiRHS) || (!HiLHS && !HiRHS)); in forceExpandMultiply()
11015 assert((!Signed || !HiLHS) && in forceExpandMultiply()
11057 if (HiLHS) { in forceExpandMultiply()
11061 DAG.getNode(ISD::MUL, dl, VT, RHS, HiLHS))); in forceExpandMultiply()
11089 SDValue HiLHS, HiRHS; in forceExpandWideMUL() local
11095 HiLHS = DAG.getNode(ISD::SRA, dl, VT, LHS, Shift); in forceExpandWideMUL()
11098 HiLHS = DAG.getConstant(0, dl, VT); in forceExpandWideMUL()
11112 SDValue Args[] = {LHS, HiLHS, RHS, HiRHS}; in forceExpandWideMUL()
11115 SDValue Args[] = {HiLHS, LHS, HiRHS, RHS}; in forceExpandWideMUL()
H A DLegalizeVectorTypes.cpp1947 SDValue LoLHS, HiLHS, LoRHS, HiRHS; in SplitVecRes_OverflowOp() local
1949 GetSplitVector(N->getOperand(0), LoLHS, HiLHS); in SplitVecRes_OverflowOp()
1952 std::tie(LoLHS, HiLHS) = DAG.SplitVectorOperand(N, 0); in SplitVecRes_OverflowOp()
1960 SDNode *HiNode = DAG.getNode(Opcode, dl, HiVTs, HiLHS, HiRHS).getNode(); in SplitVecRes_OverflowOp()
/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DAMDGPURegisterBankInfo.cpp667 Register HiLHS = MRI->createGenericVirtualRegister(HalfTy); in split64BitValueForMapping() local
670 MRI->setRegBank(HiLHS, *Bank); in split64BitValueForMapping()
673 Regs.push_back(HiLHS); in split64BitValueForMapping()
677 .addDef(HiLHS) in split64BitValueForMapping()
/freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DTargetLowering.h5669 SDValue HiLHS = SDValue(),