Searched refs:HiLHS (Results 1 – 4 of 4) sorted by relevance
| /freebsd/contrib/llvm-project/llvm/lib/Target/Sparc/ |
| H A D | SparcISelLowering.cpp | 3177 SDValue HiLHS, HiRHS; in LowerUMULO_SMULO() local
3179 HiLHS = DAG.getNode(ISD::SRA, dl, VT, LHS, ShiftAmt); in LowerUMULO_SMULO()
3182 HiLHS = DAG.getConstant(0, dl, VT); in LowerUMULO_SMULO()
3186 SDValue Args[] = { HiLHS, LHS, HiRHS, RHS }; in LowerUMULO_SMULO()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | AMDGPURegisterBankInfo.cpp | 667 Register HiLHS = MRI->createGenericVirtualRegister(HalfTy); in split64BitValueForMapping() local
670 MRI->setRegBank(HiLHS, *Bank); in split64BitValueForMapping()
673 Regs.push_back(HiLHS); in split64BitValueForMapping()
677 .addDef(HiLHS) in split64BitValueForMapping()
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| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | LegalizeVectorTypes.cpp | 1871 SDValue LoLHS, HiLHS, LoRHS, HiRHS; in SplitVecRes_OverflowOp()
1873 GetSplitVector(N->getOperand(0), LoLHS, HiLHS); in SplitVecRes_OverflowOp()
1876 std::tie(LoLHS, HiLHS) = DAG.SplitVectorOperand(N, 0); in SplitVecRes_OverflowOp()
1884 SDNode *HiNode = DAG.getNode(Opcode, dl, HiVTs, HiLHS, HiRHS).getNode(); in SplitVecRes_OverflowOp()
1867 SDValue LoLHS, HiLHS, LoRHS, HiRHS; SplitVecRes_OverflowOp() local
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| H A D | TargetLowering.cpp | 10611 SDValue HiLHS; in forceExpandWideMUL() local
10617 HiLHS = DAG.getNode( in forceExpandWideMUL()
10624 HiLHS = DAG.getConstant(0, dl, VT); in forceExpandWideMUL()
10628 forceExpandWideMUL(DAG, dl, Signed, WideVT, LHS, HiLHS, RHS, HiRHS, Lo, Hi); in forceExpandWideMUL()
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