| /freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/MCTargetDesc/ |
| H A D | RISCVAsmBackend.cpp | 528 unsigned Hi1 = (Value >> 11) & 0x1; in adjustFixupValue() local
535 Value = (Sbit << 31) | (Mid6 << 25) | (Lo4 << 8) | (Hi1 << 7); in adjustFixupValue()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Mips/ |
| H A D | MipsSEISelDAGToDAG.cpp | 706 SDValue Hi1 = Node->getOperand(1); in trySelect() local
711 SDValue ops[] = {cond, Hi1, Lo1, Hi2, Lo2}; in trySelect()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/ |
| H A D | PPCInstrInfo.td | 5163 dag Hi1 = (ORI (LIS 0xAAAA), 0xAAAA);
5177 (AND Shift1.Left, MaskValues.Hi1));
5231 dag Hi1 = (i64 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), MaskValues.Hi1, sub_32));
5240 dag Hi1 = (ORI8 (ORIS8 (RLDICR MaskValues64.Hi1, 32, 31), 0xAAAA), 0xAAAA);
5249 (AND8 (RLDICR $A, 1, 62), DWMaskValues.Hi1));
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| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | LegalizeVectorTypes.cpp | 4421 SDValue Lo0, Hi0, Lo1, Hi1, LoRes, HiRes; in SplitVecOp_VSETCC() local
4424 GetSplitVector(N->getOperand(isStrict ? 2 : 1), Lo1, Hi1); in SplitVecOp_VSETCC()
4431 HiRes = DAG.getNode(ISD::SETCC, DL, PartResVT, Hi0, Hi1, N->getOperand(2)); in SplitVecOp_VSETCC()
4436 N->getOperand(0), Hi0, Hi1, N->getOperand(3)); in SplitVecOp_VSETCC()
4448 HiRes = DAG.getNode(ISD::VP_SETCC, DL, PartResVT, Hi0, Hi1, in SplitVecOp_VSETCC()
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| H A D | TargetLowering.cpp | 5283 SDValue Lo0, Lo1, Hi0, Hi1; in SimplifySetCC() local
5285 IsConcat(N0.getOperand(1), Lo1, Hi1)) { in SimplifySetCC()
5287 DAG.getNode(N0.getOpcode(), dl, OpVT, Hi0, Hi1)); in SimplifySetCC()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | AMDGPUISelDAGToDAG.cpp | 980 SDNode *Hi1 = CurDAG->getMachineNode(TargetOpcode::EXTRACT_SUBREG, in SelectADD_SUB_I64() local
1004 SDValue(Hi1, 0), in SelectADD_SUB_I64()
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| H A D | AMDGPUInstructionSelector.cpp | 465 MachineOperand Hi1(getSubOperand64(I.getOperand(1), HalfRC, AMDGPU::sub1)); in selectG_ADD_SUB() local
476 .add(Hi1) in selectG_ADD_SUB()
489 .add(Hi1) in selectG_ADD_SUB()
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| H A D | SIISelLowering.cpp | 6058 auto [Lo1, Hi1] = DAG.SplitVectorOperand(Op.getNode(), 1); in splitBinaryVectorOp()
6065 DAG.getNode(Opc, SL, Hi0.getValueType(), Hi0, Hi1, Op->getFlags()); in splitBinaryVectorOp()
6086 auto [Lo1, Hi1] = DAG.SplitVectorOperand(Op.getNode(), 1); in splitTernaryVectorOp()
6095 DAG.getNode(Opc, SL, ResVT.second, Hi0, Hi1, Hi2, Op->getFlags()); in splitTernaryVectorOp()
11091 SDValue Hi1 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::i32, RHS, One); in LowerSELECT() local
11093 SDValue Hi = DAG.getSelect(DL, MVT::i32, Cond, Hi0, Hi1); in LowerSELECT()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/ARM/ |
| H A D | ARMISelLowering.cpp | 9482 ConstantSDNode *Hi1 = dyn_cast<ConstantSDNode>(BVN->getOperand(HiElt+2)); in isExtendedBUILD_VECTOR() local
9483 if (!Lo0 || !Hi0 || !Lo1 || !Hi1) in isExtendedBUILD_VECTOR()
9487 Hi1->getSExtValue() == Lo1->getSExtValue() >> 32) in isExtendedBUILD_VECTOR()
9490 if (Hi0->isZero() && Hi1->isZero()) in isExtendedBUILD_VECTOR()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86ISelLowering.cpp | 57958 SDValue Accum, Lo0, Lo1, Hi0, Hi1; in combineAdd() local
57964 m_Value(Hi1)))))) { in combineAdd()
57967 concatSubVectors(Lo1, Hi1, DAG, DL)); in combineAdd()
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