| /freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/MCTargetDesc/ |
| H A D | RISCVAsmBackend.cpp | 467 unsigned Hi1 = (Value >> 11) & 0x1; in adjustFixupValue() local
474 Value = (Sbit << 31) | (Mid6 << 25) | (Lo4 << 8) | (Hi1 << 7); in adjustFixupValue()
|
| /freebsd/contrib/llvm-project/llvm/lib/Target/Mips/ |
| H A D | MipsSEISelDAGToDAG.cpp | 760 SDValue Hi1 = Node->getOperand(1); in trySelect() local
765 SDValue ops[] = {cond, Hi1, Lo1, Hi2, Lo2}; in trySelect()
|
| /freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/ |
| H A D | PPCInstrInfo.td | 5124 dag Hi1 = (ORI (LIS 0xAAAA), 0xAAAA);
5138 (AND Shift1.Left, MaskValues.Hi1));
5192 dag Hi1 = (i64 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), MaskValues.Hi1, sub_32));
5201 dag Hi1 = (ORI8 (ORIS8 (RLDICR MaskValues64.Hi1, 32, 31), 0xAAAA), 0xAAAA);
5210 (AND8 (RLDICR $A, 1, 62), DWMaskValues.Hi1));
|
| /freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | AMDGPUISelDAGToDAG.cpp | 864 SDNode *Hi1 = CurDAG->getMachineNode(TargetOpcode::EXTRACT_SUBREG, in SelectADD_SUB_I64() local
888 SDValue(Hi1, 0), in SelectADD_SUB_I64()
|
| H A D | AMDGPUInstructionSelector.cpp | 367 MachineOperand Hi1(getSubOperand64(I.getOperand(1), HalfRC, AMDGPU::sub1)); in selectG_ADD_SUB() local
378 .add(Hi1) in selectG_ADD_SUB()
391 .add(Hi1) in selectG_ADD_SUB()
|
| H A D | SIISelLowering.cpp | 5706 SDValue Lo1, Hi1; in splitBinaryVectorOp() local
5707 std::tie(Lo1, Hi1) = DAG.SplitVectorOperand(Op.getNode(), 1); in splitBinaryVectorOp()
5713 SDValue OpHi = DAG.getNode(Opc, SL, Hi0.getValueType(), Hi0, Hi1, in splitBinaryVectorOp()
5735 SDValue Lo1, Hi1; in splitTernaryVectorOp() local
5736 std::tie(Lo1, Hi1) = DAG.SplitVectorOperand(Op.getNode(), 1); in splitTernaryVectorOp()
5745 SDValue OpHi = DAG.getNode(Opc, SL, ResVT.second, Hi0, Hi1, Hi2, in splitTernaryVectorOp()
10434 SDValue Hi1 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::i32, RHS, One); in LowerSELECT() local
10436 SDValue Hi = DAG.getSelect(DL, MVT::i32, Cond, Hi0, Hi1); in LowerSELECT()
|
| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | LegalizeVectorTypes.cpp | 4111 SDValue Lo0, Hi0, Lo1, Hi1, LoRes, HiRes; in SplitVecOp_VSETCC()
4114 GetSplitVector(N->getOperand(isStrict ? 2 : 1), Lo1, Hi1); in SplitVecOp_VSETCC()
4124 HiRes = DAG.getNode(ISD::SETCC, DL, PartResVT, Hi0, Hi1, N->getOperand(2)); in SplitVecOp_VSETCC()
4131 N->getOperand(0), Hi0, Hi1, N->getOperand(3)); in SplitVecOp_VSETCC()
4143 HiRes = DAG.getNode(ISD::VP_SETCC, DL, PartResVT, Hi0, Hi1, in SplitVecOp_VSETCC()
4107 SDValue Lo0, Hi0, Lo1, Hi1, LoRes, HiRes; SplitVecOp_VSETCC() local
|
| H A D | TargetLowering.cpp | 5067 SDValue Lo0, Lo1, Hi0, Hi1; in SimplifySetCC() local
5069 IsConcat(N0.getOperand(1), Lo1, Hi1)) { in SimplifySetCC()
5071 DAG.getNode(N0.getOpcode(), dl, OpVT, Hi0, Hi1)); in SimplifySetCC()
|
| /freebsd/contrib/llvm-project/llvm/lib/Target/ARM/ |
| H A D | ARMISelLowering.cpp | 9430 ConstantSDNode *Hi1 = dyn_cast<ConstantSDNode>(BVN->getOperand(HiElt+2)); in isExtendedBUILD_VECTOR() local
9431 if (!Lo0 || !Hi0 || !Lo1 || !Hi1) in isExtendedBUILD_VECTOR()
9435 Hi1->getSExtValue() == Lo1->getSExtValue() >> 32) in isExtendedBUILD_VECTOR()
9438 if (Hi0->isZero() && Hi1->isZero()) in isExtendedBUILD_VECTOR()
|