| /freebsd/contrib/llvm-project/clang/lib/Basic/Targets/ |
| H A D | WebAssembly.cpp | 61 .Case("fp16", HasFP16) in hasFeature()
99 if (HasFP16) in getTargetDefines()
263 HasFP16 = true; in handleTargetFeatures()
267 HasFP16 = false; in handleTargetFeatures()
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| H A D | WebAssembly.h | 66 bool HasFP16 = false; variable
100 bool useFP16ConversionIntrinsics() const override { return !HasFP16; } in useFP16ConversionIntrinsics()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/WebAssembly/ |
| H A D | WebAssemblySubtarget.h | 48 bool HasFP16 = false; variable
104 bool hasFP16() const { return HasFP16; } in hasFP16()
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| H A D | WebAssemblyInstrMemory.td | 77 WebAssemblyLoad<F32, "f32.load_f16", 0xfc30, [HasFP16]>;
177 WebAssemblyStore<F32, "f32.store_f16", 0xfc31, [HasFP16]>;
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| H A D | WebAssembly.td | 49 SubtargetFeature<"fp16", "HasFP16", "true",
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| H A D | WebAssemblyInstrSIMD.td | 46 asmstr_s, simdop, [HasFP16]>;
754 defm "" : SIMDCondition<vec, name, cond, simdop, [HasFP16]>;
836 defm "" : SIMDBinary<vec, node, name, simdop, [HasFP16]>;
861 defm "" : SIMDUnary<vec, node, name, simdop, [HasFP16]>;
1361 defm "" : SIMDConvert<vec, arg, op, name, simdop, [HasFP16]>;
1547 defm "" : SIMDMADD<F16x8, 0x14e, 0x14f, [HasFP16]>;
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| H A D | WebAssemblyInstrInfo.td | 49 def HasFP16 :
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/GISel/ |
| H A D | AArch64LegalizerInfo.cpp | 87 const bool HasFP16 = ST.hasFullFP16(); in AArch64LegalizerInfo() local
88 const LLT &MinFPScalar = HasFP16 ? s16 : s32; in AArch64LegalizerInfo()
402 .legalFor(HasFP16, {s16, v4s16, v8s16}) in AArch64LegalizerInfo()
413 .legalFor(HasFP16, {s16, v4s16, v8s16}) in AArch64LegalizerInfo()
676 .legalFor(HasFP16, {s16}) in AArch64LegalizerInfo()
716 .legalFor(HasFP16, {{s32, s16}, {v4s16, v4s16}, {v8s16, v8s16}}) in AArch64LegalizerInfo()
832 .legalFor(HasFP16, in AArch64LegalizerInfo()
846 .widenScalarOrEltToNextPow2OrMinSize(1, /*MinSize=*/HasFP16 ? 16 : 32) in AArch64LegalizerInfo()
875 .legalFor(HasFP16, in AArch64LegalizerInfo()
891 .widenScalarOrEltToNextPow2OrMinSize(1, /*MinSize=*/HasFP16 ? 16 : 32) in AArch64LegalizerInfo()
[all …]
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| /freebsd/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86InstrAVX512.td | 2013 let Predicates = [HasFP16], ExeDomain = SSEPackedSingle in
2442 defm VCMPPH : avx512_vcmp<SchedWriteFCmp, avx512vl_f16_info, HasFP16>,
2454 let Predicates = [HasFP16] in {
2598 sched, HasFP16>,
2601 sched.Scl, f16x_info, HasFP16>,
3907 let Predicates = !if (!eq (prd, HasFP16), [HasFP16], [prd, OptForSize]) in
3975 HasFP16>,
4155 let Predicates = [HasFP16] in {
4297 let Predicates = [HasFP16] in {
4458 let Predicates = [HasFP16] in {
[all …]
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| H A D | X86InstrPredicates.td | 96 def HasFP16 : Predicate<"Subtarget->hasFP16()">;
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| H A D | X86InstrVecCompiler.td | 178 let Predicates = [HasFP16, HasVLX] in {
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| H A D | X86.td | 169 def FeatureFP16 : SubtargetFeature<"avx512fp16", "HasFP16", "true",
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| /freebsd/contrib/llvm-project/llvm/lib/Target/ARM/ |
| H A D | ARMPredicates.td | 112 def HasFP16 : Predicate<"Subtarget->hasFP16()">,
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| H A D | ARMInstrVFP.td | 794 Requires<[HasFP16]>,
806 Requires<[HasFP16]>,
828 Requires<[HasFP16]>,
842 Requires<[HasFP16]>,
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| H A D | ARMFeatures.td | 104 def FeatureFP16 : SubtargetFeature<"fp16", "HasFP16", "true",
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| H A D | ARMInstrFormats.td | 1148 list<Predicate> Predicates = [HasFP16];
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| H A D | ARMInstrNEON.td | 6945 Requires<[HasNEON, HasFP16]>;
6949 Requires<[HasNEON, HasFP16]>;
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