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Searched refs:HasBaseReg (Results 1 – 25 of 31) sorted by relevance

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/freebsd/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86AsmPrinter.cpp381 bool HasBaseReg = BaseReg.getReg() != 0; in PrintLeaMemReference() local
382 if (HasBaseReg && Modifier && !strcmp(Modifier, "no-rip") && in PrintLeaMemReference()
384 HasBaseReg = false; in PrintLeaMemReference()
387 bool HasParenPart = IndexReg.getReg() || HasBaseReg; in PrintLeaMemReference()
412 if (HasBaseReg) in PrintLeaMemReference()
479 bool HasBaseReg = BaseReg.getReg() != 0; in PrintIntelMemReference() local
480 if (HasBaseReg && Modifier && !strcmp(Modifier, "no-rip") && in PrintIntelMemReference()
482 HasBaseReg = false; in PrintIntelMemReference()
487 HasBaseReg = false; in PrintIntelMemReference()
499 if (HasBaseReg) { in PrintIntelMemReference()
[all …]
H A DX86TargetTransformInfo.h257 StackOffset BaseOffset, bool HasBaseReg,
H A DX86TargetTransformInfo.cpp6727 bool HasBaseReg, int64_t Scale, in getScalingFactorCost() argument
6750 AM.HasBaseReg = HasBaseReg; in getScalingFactorCost()
/freebsd/contrib/llvm-project/llvm/lib/Transforms/Scalar/
H A DLoopStrengthReduce.cpp491 bool HasBaseReg = false; member
611 HasBaseReg = true; in initialMatch()
617 HasBaseReg = true; in initialMatch()
767 if (HasBaseReg && BaseRegs.empty()) { in print()
770 } else if (!HasBaseReg && !BaseRegs.empty()) { in print()
1394 bool HasBaseReg, int64_t Scale,
1560 Offset, F.HasBaseReg, F.Scale, Fixup.UserInst)) in RateFormula()
1818 bool HasBaseReg, int64_t Scale, in isAMCompletelyFolded() argument
1827 HasBaseReg, Scale, AccessTy.AddrSpace, in isAMCompletelyFolded()
1837 if (Scale != 0 && HasBaseReg && BaseOffset.isNonZero()) in isAMCompletelyFolded()
[all …]
/freebsd/contrib/llvm-project/llvm/include/llvm/Analysis/
H A DTargetTransformInfoImpl.h230 bool HasBaseReg, int64_t Scale, unsigned AddrSpace,
341 StackOffset BaseOffset, bool HasBaseReg, in getScalingFactorCost() argument
345 if (isLegalAddressingMode(Ty, BaseGV, BaseOffset.getFixed(), HasBaseReg, in getScalingFactorCost()
1072 bool HasBaseReg = (BaseGV == nullptr); in getGEPCost() local
1135 BaseOffset.sextOrTrunc(64).getSExtValue(), HasBaseReg, Scale, in getGEPCost()
H A DTargetTransformInfo.h732 bool HasBaseReg, int64_t Scale,
851 StackOffset BaseOffset, bool HasBaseReg,
1887 int64_t BaseOffset, bool HasBaseReg,
1928 bool HasBaseReg, int64_t Scale,
2361 bool HasBaseReg, int64_t Scale, unsigned AddrSpace, in isLegalAddressingMode() argument
2363 return Impl.isLegalAddressingMode(Ty, BaseGV, BaseOffset, HasBaseReg, Scale, in isLegalAddressingMode()
2452 StackOffset BaseOffset, bool HasBaseReg, in getScalingFactorCost() argument
2455 return Impl.getScalingFactorCost(Ty, BaseGV, BaseOffset, HasBaseReg, Scale, in getScalingFactorCost()
/freebsd/contrib/llvm-project/llvm/lib/Analysis/
H A DTargetTransformInfo.cpp413 bool HasBaseReg, int64_t Scale, in isLegalAddressingMode() argument
417 return TTIImpl->isLegalAddressingMode(Ty, BaseGV, BaseOffset, HasBaseReg, in isLegalAddressingMode()
547 Type *Ty, GlobalValue *BaseGV, StackOffset BaseOffset, bool HasBaseReg, in getScalingFactorCost() argument
550 Ty, BaseGV, BaseOffset, HasBaseReg, Scale, AddrSpace); in getScalingFactorCost()
/freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DBasicTTIImpl.h341 bool HasBaseReg, int64_t Scale, unsigned AddrSpace,
347 AM.HasBaseReg = HasBaseReg;
411 StackOffset BaseOffset, bool HasBaseReg, in getScalingFactorCost() argument
416 AM.HasBaseReg = HasBaseReg; in getScalingFactorCost()
H A DTargetLowering.h2793 bool HasBaseReg = false; member
/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DAMDGPUPerfHintAnalysis.cpp262 AM.HasBaseReg = !AM.BaseGV; in visit()
H A DSILoadStoreOptimizer.cpp2189 AM.HasBaseReg = true; in promoteConstantOffsetToImm()
2214 AM.HasBaseReg = true; in promoteConstantOffsetToImm()
H A DSIISelLowering.cpp1556 if (AM.HasBaseReg) { in isLegalMUBUFAddressingMode()
1635 if (AM.Scale == 1 && AM.HasBaseReg) in isLegalAddressingMode()
1658 if (AM.Scale == 1 && AM.HasBaseReg) in isLegalAddressingMode()
11335 AM.HasBaseReg = true; in performSHLPtrCombine()
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64TargetTransformInfo.h416 StackOffset BaseOffset, bool HasBaseReg,
H A DAArch64TargetTransformInfo.cpp4378 StackOffset BaseOffset, bool HasBaseReg, in getScalingFactorCost() argument
4390 AM.HasBaseReg = HasBaseReg; in getScalingFactorCost()
H A DAArch64ISelLowering.cpp17355 if (AMode.HasBaseReg && AMode.BaseOffs && AMode.Scale) in isLegalAddressingMode()
17361 if (AM.Scale && !AM.HasBaseReg) { in isLegalAddressingMode()
17363 AM.HasBaseReg = true; in isLegalAddressingMode()
17366 AM.HasBaseReg = true; in isLegalAddressingMode()
17374 if (!AM.HasBaseReg) in isLegalAddressingMode()
17384 if (AM.HasBaseReg && !AM.BaseOffs && AM.ScalableOffset && !AM.Scale && in isLegalAddressingMode()
17391 return AM.HasBaseReg && !AM.BaseOffs && !AM.ScalableOffset && in isLegalAddressingMode()
17395 return AM.HasBaseReg && !AM.BaseOffs && !AM.ScalableOffset && !AM.Scale; in isLegalAddressingMode()
/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMTargetTransformInfo.h306 StackOffset BaseOffset, bool HasBaseReg,
H A DARMTargetTransformInfo.cpp2579 bool HasBaseReg, int64_t Scale, in getScalingFactorCost() argument
2584 AM.HasBaseReg = HasBaseReg; in getScalingFactorCost()
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/
H A DCodeGenPrepare.cpp3852 !NewAddrMode.HasBaseReg); in addNewAddrMode()
4996 if (AddrMode.HasBaseReg) { in matchOperationAddr()
5001 AddrMode.HasBaseReg = true; in matchOperationAddr()
5012 if (AddrMode.HasBaseReg) in matchOperationAddr()
5014 AddrMode.HasBaseReg = true; in matchOperationAddr()
5157 if (!AddrMode.HasBaseReg) { in matchAddr()
5158 AddrMode.HasBaseReg = true; in matchAddr()
5163 AddrMode.HasBaseReg = false; in matchAddr()
6336 AddrMode.HasBaseReg = true; in splitLargeGEPOffsets()
H A DTargetLoweringBase.cpp1908 if (AM.HasBaseReg && AM.BaseOffs) // "r+r+i" is not allowed. in isLegalAddressingMode()
1913 if (AM.HasBaseReg || AM.BaseOffs) // 2*r+r or 2*r+i is not allowed. in isLegalAddressingMode()
/freebsd/contrib/llvm-project/llvm/lib/Target/BPF/
H A DBPFISelLowering.cpp955 if (!AM.HasBaseReg) // allow "r+i". in isLegalAddressingMode()
/freebsd/contrib/llvm-project/llvm/lib/Target/AVR/
H A DAVRISelLowering.cpp1048 if (AM.BaseGV && !AM.HasBaseReg && AM.Scale == 0 && Offs == 0) { in isLegalAddressingMode()
1060 if (AM.BaseGV == nullptr && AM.HasBaseReg && AM.Scale == 0 && in isLegalAddressingMode()
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/
H A DCombinerHelper.cpp1115 AM.HasBaseReg = true; in canFoldInAddressingMode()
1745 AMNew.HasBaseReg = true; in matchPtrAddImmedChain()
1748 AMOld.HasBaseReg = true; in matchPtrAddImmedChain()
4715 AM.HasBaseReg = true; in reassociationCanBreakAddressingModePattern()
/freebsd/contrib/llvm-project/llvm/lib/Target/XCore/
H A DXCoreISelLowering.cpp1794 return Size >= 4 && !AM.HasBaseReg && AM.Scale == 0 && in isLegalAddressingMode()
/freebsd/contrib/llvm-project/llvm/lib/Target/LoongArch/
H A DLoongArchISelLowering.cpp6089 if (AM.HasBaseReg && AM.BaseOffs) in isLegalAddressingMode()
6095 if (AM.HasBaseReg || AM.BaseOffs) in isLegalAddressingMode()
/freebsd/contrib/llvm-project/llvm/lib/Target/NVPTX/
H A DNVPTXISelLowering.cpp5180 return !AM.BaseOffs && !AM.HasBaseReg && !AM.Scale; in isLegalAddressingMode()
5186 if (AM.HasBaseReg) // "r+r+i" or "r+r" is not allowed. in isLegalAddressingMode()

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