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Searched refs:HasBaseReg (Results 1 – 25 of 31) sorted by relevance

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/freebsd/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86AsmPrinter.cpp425 bool HasBaseReg = BaseReg.getReg() != 0; in PrintLeaMemReference() local
426 if (HasBaseReg && Modifier == "no-rip" && BaseReg.getReg() == X86::RIP) in PrintLeaMemReference()
427 HasBaseReg = false; in PrintLeaMemReference()
430 bool HasParenPart = IndexReg.getReg() || HasBaseReg; in PrintLeaMemReference()
455 if (HasBaseReg) in PrintLeaMemReference()
522 bool HasBaseReg = BaseReg.getReg() != 0; in PrintIntelMemReference() local
523 if (HasBaseReg && Modifier == "no-rip" && BaseReg.getReg() == X86::RIP) in PrintIntelMemReference()
524 HasBaseReg = false; in PrintIntelMemReference()
528 HasBaseReg = false; in PrintIntelMemReference()
540 if (HasBaseReg) { in PrintIntelMemReference()
[all …]
H A DX86TargetTransformInfo.h262 StackOffset BaseOffset, bool HasBaseReg,
H A DX86TargetTransformInfo.cpp7091 bool HasBaseReg, int64_t Scale, in getScalingFactorCost() argument
7114 AM.HasBaseReg = HasBaseReg; in getScalingFactorCost()
/freebsd/contrib/llvm-project/llvm/lib/Transforms/Scalar/
H A DLoopStrengthReduce.cpp482 bool HasBaseReg = false; member
606 HasBaseReg = true; in initialMatch()
612 HasBaseReg = true; in initialMatch()
775 if (HasBaseReg && BaseRegs.empty()) { in print()
778 } else if (!HasBaseReg && !BaseRegs.empty()) { in print()
1374 bool HasBaseReg, int64_t Scale,
1542 Offset, F.HasBaseReg, F.Scale, Fixup.UserInst)) in RateFormula()
1800 bool HasBaseReg, int64_t Scale, in isAMCompletelyFolded() argument
1809 HasBaseReg, Scale, AccessTy.AddrSpace, in isAMCompletelyFolded()
1819 if (Scale != 0 && HasBaseReg && BaseOffset.isNonZero()) in isAMCompletelyFolded()
[all …]
/freebsd/contrib/llvm-project/llvm/include/llvm/Analysis/
H A DTargetTransformInfoImpl.h273 int64_t BaseOffset, bool HasBaseReg,
402 bool HasBaseReg, int64_t Scale, in getScalingFactorCost() argument
405 if (isLegalAddressingMode(Ty, BaseGV, BaseOffset.getFixed(), HasBaseReg, in getScalingFactorCost()
1244 bool HasBaseReg = (BaseGV == nullptr); in getGEPCost() local
1307 BaseOffset.sextOrTrunc(64).getSExtValue(), HasBaseReg, Scale, in getGEPCost()
H A DTargetTransformInfo.h765 int64_t BaseOffset, bool HasBaseReg,
896 bool HasBaseReg, int64_t Scale,
/freebsd/contrib/llvm-project/llvm/lib/Analysis/
H A DTargetTransformInfo.cpp427 bool HasBaseReg, int64_t Scale, in isLegalAddressingMode() argument
431 return TTIImpl->isLegalAddressingMode(Ty, BaseGV, BaseOffset, HasBaseReg, in isLegalAddressingMode()
564 Type *Ty, GlobalValue *BaseGV, StackOffset BaseOffset, bool HasBaseReg, in getScalingFactorCost() argument
567 Ty, BaseGV, BaseOffset, HasBaseReg, Scale, AddrSpace); in getScalingFactorCost()
/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMTargetTransformInfo.h317 StackOffset BaseOffset, bool HasBaseReg,
H A DARMTargetTransformInfo.cpp2721 bool HasBaseReg, int64_t Scale, in getScalingFactorCost() argument
2726 AM.HasBaseReg = HasBaseReg; in getScalingFactorCost()
/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DAMDGPUPerfHintAnalysis.cpp259 AM.HasBaseReg = !AM.BaseGV; in visit()
H A DSILoadStoreOptimizer.cpp2259 AM.HasBaseReg = true; in promoteConstantOffsetToImm()
2284 AM.HasBaseReg = true; in promoteConstantOffsetToImm()
H A DSIISelLowering.cpp1667 if (AM.HasBaseReg) { in isLegalMUBUFAddressingMode()
1747 if (AM.Scale == 1 && AM.HasBaseReg) in isLegalAddressingMode()
1770 if (AM.Scale == 1 && AM.HasBaseReg) in isLegalAddressingMode()
12081 AM.HasBaseReg = true; in performSHLPtrCombine()
/freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DBasicTTIImpl.h444 bool HasBaseReg, int64_t Scale, unsigned AddrSpace,
450 AM.HasBaseReg = HasBaseReg;
508 StackOffset BaseOffset, bool HasBaseReg, in getScalingFactorCost() argument
514 AM.HasBaseReg = HasBaseReg; in getScalingFactorCost()
H A DTargetLowering.h2886 bool HasBaseReg = false; member
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64TargetTransformInfo.h469 StackOffset BaseOffset, bool HasBaseReg,
H A DAArch64TargetTransformInfo.cpp5908 StackOffset BaseOffset, bool HasBaseReg, in getScalingFactorCost() argument
5920 AM.HasBaseReg = HasBaseReg; in getScalingFactorCost()
H A DAArch64ISelLowering.cpp17775 if (AMode.HasBaseReg && AMode.BaseOffs && AMode.Scale) in isLegalAddressingMode()
17781 if (AM.Scale && !AM.HasBaseReg) { in isLegalAddressingMode()
17783 AM.HasBaseReg = true; in isLegalAddressingMode()
17786 AM.HasBaseReg = true; in isLegalAddressingMode()
17794 if (!AM.HasBaseReg) in isLegalAddressingMode()
17804 if (AM.HasBaseReg && !AM.BaseOffs && AM.ScalableOffset && !AM.Scale && in isLegalAddressingMode()
17811 return AM.HasBaseReg && !AM.BaseOffs && !AM.ScalableOffset && in isLegalAddressingMode()
17815 return AM.HasBaseReg && !AM.BaseOffs && !AM.ScalableOffset && !AM.Scale; in isLegalAddressingMode()
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/
H A DCodeGenPrepare.cpp4189 !NewAddrMode.HasBaseReg); in addNewAddrMode()
5332 if (AddrMode.HasBaseReg) { in matchOperationAddr()
5337 AddrMode.HasBaseReg = true; in matchOperationAddr()
5348 if (AddrMode.HasBaseReg) in matchOperationAddr()
5350 AddrMode.HasBaseReg = true; in matchOperationAddr()
5502 if (!AddrMode.HasBaseReg) { in matchAddr()
5503 AddrMode.HasBaseReg = true; in matchAddr()
5508 AddrMode.HasBaseReg = false; in matchAddr()
6726 AddrMode.HasBaseReg = true; in splitLargeGEPOffsets()
H A DTargetLoweringBase.cpp2011 if (AM.HasBaseReg && AM.BaseOffs) // "r+r+i" is not allowed. in isLegalAddressingMode()
2016 if (AM.HasBaseReg || AM.BaseOffs) // 2*r+r or 2*r+i is not allowed. in isLegalAddressingMode()
/freebsd/contrib/llvm-project/llvm/lib/Target/BPF/
H A DBPFISelLowering.cpp1063 if (!AM.HasBaseReg) // allow "r+i". in isLegalAddressingMode()
/freebsd/contrib/llvm-project/llvm/lib/Target/AVR/
H A DAVRISelLowering.cpp992 if (AM.BaseGV && !AM.HasBaseReg && AM.Scale == 0 && Offs == 0) { in isLegalAddressingMode()
1004 if (AM.BaseGV == nullptr && AM.HasBaseReg && AM.Scale == 0 && in isLegalAddressingMode()
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/
H A DCombinerHelper.cpp1183 AM.HasBaseReg = true; in canFoldInAddressingMode()
1813 AMNew.HasBaseReg = true; in matchPtrAddImmedChain()
1816 AMOld.HasBaseReg = true; in matchPtrAddImmedChain()
4843 AM.HasBaseReg = true; in reassociationCanBreakAddressingModePattern()
/freebsd/contrib/llvm-project/llvm/lib/Target/XCore/
H A DXCoreISelLowering.cpp1765 return Size >= 4 && !AM.HasBaseReg && AM.Scale == 0 && in isLegalAddressingMode()
/freebsd/contrib/llvm-project/llvm/lib/Target/NVPTX/
H A DNVPTXISelLowering.cpp4726 return !AM.BaseOffs && !AM.HasBaseReg && !AM.Scale; in isLegalAddressingMode()
4732 if (AM.HasBaseReg) // "r+r+i" or "r+r" is not allowed. in isLegalAddressingMode()
/freebsd/contrib/llvm-project/llvm/lib/Target/LoongArch/
H A DLoongArchISelLowering.cpp8371 if (AM.HasBaseReg && AM.BaseOffs) in isLegalAddressingMode()
8377 if (AM.HasBaseReg || AM.BaseOffs) in isLegalAddressingMode()

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