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Searched refs:HalfVT (Results 1 – 15 of 15) sorted by relevance

/freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DValueTypes.h430 EVT HalfVT = EVT((MVT::SimpleValueType)IntVT); in getHalfSizedIntegerVT() local
431 if (HalfVT.getSizeInBits() * 2 >= EVTSize) in getHalfSizedIntegerVT()
432 return HalfVT; in getHalfSizedIntegerVT()
/freebsd/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86InterleavedAccess.cpp365 MVT HalfVT = scaleVectorType(VT); in interleave8bitStride4() local
383 createUnpackShuffleMask(HalfVT, MaskLowTemp, true, false); in interleave8bitStride4()
384 createUnpackShuffleMask(HalfVT, MaskHighTemp, false, false); in interleave8bitStride4()
H A DX86ISelLowering.cpp4349 EVT HalfVT = V.getValueType().getHalfNumVectorElementsVT(*DAG.getContext()); in isUpperSubvectorUndef() local
4351 return DAG.getNode(ISD::CONCAT_VECTORS, DL, HalfVT, LowerOps); in isUpperSubvectorUndef()
4373 EVT HalfVT = VT.getHalfNumVectorElementsVT(*DAG.getContext()); in splitVector() local
4376 SDValue Lo = DAG.getNode(ISD::CONCAT_VECTORS, dl, HalfVT, LoOps); in splitVector()
4377 SDValue Hi = DAG.getNode(ISD::CONCAT_VECTORS, dl, HalfVT, HiOps); in splitVector()
7420 EVT HalfVT = in EltsFromConsecutiveLoads() local
7423 EltsFromConsecutiveLoads(HalfVT, Elts.drop_back(HalfNumElems), DL, in EltsFromConsecutiveLoads()
8575 MVT HalfVT = VT.getHalfNumVectorElementsVT(); in getHopForBuildVector() local
8578 SDValue Half = DAG.getNode(HOpcode, DL, HalfVT, V0, V1); in getHopForBuildVector()
9652 MVT HalfVT = ResVT.getHalfNumVectorElementsVT(); in LowerAVXCONCAT_VECTORS() local
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/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DAMDGPUISelLowering.cpp2085 EVT HalfVT = VT.getHalfSizedIntegerVT(*DAG.getContext()); in LowerUDIVREM64() local
2087 SDValue One = DAG.getConstant(1, DL, HalfVT); in LowerUDIVREM64()
2088 SDValue Zero = DAG.getConstant(0, DL, HalfVT); in LowerUDIVREM64()
2093 std::tie(LHS_Lo, LHS_Hi) = DAG.SplitScalar(LHS, DL, HalfVT, HalfVT); in LowerUDIVREM64()
2097 std::tie(RHS_Lo, RHS_Hi) = DAG.SplitScalar(RHS, DL, HalfVT, HalfVT); in LowerUDIVREM64()
2102 SDValue Res = DAG.getNode(ISD::UDIVREM, DL, DAG.getVTList(HalfVT, HalfVT), in LowerUDIVREM64()
2141 SDValue Rcp_Lo = DAG.getNode(ISD::FP_TO_UINT, DL, HalfVT, Mad2); in LowerUDIVREM64()
2142 SDValue Rcp_Hi = DAG.getNode(ISD::FP_TO_UINT, DL, HalfVT, Trunc); in LowerUDIVREM64()
2149 SDVTList HalfCarryVT = DAG.getVTList(HalfVT, MVT::i1); in LowerUDIVREM64()
2157 DAG.SplitScalar(Mulhi1, DL, HalfVT, HalfVT); in LowerUDIVREM64()
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/freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DLegalizeTypes.cpp1044 EVT HalfVT = in SplitInteger() local
1046 SplitInteger(Op, HalfVT, HalfVT, Lo, Hi); in SplitInteger()
H A DLegalizeIntegerTypes.cpp5170 EVT HalfVT = LHSLow.getValueType(); in ExpandIntRes_XMULO() local
5172 SDVTList VTHalfWithO = DAG.getVTList(HalfVT, BitVT); in ExpandIntRes_XMULO()
5174 SDValue HalfZero = DAG.getConstant(0, dl, HalfVT); in ExpandIntRes_XMULO()
5185 SDValue HighSum = DAG.getNode(ISD::ADD, dl, HalfVT, One, Two); in ExpandIntRes_XMULO()
5432 EVT HalfVT = In1.getValueType(); in ExpandIntRes_FunnelShift() local
5441 unsigned HalfVTBits = HalfVT.getScalarSizeInBits(); in ExpandIntRes_FunnelShift()
5449 EVT NewShAmtVT = TLI.getShiftAmountTy(HalfVT, DAG.getDataLayout()); in ExpandIntRes_FunnelShift()
5452 SDValue Select1 = DAG.getNode(ISD::SELECT, DL, HalfVT, Cond, In1, In2); in ExpandIntRes_FunnelShift()
5453 SDValue Select2 = DAG.getNode(ISD::SELECT, DL, HalfVT, Cond, In2, In3); in ExpandIntRes_FunnelShift()
5454 SDValue Select3 = DAG.getNode(ISD::SELECT, DL, HalfVT, Cond, In3, In4); in ExpandIntRes_FunnelShift()
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H A DTargetLowering.cpp1911 EVT HalfVT = EVT::getIntegerVT(*TLO.DAG.getContext(), HalfWidth); in SimplifyDemandedBits() local
1912 if (isNarrowingProfitable(Op.getNode(), VT, HalfVT) && in SimplifyDemandedBits()
1913 isTypeDesirableForOp(ISD::SHL, HalfVT) && in SimplifyDemandedBits()
1914 isTruncateFree(VT, HalfVT) && isZExtFree(HalfVT, VT) && in SimplifyDemandedBits()
1915 (!TLO.LegalOperations() || isOperationLegal(ISD::SHL, HalfVT))) { in SimplifyDemandedBits()
1924 SDValue NewOp = TLO.DAG.getNode(ISD::TRUNCATE, dl, HalfVT, Op0); in SimplifyDemandedBits()
1926 TLO.DAG.getShiftAmountConstant(ShAmt, HalfVT, dl); in SimplifyDemandedBits()
1927 SDValue NewShift = TLO.DAG.getNode(ISD::SHL, dl, HalfVT, NewOp, in SimplifyDemandedBits()
2025 EVT HalfVT = EVT::getIntegerVT(*TLO.DAG.getContext(), BitWidth / 2); in SimplifyDemandedBits() local
2026 if (isNarrowingProfitable(Op.getNode(), VT, HalfVT) && in SimplifyDemandedBits()
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H A DDAGCombiner.cpp11522 EVT HalfVT = EVT::getIntegerVT(*DAG.getContext(), BW / 2); in visitBSWAP() local
11525 (ShAmt->getZExtValue() % 16) == 0 && TLI.isTypeLegal(HalfVT) && in visitBSWAP()
11526 TLI.isTruncateFree(VT, HalfVT) && in visitBSWAP()
11527 (!LegalOperations || hasOperation(ISD::BSWAP, HalfVT))) { in visitBSWAP()
11532 Res = DAG.getZExtOrTrunc(Res, DL, HalfVT); in visitBSWAP()
11533 Res = DAG.getNode(ISD::BSWAP, DL, HalfVT, Res); in visitBSWAP()
11675 EVT HalfVT = EVT::getIntegerVT(*DAG.getContext(), NumBits / 2); in visitCTPOP() local
11676 if (hasOperation(ISD::CTPOP, HalfVT) && in visitCTPOP()
11677 TLI.isTypeDesirableForOp(ISD::CTPOP, HalfVT) && in visitCTPOP()
11678 TLI.isTruncateFree(N0, HalfVT) && TLI.isZExtFree(HalfVT, VT)) { in visitCTPOP()
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H A DLegalizeVectorTypes.cpp4368 EVT HalfVT = EVT::getVectorVT(*DAG.getContext(), HalfElementVT, in SplitVecOp_TruncateHelper() local
4375 HalfLo = DAG.getNode(N->getOpcode(), DL, {HalfVT, MVT::Other}, in SplitVecOp_TruncateHelper()
4377 HalfHi = DAG.getNode(N->getOpcode(), DL, {HalfVT, MVT::Other}, in SplitVecOp_TruncateHelper()
4384 HalfLo = DAG.getNode(N->getOpcode(), DL, HalfVT, InLoVec); in SplitVecOp_TruncateHelper()
4385 HalfHi = DAG.getNode(N->getOpcode(), DL, HalfVT, InHiVec); in SplitVecOp_TruncateHelper()
H A DSelectionDAGBuilder.cpp196 EVT HalfVT = EVT::getIntegerVT(*DAG.getContext(), RoundBits/2); in getCopyFromParts() local
199 Lo = getCopyFromParts(DAG, DL, Parts, RoundParts / 2, PartVT, HalfVT, V, in getCopyFromParts()
202 PartVT, HalfVT, V, InChain); in getCopyFromParts()
204 Lo = DAG.getNode(ISD::BITCAST, DL, HalfVT, Parts[0]); in getCopyFromParts()
205 Hi = DAG.getNode(ISD::BITCAST, DL, HalfVT, Parts[1]); in getCopyFromParts()
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64ISelLowering.cpp5206 EVT HalfVT = EVT::getVectorVT( in skipExtensionForVectorMULL() local
5210 return DAG.getNode(ISD::TRUNCATE, SDLoc(N), HalfVT, N); in skipExtensionForVectorMULL()
15479 EVT HalfVT = VT.getHalfNumVectorElementsVT(*DAG.getContext()); in LowerINSERT_SUBVECTOR() local
15482 Lo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, HalfVT, Vec0, in LowerINSERT_SUBVECTOR()
15484 Hi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, HalfVT, Vec0, in LowerINSERT_SUBVECTOR()
15487 Lo = DAG.getNode(ISD::INSERT_SUBVECTOR, DL, HalfVT, Lo, Vec1, in LowerINSERT_SUBVECTOR()
15490 Hi = DAG.getNode(ISD::INSERT_SUBVECTOR, DL, HalfVT, Hi, Vec1, in LowerINSERT_SUBVECTOR()
15974 EVT HalfVT = Lo.getValueType(); in getVectorBitwiseReduce() local
15975 SDValue HalfVec = DAG.getNode(ScalarOpcode, DL, HalfVT, Lo, Hi); in getVectorBitwiseReduce()
18776 EVT HalfVT = EVT::getVectorVT(*DAG.getContext(), in performMulVectorCmpZeroCombine() local
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H A DAArch64TargetTransformInfo.cpp5989 auto *HalfVT = cast<FixedVectorType>(HalfV->getType()); in areExtractShuffleVectors() local
5990 return FullVT->getNumElements() == 2 * HalfVT->getNumElements(); in areExtractShuffleVectors()
/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVISelLowering.cpp5928 MVT HalfVT = VT.getHalfNumVectorElementsVT(); in lowerVECTOR_SHUFFLE() local
5940 EvenV = DAG.getUNDEF(HalfVT); in lowerVECTOR_SHUFFLE()
5944 EvenV = DAG.getExtractSubvector(DL, HalfVT, EvenV, EvenSrc % Size); in lowerVECTOR_SHUFFLE()
5948 OddV = DAG.getUNDEF(HalfVT); in lowerVECTOR_SHUFFLE()
5952 OddV = DAG.getExtractSubvector(DL, HalfVT, OddV, OddSrc % Size); in lowerVECTOR_SHUFFLE()
7862 MVT HalfVT = VT.getHalfNumVectorElementsVT(); in LowerOperation() local
7865 SDValue Lo = DAG.getNode(ISD::CONCAT_VECTORS, DL, HalfVT, in LowerOperation()
7867 SDValue Hi = DAG.getNode(ISD::CONCAT_VECTORS, DL, HalfVT, in LowerOperation()
16195 EVT HalfVT = EVT::getVectorVT(*DAG.getContext(), in combineVectorMulToSraBitcast() local
16199 SDValue Cast = DAG.getNode(ISD::BITCAST, DL, HalfVT, Srl.getOperand(0)); in combineVectorMulToSraBitcast()
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/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMISelLowering.cpp18094 MVT ExtVT, HalfVT; in PerformMinMaxCombine() local
18096 HalfVT = MVT::v8i16; in PerformMinMaxCombine()
18099 HalfVT = MVT::v16i8; in PerformMinMaxCombine()
18107 DAG.getNode(ARMISD::VQMOVNs, DL, HalfVT, DAG.getUNDEF(HalfVT), in PerformMinMaxCombine()
18134 MVT HalfVT; in PerformMinMaxCombine() local
18137 HalfVT = MVT::v8i16; in PerformMinMaxCombine()
18140 HalfVT = MVT::v16i8; in PerformMinMaxCombine()
18148 DAG.getNode(ARMISD::VQMOVNu, DL, HalfVT, DAG.getUNDEF(HalfVT), N0, in PerformMinMaxCombine()
/freebsd/contrib/llvm-project/llvm/lib/Target/LoongArch/
H A DLoongArchISelLowering.cpp2567 MVT HalfVT = ResVT.getHalfNumVectorElementsVT(); in lowerCONCAT_VECTORS() local
2569 SDValue Lo = DAG.getNode(ISD::CONCAT_VECTORS, DL, HalfVT, in lowerCONCAT_VECTORS()
2571 SDValue Hi = DAG.getNode(ISD::CONCAT_VECTORS, DL, HalfVT, in lowerCONCAT_VECTORS()