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Searched refs:HalfVT (Results 1 – 14 of 14) sorted by relevance

/freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DValueTypes.h420 EVT HalfVT = EVT((MVT::SimpleValueType)IntVT); in getHalfSizedIntegerVT() local
421 if (HalfVT.getSizeInBits() * 2 >= EVTSize) in getHalfSizedIntegerVT()
422 return HalfVT; in getHalfSizedIntegerVT()
/freebsd/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86InterleavedAccess.cpp368 MVT HalfVT = scaleVectorType(VT); in interleave8bitStride4() local
386 createUnpackShuffleMask(HalfVT, MaskLowTemp, true, false); in interleave8bitStride4()
387 createUnpackShuffleMask(HalfVT, MaskHighTemp, false, false); in interleave8bitStride4()
H A DX86ISelLowering.cpp4129 EVT HalfVT = V.getValueType().getHalfNumVectorElementsVT(*DAG.getContext()); in isUpperSubvectorUndef() local
4131 return DAG.getNode(ISD::CONCAT_VECTORS, DL, HalfVT, LowerOps); in isUpperSubvectorUndef()
7070 EVT HalfVT = in EltsFromConsecutiveLoads() local
7073 EltsFromConsecutiveLoads(HalfVT, Elts.drop_back(HalfNumElems), DL, in EltsFromConsecutiveLoads()
8222 MVT HalfVT = VT.getHalfNumVectorElementsVT(); in getHopForBuildVector() local
8225 SDValue Half = DAG.getNode(HOpcode, DL, HalfVT, V0, V1); in getHopForBuildVector()
9249 MVT HalfVT = ResVT.getHalfNumVectorElementsVT(); in LowerAVXCONCAT_VECTORS() local
9251 SDValue Lo = DAG.getNode(ISD::CONCAT_VECTORS, dl, HalfVT, in LowerAVXCONCAT_VECTORS()
9253 SDValue Hi = DAG.getNode(ISD::CONCAT_VECTORS, dl, HalfVT, in LowerAVXCONCAT_VECTORS()
9335 MVT HalfVT = ResVT.getHalfNumVectorElementsVT(); in LowerCONCAT_VECTORSvXi1() local
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/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DAMDGPUISelLowering.cpp2028 EVT HalfVT = VT.getHalfSizedIntegerVT(*DAG.getContext()); in LowerUDIVREM64() local
2030 SDValue One = DAG.getConstant(1, DL, HalfVT); in LowerUDIVREM64()
2031 SDValue Zero = DAG.getConstant(0, DL, HalfVT); in LowerUDIVREM64()
2036 std::tie(LHS_Lo, LHS_Hi) = DAG.SplitScalar(LHS, DL, HalfVT, HalfVT); in LowerUDIVREM64()
2040 std::tie(RHS_Lo, RHS_Hi) = DAG.SplitScalar(RHS, DL, HalfVT, HalfVT); in LowerUDIVREM64()
2045 SDValue Res = DAG.getNode(ISD::UDIVREM, DL, DAG.getVTList(HalfVT, HalfVT), in LowerUDIVREM64()
2084 SDValue Rcp_Lo = DAG.getNode(ISD::FP_TO_UINT, DL, HalfVT, Mad2); in LowerUDIVREM64()
2085 SDValue Rcp_Hi = DAG.getNode(ISD::FP_TO_UINT, DL, HalfVT, Trunc); in LowerUDIVREM64()
2092 SDVTList HalfCarryVT = DAG.getVTList(HalfVT, MVT::i1); in LowerUDIVREM64()
2100 DAG.SplitScalar(Mulhi1, DL, HalfVT, HalfVT); in LowerUDIVREM64()
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H A DSIISelLowering.cpp7459 EVT HalfVT = MVT::getVectorVT(VT.getVectorElementType().getSimpleVT(), in lowerBUILD_VECTOR() local
7461 MVT HalfIntVT = MVT::getIntegerVT(HalfVT.getSizeInBits()); in lowerBUILD_VECTOR()
7470 SDValue Lo = DAG.getBuildVector(HalfVT, SL, LoOps); in lowerBUILD_VECTOR()
7471 SDValue Hi = DAG.getBuildVector(HalfVT, SL, HiOps); in lowerBUILD_VECTOR()
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DLegalizeTypes.cpp1041 EVT HalfVT = in SplitInteger() local
1043 SplitInteger(Op, HalfVT, HalfVT, Lo, Hi); in SplitInteger()
H A DLegalizeIntegerTypes.cpp4930 EVT HalfVT = LHSLow.getValueType(); in ExpandIntRes_XMULO() local
4932 SDVTList VTHalfWithO = DAG.getVTList(HalfVT, BitVT); in ExpandIntRes_XMULO()
4934 SDValue HalfZero = DAG.getConstant(0, dl, HalfVT); in ExpandIntRes_XMULO()
4945 SDValue HighSum = DAG.getNode(ISD::ADD, dl, HalfVT, One, Two); in ExpandIntRes_XMULO()
5196 EVT HalfVT = In1.getValueType(); in ExpandIntRes_FunnelShift() local
5205 unsigned HalfVTBits = HalfVT.getScalarSizeInBits(); in ExpandIntRes_FunnelShift()
5213 EVT NewShAmtVT = TLI.getShiftAmountTy(HalfVT, DAG.getDataLayout()); in ExpandIntRes_FunnelShift()
5216 SDValue Select1 = DAG.getNode(ISD::SELECT, DL, HalfVT, Cond, In1, In2); in ExpandIntRes_FunnelShift()
5217 SDValue Select2 = DAG.getNode(ISD::SELECT, DL, HalfVT, Cond, In2, In3); in ExpandIntRes_FunnelShift()
5218 SDValue Select3 = DAG.getNode(ISD::SELECT, DL, HalfVT, Cond, In3, In4); in ExpandIntRes_FunnelShift()
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H A DTargetLowering.cpp1869 EVT HalfVT = EVT::getIntegerVT(*TLO.DAG.getContext(), HalfWidth); in SimplifyDemandedBits() local
1870 if (isNarrowingProfitable(VT, HalfVT) && in SimplifyDemandedBits()
1871 isTypeDesirableForOp(ISD::SHL, HalfVT) && in SimplifyDemandedBits()
1872 isTruncateFree(VT, HalfVT) && isZExtFree(HalfVT, VT) && in SimplifyDemandedBits()
1873 (!TLO.LegalOperations() || isOperationLegal(ISD::SHL, HalfVT))) { in SimplifyDemandedBits()
1882 SDValue NewOp = TLO.DAG.getNode(ISD::TRUNCATE, dl, HalfVT, Op0); in SimplifyDemandedBits()
1884 TLO.DAG.getShiftAmountConstant(ShAmt, HalfVT, dl); in SimplifyDemandedBits()
1885 SDValue NewShift = TLO.DAG.getNode(ISD::SHL, dl, HalfVT, NewOp, in SimplifyDemandedBits()
1972 EVT HalfVT = EVT::getIntegerVT(*TLO.DAG.getContext(), BitWidth / 2); in SimplifyDemandedBits() local
1973 if (isNarrowingProfitable(VT, HalfVT) && in SimplifyDemandedBits()
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H A DDAGCombiner.cpp11052 EVT HalfVT = EVT::getIntegerVT(*DAG.getContext(), BW / 2); in visitBSWAP() local
11055 (ShAmt->getZExtValue() % 16) == 0 && TLI.isTypeLegal(HalfVT) && in visitBSWAP()
11056 TLI.isTruncateFree(VT, HalfVT) && in visitBSWAP()
11057 (!LegalOperations || hasOperation(ISD::BSWAP, HalfVT))) { in visitBSWAP()
11062 Res = DAG.getZExtOrTrunc(Res, DL, HalfVT); in visitBSWAP()
11063 Res = DAG.getNode(ISD::BSWAP, DL, HalfVT, Res); in visitBSWAP()
11205 EVT HalfVT = EVT::getIntegerVT(*DAG.getContext(), NumBits / 2); in visitCTPOP() local
11206 if (hasOperation(ISD::CTPOP, HalfVT) && in visitCTPOP()
11207 TLI.isTypeDesirableForOp(ISD::CTPOP, HalfVT) && in visitCTPOP()
11208 TLI.isTruncateFree(N0, HalfVT) && TLI.isZExtFree(HalfVT, VT)) { in visitCTPOP()
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H A DLegalizeVectorTypes.cpp4055 EVT HalfVT = EVT::getVectorVT(*DAG.getContext(), HalfElementVT, in SplitVecOp_TruncateHelper() local
4062 HalfLo = DAG.getNode(N->getOpcode(), DL, {HalfVT, MVT::Other}, in SplitVecOp_TruncateHelper()
4064 HalfHi = DAG.getNode(N->getOpcode(), DL, {HalfVT, MVT::Other}, in SplitVecOp_TruncateHelper()
4071 HalfLo = DAG.getNode(N->getOpcode(), DL, HalfVT, InLoVec); in SplitVecOp_TruncateHelper()
4072 HalfHi = DAG.getNode(N->getOpcode(), DL, HalfVT, InHiVec); in SplitVecOp_TruncateHelper()
H A DSelectionDAGBuilder.cpp200 EVT HalfVT = EVT::getIntegerVT(*DAG.getContext(), RoundBits/2); in getCopyFromParts() local
203 Lo = getCopyFromParts(DAG, DL, Parts, RoundParts / 2, PartVT, HalfVT, V, in getCopyFromParts()
206 PartVT, HalfVT, V, InChain); in getCopyFromParts()
208 Lo = DAG.getNode(ISD::BITCAST, DL, HalfVT, Parts[0]); in getCopyFromParts()
209 Hi = DAG.getNode(ISD::BITCAST, DL, HalfVT, Parts[1]); in getCopyFromParts()
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64ISelLowering.cpp14580 EVT HalfVT = VT.getHalfNumVectorElementsVT(*DAG.getContext()); in LowerINSERT_SUBVECTOR() local
14583 Lo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, HalfVT, Vec0, in LowerINSERT_SUBVECTOR()
14585 Hi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, HalfVT, Vec0, in LowerINSERT_SUBVECTOR()
14588 Lo = DAG.getNode(ISD::INSERT_SUBVECTOR, DL, HalfVT, Lo, Vec1, in LowerINSERT_SUBVECTOR()
14591 Hi = DAG.getNode(ISD::INSERT_SUBVECTOR, DL, HalfVT, Hi, Vec1, in LowerINSERT_SUBVECTOR()
15198 EVT HalfVT = Lo.getValueType(); in getVectorBitwiseReduce() local
15199 SDValue HalfVec = DAG.getNode(ScalarOpcode, DL, HalfVT, Lo, Hi); in getVectorBitwiseReduce()
15890 auto *HalfVT = cast<FixedVectorType>(HalfV->getType()); in areExtractShuffleVectors() local
15891 return FullVT->getNumElements() == 2 * HalfVT->getNumElements(); in areExtractShuffleVectors()
18189 EVT HalfVT = EVT::getVectorVT(*DAG.getContext(), in performMulVectorCmpZeroCombine() local
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/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMISelLowering.cpp18016 MVT ExtVT, HalfVT; in PerformMinMaxCombine() local
18018 HalfVT = MVT::v8i16; in PerformMinMaxCombine()
18021 HalfVT = MVT::v16i8; in PerformMinMaxCombine()
18029 DAG.getNode(ARMISD::VQMOVNs, DL, HalfVT, DAG.getUNDEF(HalfVT), in PerformMinMaxCombine()
18056 MVT HalfVT; in PerformMinMaxCombine() local
18059 HalfVT = MVT::v8i16; in PerformMinMaxCombine()
18062 HalfVT = MVT::v16i8; in PerformMinMaxCombine()
18070 DAG.getNode(ARMISD::VQMOVNu, DL, HalfVT, DAG.getUNDEF(HalfVT), N0, in PerformMinMaxCombine()
/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVISelLowering.cpp5264 MVT HalfVT = VT.getHalfNumVectorElementsVT(); in lowerVECTOR_SHUFFLE() local
5270 EvenV = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, HalfVT, EvenV, in lowerVECTOR_SHUFFLE()
5275 OddV = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, HalfVT, OddV, in lowerVECTOR_SHUFFLE()
6882 MVT HalfVT = VT.getHalfNumVectorElementsVT(); in LowerOperation() local
6885 SDValue Lo = DAG.getNode(ISD::CONCAT_VECTORS, DL, HalfVT, in LowerOperation()
6887 SDValue Hi = DAG.getNode(ISD::CONCAT_VECTORS, DL, HalfVT, in LowerOperation()
14041 EVT HalfVT = EVT::getVectorVT(*DAG.getContext(), in combineVectorMulToSraBitcast() local
14045 SDValue Cast = DAG.getNode(ISD::BITCAST, DL, HalfVT, Srl.getOperand(0)); in combineVectorMulToSraBitcast()
14046 SDValue Sra = DAG.getNode(ISD::SRA, DL, HalfVT, Cast, in combineVectorMulToSraBitcast()
14047 DAG.getConstant(HalfSize - 1, DL, HalfVT)); in combineVectorMulToSraBitcast()