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Searched refs:GRLenVT (Results 1 – 9 of 9) sorted by relevance

/freebsd/contrib/llvm-project/llvm/lib/Target/LoongArch/
H A DLoongArchISelDAGToDAG.cpp46 MVT GRLenVT = Subtarget->getGRLenVT(); in INITIALIZE_PASS() local
55 if (Imm == 0 && VT == GRLenVT) { in INITIALIZE_PASS()
57 LoongArch::R0, GRLenVT); in INITIALIZE_PASS()
62 SDValue SrcReg = CurDAG->getRegister(LoongArch::R0, GRLenVT); in INITIALIZE_PASS()
65 SDValue SDImm = CurDAG->getSignedTargetConstant(Inst.Imm, DL, GRLenVT); in INITIALIZE_PASS()
68 Result = CurDAG->getMachineNode(Inst.Opc, DL, GRLenVT, SDImm); in INITIALIZE_PASS()
74 Result = CurDAG->getMachineNode(Inst.Opc, DL, GRLenVT, SrcReg, SDImm); in INITIALIZE_PASS()
78 Inst.Opc, DL, GRLenVT, in INITIALIZE_PASS()
80 CurDAG->getSignedTargetConstant(Inst.Imm >> 32, DL, GRLenVT), in INITIALIZE_PASS()
81 CurDAG->getTargetConstant(Inst.Imm & 0xFF, DL, GRLenVT)}); in INITIALIZE_PASS()
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H A DLoongArchInstrInfo.td24 def SDT_LoongArchCall : SDTypeProfile<0, -1, [SDTCisVT<0, GRLenVT>]>;
44 def SDT_LoongArchVI : SDTypeProfile<0, 1, [SDTCisVT<0, GRLenVT>]>;
47 SDTCisVT<1, GRLenVT>]>;
49 SDTCisVT<2, GRLenVT>]>;
53 SDTCisVT<3, GRLenVT>]>;
56 def SDT_LoongArchMovgr2fcsr : SDTypeProfile<0, 2, [SDTCisVT<0, GRLenVT>,
58 def SDT_LoongArchMovfcsr2gr : SDTypeProfile<1, 1, [SDTCisVT<0, GRLenVT>,
240 def grlenimm : Operand<GRLenVT>;
241 def imm32 : Operand<GRLenVT> {
248 def uimm1 : Operand<GRLenVT>, ImmLeaf<GRLenVT, [{return isUInt<1>(Imm);}]>{
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H A DLoongArchSubtarget.h44 MVT GRLenVT = MVT::i32; variable
95 MVT getGRLenVT() const { return GRLenVT; } in getGRLenVT()
H A DLoongArchISelLowering.cpp51 MVT GRLenVT = Subtarget.getGRLenVT(); in LoongArchTargetLowering() local
55 addRegisterClass(GRLenVT, &LoongArch::GPRRegClass); in LoongArchTargetLowering()
76 setLoadExtAction({ISD::EXTLOAD, ISD::SEXTLOAD, ISD::ZEXTLOAD}, GRLenVT, in LoongArchTargetLowering()
79 setOperationAction(ISD::SHL_PARTS, GRLenVT, Custom); in LoongArchTargetLowering()
80 setOperationAction(ISD::SRA_PARTS, GRLenVT, Custom); in LoongArchTargetLowering()
81 setOperationAction(ISD::SRL_PARTS, GRLenVT, Custom); in LoongArchTargetLowering()
82 setOperationAction(ISD::FP_TO_SINT, GRLenVT, Custom); in LoongArchTargetLowering()
83 setOperationAction(ISD::ROTL, GRLenVT, Expand); in LoongArchTargetLowering()
84 setOperationAction(ISD::CTPOP, GRLenVT, Expand); in LoongArchTargetLowering()
88 GRLenVT, Custom); in LoongArchTargetLowering()
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H A DLoongArchRegisterInfo.td94 def GRLenVT : ValueTypeByHwMode<[LA32, LA64],
101 : RegisterClass<"LoongArch", [GRLenVT], 32, regList> {
186 def CFR : RegisterClass<"LoongArch", [GRLenVT], 32, (sequence "FCC%u", 0, 7)> {
224 def SCR : RegisterClass<"LoongArch", [GRLenVT], 32, (sequence "SCR%u", 0, 3)>;
H A DLoongArchSubtarget.cpp47 GRLenVT = MVT::i64; in initializeSubtargetDependencies()
H A DLoongArchLASXInstrInfo.td1586 def : Pat<(vector_insert v32i8:$xd, GRLenVT:$rj, uimm5:$imm),
1587 (PseudoXVINSGR2VR_B v32i8:$xd, GRLenVT:$rj, uimm5:$imm)>;
1588 def : Pat<(vector_insert v16i16:$xd, GRLenVT:$rj, uimm4:$imm),
1589 (PseudoXVINSGR2VR_H v16i16:$xd, GRLenVT:$rj, uimm4:$imm)>;
1592 def : Pat<(vector_insert v8i32:$xd, GRLenVT:$rj, uimm3:$imm),
1593 (XVINSGR2VR_W v8i32:$xd, GRLenVT:$rj, uimm3:$imm)>;
1594 def : Pat<(vector_insert v4i64:$xd, GRLenVT:$rj, uimm2:$imm),
1595 (XVINSGR2VR_D v4i64:$xd, GRLenVT:$rj, uimm2:$imm)>;
1620 def : Pat<(v32i8 (loongarch_vreplgr2vr GRLenVT:$rj)),
1621 (v32i8 (XVREPLGR2VR_B GRLenVT:$rj))>;
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H A DLoongArchLSXInstrInfo.td1786 def : Pat<(vector_insert v16i8:$vd, GRLenVT:$rj, uimm4:$imm),
1787 (VINSGR2VR_B v16i8:$vd, GRLenVT:$rj, uimm4:$imm)>;
1788 def : Pat<(vector_insert v8i16:$vd, GRLenVT:$rj, uimm3:$imm),
1789 (VINSGR2VR_H v8i16:$vd, GRLenVT:$rj, uimm3:$imm)>;
1790 def : Pat<(vector_insert v4i32:$vd, GRLenVT:$rj, uimm2:$imm),
1791 (VINSGR2VR_W v4i32:$vd, GRLenVT:$rj, uimm2:$imm)>;
1792 def : Pat<(vector_insert v2i64:$vd, GRLenVT:$rj, uimm1:$imm),
1793 (VINSGR2VR_D v2i64:$vd, GRLenVT:$rj, uimm1:$imm)>;
1827 def : Pat<(v16i8 (loongarch_vreplgr2vr GRLenVT:$rj)),
1828 (v16i8 (VREPLGR2VR_B GRLenVT:$rj))>;
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H A DLoongArchFloat32InstrInfo.td211 def : Pat<(brcond (xor (GRLenVT (setcc RegTy:$fj, RegTy:$fk, cc)), -1),
214 def : Pat<(brcond (GRLenVT (setcc RegTy:$fj, RegTy:$fk, cc)), bb:$imm21),
256 : Pat<(select (GRLenVT (setcc RegTy:$a, RegTy:$b, cc)), RegTy:$t, RegTy:$f),