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Searched refs:GPR_32 (Results 1 – 5 of 5) sorted by relevance

/freebsd/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86GenRegisterBankInfo.def64 INSTR_3OP(BREAKDOWN(PMI_GPR32, 1)) // 6: GPR_32
H A DX86CallingConv.td42 list<Register> GPR_32 = [];
55 let GPR_32 = [EAX, ECX, EDX, EDI, ESI];
69 let GPR_32 = [ECX, EDX, EDI, ESI];
89 let GPR_32 = [EAX, ECX, EDX, EDI, ESI, R8D, R9D, R10D, R11D, R12D, R14D, R15D];
101 let GPR_32 = [EAX, ECX, EDX, EDI, ESI, R8D, R9D, R11D, R12D, R14D, R15D];
108 let GPR_32 = [EAX, ECX, EDX, EDI, ESI, R8D, R9D, R12D, R13D, R14D, R15D];
126 CCIfType<[i32], CCAssignToReg<RC.GPR_32>>,
205 CCIfType<[i32], CCAssignToReg<RC.GPR_32>>,
/freebsd/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMipsInstrInfo.td267 class GPR_32 { list<Predicate> GPRPredicates = [IsGP32bit]; }
2679 GPR_32, ISA_MIPS1;
2682 GPR_32, ISA_MIPS1;
2711 "sge\t$rd, $rs, $imm">, GPR_32;
2715 GPR_32;
2725 "sgeu\t$rd, $rs, $imm">, GPR_32;
2729 GPR_32;
2740 "sgt\t$rd, $rs, $imm">, GPR_32;
2744 GPR_32;
2754 "sgtu\t$rd, $rs, $imm">, GPR_32;
[all …]
H A DMips32r6InstrInfo.td972 def SELEQZ : R6MMR6Rel, SELEQZ_ENC, SELEQZ_DESC, ISA_MIPS32R6, GPR_32;
973 def SELNEZ : R6MMR6Rel, SELNEZ_ENC, SELNEZ_DESC, ISA_MIPS32R6, GPR_32;
1016 ISA_MIPS32R6, GPR_32;
1019 def : MipsInstAlias<"jrc $rs", (JIC GPR32Opnd:$rs, 0), 1>, ISA_MIPS32R6, GPR_32;
1023 ISA_MIPS32R6, GPR_32;
/freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCISelLowering.cpp6860 static const MCPhysReg GPR_32[] = {// 32-bit registers. in CC_AIX() local
6872 const ArrayRef<MCPhysReg> GPRs = IsPPC64 ? GPR_64 : GPR_32; in CC_AIX()
7452 static const MCPhysReg GPR_32[] = {PPC::R3, PPC::R4, PPC::R5, PPC::R6, in LowerFormalArguments_AIX() local
7457 const unsigned NumGPArgRegs = std::size(IsPPC64 ? GPR_64 : GPR_32); in LowerFormalArguments_AIX()
7468 : MF.addLiveIn(GPR_32[GPRIndex], &PPC::GPRCRegClass); in LowerFormalArguments_AIX()