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Searched refs:GFX9 (Results 1 – 25 of 28) sorted by relevance

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/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DGCNSubtarget.h425 return getGeneration() >= AMDGPUSubtarget::GFX9; in hasMed3_16()
429 return getGeneration() >= AMDGPUSubtarget::GFX9; in hasMin3Max3_16()
464 return getGeneration() >= GFX9; in supportsGetDoorbellID()
524 return getGeneration() >= AMDGPUSubtarget::GFX9; in supportsMinMaxDenormModes()
555 return getGeneration() < AMDGPUSubtarget::GFX9; in privateMemoryResourceIsRangeChecked()
678 return getGeneration() >= GFX9; in hasMultiDwordFlatScratchAddressing()
686 return getGeneration() > GFX9; in hasFlatLgkmVMemCountInOrder()
690 return getGeneration() >= GFX9; in hasD16LoadStore()
704 return getGeneration() < GFX9; in ldsRequiresM0Init()
713 return getGeneration() >= GFX9; in hasGWSAutoReplay()
[all …]
H A DAMDGPU.td271 "Negative immediate offsets in scratch instructions with an SGPR offset page fault on GFX9"
347 "Additional instructions for GFX9+"
390 "Instructions shared in GFX7, GFX8, GFX9"
1167 def FeatureGFX9 : GCNSubtargetFeatureGeneration<"GFX9",
1806 "Subtarget->getGeneration() == AMDGPUSubtarget::GFX9">,
1813 "Subtarget->getGeneration() == AMDGPUSubtarget::GFX9">,
1821 " Subtarget->getGeneration() == AMDGPUSubtarget::GFX9)">,
1828 "Subtarget->getGeneration() == AMDGPUSubtarget::GFX9 ||"
1839 "Subtarget->getGeneration() == AMDGPUSubtarget::GFX9 ||"
1845 "Subtarget->getGeneration() == AMDGPUSubtarget::GFX9 ||"
[all …]
H A DAMDGPUSubtarget.h40 GFX9 = 8, enumerator
H A DSMInstructions.td525 // VI and GFX9.
539 // Note that for GFX9 instructions with immediate offsets, soffset_en
541 // meaning GFX9 is not perfectly backward-compatible with GFX8, despite
558 // VI supports 20-bit unsigned offsets while GFX9+ supports 21-bit signed.
575 // The alternative GFX9 SGPR encoding using soffset to encode the
576 // offset register. Not available in assembler and goes to the GFX9
582 int Subtarget = SIEncodingFamily.GFX9;
668 // GFX9
H A DVOP3Instructions.td414 // on GFX8 and GFX9 and preserve high 16 bits on GFX10+
807 // exclude pre-GFX9 where it was slow
1477 // GFX8, GFX9 (VI).
1529 let AssemblerPredicate = isGFX9Only, DecoderNamespace = "GFX9" in {
1532 def _gfx9 : VOP3_Real<!cast<VOP3_Pseudo>(OpName#"_e64"), SIEncodingFamily.GFX9>,
1540 def _gfx9 : VOP3_Real<!cast<VOP3_Pseudo>(NAME#"_e64"), SIEncodingFamily.GFX9>,
1548 def _gfx9 : VOP3_Real<!cast<VOP3_Pseudo>(OpName), SIEncodingFamily.GFX9>,
1556 def _gfx9 : VOP3_Real<!cast<VOP_Pseudo>(NAME#"_e64"), SIEncodingFamily.GFX9>,
1563 } // End AssemblerPredicate = isGFX9Only, DecoderNamespace = "GFX9"
H A DGCNProcessors.td160 // GCN GFX9.
H A DVOP2Instructions.td1143 // on GFX8 and GFX9 and preserve high 16 bits on GFX10+
2205 // GFX8, GFX9 (VI).
2218 let DecoderNamespace = "GFX9";
2295 let AssemblerPredicate = isGFX9Only, DecoderNamespace = "GFX9" in {
2299 VOP2_Real<!cast<VOP2_Pseudo>(OpName#"_e32"), SIEncodingFamily.GFX9>,
2305 VOP3_Real<!cast<VOP3_Pseudo>(OpName#"_e64"), SIEncodingFamily.GFX9>,
2319 VOP_DPP_Real<!cast<VOP2_DPP_Pseudo>(OpName#"_dpp"), SIEncodingFamily.GFX9>,
2328 VOP2_Real<!cast<VOP2_Pseudo>(NAME#"_e32"), SIEncodingFamily.GFX9>,
2331 VOP3_Real<!cast<VOP3_Pseudo>(NAME#"_e64"), SIEncodingFamily.GFX9>,
2340 VOP_DPP_Real<!cast<VOP2_DPP_Pseudo>(NAME#"_dpp"), SIEncodingFamily.GFX9>,
[all …]
H A DAMDGPUSubtarget.cpp165 HasSMulHi = getGeneration() >= AMDGPUSubtarget::GFX9; in initializeSubtargetDependencies()
321 return getGeneration() <= AMDGPUSubtarget::GFX9; in zeroesHigh16BitsOfDest()
H A DVOP1Instructions.td1209 // GFX8, GFX9 (VI).
1410 // GFX9
1413 let AssemblerPredicate = isGFX9Only, DecoderNamespace = "GFX9" in {
1424 VOP_DPP_Real<!cast<VOP1_DPP_Pseudo>(NAME#"_dpp"), SIEncodingFamily.GFX9>,
1440 VOP_DPP_Real<!cast<VOP1_DPP_Pseudo>(NAME#"_dpp"), SIEncodingFamily.GFX9>,
H A DSIDefines.h41 GFX9 = 5, enumerator
H A DSOPInstructions.td1843 // On GFX9+:
2681 // SOPP - GFX6, GFX7, GFX8, GFX9, GFX10
2853 // SOPC - GFX6, GFX7, GFX8, GFX9, GFX10
2906 // GFX8 (VI), GFX9.
3045 // SOP1 - GFX9.
3055 // SOP2 - GFX9.
H A DAMDGPUSearchableTables.td77 // Buffer formats with equal component sizes (GFX9 and earlier)
H A DSIInstrFormats.td88 // in GFX9. Required for correct mapping from pseudo to MC.
H A DSIMachineFunctionInfo.cpp150 if (ST.getGeneration() >= AMDGPUSubtarget::GFX9 && in SIMachineFunctionInfo()
H A DVOPInstructions.td535 // GFX9 adds two features to SDWA:
546 // In GFX9, V_MAC_F16, V_MAC_F32 opcodes cannot be used with SDWA
678 let DecoderNamespace = "GFX9";
H A DFLATInstructions.td131 // Only valid on GFX9+
145 let Inst{55} = acc; // nv on GFX9+, TFE before. AccVGPR for data on GFX90A.
1845 let DecoderNamespace = "GFX9";
1856 let DecoderNamespace = "GFX9";
H A DSIInstrInfo.cpp8614 ST.getGeneration() <= AMDGPUSubtarget::GFX9) in getScratchRsrcWords23()
9194 case AMDGPUSubtarget::GFX9: in subtargetEncodingFamily()
9232 ST.getGeneration() == AMDGPUSubtarget::GFX9) in pseudoToMCOpcode()
9233 Gen = SIEncodingFamily::GFX9; in pseudoToMCOpcode()
9246 case AMDGPUSubtarget::GFX9: in pseudoToMCOpcode()
9274 NMCOp = AMDGPU::getMCOpcode(Opcode, SIEncodingFamily::GFX9); in pseudoToMCOpcode()
H A DSIFrameLowering.cpp504 assert(ST.getGeneration() < AMDGPUSubtarget::GFX9); in emitEntryFunctionFlatScratchInit()
H A DSIInstrInfo.td27 int GFX9 = 5;
2787 [!cast<string>(SIEncodingFamily.GFX9)],
H A DBUFInstructions.td3035 // GFX8, GFX9 (VI).
3086 let DecoderNamespace = "GFX9";
H A DDSInstructions.td1558 // GFX8, GFX9 (VI).
H A DAMDGPUISelDAGToDAG.cpp181 return Subtarget->getGeneration() <= AMDGPUSubtarget::GFX9; in fp16SrcZerosHighBits()
/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/MCTargetDesc/
H A DAMDGPUTargetStreamer.cpp779 Version = GenericVersion::GFX9; in getEFlagsV6()
/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/Utils/
H A DAMDGPUBaseInfo.h48 static constexpr unsigned GFX9 = 1; variable
/freebsd/contrib/llvm-project/clang/include/clang/Basic/
H A DBuiltinsAMDGPU.def233 // GFX9+ only builtins.

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