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Searched refs:GFX12 (Results 1 – 25 of 36) sorted by relevance

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/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DGCNSubtarget.h349 if (getGeneration() >= GFX12) { in getMaxWaveScratchSize()
481 bool hasScalarSubwordLoads() const { return getGeneration() >= GFX12; } in hasScalarSubwordLoads()
762 bool hasScalarAddSub64() const { return getGeneration() >= GFX12; } in hasScalarAddSub64()
764 bool hasScalarSMulU64() const { return getGeneration() >= GFX12; } in hasScalarSMulU64()
989 bool hasSCmpK() const { return getGeneration() < GFX12; } in hasSCmpK()
1137 bool hasNonNSAEncoding() const { return getGeneration() < GFX12; } in hasNonNSAEncoding()
1283 bool hasLdsWaitVMSRC() const { return getGeneration() >= GFX12; } in hasLdsWaitVMSRC()
1299 bool hasVALUReadSGPRHazard() const { return getGeneration() == GFX12; } in hasVALUReadSGPRHazard()
1355 bool hasExtendedWaitCounts() const { return getGeneration() >= GFX12; } in hasExtendedWaitCounts()
1360 return getGeneration() == GFX12; in hasNoF16PseudoScalarTransInlineConstants()
[all …]
H A DDSDIRInstructions.td180 // GFX12+
187 SIEncodingFamily.GFX12>,
190 let DecoderNamespace = "GFX12";
H A DEXPInstructions.td104 // GFX11, GFX12.
119 def _gfx12 : EXP_Real_Row<ps, SIEncodingFamily.GFX12, "export">,
123 let DecoderNamespace = "GFX12";
H A DAMDGPUMarkLastScratchLoad.cpp89 if (ST.getGeneration() < AMDGPUSubtarget::GFX12) in run()
H A DAMDGPUSubtarget.h44 GFX12 = 11, enumerator
H A DVINTERPInstructions.td252 let AssemblerPredicate = isGFX12Only, DecoderNamespace = "GFX12" #
255 VINTERP_Real<ps, SIEncodingFamily.GFX12, asmName>,
H A DMIMGInstructions.td104 field bits<8> GFX12 = gfx12;
501 : VIMAGE_gfx12<op.GFX12, (outs DataRC:$vdata), num_addrs, dns> {
513 : VSAMPLE_gfx12<op.GFX12, (outs DataRC:$vdata), num_addrs, dns, Addr3RC> {
530 : VSAMPLE_gfx12<op.GFX12, (outs), num_addrs, dns, Addr3RC> {
644 !if(enableDisasm, "GFX12", "")>;
648 !if(enableDisasm, "GFX12", "")>;
761 : VIMAGE_gfx12<op.GFX12, (outs), num_addrs, dns> {
847 !if(enableDisasm, "GFX12", "")>;
977 : VIMAGE_gfx12<op.GFX12, (outs DataRC:$vdst), num_addrs,
978 !if(enableDisasm, "GFX12", "")> {
[all …]
H A DAMDGPU.td493 "Additional instructions for GFX12+"
977 "BUFFER/IMAGE store instructions set unspecified components to zero (before GFX12)"
983 "BUFFER/IMAGE store instructions set unspecified components to x component (GFX12)"
1473 def FeatureGFX12 : GCNSubtargetFeatureGeneration<"GFX12",
2277 "Subtarget->getGeneration() < AMDGPUSubtarget::GFX12">,
2295 Predicate<"Subtarget->getGeneration() == AMDGPUSubtarget::GFX12">,
2299 …Predicate<"Subtarget->getGeneration() == AMDGPUSubtarget::GFX12 && !Subtarget->hasGFX1250Insts()">,
2303 Predicate<"Subtarget->getGeneration() >= AMDGPUSubtarget::GFX12">,
2307 …Predicate<"Subtarget->getGeneration() >= AMDGPUSubtarget::GFX12 && !Subtarget->hasGFX1250Insts()">,
H A DGCNVOPDUtils.cpp155 bool SkipSrc = ST.getGeneration() >= AMDGPUSubtarget::GFX12 && in checkVOPDRegConstraints()
H A DGCNProcessors.td313 // GCN GFX12.
H A DDSInstructions.td768 // Instruction definitions for GFX12 and newer.
1336 // Base ENC_DS for GFX6, GFX7, GFX10, GFX11, GFX12.
1358 // GFX12.
1364 let DecoderNamespace = "GFX12" in
1366 Base_DS_Real_gfx6_gfx7_gfx10_gfx11_gfx12<op, ps, SIEncodingFamily.GFX12,
1406 // New aliases added in GFX12 without renaming the instructions.
1518 // GFX10, GFX11, GFX12.
1533 // GFX7, GFX10, GFX11, GFX12.
H A DSOPInstructions.td926 // On GFX12 MIN/MAX instructions do not read MODE register.
2006 // SOP1 - GFX11, GFX12
2134 // SOP1 - GFX1150, GFX12
2253 // SOP2 - GFX12
2272 // SOP2 - GFX11, GFX12.
2336 // SOP2 - GFX1150, GFX12
2462 // SOPK - GFX11, GFX12.
2604 // SOPP - GFX12 only.
2637 // SOPP - GFX11, GFX12.
2849 // SOPC - GFX11, GFX12.
[all …]
H A DSIInstrInfo.td33 int GFX12 = 11;
49 def GFX12Not12_50Gen : GFXGen<isGFX12Not12_50, "GFX12", "_gfx12", SIEncodingFamily.GFX12>;
50 def GFX12Gen : GFXGen<isGFX12Only, "GFX12", "_gfx12", SIEncodingFamily.GFX12>;
992 N->getZExtValue() & (Subtarget->getGeneration() >= AMDGPUSubtarget::GFX12
1000 N->getZExtValue() & (Subtarget->getGeneration() >= AMDGPUSubtarget::GFX12
1007 const uint32_t cpol = N->getZExtValue() & (Subtarget->getGeneration() >= AMDGPUSubtarget::GFX12
3173 [!cast<string>(SIEncodingFamily.GFX12)],
H A DGCNSubtarget.cpp586 if (getGeneration() >= AMDGPUSubtarget::GFX12) in getNSAThreshold()
H A DSIDefines.h47 GFX12 = 11, enumerator
H A DSMInstructions.td1449 // GFX12.
1465 SMEM_Real_gfx12Plus<op, ps, opName, SIEncodingFamily.GFX12,
1468 let DecoderNamespace = "GFX12";
H A DAMDGPUAsmPrinter.cpp1347 if (STM.getGeneration() >= AMDGPUSubtarget::GFX12) { in EmitProgramInfoSI()
1375 if (STM.getGeneration() >= AMDGPUSubtarget::GFX12) { in EmitProgramInfoSI()
H A DVOP1Instructions.td926 // GFX11, GFX12
1225 // GFX7, GFX10, GFX11, GFX12
1257 // GFX6, GFX7, GFX10, GFX11, GFX12
H A DBUFInstructions.td2401 // Base ENC_VBUFFER for GFX12.
2463 SIMCInstr<ps.PseudoInstr, SIEncodingFamily.GFX12> {
2465 let DecoderNamespace = "GFX12";
2479 let DecoderNamespace = "GFX12";
2492 // MUBUF - GFX11, GFX12.
H A DAMDGPURegBankLegalizeRules.cpp617 bool hasUnalignedLoads = ST->getGeneration() >= AMDGPUSubtarget::GFX12; in RegBankLegalizeRules()
H A DVOP3PInstructions.td1858 // GFX11, GFX12
1902 let WaveSizePredicate = isWave32, DecoderNamespace = "GFX12" in {
1914 let WaveSizePredicate = isWave32, DecoderNamespace = "GFX12" in {
2054 // GFX12
H A DVOP3Instructions.td1696 // GFX12.
1745 // GFX11, GFX12
1909 // These instructions differ from GFX12 variant by supporting DPP:
/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/MCTargetDesc/
H A DAMDGPUTargetStreamer.cpp840 Version = GenericVersion::GFX12; in getEFlagsV6()
/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/Utils/
H A DAMDGPUBaseInfo.h57 static constexpr unsigned GFX12 = 1; variable
/freebsd/contrib/llvm-project/clang/include/clang/Basic/
H A DBuiltinsAMDGPU.def485 // GFX12+ only builtins.

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