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Searched refs:GFX12 (Results 1 – 25 of 33) sorted by relevance

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/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DGCNSubtarget.h324 if (getGeneration() >= GFX12) { in getMaxWaveScratchSize()
456 bool hasScalarSubwordLoads() const { return getGeneration() >= GFX12; } in hasScalarSubwordLoads()
729 bool hasScalarAddSub64() const { return getGeneration() >= GFX12; } in hasScalarAddSub64()
731 bool hasScalarSMulU64() const { return getGeneration() >= GFX12; } in hasScalarSMulU64()
944 bool hasSCmpK() const { return getGeneration() < GFX12; } in hasSCmpK()
1090 bool hasNonNSAEncoding() const { return getGeneration() < GFX12; } in hasNonNSAEncoding()
1236 bool hasLdsWaitVMSRC() const { return getGeneration() >= GFX12; } in hasLdsWaitVMSRC()
1293 bool hasExtendedWaitCounts() const { return getGeneration() >= GFX12; } in hasExtendedWaitCounts()
1298 return getGeneration() == GFX12; in hasNoF16PseudoScalarTransInlineConstants()
1353 bool hasSplitBarriers() const { return getGeneration() >= GFX12; } in hasSplitBarriers()
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H A DDSDIRInstructions.td180 // GFX12+
187 SIEncodingFamily.GFX12>,
190 let DecoderNamespace = "GFX12";
H A DEXPInstructions.td104 // GFX11, GFX12.
119 def _gfx12 : EXP_Real_Row<ps, SIEncodingFamily.GFX12, "export">,
122 let DecoderNamespace = "GFX12";
H A DVINTERPInstructions.td196 let AssemblerPredicate = isGFX12Only, DecoderNamespace = "GFX12" in {
198 VINTERP_Real<!cast<VOP3_Pseudo>(NAME), SIEncodingFamily.GFX12>,
H A DAMDGPUMarkLastScratchLoad.cpp64 if (ST.getGeneration() < AMDGPUSubtarget::GFX12) in runOnMachineFunction()
H A DAMDGPUSubtarget.h43 GFX12 = 11, enumerator
H A DMIMGInstructions.td102 field bits<8> GFX12 = gfx12;
499 : VIMAGE_gfx12<op.GFX12, (outs DataRC:$vdata), num_addrs, dns> {
511 : VSAMPLE_gfx12<op.GFX12, (outs DataRC:$vdata), num_addrs, dns, Addr3RC> {
528 : VSAMPLE_gfx12<op.GFX12, (outs), num_addrs, dns, Addr3RC> {
571 !if(enableDisasm, "GFX12", "")>;
643 !if(enableDisasm, "GFX12", "")>;
647 !if(enableDisasm, "GFX12", "")>;
760 : VIMAGE_gfx12<op.GFX12, (outs), num_addrs, dns> {
793 !if(enableDisasm, "GFX12", "")>;
847 !if(enableDisasm, "GFX12", "")>;
[all …]
H A DDSInstructions.td726 // Instruction definitions for GFX12 and newer.
1186 // Base ENC_DS for GFX6, GFX7, GFX10, GFX11, GFX12.
1208 // GFX12.
1214 let DecoderNamespace = "GFX12" in
1216 Base_DS_Real_gfx6_gfx7_gfx10_gfx11_gfx12<op, ps, SIEncodingFamily.GFX12,
1240 // New aliases added in GFX12 without renaming the instructions.
1348 // GFX10, GFX11, GFX12.
1363 // GFX7, GFX10, GFX11, GFX12.
H A DGCNProcessors.td308 // GCN GFX12.
H A DSOPInstructions.td947 // On GFX12 MIN/MAX instructions do not read MODE register.
1985 // SOP1 - GFX11, GFX12
2103 // SOP1 - GFX1150, GFX12
2222 // SOP2 - GFX12
2241 // SOP2 - GFX11, GFX12.
2305 // SOP2 - GFX1150, GFX12
2431 // SOPK - GFX11, GFX12.
2562 // SOPP - GFX12 only.
2588 // SOPP - GFX11, GFX12.
2675 // SOPP - GFX1150, GFX12.
[all …]
H A DAMDGPU.td378 "Additional instructions for GFX12+"
818 "BUFFER/IMAGE store instructions set unspecified components to zero (before GFX12)"
824 "BUFFER/IMAGE store instructions set unspecified components to x component (GFX12)"
1233 def FeatureGFX12 : GCNSubtargetFeatureGeneration<"GFX12",
1952 Predicate<"Subtarget->getGeneration() == AMDGPUSubtarget::GFX12">,
1956 Predicate<"Subtarget->getGeneration() >= AMDGPUSubtarget::GFX12">,
H A DSIDefines.h47 GFX12 = 11, enumerator
H A DSIInstrInfo.td33 int GFX12 = 11;
47 def GFX12Gen : GFXGen<isGFX12Only, "GFX12", "_gfx12", SIEncodingFamily.GFX12>;
874 N->getZExtValue() & (Subtarget->getGeneration() >= AMDGPUSubtarget::GFX12
882 N->getZExtValue() & (Subtarget->getGeneration() >= AMDGPUSubtarget::GFX12
889 const uint32_t cpol = N->getZExtValue() & (Subtarget->getGeneration() >= AMDGPUSubtarget::GFX12
2793 [!cast<string>(SIEncodingFamily.GFX12)]];
H A DAMDGPUAsmPrinter.cpp1150 if (STM.getGeneration() >= AMDGPUSubtarget::GFX12) { in EmitProgramInfoSI()
1178 if (STM.getGeneration() >= AMDGPUSubtarget::GFX12) { in EmitProgramInfoSI()
H A DVOP1Instructions.td807 // GFX11, GFX12
1077 // GFX7, GFX10, GFX11, GFX12
1109 // GFX6, GFX7, GFX10, GFX11, GFX12
H A DSMInstructions.td1412 // GFX12.
1428 SMEM_Real_gfx12Plus<op, ps, opName, SIEncodingFamily.GFX12,
1431 let DecoderNamespace = "GFX12";
H A DAMDGPUSubtarget.cpp1024 if (getGeneration() >= AMDGPUSubtarget::GFX12) in getNSAThreshold()
H A DBUFInstructions.td2407 // Base ENC_VBUFFER for GFX12.
2468 SIMCInstr<ps.PseudoInstr, SIEncodingFamily.GFX12> {
2470 let DecoderNamespace = "GFX12";
2484 let DecoderNamespace = "GFX12";
2497 // MUBUF - GFX11, GFX12.
H A DVOP3PInstructions.td1379 // GFX11, GFX12
1422 let WaveSizePredicate = isWave32, DecoderNamespace = "GFX12" in {
1525 // GFX12
H A DFLATInstructions.td2536 // GFX12
2542 SIMCInstr <ps.PseudoInstr, SIEncodingFamily.GFX12> {
2544 let DecoderNamespace = "GFX12";
H A DVOP3Instructions.td1038 // GFX12.
1087 // GFX11, GFX12
/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/MCTargetDesc/
H A DAMDGPUTargetStreamer.cpp791 Version = GenericVersion::GFX12; in getEFlagsV6()
/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/Utils/
H A DAMDGPUBaseInfo.h52 static constexpr unsigned GFX12 = 1; variable
/freebsd/contrib/llvm-project/clang/include/clang/Basic/
H A DBuiltinsAMDGPU.def435 // GFX12+ only builtins.
/freebsd/contrib/llvm-project/llvm/include/llvm/IR/
H A DIntrinsicsAMDGPU.td325 // GFX12 intrinsics
2498 llvm_i1_ty, // %high (op_sel) for GFX11, 0 for GFX12
2536 // GFX12: The op_sel bit must be 0.
2542 // GFX12 Intrinsics

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