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Searched refs:GFX10 (Results 1 – 25 of 34) sorted by relevance

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/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DGCNSubtarget.h356 bool supportsWGP() const { return getGeneration() >= GFX10; } in supportsWGP()
490 return getGeneration() >= GFX10; in partialVCCWritesUpdateVCCZ()
529 return getGeneration() >= AMDGPUSubtarget::GFX10; in hasDenormModeInst()
938 return getGeneration() == GFX10 || getGeneration() == GFX11; in hasInstPrefetch()
1018 bool hasPermLaneX16() const { return getGeneration() >= GFX10; } in hasPermLaneX16()
1028 return HasDPP && getGeneration() < GFX10; in hasDPPBroadcasts()
1032 return HasDPP && getGeneration() < GFX10; in hasDPPWavefrontShifts()
1055 return getGeneration() >= GFX10 || hasGFX940Insts(); in hasFmaakFmamkF32Insts()
1229 return getGeneration() == GFX10; in hasFPAtomicToDenormModeHazard()
H A DEXPInstructions.td69 // SI, VI, GFX10.
93 def _gfx10 : EXP_Real_ComprVM<ps, SIEncodingFamily.GFX10>, EXPe_ComprVM {
95 let DecoderNamespace = "GFX10";
H A DAMDGPU.td190 "Some GFX10 bug with multi-dword LDS and flat access that is not naturally aligned in WGP mode"
259 "MIMG-NSA in a hard clause has unpredictable results on GFX10.1"
265 "GFX10 bug where inst_offset is ignored when flat instructions access global memory"
277 …VGPR offset and a negative immediate offset that is not a multiple of 4 read wrong memory on GFX10"
366 "Additional instructions for GFX10+"
384 "Additional instructions for GFX10.3"
1186 def FeatureGFX10 : GCNSubtargetFeatureGeneration<"GFX10",
1779 "Subtarget->getGeneration() == AMDGPUSubtarget::GFX10">,
1785 "Subtarget->getGeneration() >= AMDGPUSubtarget::GFX10">,
1794 "Subtarget->getGeneration() == AMDGPUSubtarget::GFX10">,
[all …]
H A DVOP3Instructions.td414 // on GFX8 and GFX9 and preserve high 16 bits on GFX10+
1234 // GFX10.
1237 let AssemblerPredicate = isGFX10Only, DecoderNamespace = "GFX10" in {
1240 VOP3_Real<!cast<VOP_Pseudo>(NAME#"_e64"), SIEncodingFamily.GFX10>,
1245 VOP3_Real<!cast<VOP_Pseudo>(NAME), SIEncodingFamily.GFX10>,
1251 VOP3_Real<!cast<VOP3_Pseudo>(opName#"_e64"), SIEncodingFamily.GFX10>,
1260 VOP3_Real<!cast<VOP3_Pseudo>(NAME#"_e64"), SIEncodingFamily.GFX10>,
1265 VOP3_Real<!cast<VOP3_Pseudo>(NAME), SIEncodingFamily.GFX10>,
1270 VOP3_Real<!cast<VOP3_Pseudo>(NAME#"_e64"), SIEncodingFamily.GFX10>,
1276 VOP3_Real<!cast<VOP3_Pseudo>(opName#"_e64"), SIEncodingFamily.GFX10>,
[all …]
H A DAMDGPURemoveIncompatibleFunctions.cpp178 if (ST->getGeneration() < AMDGPUSubtarget::GFX10 && in checkFunction()
H A DAMDGPUSubtarget.h41 GFX10 = 9, enumerator
H A DVOP2Instructions.td1143 // on GFX8 and GFX9 and preserve high 16 bits on GFX10+
1742 // GFX10.
1745 let AssemblerPredicate = isGFX10Only, DecoderNamespace = "GFX10" in {
1749 VOP2_Real<!cast<VOP2_Pseudo>(NAME), SIEncodingFamily.GFX10>,
1755 VOP2_Real<!cast<VOP2_Pseudo>(opName), SIEncodingFamily.GFX10>,
1763 VOP2_Real<!cast<VOP2_Pseudo>(NAME#"_e32"), SIEncodingFamily.GFX10>,
1768 VOP3_Real<!cast<VOP3_Pseudo>(NAME#"_e64"), SIEncodingFamily.GFX10>,
1779 def _dpp_gfx10 : VOP2_DPP16<op, !cast<VOP2_DPP_Pseudo>(NAME#"_dpp"), SIEncodingFamily.GFX10>;
1790 VOP2_Real<!cast<VOP2_Pseudo>(opName#"_e32"), SIEncodingFamily.GFX10>,
1799 VOP3_Real<!cast<VOP3_Pseudo>(opName#"_e64"), SIEncodingFamily.GFX10>,
[all …]
H A DSIInsertHardClauses.cpp106 if (ST->getGeneration() == AMDGPUSubtarget::GFX10) { in getHardClauseType()
H A DVOP1Instructions.td994 // GFX10.
997 let AssemblerPredicate = isGFX10Only, DecoderNamespace = "GFX10" in {
1000 VOP1_Real<!cast<VOP1_Pseudo>(NAME), SIEncodingFamily.GFX10>,
1005 VOP1_Real<!cast<VOP1_Pseudo>(NAME#"_e32"), SIEncodingFamily.GFX10>,
1010 VOP3_Real<!cast<VOP3_Pseudo>(NAME#"_e64"), SIEncodingFamily.GFX10>,
1021 … def _dpp_gfx10 : VOP1_DPP16<op{7-0}, !cast<VOP1_DPP_Pseudo>(NAME#"_dpp"), SIEncodingFamily.GFX10>;
1027 } // End AssemblerPredicate = isGFX10Only, DecoderNamespace = "GFX10"
1077 // GFX7, GFX10, GFX11, GFX12
1109 // GFX6, GFX7, GFX10, GFX11, GFX12
H A DDSInstructions.td1186 // Base ENC_DS for GFX6, GFX7, GFX10, GFX11, GFX12.
1325 // GFX10.
1328 let AssemblerPredicate = isGFX10Only, DecoderNamespace = "GFX10" in {
1331 !cast<DS_Pseudo>(NAME), SIEncodingFamily.GFX10>;
1333 } // End AssemblerPredicate = isGFX10Only, DecoderNamespace = "GFX10"
1348 // GFX10, GFX11, GFX12.
1363 // GFX7, GFX10, GFX11, GFX12.
1392 // GFX6, GFX7, GFX10, GFX11.
H A DGCNProcessors.td213 // GCN GFX10.
H A DAMDGPUSearchableTables.td130 // Buffer formats with equal component sizes (GFX10 and later)
165 // Buffer formats with equal component sizes (GFX10 only)
H A DMIMGInstructions.td557 !if(enableDisasm, "GFX10", "")>;
631 !if(enableDisasm, "GFX10", "")>;
784 !if(enableDisasm, "GFX10", "")>;
837 !if(enableDisasm, "GFX10", "")>;
923 !if(enableDisasm, "GFX10", "")> {
936 !if(enableDisasm, "GFX10", "")> {
1371 !if(!and(enableDisasm, addr.Disassemble), "GFX10", "")>;
1386 !if(!and(enableDisasm, addr.Disassemble), "GFX10", "")>;
1536 : MIMG_gfx10<op.GFX10M, (outs VReg_128:$vdata), "GFX10"> {
1544 : MIMG_nsa_gfx10<op.GFX10M, (outs VReg_128:$vdata), num_addrs, "GFX10"> {
H A DAMDGPUSubtarget.cpp216 if (getGeneration() < GFX10) in getConstantBusLimit()
702 if (getGeneration() >= AMDGPUSubtarget::GFX10) in getBaseReservedNumSGPRs()
H A DSIInstrInfo.td28 int GFX10 = 6;
49 def GFX10Gen : GFXGen<isGFX10Only, "GFX10", "_gfx10", SIEncodingFamily.GFX10>;
2664 // FIXME-GFX10: WIP.
2681 // FIXME-GFX10: WIP.
2692 let AssemblerPredicate = isGFX10Only, DecoderNamespace = "GFX10" in {
2693 def _gfx10 : VINTRP_Real_si<op, NAME, outs, ins, asm, SIEncodingFamily.GFX10>;
2694 } // End AssemblerPredicate = isGFX10Only, DecoderNamespace = "GFX10"
2788 [!cast<string>(SIEncodingFamily.GFX10)],
H A DVOPCInstructions.td1793 // GFX10.
1796 let AssemblerPredicate = isGFX10Only, DecoderNamespace = "GFX10" in {
1799 VOPC_Real<!cast<VOPC_Pseudo>(NAME#"_e32"), SIEncodingFamily.GFX10>,
1802 VOP3_Real<!cast<VOP3_Pseudo>(NAME#"_e64"), SIEncodingFamily.GFX10>,
1820 VOPC_Real<!cast<VOPC_Pseudo>(NAME#"_nosdst_e32"), SIEncodingFamily.GFX10>,
1827 VOP3_Real<!cast<VOP3_Pseudo>(NAME#"_nosdst_e64"), SIEncodingFamily.GFX10>,
1844 } // End AssemblerPredicate = isGFX10Only, DecoderNamespace = "GFX10"
1906 // GFX6, GFX7, GFX10.
H A DBUFInstructions.td2326 // Base ENC_MUBUF for GFX6, GFX7, GFX10, GFX11.
2370 def _gfx10 : Base_MUBUF_Real_gfx6_gfx7_gfx10<op{6-0}, ps, SIEncodingFamily.GFX10, asmName> {
2374 let DecoderNamespace = "GFX10";
2695 // MUBUF - GFX10.
2760 // MUBUF - GFX6, GFX7, GFX10.
2888 // Base ENC_MTBUF for GFX6, GFX7, GFX10, GFX11.
2969 // MTBUF - GFX10.
2974 def _gfx10 : Base_MTBUF_Real_gfx6_gfx7_gfx10<op{2-0}, ps, SIEncodingFamily.GFX10> {
2979 let DecoderNamespace = "GFX10";
3000 // MTBUF - GFX6, GFX7, GFX10.
H A DSIDefines.h42 GFX10 = 6, enumerator
H A DSOPInstructions.td2123 // SOP1 - GFX10.
2155 // SOP1 - GFX6, GFX7, GFX10, GFX11.
2346 // SOP2 - GFX10.
2477 // SOPK - GFX10.
2681 // SOPP - GFX6, GFX7, GFX8, GFX9, GFX10
2853 // SOPC - GFX6, GFX7, GFX8, GFX9, GFX10
H A DSMInstructions.td1152 // GFX10.
1170 : SMEM_Real_10Plus_common<op, ps, ps.Mnemonic, SIEncodingFamily.GFX10,
1173 let DecoderNamespace = "GFX10";
H A DFLATInstructions.td753 // GFX7-, GFX10-only flat instructions.
789 // GFX7-, GFX10-, GFX11-only flat instructions.
2096 // GFX10.
2100 FLAT_Real<op, ps, opName>, SIMCInstr<ps.PseudoInstr, SIEncodingFamily.GFX10> {
2102 let DecoderNamespace = "GFX10";
H A DVOP3PInstructions.td1805 // GFX10.
1808 let AssemblerPredicate = isGFX10Only, DecoderNamespace = "GFX10", VOP3P = 1 in {
1810 def _gfx10 : VOP3P_Real<!cast<VOP3P_Pseudo>(NAME), SIEncodingFamily.GFX10>,
1813 } // End AssemblerPredicate = isGFX10Only, DecoderNamespace = "GFX10", VOP3P = 1
H A DSIShrinkInstructions.cpp912 ST->getGeneration() >= AMDGPUSubtarget::GFX10 && in runOnMachineFunction()
H A DSIInstrInfo.cpp5215 ST.getGeneration() >= AMDGPUSubtarget::GFX10) { in verifyInstruction()
5221 ST.getGeneration() >= AMDGPUSubtarget::GFX10) { in verifyInstruction()
5227 ST.getGeneration() < AMDGPUSubtarget::GFX10) { in verifyInstruction()
8572 if (ST.getGeneration() >= AMDGPUSubtarget::GFX10) { in getDefaultRsrcDataFormat()
9196 case AMDGPUSubtarget::GFX10: in subtargetEncodingFamily()
9197 return SIEncodingFamily::GFX10; in subtargetEncodingFamily()
9249 case AMDGPUSubtarget::GFX10: in pseudoToMCOpcode()
/freebsd/contrib/llvm-project/clang/include/clang/Basic/
H A DBuiltinsAMDGPU.def281 // GFX10+ only builtins.

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