1 //===-- AArch64BaseInfo.cpp - AArch64 Base encoding information------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file provides basic encoding and assembly information for AArch64.
10 //
11 //===----------------------------------------------------------------------===//
12 #include "AArch64BaseInfo.h"
13 #include "llvm/ADT/SmallVector.h"
14 #include "llvm/ADT/StringExtras.h"
15 #include "llvm/Support/Regex.h"
16
17 using namespace llvm;
18
19 namespace llvm {
20 namespace AArch64AT {
21 #define GET_ATsList_IMPL
22 #include "AArch64GenSystemOperands.inc"
23 }
24 }
25
26
27 namespace llvm {
28 namespace AArch64DBnXS {
29 #define GET_DBnXSsList_IMPL
30 #include "AArch64GenSystemOperands.inc"
31 }
32 }
33
34 namespace llvm {
35 namespace AArch64DB {
36 #define GET_DBsList_IMPL
37 #include "AArch64GenSystemOperands.inc"
38 }
39 }
40
41 namespace llvm {
42 namespace AArch64DC {
43 #define GET_DCsList_IMPL
44 #include "AArch64GenSystemOperands.inc"
45 }
46 }
47
48 namespace llvm {
49 namespace AArch64IC {
50 #define GET_ICsList_IMPL
51 #include "AArch64GenSystemOperands.inc"
52 }
53 }
54
55 namespace llvm {
56 namespace AArch64ISB {
57 #define GET_ISBsList_IMPL
58 #include "AArch64GenSystemOperands.inc"
59 }
60 }
61
62 namespace llvm {
63 namespace AArch64TSB {
64 #define GET_TSBsList_IMPL
65 #include "AArch64GenSystemOperands.inc"
66 }
67 }
68
69 namespace llvm {
70 namespace AArch64PRFM {
71 #define GET_PRFMsList_IMPL
72 #include "AArch64GenSystemOperands.inc"
73 }
74 }
75
76 namespace llvm {
77 namespace AArch64SVEPRFM {
78 #define GET_SVEPRFMsList_IMPL
79 #include "AArch64GenSystemOperands.inc"
80 }
81 }
82
83 namespace llvm {
84 namespace AArch64RPRFM {
85 #define GET_RPRFMsList_IMPL
86 #include "AArch64GenSystemOperands.inc"
87 } // namespace AArch64RPRFM
88 } // namespace llvm
89
90 namespace llvm {
91 namespace AArch64SVEPredPattern {
92 #define GET_SVEPREDPATsList_IMPL
93 #include "AArch64GenSystemOperands.inc"
94 }
95 }
96
97 namespace llvm {
98 namespace AArch64SVEVecLenSpecifier {
99 #define GET_SVEVECLENSPECIFIERsList_IMPL
100 #include "AArch64GenSystemOperands.inc"
101 } // namespace AArch64SVEVecLenSpecifier
102 } // namespace llvm
103
104 namespace llvm {
105 namespace AArch64ExactFPImm {
106 #define GET_ExactFPImmsList_IMPL
107 #include "AArch64GenSystemOperands.inc"
108 }
109 }
110
111 namespace llvm {
112 namespace AArch64PState {
113 #define GET_PStateImm0_15sList_IMPL
114 #include "AArch64GenSystemOperands.inc"
115 #define GET_PStateImm0_1sList_IMPL
116 #include "AArch64GenSystemOperands.inc"
117 }
118 }
119
120 namespace llvm {
121 namespace AArch64PSBHint {
122 #define GET_PSBsList_IMPL
123 #include "AArch64GenSystemOperands.inc"
124 }
125 }
126
127 namespace llvm {
128 namespace AArch64PHint {
129 #define GET_PHintsList_IMPL
130 #include "AArch64GenSystemOperands.inc"
131 } // namespace AArch64PHint
132 } // namespace llvm
133
134 namespace llvm {
135 namespace AArch64BTIHint {
136 #define GET_BTIsList_IMPL
137 #include "AArch64GenSystemOperands.inc"
138 }
139 }
140
141 namespace llvm {
142 namespace AArch64SysReg {
143 #define GET_SysRegsList_IMPL
144 #include "AArch64GenSystemOperands.inc"
145 }
146 }
147
parseGenericRegister(StringRef Name)148 uint32_t AArch64SysReg::parseGenericRegister(StringRef Name) {
149 // Try to parse an S<op0>_<op1>_<Cn>_<Cm>_<op2> register name
150 static const Regex GenericRegPattern("^S([0-3])_([0-7])_C([0-9]|1[0-5])_C([0-9]|1[0-5])_([0-7])$");
151
152 std::string UpperName = Name.upper();
153 SmallVector<StringRef, 5> Ops;
154 if (!GenericRegPattern.match(UpperName, &Ops))
155 return -1;
156
157 uint32_t Op0 = 0, Op1 = 0, CRn = 0, CRm = 0, Op2 = 0;
158 uint32_t Bits;
159 Ops[1].getAsInteger(10, Op0);
160 Ops[2].getAsInteger(10, Op1);
161 Ops[3].getAsInteger(10, CRn);
162 Ops[4].getAsInteger(10, CRm);
163 Ops[5].getAsInteger(10, Op2);
164 Bits = (Op0 << 14) | (Op1 << 11) | (CRn << 7) | (CRm << 3) | Op2;
165
166 return Bits;
167 }
168
genericRegisterString(uint32_t Bits)169 std::string AArch64SysReg::genericRegisterString(uint32_t Bits) {
170 assert(Bits < 0x10000);
171 uint32_t Op0 = (Bits >> 14) & 0x3;
172 uint32_t Op1 = (Bits >> 11) & 0x7;
173 uint32_t CRn = (Bits >> 7) & 0xf;
174 uint32_t CRm = (Bits >> 3) & 0xf;
175 uint32_t Op2 = Bits & 0x7;
176
177 return "S" + utostr(Op0) + "_" + utostr(Op1) + "_C" + utostr(CRn) + "_C" +
178 utostr(CRm) + "_" + utostr(Op2);
179 }
180
181 namespace llvm {
182 namespace AArch64TLBI {
183 #define GET_TLBITable_IMPL
184 #include "AArch64GenSystemOperands.inc"
185 }
186 }
187
188 namespace llvm {
189 namespace AArch64SVCR {
190 #define GET_SVCRsList_IMPL
191 #include "AArch64GenSystemOperands.inc"
192 }
193 }
194