Home
last modified time | relevance | path

Searched refs:GCNSubtarget (Results 1 – 25 of 109) sorted by relevance

12345

/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DGCNSubtarget.cpp37 #define AMDGPUSubtarget GCNSubtarget
55 GCNSubtarget::~GCNSubtarget() = default;
57 GCNSubtarget &GCNSubtarget::initializeSubtargetDependencies(const Triple &TT, in initializeSubtargetDependencies()
161 void GCNSubtarget::checkSubtargetFeatures(const Function &F) const { in checkSubtargetFeatures()
170 GCNSubtarget::GCNSubtarget(const Triple &TT, StringRef GPU, StringRef FS, in GCNSubtarget() function in GCNSubtarget
196 const SelectionDAGTargetInfo *GCNSubtarget::getSelectionDAGInfo() const { in getSelectionDAGInfo()
200 unsigned GCNSubtarget::getConstantBusLimit(unsigned Opcode) const { in getConstantBusLimit()
228 bool GCNSubtarget::zeroesHigh16BitsOfDest(unsigned Opcode) const { in zeroesHigh16BitsOfDest()
326 void GCNSubtarget::overrideSchedPolicy(MachineSchedPolicy &Policy, in overrideSchedPolicy()
343 void GCNSubtarget::mirFileLoaded(MachineFunction &MF) const { in mirFileLoaded()
[all …]
H A DSIFrameLowering.cpp79 const GCNSubtarget &ST = MF.getSubtarget<GCNSubtarget>(); in getVGPRSpillLaneOrTempRegister()
134 static void buildPrologSpill(const GCNSubtarget &ST, const SIRegisterInfo &TRI, in buildPrologSpill()
157 static void buildEpilogRestore(const GCNSubtarget &ST, in buildEpilogRestore()
228 const GCNSubtarget &ST;
346 ST(MF.getSubtarget<GCNSubtarget>()), MFI(MF.getFrameInfo()), in PrologEpilogSGPRSpillBuilder()
386 const GCNSubtarget &ST = MF.getSubtarget<GCNSubtarget>(); in emitEntryFunctionFlatScratchInit()
443 const GCNSubtarget &Subtarget = MF.getSubtarget<GCNSubtarget>(); in emitEntryFunctionFlatScratchInit()
541 const GCNSubtarget &ST = MF.getSubtarget<GCNSubtarget>(); in getEntryFunctionReservedScratchRsrcReg()
591 static unsigned getScratchScaleFactor(const GCNSubtarget &ST) { in getScratchScaleFactor()
611 const GCNSubtarget &ST = MF.getSubtarget<GCNSubtarget>(); in emitEntryFunctionPrologue()
[all …]
H A DAMDGPUPreLegalizerCombiner.cpp47 const GCNSubtarget &STI;
55 const GCNSubtarget &STI, MachineDominatorTree *MDT,
78 #define AMDGPUSubtarget GCNSubtarget
85 #define AMDGPUSubtarget GCNSubtarget
94 const GCNSubtarget &STI, MachineDominatorTree *MDT, const LegalizerInfo *LI) in AMDGPUPreLegalizerCombinerImpl()
270 const GCNSubtarget &STI = MF.getSubtarget<GCNSubtarget>(); in runOnMachineFunction()
H A DSIProgramInfo.cpp82 const GCNSubtarget &ST) { in getComputePGMRSrc1Reg()
107 CallingConv::ID CC, const GCNSubtarget &ST) { in getPGMRSrc1Reg()
171 const MCExpr *SIProgramInfo::getComputePGMRSrc1(const GCNSubtarget &ST, in getComputePGMRSrc1()
182 const GCNSubtarget &ST, in getPGMRSrc1()
215 const GCNSubtarget &STM = MF.getSubtarget<GCNSubtarget>(); in getFunctionCodeSize()
H A DSIMachineFunctionInfo.cpp32 const GCNTargetMachine &getTM(const GCNSubtarget *STI) { in getTM()
38 const GCNSubtarget *STI) in SIMachineFunctionInfo()
45 const GCNSubtarget &ST = *static_cast<const GCNSubtarget *>(STI); in SIMachineFunctionInfo()
192 const GCNSubtarget& ST = MF.getSubtarget<GCNSubtarget>(); in limitOccupancy()
342 const SIRegisterInfo *TRI = MF.getSubtarget<GCNSubtarget>().getRegisterInfo(); in shiftWwmVGPRsToLowestRange()
397 const GCNSubtarget &ST = MF.getSubtarget<GCNSubtarget>(); in allocatePhysicalVGPRForSGPRSpills()
442 const GCNSubtarget &ST = MF.getSubtarget<GCNSubtarget>(); in allocateSGPRSpillToVGPRLane()
483 const GCNSubtarget &ST = MF.getSubtarget<GCNSubtarget>(); in allocateVGPRSpillToAGPR()
621 const GCNSubtarget &ST = MF.getSubtarget<GCNSubtarget>(); in getGITPtrLoReg()
H A DAMDGPUAttributor.cpp161 const GCNSubtarget &ST = TM.getSubtarget<GCNSubtarget>(F); in hasApertureRegs()
167 const GCNSubtarget &ST = TM.getSubtarget<GCNSubtarget>(F); in supportsGetDoorbellID()
181 const GCNSubtarget &ST = TM.getSubtarget<GCNSubtarget>(F); in getDefaultFlatWorkGroupSize()
187 const GCNSubtarget &ST = TM.getSubtarget<GCNSubtarget>(F); in getMaximumFlatWorkGroupRange()
192 const GCNSubtarget &ST = TM.getSubtarget<GCNSubtarget>(F); in getMaxNumWorkGroups()
205 const GCNSubtarget &ST = TM.getSubtarget<GCNSubtarget>(F); in getWavesPerEU()
216 const GCNSubtarget &ST = TM.getSubtarget<GCNSubtarget>(F); in getWavesPerEUAttr()
226 const GCNSubtarget &ST = TM.getSubtarget<GCNSubtarget>(F); in getEffectiveWavesPerEU()
232 const GCNSubtarget &ST = TM.getSubtarget<GCNSubtarget>(F); in getMaxWavesPerEU()
1319 const GCNSubtarget &ST = TM.getSubtarget<GCNSubtarget>(F); in updateWavesPerEU()
H A DAMDGPUAsmPrinter.cpp163 const GCNSubtarget &STM = MF->getSubtarget<GCNSubtarget>(); in emitFunctionBodyStart()
234 const GCNSubtarget &STM = MF->getSubtarget<GCNSubtarget>(); in emitFunctionBodyEnd()
274 const GCNSubtarget &STM = MF->getSubtarget<GCNSubtarget>(); in emitFunctionEntryLabel()
365 const GCNSubtarget &STM = TM.getSubtarget<GCNSubtarget>(F); in validateMCResourceInfo()
584 if (MF.getSubtarget<GCNSubtarget>().isWave32()) { in getAmdhsaKernelCodeProperties()
607 const GCNSubtarget &STM = MF.getSubtarget<GCNSubtarget>(); in getAmdhsaKernelDescriptor()
662 const GCNSubtarget &STM = MF.getSubtarget<GCNSubtarget>(); in runOnMachineFunction()
749 MF.getSubtarget<GCNSubtarget>().getTargetID().isXnackOnOrAny(), in runOnMachineFunction()
889 const GCNSubtarget &STM = TM.getSubtarget<GCNSubtarget>(F); in initializeTargetID()
920 const GCNSubtarget &STM = MF.getSubtarget<GCNSubtarget>(); in getSIProgramInfo()
[all …]
H A DSIProgramInfo.h26 class GCNSubtarget; variable
111 const MCExpr *getComputePGMRSrc1(const GCNSubtarget &ST,
113 const MCExpr *getPGMRSrc1(CallingConv::ID CC, const GCNSubtarget &ST,
H A DSILateBranchLowering.cpp33 void expandChainCall(MachineInstr &MI, const GCNSubtarget &ST,
95 const GCNSubtarget &ST = MBB.getParent()->getSubtarget<GCNSubtarget>(); in generateEndPgm()
139 const GCNSubtarget &ST, in expandChainCall()
217 const GCNSubtarget &ST = MF.getSubtarget<GCNSubtarget>(); in run()
H A DGCNVOPDUtils.cpp43 const GCNSubtarget &ST = MF->getSubtarget<GCNSubtarget>(); in checkVOPDRegConstraints()
193 const GCNSubtarget &ST = STII.getSubtarget(); in shouldScheduleVOPDAdjacent()
231 const GCNSubtarget &ST = DAG->MF.getSubtarget<GCNSubtarget>(); in apply()
H A DSIAnnotateControlFlow.cpp65 void initialize(const GCNSubtarget &ST);
100 SIAnnotateControlFlow(Function &F, const GCNSubtarget &ST, DominatorTree &DT, in SIAnnotateControlFlow()
112 void SIAnnotateControlFlow::initialize(const GCNSubtarget &ST) { in initialize()
390 const GCNSubtarget &ST = TM.getSubtarget<GCNSubtarget>(F); in run()
433 const GCNSubtarget &ST = TM.getSubtarget<GCNSubtarget>(F); in runOnFunction()
H A DAMDGPULateCodeGenPrepare.cpp48 const GCNSubtarget &ST;
56 AMDGPULateCodeGenPrepare(Function &F, const GCNSubtarget &ST, in AMDGPULateCodeGenPrepare()
78 const GCNSubtarget &ST;
166 LiveRegOptimizer(Module &Mod, const GCNSubtarget &ST) in LiveRegOptimizer()
521 const GCNSubtarget &ST = TM.getSubtarget<GCNSubtarget>(F); in run()
560 const GCNSubtarget &ST = TM.getSubtarget<GCNSubtarget>(F); in runOnFunction()
H A DAMDGPUCombinerHelper.h25 const GCNSubtarget &STI;
33 const GCNSubtarget &STI);
H A DAMDGPURegBankCombiner.cpp47 const GCNSubtarget &STI;
58 const GCNSubtarget &STI, MachineDominatorTree *MDT,
101 #define AMDGPUSubtarget GCNSubtarget
108 #define AMDGPUSubtarget GCNSubtarget
117 const GCNSubtarget &STI, MachineDominatorTree *MDT, const LegalizerInfo *LI) in AMDGPURegBankCombinerImpl()
472 const GCNSubtarget &ST = MF.getSubtarget<GCNSubtarget>(); in runOnMachineFunction()
H A DAMDGPURegBankLegalizeRules.h21 class GCNSubtarget; variable
291 const GCNSubtarget *ST;
361 RegBankLegalizeRules(const GCNSubtarget &ST, MachineRegisterInfo &MRI);
366 void refreshRefs(const GCNSubtarget &_ST, MachineRegisterInfo &_MRI) { in refreshRefs()
H A DAMDGPURemoveIncompatibleFunctions.cpp96 const SubtargetSubTypeKV *getGPUInfo(const GCNSubtarget &ST, in getGPUInfo()
161 const GCNSubtarget *ST = in checkFunction()
162 static_cast<const GCNSubtarget *>(TM->getSubtargetImpl(F)); in checkFunction()
H A DAMDGPUCallLowering.cpp211 const GCNSubtarget &ST = MIRBuilder.getMF().getSubtarget<GCNSubtarget>(); in getStackAddress()
237 const auto &ST = MF.getSubtarget<GCNSubtarget>(); in assignValueToAddress()
510 const GCNSubtarget *Subtarget = &MF.getSubtarget<GCNSubtarget>(); in lowerFormalArgumentsKernel()
601 const GCNSubtarget &Subtarget = MF.getSubtarget<GCNSubtarget>(); in lowerFormalArguments()
797 const GCNSubtarget &ST = MF.getSubtarget<GCNSubtarget>(); in passSpecialInputs()
1021 const GCNSubtarget &ST = MF.getSubtarget<GCNSubtarget>(); in doCallerAndCalleePassArgsTheSameWay()
1086 const GCNSubtarget &ST = MF.getSubtarget<GCNSubtarget>(); in areCalleeOutgoingArgsTailCallable()
1110 const SIRegisterInfo *TRI = MF.getSubtarget<GCNSubtarget>().getRegisterInfo(); in isEligibleForTailCallOptimization()
1160 const GCNSubtarget &ST, const SIMachineFunctionInfo &FuncInfo, in handleImplicitCallArguments()
1199 const GCNSubtarget &ST = MF.getSubtarget<GCNSubtarget>(); in lowerTailCall()
[all …]
H A DAMDGPUPostLegalizerCombiner.cpp48 const GCNSubtarget &STI;
58 const GCNSubtarget &STI, MachineDominatorTree *MDT,
118 #define AMDGPUSubtarget GCNSubtarget
125 #define AMDGPUSubtarget GCNSubtarget
134 const GCNSubtarget &STI, MachineDominatorTree *MDT, const LegalizerInfo *LI) in AMDGPUPostLegalizerCombinerImpl()
488 const GCNSubtarget &ST = MF.getSubtarget<GCNSubtarget>(); in runOnMachineFunction()
H A DSIFixVGPRCopies.cpp69 const GCNSubtarget &ST = MF.getSubtarget<GCNSubtarget>(); in run()
H A DAMDGPUInstructionSelector.h22 #define AMDGPUSubtarget GCNSubtarget
38 class GCNSubtarget; variable
51 const GCNSubtarget *Subtarget;
54 AMDGPUInstructionSelector(const GCNSubtarget &STI,
418 const GCNSubtarget &STI;
420 #define AMDGPUSubtarget GCNSubtarget
H A DSIPeepholeSDWA.cpp41 bool isConvertibleToSDWA(MachineInstr &MI, const GCNSubtarget &ST,
64 const GCNSubtarget &ST) const;
65 void convertVcndmaskToVOP2(MachineInstr &MI, const GCNSubtarget &ST) const;
68 void legalizeScalarOperands(MachineInstr &MI, const GCNSubtarget &ST) const;
112 const GCNSubtarget &ST,
145 const GCNSubtarget &ST,
175 const GCNSubtarget &ST,
387 const GCNSubtarget &ST, in potentialToConvert()
566 const GCNSubtarget &ST, in potentialToConvert()
1031 const GCNSubtarget &ST) const { in pseudoOpConvertToVOP2()
[all …]
H A DAMDGPUTargetMachine.cpp582 const GCNSubtarget &ST = C->MF->getSubtarget<GCNSubtarget>(); in createGCNMaxOccupancyMachineScheduler()
604 const GCNSubtarget &ST = C->MF->getSubtarget<GCNSubtarget>(); in createGCNMaxMemoryClauseMachineScheduler()
616 const GCNSubtarget &ST = C->MF->getSubtarget<GCNSubtarget>(); in createIterativeGCNMaxOccupancyMachineScheduler()
635 const GCNSubtarget &ST = C->MF->getSubtarget<GCNSubtarget>(); in createIterativeILPMachineScheduler()
753 const GCNSubtarget &ST = C->MF->getSubtarget<GCNSubtarget>(); in createMachineScheduler()
1095 I = std::make_unique<GCNSubtarget>(TargetTriple, GPU, FS, *this); in getSubtargetImpl()
1118 const GCNSubtarget &ST = C->MF->getSubtarget<GCNSubtarget>(); in createMachineScheduler()
1151 const GCNSubtarget &ST = C->MF->getSubtarget<GCNSubtarget>(); in createPostMachineScheduler()
1775 Allocator, F, static_cast<const GCNSubtarget *>(STI)); in createMachineFunctionInfo()
1786 *MFI, *MF.getSubtarget<GCNSubtarget>().getRegisterInfo(), MF); in convertFuncInfoToYAML()
[all …]
H A DAMDGPURegisterBankInfo.h27 class GCNSubtarget; variable
44 const GCNSubtarget &Subtarget;
166 AMDGPURegisterBankInfo(const GCNSubtarget &STI);
H A DAMDGPUPreloadKernelArguments.cpp60 const GCNSubtarget &ST;
165 PreloadKernelArgInfo(Function &F, const GCNSubtarget &ST) : F(F), ST(ST) { in PreloadKernelArgInfo()
281 const GCNSubtarget &ST = TM.getSubtarget<GCNSubtarget>(F); in markKernelArgsAsInreg()
H A DSILowerSGPRSpills.cpp120 const GCNSubtarget &ST = MF.getSubtarget<GCNSubtarget>(); in insertCSRSaves()
248 const GCNSubtarget &ST = MF.getSubtarget<GCNSubtarget>(); in spillCalleeSavedRegs()
394 const GCNSubtarget &ST = MF.getSubtarget<GCNSubtarget>(); in run()

12345