| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | LegalizeDAG.cpp | 65 EVT FloatVT; member
1635 EVT FloatVT = Value.getValueType(); in getSignAsIntValue() local
1636 unsigned NumBits = FloatVT.getScalarSizeInBits(); in getSignAsIntValue()
1637 State.FloatVT = FloatVT; in getSignAsIntValue()
1651 SDValue StackPtr = DAG.CreateStackTemporary(FloatVT, LoadTy); in getSignAsIntValue()
1662 assert(FloatVT.isByteSized() && "Unsupported floating point type!"); in getSignAsIntValue()
1688 return DAG.getNode(ISD::BITCAST, DL, State.FloatVT, NewIntValue); in modifySignAsInt()
1693 return DAG.getLoad(State.FloatVT, DL, Chain, State.FloatPtr, in modifySignAsInt()
1713 EVT FloatVT = Mag.getValueType(); in ExpandFCOPYSIGN() local
1714 if (TLI.isOperationLegalOrCustom(ISD::FABS, FloatVT) && in ExpandFCOPYSIGN()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64InstrFormats.td | 764 class fixedpoint_i32<ValueType FloatVT>
765 : Operand<FloatVT>,
766 ComplexPattern<FloatVT, 1, "SelectCVTFixedPosOperand<32>", [fpimm, ld]> {
772 class fixedpoint_i64<ValueType FloatVT>
773 : Operand<FloatVT>,
774 ComplexPattern<FloatVT, 1, "SelectCVTFixedPosOperand<64>", [fpimm, ld]> {
788 class fixedpoint_recip_i32<ValueType FloatVT>
789 : Operand<FloatVT>,
790 ComplexPattern<FloatVT, 1, "SelectCVTFixedPosRecipOperand<32>", [fpimm, ld]> {
795 class fixedpoint_recip_i64<ValueType FloatVT>
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| /freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/ |
| H A D | RISCVISelLowering.cpp | 972 EVT FloatVT = MVT::getVectorVT(MVT::f32, VT.getVectorElementCount()); in RISCVTargetLowering() local
973 if (isTypeLegal(FloatVT)) { in RISCVTargetLowering()
1396 EVT FloatVT = MVT::getVectorVT(MVT::f32, VT.getVectorElementCount()); in RISCVTargetLowering() local
1397 if (isTypeLegal(FloatVT)) in RISCVTargetLowering()
6380 MVT FloatVT = MVT::getVectorVT(FloatEltVT, VT.getVectorElementCount()); in lowerCTLZ_CTTZ_ZERO_UNDEF() local
6385 assert(DAG.getTargetLoweringInfo().isTypeLegal(FloatVT) && in lowerCTLZ_CTTZ_ZERO_UNDEF()
6401 if (FloatVT.bitsGT(VT)) { in lowerCTLZ_CTTZ_ZERO_UNDEF()
6403 FloatVal = DAG.getNode(ISD::VP_UINT_TO_FP, DL, FloatVT, Src, Mask, VL); in lowerCTLZ_CTTZ_ZERO_UNDEF()
6405 FloatVal = DAG.getNode(ISD::UINT_TO_FP, DL, FloatVT, Src); in lowerCTLZ_CTTZ_ZERO_UNDEF()
6421 FloatVal = convertFromScalableVector(FloatVT, FloatVal, DAG, Subtarget); in lowerCTLZ_CTTZ_ZERO_UNDEF()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/ARM/ |
| H A D | ARMISelLowering.cpp | 15373 EVT FloatVT = EVT::getVectorVT(*DAG.getContext(), MVT::f64, NumElts); in PerformBUILD_VECTORCombine() local
15374 SDValue BV = DAG.getBuildVector(FloatVT, dl, Ops); in PerformBUILD_VECTORCombine()
15576 EVT FloatVT = EVT::getVectorVT(*DAG.getContext(), MVT::f64, in PerformInsertEltCombine() local
15578 SDValue Vec = DAG.getNode(ISD::BITCAST, dl, FloatVT, N->getOperand(0)); in PerformInsertEltCombine()
15583 SDValue InsElt = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, FloatVT, in PerformInsertEltCombine()
16937 EVT FloatVT = EVT::getVectorVT(*DAG.getContext(), MVT::f64, in PerformSTORECombine() local
16939 SDValue Vec = DAG.getNode(ISD::BITCAST, dl, FloatVT, IntVec); in PerformSTORECombine()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86ISelLowering.cpp | 20023 static bool isLegalConversion(MVT VT, MVT FloatVT, bool IsSigned, in isLegalConversion() argument
20025 if (FloatVT.getScalarType() != MVT::f16 || Subtarget.hasVLX()) { in isLegalConversion()
20036 if (VT == MVT::v8i64 && FloatVT == MVT::v8f16 && Subtarget.hasFP16()) in isLegalConversion()
48693 MVT FloatVT = in combinePTESTCC() local
48695 Res = DAG.getBitcast(FloatVT, Res); in combinePTESTCC()
48964 MVT FloatVT = MVT::getVectorVT(FloatSVT, NumElts); in combineSetCCMOVMSK() local
48965 MVT IntVT = FloatVT.changeVectorElementTypeToInteger(); in combineSetCCMOVMSK()
48970 DAG.getBitcast(FloatVT, LHS), in combineSetCCMOVMSK()
48971 DAG.getBitcast(FloatVT, RHS)); in combineSetCCMOVMSK()
58558 MVT FloatVT = VT.changeVectorElementType(MVT::f32); in combineConcatVectorOps() local
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