Searched refs:FlatScratchInitReg (Results 1 – 3 of 3) sorted by relevance
501 Register FlatScratchInitReg = Info.addFlatScratchInit(TRI); in allocateHSAUserSGPRs() local502 MF.addLiveIn(FlatScratchInitReg, &AMDGPU::SGPR_64RegClass); in allocateHSAUserSGPRs()503 CCInfo.AllocateReg(FlatScratchInitReg); in allocateHSAUserSGPRs()615 Register FlatScratchInitReg = Info->addFlatScratchInit(*TRI); in lowerFormalArguments() local616 MF.addLiveIn(FlatScratchInitReg, &AMDGPU::SGPR_64RegClass); in lowerFormalArguments()617 CCInfo.AllocateReg(FlatScratchInitReg); in lowerFormalArguments()
457 Register FlatScratchInitReg = in emitEntryFunctionFlatScratchInit() local459 assert(FlatScratchInitReg); in emitEntryFunctionFlatScratchInit()462 MRI.addLiveIn(FlatScratchInitReg); in emitEntryFunctionFlatScratchInit()463 MBB.addLiveIn(FlatScratchInitReg); in emitEntryFunctionFlatScratchInit()465 FlatScrInitLo = TRI->getSubReg(FlatScratchInitReg, AMDGPU::sub0); in emitEntryFunctionFlatScratchInit()466 FlatScrInitHi = TRI->getSubReg(FlatScratchInitReg, AMDGPU::sub1); in emitEntryFunctionFlatScratchInit()
2485 Register FlatScratchInitReg = Info.addFlatScratchInit(TRI); in allocateHSAUserSGPRs() local2486 MF.addLiveIn(FlatScratchInitReg, &AMDGPU::SGPR_64RegClass); in allocateHSAUserSGPRs()2487 CCInfo.AllocateReg(FlatScratchInitReg); in allocateHSAUserSGPRs()