Searched refs:FlatScratchInitReg (Results 1 – 3 of 3) sorted by relevance
491 Register FlatScratchInitReg = Info.addFlatScratchInit(TRI); in allocateHSAUserSGPRs() local492 MF.addLiveIn(FlatScratchInitReg, &AMDGPU::SGPR_64RegClass); in allocateHSAUserSGPRs()493 CCInfo.AllocateReg(FlatScratchInitReg); in allocateHSAUserSGPRs()617 Register FlatScratchInitReg = Info->addFlatScratchInit(*TRI); in lowerFormalArguments() local618 MF.addLiveIn(FlatScratchInitReg, &AMDGPU::SGPR_64RegClass); in lowerFormalArguments()619 CCInfo.AllocateReg(FlatScratchInitReg); in lowerFormalArguments()
458 Register FlatScratchInitReg = in emitEntryFunctionFlatScratchInit() local460 assert(FlatScratchInitReg); in emitEntryFunctionFlatScratchInit()463 MRI.addLiveIn(FlatScratchInitReg); in emitEntryFunctionFlatScratchInit()464 MBB.addLiveIn(FlatScratchInitReg); in emitEntryFunctionFlatScratchInit()466 FlatScrInitLo = TRI->getSubReg(FlatScratchInitReg, AMDGPU::sub0); in emitEntryFunctionFlatScratchInit()467 FlatScrInitHi = TRI->getSubReg(FlatScratchInitReg, AMDGPU::sub1); in emitEntryFunctionFlatScratchInit()
2582 Register FlatScratchInitReg = Info.addFlatScratchInit(TRI); in allocateHSAUserSGPRs() local2583 MF.addLiveIn(FlatScratchInitReg, &AMDGPU::SGPR_64RegClass); in allocateHSAUserSGPRs()2584 CCInfo.AllocateReg(FlatScratchInitReg); in allocateHSAUserSGPRs()