| /freebsd/contrib/llvm-project/llvm/lib/TargetParser/ |
| H A D | TargetParser.cpp | 27 unsigned Features; member
204 return Entry->Features; in getArchAttrAMDGCN()
210 return Entry->Features; in getArchAttrR600()
316 StringMap<bool> &Features) { in fillAMDGPUFeatureMap() argument
320 Features["atomic-ds-pk-add-16-insts"] = true; in fillAMDGPUFeatureMap()
321 Features["atomic-flat-pk-add-16-insts"] = true; in fillAMDGPUFeatureMap()
322 Features["atomic-buffer-global-pk-add-f16-insts"] = true; in fillAMDGPUFeatureMap()
323 Features["atomic-global-pk-add-bf16-inst"] = true; in fillAMDGPUFeatureMap()
324 Features["atomic-fadd-rtn-insts"] = true; in fillAMDGPUFeatureMap()
325 Features["ci-insts"] = true; in fillAMDGPUFeatureMap()
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| H A D | Host.cpp | 707 #define testFeature(F) (Features[F / 32] & (1 << (F % 32))) != 0
711 const unsigned *Features, in getIntelProcessorTypeAndSubtype() argument
1072 const unsigned *Features, in getAMDProcessorTypeAndSubtype() argument
1245 unsigned *Features) { in getAvailableFeatures() argument
1249 Features[F / 32] |= 1U << (F % 32); in getAvailableFeatures()
1388 unsigned Features[(X86::CPU_FEATURE_MAX + 31) / 32] = {0}; in getHostCPUName() local
1390 getAvailableFeatures(ECX, EDX, MaxLeaf, Features); in getHostCPUName()
1400 CPU = getIntelProcessorTypeAndSubtype(Family, Model, Features, &Type, in getHostCPUName()
1403 CPU = getAMDProcessorTypeAndSubtype(Family, Model, Features, &Type, in getHostCPUName()
1743 StringMap<bool> Features; in getHostCPUFeatures() local
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| H A D | CSKYTargetParser.cpp | 21 std::vector<StringRef> &Features) { in getFPUFeatures() argument
28 Features.push_back("+fpuv2_sf"); in getFPUFeatures()
29 Features.push_back("+fpuv2_df"); in getFPUFeatures()
30 Features.push_back("+fdivdu"); in getFPUFeatures()
33 Features.push_back("+fpuv2_sf"); in getFPUFeatures()
34 Features.push_back("+fpuv2_df"); in getFPUFeatures()
37 Features.push_back("+fpuv2_sf"); in getFPUFeatures()
38 Features.push_back("+fpuv2_df"); in getFPUFeatures()
39 Features.push_back("+fdivdu"); in getFPUFeatures()
42 Features in getFPUFeatures()
171 getExtensionFeatures(uint64_t Extensions,std::vector<StringRef> & Features) getExtensionFeatures() argument
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| H A D | LoongArchTargetParser.cpp | 38 std::vector<StringRef> &Features) { in getArchFeatures() argument
42 if ((A.Features & F.Kind) == F.Kind) in getArchFeatures()
43 Features.push_back(F.Name); in getArchFeatures()
49 Features.push_back("+64bit"); in getArchFeatures()
50 Features.push_back("+d"); in getArchFeatures()
51 Features.push_back("+lsx"); in getArchFeatures()
52 Features.push_back("+ual"); in getArchFeatures()
54 Features.push_back("+frecipe"); in getArchFeatures()
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| H A D | SubtargetFeature.cpp | 41 Features.push_back(hasFlag(String) ? String.lower() in AddFeature()
47 Features.insert(Features.cend(), OtherFeatures.begin(), OtherFeatures.end()); in addFeaturesVector()
52 Split(Features, Initial); in SubtargetFeatures()
56 return join(Features.begin(), Features.end(), ","); in getString()
60 for (const auto &F : Features) in print()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | GCNProcessors.td | 24 FeatureISAVersion6_0_0.Features
28 FeatureISAVersion6_0_0.Features
32 FeatureISAVersion6_0_1.Features
36 FeatureISAVersion6_0_1.Features
40 FeatureISAVersion6_0_1.Features
44 FeatureISAVersion6_0_2.Features
48 FeatureISAVersion6_0_2.Features
52 FeatureISAVersion6_0_2.Features
60 FeatureISAVersion7_0_0.Features
64 FeatureISAVersion7_0_0.Features
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| /freebsd/contrib/llvm-project/clang/lib/Driver/ToolChains/Arch/ |
| H A D | RISCV.cpp | 30 std::vector<StringRef> &Features, in getArchFeatures() argument
47 Features.push_back(Args.MakeArgString(Str)); in getArchFeatures()
50 Features.push_back(Args.MakeArgString("+experimental")); in getArchFeatures()
59 std::vector<StringRef> &Features) { in getRISCFeaturesFromMcpu() argument
74 std::vector<StringRef> &Features) { in getRISCVTargetFeatures() argument
77 if (!getArchFeatures(D, MArch, Features, Args)) in getRISCVTargetFeatures()
90 getRISCFeaturesFromMcpu(D, A, Triple, CPU, Features); in getRISCVTargetFeatures()
100 Features.push_back("+reserve-x1"); in getRISCVTargetFeatures()
102 Features.push_back("+reserve-x2"); in getRISCVTargetFeatures()
104 Features.push_back("+reserve-x3"); in getRISCVTargetFeatures()
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| H A D | LoongArch.cpp | 129 std::vector<StringRef> &Features) { in getLoongArchTargetFeatures() argument
133 Features.push_back("+lsx"); in getLoongArchTargetFeatures()
139 llvm::LoongArch::getArchFeatures(ArchName, Features); in getLoongArchTargetFeatures()
148 Features.push_back("+f"); in getLoongArchTargetFeatures()
149 Features.push_back("+d"); in getLoongArchTargetFeatures()
151 Features.push_back("+f"); in getLoongArchTargetFeatures()
152 Features.push_back("-d"); in getLoongArchTargetFeatures()
153 Features.push_back("-lsx"); in getLoongArchTargetFeatures()
155 Features.push_back("-f"); in getLoongArchTargetFeatures()
156 Features.push_back("-d"); in getLoongArchTargetFeatures()
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| H A D | AArch64.cpp | 153 std::vector<StringRef> &Features) { in getAArch64MicroArchFeaturesFromMtune() argument
168 Features.push_back("+zcm"); in getAArch64MicroArchFeaturesFromMtune()
169 Features.push_back("+zcz"); in getAArch64MicroArchFeaturesFromMtune()
178 std::vector<StringRef> &Features) { in getAArch64MicroArchFeaturesFromMcpu() argument
186 return getAArch64MicroArchFeaturesFromMtune(D, CPU, Args, Features); in getAArch64MicroArchFeaturesFromMcpu()
192 std::vector<StringRef> &Features, in getAArch64TargetFeatures() argument
224 getAArch64MicroArchFeaturesFromMtune(D, A->getValue(), Args, Features); in getAArch64TargetFeatures()
227 getAArch64MicroArchFeaturesFromMcpu(D, A->getValue(), Args, Features); in getAArch64TargetFeatures()
230 D, getAArch64TargetCPU(Args, Triple, A), Args, Features); in getAArch64TargetFeatures()
257 Extensions.toLLVMFeatureList(Features); in getAArch64TargetFeatures()
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| H A D | M68k.cpp | 69 std::vector<llvm::StringRef> &Features) { in addFloatABIFeatures() argument
74 Features.push_back("-isa-68881"); in addFloatABIFeatures()
75 Features.push_back("-isa-68882"); in addFloatABIFeatures()
84 Features.push_back("+isa-68881"); in addFloatABIFeatures()
90 Features.push_back("+isa-68882"); in addFloatABIFeatures()
95 std::vector<StringRef> &Features) { in getM68kTargetFeatures() argument
96 addFloatABIFeatures(Args, Features); in getM68kTargetFeatures()
100 Features.push_back("+reserve-a0"); in getM68kTargetFeatures()
102 Features.push_back("+reserve-a1"); in getM68kTargetFeatures()
104 Features.push_back("+reserve-a2"); in getM68kTargetFeatures()
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| H A D | X86.cpp | 121 std::vector<StringRef> &Features) { in getX86TargetFeatures() argument
135 Features.push_back( in getX86TargetFeatures()
143 Features.push_back("-rdrnd"); in getX86TargetFeatures()
144 Features.push_back("-aes"); in getX86TargetFeatures()
145 Features.push_back("-pclmul"); in getX86TargetFeatures()
146 Features.push_back("-rtm"); in getX86TargetFeatures()
147 Features.push_back("-fsgsbase"); in getX86TargetFeatures()
154 Features.push_back("+sse4.2"); in getX86TargetFeatures()
155 Features.push_back("+popcnt"); in getX86TargetFeatures()
156 Features.push_back("+cx16"); in getX86TargetFeatures()
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| H A D | Mips.cpp | 187 std::vector<StringRef> &Features) { in getMIPSTargetFeatures() argument
257 Features.push_back("+noabicalls"); in getMIPSTargetFeatures()
259 Features.push_back("-noabicalls"); in getMIPSTargetFeatures()
264 Features.push_back("-long-calls"); in getMIPSTargetFeatures()
266 Features.push_back("+long-calls"); in getMIPSTargetFeatures()
273 Features.push_back("+xgot"); in getMIPSTargetFeatures()
275 Features.push_back("-xgot"); in getMIPSTargetFeatures()
283 Features.push_back("+soft-float"); in getMIPSTargetFeatures()
290 Features.push_back("+nan2008"); in getMIPSTargetFeatures()
293 Features.push_back("-nan2008"); in getMIPSTargetFeatures()
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| H A D | ARM.cpp | 82 std::vector<StringRef> &Features) { in getARMHWDivFeatures() argument
84 if (!llvm::ARM::getHWDivFeatures(HWDivID, Features)) in getARMHWDivFeatures()
91 std::vector<StringRef> &Features) { in getARMFPUFeatures() argument
93 if (!llvm::ARM::getFPUFeatures(FPUKind, Features)) in getARMFPUFeatures()
101 std::vector<StringRef> &Features, in DecodeARMFeatures() argument
107 if (!appendArchExtFeatures(CPU, ArchKind, Feature, Features, ArgFPUKind)) in DecodeARMFeatures()
114 std::vector<StringRef> &Features) { in DecodeARMFeaturesFromCPU() argument
119 llvm::ARM::getExtensionFeatures(Extension, Features); in DecodeARMFeaturesFromCPU()
128 std::vector<StringRef> &Features, in checkARMArchName() argument
137 !DecodeARMFeatures(D, Split.second, CPUName, ArchKind, Features, in checkARMArchName()
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| H A D | SystemZ.cpp | 55 std::vector<llvm::StringRef> &Features) { in getSystemZTargetFeatures() argument
59 Features.push_back("+transactional-execution"); in getSystemZTargetFeatures()
61 Features.push_back("-transactional-execution"); in getSystemZTargetFeatures()
66 Features.push_back("+vector"); in getSystemZTargetFeatures()
68 Features.push_back("-vector"); in getSystemZTargetFeatures()
73 Features.push_back("+soft-float"); in getSystemZTargetFeatures()
78 Features.push_back("+unaligned-symbols"); in getSystemZTargetFeatures()
80 Features.push_back("-unaligned-symbols"); in getSystemZTargetFeatures()
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| H A D | CSKY.cpp | 80 StringRef FPU, std::vector<StringRef> &Features) { in getCSKYFPUFeatures() argument
99 [&Features](ArrayRef<const char *> FPUFeatures) { in getCSKYFPUFeatures()
101 auto it = llvm::find(Features, FPUFeature); in getCSKYFPUFeatures()
102 if (it != Features.end()) in getCSKYFPUFeatures()
103 Features.erase(it); in getCSKYFPUFeatures()
110 if (!llvm::CSKY::getFPUFeatures(FPUID, Features)) { in getCSKYFPUFeatures()
120 std::vector<llvm::StringRef> &Features) { in getCSKYTargetFeatures() argument
158 Features.push_back("+hard-float-abi"); in getCSKYTargetFeatures()
159 Features.push_back("+hard-float"); in getCSKYTargetFeatures()
161 Features.push_back("+hard-float"); in getCSKYTargetFeatures()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AVR/MCTargetDesc/ |
| H A D | AVRELFStreamer.cpp | 13 static unsigned getEFlagsForFeatureSet(const FeatureBitset &Features) { in getEFlagsForFeatureSet() argument
17 if (Features[AVR::ELFArchAVR1]) in getEFlagsForFeatureSet()
19 else if (Features[AVR::ELFArchAVR2]) in getEFlagsForFeatureSet()
21 else if (Features[AVR::ELFArchAVR25]) in getEFlagsForFeatureSet()
23 else if (Features[AVR::ELFArchAVR3]) in getEFlagsForFeatureSet()
25 else if (Features[AVR::ELFArchAVR31]) in getEFlagsForFeatureSet()
27 else if (Features[AVR::ELFArchAVR35]) in getEFlagsForFeatureSet()
29 else if (Features[AVR::ELFArchAVR4]) in getEFlagsForFeatureSet()
31 else if (Features[AVR::ELFArchAVR5]) in getEFlagsForFeatureSet()
33 else if (Features[AVR::ELFArchAVR51]) in getEFlagsForFeatureSet()
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| /freebsd/contrib/llvm-project/clang/lib/Basic/Targets/ |
| H A D | PPC.cpp | 33 bool PPCTargetInfo::handleTargetFeatures(std::vector<std::string> &Features, in handleTargetFeatures() argument
36 for (const auto &Feature : Features) { in handleTargetFeatures()
517 llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, StringRef CPU, in initFeatureMap() argument
519 Features["altivec"] = llvm::StringSwitch<bool>(CPU) in initFeatureMap()
534 Features["power9-vector"] = (CPU == "pwr9"); in initFeatureMap()
535 Features["crypto"] = llvm::StringSwitch<bool>(CPU) in initFeatureMap()
540 Features["power8-vector"] = llvm::StringSwitch<bool>(CPU) in initFeatureMap()
545 Features["bpermd"] = llvm::StringSwitch<bool>(CPU) in initFeatureMap()
551 Features["extdiv"] = llvm::StringSwitch<bool>(CPU) in initFeatureMap()
557 Features["direct-move"] = llvm::StringSwitch<bool>(CPU) in initFeatureMap()
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| H A D | WebAssembly.cpp | 112 void WebAssemblyTargetInfo::setSIMDLevel(llvm::StringMap<bool> &Features, in setSIMDLevel() argument
117 Features["relaxed-simd"] = true; in setSIMDLevel()
120 Features["simd128"] = true; in setSIMDLevel()
131 Features["simd128"] = false; in setSIMDLevel()
134 Features["relaxed-simd"] = false; in setSIMDLevel()
139 void WebAssemblyTargetInfo::setFeatureEnabled(llvm::StringMap<bool> &Features, in setFeatureEnabled() argument
143 setSIMDLevel(Features, SIMD128, Enabled); in setFeatureEnabled()
145 setSIMDLevel(Features, RelaxedSIMD, Enabled); in setFeatureEnabled()
147 Features[Name] = Enabled; in setFeatureEnabled()
151 llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, StringRef CPU, in initFeatureMap() argument
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| H A D | RISCV.cpp | 246 llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, StringRef CPU, in initFeatureMap() argument
252 Features["64bit"] = true; in initFeatureMap()
255 Features["32bit"] = true; in initFeatureMap()
273 return TargetInfo::initFeatureMap(Features, Diags, CPU, OverrideFeatures); in initFeatureMap()
291 return TargetInfo::initFeatureMap(Features, Diags, CPU, AllFeatures); in initFeatureMap()
334 bool RISCVTargetInfo::handleTargetFeatures(std::vector<std::string> &Features, in handleTargetFeatures() argument
337 auto ParseResult = llvm::RISCVISAInfo::parseFeatures(XLen, Features); in handleTargetFeatures()
357 llvm::is_contained(Features, "+unaligned-scalar-mem"); in handleTargetFeatures()
359 if (llvm::is_contained(Features, "+experimental")) in handleTargetFeatures()
393 std::vector<std::string> &Features) { in handleFullArchString() argument
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| H A D | SystemZ.h | 149 initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, in initFeatureMap() argument
154 Features["transactional-execution"] = true; in initFeatureMap()
156 Features["vector"] = true; in initFeatureMap()
158 Features["vector-enhancements-1"] = true; in initFeatureMap()
160 Features["vector-enhancements-2"] = true; in initFeatureMap()
162 Features["nnp-assist"] = true; in initFeatureMap()
163 return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec); in initFeatureMap()
166 bool handleTargetFeatures(std::vector<std::string> &Features, in handleTargetFeatures() argument
172 for (const auto &Feature : Features) { in handleTargetFeatures()
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| /freebsd/contrib/llvm-project/llvm/lib/Object/ |
| H A D | ELFObjectFile.cpp | 102 SubtargetFeatures Features; in getMIPSFeatures() local
109 Features.AddFeature("mips2"); in getMIPSFeatures()
112 Features.AddFeature("mips3"); in getMIPSFeatures()
115 Features.AddFeature("mips4"); in getMIPSFeatures()
118 Features.AddFeature("mips5"); in getMIPSFeatures()
121 Features.AddFeature("mips32"); in getMIPSFeatures()
124 Features.AddFeature("mips64"); in getMIPSFeatures()
127 Features.AddFeature("mips32r2"); in getMIPSFeatures()
130 Features.AddFeature("mips64r2"); in getMIPSFeatures()
133 Features.AddFeature("mips32r6"); in getMIPSFeatures()
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| /freebsd/contrib/llvm-project/clang/include/clang/Basic/ |
| H A D | BuiltinsRISCV.td | 18 let Features = features;
45 let Features = "zbkx,32bit" in {
48 } // Features = "zbkx,32bit"
50 let Features = "zbkx,64bit" in {
53 } // Features = "zbkx,64bit"
66 let Features = "zknd,32bit" in {
69 } // Features = "zknd,32bit"
71 let Features = "zknd,64bit" in {
75 } // Features = "zknd,64bit"
80 let Features = "zknd|zkne,64bit" in {
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| /freebsd/contrib/llvm-project/clang/lib/Basic/ |
| H A D | TargetID.cpp | 28 auto Features = T.isAMDGCN() ? llvm::AMDGPU::getArchAttrAMDGCN(ProcKind) in getAllPossibleAMDGPUTargetIDFeatures() local
30 if (Features & llvm::AMDGPU::FEATURE_SRAMECC) in getAllPossibleAMDGPUTargetIDFeatures()
32 if (Features & llvm::AMDGPU::FEATURE_XNACK) in getAllPossibleAMDGPUTargetIDFeatures()
79 auto Features = Split.second; in parseTargetIDWithFormatCheckingOnly() local
80 if (Features.empty()) in parseTargetIDWithFormatCheckingOnly()
87 while (!Features.empty()) { in parseTargetIDWithFormatCheckingOnly()
88 auto Splits = Features.split(':'); in parseTargetIDWithFormatCheckingOnly()
99 Features = Splits.second; in parseTargetIDWithFormatCheckingOnly()
131 const llvm::StringMap<bool> &Features) { in getCanonicalTargetID() argument
134 for (const auto &F : Features) in getCanonicalTargetID()
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| /freebsd/contrib/llvm-project/clang/lib/Lex/ |
| H A D | LiteralSupport.cpp | 80 static CharSourceRange MakeCharSourceRange(const LangOptions &Features, in MakeCharSourceRange() argument
87 TokLoc.getManager(), Features); in MakeCharSourceRange()
90 TokLoc.getManager(), Features); in MakeCharSourceRange()
100 const LangOptions &Features, FullSourceLoc TokLoc, in Diag() argument
105 TokLoc.getManager(), Features); in Diag()
107 MakeCharSourceRange(Features, TokLoc, TokBegin, TokRangeBegin, TokRangeEnd); in Diag()
135 const LangOptions &Features, in ProcessCharEscape() argument
162 Diag(Diags, Features, Loc, ThisTokBegin, EscapeBegin, ThisTokBuf, in ProcessCharEscape()
168 Diag(Diags, Features, Loc, ThisTokBegin, EscapeBegin, ThisTokBuf, in ProcessCharEscape()
193 Diag(Diags, Features, Loc, ThisTokBegin, EscapeBegin, ThisTokBuf, in ProcessCharEscape()
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| /freebsd/contrib/llvm-project/llvm/include/llvm/TargetParser/ |
| H A D | AArch64TargetParser.h | 73 StringRef Features; // List of SubtargetFeatures to enable. member
75 FMVInfo(StringRef Name, CPUFeatures Bit, StringRef Features, in FMVInfo()
77 : Name(Name), Bit(Bit), Features(Features), Priority(Priority){}; in FMVInfo()
81 Features.split(Feats, ',', -1, false); // discard empty strings in getImpliedFeatures()
215 void reconstructFromParsedFeatures(const std::vector<std::string> &Features,
220 template <typename T> void toLLVMFeatureList(std::vector<T> &Features) const { in toLLVMFeatureList()
222 Features.emplace_back(T(BaseArch->ArchFeature)); in toLLVMFeatureList()
228 Features.emplace_back(T(E.PosTargetFeature)); in toLLVMFeatureList()
230 Features.emplace_back(T(E.NegTargetFeature)); in toLLVMFeatureList()
250 std::vector<StringRef> &Features);
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