Home
last modified time | relevance | path

Searched refs:FalseReg (Results 1 – 20 of 20) sorted by relevance

/freebsd/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86CmovConversion.cpp732 Register FalseReg = in convertCmovInstsToBranches() local
736 auto FRIt = FalseBBRegRewriteTable.find(FalseReg); in convertCmovInstsToBranches()
739 FalseReg = FRIt->second; in convertCmovInstsToBranches()
741 FalseBBRegRewriteTable[MI.getOperand(0).getReg()] = FalseReg; in convertCmovInstsToBranches()
H A DX86InstrInfo.h418 Register FalseReg) const override;
H A DX86InstrInfo.cpp4100 Register FalseReg, int &CondCycles, in canInsertSelect() argument
4114 RI.getCommonSubClass(MRI.getRegClass(TrueReg), MRI.getRegClass(FalseReg)); in canInsertSelect()
4138 Register FalseReg) const { in insertSelect()
4147 .addReg(FalseReg) in insertSelect()
/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVVectorPeephole.cpp179 Register FalseReg = MI.getOperand(2).getReg(); in convertVMergeToVMv() local
182 TRI->lookThruCopyLike(FalseReg, MRI)) in convertVMergeToVMv()
H A DRISCVInstrInfo.cpp1415 MachineOperand FalseReg = MI.getOperand(Invert ? 5 : 4); in optimizeSelect() local
1417 const TargetRegisterClass *PreviousClass = MRI.getRegClass(FalseReg.getReg()); in optimizeSelect()
1439 NewMI.add(FalseReg); in optimizeSelect()
/freebsd/contrib/llvm-project/llvm/lib/Target/Lanai/
H A DLanaiInstrInfo.cpp505 MachineOperand FalseReg = MI.getOperand(Invert ? 1 : 2); in optimizeSelect() local
507 const TargetRegisterClass *PreviousClass = MRI.getRegClass(FalseReg.getReg()); in optimizeSelect()
531 FalseReg.setImplicit(); in optimizeSelect()
532 NewMI.add(FalseReg); in optimizeSelect()
/freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCInstrInfo.cpp1523 Register FalseReg, int &CondCycles, in canInsertSelect() argument
1544 RI.getCommonSubClass(MRI.getRegClass(TrueReg), MRI.getRegClass(FalseReg)); in canInsertSelect()
1570 Register FalseReg) const { in insertSelect()
1577 RI.getCommonSubClass(MRI.getRegClass(TrueReg), MRI.getRegClass(FalseReg)); in insertSelect()
1629 Register FirstReg = SwapOps ? FalseReg : TrueReg, in insertSelect()
1630 SecondReg = SwapOps ? TrueReg : FalseReg; in insertSelect()
3254 unsigned TrueReg, unsigned FalseReg, in selectReg() argument
3261 return Imm1 < Imm2 ? TrueReg : FalseReg; in selectReg()
3263 return Imm1 > Imm2 ? TrueReg : FalseReg; in selectReg()
3265 return Imm1 == Imm2 ? TrueReg : FalseReg; in selectReg()
[all …]
H A DPPCInstrInfo.h453 Register FalseReg) const override;
/freebsd/contrib/llvm-project/llvm/lib/Target/WebAssembly/
H A DWebAssemblyFastISel.cpp925 Register FalseReg = getRegForValue(Select->getFalseValue()); in selectSelect() local
926 if (FalseReg == 0) in selectSelect()
930 std::swap(TrueReg, FalseReg); in selectSelect()
973 .addReg(FalseReg) in selectSelect()
H A DWebAssemblyISelLowering.cpp503 unsigned Tmp0, Tmp1, CmpReg, EqzReg, FalseReg, TrueReg; in LowerFPToInt() local
508 FalseReg = MRI.createVirtualRegister(MRI.getRegClass(OutReg)); in LowerFPToInt()
541 BuildMI(FalseMBB, DL, TII.get(LoweredOpcode), FalseReg).addReg(InReg); in LowerFPToInt()
545 .addReg(FalseReg) in LowerFPToInt()
/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMInstructionSelector.cpp790 auto FalseReg = MIB.getReg(3); in selectSelect() local
792 validOpRegPair(MRI, TrueReg, FalseReg, 32, ARM::GPRRegBankID) && in selectSelect()
797 .addUse(FalseReg) in selectSelect()
H A DARMBaseInstrInfo.cpp2355 MachineOperand FalseReg = MI.getOperand(Invert ? 2 : 1); in optimizeSelect() local
2358 const TargetRegisterClass *FalseClass = MRI.getRegClass(FalseReg.getReg()); in optimizeSelect()
2391 FalseReg.setImplicit(); in optimizeSelect()
2392 NewMI.add(FalseReg); in optimizeSelect()
/freebsd/contrib/llvm-project/llvm/lib/Target/SystemZ/
H A DSystemZInstrInfo.h256 Register FalseReg) const override;
H A DSystemZInstrInfo.cpp553 Register FalseReg, int &CondCycles, in canInsertSelect() argument
565 RI.getCommonSubClass(MRI.getRegClass(TrueReg), MRI.getRegClass(FalseReg)); in canInsertSelect()
589 Register FalseReg) const { in insertSelect()
609 BuildMI(MBB, I, DL, get(TargetOpcode::COPY), FReg).addReg(FalseReg); in insertSelect()
611 FalseReg = FReg; in insertSelect()
622 .addReg(FalseReg).addReg(TrueReg) in insertSelect()
H A DSystemZISelLowering.cpp8257 Register FalseReg = MI->getOperand(2).getReg(); in createPHIsForSelects() local
8263 std::swap(TrueReg, FalseReg); in createPHIsForSelects()
8268 if (RegRewriteTable.contains(FalseReg)) in createPHIsForSelects()
8269 FalseReg = RegRewriteTable[FalseReg].second; in createPHIsForSelects()
8274 .addReg(FalseReg).addMBB(FalseMBB); in createPHIsForSelects()
8277 RegRewriteTable[DestReg] = std::make_pair(TrueReg, FalseReg); in createPHIsForSelects()
/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DSIInstrInfo.h367 Register TrueReg, Register FalseReg, int &CondCycles,
373 Register TrueReg, Register FalseReg) const override;
378 Register TrueReg, Register FalseReg) const;
H A DSIInstrInfo.cpp1231 Register FalseReg) const { in insertVectorSelect()
1244 .addReg(FalseReg) in insertVectorSelect()
1259 .addReg(FalseReg) in insertVectorSelect()
1273 .addReg(FalseReg) in insertVectorSelect()
1287 .addReg(FalseReg) in insertVectorSelect()
1303 .addReg(FalseReg) in insertVectorSelect()
1319 .addReg(FalseReg) in insertVectorSelect()
1337 .addReg(FalseReg) in insertVectorSelect()
3224 Register FalseReg, int &CondCycles, in canInsertSelect() argument
3231 if (MRI.getRegClass(FalseReg) != RC) in canInsertSelect()
[all …]
/freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DTargetInstrInfo.h936 Register TrueReg, Register FalseReg, in canInsertSelect() argument
960 Register TrueReg, Register FalseReg) const { in insertSelect() argument
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64InstrInfo.h405 Register FalseReg) const override;
H A DAArch64InstrInfo.cpp705 Register FalseReg, int &CondCycles, in canInsertSelect() argument
711 RI.getCommonSubClass(MRI.getRegClass(TrueReg), MRI.getRegClass(FalseReg)); in canInsertSelect()
733 else if (canFoldIntoCSel(MRI, FalseReg)) in canInsertSelect()
755 Register TrueReg, Register FalseReg) const { in insertSelect()
863 TrueReg = FalseReg; in insertSelect()
865 FoldedOpc = canFoldIntoCSel(MRI, FalseReg, &NewVReg); in insertSelect()
869 FalseReg = NewVReg; in insertSelect()
878 MRI.constrainRegClass(FalseReg, RC); in insertSelect()
883 .addReg(FalseReg) in insertSelect()