xref: /freebsd/sys/dev/cxgbe/common/t4_regs.h (revision 95ee2897e98f5d444f26ed2334cc7c439f9c16c6)
1 /*-
2  * SPDX-License-Identifier: BSD-2-Clause
3  *
4  * Copyright (c) 2013, 2016 Chelsio Communications, Inc.
5  * All rights reserved.
6  *
7  * Redistribution and use in source and binary forms, with or without
8  * modification, are permitted provided that the following conditions
9  * are met:
10  * 1. Redistributions of source code must retain the above copyright
11  *    notice, this list of conditions and the following disclaimer.
12  * 2. Redistributions in binary form must reproduce the above copyright
13  *    notice, this list of conditions and the following disclaimer in the
14  *    documentation and/or other materials provided with the distribution.
15  *
16  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
17  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
20  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
21  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
22  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
23  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
24  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
26  * SUCH DAMAGE.
27  *
28  */
29 
30 /* This file is automatically generated --- changes will be lost */
31 /* Generation Date : Wed Jan 27 10:57:51 IST 2016 */
32 /* Directory name: t4_reg.txt, Changeset:  */
33 /* Directory name: t5_reg.txt, Changeset: 6936:7f6342b03d61 */
34 /* Directory name: t6_reg.txt, Changeset: 4191:ce3ccd95c109 */
35 
36 #define MYPF_BASE 0x1b000
37 #define MYPF_REG(reg_addr) (MYPF_BASE + (reg_addr))
38 
39 #define PF0_BASE 0x1e000
40 #define PF0_REG(reg_addr) (PF0_BASE + (reg_addr))
41 
42 #define PF1_BASE 0x1e400
43 #define PF1_REG(reg_addr) (PF1_BASE + (reg_addr))
44 
45 #define PF2_BASE 0x1e800
46 #define PF2_REG(reg_addr) (PF2_BASE + (reg_addr))
47 
48 #define PF3_BASE 0x1ec00
49 #define PF3_REG(reg_addr) (PF3_BASE + (reg_addr))
50 
51 #define PF4_BASE 0x1f000
52 #define PF4_REG(reg_addr) (PF4_BASE + (reg_addr))
53 
54 #define PF5_BASE 0x1f400
55 #define PF5_REG(reg_addr) (PF5_BASE + (reg_addr))
56 
57 #define PF6_BASE 0x1f800
58 #define PF6_REG(reg_addr) (PF6_BASE + (reg_addr))
59 
60 #define PF7_BASE 0x1fc00
61 #define PF7_REG(reg_addr) (PF7_BASE + (reg_addr))
62 
63 #define PF_STRIDE 0x400
64 #define PF_BASE(idx) (PF0_BASE + (idx) * PF_STRIDE)
65 #define PF_REG(idx, reg) (PF_BASE(idx) + (reg))
66 
67 #define VF_SGE_BASE 0x0
68 #define VF_SGE_REG(reg_addr) (VF_SGE_BASE + (reg_addr))
69 
70 #define VF_MPS_BASE 0x100
71 #define VF_MPS_REG(reg_addr) (VF_MPS_BASE + (reg_addr))
72 
73 #define VF_PL_BASE 0x200
74 #define VF_PL_REG(reg_addr) (VF_PL_BASE + (reg_addr))
75 
76 #define VF_MBDATA_BASE 0x240
77 #define VF_MBDATA_REG(reg_addr) (VF_MBDATA_BASE + (reg_addr))
78 
79 #define VF_CIM_BASE 0x300
80 #define VF_CIM_REG(reg_addr) (VF_CIM_BASE + (reg_addr))
81 
82 #define MYPORT_BASE 0x1c000
83 #define MYPORT_REG(reg_addr) (MYPORT_BASE + (reg_addr))
84 
85 #define PORT0_BASE 0x20000
86 #define PORT0_REG(reg_addr) (PORT0_BASE + (reg_addr))
87 
88 #define PORT1_BASE 0x22000
89 #define PORT1_REG(reg_addr) (PORT1_BASE + (reg_addr))
90 
91 #define PORT2_BASE 0x24000
92 #define PORT2_REG(reg_addr) (PORT2_BASE + (reg_addr))
93 
94 #define PORT3_BASE 0x26000
95 #define PORT3_REG(reg_addr) (PORT3_BASE + (reg_addr))
96 
97 #define PORT_STRIDE 0x2000
98 #define PORT_BASE(idx) (PORT0_BASE + (idx) * PORT_STRIDE)
99 #define PORT_REG(idx, reg) (PORT_BASE(idx) + (reg))
100 
101 #define SGE_QUEUE_BASE_MAP_HIGH(idx) (A_SGE_QUEUE_BASE_MAP_HIGH + (idx) * 8)
102 #define NUM_SGE_QUEUE_BASE_MAP_HIGH_INSTANCES 136
103 
104 #define SGE_QUEUE_BASE_MAP_LOW(idx) (A_SGE_QUEUE_BASE_MAP_LOW + (idx) * 8)
105 #define NUM_SGE_QUEUE_BASE_MAP_LOW_INSTANCES 136
106 
107 #define PCIE_DMA_REG(reg_addr, idx) ((reg_addr) + (idx) * 8)
108 #define NUM_PCIE_DMA_INSTANCES 4
109 
110 #define PCIE_CMD_REG(reg_addr, idx) ((reg_addr) + (idx) * 8)
111 #define NUM_PCIE_CMD_INSTANCES 2
112 
113 #define PCIE_HMA_REG(reg_addr, idx) ((reg_addr) + (idx) * 8)
114 #define NUM_PCIE_HMA_INSTANCES 1
115 
116 #define PCIE_MEM_ACCESS_REG(reg_addr, idx) ((reg_addr) + (idx) * 8)
117 #define NUM_PCIE_MEM_ACCESS_INSTANCES 8
118 
119 #define PCIE_MAILBOX_REG(reg_addr, idx) ((reg_addr) + (idx) * 8)
120 #define NUM_PCIE_MAILBOX_INSTANCES 1
121 
122 #define PCIE_FW_REG(reg_addr, idx) ((reg_addr) + (idx) * 4)
123 #define NUM_PCIE_FW_INSTANCES 8
124 
125 #define PCIE_FUNC_REG(reg_addr, idx) ((reg_addr) + (idx) * 8)
126 #define NUM_PCIE_FUNC_INSTANCES 256
127 
128 #define PCIE_FID(idx) (A_PCIE_FID + (idx) * 4)
129 #define NUM_PCIE_FID_INSTANCES 2048
130 
131 #define PCIE_DMA_BUF_REG(reg_addr, idx) ((reg_addr) + (idx) * 8)
132 #define NUM_PCIE_DMA_BUF_INSTANCES 4
133 
134 #define MC_DDR3PHYDATX8_REG(reg_addr, idx) ((reg_addr) + (idx) * 256)
135 #define NUM_MC_DDR3PHYDATX8_INSTANCES 9
136 
137 #define MC_BIST_STATUS_REG(reg_addr, idx) ((reg_addr) + (idx) * 4)
138 #define NUM_MC_BIST_STATUS_INSTANCES 18
139 
140 #define EDC_BIST_STATUS_REG(reg_addr, idx) ((reg_addr) + (idx) * 4)
141 #define NUM_EDC_BIST_STATUS_INSTANCES 18
142 
143 #define CIM_PF_MAILBOX_DATA(idx) (A_CIM_PF_MAILBOX_DATA + (idx) * 4)
144 #define NUM_CIM_PF_MAILBOX_DATA_INSTANCES 16
145 
146 #define MPS_TRC_FILTER_MATCH_CTL_A(idx) (A_MPS_TRC_FILTER_MATCH_CTL_A + (idx) * 4)
147 #define NUM_MPS_TRC_FILTER_MATCH_CTL_A_INSTANCES 4
148 
149 #define MPS_TRC_FILTER_MATCH_CTL_B(idx) (A_MPS_TRC_FILTER_MATCH_CTL_B + (idx) * 4)
150 #define NUM_MPS_TRC_FILTER_MATCH_CTL_B_INSTANCES 4
151 
152 #define MPS_TRC_FILTER_RUNT_CTL(idx) (A_MPS_TRC_FILTER_RUNT_CTL + (idx) * 4)
153 #define NUM_MPS_TRC_FILTER_RUNT_CTL_INSTANCES 4
154 
155 #define MPS_TRC_FILTER_DROP(idx) (A_MPS_TRC_FILTER_DROP + (idx) * 4)
156 #define NUM_MPS_TRC_FILTER_DROP_INSTANCES 4
157 
158 #define MPS_TRC_FILTER0_MATCH(idx) (A_MPS_TRC_FILTER0_MATCH + (idx) * 4)
159 #define NUM_MPS_TRC_FILTER0_MATCH_INSTANCES 28
160 
161 #define MPS_TRC_FILTER0_DONT_CARE(idx) (A_MPS_TRC_FILTER0_DONT_CARE + (idx) * 4)
162 #define NUM_MPS_TRC_FILTER0_DONT_CARE_INSTANCES 28
163 
164 #define MPS_TRC_FILTER1_MATCH(idx) (A_MPS_TRC_FILTER1_MATCH + (idx) * 4)
165 #define NUM_MPS_TRC_FILTER1_MATCH_INSTANCES 28
166 
167 #define MPS_TRC_FILTER1_DONT_CARE(idx) (A_MPS_TRC_FILTER1_DONT_CARE + (idx) * 4)
168 #define NUM_MPS_TRC_FILTER1_DONT_CARE_INSTANCES 28
169 
170 #define MPS_TRC_FILTER2_MATCH(idx) (A_MPS_TRC_FILTER2_MATCH + (idx) * 4)
171 #define NUM_MPS_TRC_FILTER2_MATCH_INSTANCES 28
172 
173 #define MPS_TRC_FILTER2_DONT_CARE(idx) (A_MPS_TRC_FILTER2_DONT_CARE + (idx) * 4)
174 #define NUM_MPS_TRC_FILTER2_DONT_CARE_INSTANCES 28
175 
176 #define MPS_TRC_FILTER3_MATCH(idx) (A_MPS_TRC_FILTER3_MATCH + (idx) * 4)
177 #define NUM_MPS_TRC_FILTER3_MATCH_INSTANCES 28
178 
179 #define MPS_TRC_FILTER3_DONT_CARE(idx) (A_MPS_TRC_FILTER3_DONT_CARE + (idx) * 4)
180 #define NUM_MPS_TRC_FILTER3_DONT_CARE_INSTANCES 28
181 
182 #define MPS_PORT_CLS_HASH_SRAM(idx) (A_MPS_PORT_CLS_HASH_SRAM + (idx) * 4)
183 #define NUM_MPS_PORT_CLS_HASH_SRAM_INSTANCES 65
184 
185 #define MPS_CLS_VLAN_TABLE(idx) (A_MPS_CLS_VLAN_TABLE + (idx) * 4)
186 #define NUM_MPS_CLS_VLAN_TABLE_INSTANCES 9
187 
188 #define MPS_CLS_SRAM_L(idx) (A_MPS_CLS_SRAM_L + (idx) * 8)
189 #define NUM_MPS_CLS_SRAM_L_INSTANCES 336
190 
191 #define MPS_CLS_SRAM_H(idx) (A_MPS_CLS_SRAM_H + (idx) * 8)
192 #define NUM_MPS_CLS_SRAM_H_INSTANCES 336
193 
194 #define MPS_CLS_TCAM_Y_L(idx) (A_MPS_CLS_TCAM_Y_L + (idx) * 16)
195 #define NUM_MPS_CLS_TCAM_Y_L_INSTANCES 512
196 
197 #define MPS_CLS_TCAM_Y_H(idx) (A_MPS_CLS_TCAM_Y_H + (idx) * 16)
198 #define NUM_MPS_CLS_TCAM_Y_H_INSTANCES 512
199 
200 #define MPS_CLS_TCAM_X_L(idx) (A_MPS_CLS_TCAM_X_L + (idx) * 16)
201 #define NUM_MPS_CLS_TCAM_X_L_INSTANCES 512
202 
203 #define MPS_CLS_TCAM_X_H(idx) (A_MPS_CLS_TCAM_X_H + (idx) * 16)
204 #define NUM_MPS_CLS_TCAM_X_H_INSTANCES 512
205 
206 #define PL_SEMAPHORE_LOCK(idx) (A_PL_SEMAPHORE_LOCK + (idx) * 4)
207 #define NUM_PL_SEMAPHORE_LOCK_INSTANCES 8
208 
209 #define PL_VF_SLICE_L(idx) (A_PL_VF_SLICE_L + (idx) * 8)
210 #define NUM_PL_VF_SLICE_L_INSTANCES 8
211 
212 #define PL_VF_SLICE_H(idx) (A_PL_VF_SLICE_H + (idx) * 8)
213 #define NUM_PL_VF_SLICE_H_INSTANCES 8
214 
215 #define PL_FLR_VF_STATUS(idx) (A_PL_FLR_VF_STATUS + (idx) * 4)
216 #define NUM_PL_FLR_VF_STATUS_INSTANCES 4
217 
218 #define PL_VFID_MAP(idx) (A_PL_VFID_MAP + (idx) * 4)
219 #define NUM_PL_VFID_MAP_INSTANCES 256
220 
221 #define LE_DB_MASK_IPV4(idx) (A_LE_DB_MASK_IPV4 + (idx) * 4)
222 #define NUM_LE_DB_MASK_IPV4_INSTANCES 17
223 
224 #define LE_DB_MASK_IPV6(idx) (A_LE_DB_MASK_IPV6 + (idx) * 4)
225 #define NUM_LE_DB_MASK_IPV6_INSTANCES 17
226 
227 #define LE_DB_DBGI_REQ_DATA(idx) (A_LE_DB_DBGI_REQ_DATA + (idx) * 4)
228 #define NUM_LE_DB_DBGI_REQ_DATA_INSTANCES 17
229 
230 #define LE_DB_DBGI_REQ_MASK(idx) (A_LE_DB_DBGI_REQ_MASK + (idx) * 4)
231 #define NUM_LE_DB_DBGI_REQ_MASK_INSTANCES 17
232 
233 #define LE_DB_DBGI_RSP_DATA(idx) (A_LE_DB_DBGI_RSP_DATA + (idx) * 4)
234 #define NUM_LE_DB_DBGI_RSP_DATA_INSTANCES 17
235 
236 #define LE_DB_ACTIVE_MASK_IPV4(idx) (A_LE_DB_ACTIVE_MASK_IPV4 + (idx) * 4)
237 #define NUM_LE_DB_ACTIVE_MASK_IPV4_INSTANCES 17
238 
239 #define LE_DB_ACTIVE_MASK_IPV6(idx) (A_LE_DB_ACTIVE_MASK_IPV6 + (idx) * 4)
240 #define NUM_LE_DB_ACTIVE_MASK_IPV6_INSTANCES 17
241 
242 #define LE_HASH_MASK_GEN_IPV4(idx) (A_LE_HASH_MASK_GEN_IPV4 + (idx) * 4)
243 #define NUM_LE_HASH_MASK_GEN_IPV4_INSTANCES 4
244 
245 #define LE_HASH_MASK_GEN_IPV6(idx) (A_LE_HASH_MASK_GEN_IPV6 + (idx) * 4)
246 #define NUM_LE_HASH_MASK_GEN_IPV6_INSTANCES 12
247 
248 #define LE_HASH_MASK_CMP_IPV4(idx) (A_LE_HASH_MASK_CMP_IPV4 + (idx) * 4)
249 #define NUM_LE_HASH_MASK_CMP_IPV4_INSTANCES 4
250 
251 #define LE_HASH_MASK_CMP_IPV6(idx) (A_LE_HASH_MASK_CMP_IPV6 + (idx) * 4)
252 #define NUM_LE_HASH_MASK_CMP_IPV6_INSTANCES 12
253 
254 #define UP_TSCH_CHANNEL_REG(reg_addr, idx) ((reg_addr) + (idx) * 16)
255 #define NUM_UP_TSCH_CHANNEL_INSTANCES 4
256 
257 #define CIM_CTL_MAILBOX_VF_STATUS(idx) (A_CIM_CTL_MAILBOX_VF_STATUS + (idx) * 4)
258 #define NUM_CIM_CTL_MAILBOX_VF_STATUS_INSTANCES 4
259 
260 #define CIM_CTL_MAILBOX_VFN_CTL(idx) (A_CIM_CTL_MAILBOX_VFN_CTL + (idx) * 16)
261 #define NUM_CIM_CTL_MAILBOX_VFN_CTL_INSTANCES 128
262 
263 #define CIM_CTL_TSCH_CHANNEL_REG(reg_addr, idx) ((reg_addr) + (idx) * 288)
264 #define NUM_CIM_CTL_TSCH_CHANNEL_INSTANCES 4
265 
266 #define CIM_CTL_TSCH_CHANNEL_TSCH_CLASS_REG(reg_addr, idx) ((reg_addr) + (idx) * 16)
267 #define NUM_CIM_CTL_TSCH_CHANNEL_TSCH_CLASS_INSTANCES 16
268 
269 #define T5_MYPORT_BASE 0x2c000
270 #define T5_MYPORT_REG(reg_addr) (T5_MYPORT_BASE + (reg_addr))
271 
272 #define T5_PORT0_BASE 0x30000
273 #define T5_PORT0_REG(reg_addr) (T5_PORT0_BASE + (reg_addr))
274 
275 #define T5_PORT1_BASE 0x34000
276 #define T5_PORT1_REG(reg_addr) (T5_PORT1_BASE + (reg_addr))
277 
278 #define T5_PORT2_BASE 0x38000
279 #define T5_PORT2_REG(reg_addr) (T5_PORT2_BASE + (reg_addr))
280 
281 #define T5_PORT3_BASE 0x3c000
282 #define T5_PORT3_REG(reg_addr) (T5_PORT3_BASE + (reg_addr))
283 
284 #define T5_PORT_STRIDE 0x4000
285 #define T5_PORT_BASE(idx) (T5_PORT0_BASE + (idx) * T5_PORT_STRIDE)
286 #define T5_PORT_REG(idx, reg) (T5_PORT_BASE(idx) + (reg))
287 
288 #define MC_STRIDE (MC_1_BASE_ADDR - MC_0_BASE_ADDR)
289 #define MC_REG(reg, idx) (reg + MC_STRIDE * idx)
290 
291 #define PCIE_PF_INT_REG(reg_addr, idx) ((reg_addr) + (idx) * 8)
292 #define NUM_PCIE_PF_INT_INSTANCES 8
293 
294 #define PCIE_VF_INT_REG(reg_addr, idx) ((reg_addr) + (idx) * 8)
295 #define NUM_PCIE_VF_INT_INSTANCES 128
296 
297 #define PCIE_FID_VFID(idx) (A_PCIE_FID_VFID + (idx) * 4)
298 #define NUM_PCIE_FID_VFID_INSTANCES 2048
299 
300 #define PCIE_COOKIE_REG(reg_addr, idx) ((reg_addr) + (idx) * 4)
301 #define NUM_PCIE_COOKIE_INSTANCES 8
302 
303 #define PCIE_T5_DMA_REG(reg_addr, idx) ((reg_addr) + (idx) * 16)
304 #define NUM_PCIE_T5_DMA_INSTANCES 4
305 
306 #define PCIE_T5_CMD_REG(reg_addr, idx) ((reg_addr) + (idx) * 16)
307 #define NUM_PCIE_T5_CMD_INSTANCES 3
308 
309 #define PCIE_T5_HMA_REG(reg_addr, idx) ((reg_addr) + (idx) * 16)
310 #define NUM_PCIE_T5_HMA_INSTANCES 1
311 
312 #define PCIE_PHY_PRESET_REG(reg_addr, idx) ((reg_addr) + (idx) * 4)
313 #define NUM_PCIE_PHY_PRESET_INSTANCES 11
314 
315 #define MPS_T5_CLS_SRAM_L(idx) (A_MPS_T5_CLS_SRAM_L + (idx) * 8)
316 #define NUM_MPS_T5_CLS_SRAM_L_INSTANCES 512
317 
318 #define MPS_T5_CLS_SRAM_H(idx) (A_MPS_T5_CLS_SRAM_H + (idx) * 8)
319 #define NUM_MPS_T5_CLS_SRAM_H_INSTANCES 512
320 
321 #define LE_T5_DB_MASK_IPV4(idx) (A_LE_T5_DB_MASK_IPV4 + (idx) * 4)
322 #define NUM_LE_T5_DB_MASK_IPV4_INSTANCES 5
323 
324 #define LE_T5_DB_ACTIVE_MASK_IPV4(idx) (A_LE_T5_DB_ACTIVE_MASK_IPV4 + (idx) * 4)
325 #define NUM_LE_T5_DB_ACTIVE_MASK_IPV4_INSTANCES 5
326 
327 #define LE_HASH_MASK_GEN_IPV4T5(idx) (A_LE_HASH_MASK_GEN_IPV4T5 + (idx) * 4)
328 #define NUM_LE_HASH_MASK_GEN_IPV4T5_INSTANCES 5
329 
330 #define LE_HASH_MASK_GEN_IPV6T5(idx) (A_LE_HASH_MASK_GEN_IPV6T5 + (idx) * 4)
331 #define NUM_LE_HASH_MASK_GEN_IPV6T5_INSTANCES 12
332 
333 #define LE_HASH_MASK_CMP_IPV4T5(idx) (A_LE_HASH_MASK_CMP_IPV4T5 + (idx) * 4)
334 #define NUM_LE_HASH_MASK_CMP_IPV4T5_INSTANCES 5
335 
336 #define LE_HASH_MASK_CMP_IPV6T5(idx) (A_LE_HASH_MASK_CMP_IPV6T5 + (idx) * 4)
337 #define NUM_LE_HASH_MASK_CMP_IPV6T5_INSTANCES 12
338 
339 #define LE_DB_SECOND_ACTIVE_MASK_IPV4(idx) (A_LE_DB_SECOND_ACTIVE_MASK_IPV4 + (idx) * 4)
340 #define NUM_LE_DB_SECOND_ACTIVE_MASK_IPV4_INSTANCES 5
341 
342 #define LE_DB_SECOND_GEN_HASH_MASK_IPV4(idx) (A_LE_DB_SECOND_GEN_HASH_MASK_IPV4 + (idx) * 4)
343 #define NUM_LE_DB_SECOND_GEN_HASH_MASK_IPV4_INSTANCES 5
344 
345 #define LE_DB_SECOND_CMP_HASH_MASK_IPV4(idx) (A_LE_DB_SECOND_CMP_HASH_MASK_IPV4 + (idx) * 4)
346 #define NUM_LE_DB_SECOND_CMP_HASH_MASK_IPV4_INSTANCES 5
347 
348 #define MC_ADR_REG(reg_addr, idx) ((reg_addr) + (idx) * 512)
349 #define NUM_MC_ADR_INSTANCES 2
350 
351 #define MC_DDRPHY_DP18_REG(reg_addr, idx) ((reg_addr) + (idx) * 512)
352 #define NUM_MC_DDRPHY_DP18_INSTANCES 5
353 
354 #define MC_CE_ERR_DATA_REG(reg_addr, idx) ((reg_addr) + (idx) * 4)
355 #define NUM_MC_CE_ERR_DATA_INSTANCES 8
356 
357 #define MC_CE_COR_DATA_REG(reg_addr, idx) ((reg_addr) + (idx) * 4)
358 #define NUM_MC_CE_COR_DATA_INSTANCES 8
359 
360 #define MC_UE_ERR_DATA_REG(reg_addr, idx) ((reg_addr) + (idx) * 4)
361 #define NUM_MC_UE_ERR_DATA_INSTANCES 8
362 
363 #define MC_UE_COR_DATA_REG(reg_addr, idx) ((reg_addr) + (idx) * 4)
364 #define NUM_MC_UE_COR_DATA_INSTANCES 8
365 
366 #define MC_P_BIST_STATUS_REG(reg_addr, idx) ((reg_addr) + (idx) * 4)
367 #define NUM_MC_P_BIST_STATUS_INSTANCES 18
368 
369 #define EDC_H_BIST_STATUS_REG(reg_addr, idx) ((reg_addr) + (idx) * 4)
370 #define NUM_EDC_H_BIST_STATUS_INSTANCES 18
371 
372 #define EDC_H_ECC_ERR_DATA_REG(reg_addr, idx) ((reg_addr) + (idx) * 4)
373 #define NUM_EDC_H_ECC_ERR_DATA_INSTANCES 16
374 
375 #define SGE_DEBUG1_DBP_THREAD(idx) (A_SGE_DEBUG1_DBP_THREAD + (idx) * 4)
376 #define NUM_SGE_DEBUG1_DBP_THREAD_INSTANCES 4
377 
378 #define SGE_DEBUG0_DBP_THREAD(idx) (A_SGE_DEBUG0_DBP_THREAD + (idx) * 4)
379 #define NUM_SGE_DEBUG0_DBP_THREAD_INSTANCES 5
380 
381 #define SGE_WC_EGRS_BAR2_OFF_PF(idx) (A_SGE_WC_EGRS_BAR2_OFF_PF + (idx) * 4)
382 #define NUM_SGE_WC_EGRS_BAR2_OFF_PF_INSTANCES 8
383 
384 #define SGE_WC_EGRS_BAR2_OFF_VF(idx) (A_SGE_WC_EGRS_BAR2_OFF_VF + (idx) * 4)
385 #define NUM_SGE_WC_EGRS_BAR2_OFF_VF_INSTANCES 8
386 
387 #define PCIE_T6_DMA_REG(reg_addr, idx) ((reg_addr) + (idx) * 16)
388 #define NUM_PCIE_T6_DMA_INSTANCES 2
389 
390 #define PCIE_T6_CMD_REG(reg_addr, idx) ((reg_addr) + (idx) * 16)
391 #define NUM_PCIE_T6_CMD_INSTANCES 1
392 
393 #define PCIE_VF_256_INT_REG(reg_addr, idx) ((reg_addr) + (idx) * 4)
394 #define NUM_PCIE_VF_256_INT_INSTANCES 128
395 
396 #define MPS_CLS_REQUEST_TRACE_MAC_DA_L(idx) (A_MPS_CLS_REQUEST_TRACE_MAC_DA_L + (idx) * 32)
397 #define NUM_MPS_CLS_REQUEST_TRACE_MAC_DA_L_INSTANCES 8
398 
399 #define MPS_CLS_REQUEST_TRACE_MAC_DA_H(idx) (A_MPS_CLS_REQUEST_TRACE_MAC_DA_H + (idx) * 32)
400 #define NUM_MPS_CLS_REQUEST_TRACE_MAC_DA_H_INSTANCES 8
401 
402 #define MPS_CLS_REQUEST_TRACE_MAC_SA_L(idx) (A_MPS_CLS_REQUEST_TRACE_MAC_SA_L + (idx) * 32)
403 #define NUM_MPS_CLS_REQUEST_TRACE_MAC_SA_L_INSTANCES 8
404 
405 #define MPS_CLS_REQUEST_TRACE_MAC_SA_H(idx) (A_MPS_CLS_REQUEST_TRACE_MAC_SA_H + (idx) * 32)
406 #define NUM_MPS_CLS_REQUEST_TRACE_MAC_SA_H_INSTANCES 8
407 
408 #define MPS_CLS_REQUEST_TRACE_PORT_VLAN(idx) (A_MPS_CLS_REQUEST_TRACE_PORT_VLAN + (idx) * 32)
409 #define NUM_MPS_CLS_REQUEST_TRACE_PORT_VLAN_INSTANCES 8
410 
411 #define MPS_CLS_REQUEST_TRACE_ENCAP(idx) (A_MPS_CLS_REQUEST_TRACE_ENCAP + (idx) * 32)
412 #define NUM_MPS_CLS_REQUEST_TRACE_ENCAP_INSTANCES 8
413 
414 #define MPS_CLS_RESULT_TRACE(idx) (A_MPS_CLS_RESULT_TRACE + (idx) * 4)
415 #define NUM_MPS_CLS_RESULT_TRACE_INSTANCES 8
416 
417 #define MPS_CLS_DIPIPV4_ID_TABLE(idx) (A_MPS_CLS_DIPIPV4_ID_TABLE + (idx) * 8)
418 #define NUM_MPS_CLS_DIPIPV4_ID_TABLE_INSTANCES 4
419 
420 #define MPS_CLS_DIPIPV4_MASK_TABLE(idx) (A_MPS_CLS_DIPIPV4_MASK_TABLE + (idx) * 8)
421 #define NUM_MPS_CLS_DIPIPV4_MASK_TABLE_INSTANCES 4
422 
423 #define MPS_CLS_DIPIPV6ID_0_TABLE(idx) (A_MPS_CLS_DIPIPV6ID_0_TABLE + (idx) * 32)
424 #define NUM_MPS_CLS_DIPIPV6ID_0_TABLE_INSTANCES 2
425 
426 #define MPS_CLS_DIPIPV6ID_1_TABLE(idx) (A_MPS_CLS_DIPIPV6ID_1_TABLE + (idx) * 32)
427 #define NUM_MPS_CLS_DIPIPV6ID_1_TABLE_INSTANCES 2
428 
429 #define MPS_CLS_DIPIPV6ID_2_TABLE(idx) (A_MPS_CLS_DIPIPV6ID_2_TABLE + (idx) * 32)
430 #define NUM_MPS_CLS_DIPIPV6ID_2_TABLE_INSTANCES 2
431 
432 #define MPS_CLS_DIPIPV6ID_3_TABLE(idx) (A_MPS_CLS_DIPIPV6ID_3_TABLE + (idx) * 32)
433 #define NUM_MPS_CLS_DIPIPV6ID_3_TABLE_INSTANCES 2
434 
435 #define MPS_CLS_DIPIPV6MASK_0_TABLE(idx) (A_MPS_CLS_DIPIPV6MASK_0_TABLE + (idx) * 32)
436 #define NUM_MPS_CLS_DIPIPV6MASK_0_TABLE_INSTANCES 2
437 
438 #define MPS_CLS_DIPIPV6MASK_1_TABLE(idx) (A_MPS_CLS_DIPIPV6MASK_1_TABLE + (idx) * 32)
439 #define NUM_MPS_CLS_DIPIPV6MASK_1_TABLE_INSTANCES 2
440 
441 #define MPS_CLS_DIPIPV6MASK_2_TABLE(idx) (A_MPS_CLS_DIPIPV6MASK_2_TABLE + (idx) * 32)
442 #define NUM_MPS_CLS_DIPIPV6MASK_2_TABLE_INSTANCES 2
443 
444 #define MPS_CLS_DIPIPV6MASK_3_TABLE(idx) (A_MPS_CLS_DIPIPV6MASK_3_TABLE + (idx) * 32)
445 #define NUM_MPS_CLS_DIPIPV6MASK_3_TABLE_INSTANCES 2
446 
447 #define MPS_RX_HASH_LKP_TABLE(idx) (A_MPS_RX_HASH_LKP_TABLE + (idx) * 4)
448 #define NUM_MPS_RX_HASH_LKP_TABLE_INSTANCES 4
449 
450 #define LE_DB_DBG_MATCH_DATA_MASK(idx) (A_LE_DB_DBG_MATCH_DATA_MASK + (idx) * 4)
451 #define NUM_LE_DB_DBG_MATCH_DATA_MASK_INSTANCES 8
452 
453 #define LE_DB_DBG_MATCH_DATA(idx) (A_LE_DB_DBG_MATCH_DATA + (idx) * 4)
454 #define NUM_LE_DB_DBG_MATCH_DATA_INSTANCES 8
455 
456 #define LE_DB_DBGI_REQ_DATA_T6(idx) (A_LE_DB_DBGI_REQ_DATA + (idx) * 4)
457 #define NUM_LE_DB_DBGI_REQ_DATA_T6_INSTANCES 11
458 
459 #define LE_DB_DBGI_REQ_MASK_T6(idx) (A_LE_DB_DBGI_REQ_MASK + (idx) * 4)
460 #define NUM_LE_DB_DBGI_REQ_MASK_T6_INSTANCES 11
461 
462 #define LE_DB_DBGI_RSP_DATA_T6(idx) (A_LE_DB_DBGI_RSP_DATA + (idx) * 4)
463 #define NUM_LE_DB_DBGI_RSP_DATA_T6_INSTANCES 11
464 
465 #define LE_DB_ACTIVE_MASK_IPV6_T6(idx) (A_LE_DB_ACTIVE_MASK_IPV6 + (idx) * 4)
466 #define NUM_LE_DB_ACTIVE_MASK_IPV6_T6_INSTANCES 8
467 
468 #define LE_HASH_MASK_GEN_IPV4T6(idx) (A_LE_HASH_MASK_GEN_IPV4T5 + (idx) * 4)
469 #define NUM_LE_HASH_MASK_GEN_IPV4T6_INSTANCES 8
470 
471 #define T6_LE_HASH_MASK_GEN_IPV6T5(idx) (A_T6_LE_HASH_MASK_GEN_IPV6T5 + (idx) * 4)
472 #define NUM_T6_LE_HASH_MASK_GEN_IPV6T5_INSTANCES 8
473 
474 #define LE_DB_PSV_FILTER_MASK_TUP_IPV4(idx) (A_LE_DB_PSV_FILTER_MASK_TUP_IPV4 + (idx) * 4)
475 #define NUM_LE_DB_PSV_FILTER_MASK_TUP_IPV4_INSTANCES 3
476 
477 #define LE_DB_PSV_FILTER_MASK_FLT_IPV4(idx) (A_LE_DB_PSV_FILTER_MASK_FLT_IPV4 + (idx) * 4)
478 #define NUM_LE_DB_PSV_FILTER_MASK_FLT_IPV4_INSTANCES 2
479 
480 #define LE_DB_PSV_FILTER_MASK_TUP_IPV6(idx) (A_LE_DB_PSV_FILTER_MASK_TUP_IPV6 + (idx) * 4)
481 #define NUM_LE_DB_PSV_FILTER_MASK_TUP_IPV6_INSTANCES 9
482 
483 #define LE_DB_PSV_FILTER_MASK_FLT_IPV6(idx) (A_LE_DB_PSV_FILTER_MASK_FLT_IPV6 + (idx) * 4)
484 #define NUM_LE_DB_PSV_FILTER_MASK_FLT_IPV6_INSTANCES 2
485 
486 #define LE_DB_SECOND_GEN_HASH_MASK_IPV4_T6(idx) (A_LE_DB_SECOND_GEN_HASH_MASK_IPV4 + (idx) * 4)
487 #define NUM_LE_DB_SECOND_GEN_HASH_MASK_IPV4_T6_INSTANCES 8
488 
489 #define MC_DDRPHY_DP18_T6_REG(reg_addr, idx) ((reg_addr) + (idx) * 512)
490 #define NUM_MC_DDRPHY_DP18_T6_INSTANCES 9
491 
492 #define MC_CE_ERR_DATA_T6_REG(reg_addr, idx) ((reg_addr) + (idx) * 4)
493 #define NUM_MC_CE_ERR_DATA_T6_INSTANCES 16
494 
495 #define MC_UE_ERR_DATA_T6_REG(reg_addr, idx) ((reg_addr) + (idx) * 4)
496 #define NUM_MC_UE_ERR_DATA_T6_INSTANCES 16
497 
498 #define CIM_CTL_MAILBOX_VF_STATUS_T6(idx) (A_CIM_CTL_MAILBOX_VF_STATUS + (idx) * 4)
499 #define NUM_CIM_CTL_MAILBOX_VF_STATUS_T6_INSTANCES 8
500 
501 #define CIM_CTL_MAILBOX_VFN_CTL_T6(idx) (A_CIM_CTL_MAILBOX_VFN_CTL + (idx) * 4)
502 #define NUM_CIM_CTL_MAILBOX_VFN_CTL_T6_INSTANCES 256
503 
504 #define EDC_STRIDE (EDC_1_BASE_ADDR - EDC_0_BASE_ADDR)
505 #define EDC_REG(reg, idx) (reg + EDC_STRIDE * idx)
506 
507 #define EDC_T5_STRIDE (EDC_T51_BASE_ADDR - EDC_T50_BASE_ADDR)
508 #define EDC_T5_REG(reg, idx) (reg + EDC_T5_STRIDE * idx)
509 
510 /* registers for module SGE */
511 #define SGE_BASE_ADDR 0x1000
512 
513 #define A_SGE_PF_KDOORBELL 0x0
514 
515 #define S_QID    15
516 #define M_QID    0x1ffffU
517 #define V_QID(x) ((x) << S_QID)
518 #define G_QID(x) (((x) >> S_QID) & M_QID)
519 
520 #define S_DBPRIO    14
521 #define V_DBPRIO(x) ((x) << S_DBPRIO)
522 #define F_DBPRIO    V_DBPRIO(1U)
523 
524 #define S_PIDX    0
525 #define M_PIDX    0x3fffU
526 #define V_PIDX(x) ((x) << S_PIDX)
527 #define G_PIDX(x) (((x) >> S_PIDX) & M_PIDX)
528 
529 #define A_SGE_VF_KDOORBELL 0x0
530 
531 #define S_DBTYPE    13
532 #define V_DBTYPE(x) ((x) << S_DBTYPE)
533 #define F_DBTYPE    V_DBTYPE(1U)
534 
535 #define S_PIDX_T5    0
536 #define M_PIDX_T5    0x1fffU
537 #define V_PIDX_T5(x) ((x) << S_PIDX_T5)
538 #define G_PIDX_T5(x) (((x) >> S_PIDX_T5) & M_PIDX_T5)
539 
540 #define S_SYNC_T6    14
541 #define V_SYNC_T6(x) ((x) << S_SYNC_T6)
542 #define F_SYNC_T6    V_SYNC_T6(1U)
543 
544 #define A_SGE_PF_GTS 0x4
545 
546 #define S_INGRESSQID    16
547 #define M_INGRESSQID    0xffffU
548 #define V_INGRESSQID(x) ((x) << S_INGRESSQID)
549 #define G_INGRESSQID(x) (((x) >> S_INGRESSQID) & M_INGRESSQID)
550 
551 #define S_TIMERREG    13
552 #define M_TIMERREG    0x7U
553 #define V_TIMERREG(x) ((x) << S_TIMERREG)
554 #define G_TIMERREG(x) (((x) >> S_TIMERREG) & M_TIMERREG)
555 
556 #define S_SEINTARM    12
557 #define V_SEINTARM(x) ((x) << S_SEINTARM)
558 #define F_SEINTARM    V_SEINTARM(1U)
559 
560 #define S_CIDXINC    0
561 #define M_CIDXINC    0xfffU
562 #define V_CIDXINC(x) ((x) << S_CIDXINC)
563 #define G_CIDXINC(x) (((x) >> S_CIDXINC) & M_CIDXINC)
564 
565 #define A_SGE_VF_GTS 0x4
566 #define A_SGE_PF_KTIMESTAMP_LO 0x8
567 #define A_SGE_VF_KTIMESTAMP_LO 0x8
568 #define A_SGE_PF_KTIMESTAMP_HI 0xc
569 
570 #define S_TSTAMPVAL    0
571 #define M_TSTAMPVAL    0xfffffffU
572 #define V_TSTAMPVAL(x) ((x) << S_TSTAMPVAL)
573 #define G_TSTAMPVAL(x) (((x) >> S_TSTAMPVAL) & M_TSTAMPVAL)
574 
575 #define A_SGE_VF_KTIMESTAMP_HI 0xc
576 #define A_SGE_CONTROL 0x1008
577 
578 #define S_IGRALLCPLTOFL    31
579 #define V_IGRALLCPLTOFL(x) ((x) << S_IGRALLCPLTOFL)
580 #define F_IGRALLCPLTOFL    V_IGRALLCPLTOFL(1U)
581 
582 #define S_FLSPLITMIN    22
583 #define M_FLSPLITMIN    0x1ffU
584 #define V_FLSPLITMIN(x) ((x) << S_FLSPLITMIN)
585 #define G_FLSPLITMIN(x) (((x) >> S_FLSPLITMIN) & M_FLSPLITMIN)
586 
587 #define S_FLSPLITMODE    20
588 #define M_FLSPLITMODE    0x3U
589 #define V_FLSPLITMODE(x) ((x) << S_FLSPLITMODE)
590 #define G_FLSPLITMODE(x) (((x) >> S_FLSPLITMODE) & M_FLSPLITMODE)
591 
592 #define S_DCASYSTYPE    19
593 #define V_DCASYSTYPE(x) ((x) << S_DCASYSTYPE)
594 #define F_DCASYSTYPE    V_DCASYSTYPE(1U)
595 
596 #define S_RXPKTCPLMODE    18
597 #define V_RXPKTCPLMODE(x) ((x) << S_RXPKTCPLMODE)
598 #define F_RXPKTCPLMODE    V_RXPKTCPLMODE(1U)
599 
600 #define S_EGRSTATUSPAGESIZE    17
601 #define V_EGRSTATUSPAGESIZE(x) ((x) << S_EGRSTATUSPAGESIZE)
602 #define F_EGRSTATUSPAGESIZE    V_EGRSTATUSPAGESIZE(1U)
603 
604 #define S_INGHINTENABLE1    15
605 #define V_INGHINTENABLE1(x) ((x) << S_INGHINTENABLE1)
606 #define F_INGHINTENABLE1    V_INGHINTENABLE1(1U)
607 
608 #define S_INGHINTENABLE0    14
609 #define V_INGHINTENABLE0(x) ((x) << S_INGHINTENABLE0)
610 #define F_INGHINTENABLE0    V_INGHINTENABLE0(1U)
611 
612 #define S_INGINTCOMPAREIDX    13
613 #define V_INGINTCOMPAREIDX(x) ((x) << S_INGINTCOMPAREIDX)
614 #define F_INGINTCOMPAREIDX    V_INGINTCOMPAREIDX(1U)
615 
616 #define S_PKTSHIFT    10
617 #define M_PKTSHIFT    0x7U
618 #define V_PKTSHIFT(x) ((x) << S_PKTSHIFT)
619 #define G_PKTSHIFT(x) (((x) >> S_PKTSHIFT) & M_PKTSHIFT)
620 
621 #define S_INGPCIEBOUNDARY    7
622 #define M_INGPCIEBOUNDARY    0x7U
623 #define V_INGPCIEBOUNDARY(x) ((x) << S_INGPCIEBOUNDARY)
624 #define G_INGPCIEBOUNDARY(x) (((x) >> S_INGPCIEBOUNDARY) & M_INGPCIEBOUNDARY)
625 
626 #define S_INGPADBOUNDARY    4
627 #define M_INGPADBOUNDARY    0x7U
628 #define V_INGPADBOUNDARY(x) ((x) << S_INGPADBOUNDARY)
629 #define G_INGPADBOUNDARY(x) (((x) >> S_INGPADBOUNDARY) & M_INGPADBOUNDARY)
630 
631 #define S_EGRPCIEBOUNDARY    1
632 #define M_EGRPCIEBOUNDARY    0x7U
633 #define V_EGRPCIEBOUNDARY(x) ((x) << S_EGRPCIEBOUNDARY)
634 #define G_EGRPCIEBOUNDARY(x) (((x) >> S_EGRPCIEBOUNDARY) & M_EGRPCIEBOUNDARY)
635 
636 #define S_GLOBALENABLE    0
637 #define V_GLOBALENABLE(x) ((x) << S_GLOBALENABLE)
638 #define F_GLOBALENABLE    V_GLOBALENABLE(1U)
639 
640 #define A_SGE_HOST_PAGE_SIZE 0x100c
641 
642 #define S_HOSTPAGESIZEPF7    28
643 #define M_HOSTPAGESIZEPF7    0xfU
644 #define V_HOSTPAGESIZEPF7(x) ((x) << S_HOSTPAGESIZEPF7)
645 #define G_HOSTPAGESIZEPF7(x) (((x) >> S_HOSTPAGESIZEPF7) & M_HOSTPAGESIZEPF7)
646 
647 #define S_HOSTPAGESIZEPF6    24
648 #define M_HOSTPAGESIZEPF6    0xfU
649 #define V_HOSTPAGESIZEPF6(x) ((x) << S_HOSTPAGESIZEPF6)
650 #define G_HOSTPAGESIZEPF6(x) (((x) >> S_HOSTPAGESIZEPF6) & M_HOSTPAGESIZEPF6)
651 
652 #define S_HOSTPAGESIZEPF5    20
653 #define M_HOSTPAGESIZEPF5    0xfU
654 #define V_HOSTPAGESIZEPF5(x) ((x) << S_HOSTPAGESIZEPF5)
655 #define G_HOSTPAGESIZEPF5(x) (((x) >> S_HOSTPAGESIZEPF5) & M_HOSTPAGESIZEPF5)
656 
657 #define S_HOSTPAGESIZEPF4    16
658 #define M_HOSTPAGESIZEPF4    0xfU
659 #define V_HOSTPAGESIZEPF4(x) ((x) << S_HOSTPAGESIZEPF4)
660 #define G_HOSTPAGESIZEPF4(x) (((x) >> S_HOSTPAGESIZEPF4) & M_HOSTPAGESIZEPF4)
661 
662 #define S_HOSTPAGESIZEPF3    12
663 #define M_HOSTPAGESIZEPF3    0xfU
664 #define V_HOSTPAGESIZEPF3(x) ((x) << S_HOSTPAGESIZEPF3)
665 #define G_HOSTPAGESIZEPF3(x) (((x) >> S_HOSTPAGESIZEPF3) & M_HOSTPAGESIZEPF3)
666 
667 #define S_HOSTPAGESIZEPF2    8
668 #define M_HOSTPAGESIZEPF2    0xfU
669 #define V_HOSTPAGESIZEPF2(x) ((x) << S_HOSTPAGESIZEPF2)
670 #define G_HOSTPAGESIZEPF2(x) (((x) >> S_HOSTPAGESIZEPF2) & M_HOSTPAGESIZEPF2)
671 
672 #define S_HOSTPAGESIZEPF1    4
673 #define M_HOSTPAGESIZEPF1    0xfU
674 #define V_HOSTPAGESIZEPF1(x) ((x) << S_HOSTPAGESIZEPF1)
675 #define G_HOSTPAGESIZEPF1(x) (((x) >> S_HOSTPAGESIZEPF1) & M_HOSTPAGESIZEPF1)
676 
677 #define S_HOSTPAGESIZEPF0    0
678 #define M_HOSTPAGESIZEPF0    0xfU
679 #define V_HOSTPAGESIZEPF0(x) ((x) << S_HOSTPAGESIZEPF0)
680 #define G_HOSTPAGESIZEPF0(x) (((x) >> S_HOSTPAGESIZEPF0) & M_HOSTPAGESIZEPF0)
681 
682 #define A_SGE_EGRESS_QUEUES_PER_PAGE_PF 0x1010
683 
684 #define S_QUEUESPERPAGEPF7    28
685 #define M_QUEUESPERPAGEPF7    0xfU
686 #define V_QUEUESPERPAGEPF7(x) ((x) << S_QUEUESPERPAGEPF7)
687 #define G_QUEUESPERPAGEPF7(x) (((x) >> S_QUEUESPERPAGEPF7) & M_QUEUESPERPAGEPF7)
688 
689 #define S_QUEUESPERPAGEPF6    24
690 #define M_QUEUESPERPAGEPF6    0xfU
691 #define V_QUEUESPERPAGEPF6(x) ((x) << S_QUEUESPERPAGEPF6)
692 #define G_QUEUESPERPAGEPF6(x) (((x) >> S_QUEUESPERPAGEPF6) & M_QUEUESPERPAGEPF6)
693 
694 #define S_QUEUESPERPAGEPF5    20
695 #define M_QUEUESPERPAGEPF5    0xfU
696 #define V_QUEUESPERPAGEPF5(x) ((x) << S_QUEUESPERPAGEPF5)
697 #define G_QUEUESPERPAGEPF5(x) (((x) >> S_QUEUESPERPAGEPF5) & M_QUEUESPERPAGEPF5)
698 
699 #define S_QUEUESPERPAGEPF4    16
700 #define M_QUEUESPERPAGEPF4    0xfU
701 #define V_QUEUESPERPAGEPF4(x) ((x) << S_QUEUESPERPAGEPF4)
702 #define G_QUEUESPERPAGEPF4(x) (((x) >> S_QUEUESPERPAGEPF4) & M_QUEUESPERPAGEPF4)
703 
704 #define S_QUEUESPERPAGEPF3    12
705 #define M_QUEUESPERPAGEPF3    0xfU
706 #define V_QUEUESPERPAGEPF3(x) ((x) << S_QUEUESPERPAGEPF3)
707 #define G_QUEUESPERPAGEPF3(x) (((x) >> S_QUEUESPERPAGEPF3) & M_QUEUESPERPAGEPF3)
708 
709 #define S_QUEUESPERPAGEPF2    8
710 #define M_QUEUESPERPAGEPF2    0xfU
711 #define V_QUEUESPERPAGEPF2(x) ((x) << S_QUEUESPERPAGEPF2)
712 #define G_QUEUESPERPAGEPF2(x) (((x) >> S_QUEUESPERPAGEPF2) & M_QUEUESPERPAGEPF2)
713 
714 #define S_QUEUESPERPAGEPF1    4
715 #define M_QUEUESPERPAGEPF1    0xfU
716 #define V_QUEUESPERPAGEPF1(x) ((x) << S_QUEUESPERPAGEPF1)
717 #define G_QUEUESPERPAGEPF1(x) (((x) >> S_QUEUESPERPAGEPF1) & M_QUEUESPERPAGEPF1)
718 
719 #define S_QUEUESPERPAGEPF0    0
720 #define M_QUEUESPERPAGEPF0    0xfU
721 #define V_QUEUESPERPAGEPF0(x) ((x) << S_QUEUESPERPAGEPF0)
722 #define G_QUEUESPERPAGEPF0(x) (((x) >> S_QUEUESPERPAGEPF0) & M_QUEUESPERPAGEPF0)
723 
724 #define A_SGE_EGRESS_QUEUES_PER_PAGE_VF 0x1014
725 
726 #define S_QUEUESPERPAGEVFPF7    28
727 #define M_QUEUESPERPAGEVFPF7    0xfU
728 #define V_QUEUESPERPAGEVFPF7(x) ((x) << S_QUEUESPERPAGEVFPF7)
729 #define G_QUEUESPERPAGEVFPF7(x) (((x) >> S_QUEUESPERPAGEVFPF7) & M_QUEUESPERPAGEVFPF7)
730 
731 #define S_QUEUESPERPAGEVFPF6    24
732 #define M_QUEUESPERPAGEVFPF6    0xfU
733 #define V_QUEUESPERPAGEVFPF6(x) ((x) << S_QUEUESPERPAGEVFPF6)
734 #define G_QUEUESPERPAGEVFPF6(x) (((x) >> S_QUEUESPERPAGEVFPF6) & M_QUEUESPERPAGEVFPF6)
735 
736 #define S_QUEUESPERPAGEVFPF5    20
737 #define M_QUEUESPERPAGEVFPF5    0xfU
738 #define V_QUEUESPERPAGEVFPF5(x) ((x) << S_QUEUESPERPAGEVFPF5)
739 #define G_QUEUESPERPAGEVFPF5(x) (((x) >> S_QUEUESPERPAGEVFPF5) & M_QUEUESPERPAGEVFPF5)
740 
741 #define S_QUEUESPERPAGEVFPF4    16
742 #define M_QUEUESPERPAGEVFPF4    0xfU
743 #define V_QUEUESPERPAGEVFPF4(x) ((x) << S_QUEUESPERPAGEVFPF4)
744 #define G_QUEUESPERPAGEVFPF4(x) (((x) >> S_QUEUESPERPAGEVFPF4) & M_QUEUESPERPAGEVFPF4)
745 
746 #define S_QUEUESPERPAGEVFPF3    12
747 #define M_QUEUESPERPAGEVFPF3    0xfU
748 #define V_QUEUESPERPAGEVFPF3(x) ((x) << S_QUEUESPERPAGEVFPF3)
749 #define G_QUEUESPERPAGEVFPF3(x) (((x) >> S_QUEUESPERPAGEVFPF3) & M_QUEUESPERPAGEVFPF3)
750 
751 #define S_QUEUESPERPAGEVFPF2    8
752 #define M_QUEUESPERPAGEVFPF2    0xfU
753 #define V_QUEUESPERPAGEVFPF2(x) ((x) << S_QUEUESPERPAGEVFPF2)
754 #define G_QUEUESPERPAGEVFPF2(x) (((x) >> S_QUEUESPERPAGEVFPF2) & M_QUEUESPERPAGEVFPF2)
755 
756 #define S_QUEUESPERPAGEVFPF1    4
757 #define M_QUEUESPERPAGEVFPF1    0xfU
758 #define V_QUEUESPERPAGEVFPF1(x) ((x) << S_QUEUESPERPAGEVFPF1)
759 #define G_QUEUESPERPAGEVFPF1(x) (((x) >> S_QUEUESPERPAGEVFPF1) & M_QUEUESPERPAGEVFPF1)
760 
761 #define S_QUEUESPERPAGEVFPF0    0
762 #define M_QUEUESPERPAGEVFPF0    0xfU
763 #define V_QUEUESPERPAGEVFPF0(x) ((x) << S_QUEUESPERPAGEVFPF0)
764 #define G_QUEUESPERPAGEVFPF0(x) (((x) >> S_QUEUESPERPAGEVFPF0) & M_QUEUESPERPAGEVFPF0)
765 
766 #define A_SGE_USER_MODE_LIMITS 0x1018
767 
768 #define S_OPCODE_MIN    24
769 #define M_OPCODE_MIN    0xffU
770 #define V_OPCODE_MIN(x) ((x) << S_OPCODE_MIN)
771 #define G_OPCODE_MIN(x) (((x) >> S_OPCODE_MIN) & M_OPCODE_MIN)
772 
773 #define S_OPCODE_MAX    16
774 #define M_OPCODE_MAX    0xffU
775 #define V_OPCODE_MAX(x) ((x) << S_OPCODE_MAX)
776 #define G_OPCODE_MAX(x) (((x) >> S_OPCODE_MAX) & M_OPCODE_MAX)
777 
778 #define S_LENGTH_MIN    8
779 #define M_LENGTH_MIN    0xffU
780 #define V_LENGTH_MIN(x) ((x) << S_LENGTH_MIN)
781 #define G_LENGTH_MIN(x) (((x) >> S_LENGTH_MIN) & M_LENGTH_MIN)
782 
783 #define S_LENGTH_MAX    0
784 #define M_LENGTH_MAX    0xffU
785 #define V_LENGTH_MAX(x) ((x) << S_LENGTH_MAX)
786 #define G_LENGTH_MAX(x) (((x) >> S_LENGTH_MAX) & M_LENGTH_MAX)
787 
788 #define A_SGE_WR_ERROR 0x101c
789 
790 #define S_WR_ERROR_OPCODE    0
791 #define M_WR_ERROR_OPCODE    0xffU
792 #define V_WR_ERROR_OPCODE(x) ((x) << S_WR_ERROR_OPCODE)
793 #define G_WR_ERROR_OPCODE(x) (((x) >> S_WR_ERROR_OPCODE) & M_WR_ERROR_OPCODE)
794 
795 #define A_SGE_PERR_INJECT 0x1020
796 
797 #define S_MEMSEL    1
798 #define M_MEMSEL    0x1fU
799 #define V_MEMSEL(x) ((x) << S_MEMSEL)
800 #define G_MEMSEL(x) (((x) >> S_MEMSEL) & M_MEMSEL)
801 
802 #define S_INJECTDATAERR    0
803 #define V_INJECTDATAERR(x) ((x) << S_INJECTDATAERR)
804 #define F_INJECTDATAERR    V_INJECTDATAERR(1U)
805 
806 #define A_SGE_INT_CAUSE1 0x1024
807 
808 #define S_PERR_FLM_CREDITFIFO    30
809 #define V_PERR_FLM_CREDITFIFO(x) ((x) << S_PERR_FLM_CREDITFIFO)
810 #define F_PERR_FLM_CREDITFIFO    V_PERR_FLM_CREDITFIFO(1U)
811 
812 #define S_PERR_IMSG_HINT_FIFO    29
813 #define V_PERR_IMSG_HINT_FIFO(x) ((x) << S_PERR_IMSG_HINT_FIFO)
814 #define F_PERR_IMSG_HINT_FIFO    V_PERR_IMSG_HINT_FIFO(1U)
815 
816 #define S_PERR_MC_PC    28
817 #define V_PERR_MC_PC(x) ((x) << S_PERR_MC_PC)
818 #define F_PERR_MC_PC    V_PERR_MC_PC(1U)
819 
820 #define S_PERR_MC_IGR_CTXT    27
821 #define V_PERR_MC_IGR_CTXT(x) ((x) << S_PERR_MC_IGR_CTXT)
822 #define F_PERR_MC_IGR_CTXT    V_PERR_MC_IGR_CTXT(1U)
823 
824 #define S_PERR_MC_EGR_CTXT    26
825 #define V_PERR_MC_EGR_CTXT(x) ((x) << S_PERR_MC_EGR_CTXT)
826 #define F_PERR_MC_EGR_CTXT    V_PERR_MC_EGR_CTXT(1U)
827 
828 #define S_PERR_MC_FLM    25
829 #define V_PERR_MC_FLM(x) ((x) << S_PERR_MC_FLM)
830 #define F_PERR_MC_FLM    V_PERR_MC_FLM(1U)
831 
832 #define S_PERR_PC_MCTAG    24
833 #define V_PERR_PC_MCTAG(x) ((x) << S_PERR_PC_MCTAG)
834 #define F_PERR_PC_MCTAG    V_PERR_PC_MCTAG(1U)
835 
836 #define S_PERR_PC_CHPI_RSP1    23
837 #define V_PERR_PC_CHPI_RSP1(x) ((x) << S_PERR_PC_CHPI_RSP1)
838 #define F_PERR_PC_CHPI_RSP1    V_PERR_PC_CHPI_RSP1(1U)
839 
840 #define S_PERR_PC_CHPI_RSP0    22
841 #define V_PERR_PC_CHPI_RSP0(x) ((x) << S_PERR_PC_CHPI_RSP0)
842 #define F_PERR_PC_CHPI_RSP0    V_PERR_PC_CHPI_RSP0(1U)
843 
844 #define S_PERR_DBP_PC_RSP_FIFO3    21
845 #define V_PERR_DBP_PC_RSP_FIFO3(x) ((x) << S_PERR_DBP_PC_RSP_FIFO3)
846 #define F_PERR_DBP_PC_RSP_FIFO3    V_PERR_DBP_PC_RSP_FIFO3(1U)
847 
848 #define S_PERR_DBP_PC_RSP_FIFO2    20
849 #define V_PERR_DBP_PC_RSP_FIFO2(x) ((x) << S_PERR_DBP_PC_RSP_FIFO2)
850 #define F_PERR_DBP_PC_RSP_FIFO2    V_PERR_DBP_PC_RSP_FIFO2(1U)
851 
852 #define S_PERR_DBP_PC_RSP_FIFO1    19
853 #define V_PERR_DBP_PC_RSP_FIFO1(x) ((x) << S_PERR_DBP_PC_RSP_FIFO1)
854 #define F_PERR_DBP_PC_RSP_FIFO1    V_PERR_DBP_PC_RSP_FIFO1(1U)
855 
856 #define S_PERR_DBP_PC_RSP_FIFO0    18
857 #define V_PERR_DBP_PC_RSP_FIFO0(x) ((x) << S_PERR_DBP_PC_RSP_FIFO0)
858 #define F_PERR_DBP_PC_RSP_FIFO0    V_PERR_DBP_PC_RSP_FIFO0(1U)
859 
860 #define S_PERR_DMARBT    17
861 #define V_PERR_DMARBT(x) ((x) << S_PERR_DMARBT)
862 #define F_PERR_DMARBT    V_PERR_DMARBT(1U)
863 
864 #define S_PERR_FLM_DBPFIFO    16
865 #define V_PERR_FLM_DBPFIFO(x) ((x) << S_PERR_FLM_DBPFIFO)
866 #define F_PERR_FLM_DBPFIFO    V_PERR_FLM_DBPFIFO(1U)
867 
868 #define S_PERR_FLM_MCREQ_FIFO    15
869 #define V_PERR_FLM_MCREQ_FIFO(x) ((x) << S_PERR_FLM_MCREQ_FIFO)
870 #define F_PERR_FLM_MCREQ_FIFO    V_PERR_FLM_MCREQ_FIFO(1U)
871 
872 #define S_PERR_FLM_HINTFIFO    14
873 #define V_PERR_FLM_HINTFIFO(x) ((x) << S_PERR_FLM_HINTFIFO)
874 #define F_PERR_FLM_HINTFIFO    V_PERR_FLM_HINTFIFO(1U)
875 
876 #define S_PERR_ALIGN_CTL_FIFO3    13
877 #define V_PERR_ALIGN_CTL_FIFO3(x) ((x) << S_PERR_ALIGN_CTL_FIFO3)
878 #define F_PERR_ALIGN_CTL_FIFO3    V_PERR_ALIGN_CTL_FIFO3(1U)
879 
880 #define S_PERR_ALIGN_CTL_FIFO2    12
881 #define V_PERR_ALIGN_CTL_FIFO2(x) ((x) << S_PERR_ALIGN_CTL_FIFO2)
882 #define F_PERR_ALIGN_CTL_FIFO2    V_PERR_ALIGN_CTL_FIFO2(1U)
883 
884 #define S_PERR_ALIGN_CTL_FIFO1    11
885 #define V_PERR_ALIGN_CTL_FIFO1(x) ((x) << S_PERR_ALIGN_CTL_FIFO1)
886 #define F_PERR_ALIGN_CTL_FIFO1    V_PERR_ALIGN_CTL_FIFO1(1U)
887 
888 #define S_PERR_ALIGN_CTL_FIFO0    10
889 #define V_PERR_ALIGN_CTL_FIFO0(x) ((x) << S_PERR_ALIGN_CTL_FIFO0)
890 #define F_PERR_ALIGN_CTL_FIFO0    V_PERR_ALIGN_CTL_FIFO0(1U)
891 
892 #define S_PERR_EDMA_FIFO3    9
893 #define V_PERR_EDMA_FIFO3(x) ((x) << S_PERR_EDMA_FIFO3)
894 #define F_PERR_EDMA_FIFO3    V_PERR_EDMA_FIFO3(1U)
895 
896 #define S_PERR_EDMA_FIFO2    8
897 #define V_PERR_EDMA_FIFO2(x) ((x) << S_PERR_EDMA_FIFO2)
898 #define F_PERR_EDMA_FIFO2    V_PERR_EDMA_FIFO2(1U)
899 
900 #define S_PERR_EDMA_FIFO1    7
901 #define V_PERR_EDMA_FIFO1(x) ((x) << S_PERR_EDMA_FIFO1)
902 #define F_PERR_EDMA_FIFO1    V_PERR_EDMA_FIFO1(1U)
903 
904 #define S_PERR_EDMA_FIFO0    6
905 #define V_PERR_EDMA_FIFO0(x) ((x) << S_PERR_EDMA_FIFO0)
906 #define F_PERR_EDMA_FIFO0    V_PERR_EDMA_FIFO0(1U)
907 
908 #define S_PERR_PD_FIFO3    5
909 #define V_PERR_PD_FIFO3(x) ((x) << S_PERR_PD_FIFO3)
910 #define F_PERR_PD_FIFO3    V_PERR_PD_FIFO3(1U)
911 
912 #define S_PERR_PD_FIFO2    4
913 #define V_PERR_PD_FIFO2(x) ((x) << S_PERR_PD_FIFO2)
914 #define F_PERR_PD_FIFO2    V_PERR_PD_FIFO2(1U)
915 
916 #define S_PERR_PD_FIFO1    3
917 #define V_PERR_PD_FIFO1(x) ((x) << S_PERR_PD_FIFO1)
918 #define F_PERR_PD_FIFO1    V_PERR_PD_FIFO1(1U)
919 
920 #define S_PERR_PD_FIFO0    2
921 #define V_PERR_PD_FIFO0(x) ((x) << S_PERR_PD_FIFO0)
922 #define F_PERR_PD_FIFO0    V_PERR_PD_FIFO0(1U)
923 
924 #define S_PERR_ING_CTXT_MIFRSP    1
925 #define V_PERR_ING_CTXT_MIFRSP(x) ((x) << S_PERR_ING_CTXT_MIFRSP)
926 #define F_PERR_ING_CTXT_MIFRSP    V_PERR_ING_CTXT_MIFRSP(1U)
927 
928 #define S_PERR_EGR_CTXT_MIFRSP    0
929 #define V_PERR_EGR_CTXT_MIFRSP(x) ((x) << S_PERR_EGR_CTXT_MIFRSP)
930 #define F_PERR_EGR_CTXT_MIFRSP    V_PERR_EGR_CTXT_MIFRSP(1U)
931 
932 #define S_PERR_PC_CHPI_RSP2    31
933 #define V_PERR_PC_CHPI_RSP2(x) ((x) << S_PERR_PC_CHPI_RSP2)
934 #define F_PERR_PC_CHPI_RSP2    V_PERR_PC_CHPI_RSP2(1U)
935 
936 #define S_PERR_PC_RSP    23
937 #define V_PERR_PC_RSP(x) ((x) << S_PERR_PC_RSP)
938 #define F_PERR_PC_RSP    V_PERR_PC_RSP(1U)
939 
940 #define S_PERR_PC_REQ    22
941 #define V_PERR_PC_REQ(x) ((x) << S_PERR_PC_REQ)
942 #define F_PERR_PC_REQ    V_PERR_PC_REQ(1U)
943 
944 #define A_SGE_INT_ENABLE1 0x1028
945 #define A_SGE_PERR_ENABLE1 0x102c
946 #define A_SGE_INT_CAUSE2 0x1030
947 
948 #define S_PERR_HINT_DELAY_FIFO1    30
949 #define V_PERR_HINT_DELAY_FIFO1(x) ((x) << S_PERR_HINT_DELAY_FIFO1)
950 #define F_PERR_HINT_DELAY_FIFO1    V_PERR_HINT_DELAY_FIFO1(1U)
951 
952 #define S_PERR_HINT_DELAY_FIFO0    29
953 #define V_PERR_HINT_DELAY_FIFO0(x) ((x) << S_PERR_HINT_DELAY_FIFO0)
954 #define F_PERR_HINT_DELAY_FIFO0    V_PERR_HINT_DELAY_FIFO0(1U)
955 
956 #define S_PERR_IMSG_PD_FIFO    28
957 #define V_PERR_IMSG_PD_FIFO(x) ((x) << S_PERR_IMSG_PD_FIFO)
958 #define F_PERR_IMSG_PD_FIFO    V_PERR_IMSG_PD_FIFO(1U)
959 
960 #define S_PERR_ULPTX_FIFO1    27
961 #define V_PERR_ULPTX_FIFO1(x) ((x) << S_PERR_ULPTX_FIFO1)
962 #define F_PERR_ULPTX_FIFO1    V_PERR_ULPTX_FIFO1(1U)
963 
964 #define S_PERR_ULPTX_FIFO0    26
965 #define V_PERR_ULPTX_FIFO0(x) ((x) << S_PERR_ULPTX_FIFO0)
966 #define F_PERR_ULPTX_FIFO0    V_PERR_ULPTX_FIFO0(1U)
967 
968 #define S_PERR_IDMA2IMSG_FIFO1    25
969 #define V_PERR_IDMA2IMSG_FIFO1(x) ((x) << S_PERR_IDMA2IMSG_FIFO1)
970 #define F_PERR_IDMA2IMSG_FIFO1    V_PERR_IDMA2IMSG_FIFO1(1U)
971 
972 #define S_PERR_IDMA2IMSG_FIFO0    24
973 #define V_PERR_IDMA2IMSG_FIFO0(x) ((x) << S_PERR_IDMA2IMSG_FIFO0)
974 #define F_PERR_IDMA2IMSG_FIFO0    V_PERR_IDMA2IMSG_FIFO0(1U)
975 
976 #define S_PERR_HEADERSPLIT_FIFO1    23
977 #define V_PERR_HEADERSPLIT_FIFO1(x) ((x) << S_PERR_HEADERSPLIT_FIFO1)
978 #define F_PERR_HEADERSPLIT_FIFO1    V_PERR_HEADERSPLIT_FIFO1(1U)
979 
980 #define S_PERR_HEADERSPLIT_FIFO0    22
981 #define V_PERR_HEADERSPLIT_FIFO0(x) ((x) << S_PERR_HEADERSPLIT_FIFO0)
982 #define F_PERR_HEADERSPLIT_FIFO0    V_PERR_HEADERSPLIT_FIFO0(1U)
983 
984 #define S_PERR_ESWITCH_FIFO3    21
985 #define V_PERR_ESWITCH_FIFO3(x) ((x) << S_PERR_ESWITCH_FIFO3)
986 #define F_PERR_ESWITCH_FIFO3    V_PERR_ESWITCH_FIFO3(1U)
987 
988 #define S_PERR_ESWITCH_FIFO2    20
989 #define V_PERR_ESWITCH_FIFO2(x) ((x) << S_PERR_ESWITCH_FIFO2)
990 #define F_PERR_ESWITCH_FIFO2    V_PERR_ESWITCH_FIFO2(1U)
991 
992 #define S_PERR_ESWITCH_FIFO1    19
993 #define V_PERR_ESWITCH_FIFO1(x) ((x) << S_PERR_ESWITCH_FIFO1)
994 #define F_PERR_ESWITCH_FIFO1    V_PERR_ESWITCH_FIFO1(1U)
995 
996 #define S_PERR_ESWITCH_FIFO0    18
997 #define V_PERR_ESWITCH_FIFO0(x) ((x) << S_PERR_ESWITCH_FIFO0)
998 #define F_PERR_ESWITCH_FIFO0    V_PERR_ESWITCH_FIFO0(1U)
999 
1000 #define S_PERR_PC_DBP1    17
1001 #define V_PERR_PC_DBP1(x) ((x) << S_PERR_PC_DBP1)
1002 #define F_PERR_PC_DBP1    V_PERR_PC_DBP1(1U)
1003 
1004 #define S_PERR_PC_DBP0    16
1005 #define V_PERR_PC_DBP0(x) ((x) << S_PERR_PC_DBP0)
1006 #define F_PERR_PC_DBP0    V_PERR_PC_DBP0(1U)
1007 
1008 #define S_PERR_IMSG_OB_FIFO    15
1009 #define V_PERR_IMSG_OB_FIFO(x) ((x) << S_PERR_IMSG_OB_FIFO)
1010 #define F_PERR_IMSG_OB_FIFO    V_PERR_IMSG_OB_FIFO(1U)
1011 
1012 #define S_PERR_CONM_SRAM    14
1013 #define V_PERR_CONM_SRAM(x) ((x) << S_PERR_CONM_SRAM)
1014 #define F_PERR_CONM_SRAM    V_PERR_CONM_SRAM(1U)
1015 
1016 #define S_PERR_PC_MC_RSP    13
1017 #define V_PERR_PC_MC_RSP(x) ((x) << S_PERR_PC_MC_RSP)
1018 #define F_PERR_PC_MC_RSP    V_PERR_PC_MC_RSP(1U)
1019 
1020 #define S_PERR_ISW_IDMA0_FIFO    12
1021 #define V_PERR_ISW_IDMA0_FIFO(x) ((x) << S_PERR_ISW_IDMA0_FIFO)
1022 #define F_PERR_ISW_IDMA0_FIFO    V_PERR_ISW_IDMA0_FIFO(1U)
1023 
1024 #define S_PERR_ISW_IDMA1_FIFO    11
1025 #define V_PERR_ISW_IDMA1_FIFO(x) ((x) << S_PERR_ISW_IDMA1_FIFO)
1026 #define F_PERR_ISW_IDMA1_FIFO    V_PERR_ISW_IDMA1_FIFO(1U)
1027 
1028 #define S_PERR_ISW_DBP_FIFO    10
1029 #define V_PERR_ISW_DBP_FIFO(x) ((x) << S_PERR_ISW_DBP_FIFO)
1030 #define F_PERR_ISW_DBP_FIFO    V_PERR_ISW_DBP_FIFO(1U)
1031 
1032 #define S_PERR_ISW_GTS_FIFO    9
1033 #define V_PERR_ISW_GTS_FIFO(x) ((x) << S_PERR_ISW_GTS_FIFO)
1034 #define F_PERR_ISW_GTS_FIFO    V_PERR_ISW_GTS_FIFO(1U)
1035 
1036 #define S_PERR_ITP_EVR    8
1037 #define V_PERR_ITP_EVR(x) ((x) << S_PERR_ITP_EVR)
1038 #define F_PERR_ITP_EVR    V_PERR_ITP_EVR(1U)
1039 
1040 #define S_PERR_FLM_CNTXMEM    7
1041 #define V_PERR_FLM_CNTXMEM(x) ((x) << S_PERR_FLM_CNTXMEM)
1042 #define F_PERR_FLM_CNTXMEM    V_PERR_FLM_CNTXMEM(1U)
1043 
1044 #define S_PERR_FLM_L1CACHE    6
1045 #define V_PERR_FLM_L1CACHE(x) ((x) << S_PERR_FLM_L1CACHE)
1046 #define F_PERR_FLM_L1CACHE    V_PERR_FLM_L1CACHE(1U)
1047 
1048 #define S_PERR_DBP_HINT_FIFO    5
1049 #define V_PERR_DBP_HINT_FIFO(x) ((x) << S_PERR_DBP_HINT_FIFO)
1050 #define F_PERR_DBP_HINT_FIFO    V_PERR_DBP_HINT_FIFO(1U)
1051 
1052 #define S_PERR_DBP_HP_FIFO    4
1053 #define V_PERR_DBP_HP_FIFO(x) ((x) << S_PERR_DBP_HP_FIFO)
1054 #define F_PERR_DBP_HP_FIFO    V_PERR_DBP_HP_FIFO(1U)
1055 
1056 #define S_PERR_DBP_LP_FIFO    3
1057 #define V_PERR_DBP_LP_FIFO(x) ((x) << S_PERR_DBP_LP_FIFO)
1058 #define F_PERR_DBP_LP_FIFO    V_PERR_DBP_LP_FIFO(1U)
1059 
1060 #define S_PERR_ING_CTXT_CACHE    2
1061 #define V_PERR_ING_CTXT_CACHE(x) ((x) << S_PERR_ING_CTXT_CACHE)
1062 #define F_PERR_ING_CTXT_CACHE    V_PERR_ING_CTXT_CACHE(1U)
1063 
1064 #define S_PERR_EGR_CTXT_CACHE    1
1065 #define V_PERR_EGR_CTXT_CACHE(x) ((x) << S_PERR_EGR_CTXT_CACHE)
1066 #define F_PERR_EGR_CTXT_CACHE    V_PERR_EGR_CTXT_CACHE(1U)
1067 
1068 #define S_PERR_BASE_SIZE    0
1069 #define V_PERR_BASE_SIZE(x) ((x) << S_PERR_BASE_SIZE)
1070 #define F_PERR_BASE_SIZE    V_PERR_BASE_SIZE(1U)
1071 
1072 #define S_PERR_DBP_HINT_FL_FIFO    24
1073 #define V_PERR_DBP_HINT_FL_FIFO(x) ((x) << S_PERR_DBP_HINT_FL_FIFO)
1074 #define F_PERR_DBP_HINT_FL_FIFO    V_PERR_DBP_HINT_FL_FIFO(1U)
1075 
1076 #define S_PERR_EGR_DBP_TX_COAL    23
1077 #define V_PERR_EGR_DBP_TX_COAL(x) ((x) << S_PERR_EGR_DBP_TX_COAL)
1078 #define F_PERR_EGR_DBP_TX_COAL    V_PERR_EGR_DBP_TX_COAL(1U)
1079 
1080 #define S_PERR_DBP_FL_FIFO    22
1081 #define V_PERR_DBP_FL_FIFO(x) ((x) << S_PERR_DBP_FL_FIFO)
1082 #define F_PERR_DBP_FL_FIFO    V_PERR_DBP_FL_FIFO(1U)
1083 
1084 #define S_PERR_PC_DBP2    15
1085 #define V_PERR_PC_DBP2(x) ((x) << S_PERR_PC_DBP2)
1086 #define F_PERR_PC_DBP2    V_PERR_PC_DBP2(1U)
1087 
1088 #define S_DEQ_LL_PERR    21
1089 #define V_DEQ_LL_PERR(x) ((x) << S_DEQ_LL_PERR)
1090 #define F_DEQ_LL_PERR    V_DEQ_LL_PERR(1U)
1091 
1092 #define S_ENQ_PERR    20
1093 #define V_ENQ_PERR(x) ((x) << S_ENQ_PERR)
1094 #define F_ENQ_PERR    V_ENQ_PERR(1U)
1095 
1096 #define S_DEQ_OUT_PERR    19
1097 #define V_DEQ_OUT_PERR(x) ((x) << S_DEQ_OUT_PERR)
1098 #define F_DEQ_OUT_PERR    V_DEQ_OUT_PERR(1U)
1099 
1100 #define S_BUF_PERR    18
1101 #define V_BUF_PERR(x) ((x) << S_BUF_PERR)
1102 #define F_BUF_PERR    V_BUF_PERR(1U)
1103 
1104 #define S_PERR_DB_FIFO    3
1105 #define V_PERR_DB_FIFO(x) ((x) << S_PERR_DB_FIFO)
1106 #define F_PERR_DB_FIFO    V_PERR_DB_FIFO(1U)
1107 
1108 #define A_SGE_INT_ENABLE2 0x1034
1109 #define A_SGE_PERR_ENABLE2 0x1038
1110 #define A_SGE_INT_CAUSE3 0x103c
1111 
1112 #define S_ERR_FLM_DBP    31
1113 #define V_ERR_FLM_DBP(x) ((x) << S_ERR_FLM_DBP)
1114 #define F_ERR_FLM_DBP    V_ERR_FLM_DBP(1U)
1115 
1116 #define S_ERR_FLM_IDMA1    30
1117 #define V_ERR_FLM_IDMA1(x) ((x) << S_ERR_FLM_IDMA1)
1118 #define F_ERR_FLM_IDMA1    V_ERR_FLM_IDMA1(1U)
1119 
1120 #define S_ERR_FLM_IDMA0    29
1121 #define V_ERR_FLM_IDMA0(x) ((x) << S_ERR_FLM_IDMA0)
1122 #define F_ERR_FLM_IDMA0    V_ERR_FLM_IDMA0(1U)
1123 
1124 #define S_ERR_FLM_HINT    28
1125 #define V_ERR_FLM_HINT(x) ((x) << S_ERR_FLM_HINT)
1126 #define F_ERR_FLM_HINT    V_ERR_FLM_HINT(1U)
1127 
1128 #define S_ERR_PCIE_ERROR3    27
1129 #define V_ERR_PCIE_ERROR3(x) ((x) << S_ERR_PCIE_ERROR3)
1130 #define F_ERR_PCIE_ERROR3    V_ERR_PCIE_ERROR3(1U)
1131 
1132 #define S_ERR_PCIE_ERROR2    26
1133 #define V_ERR_PCIE_ERROR2(x) ((x) << S_ERR_PCIE_ERROR2)
1134 #define F_ERR_PCIE_ERROR2    V_ERR_PCIE_ERROR2(1U)
1135 
1136 #define S_ERR_PCIE_ERROR1    25
1137 #define V_ERR_PCIE_ERROR1(x) ((x) << S_ERR_PCIE_ERROR1)
1138 #define F_ERR_PCIE_ERROR1    V_ERR_PCIE_ERROR1(1U)
1139 
1140 #define S_ERR_PCIE_ERROR0    24
1141 #define V_ERR_PCIE_ERROR0(x) ((x) << S_ERR_PCIE_ERROR0)
1142 #define F_ERR_PCIE_ERROR0    V_ERR_PCIE_ERROR0(1U)
1143 
1144 #define S_ERR_TIMER_ABOVE_MAX_QID    23
1145 #define V_ERR_TIMER_ABOVE_MAX_QID(x) ((x) << S_ERR_TIMER_ABOVE_MAX_QID)
1146 #define F_ERR_TIMER_ABOVE_MAX_QID    V_ERR_TIMER_ABOVE_MAX_QID(1U)
1147 
1148 #define S_ERR_CPL_EXCEED_IQE_SIZE    22
1149 #define V_ERR_CPL_EXCEED_IQE_SIZE(x) ((x) << S_ERR_CPL_EXCEED_IQE_SIZE)
1150 #define F_ERR_CPL_EXCEED_IQE_SIZE    V_ERR_CPL_EXCEED_IQE_SIZE(1U)
1151 
1152 #define S_ERR_INVALID_CIDX_INC    21
1153 #define V_ERR_INVALID_CIDX_INC(x) ((x) << S_ERR_INVALID_CIDX_INC)
1154 #define F_ERR_INVALID_CIDX_INC    V_ERR_INVALID_CIDX_INC(1U)
1155 
1156 #define S_ERR_ITP_TIME_PAUSED    20
1157 #define V_ERR_ITP_TIME_PAUSED(x) ((x) << S_ERR_ITP_TIME_PAUSED)
1158 #define F_ERR_ITP_TIME_PAUSED    V_ERR_ITP_TIME_PAUSED(1U)
1159 
1160 #define S_ERR_CPL_OPCODE_0    19
1161 #define V_ERR_CPL_OPCODE_0(x) ((x) << S_ERR_CPL_OPCODE_0)
1162 #define F_ERR_CPL_OPCODE_0    V_ERR_CPL_OPCODE_0(1U)
1163 
1164 #define S_ERR_DROPPED_DB    18
1165 #define V_ERR_DROPPED_DB(x) ((x) << S_ERR_DROPPED_DB)
1166 #define F_ERR_DROPPED_DB    V_ERR_DROPPED_DB(1U)
1167 
1168 #define S_ERR_DATA_CPL_ON_HIGH_QID1    17
1169 #define V_ERR_DATA_CPL_ON_HIGH_QID1(x) ((x) << S_ERR_DATA_CPL_ON_HIGH_QID1)
1170 #define F_ERR_DATA_CPL_ON_HIGH_QID1    V_ERR_DATA_CPL_ON_HIGH_QID1(1U)
1171 
1172 #define S_ERR_DATA_CPL_ON_HIGH_QID0    16
1173 #define V_ERR_DATA_CPL_ON_HIGH_QID0(x) ((x) << S_ERR_DATA_CPL_ON_HIGH_QID0)
1174 #define F_ERR_DATA_CPL_ON_HIGH_QID0    V_ERR_DATA_CPL_ON_HIGH_QID0(1U)
1175 
1176 #define S_ERR_BAD_DB_PIDX3    15
1177 #define V_ERR_BAD_DB_PIDX3(x) ((x) << S_ERR_BAD_DB_PIDX3)
1178 #define F_ERR_BAD_DB_PIDX3    V_ERR_BAD_DB_PIDX3(1U)
1179 
1180 #define S_ERR_BAD_DB_PIDX2    14
1181 #define V_ERR_BAD_DB_PIDX2(x) ((x) << S_ERR_BAD_DB_PIDX2)
1182 #define F_ERR_BAD_DB_PIDX2    V_ERR_BAD_DB_PIDX2(1U)
1183 
1184 #define S_ERR_BAD_DB_PIDX1    13
1185 #define V_ERR_BAD_DB_PIDX1(x) ((x) << S_ERR_BAD_DB_PIDX1)
1186 #define F_ERR_BAD_DB_PIDX1    V_ERR_BAD_DB_PIDX1(1U)
1187 
1188 #define S_ERR_BAD_DB_PIDX0    12
1189 #define V_ERR_BAD_DB_PIDX0(x) ((x) << S_ERR_BAD_DB_PIDX0)
1190 #define F_ERR_BAD_DB_PIDX0    V_ERR_BAD_DB_PIDX0(1U)
1191 
1192 #define S_ERR_ING_PCIE_CHAN    11
1193 #define V_ERR_ING_PCIE_CHAN(x) ((x) << S_ERR_ING_PCIE_CHAN)
1194 #define F_ERR_ING_PCIE_CHAN    V_ERR_ING_PCIE_CHAN(1U)
1195 
1196 #define S_ERR_ING_CTXT_PRIO    10
1197 #define V_ERR_ING_CTXT_PRIO(x) ((x) << S_ERR_ING_CTXT_PRIO)
1198 #define F_ERR_ING_CTXT_PRIO    V_ERR_ING_CTXT_PRIO(1U)
1199 
1200 #define S_ERR_EGR_CTXT_PRIO    9
1201 #define V_ERR_EGR_CTXT_PRIO(x) ((x) << S_ERR_EGR_CTXT_PRIO)
1202 #define F_ERR_EGR_CTXT_PRIO    V_ERR_EGR_CTXT_PRIO(1U)
1203 
1204 #define S_DBFIFO_HP_INT    8
1205 #define V_DBFIFO_HP_INT(x) ((x) << S_DBFIFO_HP_INT)
1206 #define F_DBFIFO_HP_INT    V_DBFIFO_HP_INT(1U)
1207 
1208 #define S_DBFIFO_LP_INT    7
1209 #define V_DBFIFO_LP_INT(x) ((x) << S_DBFIFO_LP_INT)
1210 #define F_DBFIFO_LP_INT    V_DBFIFO_LP_INT(1U)
1211 
1212 #define S_REG_ADDRESS_ERR    6
1213 #define V_REG_ADDRESS_ERR(x) ((x) << S_REG_ADDRESS_ERR)
1214 #define F_REG_ADDRESS_ERR    V_REG_ADDRESS_ERR(1U)
1215 
1216 #define S_INGRESS_SIZE_ERR    5
1217 #define V_INGRESS_SIZE_ERR(x) ((x) << S_INGRESS_SIZE_ERR)
1218 #define F_INGRESS_SIZE_ERR    V_INGRESS_SIZE_ERR(1U)
1219 
1220 #define S_EGRESS_SIZE_ERR    4
1221 #define V_EGRESS_SIZE_ERR(x) ((x) << S_EGRESS_SIZE_ERR)
1222 #define F_EGRESS_SIZE_ERR    V_EGRESS_SIZE_ERR(1U)
1223 
1224 #define S_ERR_INV_CTXT3    3
1225 #define V_ERR_INV_CTXT3(x) ((x) << S_ERR_INV_CTXT3)
1226 #define F_ERR_INV_CTXT3    V_ERR_INV_CTXT3(1U)
1227 
1228 #define S_ERR_INV_CTXT2    2
1229 #define V_ERR_INV_CTXT2(x) ((x) << S_ERR_INV_CTXT2)
1230 #define F_ERR_INV_CTXT2    V_ERR_INV_CTXT2(1U)
1231 
1232 #define S_ERR_INV_CTXT1    1
1233 #define V_ERR_INV_CTXT1(x) ((x) << S_ERR_INV_CTXT1)
1234 #define F_ERR_INV_CTXT1    V_ERR_INV_CTXT1(1U)
1235 
1236 #define S_ERR_INV_CTXT0    0
1237 #define V_ERR_INV_CTXT0(x) ((x) << S_ERR_INV_CTXT0)
1238 #define F_ERR_INV_CTXT0    V_ERR_INV_CTXT0(1U)
1239 
1240 #define S_DBP_TBUF_FULL    8
1241 #define V_DBP_TBUF_FULL(x) ((x) << S_DBP_TBUF_FULL)
1242 #define F_DBP_TBUF_FULL    V_DBP_TBUF_FULL(1U)
1243 
1244 #define S_FATAL_WRE_LEN    7
1245 #define V_FATAL_WRE_LEN(x) ((x) << S_FATAL_WRE_LEN)
1246 #define F_FATAL_WRE_LEN    V_FATAL_WRE_LEN(1U)
1247 
1248 #define A_SGE_INT_ENABLE3 0x1040
1249 #define A_SGE_FL_BUFFER_SIZE0 0x1044
1250 
1251 #define S_SIZE    4
1252 #define CXGBE_M_SIZE    0xfffffffU
1253 #define V_SIZE(x) ((x) << S_SIZE)
1254 #define G_SIZE(x) (((x) >> S_SIZE) & CXGBE_M_SIZE)
1255 
1256 #define S_T6_SIZE    4
1257 #define M_T6_SIZE    0xfffffU
1258 #define V_T6_SIZE(x) ((x) << S_T6_SIZE)
1259 #define G_T6_SIZE(x) (((x) >> S_T6_SIZE) & M_T6_SIZE)
1260 
1261 #define A_SGE_FL_BUFFER_SIZE1 0x1048
1262 
1263 #define S_T6_SIZE    4
1264 #define M_T6_SIZE    0xfffffU
1265 #define V_T6_SIZE(x) ((x) << S_T6_SIZE)
1266 #define G_T6_SIZE(x) (((x) >> S_T6_SIZE) & M_T6_SIZE)
1267 
1268 #define A_SGE_FL_BUFFER_SIZE2 0x104c
1269 
1270 #define S_T6_SIZE    4
1271 #define M_T6_SIZE    0xfffffU
1272 #define V_T6_SIZE(x) ((x) << S_T6_SIZE)
1273 #define G_T6_SIZE(x) (((x) >> S_T6_SIZE) & M_T6_SIZE)
1274 
1275 #define A_SGE_FL_BUFFER_SIZE3 0x1050
1276 
1277 #define S_T6_SIZE    4
1278 #define M_T6_SIZE    0xfffffU
1279 #define V_T6_SIZE(x) ((x) << S_T6_SIZE)
1280 #define G_T6_SIZE(x) (((x) >> S_T6_SIZE) & M_T6_SIZE)
1281 
1282 #define A_SGE_FL_BUFFER_SIZE4 0x1054
1283 
1284 #define S_T6_SIZE    4
1285 #define M_T6_SIZE    0xfffffU
1286 #define V_T6_SIZE(x) ((x) << S_T6_SIZE)
1287 #define G_T6_SIZE(x) (((x) >> S_T6_SIZE) & M_T6_SIZE)
1288 
1289 #define A_SGE_FL_BUFFER_SIZE5 0x1058
1290 
1291 #define S_T6_SIZE    4
1292 #define M_T6_SIZE    0xfffffU
1293 #define V_T6_SIZE(x) ((x) << S_T6_SIZE)
1294 #define G_T6_SIZE(x) (((x) >> S_T6_SIZE) & M_T6_SIZE)
1295 
1296 #define A_SGE_FL_BUFFER_SIZE6 0x105c
1297 
1298 #define S_T6_SIZE    4
1299 #define M_T6_SIZE    0xfffffU
1300 #define V_T6_SIZE(x) ((x) << S_T6_SIZE)
1301 #define G_T6_SIZE(x) (((x) >> S_T6_SIZE) & M_T6_SIZE)
1302 
1303 #define A_SGE_FL_BUFFER_SIZE7 0x1060
1304 
1305 #define S_T6_SIZE    4
1306 #define M_T6_SIZE    0xfffffU
1307 #define V_T6_SIZE(x) ((x) << S_T6_SIZE)
1308 #define G_T6_SIZE(x) (((x) >> S_T6_SIZE) & M_T6_SIZE)
1309 
1310 #define A_SGE_FL_BUFFER_SIZE8 0x1064
1311 
1312 #define S_T6_SIZE    4
1313 #define M_T6_SIZE    0xfffffU
1314 #define V_T6_SIZE(x) ((x) << S_T6_SIZE)
1315 #define G_T6_SIZE(x) (((x) >> S_T6_SIZE) & M_T6_SIZE)
1316 
1317 #define A_SGE_FL_BUFFER_SIZE9 0x1068
1318 
1319 #define S_T6_SIZE    4
1320 #define M_T6_SIZE    0xfffffU
1321 #define V_T6_SIZE(x) ((x) << S_T6_SIZE)
1322 #define G_T6_SIZE(x) (((x) >> S_T6_SIZE) & M_T6_SIZE)
1323 
1324 #define A_SGE_FL_BUFFER_SIZE10 0x106c
1325 
1326 #define S_T6_SIZE    4
1327 #define M_T6_SIZE    0xfffffU
1328 #define V_T6_SIZE(x) ((x) << S_T6_SIZE)
1329 #define G_T6_SIZE(x) (((x) >> S_T6_SIZE) & M_T6_SIZE)
1330 
1331 #define A_SGE_FL_BUFFER_SIZE11 0x1070
1332 
1333 #define S_T6_SIZE    4
1334 #define M_T6_SIZE    0xfffffU
1335 #define V_T6_SIZE(x) ((x) << S_T6_SIZE)
1336 #define G_T6_SIZE(x) (((x) >> S_T6_SIZE) & M_T6_SIZE)
1337 
1338 #define A_SGE_FL_BUFFER_SIZE12 0x1074
1339 
1340 #define S_T6_SIZE    4
1341 #define M_T6_SIZE    0xfffffU
1342 #define V_T6_SIZE(x) ((x) << S_T6_SIZE)
1343 #define G_T6_SIZE(x) (((x) >> S_T6_SIZE) & M_T6_SIZE)
1344 
1345 #define A_SGE_FL_BUFFER_SIZE13 0x1078
1346 
1347 #define S_T6_SIZE    4
1348 #define M_T6_SIZE    0xfffffU
1349 #define V_T6_SIZE(x) ((x) << S_T6_SIZE)
1350 #define G_T6_SIZE(x) (((x) >> S_T6_SIZE) & M_T6_SIZE)
1351 
1352 #define A_SGE_FL_BUFFER_SIZE14 0x107c
1353 
1354 #define S_T6_SIZE    4
1355 #define M_T6_SIZE    0xfffffU
1356 #define V_T6_SIZE(x) ((x) << S_T6_SIZE)
1357 #define G_T6_SIZE(x) (((x) >> S_T6_SIZE) & M_T6_SIZE)
1358 
1359 #define A_SGE_FL_BUFFER_SIZE15 0x1080
1360 
1361 #define S_T6_SIZE    4
1362 #define M_T6_SIZE    0xfffffU
1363 #define V_T6_SIZE(x) ((x) << S_T6_SIZE)
1364 #define G_T6_SIZE(x) (((x) >> S_T6_SIZE) & M_T6_SIZE)
1365 
1366 #define A_SGE_DBQ_CTXT_BADDR 0x1084
1367 
1368 #define S_BASEADDR    3
1369 #define M_BASEADDR    0x1fffffffU
1370 #define V_BASEADDR(x) ((x) << S_BASEADDR)
1371 #define G_BASEADDR(x) (((x) >> S_BASEADDR) & M_BASEADDR)
1372 
1373 #define A_SGE_IMSG_CTXT_BADDR 0x1088
1374 #define A_SGE_FLM_CACHE_BADDR 0x108c
1375 #define A_SGE_FLM_CFG 0x1090
1376 
1377 #define S_OPMODE    26
1378 #define M_OPMODE    0x3fU
1379 #define V_OPMODE(x) ((x) << S_OPMODE)
1380 #define G_OPMODE(x) (((x) >> S_OPMODE) & M_OPMODE)
1381 
1382 #define S_NOHDR    18
1383 #define V_NOHDR(x) ((x) << S_NOHDR)
1384 #define F_NOHDR    V_NOHDR(1U)
1385 
1386 #define S_CACHEPTRCNT    16
1387 #define M_CACHEPTRCNT    0x3U
1388 #define V_CACHEPTRCNT(x) ((x) << S_CACHEPTRCNT)
1389 #define G_CACHEPTRCNT(x) (((x) >> S_CACHEPTRCNT) & M_CACHEPTRCNT)
1390 
1391 #define S_EDRAMPTRCNT    14
1392 #define M_EDRAMPTRCNT    0x3U
1393 #define V_EDRAMPTRCNT(x) ((x) << S_EDRAMPTRCNT)
1394 #define G_EDRAMPTRCNT(x) (((x) >> S_EDRAMPTRCNT) & M_EDRAMPTRCNT)
1395 
1396 #define S_HDRSTARTFLQ    11
1397 #define M_HDRSTARTFLQ    0x7U
1398 #define V_HDRSTARTFLQ(x) ((x) << S_HDRSTARTFLQ)
1399 #define G_HDRSTARTFLQ(x) (((x) >> S_HDRSTARTFLQ) & M_HDRSTARTFLQ)
1400 
1401 #define S_FETCHTHRESH    6
1402 #define M_FETCHTHRESH    0x1fU
1403 #define V_FETCHTHRESH(x) ((x) << S_FETCHTHRESH)
1404 #define G_FETCHTHRESH(x) (((x) >> S_FETCHTHRESH) & M_FETCHTHRESH)
1405 
1406 #define S_CREDITCNT    4
1407 #define M_CREDITCNT    0x3U
1408 #define V_CREDITCNT(x) ((x) << S_CREDITCNT)
1409 #define G_CREDITCNT(x) (((x) >> S_CREDITCNT) & M_CREDITCNT)
1410 
1411 #define S_NOEDRAM    0
1412 #define V_NOEDRAM(x) ((x) << S_NOEDRAM)
1413 #define F_NOEDRAM    V_NOEDRAM(1U)
1414 
1415 #define S_CREDITCNTPACKING    2
1416 #define M_CREDITCNTPACKING    0x3U
1417 #define V_CREDITCNTPACKING(x) ((x) << S_CREDITCNTPACKING)
1418 #define G_CREDITCNTPACKING(x) (((x) >> S_CREDITCNTPACKING) & M_CREDITCNTPACKING)
1419 
1420 #define S_NULLPTR    20
1421 #define M_NULLPTR    0xfU
1422 #define V_NULLPTR(x) ((x) << S_NULLPTR)
1423 #define G_NULLPTR(x) (((x) >> S_NULLPTR) & M_NULLPTR)
1424 
1425 #define S_NULLPTREN    19
1426 #define V_NULLPTREN(x) ((x) << S_NULLPTREN)
1427 #define F_NULLPTREN    V_NULLPTREN(1U)
1428 
1429 #define A_SGE_CONM_CTRL 0x1094
1430 
1431 #define S_EGRTHRESHOLD    8
1432 #define M_EGRTHRESHOLD    0x3fU
1433 #define V_EGRTHRESHOLD(x) ((x) << S_EGRTHRESHOLD)
1434 #define G_EGRTHRESHOLD(x) (((x) >> S_EGRTHRESHOLD) & M_EGRTHRESHOLD)
1435 
1436 #define S_INGTHRESHOLD    2
1437 #define M_INGTHRESHOLD    0x3fU
1438 #define V_INGTHRESHOLD(x) ((x) << S_INGTHRESHOLD)
1439 #define G_INGTHRESHOLD(x) (((x) >> S_INGTHRESHOLD) & M_INGTHRESHOLD)
1440 
1441 #define S_MPS_ENABLE    1
1442 #define V_MPS_ENABLE(x) ((x) << S_MPS_ENABLE)
1443 #define F_MPS_ENABLE    V_MPS_ENABLE(1U)
1444 
1445 #define S_TP_ENABLE    0
1446 #define V_TP_ENABLE(x) ((x) << S_TP_ENABLE)
1447 #define F_TP_ENABLE    V_TP_ENABLE(1U)
1448 
1449 #define S_EGRTHRESHOLDPACKING    14
1450 #define M_EGRTHRESHOLDPACKING    0x3fU
1451 #define V_EGRTHRESHOLDPACKING(x) ((x) << S_EGRTHRESHOLDPACKING)
1452 #define G_EGRTHRESHOLDPACKING(x) (((x) >> S_EGRTHRESHOLDPACKING) & M_EGRTHRESHOLDPACKING)
1453 
1454 #define S_T6_EGRTHRESHOLDPACKING    16
1455 #define M_T6_EGRTHRESHOLDPACKING    0xffU
1456 #define V_T6_EGRTHRESHOLDPACKING(x) ((x) << S_T6_EGRTHRESHOLDPACKING)
1457 #define G_T6_EGRTHRESHOLDPACKING(x) (((x) >> S_T6_EGRTHRESHOLDPACKING) & M_T6_EGRTHRESHOLDPACKING)
1458 
1459 #define S_T6_EGRTHRESHOLD    8
1460 #define M_T6_EGRTHRESHOLD    0xffU
1461 #define V_T6_EGRTHRESHOLD(x) ((x) << S_T6_EGRTHRESHOLD)
1462 #define G_T6_EGRTHRESHOLD(x) (((x) >> S_T6_EGRTHRESHOLD) & M_T6_EGRTHRESHOLD)
1463 
1464 #define A_SGE_TIMESTAMP_LO 0x1098
1465 #define A_SGE_TIMESTAMP_HI 0x109c
1466 
1467 #define S_TSOP    28
1468 #define M_TSOP    0x3U
1469 #define V_TSOP(x) ((x) << S_TSOP)
1470 #define G_TSOP(x) (((x) >> S_TSOP) & M_TSOP)
1471 
1472 #define S_TSVAL    0
1473 #define M_TSVAL    0xfffffffU
1474 #define V_TSVAL(x) ((x) << S_TSVAL)
1475 #define G_TSVAL(x) (((x) >> S_TSVAL) & M_TSVAL)
1476 
1477 #define A_SGE_INGRESS_RX_THRESHOLD 0x10a0
1478 
1479 #define S_THRESHOLD_0    24
1480 #define M_THRESHOLD_0    0x3fU
1481 #define V_THRESHOLD_0(x) ((x) << S_THRESHOLD_0)
1482 #define G_THRESHOLD_0(x) (((x) >> S_THRESHOLD_0) & M_THRESHOLD_0)
1483 
1484 #define S_THRESHOLD_1    16
1485 #define M_THRESHOLD_1    0x3fU
1486 #define V_THRESHOLD_1(x) ((x) << S_THRESHOLD_1)
1487 #define G_THRESHOLD_1(x) (((x) >> S_THRESHOLD_1) & M_THRESHOLD_1)
1488 
1489 #define S_THRESHOLD_2    8
1490 #define M_THRESHOLD_2    0x3fU
1491 #define V_THRESHOLD_2(x) ((x) << S_THRESHOLD_2)
1492 #define G_THRESHOLD_2(x) (((x) >> S_THRESHOLD_2) & M_THRESHOLD_2)
1493 
1494 #define S_THRESHOLD_3    0
1495 #define M_THRESHOLD_3    0x3fU
1496 #define V_THRESHOLD_3(x) ((x) << S_THRESHOLD_3)
1497 #define G_THRESHOLD_3(x) (((x) >> S_THRESHOLD_3) & M_THRESHOLD_3)
1498 
1499 #define A_SGE_DBFIFO_STATUS 0x10a4
1500 
1501 #define S_HP_INT_THRESH    28
1502 #define M_HP_INT_THRESH    0xfU
1503 #define V_HP_INT_THRESH(x) ((x) << S_HP_INT_THRESH)
1504 #define G_HP_INT_THRESH(x) (((x) >> S_HP_INT_THRESH) & M_HP_INT_THRESH)
1505 
1506 #define S_HP_COUNT    16
1507 #define M_HP_COUNT    0x7ffU
1508 #define V_HP_COUNT(x) ((x) << S_HP_COUNT)
1509 #define G_HP_COUNT(x) (((x) >> S_HP_COUNT) & M_HP_COUNT)
1510 
1511 #define S_LP_INT_THRESH    12
1512 #define M_LP_INT_THRESH    0xfU
1513 #define V_LP_INT_THRESH(x) ((x) << S_LP_INT_THRESH)
1514 #define G_LP_INT_THRESH(x) (((x) >> S_LP_INT_THRESH) & M_LP_INT_THRESH)
1515 
1516 #define S_LP_COUNT    0
1517 #define M_LP_COUNT    0x7ffU
1518 #define V_LP_COUNT(x) ((x) << S_LP_COUNT)
1519 #define G_LP_COUNT(x) (((x) >> S_LP_COUNT) & M_LP_COUNT)
1520 
1521 #define S_BAR2VALID    31
1522 #define V_BAR2VALID(x) ((x) << S_BAR2VALID)
1523 #define F_BAR2VALID    V_BAR2VALID(1U)
1524 
1525 #define S_BAR2FULL    30
1526 #define V_BAR2FULL(x) ((x) << S_BAR2FULL)
1527 #define F_BAR2FULL    V_BAR2FULL(1U)
1528 
1529 #define S_LP_INT_THRESH_T5    18
1530 #define M_LP_INT_THRESH_T5    0xfffU
1531 #define V_LP_INT_THRESH_T5(x) ((x) << S_LP_INT_THRESH_T5)
1532 #define G_LP_INT_THRESH_T5(x) (((x) >> S_LP_INT_THRESH_T5) & M_LP_INT_THRESH_T5)
1533 
1534 #define S_LP_COUNT_T5    0
1535 #define M_LP_COUNT_T5    0x3ffffU
1536 #define V_LP_COUNT_T5(x) ((x) << S_LP_COUNT_T5)
1537 #define G_LP_COUNT_T5(x) (((x) >> S_LP_COUNT_T5) & M_LP_COUNT_T5)
1538 
1539 #define S_VFIFO_CNT    15
1540 #define M_VFIFO_CNT    0x1ffffU
1541 #define V_VFIFO_CNT(x) ((x) << S_VFIFO_CNT)
1542 #define G_VFIFO_CNT(x) (((x) >> S_VFIFO_CNT) & M_VFIFO_CNT)
1543 
1544 #define S_COAL_CTL_FIFO_CNT    8
1545 #define M_COAL_CTL_FIFO_CNT    0x3fU
1546 #define V_COAL_CTL_FIFO_CNT(x) ((x) << S_COAL_CTL_FIFO_CNT)
1547 #define G_COAL_CTL_FIFO_CNT(x) (((x) >> S_COAL_CTL_FIFO_CNT) & M_COAL_CTL_FIFO_CNT)
1548 
1549 #define S_MERGE_FIFO_CNT    0
1550 #define M_MERGE_FIFO_CNT    0x3fU
1551 #define V_MERGE_FIFO_CNT(x) ((x) << S_MERGE_FIFO_CNT)
1552 #define G_MERGE_FIFO_CNT(x) (((x) >> S_MERGE_FIFO_CNT) & M_MERGE_FIFO_CNT)
1553 
1554 #define A_SGE_DOORBELL_CONTROL 0x10a8
1555 
1556 #define S_HINTDEPTHCTL    27
1557 #define M_HINTDEPTHCTL    0x1fU
1558 #define V_HINTDEPTHCTL(x) ((x) << S_HINTDEPTHCTL)
1559 #define G_HINTDEPTHCTL(x) (((x) >> S_HINTDEPTHCTL) & M_HINTDEPTHCTL)
1560 
1561 #define S_NOCOALESCE    26
1562 #define V_NOCOALESCE(x) ((x) << S_NOCOALESCE)
1563 #define F_NOCOALESCE    V_NOCOALESCE(1U)
1564 
1565 #define S_HP_WEIGHT    24
1566 #define M_HP_WEIGHT    0x3U
1567 #define V_HP_WEIGHT(x) ((x) << S_HP_WEIGHT)
1568 #define G_HP_WEIGHT(x) (((x) >> S_HP_WEIGHT) & M_HP_WEIGHT)
1569 
1570 #define S_HP_DISABLE    23
1571 #define V_HP_DISABLE(x) ((x) << S_HP_DISABLE)
1572 #define F_HP_DISABLE    V_HP_DISABLE(1U)
1573 
1574 #define S_FORCEUSERDBTOLP    22
1575 #define V_FORCEUSERDBTOLP(x) ((x) << S_FORCEUSERDBTOLP)
1576 #define F_FORCEUSERDBTOLP    V_FORCEUSERDBTOLP(1U)
1577 
1578 #define S_FORCEVFPF0DBTOLP    21
1579 #define V_FORCEVFPF0DBTOLP(x) ((x) << S_FORCEVFPF0DBTOLP)
1580 #define F_FORCEVFPF0DBTOLP    V_FORCEVFPF0DBTOLP(1U)
1581 
1582 #define S_FORCEVFPF1DBTOLP    20
1583 #define V_FORCEVFPF1DBTOLP(x) ((x) << S_FORCEVFPF1DBTOLP)
1584 #define F_FORCEVFPF1DBTOLP    V_FORCEVFPF1DBTOLP(1U)
1585 
1586 #define S_FORCEVFPF2DBTOLP    19
1587 #define V_FORCEVFPF2DBTOLP(x) ((x) << S_FORCEVFPF2DBTOLP)
1588 #define F_FORCEVFPF2DBTOLP    V_FORCEVFPF2DBTOLP(1U)
1589 
1590 #define S_FORCEVFPF3DBTOLP    18
1591 #define V_FORCEVFPF3DBTOLP(x) ((x) << S_FORCEVFPF3DBTOLP)
1592 #define F_FORCEVFPF3DBTOLP    V_FORCEVFPF3DBTOLP(1U)
1593 
1594 #define S_FORCEVFPF4DBTOLP    17
1595 #define V_FORCEVFPF4DBTOLP(x) ((x) << S_FORCEVFPF4DBTOLP)
1596 #define F_FORCEVFPF4DBTOLP    V_FORCEVFPF4DBTOLP(1U)
1597 
1598 #define S_FORCEVFPF5DBTOLP    16
1599 #define V_FORCEVFPF5DBTOLP(x) ((x) << S_FORCEVFPF5DBTOLP)
1600 #define F_FORCEVFPF5DBTOLP    V_FORCEVFPF5DBTOLP(1U)
1601 
1602 #define S_FORCEVFPF6DBTOLP    15
1603 #define V_FORCEVFPF6DBTOLP(x) ((x) << S_FORCEVFPF6DBTOLP)
1604 #define F_FORCEVFPF6DBTOLP    V_FORCEVFPF6DBTOLP(1U)
1605 
1606 #define S_FORCEVFPF7DBTOLP    14
1607 #define V_FORCEVFPF7DBTOLP(x) ((x) << S_FORCEVFPF7DBTOLP)
1608 #define F_FORCEVFPF7DBTOLP    V_FORCEVFPF7DBTOLP(1U)
1609 
1610 #define S_ENABLE_DROP    13
1611 #define V_ENABLE_DROP(x) ((x) << S_ENABLE_DROP)
1612 #define F_ENABLE_DROP    V_ENABLE_DROP(1U)
1613 
1614 #define S_DROP_TIMEOUT    1
1615 #define M_DROP_TIMEOUT    0xfffU
1616 #define V_DROP_TIMEOUT(x) ((x) << S_DROP_TIMEOUT)
1617 #define G_DROP_TIMEOUT(x) (((x) >> S_DROP_TIMEOUT) & M_DROP_TIMEOUT)
1618 
1619 #define S_DROPPED_DB    0
1620 #define V_DROPPED_DB(x) ((x) << S_DROPPED_DB)
1621 #define F_DROPPED_DB    V_DROPPED_DB(1U)
1622 
1623 #define S_T6_DROP_TIMEOUT    7
1624 #define M_T6_DROP_TIMEOUT    0x3fU
1625 #define V_T6_DROP_TIMEOUT(x) ((x) << S_T6_DROP_TIMEOUT)
1626 #define G_T6_DROP_TIMEOUT(x) (((x) >> S_T6_DROP_TIMEOUT) & M_T6_DROP_TIMEOUT)
1627 
1628 #define S_INVONDBSYNC    6
1629 #define V_INVONDBSYNC(x) ((x) << S_INVONDBSYNC)
1630 #define F_INVONDBSYNC    V_INVONDBSYNC(1U)
1631 
1632 #define S_INVONGTSSYNC    5
1633 #define V_INVONGTSSYNC(x) ((x) << S_INVONGTSSYNC)
1634 #define F_INVONGTSSYNC    V_INVONGTSSYNC(1U)
1635 
1636 #define S_DB_DBG_EN    4
1637 #define V_DB_DBG_EN(x) ((x) << S_DB_DBG_EN)
1638 #define F_DB_DBG_EN    V_DB_DBG_EN(1U)
1639 
1640 #define S_GTS_DBG_TIMER_REG    1
1641 #define M_GTS_DBG_TIMER_REG    0x7U
1642 #define V_GTS_DBG_TIMER_REG(x) ((x) << S_GTS_DBG_TIMER_REG)
1643 #define G_GTS_DBG_TIMER_REG(x) (((x) >> S_GTS_DBG_TIMER_REG) & M_GTS_DBG_TIMER_REG)
1644 
1645 #define S_GTS_DBG_EN    0
1646 #define V_GTS_DBG_EN(x) ((x) << S_GTS_DBG_EN)
1647 #define F_GTS_DBG_EN    V_GTS_DBG_EN(1U)
1648 
1649 #define A_SGE_DROPPED_DOORBELL 0x10ac
1650 #define A_SGE_DOORBELL_THROTTLE_CONTROL 0x10b0
1651 
1652 #define S_THROTTLE_COUNT    1
1653 #define M_THROTTLE_COUNT    0xfffU
1654 #define V_THROTTLE_COUNT(x) ((x) << S_THROTTLE_COUNT)
1655 #define G_THROTTLE_COUNT(x) (((x) >> S_THROTTLE_COUNT) & M_THROTTLE_COUNT)
1656 
1657 #define S_THROTTLE_ENABLE    0
1658 #define V_THROTTLE_ENABLE(x) ((x) << S_THROTTLE_ENABLE)
1659 #define F_THROTTLE_ENABLE    V_THROTTLE_ENABLE(1U)
1660 
1661 #define S_BAR2THROTTLECOUNT    16
1662 #define M_BAR2THROTTLECOUNT    0xffU
1663 #define V_BAR2THROTTLECOUNT(x) ((x) << S_BAR2THROTTLECOUNT)
1664 #define G_BAR2THROTTLECOUNT(x) (((x) >> S_BAR2THROTTLECOUNT) & M_BAR2THROTTLECOUNT)
1665 
1666 #define S_CLRCOALESCEDISABLE    15
1667 #define V_CLRCOALESCEDISABLE(x) ((x) << S_CLRCOALESCEDISABLE)
1668 #define F_CLRCOALESCEDISABLE    V_CLRCOALESCEDISABLE(1U)
1669 
1670 #define S_OPENBAR2GATEONCE    14
1671 #define V_OPENBAR2GATEONCE(x) ((x) << S_OPENBAR2GATEONCE)
1672 #define F_OPENBAR2GATEONCE    V_OPENBAR2GATEONCE(1U)
1673 
1674 #define S_FORCEOPENBAR2GATE    13
1675 #define V_FORCEOPENBAR2GATE(x) ((x) << S_FORCEOPENBAR2GATE)
1676 #define F_FORCEOPENBAR2GATE    V_FORCEOPENBAR2GATE(1U)
1677 
1678 #define A_SGE_ITP_CONTROL 0x10b4
1679 
1680 #define S_CRITICAL_TIME    10
1681 #define M_CRITICAL_TIME    0x7fffU
1682 #define V_CRITICAL_TIME(x) ((x) << S_CRITICAL_TIME)
1683 #define G_CRITICAL_TIME(x) (((x) >> S_CRITICAL_TIME) & M_CRITICAL_TIME)
1684 
1685 #define S_LL_EMPTY    4
1686 #define M_LL_EMPTY    0x3fU
1687 #define V_LL_EMPTY(x) ((x) << S_LL_EMPTY)
1688 #define G_LL_EMPTY(x) (((x) >> S_LL_EMPTY) & M_LL_EMPTY)
1689 
1690 #define S_LL_READ_WAIT_DISABLE    0
1691 #define V_LL_READ_WAIT_DISABLE(x) ((x) << S_LL_READ_WAIT_DISABLE)
1692 #define F_LL_READ_WAIT_DISABLE    V_LL_READ_WAIT_DISABLE(1U)
1693 
1694 #define S_TSCALE    28
1695 #define M_TSCALE    0xfU
1696 #define V_TSCALE(x) ((x) << S_TSCALE)
1697 #define G_TSCALE(x) (((x) >> S_TSCALE) & M_TSCALE)
1698 
1699 #define A_SGE_TIMER_VALUE_0_AND_1 0x10b8
1700 
1701 #define S_TIMERVALUE0    16
1702 #define M_TIMERVALUE0    0xffffU
1703 #define V_TIMERVALUE0(x) ((x) << S_TIMERVALUE0)
1704 #define G_TIMERVALUE0(x) (((x) >> S_TIMERVALUE0) & M_TIMERVALUE0)
1705 
1706 #define S_TIMERVALUE1    0
1707 #define M_TIMERVALUE1    0xffffU
1708 #define V_TIMERVALUE1(x) ((x) << S_TIMERVALUE1)
1709 #define G_TIMERVALUE1(x) (((x) >> S_TIMERVALUE1) & M_TIMERVALUE1)
1710 
1711 #define A_SGE_TIMER_VALUE_2_AND_3 0x10bc
1712 
1713 #define S_TIMERVALUE2    16
1714 #define M_TIMERVALUE2    0xffffU
1715 #define V_TIMERVALUE2(x) ((x) << S_TIMERVALUE2)
1716 #define G_TIMERVALUE2(x) (((x) >> S_TIMERVALUE2) & M_TIMERVALUE2)
1717 
1718 #define S_TIMERVALUE3    0
1719 #define M_TIMERVALUE3    0xffffU
1720 #define V_TIMERVALUE3(x) ((x) << S_TIMERVALUE3)
1721 #define G_TIMERVALUE3(x) (((x) >> S_TIMERVALUE3) & M_TIMERVALUE3)
1722 
1723 #define A_SGE_TIMER_VALUE_4_AND_5 0x10c0
1724 
1725 #define S_TIMERVALUE4    16
1726 #define M_TIMERVALUE4    0xffffU
1727 #define V_TIMERVALUE4(x) ((x) << S_TIMERVALUE4)
1728 #define G_TIMERVALUE4(x) (((x) >> S_TIMERVALUE4) & M_TIMERVALUE4)
1729 
1730 #define S_TIMERVALUE5    0
1731 #define M_TIMERVALUE5    0xffffU
1732 #define V_TIMERVALUE5(x) ((x) << S_TIMERVALUE5)
1733 #define G_TIMERVALUE5(x) (((x) >> S_TIMERVALUE5) & M_TIMERVALUE5)
1734 
1735 #define A_SGE_PD_RSP_CREDIT01 0x10c4
1736 
1737 #define S_RSPCREDITEN0    31
1738 #define V_RSPCREDITEN0(x) ((x) << S_RSPCREDITEN0)
1739 #define F_RSPCREDITEN0    V_RSPCREDITEN0(1U)
1740 
1741 #define S_MAXTAG0    24
1742 #define M_MAXTAG0    0x7fU
1743 #define V_MAXTAG0(x) ((x) << S_MAXTAG0)
1744 #define G_MAXTAG0(x) (((x) >> S_MAXTAG0) & M_MAXTAG0)
1745 
1746 #define S_MAXRSPCNT0    16
1747 #define M_MAXRSPCNT0    0xffU
1748 #define V_MAXRSPCNT0(x) ((x) << S_MAXRSPCNT0)
1749 #define G_MAXRSPCNT0(x) (((x) >> S_MAXRSPCNT0) & M_MAXRSPCNT0)
1750 
1751 #define S_RSPCREDITEN1    15
1752 #define V_RSPCREDITEN1(x) ((x) << S_RSPCREDITEN1)
1753 #define F_RSPCREDITEN1    V_RSPCREDITEN1(1U)
1754 
1755 #define S_MAXTAG1    8
1756 #define M_MAXTAG1    0x7fU
1757 #define V_MAXTAG1(x) ((x) << S_MAXTAG1)
1758 #define G_MAXTAG1(x) (((x) >> S_MAXTAG1) & M_MAXTAG1)
1759 
1760 #define S_MAXRSPCNT1    0
1761 #define M_MAXRSPCNT1    0xffU
1762 #define V_MAXRSPCNT1(x) ((x) << S_MAXRSPCNT1)
1763 #define G_MAXRSPCNT1(x) (((x) >> S_MAXRSPCNT1) & M_MAXRSPCNT1)
1764 
1765 #define A_SGE_GK_CONTROL 0x10c4
1766 
1767 #define S_EN_FLM_FIFTH    29
1768 #define V_EN_FLM_FIFTH(x) ((x) << S_EN_FLM_FIFTH)
1769 #define F_EN_FLM_FIFTH    V_EN_FLM_FIFTH(1U)
1770 
1771 #define S_FL_PROG_THRESH    20
1772 #define M_FL_PROG_THRESH    0x1ffU
1773 #define V_FL_PROG_THRESH(x) ((x) << S_FL_PROG_THRESH)
1774 #define G_FL_PROG_THRESH(x) (((x) >> S_FL_PROG_THRESH) & M_FL_PROG_THRESH)
1775 
1776 #define S_COAL_ALL_THREAD    19
1777 #define V_COAL_ALL_THREAD(x) ((x) << S_COAL_ALL_THREAD)
1778 #define F_COAL_ALL_THREAD    V_COAL_ALL_THREAD(1U)
1779 
1780 #define S_EN_PSHB    18
1781 #define V_EN_PSHB(x) ((x) << S_EN_PSHB)
1782 #define F_EN_PSHB    V_EN_PSHB(1U)
1783 
1784 #define S_EN_DB_FIFTH    17
1785 #define V_EN_DB_FIFTH(x) ((x) << S_EN_DB_FIFTH)
1786 #define F_EN_DB_FIFTH    V_EN_DB_FIFTH(1U)
1787 
1788 #define S_DB_PROG_THRESH    8
1789 #define M_DB_PROG_THRESH    0x1ffU
1790 #define V_DB_PROG_THRESH(x) ((x) << S_DB_PROG_THRESH)
1791 #define G_DB_PROG_THRESH(x) (((x) >> S_DB_PROG_THRESH) & M_DB_PROG_THRESH)
1792 
1793 #define S_100NS_TIMER    0
1794 #define M_100NS_TIMER    0xffU
1795 #define V_100NS_TIMER(x) ((x) << S_100NS_TIMER)
1796 #define G_100NS_TIMER(x) (((x) >> S_100NS_TIMER) & M_100NS_TIMER)
1797 
1798 #define A_SGE_PD_RSP_CREDIT23 0x10c8
1799 
1800 #define S_RSPCREDITEN2    31
1801 #define V_RSPCREDITEN2(x) ((x) << S_RSPCREDITEN2)
1802 #define F_RSPCREDITEN2    V_RSPCREDITEN2(1U)
1803 
1804 #define S_MAXTAG2    24
1805 #define M_MAXTAG2    0x7fU
1806 #define V_MAXTAG2(x) ((x) << S_MAXTAG2)
1807 #define G_MAXTAG2(x) (((x) >> S_MAXTAG2) & M_MAXTAG2)
1808 
1809 #define S_MAXRSPCNT2    16
1810 #define M_MAXRSPCNT2    0xffU
1811 #define V_MAXRSPCNT2(x) ((x) << S_MAXRSPCNT2)
1812 #define G_MAXRSPCNT2(x) (((x) >> S_MAXRSPCNT2) & M_MAXRSPCNT2)
1813 
1814 #define S_RSPCREDITEN3    15
1815 #define V_RSPCREDITEN3(x) ((x) << S_RSPCREDITEN3)
1816 #define F_RSPCREDITEN3    V_RSPCREDITEN3(1U)
1817 
1818 #define S_MAXTAG3    8
1819 #define M_MAXTAG3    0x7fU
1820 #define V_MAXTAG3(x) ((x) << S_MAXTAG3)
1821 #define G_MAXTAG3(x) (((x) >> S_MAXTAG3) & M_MAXTAG3)
1822 
1823 #define S_MAXRSPCNT3    0
1824 #define M_MAXRSPCNT3    0xffU
1825 #define V_MAXRSPCNT3(x) ((x) << S_MAXRSPCNT3)
1826 #define G_MAXRSPCNT3(x) (((x) >> S_MAXRSPCNT3) & M_MAXRSPCNT3)
1827 
1828 #define A_SGE_GK_CONTROL2 0x10c8
1829 
1830 #define S_DBQ_TIMER_TICK    16
1831 #define M_DBQ_TIMER_TICK    0xffffU
1832 #define V_DBQ_TIMER_TICK(x) ((x) << S_DBQ_TIMER_TICK)
1833 #define G_DBQ_TIMER_TICK(x) (((x) >> S_DBQ_TIMER_TICK) & M_DBQ_TIMER_TICK)
1834 
1835 #define S_FL_MERGE_CNT_THRESH    8
1836 #define M_FL_MERGE_CNT_THRESH    0xfU
1837 #define V_FL_MERGE_CNT_THRESH(x) ((x) << S_FL_MERGE_CNT_THRESH)
1838 #define G_FL_MERGE_CNT_THRESH(x) (((x) >> S_FL_MERGE_CNT_THRESH) & M_FL_MERGE_CNT_THRESH)
1839 
1840 #define S_MERGE_CNT_THRESH    0
1841 #define M_MERGE_CNT_THRESH    0x3fU
1842 #define V_MERGE_CNT_THRESH(x) ((x) << S_MERGE_CNT_THRESH)
1843 #define G_MERGE_CNT_THRESH(x) (((x) >> S_MERGE_CNT_THRESH) & M_MERGE_CNT_THRESH)
1844 
1845 #define A_SGE_DEBUG_INDEX 0x10cc
1846 #define A_SGE_DEBUG_DATA_HIGH 0x10d0
1847 #define A_SGE_DEBUG_DATA_LOW 0x10d4
1848 #define A_SGE_REVISION 0x10d8
1849 #define A_SGE_INT_CAUSE4 0x10dc
1850 
1851 #define S_ERR_BAD_UPFL_INC_CREDIT3    8
1852 #define V_ERR_BAD_UPFL_INC_CREDIT3(x) ((x) << S_ERR_BAD_UPFL_INC_CREDIT3)
1853 #define F_ERR_BAD_UPFL_INC_CREDIT3    V_ERR_BAD_UPFL_INC_CREDIT3(1U)
1854 
1855 #define S_ERR_BAD_UPFL_INC_CREDIT2    7
1856 #define V_ERR_BAD_UPFL_INC_CREDIT2(x) ((x) << S_ERR_BAD_UPFL_INC_CREDIT2)
1857 #define F_ERR_BAD_UPFL_INC_CREDIT2    V_ERR_BAD_UPFL_INC_CREDIT2(1U)
1858 
1859 #define S_ERR_BAD_UPFL_INC_CREDIT1    6
1860 #define V_ERR_BAD_UPFL_INC_CREDIT1(x) ((x) << S_ERR_BAD_UPFL_INC_CREDIT1)
1861 #define F_ERR_BAD_UPFL_INC_CREDIT1    V_ERR_BAD_UPFL_INC_CREDIT1(1U)
1862 
1863 #define S_ERR_BAD_UPFL_INC_CREDIT0    5
1864 #define V_ERR_BAD_UPFL_INC_CREDIT0(x) ((x) << S_ERR_BAD_UPFL_INC_CREDIT0)
1865 #define F_ERR_BAD_UPFL_INC_CREDIT0    V_ERR_BAD_UPFL_INC_CREDIT0(1U)
1866 
1867 #define S_ERR_PHYSADDR_LEN0_IDMA1    4
1868 #define V_ERR_PHYSADDR_LEN0_IDMA1(x) ((x) << S_ERR_PHYSADDR_LEN0_IDMA1)
1869 #define F_ERR_PHYSADDR_LEN0_IDMA1    V_ERR_PHYSADDR_LEN0_IDMA1(1U)
1870 
1871 #define S_ERR_PHYSADDR_LEN0_IDMA0    3
1872 #define V_ERR_PHYSADDR_LEN0_IDMA0(x) ((x) << S_ERR_PHYSADDR_LEN0_IDMA0)
1873 #define F_ERR_PHYSADDR_LEN0_IDMA0    V_ERR_PHYSADDR_LEN0_IDMA0(1U)
1874 
1875 #define S_ERR_FLM_INVALID_PKT_DROP1    2
1876 #define V_ERR_FLM_INVALID_PKT_DROP1(x) ((x) << S_ERR_FLM_INVALID_PKT_DROP1)
1877 #define F_ERR_FLM_INVALID_PKT_DROP1    V_ERR_FLM_INVALID_PKT_DROP1(1U)
1878 
1879 #define S_ERR_FLM_INVALID_PKT_DROP0    1
1880 #define V_ERR_FLM_INVALID_PKT_DROP0(x) ((x) << S_ERR_FLM_INVALID_PKT_DROP0)
1881 #define F_ERR_FLM_INVALID_PKT_DROP0    V_ERR_FLM_INVALID_PKT_DROP0(1U)
1882 
1883 #define S_ERR_UNEXPECTED_TIMER    0
1884 #define V_ERR_UNEXPECTED_TIMER(x) ((x) << S_ERR_UNEXPECTED_TIMER)
1885 #define F_ERR_UNEXPECTED_TIMER    V_ERR_UNEXPECTED_TIMER(1U)
1886 
1887 #define S_BAR2_EGRESS_LEN_OR_ADDR_ERR    29
1888 #define V_BAR2_EGRESS_LEN_OR_ADDR_ERR(x) ((x) << S_BAR2_EGRESS_LEN_OR_ADDR_ERR)
1889 #define F_BAR2_EGRESS_LEN_OR_ADDR_ERR    V_BAR2_EGRESS_LEN_OR_ADDR_ERR(1U)
1890 
1891 #define S_ERR_CPL_EXCEED_MAX_IQE_SIZE1    28
1892 #define V_ERR_CPL_EXCEED_MAX_IQE_SIZE1(x) ((x) << S_ERR_CPL_EXCEED_MAX_IQE_SIZE1)
1893 #define F_ERR_CPL_EXCEED_MAX_IQE_SIZE1    V_ERR_CPL_EXCEED_MAX_IQE_SIZE1(1U)
1894 
1895 #define S_ERR_CPL_EXCEED_MAX_IQE_SIZE0    27
1896 #define V_ERR_CPL_EXCEED_MAX_IQE_SIZE0(x) ((x) << S_ERR_CPL_EXCEED_MAX_IQE_SIZE0)
1897 #define F_ERR_CPL_EXCEED_MAX_IQE_SIZE0    V_ERR_CPL_EXCEED_MAX_IQE_SIZE0(1U)
1898 
1899 #define S_ERR_WR_LEN_TOO_LARGE3    26
1900 #define V_ERR_WR_LEN_TOO_LARGE3(x) ((x) << S_ERR_WR_LEN_TOO_LARGE3)
1901 #define F_ERR_WR_LEN_TOO_LARGE3    V_ERR_WR_LEN_TOO_LARGE3(1U)
1902 
1903 #define S_ERR_WR_LEN_TOO_LARGE2    25
1904 #define V_ERR_WR_LEN_TOO_LARGE2(x) ((x) << S_ERR_WR_LEN_TOO_LARGE2)
1905 #define F_ERR_WR_LEN_TOO_LARGE2    V_ERR_WR_LEN_TOO_LARGE2(1U)
1906 
1907 #define S_ERR_WR_LEN_TOO_LARGE1    24
1908 #define V_ERR_WR_LEN_TOO_LARGE1(x) ((x) << S_ERR_WR_LEN_TOO_LARGE1)
1909 #define F_ERR_WR_LEN_TOO_LARGE1    V_ERR_WR_LEN_TOO_LARGE1(1U)
1910 
1911 #define S_ERR_WR_LEN_TOO_LARGE0    23
1912 #define V_ERR_WR_LEN_TOO_LARGE0(x) ((x) << S_ERR_WR_LEN_TOO_LARGE0)
1913 #define F_ERR_WR_LEN_TOO_LARGE0    V_ERR_WR_LEN_TOO_LARGE0(1U)
1914 
1915 #define S_ERR_LARGE_MINFETCH_WITH_TXCOAL3    22
1916 #define V_ERR_LARGE_MINFETCH_WITH_TXCOAL3(x) ((x) << S_ERR_LARGE_MINFETCH_WITH_TXCOAL3)
1917 #define F_ERR_LARGE_MINFETCH_WITH_TXCOAL3    V_ERR_LARGE_MINFETCH_WITH_TXCOAL3(1U)
1918 
1919 #define S_ERR_LARGE_MINFETCH_WITH_TXCOAL2    21
1920 #define V_ERR_LARGE_MINFETCH_WITH_TXCOAL2(x) ((x) << S_ERR_LARGE_MINFETCH_WITH_TXCOAL2)
1921 #define F_ERR_LARGE_MINFETCH_WITH_TXCOAL2    V_ERR_LARGE_MINFETCH_WITH_TXCOAL2(1U)
1922 
1923 #define S_ERR_LARGE_MINFETCH_WITH_TXCOAL1    20
1924 #define V_ERR_LARGE_MINFETCH_WITH_TXCOAL1(x) ((x) << S_ERR_LARGE_MINFETCH_WITH_TXCOAL1)
1925 #define F_ERR_LARGE_MINFETCH_WITH_TXCOAL1    V_ERR_LARGE_MINFETCH_WITH_TXCOAL1(1U)
1926 
1927 #define S_ERR_LARGE_MINFETCH_WITH_TXCOAL0    19
1928 #define V_ERR_LARGE_MINFETCH_WITH_TXCOAL0(x) ((x) << S_ERR_LARGE_MINFETCH_WITH_TXCOAL0)
1929 #define F_ERR_LARGE_MINFETCH_WITH_TXCOAL0    V_ERR_LARGE_MINFETCH_WITH_TXCOAL0(1U)
1930 
1931 #define S_COAL_WITH_HP_DISABLE_ERR    18
1932 #define V_COAL_WITH_HP_DISABLE_ERR(x) ((x) << S_COAL_WITH_HP_DISABLE_ERR)
1933 #define F_COAL_WITH_HP_DISABLE_ERR    V_COAL_WITH_HP_DISABLE_ERR(1U)
1934 
1935 #define S_BAR2_EGRESS_COAL0_ERR    17
1936 #define V_BAR2_EGRESS_COAL0_ERR(x) ((x) << S_BAR2_EGRESS_COAL0_ERR)
1937 #define F_BAR2_EGRESS_COAL0_ERR    V_BAR2_EGRESS_COAL0_ERR(1U)
1938 
1939 #define S_BAR2_EGRESS_SIZE_ERR    16
1940 #define V_BAR2_EGRESS_SIZE_ERR(x) ((x) << S_BAR2_EGRESS_SIZE_ERR)
1941 #define F_BAR2_EGRESS_SIZE_ERR    V_BAR2_EGRESS_SIZE_ERR(1U)
1942 
1943 #define S_FLM_PC_RSP_ERR    15
1944 #define V_FLM_PC_RSP_ERR(x) ((x) << S_FLM_PC_RSP_ERR)
1945 #define F_FLM_PC_RSP_ERR    V_FLM_PC_RSP_ERR(1U)
1946 
1947 #define S_DBFIFO_HP_INT_LOW    14
1948 #define V_DBFIFO_HP_INT_LOW(x) ((x) << S_DBFIFO_HP_INT_LOW)
1949 #define F_DBFIFO_HP_INT_LOW    V_DBFIFO_HP_INT_LOW(1U)
1950 
1951 #define S_DBFIFO_LP_INT_LOW    13
1952 #define V_DBFIFO_LP_INT_LOW(x) ((x) << S_DBFIFO_LP_INT_LOW)
1953 #define F_DBFIFO_LP_INT_LOW    V_DBFIFO_LP_INT_LOW(1U)
1954 
1955 #define S_DBFIFO_FL_INT_LOW    12
1956 #define V_DBFIFO_FL_INT_LOW(x) ((x) << S_DBFIFO_FL_INT_LOW)
1957 #define F_DBFIFO_FL_INT_LOW    V_DBFIFO_FL_INT_LOW(1U)
1958 
1959 #define S_DBFIFO_FL_INT    11
1960 #define V_DBFIFO_FL_INT(x) ((x) << S_DBFIFO_FL_INT)
1961 #define F_DBFIFO_FL_INT    V_DBFIFO_FL_INT(1U)
1962 
1963 #define S_ERR_RX_CPL_PACKET_SIZE1    10
1964 #define V_ERR_RX_CPL_PACKET_SIZE1(x) ((x) << S_ERR_RX_CPL_PACKET_SIZE1)
1965 #define F_ERR_RX_CPL_PACKET_SIZE1    V_ERR_RX_CPL_PACKET_SIZE1(1U)
1966 
1967 #define S_ERR_RX_CPL_PACKET_SIZE0    9
1968 #define V_ERR_RX_CPL_PACKET_SIZE0(x) ((x) << S_ERR_RX_CPL_PACKET_SIZE0)
1969 #define F_ERR_RX_CPL_PACKET_SIZE0    V_ERR_RX_CPL_PACKET_SIZE0(1U)
1970 
1971 #define S_ERR_ISHIFT_UR1    31
1972 #define V_ERR_ISHIFT_UR1(x) ((x) << S_ERR_ISHIFT_UR1)
1973 #define F_ERR_ISHIFT_UR1    V_ERR_ISHIFT_UR1(1U)
1974 
1975 #define S_ERR_ISHIFT_UR0    30
1976 #define V_ERR_ISHIFT_UR0(x) ((x) << S_ERR_ISHIFT_UR0)
1977 #define F_ERR_ISHIFT_UR0    V_ERR_ISHIFT_UR0(1U)
1978 
1979 #define S_ERR_TH3_MAX_FETCH    14
1980 #define V_ERR_TH3_MAX_FETCH(x) ((x) << S_ERR_TH3_MAX_FETCH)
1981 #define F_ERR_TH3_MAX_FETCH    V_ERR_TH3_MAX_FETCH(1U)
1982 
1983 #define S_ERR_TH2_MAX_FETCH    13
1984 #define V_ERR_TH2_MAX_FETCH(x) ((x) << S_ERR_TH2_MAX_FETCH)
1985 #define F_ERR_TH2_MAX_FETCH    V_ERR_TH2_MAX_FETCH(1U)
1986 
1987 #define S_ERR_TH1_MAX_FETCH    12
1988 #define V_ERR_TH1_MAX_FETCH(x) ((x) << S_ERR_TH1_MAX_FETCH)
1989 #define F_ERR_TH1_MAX_FETCH    V_ERR_TH1_MAX_FETCH(1U)
1990 
1991 #define S_ERR_TH0_MAX_FETCH    11
1992 #define V_ERR_TH0_MAX_FETCH(x) ((x) << S_ERR_TH0_MAX_FETCH)
1993 #define F_ERR_TH0_MAX_FETCH    V_ERR_TH0_MAX_FETCH(1U)
1994 
1995 #define A_SGE_INT_ENABLE4 0x10e0
1996 #define A_SGE_STAT_TOTAL 0x10e4
1997 #define A_SGE_STAT_MATCH 0x10e8
1998 #define A_SGE_STAT_CFG 0x10ec
1999 
2000 #define S_ITPOPMODE    8
2001 #define V_ITPOPMODE(x) ((x) << S_ITPOPMODE)
2002 #define F_ITPOPMODE    V_ITPOPMODE(1U)
2003 
2004 #define S_EGRCTXTOPMODE    6
2005 #define M_EGRCTXTOPMODE    0x3U
2006 #define V_EGRCTXTOPMODE(x) ((x) << S_EGRCTXTOPMODE)
2007 #define G_EGRCTXTOPMODE(x) (((x) >> S_EGRCTXTOPMODE) & M_EGRCTXTOPMODE)
2008 
2009 #define S_INGCTXTOPMODE    4
2010 #define M_INGCTXTOPMODE    0x3U
2011 #define V_INGCTXTOPMODE(x) ((x) << S_INGCTXTOPMODE)
2012 #define G_INGCTXTOPMODE(x) (((x) >> S_INGCTXTOPMODE) & M_INGCTXTOPMODE)
2013 
2014 #define S_STATMODE    2
2015 #define M_STATMODE    0x3U
2016 #define V_STATMODE(x) ((x) << S_STATMODE)
2017 #define G_STATMODE(x) (((x) >> S_STATMODE) & M_STATMODE)
2018 
2019 #define S_STATSOURCE    0
2020 #define M_STATSOURCE    0x3U
2021 #define V_STATSOURCE(x) ((x) << S_STATSOURCE)
2022 #define G_STATSOURCE(x) (((x) >> S_STATSOURCE) & M_STATSOURCE)
2023 
2024 #define S_STATSOURCE_T5    9
2025 #define M_STATSOURCE_T5    0xfU
2026 #define V_STATSOURCE_T5(x) ((x) << S_STATSOURCE_T5)
2027 #define G_STATSOURCE_T5(x) (((x) >> S_STATSOURCE_T5) & M_STATSOURCE_T5)
2028 
2029 #define S_T6_STATMODE    0
2030 #define M_T6_STATMODE    0xfU
2031 #define V_T6_STATMODE(x) ((x) << S_T6_STATMODE)
2032 #define G_T6_STATMODE(x) (((x) >> S_T6_STATMODE) & M_T6_STATMODE)
2033 
2034 #define A_SGE_HINT_CFG 0x10f0
2035 
2036 #define S_HINTSALLOWEDNOHDR    6
2037 #define M_HINTSALLOWEDNOHDR    0x3fU
2038 #define V_HINTSALLOWEDNOHDR(x) ((x) << S_HINTSALLOWEDNOHDR)
2039 #define G_HINTSALLOWEDNOHDR(x) (((x) >> S_HINTSALLOWEDNOHDR) & M_HINTSALLOWEDNOHDR)
2040 
2041 #define S_HINTSALLOWEDHDR    0
2042 #define M_HINTSALLOWEDHDR    0x3fU
2043 #define V_HINTSALLOWEDHDR(x) ((x) << S_HINTSALLOWEDHDR)
2044 #define G_HINTSALLOWEDHDR(x) (((x) >> S_HINTSALLOWEDHDR) & M_HINTSALLOWEDHDR)
2045 
2046 #define S_UPCUTOFFTHRESHLP    12
2047 #define M_UPCUTOFFTHRESHLP    0x7ffU
2048 #define V_UPCUTOFFTHRESHLP(x) ((x) << S_UPCUTOFFTHRESHLP)
2049 #define G_UPCUTOFFTHRESHLP(x) (((x) >> S_UPCUTOFFTHRESHLP) & M_UPCUTOFFTHRESHLP)
2050 
2051 #define A_SGE_INGRESS_QUEUES_PER_PAGE_PF 0x10f4
2052 #define A_SGE_INGRESS_QUEUES_PER_PAGE_VF 0x10f8
2053 #define A_SGE_PD_WRR_CONFIG 0x10fc
2054 
2055 #define S_EDMA_WEIGHT    0
2056 #define M_EDMA_WEIGHT    0x3fU
2057 #define V_EDMA_WEIGHT(x) ((x) << S_EDMA_WEIGHT)
2058 #define G_EDMA_WEIGHT(x) (((x) >> S_EDMA_WEIGHT) & M_EDMA_WEIGHT)
2059 
2060 #define A_SGE_ERROR_STATS 0x1100
2061 
2062 #define S_UNCAPTURED_ERROR    18
2063 #define V_UNCAPTURED_ERROR(x) ((x) << S_UNCAPTURED_ERROR)
2064 #define F_UNCAPTURED_ERROR    V_UNCAPTURED_ERROR(1U)
2065 
2066 #define S_ERROR_QID_VALID    17
2067 #define V_ERROR_QID_VALID(x) ((x) << S_ERROR_QID_VALID)
2068 #define F_ERROR_QID_VALID    V_ERROR_QID_VALID(1U)
2069 
2070 #define S_ERROR_QID    0
2071 #define M_ERROR_QID    0x1ffffU
2072 #define V_ERROR_QID(x) ((x) << S_ERROR_QID)
2073 #define G_ERROR_QID(x) (((x) >> S_ERROR_QID) & M_ERROR_QID)
2074 
2075 #define S_CAUSE_REGISTER    24
2076 #define M_CAUSE_REGISTER    0x7U
2077 #define V_CAUSE_REGISTER(x) ((x) << S_CAUSE_REGISTER)
2078 #define G_CAUSE_REGISTER(x) (((x) >> S_CAUSE_REGISTER) & M_CAUSE_REGISTER)
2079 
2080 #define S_CAUSE_BIT    19
2081 #define M_CAUSE_BIT    0x1fU
2082 #define V_CAUSE_BIT(x) ((x) << S_CAUSE_BIT)
2083 #define G_CAUSE_BIT(x) (((x) >> S_CAUSE_BIT) & M_CAUSE_BIT)
2084 
2085 #define A_SGE_SHARED_TAG_CHAN_CFG 0x1104
2086 
2087 #define S_MINTAG3    24
2088 #define M_MINTAG3    0xffU
2089 #define V_MINTAG3(x) ((x) << S_MINTAG3)
2090 #define G_MINTAG3(x) (((x) >> S_MINTAG3) & M_MINTAG3)
2091 
2092 #define S_MINTAG2    16
2093 #define M_MINTAG2    0xffU
2094 #define V_MINTAG2(x) ((x) << S_MINTAG2)
2095 #define G_MINTAG2(x) (((x) >> S_MINTAG2) & M_MINTAG2)
2096 
2097 #define S_MINTAG1    8
2098 #define M_MINTAG1    0xffU
2099 #define V_MINTAG1(x) ((x) << S_MINTAG1)
2100 #define G_MINTAG1(x) (((x) >> S_MINTAG1) & M_MINTAG1)
2101 
2102 #define S_MINTAG0    0
2103 #define M_MINTAG0    0xffU
2104 #define V_MINTAG0(x) ((x) << S_MINTAG0)
2105 #define G_MINTAG0(x) (((x) >> S_MINTAG0) & M_MINTAG0)
2106 
2107 #define A_SGE_IDMA0_DROP_CNT 0x1104
2108 #define A_SGE_SHARED_TAG_POOL_CFG 0x1108
2109 
2110 #define S_TAGPOOLTOTAL    0
2111 #define M_TAGPOOLTOTAL    0xffU
2112 #define V_TAGPOOLTOTAL(x) ((x) << S_TAGPOOLTOTAL)
2113 #define G_TAGPOOLTOTAL(x) (((x) >> S_TAGPOOLTOTAL) & M_TAGPOOLTOTAL)
2114 
2115 #define A_SGE_IDMA1_DROP_CNT 0x1108
2116 #define A_SGE_INT_CAUSE5 0x110c
2117 
2118 #define S_ERR_T_RXCRC    31
2119 #define V_ERR_T_RXCRC(x) ((x) << S_ERR_T_RXCRC)
2120 #define F_ERR_T_RXCRC    V_ERR_T_RXCRC(1U)
2121 
2122 #define S_PERR_MC_RSPDATA    30
2123 #define V_PERR_MC_RSPDATA(x) ((x) << S_PERR_MC_RSPDATA)
2124 #define F_PERR_MC_RSPDATA    V_PERR_MC_RSPDATA(1U)
2125 
2126 #define S_PERR_PC_RSPDATA    29
2127 #define V_PERR_PC_RSPDATA(x) ((x) << S_PERR_PC_RSPDATA)
2128 #define F_PERR_PC_RSPDATA    V_PERR_PC_RSPDATA(1U)
2129 
2130 #define S_PERR_PD_RDRSPDATA    28
2131 #define V_PERR_PD_RDRSPDATA(x) ((x) << S_PERR_PD_RDRSPDATA)
2132 #define F_PERR_PD_RDRSPDATA    V_PERR_PD_RDRSPDATA(1U)
2133 
2134 #define S_PERR_U_RXDATA    27
2135 #define V_PERR_U_RXDATA(x) ((x) << S_PERR_U_RXDATA)
2136 #define F_PERR_U_RXDATA    V_PERR_U_RXDATA(1U)
2137 
2138 #define S_PERR_UD_RXDATA    26
2139 #define V_PERR_UD_RXDATA(x) ((x) << S_PERR_UD_RXDATA)
2140 #define F_PERR_UD_RXDATA    V_PERR_UD_RXDATA(1U)
2141 
2142 #define S_PERR_UP_DATA    25
2143 #define V_PERR_UP_DATA(x) ((x) << S_PERR_UP_DATA)
2144 #define F_PERR_UP_DATA    V_PERR_UP_DATA(1U)
2145 
2146 #define S_PERR_CIM2SGE_RXDATA    24
2147 #define V_PERR_CIM2SGE_RXDATA(x) ((x) << S_PERR_CIM2SGE_RXDATA)
2148 #define F_PERR_CIM2SGE_RXDATA    V_PERR_CIM2SGE_RXDATA(1U)
2149 
2150 #define S_PERR_HINT_DELAY_FIFO1_T5    23
2151 #define V_PERR_HINT_DELAY_FIFO1_T5(x) ((x) << S_PERR_HINT_DELAY_FIFO1_T5)
2152 #define F_PERR_HINT_DELAY_FIFO1_T5    V_PERR_HINT_DELAY_FIFO1_T5(1U)
2153 
2154 #define S_PERR_HINT_DELAY_FIFO0_T5    22
2155 #define V_PERR_HINT_DELAY_FIFO0_T5(x) ((x) << S_PERR_HINT_DELAY_FIFO0_T5)
2156 #define F_PERR_HINT_DELAY_FIFO0_T5    V_PERR_HINT_DELAY_FIFO0_T5(1U)
2157 
2158 #define S_PERR_IMSG_PD_FIFO_T5    21
2159 #define V_PERR_IMSG_PD_FIFO_T5(x) ((x) << S_PERR_IMSG_PD_FIFO_T5)
2160 #define F_PERR_IMSG_PD_FIFO_T5    V_PERR_IMSG_PD_FIFO_T5(1U)
2161 
2162 #define S_PERR_ULPTX_FIFO1_T5    20
2163 #define V_PERR_ULPTX_FIFO1_T5(x) ((x) << S_PERR_ULPTX_FIFO1_T5)
2164 #define F_PERR_ULPTX_FIFO1_T5    V_PERR_ULPTX_FIFO1_T5(1U)
2165 
2166 #define S_PERR_ULPTX_FIFO0_T5    19
2167 #define V_PERR_ULPTX_FIFO0_T5(x) ((x) << S_PERR_ULPTX_FIFO0_T5)
2168 #define F_PERR_ULPTX_FIFO0_T5    V_PERR_ULPTX_FIFO0_T5(1U)
2169 
2170 #define S_PERR_IDMA2IMSG_FIFO1_T5    18
2171 #define V_PERR_IDMA2IMSG_FIFO1_T5(x) ((x) << S_PERR_IDMA2IMSG_FIFO1_T5)
2172 #define F_PERR_IDMA2IMSG_FIFO1_T5    V_PERR_IDMA2IMSG_FIFO1_T5(1U)
2173 
2174 #define S_PERR_IDMA2IMSG_FIFO0_T5    17
2175 #define V_PERR_IDMA2IMSG_FIFO0_T5(x) ((x) << S_PERR_IDMA2IMSG_FIFO0_T5)
2176 #define F_PERR_IDMA2IMSG_FIFO0_T5    V_PERR_IDMA2IMSG_FIFO0_T5(1U)
2177 
2178 #define S_PERR_POINTER_DATA_FIFO0    16
2179 #define V_PERR_POINTER_DATA_FIFO0(x) ((x) << S_PERR_POINTER_DATA_FIFO0)
2180 #define F_PERR_POINTER_DATA_FIFO0    V_PERR_POINTER_DATA_FIFO0(1U)
2181 
2182 #define S_PERR_POINTER_DATA_FIFO1    15
2183 #define V_PERR_POINTER_DATA_FIFO1(x) ((x) << S_PERR_POINTER_DATA_FIFO1)
2184 #define F_PERR_POINTER_DATA_FIFO1    V_PERR_POINTER_DATA_FIFO1(1U)
2185 
2186 #define S_PERR_POINTER_HDR_FIFO0    14
2187 #define V_PERR_POINTER_HDR_FIFO0(x) ((x) << S_PERR_POINTER_HDR_FIFO0)
2188 #define F_PERR_POINTER_HDR_FIFO0    V_PERR_POINTER_HDR_FIFO0(1U)
2189 
2190 #define S_PERR_POINTER_HDR_FIFO1    13
2191 #define V_PERR_POINTER_HDR_FIFO1(x) ((x) << S_PERR_POINTER_HDR_FIFO1)
2192 #define F_PERR_POINTER_HDR_FIFO1    V_PERR_POINTER_HDR_FIFO1(1U)
2193 
2194 #define S_PERR_PAYLOAD_FIFO0    12
2195 #define V_PERR_PAYLOAD_FIFO0(x) ((x) << S_PERR_PAYLOAD_FIFO0)
2196 #define F_PERR_PAYLOAD_FIFO0    V_PERR_PAYLOAD_FIFO0(1U)
2197 
2198 #define S_PERR_PAYLOAD_FIFO1    11
2199 #define V_PERR_PAYLOAD_FIFO1(x) ((x) << S_PERR_PAYLOAD_FIFO1)
2200 #define F_PERR_PAYLOAD_FIFO1    V_PERR_PAYLOAD_FIFO1(1U)
2201 
2202 #define S_PERR_EDMA_INPUT_FIFO3    10
2203 #define V_PERR_EDMA_INPUT_FIFO3(x) ((x) << S_PERR_EDMA_INPUT_FIFO3)
2204 #define F_PERR_EDMA_INPUT_FIFO3    V_PERR_EDMA_INPUT_FIFO3(1U)
2205 
2206 #define S_PERR_EDMA_INPUT_FIFO2    9
2207 #define V_PERR_EDMA_INPUT_FIFO2(x) ((x) << S_PERR_EDMA_INPUT_FIFO2)
2208 #define F_PERR_EDMA_INPUT_FIFO2    V_PERR_EDMA_INPUT_FIFO2(1U)
2209 
2210 #define S_PERR_EDMA_INPUT_FIFO1    8
2211 #define V_PERR_EDMA_INPUT_FIFO1(x) ((x) << S_PERR_EDMA_INPUT_FIFO1)
2212 #define F_PERR_EDMA_INPUT_FIFO1    V_PERR_EDMA_INPUT_FIFO1(1U)
2213 
2214 #define S_PERR_EDMA_INPUT_FIFO0    7
2215 #define V_PERR_EDMA_INPUT_FIFO0(x) ((x) << S_PERR_EDMA_INPUT_FIFO0)
2216 #define F_PERR_EDMA_INPUT_FIFO0    V_PERR_EDMA_INPUT_FIFO0(1U)
2217 
2218 #define S_PERR_MGT_BAR2_FIFO    6
2219 #define V_PERR_MGT_BAR2_FIFO(x) ((x) << S_PERR_MGT_BAR2_FIFO)
2220 #define F_PERR_MGT_BAR2_FIFO    V_PERR_MGT_BAR2_FIFO(1U)
2221 
2222 #define S_PERR_HEADERSPLIT_FIFO1_T5    5
2223 #define V_PERR_HEADERSPLIT_FIFO1_T5(x) ((x) << S_PERR_HEADERSPLIT_FIFO1_T5)
2224 #define F_PERR_HEADERSPLIT_FIFO1_T5    V_PERR_HEADERSPLIT_FIFO1_T5(1U)
2225 
2226 #define S_PERR_HEADERSPLIT_FIFO0_T5    4
2227 #define V_PERR_HEADERSPLIT_FIFO0_T5(x) ((x) << S_PERR_HEADERSPLIT_FIFO0_T5)
2228 #define F_PERR_HEADERSPLIT_FIFO0_T5    V_PERR_HEADERSPLIT_FIFO0_T5(1U)
2229 
2230 #define S_PERR_CIM_FIFO1    3
2231 #define V_PERR_CIM_FIFO1(x) ((x) << S_PERR_CIM_FIFO1)
2232 #define F_PERR_CIM_FIFO1    V_PERR_CIM_FIFO1(1U)
2233 
2234 #define S_PERR_CIM_FIFO0    2
2235 #define V_PERR_CIM_FIFO0(x) ((x) << S_PERR_CIM_FIFO0)
2236 #define F_PERR_CIM_FIFO0    V_PERR_CIM_FIFO0(1U)
2237 
2238 #define S_PERR_IDMA_SWITCH_OUTPUT_FIFO1    1
2239 #define V_PERR_IDMA_SWITCH_OUTPUT_FIFO1(x) ((x) << S_PERR_IDMA_SWITCH_OUTPUT_FIFO1)
2240 #define F_PERR_IDMA_SWITCH_OUTPUT_FIFO1    V_PERR_IDMA_SWITCH_OUTPUT_FIFO1(1U)
2241 
2242 #define S_PERR_IDMA_SWITCH_OUTPUT_FIFO0    0
2243 #define V_PERR_IDMA_SWITCH_OUTPUT_FIFO0(x) ((x) << S_PERR_IDMA_SWITCH_OUTPUT_FIFO0)
2244 #define F_PERR_IDMA_SWITCH_OUTPUT_FIFO0    V_PERR_IDMA_SWITCH_OUTPUT_FIFO0(1U)
2245 
2246 #define A_SGE_INT_ENABLE5 0x1110
2247 #define A_SGE_PERR_ENABLE5 0x1114
2248 #define A_SGE_DBFIFO_STATUS2 0x1118
2249 
2250 #define S_FL_INT_THRESH    24
2251 #define M_FL_INT_THRESH    0xfU
2252 #define V_FL_INT_THRESH(x) ((x) << S_FL_INT_THRESH)
2253 #define G_FL_INT_THRESH(x) (((x) >> S_FL_INT_THRESH) & M_FL_INT_THRESH)
2254 
2255 #define S_FL_COUNT    14
2256 #define M_FL_COUNT    0x3ffU
2257 #define V_FL_COUNT(x) ((x) << S_FL_COUNT)
2258 #define G_FL_COUNT(x) (((x) >> S_FL_COUNT) & M_FL_COUNT)
2259 
2260 #define S_HP_INT_THRESH_T5    10
2261 #define M_HP_INT_THRESH_T5    0xfU
2262 #define V_HP_INT_THRESH_T5(x) ((x) << S_HP_INT_THRESH_T5)
2263 #define G_HP_INT_THRESH_T5(x) (((x) >> S_HP_INT_THRESH_T5) & M_HP_INT_THRESH_T5)
2264 
2265 #define S_HP_COUNT_T5    0
2266 #define M_HP_COUNT_T5    0x3ffU
2267 #define V_HP_COUNT_T5(x) ((x) << S_HP_COUNT_T5)
2268 #define G_HP_COUNT_T5(x) (((x) >> S_HP_COUNT_T5) & M_HP_COUNT_T5)
2269 
2270 #define A_SGE_FETCH_BURST_MAX_0_AND_1 0x111c
2271 
2272 #define S_FETCHBURSTMAX0    16
2273 #define M_FETCHBURSTMAX0    0x3ffU
2274 #define V_FETCHBURSTMAX0(x) ((x) << S_FETCHBURSTMAX0)
2275 #define G_FETCHBURSTMAX0(x) (((x) >> S_FETCHBURSTMAX0) & M_FETCHBURSTMAX0)
2276 
2277 #define S_FETCHBURSTMAX1    0
2278 #define M_FETCHBURSTMAX1    0x3ffU
2279 #define V_FETCHBURSTMAX1(x) ((x) << S_FETCHBURSTMAX1)
2280 #define G_FETCHBURSTMAX1(x) (((x) >> S_FETCHBURSTMAX1) & M_FETCHBURSTMAX1)
2281 
2282 #define A_SGE_FETCH_BURST_MAX_2_AND_3 0x1120
2283 
2284 #define S_FETCHBURSTMAX2    16
2285 #define M_FETCHBURSTMAX2    0x3ffU
2286 #define V_FETCHBURSTMAX2(x) ((x) << S_FETCHBURSTMAX2)
2287 #define G_FETCHBURSTMAX2(x) (((x) >> S_FETCHBURSTMAX2) & M_FETCHBURSTMAX2)
2288 
2289 #define S_FETCHBURSTMAX3    0
2290 #define M_FETCHBURSTMAX3    0x3ffU
2291 #define V_FETCHBURSTMAX3(x) ((x) << S_FETCHBURSTMAX3)
2292 #define G_FETCHBURSTMAX3(x) (((x) >> S_FETCHBURSTMAX3) & M_FETCHBURSTMAX3)
2293 
2294 #define A_SGE_CONTROL2 0x1124
2295 
2296 #define S_UPFLCUTOFFDIS    21
2297 #define V_UPFLCUTOFFDIS(x) ((x) << S_UPFLCUTOFFDIS)
2298 #define F_UPFLCUTOFFDIS    V_UPFLCUTOFFDIS(1U)
2299 
2300 #define S_RXCPLSIZEAUTOCORRECT    20
2301 #define V_RXCPLSIZEAUTOCORRECT(x) ((x) << S_RXCPLSIZEAUTOCORRECT)
2302 #define F_RXCPLSIZEAUTOCORRECT    V_RXCPLSIZEAUTOCORRECT(1U)
2303 
2304 #define S_IDMAARBROUNDROBIN    19
2305 #define V_IDMAARBROUNDROBIN(x) ((x) << S_IDMAARBROUNDROBIN)
2306 #define F_IDMAARBROUNDROBIN    V_IDMAARBROUNDROBIN(1U)
2307 
2308 #define S_INGPACKBOUNDARY    16
2309 #define M_INGPACKBOUNDARY    0x7U
2310 #define V_INGPACKBOUNDARY(x) ((x) << S_INGPACKBOUNDARY)
2311 #define G_INGPACKBOUNDARY(x) (((x) >> S_INGPACKBOUNDARY) & M_INGPACKBOUNDARY)
2312 
2313 #define S_CGEN_EGRESS_CONTEXT    15
2314 #define V_CGEN_EGRESS_CONTEXT(x) ((x) << S_CGEN_EGRESS_CONTEXT)
2315 #define F_CGEN_EGRESS_CONTEXT    V_CGEN_EGRESS_CONTEXT(1U)
2316 
2317 #define S_CGEN_INGRESS_CONTEXT    14
2318 #define V_CGEN_INGRESS_CONTEXT(x) ((x) << S_CGEN_INGRESS_CONTEXT)
2319 #define F_CGEN_INGRESS_CONTEXT    V_CGEN_INGRESS_CONTEXT(1U)
2320 
2321 #define S_CGEN_IDMA    13
2322 #define V_CGEN_IDMA(x) ((x) << S_CGEN_IDMA)
2323 #define F_CGEN_IDMA    V_CGEN_IDMA(1U)
2324 
2325 #define S_CGEN_DBP    12
2326 #define V_CGEN_DBP(x) ((x) << S_CGEN_DBP)
2327 #define F_CGEN_DBP    V_CGEN_DBP(1U)
2328 
2329 #define S_CGEN_EDMA    11
2330 #define V_CGEN_EDMA(x) ((x) << S_CGEN_EDMA)
2331 #define F_CGEN_EDMA    V_CGEN_EDMA(1U)
2332 
2333 #define S_VFIFO_ENABLE    10
2334 #define V_VFIFO_ENABLE(x) ((x) << S_VFIFO_ENABLE)
2335 #define F_VFIFO_ENABLE    V_VFIFO_ENABLE(1U)
2336 
2337 #define S_FLM_RESCHEDULE_MODE    9
2338 #define V_FLM_RESCHEDULE_MODE(x) ((x) << S_FLM_RESCHEDULE_MODE)
2339 #define F_FLM_RESCHEDULE_MODE    V_FLM_RESCHEDULE_MODE(1U)
2340 
2341 #define S_HINTDEPTHCTLFL    4
2342 #define M_HINTDEPTHCTLFL    0x1fU
2343 #define V_HINTDEPTHCTLFL(x) ((x) << S_HINTDEPTHCTLFL)
2344 #define G_HINTDEPTHCTLFL(x) (((x) >> S_HINTDEPTHCTLFL) & M_HINTDEPTHCTLFL)
2345 
2346 #define S_FORCE_ORDERING    3
2347 #define V_FORCE_ORDERING(x) ((x) << S_FORCE_ORDERING)
2348 #define F_FORCE_ORDERING    V_FORCE_ORDERING(1U)
2349 
2350 #define S_TX_COALESCE_SIZE    2
2351 #define V_TX_COALESCE_SIZE(x) ((x) << S_TX_COALESCE_SIZE)
2352 #define F_TX_COALESCE_SIZE    V_TX_COALESCE_SIZE(1U)
2353 
2354 #define S_COAL_STRICT_CIM_PRI    1
2355 #define V_COAL_STRICT_CIM_PRI(x) ((x) << S_COAL_STRICT_CIM_PRI)
2356 #define F_COAL_STRICT_CIM_PRI    V_COAL_STRICT_CIM_PRI(1U)
2357 
2358 #define S_TX_COALESCE_PRI    0
2359 #define V_TX_COALESCE_PRI(x) ((x) << S_TX_COALESCE_PRI)
2360 #define F_TX_COALESCE_PRI    V_TX_COALESCE_PRI(1U)
2361 
2362 #define A_SGE_DEEP_SLEEP 0x1128
2363 
2364 #define S_IDMA1_SLEEP_STATUS    11
2365 #define V_IDMA1_SLEEP_STATUS(x) ((x) << S_IDMA1_SLEEP_STATUS)
2366 #define F_IDMA1_SLEEP_STATUS    V_IDMA1_SLEEP_STATUS(1U)
2367 
2368 #define S_IDMA0_SLEEP_STATUS    10
2369 #define V_IDMA0_SLEEP_STATUS(x) ((x) << S_IDMA0_SLEEP_STATUS)
2370 #define F_IDMA0_SLEEP_STATUS    V_IDMA0_SLEEP_STATUS(1U)
2371 
2372 #define S_IDMA1_SLEEP_REQ    9
2373 #define V_IDMA1_SLEEP_REQ(x) ((x) << S_IDMA1_SLEEP_REQ)
2374 #define F_IDMA1_SLEEP_REQ    V_IDMA1_SLEEP_REQ(1U)
2375 
2376 #define S_IDMA0_SLEEP_REQ    8
2377 #define V_IDMA0_SLEEP_REQ(x) ((x) << S_IDMA0_SLEEP_REQ)
2378 #define F_IDMA0_SLEEP_REQ    V_IDMA0_SLEEP_REQ(1U)
2379 
2380 #define S_EDMA3_SLEEP_STATUS    7
2381 #define V_EDMA3_SLEEP_STATUS(x) ((x) << S_EDMA3_SLEEP_STATUS)
2382 #define F_EDMA3_SLEEP_STATUS    V_EDMA3_SLEEP_STATUS(1U)
2383 
2384 #define S_EDMA2_SLEEP_STATUS    6
2385 #define V_EDMA2_SLEEP_STATUS(x) ((x) << S_EDMA2_SLEEP_STATUS)
2386 #define F_EDMA2_SLEEP_STATUS    V_EDMA2_SLEEP_STATUS(1U)
2387 
2388 #define S_EDMA1_SLEEP_STATUS    5
2389 #define V_EDMA1_SLEEP_STATUS(x) ((x) << S_EDMA1_SLEEP_STATUS)
2390 #define F_EDMA1_SLEEP_STATUS    V_EDMA1_SLEEP_STATUS(1U)
2391 
2392 #define S_EDMA0_SLEEP_STATUS    4
2393 #define V_EDMA0_SLEEP_STATUS(x) ((x) << S_EDMA0_SLEEP_STATUS)
2394 #define F_EDMA0_SLEEP_STATUS    V_EDMA0_SLEEP_STATUS(1U)
2395 
2396 #define S_EDMA3_SLEEP_REQ    3
2397 #define V_EDMA3_SLEEP_REQ(x) ((x) << S_EDMA3_SLEEP_REQ)
2398 #define F_EDMA3_SLEEP_REQ    V_EDMA3_SLEEP_REQ(1U)
2399 
2400 #define S_EDMA2_SLEEP_REQ    2
2401 #define V_EDMA2_SLEEP_REQ(x) ((x) << S_EDMA2_SLEEP_REQ)
2402 #define F_EDMA2_SLEEP_REQ    V_EDMA2_SLEEP_REQ(1U)
2403 
2404 #define S_EDMA1_SLEEP_REQ    1
2405 #define V_EDMA1_SLEEP_REQ(x) ((x) << S_EDMA1_SLEEP_REQ)
2406 #define F_EDMA1_SLEEP_REQ    V_EDMA1_SLEEP_REQ(1U)
2407 
2408 #define S_EDMA0_SLEEP_REQ    0
2409 #define V_EDMA0_SLEEP_REQ(x) ((x) << S_EDMA0_SLEEP_REQ)
2410 #define F_EDMA0_SLEEP_REQ    V_EDMA0_SLEEP_REQ(1U)
2411 
2412 #define A_SGE_INT_CAUSE6 0x1128
2413 
2414 #define S_ERR_DB_SYNC    21
2415 #define V_ERR_DB_SYNC(x) ((x) << S_ERR_DB_SYNC)
2416 #define F_ERR_DB_SYNC    V_ERR_DB_SYNC(1U)
2417 
2418 #define S_ERR_GTS_SYNC    20
2419 #define V_ERR_GTS_SYNC(x) ((x) << S_ERR_GTS_SYNC)
2420 #define F_ERR_GTS_SYNC    V_ERR_GTS_SYNC(1U)
2421 
2422 #define S_FATAL_LARGE_COAL    19
2423 #define V_FATAL_LARGE_COAL(x) ((x) << S_FATAL_LARGE_COAL)
2424 #define F_FATAL_LARGE_COAL    V_FATAL_LARGE_COAL(1U)
2425 
2426 #define S_PL_BAR2_FRM_ERR    18
2427 #define V_PL_BAR2_FRM_ERR(x) ((x) << S_PL_BAR2_FRM_ERR)
2428 #define F_PL_BAR2_FRM_ERR    V_PL_BAR2_FRM_ERR(1U)
2429 
2430 #define S_SILENT_DROP_TX_COAL    17
2431 #define V_SILENT_DROP_TX_COAL(x) ((x) << S_SILENT_DROP_TX_COAL)
2432 #define F_SILENT_DROP_TX_COAL    V_SILENT_DROP_TX_COAL(1U)
2433 
2434 #define S_ERR_INV_CTXT4    16
2435 #define V_ERR_INV_CTXT4(x) ((x) << S_ERR_INV_CTXT4)
2436 #define F_ERR_INV_CTXT4    V_ERR_INV_CTXT4(1U)
2437 
2438 #define S_ERR_BAD_DB_PIDX4    15
2439 #define V_ERR_BAD_DB_PIDX4(x) ((x) << S_ERR_BAD_DB_PIDX4)
2440 #define F_ERR_BAD_DB_PIDX4    V_ERR_BAD_DB_PIDX4(1U)
2441 
2442 #define S_ERR_BAD_UPFL_INC_CREDIT4    14
2443 #define V_ERR_BAD_UPFL_INC_CREDIT4(x) ((x) << S_ERR_BAD_UPFL_INC_CREDIT4)
2444 #define F_ERR_BAD_UPFL_INC_CREDIT4    V_ERR_BAD_UPFL_INC_CREDIT4(1U)
2445 
2446 #define S_FATAL_TAG_MISMATCH    13
2447 #define V_FATAL_TAG_MISMATCH(x) ((x) << S_FATAL_TAG_MISMATCH)
2448 #define F_FATAL_TAG_MISMATCH    V_FATAL_TAG_MISMATCH(1U)
2449 
2450 #define S_FATAL_ENQ_CTL_RDY    12
2451 #define V_FATAL_ENQ_CTL_RDY(x) ((x) << S_FATAL_ENQ_CTL_RDY)
2452 #define F_FATAL_ENQ_CTL_RDY    V_FATAL_ENQ_CTL_RDY(1U)
2453 
2454 #define S_ERR_PC_RSP_LEN3    11
2455 #define V_ERR_PC_RSP_LEN3(x) ((x) << S_ERR_PC_RSP_LEN3)
2456 #define F_ERR_PC_RSP_LEN3    V_ERR_PC_RSP_LEN3(1U)
2457 
2458 #define S_ERR_PC_RSP_LEN2    10
2459 #define V_ERR_PC_RSP_LEN2(x) ((x) << S_ERR_PC_RSP_LEN2)
2460 #define F_ERR_PC_RSP_LEN2    V_ERR_PC_RSP_LEN2(1U)
2461 
2462 #define S_ERR_PC_RSP_LEN1    9
2463 #define V_ERR_PC_RSP_LEN1(x) ((x) << S_ERR_PC_RSP_LEN1)
2464 #define F_ERR_PC_RSP_LEN1    V_ERR_PC_RSP_LEN1(1U)
2465 
2466 #define S_ERR_PC_RSP_LEN0    8
2467 #define V_ERR_PC_RSP_LEN0(x) ((x) << S_ERR_PC_RSP_LEN0)
2468 #define F_ERR_PC_RSP_LEN0    V_ERR_PC_RSP_LEN0(1U)
2469 
2470 #define S_FATAL_ENQ2LL_VLD    7
2471 #define V_FATAL_ENQ2LL_VLD(x) ((x) << S_FATAL_ENQ2LL_VLD)
2472 #define F_FATAL_ENQ2LL_VLD    V_FATAL_ENQ2LL_VLD(1U)
2473 
2474 #define S_FATAL_LL_EMPTY    6
2475 #define V_FATAL_LL_EMPTY(x) ((x) << S_FATAL_LL_EMPTY)
2476 #define F_FATAL_LL_EMPTY    V_FATAL_LL_EMPTY(1U)
2477 
2478 #define S_FATAL_OFF_WDENQ    5
2479 #define V_FATAL_OFF_WDENQ(x) ((x) << S_FATAL_OFF_WDENQ)
2480 #define F_FATAL_OFF_WDENQ    V_FATAL_OFF_WDENQ(1U)
2481 
2482 #define S_FATAL_DEQ_DRDY    3
2483 #define M_FATAL_DEQ_DRDY    0x3U
2484 #define V_FATAL_DEQ_DRDY(x) ((x) << S_FATAL_DEQ_DRDY)
2485 #define G_FATAL_DEQ_DRDY(x) (((x) >> S_FATAL_DEQ_DRDY) & M_FATAL_DEQ_DRDY)
2486 
2487 #define S_FATAL_OUTP_DRDY    1
2488 #define M_FATAL_OUTP_DRDY    0x3U
2489 #define V_FATAL_OUTP_DRDY(x) ((x) << S_FATAL_OUTP_DRDY)
2490 #define G_FATAL_OUTP_DRDY(x) (((x) >> S_FATAL_OUTP_DRDY) & M_FATAL_OUTP_DRDY)
2491 
2492 #define S_FATAL_DEQ    0
2493 #define V_FATAL_DEQ(x) ((x) << S_FATAL_DEQ)
2494 #define F_FATAL_DEQ    V_FATAL_DEQ(1U)
2495 
2496 #define A_SGE_DOORBELL_THROTTLE_THRESHOLD 0x112c
2497 
2498 #define S_THROTTLE_THRESHOLD_FL    16
2499 #define M_THROTTLE_THRESHOLD_FL    0xfU
2500 #define V_THROTTLE_THRESHOLD_FL(x) ((x) << S_THROTTLE_THRESHOLD_FL)
2501 #define G_THROTTLE_THRESHOLD_FL(x) (((x) >> S_THROTTLE_THRESHOLD_FL) & M_THROTTLE_THRESHOLD_FL)
2502 
2503 #define S_THROTTLE_THRESHOLD_HP    12
2504 #define M_THROTTLE_THRESHOLD_HP    0xfU
2505 #define V_THROTTLE_THRESHOLD_HP(x) ((x) << S_THROTTLE_THRESHOLD_HP)
2506 #define G_THROTTLE_THRESHOLD_HP(x) (((x) >> S_THROTTLE_THRESHOLD_HP) & M_THROTTLE_THRESHOLD_HP)
2507 
2508 #define S_THROTTLE_THRESHOLD_LP    0
2509 #define M_THROTTLE_THRESHOLD_LP    0xfffU
2510 #define V_THROTTLE_THRESHOLD_LP(x) ((x) << S_THROTTLE_THRESHOLD_LP)
2511 #define G_THROTTLE_THRESHOLD_LP(x) (((x) >> S_THROTTLE_THRESHOLD_LP) & M_THROTTLE_THRESHOLD_LP)
2512 
2513 #define A_SGE_INT_ENABLE6 0x112c
2514 #define A_SGE_DBP_FETCH_THRESHOLD 0x1130
2515 
2516 #define S_DBP_FETCH_THRESHOLD_FL    21
2517 #define M_DBP_FETCH_THRESHOLD_FL    0xfU
2518 #define V_DBP_FETCH_THRESHOLD_FL(x) ((x) << S_DBP_FETCH_THRESHOLD_FL)
2519 #define G_DBP_FETCH_THRESHOLD_FL(x) (((x) >> S_DBP_FETCH_THRESHOLD_FL) & M_DBP_FETCH_THRESHOLD_FL)
2520 
2521 #define S_DBP_FETCH_THRESHOLD_HP    17
2522 #define M_DBP_FETCH_THRESHOLD_HP    0xfU
2523 #define V_DBP_FETCH_THRESHOLD_HP(x) ((x) << S_DBP_FETCH_THRESHOLD_HP)
2524 #define G_DBP_FETCH_THRESHOLD_HP(x) (((x) >> S_DBP_FETCH_THRESHOLD_HP) & M_DBP_FETCH_THRESHOLD_HP)
2525 
2526 #define S_DBP_FETCH_THRESHOLD_LP    5
2527 #define M_DBP_FETCH_THRESHOLD_LP    0xfffU
2528 #define V_DBP_FETCH_THRESHOLD_LP(x) ((x) << S_DBP_FETCH_THRESHOLD_LP)
2529 #define G_DBP_FETCH_THRESHOLD_LP(x) (((x) >> S_DBP_FETCH_THRESHOLD_LP) & M_DBP_FETCH_THRESHOLD_LP)
2530 
2531 #define S_DBP_FETCH_THRESHOLD_MODE    4
2532 #define V_DBP_FETCH_THRESHOLD_MODE(x) ((x) << S_DBP_FETCH_THRESHOLD_MODE)
2533 #define F_DBP_FETCH_THRESHOLD_MODE    V_DBP_FETCH_THRESHOLD_MODE(1U)
2534 
2535 #define S_DBP_FETCH_THRESHOLD_EN3    3
2536 #define V_DBP_FETCH_THRESHOLD_EN3(x) ((x) << S_DBP_FETCH_THRESHOLD_EN3)
2537 #define F_DBP_FETCH_THRESHOLD_EN3    V_DBP_FETCH_THRESHOLD_EN3(1U)
2538 
2539 #define S_DBP_FETCH_THRESHOLD_EN2    2
2540 #define V_DBP_FETCH_THRESHOLD_EN2(x) ((x) << S_DBP_FETCH_THRESHOLD_EN2)
2541 #define F_DBP_FETCH_THRESHOLD_EN2    V_DBP_FETCH_THRESHOLD_EN2(1U)
2542 
2543 #define S_DBP_FETCH_THRESHOLD_EN1    1
2544 #define V_DBP_FETCH_THRESHOLD_EN1(x) ((x) << S_DBP_FETCH_THRESHOLD_EN1)
2545 #define F_DBP_FETCH_THRESHOLD_EN1    V_DBP_FETCH_THRESHOLD_EN1(1U)
2546 
2547 #define S_DBP_FETCH_THRESHOLD_EN0    0
2548 #define V_DBP_FETCH_THRESHOLD_EN0(x) ((x) << S_DBP_FETCH_THRESHOLD_EN0)
2549 #define F_DBP_FETCH_THRESHOLD_EN0    V_DBP_FETCH_THRESHOLD_EN0(1U)
2550 
2551 #define A_SGE_DBP_FETCH_THRESHOLD_QUEUE 0x1134
2552 
2553 #define S_DBP_FETCH_THRESHOLD_IQ1    16
2554 #define M_DBP_FETCH_THRESHOLD_IQ1    0xffffU
2555 #define V_DBP_FETCH_THRESHOLD_IQ1(x) ((x) << S_DBP_FETCH_THRESHOLD_IQ1)
2556 #define G_DBP_FETCH_THRESHOLD_IQ1(x) (((x) >> S_DBP_FETCH_THRESHOLD_IQ1) & M_DBP_FETCH_THRESHOLD_IQ1)
2557 
2558 #define S_DBP_FETCH_THRESHOLD_IQ0    0
2559 #define M_DBP_FETCH_THRESHOLD_IQ0    0xffffU
2560 #define V_DBP_FETCH_THRESHOLD_IQ0(x) ((x) << S_DBP_FETCH_THRESHOLD_IQ0)
2561 #define G_DBP_FETCH_THRESHOLD_IQ0(x) (((x) >> S_DBP_FETCH_THRESHOLD_IQ0) & M_DBP_FETCH_THRESHOLD_IQ0)
2562 
2563 #define A_SGE_DBVFIFO_BADDR 0x1138
2564 #define A_SGE_DBVFIFO_SIZE 0x113c
2565 
2566 #define S_DBVFIFO_SIZE    6
2567 #define M_DBVFIFO_SIZE    0xfffU
2568 #define V_DBVFIFO_SIZE(x) ((x) << S_DBVFIFO_SIZE)
2569 #define G_DBVFIFO_SIZE(x) (((x) >> S_DBVFIFO_SIZE) & M_DBVFIFO_SIZE)
2570 
2571 #define S_T6_DBVFIFO_SIZE    0
2572 #define M_T6_DBVFIFO_SIZE    0x1fffU
2573 #define V_T6_DBVFIFO_SIZE(x) ((x) << S_T6_DBVFIFO_SIZE)
2574 #define G_T6_DBVFIFO_SIZE(x) (((x) >> S_T6_DBVFIFO_SIZE) & M_T6_DBVFIFO_SIZE)
2575 
2576 #define A_SGE_DBFIFO_STATUS3 0x1140
2577 
2578 #define S_LP_PTRS_EQUAL    21
2579 #define V_LP_PTRS_EQUAL(x) ((x) << S_LP_PTRS_EQUAL)
2580 #define F_LP_PTRS_EQUAL    V_LP_PTRS_EQUAL(1U)
2581 
2582 #define S_LP_SNAPHOT    20
2583 #define V_LP_SNAPHOT(x) ((x) << S_LP_SNAPHOT)
2584 #define F_LP_SNAPHOT    V_LP_SNAPHOT(1U)
2585 
2586 #define S_FL_INT_THRESH_LOW    16
2587 #define M_FL_INT_THRESH_LOW    0xfU
2588 #define V_FL_INT_THRESH_LOW(x) ((x) << S_FL_INT_THRESH_LOW)
2589 #define G_FL_INT_THRESH_LOW(x) (((x) >> S_FL_INT_THRESH_LOW) & M_FL_INT_THRESH_LOW)
2590 
2591 #define S_HP_INT_THRESH_LOW    12
2592 #define M_HP_INT_THRESH_LOW    0xfU
2593 #define V_HP_INT_THRESH_LOW(x) ((x) << S_HP_INT_THRESH_LOW)
2594 #define G_HP_INT_THRESH_LOW(x) (((x) >> S_HP_INT_THRESH_LOW) & M_HP_INT_THRESH_LOW)
2595 
2596 #define S_LP_INT_THRESH_LOW    0
2597 #define M_LP_INT_THRESH_LOW    0xfffU
2598 #define V_LP_INT_THRESH_LOW(x) ((x) << S_LP_INT_THRESH_LOW)
2599 #define G_LP_INT_THRESH_LOW(x) (((x) >> S_LP_INT_THRESH_LOW) & M_LP_INT_THRESH_LOW)
2600 
2601 #define A_SGE_CHANGESET 0x1144
2602 #define A_SGE_PC_RSP_ERROR 0x1148
2603 #define A_SGE_TBUF_CONTROL 0x114c
2604 
2605 #define S_DBPTBUFRSV1    9
2606 #define M_DBPTBUFRSV1    0x1ffU
2607 #define V_DBPTBUFRSV1(x) ((x) << S_DBPTBUFRSV1)
2608 #define G_DBPTBUFRSV1(x) (((x) >> S_DBPTBUFRSV1) & M_DBPTBUFRSV1)
2609 
2610 #define S_DBPTBUFRSV0    0
2611 #define M_DBPTBUFRSV0    0x1ffU
2612 #define V_DBPTBUFRSV0(x) ((x) << S_DBPTBUFRSV0)
2613 #define G_DBPTBUFRSV0(x) (((x) >> S_DBPTBUFRSV0) & M_DBPTBUFRSV0)
2614 
2615 #define A_SGE_PC0_REQ_BIST_CMD 0x1180
2616 #define A_SGE_PC0_REQ_BIST_ERROR_CNT 0x1184
2617 #define A_SGE_PC1_REQ_BIST_CMD 0x1190
2618 #define A_SGE_PC1_REQ_BIST_ERROR_CNT 0x1194
2619 #define A_SGE_PC0_RSP_BIST_CMD 0x11a0
2620 #define A_SGE_PC0_RSP_BIST_ERROR_CNT 0x11a4
2621 #define A_SGE_PC1_RSP_BIST_CMD 0x11b0
2622 #define A_SGE_PC1_RSP_BIST_ERROR_CNT 0x11b4
2623 #define A_SGE_CTXT_CMD 0x11fc
2624 
2625 #define S_BUSY    31
2626 #define V_BUSY(x) ((x) << S_BUSY)
2627 #define F_BUSY    V_BUSY(1U)
2628 
2629 #define S_CTXTOP    28
2630 #define M_CTXTOP    0x3U
2631 #define V_CTXTOP(x) ((x) << S_CTXTOP)
2632 #define G_CTXTOP(x) (((x) >> S_CTXTOP) & M_CTXTOP)
2633 
2634 #define S_CTXTTYPE    24
2635 #define M_CTXTTYPE    0x3U
2636 #define V_CTXTTYPE(x) ((x) << S_CTXTTYPE)
2637 #define G_CTXTTYPE(x) (((x) >> S_CTXTTYPE) & M_CTXTTYPE)
2638 
2639 #define S_CTXTQID    0
2640 #define M_CTXTQID    0x1ffffU
2641 #define V_CTXTQID(x) ((x) << S_CTXTQID)
2642 #define G_CTXTQID(x) (((x) >> S_CTXTQID) & M_CTXTQID)
2643 
2644 #define A_SGE_CTXT_DATA0 0x1200
2645 #define A_SGE_CTXT_DATA1 0x1204
2646 #define A_SGE_CTXT_DATA2 0x1208
2647 #define A_SGE_CTXT_DATA3 0x120c
2648 #define A_SGE_CTXT_DATA4 0x1210
2649 #define A_SGE_CTXT_DATA5 0x1214
2650 #define A_SGE_CTXT_DATA6 0x1218
2651 #define A_SGE_CTXT_DATA7 0x121c
2652 #define A_SGE_CTXT_MASK0 0x1220
2653 #define A_SGE_CTXT_MASK1 0x1224
2654 #define A_SGE_CTXT_MASK2 0x1228
2655 #define A_SGE_CTXT_MASK3 0x122c
2656 #define A_SGE_CTXT_MASK4 0x1230
2657 #define A_SGE_CTXT_MASK5 0x1234
2658 #define A_SGE_CTXT_MASK6 0x1238
2659 #define A_SGE_CTXT_MASK7 0x123c
2660 #define A_SGE_QBASE_MAP0 0x1240
2661 
2662 #define S_EGRESS0_SIZE    24
2663 #define M_EGRESS0_SIZE    0x1fU
2664 #define V_EGRESS0_SIZE(x) ((x) << S_EGRESS0_SIZE)
2665 #define G_EGRESS0_SIZE(x) (((x) >> S_EGRESS0_SIZE) & M_EGRESS0_SIZE)
2666 
2667 #define S_EGRESS1_SIZE    16
2668 #define M_EGRESS1_SIZE    0x1fU
2669 #define V_EGRESS1_SIZE(x) ((x) << S_EGRESS1_SIZE)
2670 #define G_EGRESS1_SIZE(x) (((x) >> S_EGRESS1_SIZE) & M_EGRESS1_SIZE)
2671 
2672 #define S_INGRESS0_SIZE    8
2673 #define M_INGRESS0_SIZE    0x1fU
2674 #define V_INGRESS0_SIZE(x) ((x) << S_INGRESS0_SIZE)
2675 #define G_INGRESS0_SIZE(x) (((x) >> S_INGRESS0_SIZE) & M_INGRESS0_SIZE)
2676 
2677 #define A_SGE_QBASE_MAP1 0x1244
2678 
2679 #define S_EGRESS0_BASE    0
2680 #define M_EGRESS0_BASE    0x1ffffU
2681 #define V_EGRESS0_BASE(x) ((x) << S_EGRESS0_BASE)
2682 #define G_EGRESS0_BASE(x) (((x) >> S_EGRESS0_BASE) & M_EGRESS0_BASE)
2683 
2684 #define A_SGE_QBASE_MAP2 0x1248
2685 
2686 #define S_EGRESS1_BASE    0
2687 #define M_EGRESS1_BASE    0x1ffffU
2688 #define V_EGRESS1_BASE(x) ((x) << S_EGRESS1_BASE)
2689 #define G_EGRESS1_BASE(x) (((x) >> S_EGRESS1_BASE) & M_EGRESS1_BASE)
2690 
2691 #define A_SGE_QBASE_MAP3 0x124c
2692 
2693 #define S_INGRESS1_BASE_256VF    16
2694 #define M_INGRESS1_BASE_256VF    0xffffU
2695 #define V_INGRESS1_BASE_256VF(x) ((x) << S_INGRESS1_BASE_256VF)
2696 #define G_INGRESS1_BASE_256VF(x) (((x) >> S_INGRESS1_BASE_256VF) & M_INGRESS1_BASE_256VF)
2697 
2698 #define S_INGRESS0_BASE    0
2699 #define M_INGRESS0_BASE    0xffffU
2700 #define V_INGRESS0_BASE(x) ((x) << S_INGRESS0_BASE)
2701 #define G_INGRESS0_BASE(x) (((x) >> S_INGRESS0_BASE) & M_INGRESS0_BASE)
2702 
2703 #define A_SGE_QBASE_INDEX 0x1250
2704 
2705 #define S_QIDX    0
2706 #define M_QIDX    0x1ffU
2707 #define V_QIDX(x) ((x) << S_QIDX)
2708 #define G_QIDX(x) (((x) >> S_QIDX) & M_QIDX)
2709 
2710 #define A_SGE_CONM_CTRL2 0x1254
2711 
2712 #define S_FLMTHRESHPACK    8
2713 #define M_FLMTHRESHPACK    0x7fU
2714 #define V_FLMTHRESHPACK(x) ((x) << S_FLMTHRESHPACK)
2715 #define G_FLMTHRESHPACK(x) (((x) >> S_FLMTHRESHPACK) & M_FLMTHRESHPACK)
2716 
2717 #define S_FLMTHRESH    0
2718 #define M_FLMTHRESH    0x7fU
2719 #define V_FLMTHRESH(x) ((x) << S_FLMTHRESH)
2720 #define G_FLMTHRESH(x) (((x) >> S_FLMTHRESH) & M_FLMTHRESH)
2721 
2722 #define A_SGE_DEBUG_CONM 0x1258
2723 
2724 #define S_MPS_CH_CNG    16
2725 #define M_MPS_CH_CNG    0xffffU
2726 #define V_MPS_CH_CNG(x) ((x) << S_MPS_CH_CNG)
2727 #define G_MPS_CH_CNG(x) (((x) >> S_MPS_CH_CNG) & M_MPS_CH_CNG)
2728 
2729 #define S_TP_CH_CNG    14
2730 #define M_TP_CH_CNG    0x3U
2731 #define V_TP_CH_CNG(x) ((x) << S_TP_CH_CNG)
2732 #define G_TP_CH_CNG(x) (((x) >> S_TP_CH_CNG) & M_TP_CH_CNG)
2733 
2734 #define S_ST_CONG    12
2735 #define M_ST_CONG    0x3U
2736 #define V_ST_CONG(x) ((x) << S_ST_CONG)
2737 #define G_ST_CONG(x) (((x) >> S_ST_CONG) & M_ST_CONG)
2738 
2739 #define S_LAST_XOFF    10
2740 #define V_LAST_XOFF(x) ((x) << S_LAST_XOFF)
2741 #define F_LAST_XOFF    V_LAST_XOFF(1U)
2742 
2743 #define S_LAST_QID    0
2744 #define M_LAST_QID    0x3ffU
2745 #define V_LAST_QID(x) ((x) << S_LAST_QID)
2746 #define G_LAST_QID(x) (((x) >> S_LAST_QID) & M_LAST_QID)
2747 
2748 #define A_SGE_DBG_QUEUE_STAT0_CTRL 0x125c
2749 
2750 #define S_IMSG_GTS_SEL    18
2751 #define V_IMSG_GTS_SEL(x) ((x) << S_IMSG_GTS_SEL)
2752 #define F_IMSG_GTS_SEL    V_IMSG_GTS_SEL(1U)
2753 
2754 #define S_MGT_SEL    17
2755 #define V_MGT_SEL(x) ((x) << S_MGT_SEL)
2756 #define F_MGT_SEL    V_MGT_SEL(1U)
2757 
2758 #define S_DB_GTS_QID    0
2759 #define M_DB_GTS_QID    0x1ffffU
2760 #define V_DB_GTS_QID(x) ((x) << S_DB_GTS_QID)
2761 #define G_DB_GTS_QID(x) (((x) >> S_DB_GTS_QID) & M_DB_GTS_QID)
2762 
2763 #define A_SGE_DBG_QUEUE_STAT1_CTRL 0x1260
2764 #define A_SGE_DBG_QUEUE_STAT0 0x1264
2765 #define A_SGE_DBG_QUEUE_STAT1 0x1268
2766 #define A_SGE_DBG_BAR2_PKT_CNT 0x126c
2767 #define A_SGE_DBG_DB_PKT_CNT 0x1270
2768 #define A_SGE_DBG_GTS_PKT_CNT 0x1274
2769 #define A_SGE_DEBUG_DATA_HIGH_INDEX_0 0x1280
2770 
2771 #define S_CIM_WM    24
2772 #define M_CIM_WM    0x3U
2773 #define V_CIM_WM(x) ((x) << S_CIM_WM)
2774 #define G_CIM_WM(x) (((x) >> S_CIM_WM) & M_CIM_WM)
2775 
2776 #define S_DEBUG_UP_SOP_CNT    20
2777 #define M_DEBUG_UP_SOP_CNT    0xfU
2778 #define V_DEBUG_UP_SOP_CNT(x) ((x) << S_DEBUG_UP_SOP_CNT)
2779 #define G_DEBUG_UP_SOP_CNT(x) (((x) >> S_DEBUG_UP_SOP_CNT) & M_DEBUG_UP_SOP_CNT)
2780 
2781 #define S_DEBUG_UP_EOP_CNT    16
2782 #define M_DEBUG_UP_EOP_CNT    0xfU
2783 #define V_DEBUG_UP_EOP_CNT(x) ((x) << S_DEBUG_UP_EOP_CNT)
2784 #define G_DEBUG_UP_EOP_CNT(x) (((x) >> S_DEBUG_UP_EOP_CNT) & M_DEBUG_UP_EOP_CNT)
2785 
2786 #define S_DEBUG_CIM_SOP1_CNT    12
2787 #define M_DEBUG_CIM_SOP1_CNT    0xfU
2788 #define V_DEBUG_CIM_SOP1_CNT(x) ((x) << S_DEBUG_CIM_SOP1_CNT)
2789 #define G_DEBUG_CIM_SOP1_CNT(x) (((x) >> S_DEBUG_CIM_SOP1_CNT) & M_DEBUG_CIM_SOP1_CNT)
2790 
2791 #define S_DEBUG_CIM_EOP1_CNT    8
2792 #define M_DEBUG_CIM_EOP1_CNT    0xfU
2793 #define V_DEBUG_CIM_EOP1_CNT(x) ((x) << S_DEBUG_CIM_EOP1_CNT)
2794 #define G_DEBUG_CIM_EOP1_CNT(x) (((x) >> S_DEBUG_CIM_EOP1_CNT) & M_DEBUG_CIM_EOP1_CNT)
2795 
2796 #define S_DEBUG_CIM_SOP0_CNT    4
2797 #define M_DEBUG_CIM_SOP0_CNT    0xfU
2798 #define V_DEBUG_CIM_SOP0_CNT(x) ((x) << S_DEBUG_CIM_SOP0_CNT)
2799 #define G_DEBUG_CIM_SOP0_CNT(x) (((x) >> S_DEBUG_CIM_SOP0_CNT) & M_DEBUG_CIM_SOP0_CNT)
2800 
2801 #define S_DEBUG_CIM_EOP0_CNT    0
2802 #define M_DEBUG_CIM_EOP0_CNT    0xfU
2803 #define V_DEBUG_CIM_EOP0_CNT(x) ((x) << S_DEBUG_CIM_EOP0_CNT)
2804 #define G_DEBUG_CIM_EOP0_CNT(x) (((x) >> S_DEBUG_CIM_EOP0_CNT) & M_DEBUG_CIM_EOP0_CNT)
2805 
2806 #define S_DEBUG_BAR2_SOP_CNT    28
2807 #define M_DEBUG_BAR2_SOP_CNT    0xfU
2808 #define V_DEBUG_BAR2_SOP_CNT(x) ((x) << S_DEBUG_BAR2_SOP_CNT)
2809 #define G_DEBUG_BAR2_SOP_CNT(x) (((x) >> S_DEBUG_BAR2_SOP_CNT) & M_DEBUG_BAR2_SOP_CNT)
2810 
2811 #define S_DEBUG_BAR2_EOP_CNT    24
2812 #define M_DEBUG_BAR2_EOP_CNT    0xfU
2813 #define V_DEBUG_BAR2_EOP_CNT(x) ((x) << S_DEBUG_BAR2_EOP_CNT)
2814 #define G_DEBUG_BAR2_EOP_CNT(x) (((x) >> S_DEBUG_BAR2_EOP_CNT) & M_DEBUG_BAR2_EOP_CNT)
2815 
2816 #define A_SGE_DEBUG_DATA_HIGH_INDEX_1 0x1284
2817 
2818 #define S_DEBUG_T_RX_SOP1_CNT    28
2819 #define M_DEBUG_T_RX_SOP1_CNT    0xfU
2820 #define V_DEBUG_T_RX_SOP1_CNT(x) ((x) << S_DEBUG_T_RX_SOP1_CNT)
2821 #define G_DEBUG_T_RX_SOP1_CNT(x) (((x) >> S_DEBUG_T_RX_SOP1_CNT) & M_DEBUG_T_RX_SOP1_CNT)
2822 
2823 #define S_DEBUG_T_RX_EOP1_CNT    24
2824 #define M_DEBUG_T_RX_EOP1_CNT    0xfU
2825 #define V_DEBUG_T_RX_EOP1_CNT(x) ((x) << S_DEBUG_T_RX_EOP1_CNT)
2826 #define G_DEBUG_T_RX_EOP1_CNT(x) (((x) >> S_DEBUG_T_RX_EOP1_CNT) & M_DEBUG_T_RX_EOP1_CNT)
2827 
2828 #define S_DEBUG_T_RX_SOP0_CNT    20
2829 #define M_DEBUG_T_RX_SOP0_CNT    0xfU
2830 #define V_DEBUG_T_RX_SOP0_CNT(x) ((x) << S_DEBUG_T_RX_SOP0_CNT)
2831 #define G_DEBUG_T_RX_SOP0_CNT(x) (((x) >> S_DEBUG_T_RX_SOP0_CNT) & M_DEBUG_T_RX_SOP0_CNT)
2832 
2833 #define S_DEBUG_T_RX_EOP0_CNT    16
2834 #define M_DEBUG_T_RX_EOP0_CNT    0xfU
2835 #define V_DEBUG_T_RX_EOP0_CNT(x) ((x) << S_DEBUG_T_RX_EOP0_CNT)
2836 #define G_DEBUG_T_RX_EOP0_CNT(x) (((x) >> S_DEBUG_T_RX_EOP0_CNT) & M_DEBUG_T_RX_EOP0_CNT)
2837 
2838 #define S_DEBUG_U_RX_SOP1_CNT    12
2839 #define M_DEBUG_U_RX_SOP1_CNT    0xfU
2840 #define V_DEBUG_U_RX_SOP1_CNT(x) ((x) << S_DEBUG_U_RX_SOP1_CNT)
2841 #define G_DEBUG_U_RX_SOP1_CNT(x) (((x) >> S_DEBUG_U_RX_SOP1_CNT) & M_DEBUG_U_RX_SOP1_CNT)
2842 
2843 #define S_DEBUG_U_RX_EOP1_CNT    8
2844 #define M_DEBUG_U_RX_EOP1_CNT    0xfU
2845 #define V_DEBUG_U_RX_EOP1_CNT(x) ((x) << S_DEBUG_U_RX_EOP1_CNT)
2846 #define G_DEBUG_U_RX_EOP1_CNT(x) (((x) >> S_DEBUG_U_RX_EOP1_CNT) & M_DEBUG_U_RX_EOP1_CNT)
2847 
2848 #define S_DEBUG_U_RX_SOP0_CNT    4
2849 #define M_DEBUG_U_RX_SOP0_CNT    0xfU
2850 #define V_DEBUG_U_RX_SOP0_CNT(x) ((x) << S_DEBUG_U_RX_SOP0_CNT)
2851 #define G_DEBUG_U_RX_SOP0_CNT(x) (((x) >> S_DEBUG_U_RX_SOP0_CNT) & M_DEBUG_U_RX_SOP0_CNT)
2852 
2853 #define S_DEBUG_U_RX_EOP0_CNT    0
2854 #define M_DEBUG_U_RX_EOP0_CNT    0xfU
2855 #define V_DEBUG_U_RX_EOP0_CNT(x) ((x) << S_DEBUG_U_RX_EOP0_CNT)
2856 #define G_DEBUG_U_RX_EOP0_CNT(x) (((x) >> S_DEBUG_U_RX_EOP0_CNT) & M_DEBUG_U_RX_EOP0_CNT)
2857 
2858 #define A_SGE_DEBUG_DATA_HIGH_INDEX_2 0x1288
2859 
2860 #define S_DEBUG_UD_RX_SOP3_CNT    28
2861 #define M_DEBUG_UD_RX_SOP3_CNT    0xfU
2862 #define V_DEBUG_UD_RX_SOP3_CNT(x) ((x) << S_DEBUG_UD_RX_SOP3_CNT)
2863 #define G_DEBUG_UD_RX_SOP3_CNT(x) (((x) >> S_DEBUG_UD_RX_SOP3_CNT) & M_DEBUG_UD_RX_SOP3_CNT)
2864 
2865 #define S_DEBUG_UD_RX_EOP3_CNT    24
2866 #define M_DEBUG_UD_RX_EOP3_CNT    0xfU
2867 #define V_DEBUG_UD_RX_EOP3_CNT(x) ((x) << S_DEBUG_UD_RX_EOP3_CNT)
2868 #define G_DEBUG_UD_RX_EOP3_CNT(x) (((x) >> S_DEBUG_UD_RX_EOP3_CNT) & M_DEBUG_UD_RX_EOP3_CNT)
2869 
2870 #define S_DEBUG_UD_RX_SOP2_CNT    20
2871 #define M_DEBUG_UD_RX_SOP2_CNT    0xfU
2872 #define V_DEBUG_UD_RX_SOP2_CNT(x) ((x) << S_DEBUG_UD_RX_SOP2_CNT)
2873 #define G_DEBUG_UD_RX_SOP2_CNT(x) (((x) >> S_DEBUG_UD_RX_SOP2_CNT) & M_DEBUG_UD_RX_SOP2_CNT)
2874 
2875 #define S_DEBUG_UD_RX_EOP2_CNT    16
2876 #define M_DEBUG_UD_RX_EOP2_CNT    0xfU
2877 #define V_DEBUG_UD_RX_EOP2_CNT(x) ((x) << S_DEBUG_UD_RX_EOP2_CNT)
2878 #define G_DEBUG_UD_RX_EOP2_CNT(x) (((x) >> S_DEBUG_UD_RX_EOP2_CNT) & M_DEBUG_UD_RX_EOP2_CNT)
2879 
2880 #define S_DEBUG_UD_RX_SOP1_CNT    12
2881 #define M_DEBUG_UD_RX_SOP1_CNT    0xfU
2882 #define V_DEBUG_UD_RX_SOP1_CNT(x) ((x) << S_DEBUG_UD_RX_SOP1_CNT)
2883 #define G_DEBUG_UD_RX_SOP1_CNT(x) (((x) >> S_DEBUG_UD_RX_SOP1_CNT) & M_DEBUG_UD_RX_SOP1_CNT)
2884 
2885 #define S_DEBUG_UD_RX_EOP1_CNT    8
2886 #define M_DEBUG_UD_RX_EOP1_CNT    0xfU
2887 #define V_DEBUG_UD_RX_EOP1_CNT(x) ((x) << S_DEBUG_UD_RX_EOP1_CNT)
2888 #define G_DEBUG_UD_RX_EOP1_CNT(x) (((x) >> S_DEBUG_UD_RX_EOP1_CNT) & M_DEBUG_UD_RX_EOP1_CNT)
2889 
2890 #define S_DEBUG_UD_RX_SOP0_CNT    4
2891 #define M_DEBUG_UD_RX_SOP0_CNT    0xfU
2892 #define V_DEBUG_UD_RX_SOP0_CNT(x) ((x) << S_DEBUG_UD_RX_SOP0_CNT)
2893 #define G_DEBUG_UD_RX_SOP0_CNT(x) (((x) >> S_DEBUG_UD_RX_SOP0_CNT) & M_DEBUG_UD_RX_SOP0_CNT)
2894 
2895 #define S_DEBUG_UD_RX_EOP0_CNT    0
2896 #define M_DEBUG_UD_RX_EOP0_CNT    0xfU
2897 #define V_DEBUG_UD_RX_EOP0_CNT(x) ((x) << S_DEBUG_UD_RX_EOP0_CNT)
2898 #define G_DEBUG_UD_RX_EOP0_CNT(x) (((x) >> S_DEBUG_UD_RX_EOP0_CNT) & M_DEBUG_UD_RX_EOP0_CNT)
2899 
2900 #define S_DBG_TBUF_USED1    9
2901 #define M_DBG_TBUF_USED1    0x1ffU
2902 #define V_DBG_TBUF_USED1(x) ((x) << S_DBG_TBUF_USED1)
2903 #define G_DBG_TBUF_USED1(x) (((x) >> S_DBG_TBUF_USED1) & M_DBG_TBUF_USED1)
2904 
2905 #define S_DBG_TBUF_USED0    0
2906 #define M_DBG_TBUF_USED0    0x1ffU
2907 #define V_DBG_TBUF_USED0(x) ((x) << S_DBG_TBUF_USED0)
2908 #define G_DBG_TBUF_USED0(x) (((x) >> S_DBG_TBUF_USED0) & M_DBG_TBUF_USED0)
2909 
2910 #define A_SGE_DEBUG_DATA_HIGH_INDEX_3 0x128c
2911 
2912 #define S_DEBUG_U_TX_SOP3_CNT    28
2913 #define M_DEBUG_U_TX_SOP3_CNT    0xfU
2914 #define V_DEBUG_U_TX_SOP3_CNT(x) ((x) << S_DEBUG_U_TX_SOP3_CNT)
2915 #define G_DEBUG_U_TX_SOP3_CNT(x) (((x) >> S_DEBUG_U_TX_SOP3_CNT) & M_DEBUG_U_TX_SOP3_CNT)
2916 
2917 #define S_DEBUG_U_TX_EOP3_CNT    24
2918 #define M_DEBUG_U_TX_EOP3_CNT    0xfU
2919 #define V_DEBUG_U_TX_EOP3_CNT(x) ((x) << S_DEBUG_U_TX_EOP3_CNT)
2920 #define G_DEBUG_U_TX_EOP3_CNT(x) (((x) >> S_DEBUG_U_TX_EOP3_CNT) & M_DEBUG_U_TX_EOP3_CNT)
2921 
2922 #define S_DEBUG_U_TX_SOP2_CNT    20
2923 #define M_DEBUG_U_TX_SOP2_CNT    0xfU
2924 #define V_DEBUG_U_TX_SOP2_CNT(x) ((x) << S_DEBUG_U_TX_SOP2_CNT)
2925 #define G_DEBUG_U_TX_SOP2_CNT(x) (((x) >> S_DEBUG_U_TX_SOP2_CNT) & M_DEBUG_U_TX_SOP2_CNT)
2926 
2927 #define S_DEBUG_U_TX_EOP2_CNT    16
2928 #define M_DEBUG_U_TX_EOP2_CNT    0xfU
2929 #define V_DEBUG_U_TX_EOP2_CNT(x) ((x) << S_DEBUG_U_TX_EOP2_CNT)
2930 #define G_DEBUG_U_TX_EOP2_CNT(x) (((x) >> S_DEBUG_U_TX_EOP2_CNT) & M_DEBUG_U_TX_EOP2_CNT)
2931 
2932 #define S_DEBUG_U_TX_SOP1_CNT    12
2933 #define M_DEBUG_U_TX_SOP1_CNT    0xfU
2934 #define V_DEBUG_U_TX_SOP1_CNT(x) ((x) << S_DEBUG_U_TX_SOP1_CNT)
2935 #define G_DEBUG_U_TX_SOP1_CNT(x) (((x) >> S_DEBUG_U_TX_SOP1_CNT) & M_DEBUG_U_TX_SOP1_CNT)
2936 
2937 #define S_DEBUG_U_TX_EOP1_CNT    8
2938 #define M_DEBUG_U_TX_EOP1_CNT    0xfU
2939 #define V_DEBUG_U_TX_EOP1_CNT(x) ((x) << S_DEBUG_U_TX_EOP1_CNT)
2940 #define G_DEBUG_U_TX_EOP1_CNT(x) (((x) >> S_DEBUG_U_TX_EOP1_CNT) & M_DEBUG_U_TX_EOP1_CNT)
2941 
2942 #define S_DEBUG_U_TX_SOP0_CNT    4
2943 #define M_DEBUG_U_TX_SOP0_CNT    0xfU
2944 #define V_DEBUG_U_TX_SOP0_CNT(x) ((x) << S_DEBUG_U_TX_SOP0_CNT)
2945 #define G_DEBUG_U_TX_SOP0_CNT(x) (((x) >> S_DEBUG_U_TX_SOP0_CNT) & M_DEBUG_U_TX_SOP0_CNT)
2946 
2947 #define S_DEBUG_U_TX_EOP0_CNT    0
2948 #define M_DEBUG_U_TX_EOP0_CNT    0xfU
2949 #define V_DEBUG_U_TX_EOP0_CNT(x) ((x) << S_DEBUG_U_TX_EOP0_CNT)
2950 #define G_DEBUG_U_TX_EOP0_CNT(x) (((x) >> S_DEBUG_U_TX_EOP0_CNT) & M_DEBUG_U_TX_EOP0_CNT)
2951 
2952 #define A_SGE_DEBUG1_DBP_THREAD 0x128c
2953 
2954 #define S_WR_DEQ_CNT    12
2955 #define M_WR_DEQ_CNT    0xfU
2956 #define V_WR_DEQ_CNT(x) ((x) << S_WR_DEQ_CNT)
2957 #define G_WR_DEQ_CNT(x) (((x) >> S_WR_DEQ_CNT) & M_WR_DEQ_CNT)
2958 
2959 #define S_WR_ENQ_CNT    8
2960 #define M_WR_ENQ_CNT    0xfU
2961 #define V_WR_ENQ_CNT(x) ((x) << S_WR_ENQ_CNT)
2962 #define G_WR_ENQ_CNT(x) (((x) >> S_WR_ENQ_CNT) & M_WR_ENQ_CNT)
2963 
2964 #define S_FL_DEQ_CNT    4
2965 #define M_FL_DEQ_CNT    0xfU
2966 #define V_FL_DEQ_CNT(x) ((x) << S_FL_DEQ_CNT)
2967 #define G_FL_DEQ_CNT(x) (((x) >> S_FL_DEQ_CNT) & M_FL_DEQ_CNT)
2968 
2969 #define S_FL_ENQ_CNT    0
2970 #define M_FL_ENQ_CNT    0xfU
2971 #define V_FL_ENQ_CNT(x) ((x) << S_FL_ENQ_CNT)
2972 #define G_FL_ENQ_CNT(x) (((x) >> S_FL_ENQ_CNT) & M_FL_ENQ_CNT)
2973 
2974 #define A_SGE_DEBUG_DATA_HIGH_INDEX_4 0x1290
2975 
2976 #define S_DEBUG_PC_RSP_SOP1_CNT    28
2977 #define M_DEBUG_PC_RSP_SOP1_CNT    0xfU
2978 #define V_DEBUG_PC_RSP_SOP1_CNT(x) ((x) << S_DEBUG_PC_RSP_SOP1_CNT)
2979 #define G_DEBUG_PC_RSP_SOP1_CNT(x) (((x) >> S_DEBUG_PC_RSP_SOP1_CNT) & M_DEBUG_PC_RSP_SOP1_CNT)
2980 
2981 #define S_DEBUG_PC_RSP_EOP1_CNT    24
2982 #define M_DEBUG_PC_RSP_EOP1_CNT    0xfU
2983 #define V_DEBUG_PC_RSP_EOP1_CNT(x) ((x) << S_DEBUG_PC_RSP_EOP1_CNT)
2984 #define G_DEBUG_PC_RSP_EOP1_CNT(x) (((x) >> S_DEBUG_PC_RSP_EOP1_CNT) & M_DEBUG_PC_RSP_EOP1_CNT)
2985 
2986 #define S_DEBUG_PC_RSP_SOP0_CNT    20
2987 #define M_DEBUG_PC_RSP_SOP0_CNT    0xfU
2988 #define V_DEBUG_PC_RSP_SOP0_CNT(x) ((x) << S_DEBUG_PC_RSP_SOP0_CNT)
2989 #define G_DEBUG_PC_RSP_SOP0_CNT(x) (((x) >> S_DEBUG_PC_RSP_SOP0_CNT) & M_DEBUG_PC_RSP_SOP0_CNT)
2990 
2991 #define S_DEBUG_PC_RSP_EOP0_CNT    16
2992 #define M_DEBUG_PC_RSP_EOP0_CNT    0xfU
2993 #define V_DEBUG_PC_RSP_EOP0_CNT(x) ((x) << S_DEBUG_PC_RSP_EOP0_CNT)
2994 #define G_DEBUG_PC_RSP_EOP0_CNT(x) (((x) >> S_DEBUG_PC_RSP_EOP0_CNT) & M_DEBUG_PC_RSP_EOP0_CNT)
2995 
2996 #define S_DEBUG_PC_REQ_SOP1_CNT    12
2997 #define M_DEBUG_PC_REQ_SOP1_CNT    0xfU
2998 #define V_DEBUG_PC_REQ_SOP1_CNT(x) ((x) << S_DEBUG_PC_REQ_SOP1_CNT)
2999 #define G_DEBUG_PC_REQ_SOP1_CNT(x) (((x) >> S_DEBUG_PC_REQ_SOP1_CNT) & M_DEBUG_PC_REQ_SOP1_CNT)
3000 
3001 #define S_DEBUG_PC_REQ_EOP1_CNT    8
3002 #define M_DEBUG_PC_REQ_EOP1_CNT    0xfU
3003 #define V_DEBUG_PC_REQ_EOP1_CNT(x) ((x) << S_DEBUG_PC_REQ_EOP1_CNT)
3004 #define G_DEBUG_PC_REQ_EOP1_CNT(x) (((x) >> S_DEBUG_PC_REQ_EOP1_CNT) & M_DEBUG_PC_REQ_EOP1_CNT)
3005 
3006 #define S_DEBUG_PC_REQ_SOP0_CNT    4
3007 #define M_DEBUG_PC_REQ_SOP0_CNT    0xfU
3008 #define V_DEBUG_PC_REQ_SOP0_CNT(x) ((x) << S_DEBUG_PC_REQ_SOP0_CNT)
3009 #define G_DEBUG_PC_REQ_SOP0_CNT(x) (((x) >> S_DEBUG_PC_REQ_SOP0_CNT) & M_DEBUG_PC_REQ_SOP0_CNT)
3010 
3011 #define S_DEBUG_PC_REQ_EOP0_CNT    0
3012 #define M_DEBUG_PC_REQ_EOP0_CNT    0xfU
3013 #define V_DEBUG_PC_REQ_EOP0_CNT(x) ((x) << S_DEBUG_PC_REQ_EOP0_CNT)
3014 #define G_DEBUG_PC_REQ_EOP0_CNT(x) (((x) >> S_DEBUG_PC_REQ_EOP0_CNT) & M_DEBUG_PC_REQ_EOP0_CNT)
3015 
3016 #define A_SGE_DEBUG_DATA_HIGH_INDEX_5 0x1294
3017 
3018 #define S_DEBUG_PD_RDREQ_SOP3_CNT    28
3019 #define M_DEBUG_PD_RDREQ_SOP3_CNT    0xfU
3020 #define V_DEBUG_PD_RDREQ_SOP3_CNT(x) ((x) << S_DEBUG_PD_RDREQ_SOP3_CNT)
3021 #define G_DEBUG_PD_RDREQ_SOP3_CNT(x) (((x) >> S_DEBUG_PD_RDREQ_SOP3_CNT) & M_DEBUG_PD_RDREQ_SOP3_CNT)
3022 
3023 #define S_DEBUG_PD_RDREQ_EOP3_CNT    24
3024 #define M_DEBUG_PD_RDREQ_EOP3_CNT    0xfU
3025 #define V_DEBUG_PD_RDREQ_EOP3_CNT(x) ((x) << S_DEBUG_PD_RDREQ_EOP3_CNT)
3026 #define G_DEBUG_PD_RDREQ_EOP3_CNT(x) (((x) >> S_DEBUG_PD_RDREQ_EOP3_CNT) & M_DEBUG_PD_RDREQ_EOP3_CNT)
3027 
3028 #define S_DEBUG_PD_RDREQ_SOP2_CNT    20
3029 #define M_DEBUG_PD_RDREQ_SOP2_CNT    0xfU
3030 #define V_DEBUG_PD_RDREQ_SOP2_CNT(x) ((x) << S_DEBUG_PD_RDREQ_SOP2_CNT)
3031 #define G_DEBUG_PD_RDREQ_SOP2_CNT(x) (((x) >> S_DEBUG_PD_RDREQ_SOP2_CNT) & M_DEBUG_PD_RDREQ_SOP2_CNT)
3032 
3033 #define S_DEBUG_PD_RDREQ_EOP2_CNT    16
3034 #define M_DEBUG_PD_RDREQ_EOP2_CNT    0xfU
3035 #define V_DEBUG_PD_RDREQ_EOP2_CNT(x) ((x) << S_DEBUG_PD_RDREQ_EOP2_CNT)
3036 #define G_DEBUG_PD_RDREQ_EOP2_CNT(x) (((x) >> S_DEBUG_PD_RDREQ_EOP2_CNT) & M_DEBUG_PD_RDREQ_EOP2_CNT)
3037 
3038 #define S_DEBUG_PD_RDREQ_SOP1_CNT    12
3039 #define M_DEBUG_PD_RDREQ_SOP1_CNT    0xfU
3040 #define V_DEBUG_PD_RDREQ_SOP1_CNT(x) ((x) << S_DEBUG_PD_RDREQ_SOP1_CNT)
3041 #define G_DEBUG_PD_RDREQ_SOP1_CNT(x) (((x) >> S_DEBUG_PD_RDREQ_SOP1_CNT) & M_DEBUG_PD_RDREQ_SOP1_CNT)
3042 
3043 #define S_DEBUG_PD_RDREQ_EOP1_CNT    8
3044 #define M_DEBUG_PD_RDREQ_EOP1_CNT    0xfU
3045 #define V_DEBUG_PD_RDREQ_EOP1_CNT(x) ((x) << S_DEBUG_PD_RDREQ_EOP1_CNT)
3046 #define G_DEBUG_PD_RDREQ_EOP1_CNT(x) (((x) >> S_DEBUG_PD_RDREQ_EOP1_CNT) & M_DEBUG_PD_RDREQ_EOP1_CNT)
3047 
3048 #define S_DEBUG_PD_RDREQ_SOP0_CNT    4
3049 #define M_DEBUG_PD_RDREQ_SOP0_CNT    0xfU
3050 #define V_DEBUG_PD_RDREQ_SOP0_CNT(x) ((x) << S_DEBUG_PD_RDREQ_SOP0_CNT)
3051 #define G_DEBUG_PD_RDREQ_SOP0_CNT(x) (((x) >> S_DEBUG_PD_RDREQ_SOP0_CNT) & M_DEBUG_PD_RDREQ_SOP0_CNT)
3052 
3053 #define S_DEBUG_PD_RDREQ_EOP0_CNT    0
3054 #define M_DEBUG_PD_RDREQ_EOP0_CNT    0xfU
3055 #define V_DEBUG_PD_RDREQ_EOP0_CNT(x) ((x) << S_DEBUG_PD_RDREQ_EOP0_CNT)
3056 #define G_DEBUG_PD_RDREQ_EOP0_CNT(x) (((x) >> S_DEBUG_PD_RDREQ_EOP0_CNT) & M_DEBUG_PD_RDREQ_EOP0_CNT)
3057 
3058 #define A_SGE_DEBUG_DATA_HIGH_INDEX_6 0x1298
3059 
3060 #define S_DEBUG_PD_RDRSP_SOP3_CNT    28
3061 #define M_DEBUG_PD_RDRSP_SOP3_CNT    0xfU
3062 #define V_DEBUG_PD_RDRSP_SOP3_CNT(x) ((x) << S_DEBUG_PD_RDRSP_SOP3_CNT)
3063 #define G_DEBUG_PD_RDRSP_SOP3_CNT(x) (((x) >> S_DEBUG_PD_RDRSP_SOP3_CNT) & M_DEBUG_PD_RDRSP_SOP3_CNT)
3064 
3065 #define S_DEBUG_PD_RDRSP_EOP3_CNT    24
3066 #define M_DEBUG_PD_RDRSP_EOP3_CNT    0xfU
3067 #define V_DEBUG_PD_RDRSP_EOP3_CNT(x) ((x) << S_DEBUG_PD_RDRSP_EOP3_CNT)
3068 #define G_DEBUG_PD_RDRSP_EOP3_CNT(x) (((x) >> S_DEBUG_PD_RDRSP_EOP3_CNT) & M_DEBUG_PD_RDRSP_EOP3_CNT)
3069 
3070 #define S_DEBUG_PD_RDRSP_SOP2_CNT    20
3071 #define M_DEBUG_PD_RDRSP_SOP2_CNT    0xfU
3072 #define V_DEBUG_PD_RDRSP_SOP2_CNT(x) ((x) << S_DEBUG_PD_RDRSP_SOP2_CNT)
3073 #define G_DEBUG_PD_RDRSP_SOP2_CNT(x) (((x) >> S_DEBUG_PD_RDRSP_SOP2_CNT) & M_DEBUG_PD_RDRSP_SOP2_CNT)
3074 
3075 #define S_DEBUG_PD_RDRSP_EOP2_CNT    16
3076 #define M_DEBUG_PD_RDRSP_EOP2_CNT    0xfU
3077 #define V_DEBUG_PD_RDRSP_EOP2_CNT(x) ((x) << S_DEBUG_PD_RDRSP_EOP2_CNT)
3078 #define G_DEBUG_PD_RDRSP_EOP2_CNT(x) (((x) >> S_DEBUG_PD_RDRSP_EOP2_CNT) & M_DEBUG_PD_RDRSP_EOP2_CNT)
3079 
3080 #define S_DEBUG_PD_RDRSP_SOP1_CNT    12
3081 #define M_DEBUG_PD_RDRSP_SOP1_CNT    0xfU
3082 #define V_DEBUG_PD_RDRSP_SOP1_CNT(x) ((x) << S_DEBUG_PD_RDRSP_SOP1_CNT)
3083 #define G_DEBUG_PD_RDRSP_SOP1_CNT(x) (((x) >> S_DEBUG_PD_RDRSP_SOP1_CNT) & M_DEBUG_PD_RDRSP_SOP1_CNT)
3084 
3085 #define S_DEBUG_PD_RDRSP_EOP1_CNT    8
3086 #define M_DEBUG_PD_RDRSP_EOP1_CNT    0xfU
3087 #define V_DEBUG_PD_RDRSP_EOP1_CNT(x) ((x) << S_DEBUG_PD_RDRSP_EOP1_CNT)
3088 #define G_DEBUG_PD_RDRSP_EOP1_CNT(x) (((x) >> S_DEBUG_PD_RDRSP_EOP1_CNT) & M_DEBUG_PD_RDRSP_EOP1_CNT)
3089 
3090 #define S_DEBUG_PD_RDRSP_SOP0_CNT    4
3091 #define M_DEBUG_PD_RDRSP_SOP0_CNT    0xfU
3092 #define V_DEBUG_PD_RDRSP_SOP0_CNT(x) ((x) << S_DEBUG_PD_RDRSP_SOP0_CNT)
3093 #define G_DEBUG_PD_RDRSP_SOP0_CNT(x) (((x) >> S_DEBUG_PD_RDRSP_SOP0_CNT) & M_DEBUG_PD_RDRSP_SOP0_CNT)
3094 
3095 #define S_DEBUG_PD_RDRSP_EOP0_CNT    0
3096 #define M_DEBUG_PD_RDRSP_EOP0_CNT    0xfU
3097 #define V_DEBUG_PD_RDRSP_EOP0_CNT(x) ((x) << S_DEBUG_PD_RDRSP_EOP0_CNT)
3098 #define G_DEBUG_PD_RDRSP_EOP0_CNT(x) (((x) >> S_DEBUG_PD_RDRSP_EOP0_CNT) & M_DEBUG_PD_RDRSP_EOP0_CNT)
3099 
3100 #define A_SGE_DEBUG_DATA_HIGH_INDEX_7 0x129c
3101 
3102 #define S_DEBUG_PD_WRREQ_SOP3_CNT    28
3103 #define M_DEBUG_PD_WRREQ_SOP3_CNT    0xfU
3104 #define V_DEBUG_PD_WRREQ_SOP3_CNT(x) ((x) << S_DEBUG_PD_WRREQ_SOP3_CNT)
3105 #define G_DEBUG_PD_WRREQ_SOP3_CNT(x) (((x) >> S_DEBUG_PD_WRREQ_SOP3_CNT) & M_DEBUG_PD_WRREQ_SOP3_CNT)
3106 
3107 #define S_DEBUG_PD_WRREQ_EOP3_CNT    24
3108 #define M_DEBUG_PD_WRREQ_EOP3_CNT    0xfU
3109 #define V_DEBUG_PD_WRREQ_EOP3_CNT(x) ((x) << S_DEBUG_PD_WRREQ_EOP3_CNT)
3110 #define G_DEBUG_PD_WRREQ_EOP3_CNT(x) (((x) >> S_DEBUG_PD_WRREQ_EOP3_CNT) & M_DEBUG_PD_WRREQ_EOP3_CNT)
3111 
3112 #define S_DEBUG_PD_WRREQ_SOP2_CNT    20
3113 #define M_DEBUG_PD_WRREQ_SOP2_CNT    0xfU
3114 #define V_DEBUG_PD_WRREQ_SOP2_CNT(x) ((x) << S_DEBUG_PD_WRREQ_SOP2_CNT)
3115 #define G_DEBUG_PD_WRREQ_SOP2_CNT(x) (((x) >> S_DEBUG_PD_WRREQ_SOP2_CNT) & M_DEBUG_PD_WRREQ_SOP2_CNT)
3116 
3117 #define S_DEBUG_PD_WRREQ_EOP2_CNT    16
3118 #define M_DEBUG_PD_WRREQ_EOP2_CNT    0xfU
3119 #define V_DEBUG_PD_WRREQ_EOP2_CNT(x) ((x) << S_DEBUG_PD_WRREQ_EOP2_CNT)
3120 #define G_DEBUG_PD_WRREQ_EOP2_CNT(x) (((x) >> S_DEBUG_PD_WRREQ_EOP2_CNT) & M_DEBUG_PD_WRREQ_EOP2_CNT)
3121 
3122 #define S_DEBUG_PD_WRREQ_SOP1_CNT    12
3123 #define M_DEBUG_PD_WRREQ_SOP1_CNT    0xfU
3124 #define V_DEBUG_PD_WRREQ_SOP1_CNT(x) ((x) << S_DEBUG_PD_WRREQ_SOP1_CNT)
3125 #define G_DEBUG_PD_WRREQ_SOP1_CNT(x) (((x) >> S_DEBUG_PD_WRREQ_SOP1_CNT) & M_DEBUG_PD_WRREQ_SOP1_CNT)
3126 
3127 #define S_DEBUG_PD_WRREQ_EOP1_CNT    8
3128 #define M_DEBUG_PD_WRREQ_EOP1_CNT    0xfU
3129 #define V_DEBUG_PD_WRREQ_EOP1_CNT(x) ((x) << S_DEBUG_PD_WRREQ_EOP1_CNT)
3130 #define G_DEBUG_PD_WRREQ_EOP1_CNT(x) (((x) >> S_DEBUG_PD_WRREQ_EOP1_CNT) & M_DEBUG_PD_WRREQ_EOP1_CNT)
3131 
3132 #define S_DEBUG_PD_WRREQ_SOP0_CNT    4
3133 #define M_DEBUG_PD_WRREQ_SOP0_CNT    0xfU
3134 #define V_DEBUG_PD_WRREQ_SOP0_CNT(x) ((x) << S_DEBUG_PD_WRREQ_SOP0_CNT)
3135 #define G_DEBUG_PD_WRREQ_SOP0_CNT(x) (((x) >> S_DEBUG_PD_WRREQ_SOP0_CNT) & M_DEBUG_PD_WRREQ_SOP0_CNT)
3136 
3137 #define S_DEBUG_PD_WRREQ_EOP0_CNT    0
3138 #define M_DEBUG_PD_WRREQ_EOP0_CNT    0xfU
3139 #define V_DEBUG_PD_WRREQ_EOP0_CNT(x) ((x) << S_DEBUG_PD_WRREQ_EOP0_CNT)
3140 #define G_DEBUG_PD_WRREQ_EOP0_CNT(x) (((x) >> S_DEBUG_PD_WRREQ_EOP0_CNT) & M_DEBUG_PD_WRREQ_EOP0_CNT)
3141 
3142 #define S_DEBUG_PC_RSP_SOP_CNT    28
3143 #define M_DEBUG_PC_RSP_SOP_CNT    0xfU
3144 #define V_DEBUG_PC_RSP_SOP_CNT(x) ((x) << S_DEBUG_PC_RSP_SOP_CNT)
3145 #define G_DEBUG_PC_RSP_SOP_CNT(x) (((x) >> S_DEBUG_PC_RSP_SOP_CNT) & M_DEBUG_PC_RSP_SOP_CNT)
3146 
3147 #define S_DEBUG_PC_RSP_EOP_CNT    24
3148 #define M_DEBUG_PC_RSP_EOP_CNT    0xfU
3149 #define V_DEBUG_PC_RSP_EOP_CNT(x) ((x) << S_DEBUG_PC_RSP_EOP_CNT)
3150 #define G_DEBUG_PC_RSP_EOP_CNT(x) (((x) >> S_DEBUG_PC_RSP_EOP_CNT) & M_DEBUG_PC_RSP_EOP_CNT)
3151 
3152 #define S_DEBUG_PC_REQ_SOP_CNT    20
3153 #define M_DEBUG_PC_REQ_SOP_CNT    0xfU
3154 #define V_DEBUG_PC_REQ_SOP_CNT(x) ((x) << S_DEBUG_PC_REQ_SOP_CNT)
3155 #define G_DEBUG_PC_REQ_SOP_CNT(x) (((x) >> S_DEBUG_PC_REQ_SOP_CNT) & M_DEBUG_PC_REQ_SOP_CNT)
3156 
3157 #define S_DEBUG_PC_REQ_EOP_CNT    16
3158 #define M_DEBUG_PC_REQ_EOP_CNT    0xfU
3159 #define V_DEBUG_PC_REQ_EOP_CNT(x) ((x) << S_DEBUG_PC_REQ_EOP_CNT)
3160 #define G_DEBUG_PC_REQ_EOP_CNT(x) (((x) >> S_DEBUG_PC_REQ_EOP_CNT) & M_DEBUG_PC_REQ_EOP_CNT)
3161 
3162 #define A_SGE_DEBUG_DATA_HIGH_INDEX_8 0x12a0
3163 
3164 #define S_GLOBALENABLE_OFF    29
3165 #define V_GLOBALENABLE_OFF(x) ((x) << S_GLOBALENABLE_OFF)
3166 #define F_GLOBALENABLE_OFF    V_GLOBALENABLE_OFF(1U)
3167 
3168 #define S_DEBUG_CIM2SGE_RXAFULL_D    27
3169 #define M_DEBUG_CIM2SGE_RXAFULL_D    0x3U
3170 #define V_DEBUG_CIM2SGE_RXAFULL_D(x) ((x) << S_DEBUG_CIM2SGE_RXAFULL_D)
3171 #define G_DEBUG_CIM2SGE_RXAFULL_D(x) (((x) >> S_DEBUG_CIM2SGE_RXAFULL_D) & M_DEBUG_CIM2SGE_RXAFULL_D)
3172 
3173 #define S_DEBUG_CPLSW_CIM_TXAFULL_D    25
3174 #define M_DEBUG_CPLSW_CIM_TXAFULL_D    0x3U
3175 #define V_DEBUG_CPLSW_CIM_TXAFULL_D(x) ((x) << S_DEBUG_CPLSW_CIM_TXAFULL_D)
3176 #define G_DEBUG_CPLSW_CIM_TXAFULL_D(x) (((x) >> S_DEBUG_CPLSW_CIM_TXAFULL_D) & M_DEBUG_CPLSW_CIM_TXAFULL_D)
3177 
3178 #define S_DEBUG_UP_FULL    24
3179 #define V_DEBUG_UP_FULL(x) ((x) << S_DEBUG_UP_FULL)
3180 #define F_DEBUG_UP_FULL    V_DEBUG_UP_FULL(1U)
3181 
3182 #define S_DEBUG_M_RD_REQ_OUTSTANDING_PC    23
3183 #define V_DEBUG_M_RD_REQ_OUTSTANDING_PC(x) ((x) << S_DEBUG_M_RD_REQ_OUTSTANDING_PC)
3184 #define F_DEBUG_M_RD_REQ_OUTSTANDING_PC    V_DEBUG_M_RD_REQ_OUTSTANDING_PC(1U)
3185 
3186 #define S_DEBUG_M_RD_REQ_OUTSTANDING_VFIFO    22
3187 #define V_DEBUG_M_RD_REQ_OUTSTANDING_VFIFO(x) ((x) << S_DEBUG_M_RD_REQ_OUTSTANDING_VFIFO)
3188 #define F_DEBUG_M_RD_REQ_OUTSTANDING_VFIFO    V_DEBUG_M_RD_REQ_OUTSTANDING_VFIFO(1U)
3189 
3190 #define S_DEBUG_M_RD_REQ_OUTSTANDING_IMSG    21
3191 #define V_DEBUG_M_RD_REQ_OUTSTANDING_IMSG(x) ((x) << S_DEBUG_M_RD_REQ_OUTSTANDING_IMSG)
3192 #define F_DEBUG_M_RD_REQ_OUTSTANDING_IMSG    V_DEBUG_M_RD_REQ_OUTSTANDING_IMSG(1U)
3193 
3194 #define S_DEBUG_M_RD_REQ_OUTSTANDING_CMARB    20
3195 #define V_DEBUG_M_RD_REQ_OUTSTANDING_CMARB(x) ((x) << S_DEBUG_M_RD_REQ_OUTSTANDING_CMARB)
3196 #define F_DEBUG_M_RD_REQ_OUTSTANDING_CMARB    V_DEBUG_M_RD_REQ_OUTSTANDING_CMARB(1U)
3197 
3198 #define S_DEBUG_M_RD_REQ_OUTSTANDING_FLM    19
3199 #define V_DEBUG_M_RD_REQ_OUTSTANDING_FLM(x) ((x) << S_DEBUG_M_RD_REQ_OUTSTANDING_FLM)
3200 #define F_DEBUG_M_RD_REQ_OUTSTANDING_FLM    V_DEBUG_M_RD_REQ_OUTSTANDING_FLM(1U)
3201 
3202 #define S_DEBUG_M_REQVLD    18
3203 #define V_DEBUG_M_REQVLD(x) ((x) << S_DEBUG_M_REQVLD)
3204 #define F_DEBUG_M_REQVLD    V_DEBUG_M_REQVLD(1U)
3205 
3206 #define S_DEBUG_M_REQRDY    17
3207 #define V_DEBUG_M_REQRDY(x) ((x) << S_DEBUG_M_REQRDY)
3208 #define F_DEBUG_M_REQRDY    V_DEBUG_M_REQRDY(1U)
3209 
3210 #define S_DEBUG_M_RSPVLD    16
3211 #define V_DEBUG_M_RSPVLD(x) ((x) << S_DEBUG_M_RSPVLD)
3212 #define F_DEBUG_M_RSPVLD    V_DEBUG_M_RSPVLD(1U)
3213 
3214 #define S_DEBUG_PD_WRREQ_INT3_CNT    12
3215 #define M_DEBUG_PD_WRREQ_INT3_CNT    0xfU
3216 #define V_DEBUG_PD_WRREQ_INT3_CNT(x) ((x) << S_DEBUG_PD_WRREQ_INT3_CNT)
3217 #define G_DEBUG_PD_WRREQ_INT3_CNT(x) (((x) >> S_DEBUG_PD_WRREQ_INT3_CNT) & M_DEBUG_PD_WRREQ_INT3_CNT)
3218 
3219 #define S_DEBUG_PD_WRREQ_INT2_CNT    8
3220 #define M_DEBUG_PD_WRREQ_INT2_CNT    0xfU
3221 #define V_DEBUG_PD_WRREQ_INT2_CNT(x) ((x) << S_DEBUG_PD_WRREQ_INT2_CNT)
3222 #define G_DEBUG_PD_WRREQ_INT2_CNT(x) (((x) >> S_DEBUG_PD_WRREQ_INT2_CNT) & M_DEBUG_PD_WRREQ_INT2_CNT)
3223 
3224 #define S_DEBUG_PD_WRREQ_INT1_CNT    4
3225 #define M_DEBUG_PD_WRREQ_INT1_CNT    0xfU
3226 #define V_DEBUG_PD_WRREQ_INT1_CNT(x) ((x) << S_DEBUG_PD_WRREQ_INT1_CNT)
3227 #define G_DEBUG_PD_WRREQ_INT1_CNT(x) (((x) >> S_DEBUG_PD_WRREQ_INT1_CNT) & M_DEBUG_PD_WRREQ_INT1_CNT)
3228 
3229 #define S_DEBUG_PD_WRREQ_INT0_CNT    0
3230 #define M_DEBUG_PD_WRREQ_INT0_CNT    0xfU
3231 #define V_DEBUG_PD_WRREQ_INT0_CNT(x) ((x) << S_DEBUG_PD_WRREQ_INT0_CNT)
3232 #define G_DEBUG_PD_WRREQ_INT0_CNT(x) (((x) >> S_DEBUG_PD_WRREQ_INT0_CNT) & M_DEBUG_PD_WRREQ_INT0_CNT)
3233 
3234 #define S_DEBUG_PL_BAR2_REQVLD    31
3235 #define V_DEBUG_PL_BAR2_REQVLD(x) ((x) << S_DEBUG_PL_BAR2_REQVLD)
3236 #define F_DEBUG_PL_BAR2_REQVLD    V_DEBUG_PL_BAR2_REQVLD(1U)
3237 
3238 #define S_DEBUG_PL_BAR2_REQFULL    30
3239 #define V_DEBUG_PL_BAR2_REQFULL(x) ((x) << S_DEBUG_PL_BAR2_REQFULL)
3240 #define F_DEBUG_PL_BAR2_REQFULL    V_DEBUG_PL_BAR2_REQFULL(1U)
3241 
3242 #define A_SGE_DEBUG_DATA_HIGH_INDEX_9 0x12a4
3243 
3244 #define S_DEBUG_CPLSW_TP_RX_SOP1_CNT    28
3245 #define M_DEBUG_CPLSW_TP_RX_SOP1_CNT    0xfU
3246 #define V_DEBUG_CPLSW_TP_RX_SOP1_CNT(x) ((x) << S_DEBUG_CPLSW_TP_RX_SOP1_CNT)
3247 #define G_DEBUG_CPLSW_TP_RX_SOP1_CNT(x) (((x) >> S_DEBUG_CPLSW_TP_RX_SOP1_CNT) & M_DEBUG_CPLSW_TP_RX_SOP1_CNT)
3248 
3249 #define S_DEBUG_CPLSW_TP_RX_EOP1_CNT    24
3250 #define M_DEBUG_CPLSW_TP_RX_EOP1_CNT    0xfU
3251 #define V_DEBUG_CPLSW_TP_RX_EOP1_CNT(x) ((x) << S_DEBUG_CPLSW_TP_RX_EOP1_CNT)
3252 #define G_DEBUG_CPLSW_TP_RX_EOP1_CNT(x) (((x) >> S_DEBUG_CPLSW_TP_RX_EOP1_CNT) & M_DEBUG_CPLSW_TP_RX_EOP1_CNT)
3253 
3254 #define S_DEBUG_CPLSW_TP_RX_SOP0_CNT    20
3255 #define M_DEBUG_CPLSW_TP_RX_SOP0_CNT    0xfU
3256 #define V_DEBUG_CPLSW_TP_RX_SOP0_CNT(x) ((x) << S_DEBUG_CPLSW_TP_RX_SOP0_CNT)
3257 #define G_DEBUG_CPLSW_TP_RX_SOP0_CNT(x) (((x) >> S_DEBUG_CPLSW_TP_RX_SOP0_CNT) & M_DEBUG_CPLSW_TP_RX_SOP0_CNT)
3258 
3259 #define S_DEBUG_CPLSW_TP_RX_EOP0_CNT    16
3260 #define M_DEBUG_CPLSW_TP_RX_EOP0_CNT    0xfU
3261 #define V_DEBUG_CPLSW_TP_RX_EOP0_CNT(x) ((x) << S_DEBUG_CPLSW_TP_RX_EOP0_CNT)
3262 #define G_DEBUG_CPLSW_TP_RX_EOP0_CNT(x) (((x) >> S_DEBUG_CPLSW_TP_RX_EOP0_CNT) & M_DEBUG_CPLSW_TP_RX_EOP0_CNT)
3263 
3264 #define S_DEBUG_CPLSW_CIM_SOP1_CNT    12
3265 #define M_DEBUG_CPLSW_CIM_SOP1_CNT    0xfU
3266 #define V_DEBUG_CPLSW_CIM_SOP1_CNT(x) ((x) << S_DEBUG_CPLSW_CIM_SOP1_CNT)
3267 #define G_DEBUG_CPLSW_CIM_SOP1_CNT(x) (((x) >> S_DEBUG_CPLSW_CIM_SOP1_CNT) & M_DEBUG_CPLSW_CIM_SOP1_CNT)
3268 
3269 #define S_DEBUG_CPLSW_CIM_EOP1_CNT    8
3270 #define M_DEBUG_CPLSW_CIM_EOP1_CNT    0xfU
3271 #define V_DEBUG_CPLSW_CIM_EOP1_CNT(x) ((x) << S_DEBUG_CPLSW_CIM_EOP1_CNT)
3272 #define G_DEBUG_CPLSW_CIM_EOP1_CNT(x) (((x) >> S_DEBUG_CPLSW_CIM_EOP1_CNT) & M_DEBUG_CPLSW_CIM_EOP1_CNT)
3273 
3274 #define S_DEBUG_CPLSW_CIM_SOP0_CNT    4
3275 #define M_DEBUG_CPLSW_CIM_SOP0_CNT    0xfU
3276 #define V_DEBUG_CPLSW_CIM_SOP0_CNT(x) ((x) << S_DEBUG_CPLSW_CIM_SOP0_CNT)
3277 #define G_DEBUG_CPLSW_CIM_SOP0_CNT(x) (((x) >> S_DEBUG_CPLSW_CIM_SOP0_CNT) & M_DEBUG_CPLSW_CIM_SOP0_CNT)
3278 
3279 #define S_DEBUG_CPLSW_CIM_EOP0_CNT    0
3280 #define M_DEBUG_CPLSW_CIM_EOP0_CNT    0xfU
3281 #define V_DEBUG_CPLSW_CIM_EOP0_CNT(x) ((x) << S_DEBUG_CPLSW_CIM_EOP0_CNT)
3282 #define G_DEBUG_CPLSW_CIM_EOP0_CNT(x) (((x) >> S_DEBUG_CPLSW_CIM_EOP0_CNT) & M_DEBUG_CPLSW_CIM_EOP0_CNT)
3283 
3284 #define A_SGE_DEBUG_DATA_HIGH_INDEX_10 0x12a8
3285 
3286 #define S_DEBUG_T_RXAFULL_D    30
3287 #define M_DEBUG_T_RXAFULL_D    0x3U
3288 #define V_DEBUG_T_RXAFULL_D(x) ((x) << S_DEBUG_T_RXAFULL_D)
3289 #define G_DEBUG_T_RXAFULL_D(x) (((x) >> S_DEBUG_T_RXAFULL_D) & M_DEBUG_T_RXAFULL_D)
3290 
3291 #define S_DEBUG_PD_RDRSPAFULL_D    26
3292 #define M_DEBUG_PD_RDRSPAFULL_D    0xfU
3293 #define V_DEBUG_PD_RDRSPAFULL_D(x) ((x) << S_DEBUG_PD_RDRSPAFULL_D)
3294 #define G_DEBUG_PD_RDRSPAFULL_D(x) (((x) >> S_DEBUG_PD_RDRSPAFULL_D) & M_DEBUG_PD_RDRSPAFULL_D)
3295 
3296 #define S_DEBUG_PD_RDREQAFULL_D    22
3297 #define M_DEBUG_PD_RDREQAFULL_D    0xfU
3298 #define V_DEBUG_PD_RDREQAFULL_D(x) ((x) << S_DEBUG_PD_RDREQAFULL_D)
3299 #define G_DEBUG_PD_RDREQAFULL_D(x) (((x) >> S_DEBUG_PD_RDREQAFULL_D) & M_DEBUG_PD_RDREQAFULL_D)
3300 
3301 #define S_DEBUG_PD_WRREQAFULL_D    18
3302 #define M_DEBUG_PD_WRREQAFULL_D    0xfU
3303 #define V_DEBUG_PD_WRREQAFULL_D(x) ((x) << S_DEBUG_PD_WRREQAFULL_D)
3304 #define G_DEBUG_PD_WRREQAFULL_D(x) (((x) >> S_DEBUG_PD_WRREQAFULL_D) & M_DEBUG_PD_WRREQAFULL_D)
3305 
3306 #define S_DEBUG_PC_RSPAFULL_D    15
3307 #define M_DEBUG_PC_RSPAFULL_D    0x7U
3308 #define V_DEBUG_PC_RSPAFULL_D(x) ((x) << S_DEBUG_PC_RSPAFULL_D)
3309 #define G_DEBUG_PC_RSPAFULL_D(x) (((x) >> S_DEBUG_PC_RSPAFULL_D) & M_DEBUG_PC_RSPAFULL_D)
3310 
3311 #define S_DEBUG_PC_REQAFULL_D    12
3312 #define M_DEBUG_PC_REQAFULL_D    0x7U
3313 #define V_DEBUG_PC_REQAFULL_D(x) ((x) << S_DEBUG_PC_REQAFULL_D)
3314 #define G_DEBUG_PC_REQAFULL_D(x) (((x) >> S_DEBUG_PC_REQAFULL_D) & M_DEBUG_PC_REQAFULL_D)
3315 
3316 #define S_DEBUG_U_TXAFULL_D    8
3317 #define M_DEBUG_U_TXAFULL_D    0xfU
3318 #define V_DEBUG_U_TXAFULL_D(x) ((x) << S_DEBUG_U_TXAFULL_D)
3319 #define G_DEBUG_U_TXAFULL_D(x) (((x) >> S_DEBUG_U_TXAFULL_D) & M_DEBUG_U_TXAFULL_D)
3320 
3321 #define S_DEBUG_UD_RXAFULL_D    4
3322 #define M_DEBUG_UD_RXAFULL_D    0xfU
3323 #define V_DEBUG_UD_RXAFULL_D(x) ((x) << S_DEBUG_UD_RXAFULL_D)
3324 #define G_DEBUG_UD_RXAFULL_D(x) (((x) >> S_DEBUG_UD_RXAFULL_D) & M_DEBUG_UD_RXAFULL_D)
3325 
3326 #define S_DEBUG_U_RXAFULL_D    2
3327 #define M_DEBUG_U_RXAFULL_D    0x3U
3328 #define V_DEBUG_U_RXAFULL_D(x) ((x) << S_DEBUG_U_RXAFULL_D)
3329 #define G_DEBUG_U_RXAFULL_D(x) (((x) >> S_DEBUG_U_RXAFULL_D) & M_DEBUG_U_RXAFULL_D)
3330 
3331 #define S_DEBUG_CIM_AFULL_D    0
3332 #define M_DEBUG_CIM_AFULL_D    0x3U
3333 #define V_DEBUG_CIM_AFULL_D(x) ((x) << S_DEBUG_CIM_AFULL_D)
3334 #define G_DEBUG_CIM_AFULL_D(x) (((x) >> S_DEBUG_CIM_AFULL_D) & M_DEBUG_CIM_AFULL_D)
3335 
3336 #define S_DEBUG_IDMA1_S_CPL_FLIT_REMAINING    28
3337 #define M_DEBUG_IDMA1_S_CPL_FLIT_REMAINING    0xfU
3338 #define V_DEBUG_IDMA1_S_CPL_FLIT_REMAINING(x) ((x) << S_DEBUG_IDMA1_S_CPL_FLIT_REMAINING)
3339 #define G_DEBUG_IDMA1_S_CPL_FLIT_REMAINING(x) (((x) >> S_DEBUG_IDMA1_S_CPL_FLIT_REMAINING) & M_DEBUG_IDMA1_S_CPL_FLIT_REMAINING)
3340 
3341 #define S_DEBUG_IDMA1_IDMA2IMSG_CMP_OUT_SRDY    27
3342 #define V_DEBUG_IDMA1_IDMA2IMSG_CMP_OUT_SRDY(x) ((x) << S_DEBUG_IDMA1_IDMA2IMSG_CMP_OUT_SRDY)
3343 #define F_DEBUG_IDMA1_IDMA2IMSG_CMP_OUT_SRDY    V_DEBUG_IDMA1_IDMA2IMSG_CMP_OUT_SRDY(1U)
3344 
3345 #define S_DEBUG_IDMA1_IDMA2IMSG_CMP_OUT_RSS    26
3346 #define V_DEBUG_IDMA1_IDMA2IMSG_CMP_OUT_RSS(x) ((x) << S_DEBUG_IDMA1_IDMA2IMSG_CMP_OUT_RSS)
3347 #define F_DEBUG_IDMA1_IDMA2IMSG_CMP_OUT_RSS    V_DEBUG_IDMA1_IDMA2IMSG_CMP_OUT_RSS(1U)
3348 
3349 #define S_DEBUG_IDMA1_IDMA2IMSG_CMP_OUT_NOCPL    25
3350 #define V_DEBUG_IDMA1_IDMA2IMSG_CMP_OUT_NOCPL(x) ((x) << S_DEBUG_IDMA1_IDMA2IMSG_CMP_OUT_NOCPL)
3351 #define F_DEBUG_IDMA1_IDMA2IMSG_CMP_OUT_NOCPL    V_DEBUG_IDMA1_IDMA2IMSG_CMP_OUT_NOCPL(1U)
3352 
3353 #define S_DEBUG_IDMA1_IDMA2IMSG_FULL    24
3354 #define V_DEBUG_IDMA1_IDMA2IMSG_FULL(x) ((x) << S_DEBUG_IDMA1_IDMA2IMSG_FULL)
3355 #define F_DEBUG_IDMA1_IDMA2IMSG_FULL    V_DEBUG_IDMA1_IDMA2IMSG_FULL(1U)
3356 
3357 #define S_DEBUG_IDMA1_IDMA2IMSG_EOP    23
3358 #define V_DEBUG_IDMA1_IDMA2IMSG_EOP(x) ((x) << S_DEBUG_IDMA1_IDMA2IMSG_EOP)
3359 #define F_DEBUG_IDMA1_IDMA2IMSG_EOP    V_DEBUG_IDMA1_IDMA2IMSG_EOP(1U)
3360 
3361 #define S_DEBUG_IDMA1_IDMA2IMSG_FIFO_IN_DRDY    22
3362 #define V_DEBUG_IDMA1_IDMA2IMSG_FIFO_IN_DRDY(x) ((x) << S_DEBUG_IDMA1_IDMA2IMSG_FIFO_IN_DRDY)
3363 #define F_DEBUG_IDMA1_IDMA2IMSG_FIFO_IN_DRDY    V_DEBUG_IDMA1_IDMA2IMSG_FIFO_IN_DRDY(1U)
3364 
3365 #define S_DEBUG_IDMA1_IDMA2IMSG_CMP_IN_DRDY    21
3366 #define V_DEBUG_IDMA1_IDMA2IMSG_CMP_IN_DRDY(x) ((x) << S_DEBUG_IDMA1_IDMA2IMSG_CMP_IN_DRDY)
3367 #define F_DEBUG_IDMA1_IDMA2IMSG_CMP_IN_DRDY    V_DEBUG_IDMA1_IDMA2IMSG_CMP_IN_DRDY(1U)
3368 
3369 #define S_DEBUG_IDMA0_S_CPL_FLIT_REMAINING    17
3370 #define M_DEBUG_IDMA0_S_CPL_FLIT_REMAINING    0xfU
3371 #define V_DEBUG_IDMA0_S_CPL_FLIT_REMAINING(x) ((x) << S_DEBUG_IDMA0_S_CPL_FLIT_REMAINING)
3372 #define G_DEBUG_IDMA0_S_CPL_FLIT_REMAINING(x) (((x) >> S_DEBUG_IDMA0_S_CPL_FLIT_REMAINING) & M_DEBUG_IDMA0_S_CPL_FLIT_REMAINING)
3373 
3374 #define S_DEBUG_IDMA0_IDMA2IMSG_CMP_OUT_SRDY    16
3375 #define V_DEBUG_IDMA0_IDMA2IMSG_CMP_OUT_SRDY(x) ((x) << S_DEBUG_IDMA0_IDMA2IMSG_CMP_OUT_SRDY)
3376 #define F_DEBUG_IDMA0_IDMA2IMSG_CMP_OUT_SRDY    V_DEBUG_IDMA0_IDMA2IMSG_CMP_OUT_SRDY(1U)
3377 
3378 #define S_DEBUG_IDMA0_IDMA2IMSG_CMP_OUT_RSS    15
3379 #define V_DEBUG_IDMA0_IDMA2IMSG_CMP_OUT_RSS(x) ((x) << S_DEBUG_IDMA0_IDMA2IMSG_CMP_OUT_RSS)
3380 #define F_DEBUG_IDMA0_IDMA2IMSG_CMP_OUT_RSS    V_DEBUG_IDMA0_IDMA2IMSG_CMP_OUT_RSS(1U)
3381 
3382 #define S_DEBUG_IDMA0_IDMA2IMSG_CMP_OUT_NOCPL    14
3383 #define V_DEBUG_IDMA0_IDMA2IMSG_CMP_OUT_NOCPL(x) ((x) << S_DEBUG_IDMA0_IDMA2IMSG_CMP_OUT_NOCPL)
3384 #define F_DEBUG_IDMA0_IDMA2IMSG_CMP_OUT_NOCPL    V_DEBUG_IDMA0_IDMA2IMSG_CMP_OUT_NOCPL(1U)
3385 
3386 #define S_DEBUG_IDMA0_IDMA2IMSG_FULL    13
3387 #define V_DEBUG_IDMA0_IDMA2IMSG_FULL(x) ((x) << S_DEBUG_IDMA0_IDMA2IMSG_FULL)
3388 #define F_DEBUG_IDMA0_IDMA2IMSG_FULL    V_DEBUG_IDMA0_IDMA2IMSG_FULL(1U)
3389 
3390 #define S_DEBUG_IDMA0_IDMA2IMSG_EOP    12
3391 #define V_DEBUG_IDMA0_IDMA2IMSG_EOP(x) ((x) << S_DEBUG_IDMA0_IDMA2IMSG_EOP)
3392 #define F_DEBUG_IDMA0_IDMA2IMSG_EOP    V_DEBUG_IDMA0_IDMA2IMSG_EOP(1U)
3393 
3394 #define S_DEBUG_IDMA0_IDMA2IMSG_CMP_IN_DRDY    11
3395 #define V_DEBUG_IDMA0_IDMA2IMSG_CMP_IN_DRDY(x) ((x) << S_DEBUG_IDMA0_IDMA2IMSG_CMP_IN_DRDY)
3396 #define F_DEBUG_IDMA0_IDMA2IMSG_CMP_IN_DRDY    V_DEBUG_IDMA0_IDMA2IMSG_CMP_IN_DRDY(1U)
3397 
3398 #define S_DEBUG_IDMA0_IDMA2IMSG_FIFO_IN_DRDY    10
3399 #define V_DEBUG_IDMA0_IDMA2IMSG_FIFO_IN_DRDY(x) ((x) << S_DEBUG_IDMA0_IDMA2IMSG_FIFO_IN_DRDY)
3400 #define F_DEBUG_IDMA0_IDMA2IMSG_FIFO_IN_DRDY    V_DEBUG_IDMA0_IDMA2IMSG_FIFO_IN_DRDY(1U)
3401 
3402 #define S_T6_DEBUG_T_RXAFULL_D    8
3403 #define M_T6_DEBUG_T_RXAFULL_D    0x3U
3404 #define V_T6_DEBUG_T_RXAFULL_D(x) ((x) << S_T6_DEBUG_T_RXAFULL_D)
3405 #define G_T6_DEBUG_T_RXAFULL_D(x) (((x) >> S_T6_DEBUG_T_RXAFULL_D) & M_T6_DEBUG_T_RXAFULL_D)
3406 
3407 #define S_T6_DEBUG_PD_WRREQAFULL_D    6
3408 #define M_T6_DEBUG_PD_WRREQAFULL_D    0x3U
3409 #define V_T6_DEBUG_PD_WRREQAFULL_D(x) ((x) << S_T6_DEBUG_PD_WRREQAFULL_D)
3410 #define G_T6_DEBUG_PD_WRREQAFULL_D(x) (((x) >> S_T6_DEBUG_PD_WRREQAFULL_D) & M_T6_DEBUG_PD_WRREQAFULL_D)
3411 
3412 #define S_T6_DEBUG_PC_RSPAFULL_D    5
3413 #define V_T6_DEBUG_PC_RSPAFULL_D(x) ((x) << S_T6_DEBUG_PC_RSPAFULL_D)
3414 #define F_T6_DEBUG_PC_RSPAFULL_D    V_T6_DEBUG_PC_RSPAFULL_D(1U)
3415 
3416 #define S_T6_DEBUG_PC_REQAFULL_D    4
3417 #define V_T6_DEBUG_PC_REQAFULL_D(x) ((x) << S_T6_DEBUG_PC_REQAFULL_D)
3418 #define F_T6_DEBUG_PC_REQAFULL_D    V_T6_DEBUG_PC_REQAFULL_D(1U)
3419 
3420 #define S_T6_DEBUG_CIM_AFULL_D    0
3421 #define V_T6_DEBUG_CIM_AFULL_D(x) ((x) << S_T6_DEBUG_CIM_AFULL_D)
3422 #define F_T6_DEBUG_CIM_AFULL_D    V_T6_DEBUG_CIM_AFULL_D(1U)
3423 
3424 #define A_SGE_DEBUG_DATA_HIGH_INDEX_11 0x12ac
3425 
3426 #define S_DEBUG_FLM_IDMA1_CACHE_DATA_ACTIVE    24
3427 #define V_DEBUG_FLM_IDMA1_CACHE_DATA_ACTIVE(x) ((x) << S_DEBUG_FLM_IDMA1_CACHE_DATA_ACTIVE)
3428 #define F_DEBUG_FLM_IDMA1_CACHE_DATA_ACTIVE    V_DEBUG_FLM_IDMA1_CACHE_DATA_ACTIVE(1U)
3429 
3430 #define S_DEBUG_FLM_IDMA1_CACHE_HDR_ACTIVE    23
3431 #define V_DEBUG_FLM_IDMA1_CACHE_HDR_ACTIVE(x) ((x) << S_DEBUG_FLM_IDMA1_CACHE_HDR_ACTIVE)
3432 #define F_DEBUG_FLM_IDMA1_CACHE_HDR_ACTIVE    V_DEBUG_FLM_IDMA1_CACHE_HDR_ACTIVE(1U)
3433 
3434 #define S_DEBUG_FLM_IDMA1_CTXT_DATA_ACTIVE    22
3435 #define V_DEBUG_FLM_IDMA1_CTXT_DATA_ACTIVE(x) ((x) << S_DEBUG_FLM_IDMA1_CTXT_DATA_ACTIVE)
3436 #define F_DEBUG_FLM_IDMA1_CTXT_DATA_ACTIVE    V_DEBUG_FLM_IDMA1_CTXT_DATA_ACTIVE(1U)
3437 
3438 #define S_DEBUG_FLM_IDMA1_CTXT_HDR_ACTIVE    21
3439 #define V_DEBUG_FLM_IDMA1_CTXT_HDR_ACTIVE(x) ((x) << S_DEBUG_FLM_IDMA1_CTXT_HDR_ACTIVE)
3440 #define F_DEBUG_FLM_IDMA1_CTXT_HDR_ACTIVE    V_DEBUG_FLM_IDMA1_CTXT_HDR_ACTIVE(1U)
3441 
3442 #define S_DEBUG_ST_FLM_IDMA1_CACHE    19
3443 #define M_DEBUG_ST_FLM_IDMA1_CACHE    0x3U
3444 #define V_DEBUG_ST_FLM_IDMA1_CACHE(x) ((x) << S_DEBUG_ST_FLM_IDMA1_CACHE)
3445 #define G_DEBUG_ST_FLM_IDMA1_CACHE(x) (((x) >> S_DEBUG_ST_FLM_IDMA1_CACHE) & M_DEBUG_ST_FLM_IDMA1_CACHE)
3446 
3447 #define S_DEBUG_ST_FLM_IDMA1_CTXT    16
3448 #define M_DEBUG_ST_FLM_IDMA1_CTXT    0x7U
3449 #define V_DEBUG_ST_FLM_IDMA1_CTXT(x) ((x) << S_DEBUG_ST_FLM_IDMA1_CTXT)
3450 #define G_DEBUG_ST_FLM_IDMA1_CTXT(x) (((x) >> S_DEBUG_ST_FLM_IDMA1_CTXT) & M_DEBUG_ST_FLM_IDMA1_CTXT)
3451 
3452 #define S_DEBUG_FLM_IDMA0_CACHE_DATA_ACTIVE    8
3453 #define V_DEBUG_FLM_IDMA0_CACHE_DATA_ACTIVE(x) ((x) << S_DEBUG_FLM_IDMA0_CACHE_DATA_ACTIVE)
3454 #define F_DEBUG_FLM_IDMA0_CACHE_DATA_ACTIVE    V_DEBUG_FLM_IDMA0_CACHE_DATA_ACTIVE(1U)
3455 
3456 #define S_DEBUG_FLM_IDMA0_CACHE_HDR_ACTIVE    7
3457 #define V_DEBUG_FLM_IDMA0_CACHE_HDR_ACTIVE(x) ((x) << S_DEBUG_FLM_IDMA0_CACHE_HDR_ACTIVE)
3458 #define F_DEBUG_FLM_IDMA0_CACHE_HDR_ACTIVE    V_DEBUG_FLM_IDMA0_CACHE_HDR_ACTIVE(1U)
3459 
3460 #define S_DEBUG_FLM_IDMA0_CTXT_DATA_ACTIVE    6
3461 #define V_DEBUG_FLM_IDMA0_CTXT_DATA_ACTIVE(x) ((x) << S_DEBUG_FLM_IDMA0_CTXT_DATA_ACTIVE)
3462 #define F_DEBUG_FLM_IDMA0_CTXT_DATA_ACTIVE    V_DEBUG_FLM_IDMA0_CTXT_DATA_ACTIVE(1U)
3463 
3464 #define S_DEBUG_FLM_IDMA0_CTXT_HDR_ACTIVE    5
3465 #define V_DEBUG_FLM_IDMA0_CTXT_HDR_ACTIVE(x) ((x) << S_DEBUG_FLM_IDMA0_CTXT_HDR_ACTIVE)
3466 #define F_DEBUG_FLM_IDMA0_CTXT_HDR_ACTIVE    V_DEBUG_FLM_IDMA0_CTXT_HDR_ACTIVE(1U)
3467 
3468 #define S_DEBUG_ST_FLM_IDMA0_CACHE    3
3469 #define M_DEBUG_ST_FLM_IDMA0_CACHE    0x3U
3470 #define V_DEBUG_ST_FLM_IDMA0_CACHE(x) ((x) << S_DEBUG_ST_FLM_IDMA0_CACHE)
3471 #define G_DEBUG_ST_FLM_IDMA0_CACHE(x) (((x) >> S_DEBUG_ST_FLM_IDMA0_CACHE) & M_DEBUG_ST_FLM_IDMA0_CACHE)
3472 
3473 #define S_DEBUG_ST_FLM_IDMA0_CTXT    0
3474 #define M_DEBUG_ST_FLM_IDMA0_CTXT    0x7U
3475 #define V_DEBUG_ST_FLM_IDMA0_CTXT(x) ((x) << S_DEBUG_ST_FLM_IDMA0_CTXT)
3476 #define G_DEBUG_ST_FLM_IDMA0_CTXT(x) (((x) >> S_DEBUG_ST_FLM_IDMA0_CTXT) & M_DEBUG_ST_FLM_IDMA0_CTXT)
3477 
3478 #define A_SGE_DEBUG_DATA_HIGH_INDEX_12 0x12b0
3479 
3480 #define S_DEBUG_CPLSW_SOP1_CNT    28
3481 #define M_DEBUG_CPLSW_SOP1_CNT    0xfU
3482 #define V_DEBUG_CPLSW_SOP1_CNT(x) ((x) << S_DEBUG_CPLSW_SOP1_CNT)
3483 #define G_DEBUG_CPLSW_SOP1_CNT(x) (((x) >> S_DEBUG_CPLSW_SOP1_CNT) & M_DEBUG_CPLSW_SOP1_CNT)
3484 
3485 #define S_DEBUG_CPLSW_EOP1_CNT    24
3486 #define M_DEBUG_CPLSW_EOP1_CNT    0xfU
3487 #define V_DEBUG_CPLSW_EOP1_CNT(x) ((x) << S_DEBUG_CPLSW_EOP1_CNT)
3488 #define G_DEBUG_CPLSW_EOP1_CNT(x) (((x) >> S_DEBUG_CPLSW_EOP1_CNT) & M_DEBUG_CPLSW_EOP1_CNT)
3489 
3490 #define S_DEBUG_CPLSW_SOP0_CNT    20
3491 #define M_DEBUG_CPLSW_SOP0_CNT    0xfU
3492 #define V_DEBUG_CPLSW_SOP0_CNT(x) ((x) << S_DEBUG_CPLSW_SOP0_CNT)
3493 #define G_DEBUG_CPLSW_SOP0_CNT(x) (((x) >> S_DEBUG_CPLSW_SOP0_CNT) & M_DEBUG_CPLSW_SOP0_CNT)
3494 
3495 #define S_DEBUG_CPLSW_EOP0_CNT    16
3496 #define M_DEBUG_CPLSW_EOP0_CNT    0xfU
3497 #define V_DEBUG_CPLSW_EOP0_CNT(x) ((x) << S_DEBUG_CPLSW_EOP0_CNT)
3498 #define G_DEBUG_CPLSW_EOP0_CNT(x) (((x) >> S_DEBUG_CPLSW_EOP0_CNT) & M_DEBUG_CPLSW_EOP0_CNT)
3499 
3500 #define S_DEBUG_PC_RSP_SOP2_CNT    12
3501 #define M_DEBUG_PC_RSP_SOP2_CNT    0xfU
3502 #define V_DEBUG_PC_RSP_SOP2_CNT(x) ((x) << S_DEBUG_PC_RSP_SOP2_CNT)
3503 #define G_DEBUG_PC_RSP_SOP2_CNT(x) (((x) >> S_DEBUG_PC_RSP_SOP2_CNT) & M_DEBUG_PC_RSP_SOP2_CNT)
3504 
3505 #define S_DEBUG_PC_RSP_EOP2_CNT    8
3506 #define M_DEBUG_PC_RSP_EOP2_CNT    0xfU
3507 #define V_DEBUG_PC_RSP_EOP2_CNT(x) ((x) << S_DEBUG_PC_RSP_EOP2_CNT)
3508 #define G_DEBUG_PC_RSP_EOP2_CNT(x) (((x) >> S_DEBUG_PC_RSP_EOP2_CNT) & M_DEBUG_PC_RSP_EOP2_CNT)
3509 
3510 #define S_DEBUG_PC_REQ_SOP2_CNT    4
3511 #define M_DEBUG_PC_REQ_SOP2_CNT    0xfU
3512 #define V_DEBUG_PC_REQ_SOP2_CNT(x) ((x) << S_DEBUG_PC_REQ_SOP2_CNT)
3513 #define G_DEBUG_PC_REQ_SOP2_CNT(x) (((x) >> S_DEBUG_PC_REQ_SOP2_CNT) & M_DEBUG_PC_REQ_SOP2_CNT)
3514 
3515 #define S_DEBUG_PC_REQ_EOP2_CNT    0
3516 #define M_DEBUG_PC_REQ_EOP2_CNT    0xfU
3517 #define V_DEBUG_PC_REQ_EOP2_CNT(x) ((x) << S_DEBUG_PC_REQ_EOP2_CNT)
3518 #define G_DEBUG_PC_REQ_EOP2_CNT(x) (((x) >> S_DEBUG_PC_REQ_EOP2_CNT) & M_DEBUG_PC_REQ_EOP2_CNT)
3519 
3520 #define S_DEBUG_IDMA1_ISHIFT_TX_SIZE    8
3521 #define M_DEBUG_IDMA1_ISHIFT_TX_SIZE    0x7fU
3522 #define V_DEBUG_IDMA1_ISHIFT_TX_SIZE(x) ((x) << S_DEBUG_IDMA1_ISHIFT_TX_SIZE)
3523 #define G_DEBUG_IDMA1_ISHIFT_TX_SIZE(x) (((x) >> S_DEBUG_IDMA1_ISHIFT_TX_SIZE) & M_DEBUG_IDMA1_ISHIFT_TX_SIZE)
3524 
3525 #define S_DEBUG_IDMA0_ISHIFT_TX_SIZE    0
3526 #define M_DEBUG_IDMA0_ISHIFT_TX_SIZE    0x7fU
3527 #define V_DEBUG_IDMA0_ISHIFT_TX_SIZE(x) ((x) << S_DEBUG_IDMA0_ISHIFT_TX_SIZE)
3528 #define G_DEBUG_IDMA0_ISHIFT_TX_SIZE(x) (((x) >> S_DEBUG_IDMA0_ISHIFT_TX_SIZE) & M_DEBUG_IDMA0_ISHIFT_TX_SIZE)
3529 
3530 #define A_SGE_DEBUG_DATA_HIGH_INDEX_13 0x12b4
3531 #define A_SGE_DEBUG_DATA_HIGH_INDEX_14 0x12b8
3532 #define A_SGE_DEBUG_DATA_HIGH_INDEX_15 0x12bc
3533 #define A_SGE_DEBUG_DATA_LOW_INDEX_0 0x12c0
3534 
3535 #define S_DEBUG_ST_IDMA1_FLM_REQ    29
3536 #define M_DEBUG_ST_IDMA1_FLM_REQ    0x7U
3537 #define V_DEBUG_ST_IDMA1_FLM_REQ(x) ((x) << S_DEBUG_ST_IDMA1_FLM_REQ)
3538 #define G_DEBUG_ST_IDMA1_FLM_REQ(x) (((x) >> S_DEBUG_ST_IDMA1_FLM_REQ) & M_DEBUG_ST_IDMA1_FLM_REQ)
3539 
3540 #define S_DEBUG_ST_IDMA0_FLM_REQ    26
3541 #define M_DEBUG_ST_IDMA0_FLM_REQ    0x7U
3542 #define V_DEBUG_ST_IDMA0_FLM_REQ(x) ((x) << S_DEBUG_ST_IDMA0_FLM_REQ)
3543 #define G_DEBUG_ST_IDMA0_FLM_REQ(x) (((x) >> S_DEBUG_ST_IDMA0_FLM_REQ) & M_DEBUG_ST_IDMA0_FLM_REQ)
3544 
3545 #define S_DEBUG_ST_IMSG_CTXT    23
3546 #define M_DEBUG_ST_IMSG_CTXT    0x7U
3547 #define V_DEBUG_ST_IMSG_CTXT(x) ((x) << S_DEBUG_ST_IMSG_CTXT)
3548 #define G_DEBUG_ST_IMSG_CTXT(x) (((x) >> S_DEBUG_ST_IMSG_CTXT) & M_DEBUG_ST_IMSG_CTXT)
3549 
3550 #define S_DEBUG_ST_IMSG    18
3551 #define M_DEBUG_ST_IMSG    0x1fU
3552 #define V_DEBUG_ST_IMSG(x) ((x) << S_DEBUG_ST_IMSG)
3553 #define G_DEBUG_ST_IMSG(x) (((x) >> S_DEBUG_ST_IMSG) & M_DEBUG_ST_IMSG)
3554 
3555 #define S_DEBUG_ST_IDMA1_IALN    16
3556 #define M_DEBUG_ST_IDMA1_IALN    0x3U
3557 #define V_DEBUG_ST_IDMA1_IALN(x) ((x) << S_DEBUG_ST_IDMA1_IALN)
3558 #define G_DEBUG_ST_IDMA1_IALN(x) (((x) >> S_DEBUG_ST_IDMA1_IALN) & M_DEBUG_ST_IDMA1_IALN)
3559 
3560 #define S_DEBUG_ST_IDMA1_IDMA_SM    9
3561 #define M_DEBUG_ST_IDMA1_IDMA_SM    0x3fU
3562 #define V_DEBUG_ST_IDMA1_IDMA_SM(x) ((x) << S_DEBUG_ST_IDMA1_IDMA_SM)
3563 #define G_DEBUG_ST_IDMA1_IDMA_SM(x) (((x) >> S_DEBUG_ST_IDMA1_IDMA_SM) & M_DEBUG_ST_IDMA1_IDMA_SM)
3564 
3565 #define S_DEBUG_ST_IDMA0_IALN    7
3566 #define M_DEBUG_ST_IDMA0_IALN    0x3U
3567 #define V_DEBUG_ST_IDMA0_IALN(x) ((x) << S_DEBUG_ST_IDMA0_IALN)
3568 #define G_DEBUG_ST_IDMA0_IALN(x) (((x) >> S_DEBUG_ST_IDMA0_IALN) & M_DEBUG_ST_IDMA0_IALN)
3569 
3570 #define S_DEBUG_ST_IDMA0_IDMA_SM    0
3571 #define M_DEBUG_ST_IDMA0_IDMA_SM    0x3fU
3572 #define V_DEBUG_ST_IDMA0_IDMA_SM(x) ((x) << S_DEBUG_ST_IDMA0_IDMA_SM)
3573 #define G_DEBUG_ST_IDMA0_IDMA_SM(x) (((x) >> S_DEBUG_ST_IDMA0_IDMA_SM) & M_DEBUG_ST_IDMA0_IDMA_SM)
3574 
3575 #define S_DEBUG_ST_IDMA1_IDMA2IMSG    15
3576 #define V_DEBUG_ST_IDMA1_IDMA2IMSG(x) ((x) << S_DEBUG_ST_IDMA1_IDMA2IMSG)
3577 #define F_DEBUG_ST_IDMA1_IDMA2IMSG    V_DEBUG_ST_IDMA1_IDMA2IMSG(1U)
3578 
3579 #define S_DEBUG_ST_IDMA0_IDMA2IMSG    6
3580 #define V_DEBUG_ST_IDMA0_IDMA2IMSG(x) ((x) << S_DEBUG_ST_IDMA0_IDMA2IMSG)
3581 #define F_DEBUG_ST_IDMA0_IDMA2IMSG    V_DEBUG_ST_IDMA0_IDMA2IMSG(1U)
3582 
3583 #define A_SGE_DEBUG_DATA_LOW_INDEX_1 0x12c4
3584 
3585 #define S_DEBUG_ITP_EMPTY    12
3586 #define M_DEBUG_ITP_EMPTY    0x3fU
3587 #define V_DEBUG_ITP_EMPTY(x) ((x) << S_DEBUG_ITP_EMPTY)
3588 #define G_DEBUG_ITP_EMPTY(x) (((x) >> S_DEBUG_ITP_EMPTY) & M_DEBUG_ITP_EMPTY)
3589 
3590 #define S_DEBUG_ITP_EXPIRED    6
3591 #define M_DEBUG_ITP_EXPIRED    0x3fU
3592 #define V_DEBUG_ITP_EXPIRED(x) ((x) << S_DEBUG_ITP_EXPIRED)
3593 #define G_DEBUG_ITP_EXPIRED(x) (((x) >> S_DEBUG_ITP_EXPIRED) & M_DEBUG_ITP_EXPIRED)
3594 
3595 #define S_DEBUG_ITP_PAUSE    5
3596 #define V_DEBUG_ITP_PAUSE(x) ((x) << S_DEBUG_ITP_PAUSE)
3597 #define F_DEBUG_ITP_PAUSE    V_DEBUG_ITP_PAUSE(1U)
3598 
3599 #define S_DEBUG_ITP_DEL_DONE    4
3600 #define V_DEBUG_ITP_DEL_DONE(x) ((x) << S_DEBUG_ITP_DEL_DONE)
3601 #define F_DEBUG_ITP_DEL_DONE    V_DEBUG_ITP_DEL_DONE(1U)
3602 
3603 #define S_DEBUG_ITP_ADD_DONE    3
3604 #define V_DEBUG_ITP_ADD_DONE(x) ((x) << S_DEBUG_ITP_ADD_DONE)
3605 #define F_DEBUG_ITP_ADD_DONE    V_DEBUG_ITP_ADD_DONE(1U)
3606 
3607 #define S_DEBUG_ITP_EVR_STATE    0
3608 #define M_DEBUG_ITP_EVR_STATE    0x7U
3609 #define V_DEBUG_ITP_EVR_STATE(x) ((x) << S_DEBUG_ITP_EVR_STATE)
3610 #define G_DEBUG_ITP_EVR_STATE(x) (((x) >> S_DEBUG_ITP_EVR_STATE) & M_DEBUG_ITP_EVR_STATE)
3611 
3612 #define A_SGE_DEBUG_DATA_LOW_INDEX_2 0x12c8
3613 
3614 #define S_DEBUG_ST_DBP_THREAD2_CIMFL    25
3615 #define M_DEBUG_ST_DBP_THREAD2_CIMFL    0x1fU
3616 #define V_DEBUG_ST_DBP_THREAD2_CIMFL(x) ((x) << S_DEBUG_ST_DBP_THREAD2_CIMFL)
3617 #define G_DEBUG_ST_DBP_THREAD2_CIMFL(x) (((x) >> S_DEBUG_ST_DBP_THREAD2_CIMFL) & M_DEBUG_ST_DBP_THREAD2_CIMFL)
3618 
3619 #define S_DEBUG_ST_DBP_THREAD2_MAIN    20
3620 #define M_DEBUG_ST_DBP_THREAD2_MAIN    0x1fU
3621 #define V_DEBUG_ST_DBP_THREAD2_MAIN(x) ((x) << S_DEBUG_ST_DBP_THREAD2_MAIN)
3622 #define G_DEBUG_ST_DBP_THREAD2_MAIN(x) (((x) >> S_DEBUG_ST_DBP_THREAD2_MAIN) & M_DEBUG_ST_DBP_THREAD2_MAIN)
3623 
3624 #define S_DEBUG_ST_DBP_THREAD1_CIMFL    15
3625 #define M_DEBUG_ST_DBP_THREAD1_CIMFL    0x1fU
3626 #define V_DEBUG_ST_DBP_THREAD1_CIMFL(x) ((x) << S_DEBUG_ST_DBP_THREAD1_CIMFL)
3627 #define G_DEBUG_ST_DBP_THREAD1_CIMFL(x) (((x) >> S_DEBUG_ST_DBP_THREAD1_CIMFL) & M_DEBUG_ST_DBP_THREAD1_CIMFL)
3628 
3629 #define S_DEBUG_ST_DBP_THREAD1_MAIN    10
3630 #define M_DEBUG_ST_DBP_THREAD1_MAIN    0x1fU
3631 #define V_DEBUG_ST_DBP_THREAD1_MAIN(x) ((x) << S_DEBUG_ST_DBP_THREAD1_MAIN)
3632 #define G_DEBUG_ST_DBP_THREAD1_MAIN(x) (((x) >> S_DEBUG_ST_DBP_THREAD1_MAIN) & M_DEBUG_ST_DBP_THREAD1_MAIN)
3633 
3634 #define S_DEBUG_ST_DBP_THREAD0_CIMFL    5
3635 #define M_DEBUG_ST_DBP_THREAD0_CIMFL    0x1fU
3636 #define V_DEBUG_ST_DBP_THREAD0_CIMFL(x) ((x) << S_DEBUG_ST_DBP_THREAD0_CIMFL)
3637 #define G_DEBUG_ST_DBP_THREAD0_CIMFL(x) (((x) >> S_DEBUG_ST_DBP_THREAD0_CIMFL) & M_DEBUG_ST_DBP_THREAD0_CIMFL)
3638 
3639 #define S_DEBUG_ST_DBP_THREAD0_MAIN    0
3640 #define M_DEBUG_ST_DBP_THREAD0_MAIN    0x1fU
3641 #define V_DEBUG_ST_DBP_THREAD0_MAIN(x) ((x) << S_DEBUG_ST_DBP_THREAD0_MAIN)
3642 #define G_DEBUG_ST_DBP_THREAD0_MAIN(x) (((x) >> S_DEBUG_ST_DBP_THREAD0_MAIN) & M_DEBUG_ST_DBP_THREAD0_MAIN)
3643 
3644 #define S_T6_DEBUG_ST_DBP_UPCP_MAIN    14
3645 #define M_T6_DEBUG_ST_DBP_UPCP_MAIN    0x7U
3646 #define V_T6_DEBUG_ST_DBP_UPCP_MAIN(x) ((x) << S_T6_DEBUG_ST_DBP_UPCP_MAIN)
3647 #define G_T6_DEBUG_ST_DBP_UPCP_MAIN(x) (((x) >> S_T6_DEBUG_ST_DBP_UPCP_MAIN) & M_T6_DEBUG_ST_DBP_UPCP_MAIN)
3648 
3649 #define A_SGE_DEBUG_DATA_LOW_INDEX_3 0x12cc
3650 
3651 #define S_DEBUG_ST_DBP_UPCP_MAIN    14
3652 #define M_DEBUG_ST_DBP_UPCP_MAIN    0x1fU
3653 #define V_DEBUG_ST_DBP_UPCP_MAIN(x) ((x) << S_DEBUG_ST_DBP_UPCP_MAIN)
3654 #define G_DEBUG_ST_DBP_UPCP_MAIN(x) (((x) >> S_DEBUG_ST_DBP_UPCP_MAIN) & M_DEBUG_ST_DBP_UPCP_MAIN)
3655 
3656 #define S_DEBUG_ST_DBP_DBFIFO_MAIN    13
3657 #define V_DEBUG_ST_DBP_DBFIFO_MAIN(x) ((x) << S_DEBUG_ST_DBP_DBFIFO_MAIN)
3658 #define F_DEBUG_ST_DBP_DBFIFO_MAIN    V_DEBUG_ST_DBP_DBFIFO_MAIN(1U)
3659 
3660 #define S_DEBUG_ST_DBP_CTXT    10
3661 #define M_DEBUG_ST_DBP_CTXT    0x7U
3662 #define V_DEBUG_ST_DBP_CTXT(x) ((x) << S_DEBUG_ST_DBP_CTXT)
3663 #define G_DEBUG_ST_DBP_CTXT(x) (((x) >> S_DEBUG_ST_DBP_CTXT) & M_DEBUG_ST_DBP_CTXT)
3664 
3665 #define S_DEBUG_ST_DBP_THREAD3_CIMFL    5
3666 #define M_DEBUG_ST_DBP_THREAD3_CIMFL    0x1fU
3667 #define V_DEBUG_ST_DBP_THREAD3_CIMFL(x) ((x) << S_DEBUG_ST_DBP_THREAD3_CIMFL)
3668 #define G_DEBUG_ST_DBP_THREAD3_CIMFL(x) (((x) >> S_DEBUG_ST_DBP_THREAD3_CIMFL) & M_DEBUG_ST_DBP_THREAD3_CIMFL)
3669 
3670 #define S_DEBUG_ST_DBP_THREAD3_MAIN    0
3671 #define M_DEBUG_ST_DBP_THREAD3_MAIN    0x1fU
3672 #define V_DEBUG_ST_DBP_THREAD3_MAIN(x) ((x) << S_DEBUG_ST_DBP_THREAD3_MAIN)
3673 #define G_DEBUG_ST_DBP_THREAD3_MAIN(x) (((x) >> S_DEBUG_ST_DBP_THREAD3_MAIN) & M_DEBUG_ST_DBP_THREAD3_MAIN)
3674 
3675 #define A_SGE_DEBUG_DATA_LOW_INDEX_4 0x12d0
3676 
3677 #define S_DEBUG_ST_EDMA3_ALIGN_SUB    29
3678 #define M_DEBUG_ST_EDMA3_ALIGN_SUB    0x7U
3679 #define V_DEBUG_ST_EDMA3_ALIGN_SUB(x) ((x) << S_DEBUG_ST_EDMA3_ALIGN_SUB)
3680 #define G_DEBUG_ST_EDMA3_ALIGN_SUB(x) (((x) >> S_DEBUG_ST_EDMA3_ALIGN_SUB) & M_DEBUG_ST_EDMA3_ALIGN_SUB)
3681 
3682 #define S_DEBUG_ST_EDMA3_ALIGN    27
3683 #define M_DEBUG_ST_EDMA3_ALIGN    0x3U
3684 #define V_DEBUG_ST_EDMA3_ALIGN(x) ((x) << S_DEBUG_ST_EDMA3_ALIGN)
3685 #define G_DEBUG_ST_EDMA3_ALIGN(x) (((x) >> S_DEBUG_ST_EDMA3_ALIGN) & M_DEBUG_ST_EDMA3_ALIGN)
3686 
3687 #define S_DEBUG_ST_EDMA3_REQ    24
3688 #define M_DEBUG_ST_EDMA3_REQ    0x7U
3689 #define V_DEBUG_ST_EDMA3_REQ(x) ((x) << S_DEBUG_ST_EDMA3_REQ)
3690 #define G_DEBUG_ST_EDMA3_REQ(x) (((x) >> S_DEBUG_ST_EDMA3_REQ) & M_DEBUG_ST_EDMA3_REQ)
3691 
3692 #define S_DEBUG_ST_EDMA2_ALIGN_SUB    21
3693 #define M_DEBUG_ST_EDMA2_ALIGN_SUB    0x7U
3694 #define V_DEBUG_ST_EDMA2_ALIGN_SUB(x) ((x) << S_DEBUG_ST_EDMA2_ALIGN_SUB)
3695 #define G_DEBUG_ST_EDMA2_ALIGN_SUB(x) (((x) >> S_DEBUG_ST_EDMA2_ALIGN_SUB) & M_DEBUG_ST_EDMA2_ALIGN_SUB)
3696 
3697 #define S_DEBUG_ST_EDMA2_ALIGN    19
3698 #define M_DEBUG_ST_EDMA2_ALIGN    0x3U
3699 #define V_DEBUG_ST_EDMA2_ALIGN(x) ((x) << S_DEBUG_ST_EDMA2_ALIGN)
3700 #define G_DEBUG_ST_EDMA2_ALIGN(x) (((x) >> S_DEBUG_ST_EDMA2_ALIGN) & M_DEBUG_ST_EDMA2_ALIGN)
3701 
3702 #define S_DEBUG_ST_EDMA2_REQ    16
3703 #define M_DEBUG_ST_EDMA2_REQ    0x7U
3704 #define V_DEBUG_ST_EDMA2_REQ(x) ((x) << S_DEBUG_ST_EDMA2_REQ)
3705 #define G_DEBUG_ST_EDMA2_REQ(x) (((x) >> S_DEBUG_ST_EDMA2_REQ) & M_DEBUG_ST_EDMA2_REQ)
3706 
3707 #define S_DEBUG_ST_EDMA1_ALIGN_SUB    13
3708 #define M_DEBUG_ST_EDMA1_ALIGN_SUB    0x7U
3709 #define V_DEBUG_ST_EDMA1_ALIGN_SUB(x) ((x) << S_DEBUG_ST_EDMA1_ALIGN_SUB)
3710 #define G_DEBUG_ST_EDMA1_ALIGN_SUB(x) (((x) >> S_DEBUG_ST_EDMA1_ALIGN_SUB) & M_DEBUG_ST_EDMA1_ALIGN_SUB)
3711 
3712 #define S_DEBUG_ST_EDMA1_ALIGN    11
3713 #define M_DEBUG_ST_EDMA1_ALIGN    0x3U
3714 #define V_DEBUG_ST_EDMA1_ALIGN(x) ((x) << S_DEBUG_ST_EDMA1_ALIGN)
3715 #define G_DEBUG_ST_EDMA1_ALIGN(x) (((x) >> S_DEBUG_ST_EDMA1_ALIGN) & M_DEBUG_ST_EDMA1_ALIGN)
3716 
3717 #define S_DEBUG_ST_EDMA1_REQ    8
3718 #define M_DEBUG_ST_EDMA1_REQ    0x7U
3719 #define V_DEBUG_ST_EDMA1_REQ(x) ((x) << S_DEBUG_ST_EDMA1_REQ)
3720 #define G_DEBUG_ST_EDMA1_REQ(x) (((x) >> S_DEBUG_ST_EDMA1_REQ) & M_DEBUG_ST_EDMA1_REQ)
3721 
3722 #define S_DEBUG_ST_EDMA0_ALIGN_SUB    5
3723 #define M_DEBUG_ST_EDMA0_ALIGN_SUB    0x7U
3724 #define V_DEBUG_ST_EDMA0_ALIGN_SUB(x) ((x) << S_DEBUG_ST_EDMA0_ALIGN_SUB)
3725 #define G_DEBUG_ST_EDMA0_ALIGN_SUB(x) (((x) >> S_DEBUG_ST_EDMA0_ALIGN_SUB) & M_DEBUG_ST_EDMA0_ALIGN_SUB)
3726 
3727 #define S_DEBUG_ST_EDMA0_ALIGN    3
3728 #define M_DEBUG_ST_EDMA0_ALIGN    0x3U
3729 #define V_DEBUG_ST_EDMA0_ALIGN(x) ((x) << S_DEBUG_ST_EDMA0_ALIGN)
3730 #define G_DEBUG_ST_EDMA0_ALIGN(x) (((x) >> S_DEBUG_ST_EDMA0_ALIGN) & M_DEBUG_ST_EDMA0_ALIGN)
3731 
3732 #define S_DEBUG_ST_EDMA0_REQ    0
3733 #define M_DEBUG_ST_EDMA0_REQ    0x7U
3734 #define V_DEBUG_ST_EDMA0_REQ(x) ((x) << S_DEBUG_ST_EDMA0_REQ)
3735 #define G_DEBUG_ST_EDMA0_REQ(x) (((x) >> S_DEBUG_ST_EDMA0_REQ) & M_DEBUG_ST_EDMA0_REQ)
3736 
3737 #define A_SGE_DEBUG_DATA_LOW_INDEX_5 0x12d4
3738 
3739 #define S_DEBUG_ST_FLM_DBPTR    30
3740 #define M_DEBUG_ST_FLM_DBPTR    0x3U
3741 #define V_DEBUG_ST_FLM_DBPTR(x) ((x) << S_DEBUG_ST_FLM_DBPTR)
3742 #define G_DEBUG_ST_FLM_DBPTR(x) (((x) >> S_DEBUG_ST_FLM_DBPTR) & M_DEBUG_ST_FLM_DBPTR)
3743 
3744 #define S_DEBUG_FLM_CACHE_LOCKED_COUNT    23
3745 #define M_DEBUG_FLM_CACHE_LOCKED_COUNT    0x7fU
3746 #define V_DEBUG_FLM_CACHE_LOCKED_COUNT(x) ((x) << S_DEBUG_FLM_CACHE_LOCKED_COUNT)
3747 #define G_DEBUG_FLM_CACHE_LOCKED_COUNT(x) (((x) >> S_DEBUG_FLM_CACHE_LOCKED_COUNT) & M_DEBUG_FLM_CACHE_LOCKED_COUNT)
3748 
3749 #define S_DEBUG_FLM_CACHE_AGENT    20
3750 #define M_DEBUG_FLM_CACHE_AGENT    0x7U
3751 #define V_DEBUG_FLM_CACHE_AGENT(x) ((x) << S_DEBUG_FLM_CACHE_AGENT)
3752 #define G_DEBUG_FLM_CACHE_AGENT(x) (((x) >> S_DEBUG_FLM_CACHE_AGENT) & M_DEBUG_FLM_CACHE_AGENT)
3753 
3754 #define S_DEBUG_ST_FLM_CACHE    16
3755 #define M_DEBUG_ST_FLM_CACHE    0xfU
3756 #define V_DEBUG_ST_FLM_CACHE(x) ((x) << S_DEBUG_ST_FLM_CACHE)
3757 #define G_DEBUG_ST_FLM_CACHE(x) (((x) >> S_DEBUG_ST_FLM_CACHE) & M_DEBUG_ST_FLM_CACHE)
3758 
3759 #define S_DEBUG_FLM_DBPTR_CIDX_STALL    12
3760 #define V_DEBUG_FLM_DBPTR_CIDX_STALL(x) ((x) << S_DEBUG_FLM_DBPTR_CIDX_STALL)
3761 #define F_DEBUG_FLM_DBPTR_CIDX_STALL    V_DEBUG_FLM_DBPTR_CIDX_STALL(1U)
3762 
3763 #define S_DEBUG_FLM_DBPTR_QID    0
3764 #define M_DEBUG_FLM_DBPTR_QID    0xfffU
3765 #define V_DEBUG_FLM_DBPTR_QID(x) ((x) << S_DEBUG_FLM_DBPTR_QID)
3766 #define G_DEBUG_FLM_DBPTR_QID(x) (((x) >> S_DEBUG_FLM_DBPTR_QID) & M_DEBUG_FLM_DBPTR_QID)
3767 
3768 #define A_SGE_DEBUG0_DBP_THREAD 0x12d4
3769 
3770 #define S_THREAD_ST_MAIN    25
3771 #define M_THREAD_ST_MAIN    0x3fU
3772 #define V_THREAD_ST_MAIN(x) ((x) << S_THREAD_ST_MAIN)
3773 #define G_THREAD_ST_MAIN(x) (((x) >> S_THREAD_ST_MAIN) & M_THREAD_ST_MAIN)
3774 
3775 #define S_THREAD_ST_CIMFL    21
3776 #define M_THREAD_ST_CIMFL    0xfU
3777 #define V_THREAD_ST_CIMFL(x) ((x) << S_THREAD_ST_CIMFL)
3778 #define G_THREAD_ST_CIMFL(x) (((x) >> S_THREAD_ST_CIMFL) & M_THREAD_ST_CIMFL)
3779 
3780 #define S_THREAD_CMDOP    17
3781 #define M_THREAD_CMDOP    0xfU
3782 #define V_THREAD_CMDOP(x) ((x) << S_THREAD_CMDOP)
3783 #define G_THREAD_CMDOP(x) (((x) >> S_THREAD_CMDOP) & M_THREAD_CMDOP)
3784 
3785 #define S_THREAD_QID    0
3786 #define M_THREAD_QID    0x1ffffU
3787 #define V_THREAD_QID(x) ((x) << S_THREAD_QID)
3788 #define G_THREAD_QID(x) (((x) >> S_THREAD_QID) & M_THREAD_QID)
3789 
3790 #define A_SGE_DEBUG_DATA_LOW_INDEX_6 0x12d8
3791 
3792 #define S_DEBUG_DBP_THREAD0_QID    0
3793 #define M_DEBUG_DBP_THREAD0_QID    0x1ffffU
3794 #define V_DEBUG_DBP_THREAD0_QID(x) ((x) << S_DEBUG_DBP_THREAD0_QID)
3795 #define G_DEBUG_DBP_THREAD0_QID(x) (((x) >> S_DEBUG_DBP_THREAD0_QID) & M_DEBUG_DBP_THREAD0_QID)
3796 
3797 #define A_SGE_DEBUG_DATA_LOW_INDEX_7 0x12dc
3798 
3799 #define S_DEBUG_DBP_THREAD1_QID    0
3800 #define M_DEBUG_DBP_THREAD1_QID    0x1ffffU
3801 #define V_DEBUG_DBP_THREAD1_QID(x) ((x) << S_DEBUG_DBP_THREAD1_QID)
3802 #define G_DEBUG_DBP_THREAD1_QID(x) (((x) >> S_DEBUG_DBP_THREAD1_QID) & M_DEBUG_DBP_THREAD1_QID)
3803 
3804 #define A_SGE_DEBUG_DATA_LOW_INDEX_8 0x12e0
3805 
3806 #define S_DEBUG_DBP_THREAD2_QID    0
3807 #define M_DEBUG_DBP_THREAD2_QID    0x1ffffU
3808 #define V_DEBUG_DBP_THREAD2_QID(x) ((x) << S_DEBUG_DBP_THREAD2_QID)
3809 #define G_DEBUG_DBP_THREAD2_QID(x) (((x) >> S_DEBUG_DBP_THREAD2_QID) & M_DEBUG_DBP_THREAD2_QID)
3810 
3811 #define A_SGE_DEBUG_DATA_LOW_INDEX_9 0x12e4
3812 
3813 #define S_DEBUG_DBP_THREAD3_QID    0
3814 #define M_DEBUG_DBP_THREAD3_QID    0x1ffffU
3815 #define V_DEBUG_DBP_THREAD3_QID(x) ((x) << S_DEBUG_DBP_THREAD3_QID)
3816 #define G_DEBUG_DBP_THREAD3_QID(x) (((x) >> S_DEBUG_DBP_THREAD3_QID) & M_DEBUG_DBP_THREAD3_QID)
3817 
3818 #define A_SGE_DEBUG_DATA_LOW_INDEX_10 0x12e8
3819 
3820 #define S_DEBUG_IMSG_CPL    16
3821 #define M_DEBUG_IMSG_CPL    0xffU
3822 #define V_DEBUG_IMSG_CPL(x) ((x) << S_DEBUG_IMSG_CPL)
3823 #define G_DEBUG_IMSG_CPL(x) (((x) >> S_DEBUG_IMSG_CPL) & M_DEBUG_IMSG_CPL)
3824 
3825 #define S_DEBUG_IMSG_QID    0
3826 #define M_DEBUG_IMSG_QID    0xffffU
3827 #define V_DEBUG_IMSG_QID(x) ((x) << S_DEBUG_IMSG_QID)
3828 #define G_DEBUG_IMSG_QID(x) (((x) >> S_DEBUG_IMSG_QID) & M_DEBUG_IMSG_QID)
3829 
3830 #define A_SGE_DEBUG_DATA_LOW_INDEX_11 0x12ec
3831 
3832 #define S_DEBUG_IDMA1_QID    16
3833 #define M_DEBUG_IDMA1_QID    0xffffU
3834 #define V_DEBUG_IDMA1_QID(x) ((x) << S_DEBUG_IDMA1_QID)
3835 #define G_DEBUG_IDMA1_QID(x) (((x) >> S_DEBUG_IDMA1_QID) & M_DEBUG_IDMA1_QID)
3836 
3837 #define S_DEBUG_IDMA0_QID    0
3838 #define M_DEBUG_IDMA0_QID    0xffffU
3839 #define V_DEBUG_IDMA0_QID(x) ((x) << S_DEBUG_IDMA0_QID)
3840 #define G_DEBUG_IDMA0_QID(x) (((x) >> S_DEBUG_IDMA0_QID) & M_DEBUG_IDMA0_QID)
3841 
3842 #define A_SGE_DEBUG_DATA_LOW_INDEX_12 0x12f0
3843 
3844 #define S_DEBUG_IDMA1_FLM_REQ_QID    16
3845 #define M_DEBUG_IDMA1_FLM_REQ_QID    0xffffU
3846 #define V_DEBUG_IDMA1_FLM_REQ_QID(x) ((x) << S_DEBUG_IDMA1_FLM_REQ_QID)
3847 #define G_DEBUG_IDMA1_FLM_REQ_QID(x) (((x) >> S_DEBUG_IDMA1_FLM_REQ_QID) & M_DEBUG_IDMA1_FLM_REQ_QID)
3848 
3849 #define S_DEBUG_IDMA0_FLM_REQ_QID    0
3850 #define M_DEBUG_IDMA0_FLM_REQ_QID    0xffffU
3851 #define V_DEBUG_IDMA0_FLM_REQ_QID(x) ((x) << S_DEBUG_IDMA0_FLM_REQ_QID)
3852 #define G_DEBUG_IDMA0_FLM_REQ_QID(x) (((x) >> S_DEBUG_IDMA0_FLM_REQ_QID) & M_DEBUG_IDMA0_FLM_REQ_QID)
3853 
3854 #define A_SGE_DEBUG_DATA_LOW_INDEX_13 0x12f4
3855 #define A_SGE_DEBUG_DATA_LOW_INDEX_14 0x12f8
3856 #define A_SGE_DEBUG_DATA_LOW_INDEX_15 0x12fc
3857 #define A_SGE_QUEUE_BASE_MAP_HIGH 0x1300
3858 
3859 #define S_EGRESS_LOG2SIZE    27
3860 #define M_EGRESS_LOG2SIZE    0x1fU
3861 #define V_EGRESS_LOG2SIZE(x) ((x) << S_EGRESS_LOG2SIZE)
3862 #define G_EGRESS_LOG2SIZE(x) (((x) >> S_EGRESS_LOG2SIZE) & M_EGRESS_LOG2SIZE)
3863 
3864 #define S_EGRESS_BASE    10
3865 #define M_EGRESS_BASE    0x1ffffU
3866 #define V_EGRESS_BASE(x) ((x) << S_EGRESS_BASE)
3867 #define G_EGRESS_BASE(x) (((x) >> S_EGRESS_BASE) & M_EGRESS_BASE)
3868 
3869 #define S_INGRESS2_LOG2SIZE    5
3870 #define M_INGRESS2_LOG2SIZE    0x1fU
3871 #define V_INGRESS2_LOG2SIZE(x) ((x) << S_INGRESS2_LOG2SIZE)
3872 #define G_INGRESS2_LOG2SIZE(x) (((x) >> S_INGRESS2_LOG2SIZE) & M_INGRESS2_LOG2SIZE)
3873 
3874 #define S_INGRESS1_LOG2SIZE    0
3875 #define M_INGRESS1_LOG2SIZE    0x1fU
3876 #define V_INGRESS1_LOG2SIZE(x) ((x) << S_INGRESS1_LOG2SIZE)
3877 #define G_INGRESS1_LOG2SIZE(x) (((x) >> S_INGRESS1_LOG2SIZE) & M_INGRESS1_LOG2SIZE)
3878 
3879 #define S_EGRESS_SIZE    27
3880 #define M_EGRESS_SIZE    0x1fU
3881 #define V_EGRESS_SIZE(x) ((x) << S_EGRESS_SIZE)
3882 #define G_EGRESS_SIZE(x) (((x) >> S_EGRESS_SIZE) & M_EGRESS_SIZE)
3883 
3884 #define S_INGRESS2_SIZE    5
3885 #define M_INGRESS2_SIZE    0x1fU
3886 #define V_INGRESS2_SIZE(x) ((x) << S_INGRESS2_SIZE)
3887 #define G_INGRESS2_SIZE(x) (((x) >> S_INGRESS2_SIZE) & M_INGRESS2_SIZE)
3888 
3889 #define S_INGRESS1_SIZE    0
3890 #define M_INGRESS1_SIZE    0x1fU
3891 #define V_INGRESS1_SIZE(x) ((x) << S_INGRESS1_SIZE)
3892 #define G_INGRESS1_SIZE(x) (((x) >> S_INGRESS1_SIZE) & M_INGRESS1_SIZE)
3893 
3894 #define A_SGE_WC_EGRS_BAR2_OFF_PF 0x1300
3895 
3896 #define S_PFIQSPERPAGE    28
3897 #define M_PFIQSPERPAGE    0xfU
3898 #define V_PFIQSPERPAGE(x) ((x) << S_PFIQSPERPAGE)
3899 #define G_PFIQSPERPAGE(x) (((x) >> S_PFIQSPERPAGE) & M_PFIQSPERPAGE)
3900 
3901 #define S_PFEQSPERPAGE    24
3902 #define M_PFEQSPERPAGE    0xfU
3903 #define V_PFEQSPERPAGE(x) ((x) << S_PFEQSPERPAGE)
3904 #define G_PFEQSPERPAGE(x) (((x) >> S_PFEQSPERPAGE) & M_PFEQSPERPAGE)
3905 
3906 #define S_PFWCQSPERPAGE    20
3907 #define M_PFWCQSPERPAGE    0xfU
3908 #define V_PFWCQSPERPAGE(x) ((x) << S_PFWCQSPERPAGE)
3909 #define G_PFWCQSPERPAGE(x) (((x) >> S_PFWCQSPERPAGE) & M_PFWCQSPERPAGE)
3910 
3911 #define S_PFWCOFFEN    19
3912 #define V_PFWCOFFEN(x) ((x) << S_PFWCOFFEN)
3913 #define F_PFWCOFFEN    V_PFWCOFFEN(1U)
3914 
3915 #define S_PFMAXWCSIZE    17
3916 #define M_PFMAXWCSIZE    0x3U
3917 #define V_PFMAXWCSIZE(x) ((x) << S_PFMAXWCSIZE)
3918 #define G_PFMAXWCSIZE(x) (((x) >> S_PFMAXWCSIZE) & M_PFMAXWCSIZE)
3919 
3920 #define S_PFWCOFFSET    0
3921 #define M_PFWCOFFSET    0x1ffffU
3922 #define V_PFWCOFFSET(x) ((x) << S_PFWCOFFSET)
3923 #define G_PFWCOFFSET(x) (((x) >> S_PFWCOFFSET) & M_PFWCOFFSET)
3924 
3925 #define A_SGE_QUEUE_BASE_MAP_LOW 0x1304
3926 
3927 #define S_INGRESS2_BASE    16
3928 #define M_INGRESS2_BASE    0xffffU
3929 #define V_INGRESS2_BASE(x) ((x) << S_INGRESS2_BASE)
3930 #define G_INGRESS2_BASE(x) (((x) >> S_INGRESS2_BASE) & M_INGRESS2_BASE)
3931 
3932 #define S_INGRESS1_BASE    0
3933 #define M_INGRESS1_BASE    0xffffU
3934 #define V_INGRESS1_BASE(x) ((x) << S_INGRESS1_BASE)
3935 #define G_INGRESS1_BASE(x) (((x) >> S_INGRESS1_BASE) & M_INGRESS1_BASE)
3936 
3937 #define A_SGE_WC_EGRS_BAR2_OFF_VF 0x1320
3938 
3939 #define S_VFIQSPERPAGE    28
3940 #define M_VFIQSPERPAGE    0xfU
3941 #define V_VFIQSPERPAGE(x) ((x) << S_VFIQSPERPAGE)
3942 #define G_VFIQSPERPAGE(x) (((x) >> S_VFIQSPERPAGE) & M_VFIQSPERPAGE)
3943 
3944 #define S_VFEQSPERPAGE    24
3945 #define M_VFEQSPERPAGE    0xfU
3946 #define V_VFEQSPERPAGE(x) ((x) << S_VFEQSPERPAGE)
3947 #define G_VFEQSPERPAGE(x) (((x) >> S_VFEQSPERPAGE) & M_VFEQSPERPAGE)
3948 
3949 #define S_VFWCQSPERPAGE    20
3950 #define M_VFWCQSPERPAGE    0xfU
3951 #define V_VFWCQSPERPAGE(x) ((x) << S_VFWCQSPERPAGE)
3952 #define G_VFWCQSPERPAGE(x) (((x) >> S_VFWCQSPERPAGE) & M_VFWCQSPERPAGE)
3953 
3954 #define S_VFWCOFFEN    19
3955 #define V_VFWCOFFEN(x) ((x) << S_VFWCOFFEN)
3956 #define F_VFWCOFFEN    V_VFWCOFFEN(1U)
3957 
3958 #define S_VFMAXWCSIZE    17
3959 #define M_VFMAXWCSIZE    0x3U
3960 #define V_VFMAXWCSIZE(x) ((x) << S_VFMAXWCSIZE)
3961 #define G_VFMAXWCSIZE(x) (((x) >> S_VFMAXWCSIZE) & M_VFMAXWCSIZE)
3962 
3963 #define S_VFWCOFFSET    0
3964 #define M_VFWCOFFSET    0x1ffffU
3965 #define V_VFWCOFFSET(x) ((x) << S_VFWCOFFSET)
3966 #define G_VFWCOFFSET(x) (((x) >> S_VFWCOFFSET) & M_VFWCOFFSET)
3967 
3968 #define A_SGE_LA_RDPTR_0 0x1800
3969 #define A_SGE_LA_RDDATA_0 0x1804
3970 #define A_SGE_LA_WRPTR_0 0x1808
3971 #define A_SGE_LA_RESERVED_0 0x180c
3972 #define A_SGE_LA_RDPTR_1 0x1810
3973 #define A_SGE_LA_RDDATA_1 0x1814
3974 #define A_SGE_LA_WRPTR_1 0x1818
3975 #define A_SGE_LA_RESERVED_1 0x181c
3976 #define A_SGE_LA_RDPTR_2 0x1820
3977 #define A_SGE_LA_RDDATA_2 0x1824
3978 #define A_SGE_LA_WRPTR_2 0x1828
3979 #define A_SGE_LA_RESERVED_2 0x182c
3980 #define A_SGE_LA_RDPTR_3 0x1830
3981 #define A_SGE_LA_RDDATA_3 0x1834
3982 #define A_SGE_LA_WRPTR_3 0x1838
3983 #define A_SGE_LA_RESERVED_3 0x183c
3984 #define A_SGE_LA_RDPTR_4 0x1840
3985 #define A_SGE_LA_RDDATA_4 0x1844
3986 #define A_SGE_LA_WRPTR_4 0x1848
3987 #define A_SGE_LA_RESERVED_4 0x184c
3988 #define A_SGE_LA_RDPTR_5 0x1850
3989 #define A_SGE_LA_RDDATA_5 0x1854
3990 #define A_SGE_LA_WRPTR_5 0x1858
3991 #define A_SGE_LA_RESERVED_5 0x185c
3992 #define A_SGE_LA_RDPTR_6 0x1860
3993 #define A_SGE_LA_RDDATA_6 0x1864
3994 #define A_SGE_LA_WRPTR_6 0x1868
3995 #define A_SGE_LA_RESERVED_6 0x186c
3996 #define A_SGE_LA_RDPTR_7 0x1870
3997 #define A_SGE_LA_RDDATA_7 0x1874
3998 #define A_SGE_LA_WRPTR_7 0x1878
3999 #define A_SGE_LA_RESERVED_7 0x187c
4000 #define A_SGE_LA_RDPTR_8 0x1880
4001 #define A_SGE_LA_RDDATA_8 0x1884
4002 #define A_SGE_LA_WRPTR_8 0x1888
4003 #define A_SGE_LA_RESERVED_8 0x188c
4004 #define A_SGE_LA_RDPTR_9 0x1890
4005 #define A_SGE_LA_RDDATA_9 0x1894
4006 #define A_SGE_LA_WRPTR_9 0x1898
4007 #define A_SGE_LA_RESERVED_9 0x189c
4008 #define A_SGE_LA_RDPTR_10 0x18a0
4009 #define A_SGE_LA_RDDATA_10 0x18a4
4010 #define A_SGE_LA_WRPTR_10 0x18a8
4011 #define A_SGE_LA_RESERVED_10 0x18ac
4012 #define A_SGE_LA_RDPTR_11 0x18b0
4013 #define A_SGE_LA_RDDATA_11 0x18b4
4014 #define A_SGE_LA_WRPTR_11 0x18b8
4015 #define A_SGE_LA_RESERVED_11 0x18bc
4016 #define A_SGE_LA_RDPTR_12 0x18c0
4017 #define A_SGE_LA_RDDATA_12 0x18c4
4018 #define A_SGE_LA_WRPTR_12 0x18c8
4019 #define A_SGE_LA_RESERVED_12 0x18cc
4020 #define A_SGE_LA_RDPTR_13 0x18d0
4021 #define A_SGE_LA_RDDATA_13 0x18d4
4022 #define A_SGE_LA_WRPTR_13 0x18d8
4023 #define A_SGE_LA_RESERVED_13 0x18dc
4024 #define A_SGE_LA_RDPTR_14 0x18e0
4025 #define A_SGE_LA_RDDATA_14 0x18e4
4026 #define A_SGE_LA_WRPTR_14 0x18e8
4027 #define A_SGE_LA_RESERVED_14 0x18ec
4028 #define A_SGE_LA_RDPTR_15 0x18f0
4029 #define A_SGE_LA_RDDATA_15 0x18f4
4030 #define A_SGE_LA_WRPTR_15 0x18f8
4031 #define A_SGE_LA_RESERVED_15 0x18fc
4032 
4033 /* registers for module PCIE */
4034 #define PCIE_BASE_ADDR 0x3000
4035 
4036 #define A_PCIE_PF_CFG 0x40
4037 
4038 #define S_INTXSTAT    16
4039 #define V_INTXSTAT(x) ((x) << S_INTXSTAT)
4040 #define F_INTXSTAT    V_INTXSTAT(1U)
4041 
4042 #define S_AUXPWRPMEN    15
4043 #define V_AUXPWRPMEN(x) ((x) << S_AUXPWRPMEN)
4044 #define F_AUXPWRPMEN    V_AUXPWRPMEN(1U)
4045 
4046 #define S_NOSOFTRESET    14
4047 #define V_NOSOFTRESET(x) ((x) << S_NOSOFTRESET)
4048 #define F_NOSOFTRESET    V_NOSOFTRESET(1U)
4049 
4050 #define S_AIVEC    4
4051 #define M_AIVEC    0x3ffU
4052 #define V_AIVEC(x) ((x) << S_AIVEC)
4053 #define G_AIVEC(x) (((x) >> S_AIVEC) & M_AIVEC)
4054 
4055 #define S_INTXTYPE    2
4056 #define M_INTXTYPE    0x3U
4057 #define V_INTXTYPE(x) ((x) << S_INTXTYPE)
4058 #define G_INTXTYPE(x) (((x) >> S_INTXTYPE) & M_INTXTYPE)
4059 
4060 #define S_D3HOTEN    1
4061 #define V_D3HOTEN(x) ((x) << S_D3HOTEN)
4062 #define F_D3HOTEN    V_D3HOTEN(1U)
4063 
4064 #define S_CLIDECEN    0
4065 #define V_CLIDECEN(x) ((x) << S_CLIDECEN)
4066 #define F_CLIDECEN    V_CLIDECEN(1U)
4067 
4068 #define A_PCIE_PF_CLI 0x44
4069 #define A_PCIE_PF_GEN_MSG 0x48
4070 
4071 #define S_MSGTYPE    0
4072 #define M_MSGTYPE    0xffU
4073 #define V_MSGTYPE(x) ((x) << S_MSGTYPE)
4074 #define G_MSGTYPE(x) (((x) >> S_MSGTYPE) & M_MSGTYPE)
4075 
4076 #define A_PCIE_PF_EXPROM_OFST 0x4c
4077 
4078 #define S_OFFSET    10
4079 #define M_OFFSET    0x3fffU
4080 #define V_OFFSET(x) ((x) << S_OFFSET)
4081 #define G_OFFSET(x) (((x) >> S_OFFSET) & M_OFFSET)
4082 
4083 #define A_PCIE_INT_ENABLE 0x3000
4084 
4085 #define S_NONFATALERR    30
4086 #define V_NONFATALERR(x) ((x) << S_NONFATALERR)
4087 #define F_NONFATALERR    V_NONFATALERR(1U)
4088 
4089 #define S_UNXSPLCPLERR    29
4090 #define V_UNXSPLCPLERR(x) ((x) << S_UNXSPLCPLERR)
4091 #define F_UNXSPLCPLERR    V_UNXSPLCPLERR(1U)
4092 
4093 #define S_PCIEPINT    28
4094 #define V_PCIEPINT(x) ((x) << S_PCIEPINT)
4095 #define F_PCIEPINT    V_PCIEPINT(1U)
4096 
4097 #define S_PCIESINT    27
4098 #define V_PCIESINT(x) ((x) << S_PCIESINT)
4099 #define F_PCIESINT    V_PCIESINT(1U)
4100 
4101 #define S_RPLPERR    26
4102 #define V_RPLPERR(x) ((x) << S_RPLPERR)
4103 #define F_RPLPERR    V_RPLPERR(1U)
4104 
4105 #define S_RXWRPERR    25
4106 #define V_RXWRPERR(x) ((x) << S_RXWRPERR)
4107 #define F_RXWRPERR    V_RXWRPERR(1U)
4108 
4109 #define S_RXCPLPERR    24
4110 #define V_RXCPLPERR(x) ((x) << S_RXCPLPERR)
4111 #define F_RXCPLPERR    V_RXCPLPERR(1U)
4112 
4113 #define S_PIOTAGPERR    23
4114 #define V_PIOTAGPERR(x) ((x) << S_PIOTAGPERR)
4115 #define F_PIOTAGPERR    V_PIOTAGPERR(1U)
4116 
4117 #define S_MATAGPERR    22
4118 #define V_MATAGPERR(x) ((x) << S_MATAGPERR)
4119 #define F_MATAGPERR    V_MATAGPERR(1U)
4120 
4121 #define S_INTXCLRPERR    21
4122 #define V_INTXCLRPERR(x) ((x) << S_INTXCLRPERR)
4123 #define F_INTXCLRPERR    V_INTXCLRPERR(1U)
4124 
4125 #define S_FIDPERR    20
4126 #define V_FIDPERR(x) ((x) << S_FIDPERR)
4127 #define F_FIDPERR    V_FIDPERR(1U)
4128 
4129 #define S_CFGSNPPERR    19
4130 #define V_CFGSNPPERR(x) ((x) << S_CFGSNPPERR)
4131 #define F_CFGSNPPERR    V_CFGSNPPERR(1U)
4132 
4133 #define S_HRSPPERR    18
4134 #define V_HRSPPERR(x) ((x) << S_HRSPPERR)
4135 #define F_HRSPPERR    V_HRSPPERR(1U)
4136 
4137 #define S_HREQPERR    17
4138 #define V_HREQPERR(x) ((x) << S_HREQPERR)
4139 #define F_HREQPERR    V_HREQPERR(1U)
4140 
4141 #define S_HCNTPERR    16
4142 #define V_HCNTPERR(x) ((x) << S_HCNTPERR)
4143 #define F_HCNTPERR    V_HCNTPERR(1U)
4144 
4145 #define S_DRSPPERR    15
4146 #define V_DRSPPERR(x) ((x) << S_DRSPPERR)
4147 #define F_DRSPPERR    V_DRSPPERR(1U)
4148 
4149 #define S_DREQPERR    14
4150 #define V_DREQPERR(x) ((x) << S_DREQPERR)
4151 #define F_DREQPERR    V_DREQPERR(1U)
4152 
4153 #define S_DCNTPERR    13
4154 #define V_DCNTPERR(x) ((x) << S_DCNTPERR)
4155 #define F_DCNTPERR    V_DCNTPERR(1U)
4156 
4157 #define S_CRSPPERR    12
4158 #define V_CRSPPERR(x) ((x) << S_CRSPPERR)
4159 #define F_CRSPPERR    V_CRSPPERR(1U)
4160 
4161 #define S_CREQPERR    11
4162 #define V_CREQPERR(x) ((x) << S_CREQPERR)
4163 #define F_CREQPERR    V_CREQPERR(1U)
4164 
4165 #define S_CCNTPERR    10
4166 #define V_CCNTPERR(x) ((x) << S_CCNTPERR)
4167 #define F_CCNTPERR    V_CCNTPERR(1U)
4168 
4169 #define S_TARTAGPERR    9
4170 #define V_TARTAGPERR(x) ((x) << S_TARTAGPERR)
4171 #define F_TARTAGPERR    V_TARTAGPERR(1U)
4172 
4173 #define S_PIOREQPERR    8
4174 #define V_PIOREQPERR(x) ((x) << S_PIOREQPERR)
4175 #define F_PIOREQPERR    V_PIOREQPERR(1U)
4176 
4177 #define S_PIOCPLPERR    7
4178 #define V_PIOCPLPERR(x) ((x) << S_PIOCPLPERR)
4179 #define F_PIOCPLPERR    V_PIOCPLPERR(1U)
4180 
4181 #define S_MSIXDIPERR    6
4182 #define V_MSIXDIPERR(x) ((x) << S_MSIXDIPERR)
4183 #define F_MSIXDIPERR    V_MSIXDIPERR(1U)
4184 
4185 #define S_MSIXDATAPERR    5
4186 #define V_MSIXDATAPERR(x) ((x) << S_MSIXDATAPERR)
4187 #define F_MSIXDATAPERR    V_MSIXDATAPERR(1U)
4188 
4189 #define S_MSIXADDRHPERR    4
4190 #define V_MSIXADDRHPERR(x) ((x) << S_MSIXADDRHPERR)
4191 #define F_MSIXADDRHPERR    V_MSIXADDRHPERR(1U)
4192 
4193 #define S_MSIXADDRLPERR    3
4194 #define V_MSIXADDRLPERR(x) ((x) << S_MSIXADDRLPERR)
4195 #define F_MSIXADDRLPERR    V_MSIXADDRLPERR(1U)
4196 
4197 #define S_MSIDATAPERR    2
4198 #define V_MSIDATAPERR(x) ((x) << S_MSIDATAPERR)
4199 #define F_MSIDATAPERR    V_MSIDATAPERR(1U)
4200 
4201 #define S_MSIADDRHPERR    1
4202 #define V_MSIADDRHPERR(x) ((x) << S_MSIADDRHPERR)
4203 #define F_MSIADDRHPERR    V_MSIADDRHPERR(1U)
4204 
4205 #define S_MSIADDRLPERR    0
4206 #define V_MSIADDRLPERR(x) ((x) << S_MSIADDRLPERR)
4207 #define F_MSIADDRLPERR    V_MSIADDRLPERR(1U)
4208 
4209 #define S_IPGRPPERR    31
4210 #define V_IPGRPPERR(x) ((x) << S_IPGRPPERR)
4211 #define F_IPGRPPERR    V_IPGRPPERR(1U)
4212 
4213 #define S_READRSPERR    29
4214 #define V_READRSPERR(x) ((x) << S_READRSPERR)
4215 #define F_READRSPERR    V_READRSPERR(1U)
4216 
4217 #define S_TRGT1GRPPERR    28
4218 #define V_TRGT1GRPPERR(x) ((x) << S_TRGT1GRPPERR)
4219 #define F_TRGT1GRPPERR    V_TRGT1GRPPERR(1U)
4220 
4221 #define S_IPSOTPERR    27
4222 #define V_IPSOTPERR(x) ((x) << S_IPSOTPERR)
4223 #define F_IPSOTPERR    V_IPSOTPERR(1U)
4224 
4225 #define S_IPRETRYPERR    26
4226 #define V_IPRETRYPERR(x) ((x) << S_IPRETRYPERR)
4227 #define F_IPRETRYPERR    V_IPRETRYPERR(1U)
4228 
4229 #define S_IPRXDATAGRPPERR    25
4230 #define V_IPRXDATAGRPPERR(x) ((x) << S_IPRXDATAGRPPERR)
4231 #define F_IPRXDATAGRPPERR    V_IPRXDATAGRPPERR(1U)
4232 
4233 #define S_IPRXHDRGRPPERR    24
4234 #define V_IPRXHDRGRPPERR(x) ((x) << S_IPRXHDRGRPPERR)
4235 #define F_IPRXHDRGRPPERR    V_IPRXHDRGRPPERR(1U)
4236 
4237 #define S_PIOTAGQPERR    23
4238 #define V_PIOTAGQPERR(x) ((x) << S_PIOTAGQPERR)
4239 #define F_PIOTAGQPERR    V_PIOTAGQPERR(1U)
4240 
4241 #define S_MAGRPPERR    22
4242 #define V_MAGRPPERR(x) ((x) << S_MAGRPPERR)
4243 #define F_MAGRPPERR    V_MAGRPPERR(1U)
4244 
4245 #define S_VFIDPERR    21
4246 #define V_VFIDPERR(x) ((x) << S_VFIDPERR)
4247 #define F_VFIDPERR    V_VFIDPERR(1U)
4248 
4249 #define S_HREQRDPERR    17
4250 #define V_HREQRDPERR(x) ((x) << S_HREQRDPERR)
4251 #define F_HREQRDPERR    V_HREQRDPERR(1U)
4252 
4253 #define S_HREQWRPERR    16
4254 #define V_HREQWRPERR(x) ((x) << S_HREQWRPERR)
4255 #define F_HREQWRPERR    V_HREQWRPERR(1U)
4256 
4257 #define S_DREQRDPERR    14
4258 #define V_DREQRDPERR(x) ((x) << S_DREQRDPERR)
4259 #define F_DREQRDPERR    V_DREQRDPERR(1U)
4260 
4261 #define S_DREQWRPERR    13
4262 #define V_DREQWRPERR(x) ((x) << S_DREQWRPERR)
4263 #define F_DREQWRPERR    V_DREQWRPERR(1U)
4264 
4265 #define S_CREQRDPERR    11
4266 #define V_CREQRDPERR(x) ((x) << S_CREQRDPERR)
4267 #define F_CREQRDPERR    V_CREQRDPERR(1U)
4268 
4269 #define S_MSTTAGQPERR    10
4270 #define V_MSTTAGQPERR(x) ((x) << S_MSTTAGQPERR)
4271 #define F_MSTTAGQPERR    V_MSTTAGQPERR(1U)
4272 
4273 #define S_TGTTAGQPERR    9
4274 #define V_TGTTAGQPERR(x) ((x) << S_TGTTAGQPERR)
4275 #define F_TGTTAGQPERR    V_TGTTAGQPERR(1U)
4276 
4277 #define S_PIOREQGRPPERR    8
4278 #define V_PIOREQGRPPERR(x) ((x) << S_PIOREQGRPPERR)
4279 #define F_PIOREQGRPPERR    V_PIOREQGRPPERR(1U)
4280 
4281 #define S_PIOCPLGRPPERR    7
4282 #define V_PIOCPLGRPPERR(x) ((x) << S_PIOCPLGRPPERR)
4283 #define F_PIOCPLGRPPERR    V_PIOCPLGRPPERR(1U)
4284 
4285 #define S_MSIXSTIPERR    2
4286 #define V_MSIXSTIPERR(x) ((x) << S_MSIXSTIPERR)
4287 #define F_MSIXSTIPERR    V_MSIXSTIPERR(1U)
4288 
4289 #define S_MSTTIMEOUTPERR    1
4290 #define V_MSTTIMEOUTPERR(x) ((x) << S_MSTTIMEOUTPERR)
4291 #define F_MSTTIMEOUTPERR    V_MSTTIMEOUTPERR(1U)
4292 
4293 #define S_MSTGRPPERR    0
4294 #define V_MSTGRPPERR(x) ((x) << S_MSTGRPPERR)
4295 #define F_MSTGRPPERR    V_MSTGRPPERR(1U)
4296 
4297 #define A_PCIE_INT_CAUSE 0x3004
4298 #define A_PCIE_PERR_ENABLE 0x3008
4299 #define A_PCIE_PERR_INJECT 0x300c
4300 
4301 #define S_IDE    0
4302 #define V_IDE(x) ((x) << S_IDE)
4303 #define F_IDE    V_IDE(1U)
4304 
4305 #define S_MEMSEL_PCIE    1
4306 #define M_MEMSEL_PCIE    0x1fU
4307 #define V_MEMSEL_PCIE(x) ((x) << S_MEMSEL_PCIE)
4308 #define G_MEMSEL_PCIE(x) (((x) >> S_MEMSEL_PCIE) & M_MEMSEL_PCIE)
4309 
4310 #define A_PCIE_NONFAT_ERR 0x3010
4311 
4312 #define S_RDRSPERR    9
4313 #define V_RDRSPERR(x) ((x) << S_RDRSPERR)
4314 #define F_RDRSPERR    V_RDRSPERR(1U)
4315 
4316 #define S_VPDRSPERR    8
4317 #define V_VPDRSPERR(x) ((x) << S_VPDRSPERR)
4318 #define F_VPDRSPERR    V_VPDRSPERR(1U)
4319 
4320 #define S_POPD    7
4321 #define V_POPD(x) ((x) << S_POPD)
4322 #define F_POPD    V_POPD(1U)
4323 
4324 #define S_POPH    6
4325 #define V_POPH(x) ((x) << S_POPH)
4326 #define F_POPH    V_POPH(1U)
4327 
4328 #define S_POPC    5
4329 #define V_POPC(x) ((x) << S_POPC)
4330 #define F_POPC    V_POPC(1U)
4331 
4332 #define S_MEMREQ    4
4333 #define V_MEMREQ(x) ((x) << S_MEMREQ)
4334 #define F_MEMREQ    V_MEMREQ(1U)
4335 
4336 #define S_PIOREQ    3
4337 #define V_PIOREQ(x) ((x) << S_PIOREQ)
4338 #define F_PIOREQ    V_PIOREQ(1U)
4339 
4340 #define S_TAGDROP    2
4341 #define V_TAGDROP(x) ((x) << S_TAGDROP)
4342 #define F_TAGDROP    V_TAGDROP(1U)
4343 
4344 #define S_TAGCPL    1
4345 #define V_TAGCPL(x) ((x) << S_TAGCPL)
4346 #define F_TAGCPL    V_TAGCPL(1U)
4347 
4348 #define S_CFGSNP    0
4349 #define V_CFGSNP(x) ((x) << S_CFGSNP)
4350 #define F_CFGSNP    V_CFGSNP(1U)
4351 
4352 #define S_MAREQTIMEOUT    29
4353 #define V_MAREQTIMEOUT(x) ((x) << S_MAREQTIMEOUT)
4354 #define F_MAREQTIMEOUT    V_MAREQTIMEOUT(1U)
4355 
4356 #define S_TRGT1BARTYPEERR    28
4357 #define V_TRGT1BARTYPEERR(x) ((x) << S_TRGT1BARTYPEERR)
4358 #define F_TRGT1BARTYPEERR    V_TRGT1BARTYPEERR(1U)
4359 
4360 #define S_MAEXTRARSPERR    27
4361 #define V_MAEXTRARSPERR(x) ((x) << S_MAEXTRARSPERR)
4362 #define F_MAEXTRARSPERR    V_MAEXTRARSPERR(1U)
4363 
4364 #define S_MARSPTIMEOUT    26
4365 #define V_MARSPTIMEOUT(x) ((x) << S_MARSPTIMEOUT)
4366 #define F_MARSPTIMEOUT    V_MARSPTIMEOUT(1U)
4367 
4368 #define S_INTVFALLMSIDISERR    25
4369 #define V_INTVFALLMSIDISERR(x) ((x) << S_INTVFALLMSIDISERR)
4370 #define F_INTVFALLMSIDISERR    V_INTVFALLMSIDISERR(1U)
4371 
4372 #define S_INTVFRANGEERR    24
4373 #define V_INTVFRANGEERR(x) ((x) << S_INTVFRANGEERR)
4374 #define F_INTVFRANGEERR    V_INTVFRANGEERR(1U)
4375 
4376 #define S_INTPLIRSPERR    23
4377 #define V_INTPLIRSPERR(x) ((x) << S_INTPLIRSPERR)
4378 #define F_INTPLIRSPERR    V_INTPLIRSPERR(1U)
4379 
4380 #define S_MEMREQRDTAGERR    22
4381 #define V_MEMREQRDTAGERR(x) ((x) << S_MEMREQRDTAGERR)
4382 #define F_MEMREQRDTAGERR    V_MEMREQRDTAGERR(1U)
4383 
4384 #define S_CFGINITDONEERR    21
4385 #define V_CFGINITDONEERR(x) ((x) << S_CFGINITDONEERR)
4386 #define F_CFGINITDONEERR    V_CFGINITDONEERR(1U)
4387 
4388 #define S_BAR2TIMEOUT    20
4389 #define V_BAR2TIMEOUT(x) ((x) << S_BAR2TIMEOUT)
4390 #define F_BAR2TIMEOUT    V_BAR2TIMEOUT(1U)
4391 
4392 #define S_VPDTIMEOUT    19
4393 #define V_VPDTIMEOUT(x) ((x) << S_VPDTIMEOUT)
4394 #define F_VPDTIMEOUT    V_VPDTIMEOUT(1U)
4395 
4396 #define S_MEMRSPRDTAGERR    18
4397 #define V_MEMRSPRDTAGERR(x) ((x) << S_MEMRSPRDTAGERR)
4398 #define F_MEMRSPRDTAGERR    V_MEMRSPRDTAGERR(1U)
4399 
4400 #define S_MEMRSPWRTAGERR    17
4401 #define V_MEMRSPWRTAGERR(x) ((x) << S_MEMRSPWRTAGERR)
4402 #define F_MEMRSPWRTAGERR    V_MEMRSPWRTAGERR(1U)
4403 
4404 #define S_PIORSPRDTAGERR    16
4405 #define V_PIORSPRDTAGERR(x) ((x) << S_PIORSPRDTAGERR)
4406 #define F_PIORSPRDTAGERR    V_PIORSPRDTAGERR(1U)
4407 
4408 #define S_PIORSPWRTAGERR    15
4409 #define V_PIORSPWRTAGERR(x) ((x) << S_PIORSPWRTAGERR)
4410 #define F_PIORSPWRTAGERR    V_PIORSPWRTAGERR(1U)
4411 
4412 #define S_DBITIMEOUT    14
4413 #define V_DBITIMEOUT(x) ((x) << S_DBITIMEOUT)
4414 #define F_DBITIMEOUT    V_DBITIMEOUT(1U)
4415 
4416 #define S_PIOUNALINDWR    13
4417 #define V_PIOUNALINDWR(x) ((x) << S_PIOUNALINDWR)
4418 #define F_PIOUNALINDWR    V_PIOUNALINDWR(1U)
4419 
4420 #define S_BAR2RDERR    12
4421 #define V_BAR2RDERR(x) ((x) << S_BAR2RDERR)
4422 #define F_BAR2RDERR    V_BAR2RDERR(1U)
4423 
4424 #define S_MAWREOPERR    11
4425 #define V_MAWREOPERR(x) ((x) << S_MAWREOPERR)
4426 #define F_MAWREOPERR    V_MAWREOPERR(1U)
4427 
4428 #define S_MARDEOPERR    10
4429 #define V_MARDEOPERR(x) ((x) << S_MARDEOPERR)
4430 #define F_MARDEOPERR    V_MARDEOPERR(1U)
4431 
4432 #define S_BAR2REQ    2
4433 #define V_BAR2REQ(x) ((x) << S_BAR2REQ)
4434 #define F_BAR2REQ    V_BAR2REQ(1U)
4435 
4436 #define S_MARSPUE    30
4437 #define V_MARSPUE(x) ((x) << S_MARSPUE)
4438 #define F_MARSPUE    V_MARSPUE(1U)
4439 
4440 #define S_KDBEOPERR    7
4441 #define V_KDBEOPERR(x) ((x) << S_KDBEOPERR)
4442 #define F_KDBEOPERR    V_KDBEOPERR(1U)
4443 
4444 #define A_PCIE_CFG 0x3014
4445 
4446 #define S_CFGDMAXPYLDSZRX    26
4447 #define M_CFGDMAXPYLDSZRX    0x7U
4448 #define V_CFGDMAXPYLDSZRX(x) ((x) << S_CFGDMAXPYLDSZRX)
4449 #define G_CFGDMAXPYLDSZRX(x) (((x) >> S_CFGDMAXPYLDSZRX) & M_CFGDMAXPYLDSZRX)
4450 
4451 #define S_CFGDMAXPYLDSZTX    23
4452 #define M_CFGDMAXPYLDSZTX    0x7U
4453 #define V_CFGDMAXPYLDSZTX(x) ((x) << S_CFGDMAXPYLDSZTX)
4454 #define G_CFGDMAXPYLDSZTX(x) (((x) >> S_CFGDMAXPYLDSZTX) & M_CFGDMAXPYLDSZTX)
4455 
4456 #define S_CFGDMAXRDREQSZ    20
4457 #define M_CFGDMAXRDREQSZ    0x7U
4458 #define V_CFGDMAXRDREQSZ(x) ((x) << S_CFGDMAXRDREQSZ)
4459 #define G_CFGDMAXRDREQSZ(x) (((x) >> S_CFGDMAXRDREQSZ) & M_CFGDMAXRDREQSZ)
4460 
4461 #define S_MASYNCEN    19
4462 #define V_MASYNCEN(x) ((x) << S_MASYNCEN)
4463 #define F_MASYNCEN    V_MASYNCEN(1U)
4464 
4465 #define S_DCAENDMA    18
4466 #define V_DCAENDMA(x) ((x) << S_DCAENDMA)
4467 #define F_DCAENDMA    V_DCAENDMA(1U)
4468 
4469 #define S_DCAENCMD    17
4470 #define V_DCAENCMD(x) ((x) << S_DCAENCMD)
4471 #define F_DCAENCMD    V_DCAENCMD(1U)
4472 
4473 #define S_VFMSIPNDEN    16
4474 #define V_VFMSIPNDEN(x) ((x) << S_VFMSIPNDEN)
4475 #define F_VFMSIPNDEN    V_VFMSIPNDEN(1U)
4476 
4477 #define S_FORCETXERROR    15
4478 #define V_FORCETXERROR(x) ((x) << S_FORCETXERROR)
4479 #define F_FORCETXERROR    V_FORCETXERROR(1U)
4480 
4481 #define S_VPDREQPROTECT    14
4482 #define V_VPDREQPROTECT(x) ((x) << S_VPDREQPROTECT)
4483 #define F_VPDREQPROTECT    V_VPDREQPROTECT(1U)
4484 
4485 #define S_FIDTABLEINVALID    13
4486 #define V_FIDTABLEINVALID(x) ((x) << S_FIDTABLEINVALID)
4487 #define F_FIDTABLEINVALID    V_FIDTABLEINVALID(1U)
4488 
4489 #define S_BYPASSMSIXCACHE    12
4490 #define V_BYPASSMSIXCACHE(x) ((x) << S_BYPASSMSIXCACHE)
4491 #define F_BYPASSMSIXCACHE    V_BYPASSMSIXCACHE(1U)
4492 
4493 #define S_BYPASSMSICACHE    11
4494 #define V_BYPASSMSICACHE(x) ((x) << S_BYPASSMSICACHE)
4495 #define F_BYPASSMSICACHE    V_BYPASSMSICACHE(1U)
4496 
4497 #define S_SIMSPEED    10
4498 #define V_SIMSPEED(x) ((x) << S_SIMSPEED)
4499 #define F_SIMSPEED    V_SIMSPEED(1U)
4500 
4501 #define S_TC0_STAMP    9
4502 #define V_TC0_STAMP(x) ((x) << S_TC0_STAMP)
4503 #define F_TC0_STAMP    V_TC0_STAMP(1U)
4504 
4505 #define S_AI_TCVAL    6
4506 #define M_AI_TCVAL    0x7U
4507 #define V_AI_TCVAL(x) ((x) << S_AI_TCVAL)
4508 #define G_AI_TCVAL(x) (((x) >> S_AI_TCVAL) & M_AI_TCVAL)
4509 
4510 #define S_DMASTOPEN    5
4511 #define V_DMASTOPEN(x) ((x) << S_DMASTOPEN)
4512 #define F_DMASTOPEN    V_DMASTOPEN(1U)
4513 
4514 #define S_DEVSTATERSTMODE    4
4515 #define V_DEVSTATERSTMODE(x) ((x) << S_DEVSTATERSTMODE)
4516 #define F_DEVSTATERSTMODE    V_DEVSTATERSTMODE(1U)
4517 
4518 #define S_HOTRSTPCIECRSTMODE    3
4519 #define V_HOTRSTPCIECRSTMODE(x) ((x) << S_HOTRSTPCIECRSTMODE)
4520 #define F_HOTRSTPCIECRSTMODE    V_HOTRSTPCIECRSTMODE(1U)
4521 
4522 #define S_DLDNPCIECRSTMODE    2
4523 #define V_DLDNPCIECRSTMODE(x) ((x) << S_DLDNPCIECRSTMODE)
4524 #define F_DLDNPCIECRSTMODE    V_DLDNPCIECRSTMODE(1U)
4525 
4526 #define S_DLDNPCIEPRECRSTMODE    1
4527 #define V_DLDNPCIEPRECRSTMODE(x) ((x) << S_DLDNPCIEPRECRSTMODE)
4528 #define F_DLDNPCIEPRECRSTMODE    V_DLDNPCIEPRECRSTMODE(1U)
4529 
4530 #define S_LINKDNRSTEN    0
4531 #define V_LINKDNRSTEN(x) ((x) << S_LINKDNRSTEN)
4532 #define F_LINKDNRSTEN    V_LINKDNRSTEN(1U)
4533 
4534 #define S_T5_PIOSTOPEN    31
4535 #define V_T5_PIOSTOPEN(x) ((x) << S_T5_PIOSTOPEN)
4536 #define F_T5_PIOSTOPEN    V_T5_PIOSTOPEN(1U)
4537 
4538 #define S_DIAGCTRLBUS    28
4539 #define M_DIAGCTRLBUS    0x7U
4540 #define V_DIAGCTRLBUS(x) ((x) << S_DIAGCTRLBUS)
4541 #define G_DIAGCTRLBUS(x) (((x) >> S_DIAGCTRLBUS) & M_DIAGCTRLBUS)
4542 
4543 #define S_IPPERREN    27
4544 #define V_IPPERREN(x) ((x) << S_IPPERREN)
4545 #define F_IPPERREN    V_IPPERREN(1U)
4546 
4547 #define S_CFGDEXTTAGEN    26
4548 #define V_CFGDEXTTAGEN(x) ((x) << S_CFGDEXTTAGEN)
4549 #define F_CFGDEXTTAGEN    V_CFGDEXTTAGEN(1U)
4550 
4551 #define S_CFGDMAXPYLDSZ    23
4552 #define M_CFGDMAXPYLDSZ    0x7U
4553 #define V_CFGDMAXPYLDSZ(x) ((x) << S_CFGDMAXPYLDSZ)
4554 #define G_CFGDMAXPYLDSZ(x) (((x) >> S_CFGDMAXPYLDSZ) & M_CFGDMAXPYLDSZ)
4555 
4556 #define S_DCAEN    17
4557 #define V_DCAEN(x) ((x) << S_DCAEN)
4558 #define F_DCAEN    V_DCAEN(1U)
4559 
4560 #define S_T5CMDREQPRIORITY    16
4561 #define V_T5CMDREQPRIORITY(x) ((x) << S_T5CMDREQPRIORITY)
4562 #define F_T5CMDREQPRIORITY    V_T5CMDREQPRIORITY(1U)
4563 
4564 #define S_T5VPDREQPROTECT    14
4565 #define M_T5VPDREQPROTECT    0x3U
4566 #define V_T5VPDREQPROTECT(x) ((x) << S_T5VPDREQPROTECT)
4567 #define G_T5VPDREQPROTECT(x) (((x) >> S_T5VPDREQPROTECT) & M_T5VPDREQPROTECT)
4568 
4569 #define S_DROPPEDRDRSPDATA    12
4570 #define V_DROPPEDRDRSPDATA(x) ((x) << S_DROPPEDRDRSPDATA)
4571 #define F_DROPPEDRDRSPDATA    V_DROPPEDRDRSPDATA(1U)
4572 
4573 #define S_AI_INTX_REASSERTEN    11
4574 #define V_AI_INTX_REASSERTEN(x) ((x) << S_AI_INTX_REASSERTEN)
4575 #define F_AI_INTX_REASSERTEN    V_AI_INTX_REASSERTEN(1U)
4576 
4577 #define S_AUTOTXNDISABLE    10
4578 #define V_AUTOTXNDISABLE(x) ((x) << S_AUTOTXNDISABLE)
4579 #define F_AUTOTXNDISABLE    V_AUTOTXNDISABLE(1U)
4580 
4581 #define S_LINKREQRSTPCIECRSTMODE    3
4582 #define V_LINKREQRSTPCIECRSTMODE(x) ((x) << S_LINKREQRSTPCIECRSTMODE)
4583 #define F_LINKREQRSTPCIECRSTMODE    V_LINKREQRSTPCIECRSTMODE(1U)
4584 
4585 #define S_T6_PIOSTOPEN    31
4586 #define V_T6_PIOSTOPEN(x) ((x) << S_T6_PIOSTOPEN)
4587 #define F_T6_PIOSTOPEN    V_T6_PIOSTOPEN(1U)
4588 
4589 #define A_PCIE_DMA_CTRL 0x3018
4590 
4591 #define S_LITTLEENDIAN    7
4592 #define V_LITTLEENDIAN(x) ((x) << S_LITTLEENDIAN)
4593 #define F_LITTLEENDIAN    V_LITTLEENDIAN(1U)
4594 
4595 #define A_PCIE_CFG2 0x3018
4596 
4597 #define S_VPDTIMER    16
4598 #define M_VPDTIMER    0xffffU
4599 #define V_VPDTIMER(x) ((x) << S_VPDTIMER)
4600 #define G_VPDTIMER(x) (((x) >> S_VPDTIMER) & M_VPDTIMER)
4601 
4602 #define S_BAR2TIMER    4
4603 #define M_BAR2TIMER    0xfffU
4604 #define V_BAR2TIMER(x) ((x) << S_BAR2TIMER)
4605 #define G_BAR2TIMER(x) (((x) >> S_BAR2TIMER) & M_BAR2TIMER)
4606 
4607 #define S_MSTREQRDRRASIMPLE    3
4608 #define V_MSTREQRDRRASIMPLE(x) ((x) << S_MSTREQRDRRASIMPLE)
4609 #define F_MSTREQRDRRASIMPLE    V_MSTREQRDRRASIMPLE(1U)
4610 
4611 #define S_TOTMAXTAG    0
4612 #define M_TOTMAXTAG    0x3U
4613 #define V_TOTMAXTAG(x) ((x) << S_TOTMAXTAG)
4614 #define G_TOTMAXTAG(x) (((x) >> S_TOTMAXTAG) & M_TOTMAXTAG)
4615 
4616 #define S_T6_TOTMAXTAG    0
4617 #define M_T6_TOTMAXTAG    0x7U
4618 #define V_T6_TOTMAXTAG(x) ((x) << S_T6_TOTMAXTAG)
4619 #define G_T6_TOTMAXTAG(x) (((x) >> S_T6_TOTMAXTAG) & M_T6_TOTMAXTAG)
4620 
4621 #define A_PCIE_DMA_CFG 0x301c
4622 
4623 #define S_MAXPYLDSIZE    28
4624 #define M_MAXPYLDSIZE    0x7U
4625 #define V_MAXPYLDSIZE(x) ((x) << S_MAXPYLDSIZE)
4626 #define G_MAXPYLDSIZE(x) (((x) >> S_MAXPYLDSIZE) & M_MAXPYLDSIZE)
4627 
4628 #define S_MAXRDREQSIZE    25
4629 #define M_MAXRDREQSIZE    0x7U
4630 #define V_MAXRDREQSIZE(x) ((x) << S_MAXRDREQSIZE)
4631 #define G_MAXRDREQSIZE(x) (((x) >> S_MAXRDREQSIZE) & M_MAXRDREQSIZE)
4632 
4633 #define S_DMA_MAXRSPCNT    16
4634 #define M_DMA_MAXRSPCNT    0x1ffU
4635 #define V_DMA_MAXRSPCNT(x) ((x) << S_DMA_MAXRSPCNT)
4636 #define G_DMA_MAXRSPCNT(x) (((x) >> S_DMA_MAXRSPCNT) & M_DMA_MAXRSPCNT)
4637 
4638 #define S_DMA_MAXREQCNT    8
4639 #define M_DMA_MAXREQCNT    0xffU
4640 #define V_DMA_MAXREQCNT(x) ((x) << S_DMA_MAXREQCNT)
4641 #define G_DMA_MAXREQCNT(x) (((x) >> S_DMA_MAXREQCNT) & M_DMA_MAXREQCNT)
4642 
4643 #define S_MAXTAG    0
4644 #define M_MAXTAG    0x7fU
4645 #define V_MAXTAG(x) ((x) << S_MAXTAG)
4646 #define G_MAXTAG(x) (((x) >> S_MAXTAG) & M_MAXTAG)
4647 
4648 #define A_PCIE_CFG3 0x301c
4649 
4650 #define S_AUTOPIOCOOKIEMATCH    6
4651 #define V_AUTOPIOCOOKIEMATCH(x) ((x) << S_AUTOPIOCOOKIEMATCH)
4652 #define F_AUTOPIOCOOKIEMATCH    V_AUTOPIOCOOKIEMATCH(1U)
4653 
4654 #define S_FLRPNDCPLMODE    4
4655 #define M_FLRPNDCPLMODE    0x3U
4656 #define V_FLRPNDCPLMODE(x) ((x) << S_FLRPNDCPLMODE)
4657 #define G_FLRPNDCPLMODE(x) (((x) >> S_FLRPNDCPLMODE) & M_FLRPNDCPLMODE)
4658 
4659 #define S_HMADCASTFIRSTONLY    2
4660 #define V_HMADCASTFIRSTONLY(x) ((x) << S_HMADCASTFIRSTONLY)
4661 #define F_HMADCASTFIRSTONLY    V_HMADCASTFIRSTONLY(1U)
4662 
4663 #define S_CMDDCASTFIRSTONLY    1
4664 #define V_CMDDCASTFIRSTONLY(x) ((x) << S_CMDDCASTFIRSTONLY)
4665 #define F_CMDDCASTFIRSTONLY    V_CMDDCASTFIRSTONLY(1U)
4666 
4667 #define S_DMADCASTFIRSTONLY    0
4668 #define V_DMADCASTFIRSTONLY(x) ((x) << S_DMADCASTFIRSTONLY)
4669 #define F_DMADCASTFIRSTONLY    V_DMADCASTFIRSTONLY(1U)
4670 
4671 #define A_PCIE_DMA_STAT 0x3020
4672 
4673 #define S_STATEREQ    28
4674 #define M_STATEREQ    0xfU
4675 #define V_STATEREQ(x) ((x) << S_STATEREQ)
4676 #define G_STATEREQ(x) (((x) >> S_STATEREQ) & M_STATEREQ)
4677 
4678 #define S_DMA_RSPCNT    16
4679 #define M_DMA_RSPCNT    0xfffU
4680 #define V_DMA_RSPCNT(x) ((x) << S_DMA_RSPCNT)
4681 #define G_DMA_RSPCNT(x) (((x) >> S_DMA_RSPCNT) & M_DMA_RSPCNT)
4682 
4683 #define S_STATEAREQ    13
4684 #define M_STATEAREQ    0x7U
4685 #define V_STATEAREQ(x) ((x) << S_STATEAREQ)
4686 #define G_STATEAREQ(x) (((x) >> S_STATEAREQ) & M_STATEAREQ)
4687 
4688 #define S_TAGFREE    12
4689 #define V_TAGFREE(x) ((x) << S_TAGFREE)
4690 #define F_TAGFREE    V_TAGFREE(1U)
4691 
4692 #define S_DMA_REQCNT    0
4693 #define M_DMA_REQCNT    0x7ffU
4694 #define V_DMA_REQCNT(x) ((x) << S_DMA_REQCNT)
4695 #define G_DMA_REQCNT(x) (((x) >> S_DMA_REQCNT) & M_DMA_REQCNT)
4696 
4697 #define A_PCIE_CFG4 0x3020
4698 
4699 #define S_L1CLKREMOVALEN    17
4700 #define V_L1CLKREMOVALEN(x) ((x) << S_L1CLKREMOVALEN)
4701 #define F_L1CLKREMOVALEN    V_L1CLKREMOVALEN(1U)
4702 
4703 #define S_READYENTERL23    16
4704 #define V_READYENTERL23(x) ((x) << S_READYENTERL23)
4705 #define F_READYENTERL23    V_READYENTERL23(1U)
4706 
4707 #define S_EXITL1    12
4708 #define V_EXITL1(x) ((x) << S_EXITL1)
4709 #define F_EXITL1    V_EXITL1(1U)
4710 
4711 #define S_ENTERL1    8
4712 #define V_ENTERL1(x) ((x) << S_ENTERL1)
4713 #define F_ENTERL1    V_ENTERL1(1U)
4714 
4715 #define S_GENPME    0
4716 #define M_GENPME    0xffU
4717 #define V_GENPME(x) ((x) << S_GENPME)
4718 #define G_GENPME(x) (((x) >> S_GENPME) & M_GENPME)
4719 
4720 #define A_PCIE_CFG5 0x3024
4721 
4722 #define S_ENABLESKPPARITYFIX    2
4723 #define V_ENABLESKPPARITYFIX(x) ((x) << S_ENABLESKPPARITYFIX)
4724 #define F_ENABLESKPPARITYFIX    V_ENABLESKPPARITYFIX(1U)
4725 
4726 #define S_ENABLEL2ENTRYINL1    1
4727 #define V_ENABLEL2ENTRYINL1(x) ((x) << S_ENABLEL2ENTRYINL1)
4728 #define F_ENABLEL2ENTRYINL1    V_ENABLEL2ENTRYINL1(1U)
4729 
4730 #define S_HOLDCPLENTERINGL1    0
4731 #define V_HOLDCPLENTERINGL1(x) ((x) << S_HOLDCPLENTERINGL1)
4732 #define F_HOLDCPLENTERINGL1    V_HOLDCPLENTERINGL1(1U)
4733 
4734 #define A_PCIE_CFG6 0x3028
4735 
4736 #define S_PERSTTIMERCOUNT    12
4737 #define M_PERSTTIMERCOUNT    0x3fffU
4738 #define V_PERSTTIMERCOUNT(x) ((x) << S_PERSTTIMERCOUNT)
4739 #define G_PERSTTIMERCOUNT(x) (((x) >> S_PERSTTIMERCOUNT) & M_PERSTTIMERCOUNT)
4740 
4741 #define S_PERSTTIMEOUT    8
4742 #define V_PERSTTIMEOUT(x) ((x) << S_PERSTTIMEOUT)
4743 #define F_PERSTTIMEOUT    V_PERSTTIMEOUT(1U)
4744 
4745 #define S_PERSTTIMER    0
4746 #define M_PERSTTIMER    0xfU
4747 #define V_PERSTTIMER(x) ((x) << S_PERSTTIMER)
4748 #define G_PERSTTIMER(x) (((x) >> S_PERSTTIMER) & M_PERSTTIMER)
4749 
4750 #define A_PCIE_CFG7 0x302c
4751 #define A_PCIE_CMD_CTRL 0x303c
4752 #define A_PCIE_CMD_CFG 0x3040
4753 
4754 #define S_MAXRSPCNT    16
4755 #define M_MAXRSPCNT    0xfU
4756 #define V_MAXRSPCNT(x) ((x) << S_MAXRSPCNT)
4757 #define G_MAXRSPCNT(x) (((x) >> S_MAXRSPCNT) & M_MAXRSPCNT)
4758 
4759 #define S_MAXREQCNT    8
4760 #define M_MAXREQCNT    0x1fU
4761 #define V_MAXREQCNT(x) ((x) << S_MAXREQCNT)
4762 #define G_MAXREQCNT(x) (((x) >> S_MAXREQCNT) & M_MAXREQCNT)
4763 
4764 #define A_PCIE_CMD_STAT 0x3044
4765 
4766 #define S_RSPCNT    16
4767 #define M_RSPCNT    0x7fU
4768 #define V_RSPCNT(x) ((x) << S_RSPCNT)
4769 #define G_RSPCNT(x) (((x) >> S_RSPCNT) & M_RSPCNT)
4770 
4771 #define S_REQCNT    0
4772 #define M_REQCNT    0xffU
4773 #define V_REQCNT(x) ((x) << S_REQCNT)
4774 #define G_REQCNT(x) (((x) >> S_REQCNT) & M_REQCNT)
4775 
4776 #define A_PCIE_HMA_CTRL 0x3050
4777 
4778 #define S_IPLTSSM    12
4779 #define M_IPLTSSM    0xfU
4780 #define V_IPLTSSM(x) ((x) << S_IPLTSSM)
4781 #define G_IPLTSSM(x) (((x) >> S_IPLTSSM) & M_IPLTSSM)
4782 
4783 #define S_IPCONFIGDOWN    8
4784 #define M_IPCONFIGDOWN    0x7U
4785 #define V_IPCONFIGDOWN(x) ((x) << S_IPCONFIGDOWN)
4786 #define G_IPCONFIGDOWN(x) (((x) >> S_IPCONFIGDOWN) & M_IPCONFIGDOWN)
4787 
4788 #define A_PCIE_HMA_CFG 0x3054
4789 
4790 #define S_HMA_MAXRSPCNT    16
4791 #define M_HMA_MAXRSPCNT    0x1fU
4792 #define V_HMA_MAXRSPCNT(x) ((x) << S_HMA_MAXRSPCNT)
4793 #define G_HMA_MAXRSPCNT(x) (((x) >> S_HMA_MAXRSPCNT) & M_HMA_MAXRSPCNT)
4794 
4795 #define A_PCIE_HMA_STAT 0x3058
4796 
4797 #define S_HMA_RSPCNT    16
4798 #define M_HMA_RSPCNT    0xffU
4799 #define V_HMA_RSPCNT(x) ((x) << S_HMA_RSPCNT)
4800 #define G_HMA_RSPCNT(x) (((x) >> S_HMA_RSPCNT) & M_HMA_RSPCNT)
4801 
4802 #define A_PCIE_PIO_FIFO_CFG 0x305c
4803 
4804 #define S_CPLCONFIG    16
4805 #define M_CPLCONFIG    0xffffU
4806 #define V_CPLCONFIG(x) ((x) << S_CPLCONFIG)
4807 #define G_CPLCONFIG(x) (((x) >> S_CPLCONFIG) & M_CPLCONFIG)
4808 
4809 #define S_PIOSTOPEN    12
4810 #define V_PIOSTOPEN(x) ((x) << S_PIOSTOPEN)
4811 #define F_PIOSTOPEN    V_PIOSTOPEN(1U)
4812 
4813 #define S_IPLANESWAP    11
4814 #define V_IPLANESWAP(x) ((x) << S_IPLANESWAP)
4815 #define F_IPLANESWAP    V_IPLANESWAP(1U)
4816 
4817 #define S_FORCESTRICTTS1    10
4818 #define V_FORCESTRICTTS1(x) ((x) << S_FORCESTRICTTS1)
4819 #define F_FORCESTRICTTS1    V_FORCESTRICTTS1(1U)
4820 
4821 #define S_FORCEPROGRESSCNT    0
4822 #define M_FORCEPROGRESSCNT    0x3ffU
4823 #define V_FORCEPROGRESSCNT(x) ((x) << S_FORCEPROGRESSCNT)
4824 #define G_FORCEPROGRESSCNT(x) (((x) >> S_FORCEPROGRESSCNT) & M_FORCEPROGRESSCNT)
4825 
4826 #define A_PCIE_CFG_SPACE_REQ 0x3060
4827 
4828 #define S_ENABLE    30
4829 #define V_ENABLE(x) ((x) << S_ENABLE)
4830 #define F_ENABLE    V_ENABLE(1U)
4831 
4832 #define S_AI    29
4833 #define V_AI(x) ((x) << S_AI)
4834 #define F_AI    V_AI(1U)
4835 
4836 #define S_LOCALCFG    28
4837 #define V_LOCALCFG(x) ((x) << S_LOCALCFG)
4838 #define F_LOCALCFG    V_LOCALCFG(1U)
4839 
4840 #define S_BUS    20
4841 #define M_BUS    0xffU
4842 #define V_BUS(x) ((x) << S_BUS)
4843 #define G_BUS(x) (((x) >> S_BUS) & M_BUS)
4844 
4845 #define S_DEVICE    15
4846 #define M_DEVICE    0x1fU
4847 #define V_DEVICE(x) ((x) << S_DEVICE)
4848 #define G_DEVICE(x) (((x) >> S_DEVICE) & M_DEVICE)
4849 
4850 #define S_FUNCTION    12
4851 #define M_FUNCTION    0x7U
4852 #define V_FUNCTION(x) ((x) << S_FUNCTION)
4853 #define G_FUNCTION(x) (((x) >> S_FUNCTION) & M_FUNCTION)
4854 
4855 #define S_EXTREGISTER    8
4856 #define M_EXTREGISTER    0xfU
4857 #define V_EXTREGISTER(x) ((x) << S_EXTREGISTER)
4858 #define G_EXTREGISTER(x) (((x) >> S_EXTREGISTER) & M_EXTREGISTER)
4859 
4860 #define S_REGISTER    0
4861 #define M_REGISTER    0xffU
4862 #define V_REGISTER(x) ((x) << S_REGISTER)
4863 #define G_REGISTER(x) (((x) >> S_REGISTER) & M_REGISTER)
4864 
4865 #define S_CS2    28
4866 #define V_CS2(x) ((x) << S_CS2)
4867 #define F_CS2    V_CS2(1U)
4868 
4869 #define S_WRBE    24
4870 #define M_WRBE    0xfU
4871 #define V_WRBE(x) ((x) << S_WRBE)
4872 #define G_WRBE(x) (((x) >> S_WRBE) & M_WRBE)
4873 
4874 #define S_CFG_SPACE_VFVLD    23
4875 #define V_CFG_SPACE_VFVLD(x) ((x) << S_CFG_SPACE_VFVLD)
4876 #define F_CFG_SPACE_VFVLD    V_CFG_SPACE_VFVLD(1U)
4877 
4878 #define S_CFG_SPACE_RVF    16
4879 #define M_CFG_SPACE_RVF    0x7fU
4880 #define V_CFG_SPACE_RVF(x) ((x) << S_CFG_SPACE_RVF)
4881 #define G_CFG_SPACE_RVF(x) (((x) >> S_CFG_SPACE_RVF) & M_CFG_SPACE_RVF)
4882 
4883 #define S_CFG_SPACE_PF    12
4884 #define M_CFG_SPACE_PF    0x7U
4885 #define V_CFG_SPACE_PF(x) ((x) << S_CFG_SPACE_PF)
4886 #define G_CFG_SPACE_PF(x) (((x) >> S_CFG_SPACE_PF) & M_CFG_SPACE_PF)
4887 
4888 #define S_T6_ENABLE    31
4889 #define V_T6_ENABLE(x) ((x) << S_T6_ENABLE)
4890 #define F_T6_ENABLE    V_T6_ENABLE(1U)
4891 
4892 #define S_T6_AI    30
4893 #define V_T6_AI(x) ((x) << S_T6_AI)
4894 #define F_T6_AI    V_T6_AI(1U)
4895 
4896 #define S_T6_CS2    29
4897 #define V_T6_CS2(x) ((x) << S_T6_CS2)
4898 #define F_T6_CS2    V_T6_CS2(1U)
4899 
4900 #define S_T6_WRBE    25
4901 #define M_T6_WRBE    0xfU
4902 #define V_T6_WRBE(x) ((x) << S_T6_WRBE)
4903 #define G_T6_WRBE(x) (((x) >> S_T6_WRBE) & M_T6_WRBE)
4904 
4905 #define S_T6_CFG_SPACE_VFVLD    24
4906 #define V_T6_CFG_SPACE_VFVLD(x) ((x) << S_T6_CFG_SPACE_VFVLD)
4907 #define F_T6_CFG_SPACE_VFVLD    V_T6_CFG_SPACE_VFVLD(1U)
4908 
4909 #define S_T6_CFG_SPACE_RVF    16
4910 #define M_T6_CFG_SPACE_RVF    0xffU
4911 #define V_T6_CFG_SPACE_RVF(x) ((x) << S_T6_CFG_SPACE_RVF)
4912 #define G_T6_CFG_SPACE_RVF(x) (((x) >> S_T6_CFG_SPACE_RVF) & M_T6_CFG_SPACE_RVF)
4913 
4914 #define A_PCIE_CFG_SPACE_DATA 0x3064
4915 #define A_PCIE_MEM_ACCESS_BASE_WIN 0x3068
4916 
4917 #define S_PCIEOFST    10
4918 #define M_PCIEOFST    0x3fffffU
4919 #define V_PCIEOFST(x) ((x) << S_PCIEOFST)
4920 #define G_PCIEOFST(x) (((x) >> S_PCIEOFST) & M_PCIEOFST)
4921 
4922 #define S_BIR    8
4923 #define M_BIR    0x3U
4924 #define V_BIR(x) ((x) << S_BIR)
4925 #define G_BIR(x) (((x) >> S_BIR) & M_BIR)
4926 
4927 #define S_WINDOW    0
4928 #define M_WINDOW    0xffU
4929 #define V_WINDOW(x) ((x) << S_WINDOW)
4930 #define G_WINDOW(x) (((x) >> S_WINDOW) & M_WINDOW)
4931 
4932 #define A_PCIE_MEM_ACCESS_OFFSET 0x306c
4933 
4934 #define S_MEMOFST    7
4935 #define M_MEMOFST    0x1ffffffU
4936 #define V_MEMOFST(x) ((x) << S_MEMOFST)
4937 #define G_MEMOFST(x) (((x) >> S_MEMOFST) & M_MEMOFST)
4938 
4939 #define A_PCIE_MAILBOX_BASE_WIN 0x30a8
4940 
4941 #define S_MBOXPCIEOFST    6
4942 #define M_MBOXPCIEOFST    0x3ffffffU
4943 #define V_MBOXPCIEOFST(x) ((x) << S_MBOXPCIEOFST)
4944 #define G_MBOXPCIEOFST(x) (((x) >> S_MBOXPCIEOFST) & M_MBOXPCIEOFST)
4945 
4946 #define S_MBOXBIR    4
4947 #define M_MBOXBIR    0x3U
4948 #define V_MBOXBIR(x) ((x) << S_MBOXBIR)
4949 #define G_MBOXBIR(x) (((x) >> S_MBOXBIR) & M_MBOXBIR)
4950 
4951 #define S_MBOXWIN    0
4952 #define M_MBOXWIN    0x3U
4953 #define V_MBOXWIN(x) ((x) << S_MBOXWIN)
4954 #define G_MBOXWIN(x) (((x) >> S_MBOXWIN) & M_MBOXWIN)
4955 
4956 #define A_PCIE_MAILBOX_OFFSET 0x30ac
4957 #define A_PCIE_MA_CTRL 0x30b0
4958 
4959 #define S_MA_TAGFREE    29
4960 #define V_MA_TAGFREE(x) ((x) << S_MA_TAGFREE)
4961 #define F_MA_TAGFREE    V_MA_TAGFREE(1U)
4962 
4963 #define S_MA_MAXRSPCNT    24
4964 #define M_MA_MAXRSPCNT    0x1fU
4965 #define V_MA_MAXRSPCNT(x) ((x) << S_MA_MAXRSPCNT)
4966 #define G_MA_MAXRSPCNT(x) (((x) >> S_MA_MAXRSPCNT) & M_MA_MAXRSPCNT)
4967 
4968 #define S_MA_MAXREQCNT    16
4969 #define M_MA_MAXREQCNT    0x1fU
4970 #define V_MA_MAXREQCNT(x) ((x) << S_MA_MAXREQCNT)
4971 #define G_MA_MAXREQCNT(x) (((x) >> S_MA_MAXREQCNT) & M_MA_MAXREQCNT)
4972 
4973 #define S_MA_LE    15
4974 #define V_MA_LE(x) ((x) << S_MA_LE)
4975 #define F_MA_LE    V_MA_LE(1U)
4976 
4977 #define S_MA_MAXPYLDSIZE    12
4978 #define M_MA_MAXPYLDSIZE    0x7U
4979 #define V_MA_MAXPYLDSIZE(x) ((x) << S_MA_MAXPYLDSIZE)
4980 #define G_MA_MAXPYLDSIZE(x) (((x) >> S_MA_MAXPYLDSIZE) & M_MA_MAXPYLDSIZE)
4981 
4982 #define S_MA_MAXRDREQSIZE    8
4983 #define M_MA_MAXRDREQSIZE    0x7U
4984 #define V_MA_MAXRDREQSIZE(x) ((x) << S_MA_MAXRDREQSIZE)
4985 #define G_MA_MAXRDREQSIZE(x) (((x) >> S_MA_MAXRDREQSIZE) & M_MA_MAXRDREQSIZE)
4986 
4987 #define S_MA_MAXTAG    0
4988 #define M_MA_MAXTAG    0x1fU
4989 #define V_MA_MAXTAG(x) ((x) << S_MA_MAXTAG)
4990 #define G_MA_MAXTAG(x) (((x) >> S_MA_MAXTAG) & M_MA_MAXTAG)
4991 
4992 #define S_T5_MA_MAXREQCNT    16
4993 #define M_T5_MA_MAXREQCNT    0x7fU
4994 #define V_T5_MA_MAXREQCNT(x) ((x) << S_T5_MA_MAXREQCNT)
4995 #define G_T5_MA_MAXREQCNT(x) (((x) >> S_T5_MA_MAXREQCNT) & M_T5_MA_MAXREQCNT)
4996 
4997 #define S_MA_MAXREQSIZE    8
4998 #define M_MA_MAXREQSIZE    0x7U
4999 #define V_MA_MAXREQSIZE(x) ((x) << S_MA_MAXREQSIZE)
5000 #define G_MA_MAXREQSIZE(x) (((x) >> S_MA_MAXREQSIZE) & M_MA_MAXREQSIZE)
5001 
5002 #define A_PCIE_MA_SYNC 0x30b4
5003 #define A_PCIE_FW 0x30b8
5004 #define A_PCIE_FW_PF 0x30bc
5005 #define A_PCIE_PIO_PAUSE 0x30dc
5006 
5007 #define S_PIOPAUSEDONE    31
5008 #define V_PIOPAUSEDONE(x) ((x) << S_PIOPAUSEDONE)
5009 #define F_PIOPAUSEDONE    V_PIOPAUSEDONE(1U)
5010 
5011 #define S_PIOPAUSETIME    4
5012 #define M_PIOPAUSETIME    0xffffffU
5013 #define V_PIOPAUSETIME(x) ((x) << S_PIOPAUSETIME)
5014 #define G_PIOPAUSETIME(x) (((x) >> S_PIOPAUSETIME) & M_PIOPAUSETIME)
5015 
5016 #define S_PIOPAUSE    0
5017 #define V_PIOPAUSE(x) ((x) << S_PIOPAUSE)
5018 #define F_PIOPAUSE    V_PIOPAUSE(1U)
5019 
5020 #define S_MSTPAUSEDONE    30
5021 #define V_MSTPAUSEDONE(x) ((x) << S_MSTPAUSEDONE)
5022 #define F_MSTPAUSEDONE    V_MSTPAUSEDONE(1U)
5023 
5024 #define S_MSTPAUSE    1
5025 #define V_MSTPAUSE(x) ((x) << S_MSTPAUSE)
5026 #define F_MSTPAUSE    V_MSTPAUSE(1U)
5027 
5028 #define A_PCIE_SYS_CFG_READY 0x30e0
5029 #define A_PCIE_MA_STAT 0x30e0
5030 #define A_PCIE_STATIC_CFG1 0x30e4
5031 
5032 #define S_LINKDOWN_RESET_EN    26
5033 #define V_LINKDOWN_RESET_EN(x) ((x) << S_LINKDOWN_RESET_EN)
5034 #define F_LINKDOWN_RESET_EN    V_LINKDOWN_RESET_EN(1U)
5035 
5036 #define S_IN_WR_DISCONTIG    25
5037 #define V_IN_WR_DISCONTIG(x) ((x) << S_IN_WR_DISCONTIG)
5038 #define F_IN_WR_DISCONTIG    V_IN_WR_DISCONTIG(1U)
5039 
5040 #define S_IN_RD_CPLSIZE    22
5041 #define M_IN_RD_CPLSIZE    0x7U
5042 #define V_IN_RD_CPLSIZE(x) ((x) << S_IN_RD_CPLSIZE)
5043 #define G_IN_RD_CPLSIZE(x) (((x) >> S_IN_RD_CPLSIZE) & M_IN_RD_CPLSIZE)
5044 
5045 #define S_IN_RD_BUFMODE    20
5046 #define M_IN_RD_BUFMODE    0x3U
5047 #define V_IN_RD_BUFMODE(x) ((x) << S_IN_RD_BUFMODE)
5048 #define G_IN_RD_BUFMODE(x) (((x) >> S_IN_RD_BUFMODE) & M_IN_RD_BUFMODE)
5049 
5050 #define S_GBIF_NPTRANS_TOT    18
5051 #define M_GBIF_NPTRANS_TOT    0x3U
5052 #define V_GBIF_NPTRANS_TOT(x) ((x) << S_GBIF_NPTRANS_TOT)
5053 #define G_GBIF_NPTRANS_TOT(x) (((x) >> S_GBIF_NPTRANS_TOT) & M_GBIF_NPTRANS_TOT)
5054 
5055 #define S_IN_PDAT_TOT    15
5056 #define M_IN_PDAT_TOT    0x7U
5057 #define V_IN_PDAT_TOT(x) ((x) << S_IN_PDAT_TOT)
5058 #define G_IN_PDAT_TOT(x) (((x) >> S_IN_PDAT_TOT) & M_IN_PDAT_TOT)
5059 
5060 #define S_PCIE_NPTRANS_TOT    12
5061 #define M_PCIE_NPTRANS_TOT    0x7U
5062 #define V_PCIE_NPTRANS_TOT(x) ((x) << S_PCIE_NPTRANS_TOT)
5063 #define G_PCIE_NPTRANS_TOT(x) (((x) >> S_PCIE_NPTRANS_TOT) & M_PCIE_NPTRANS_TOT)
5064 
5065 #define S_OUT_PDAT_TOT    9
5066 #define M_OUT_PDAT_TOT    0x7U
5067 #define V_OUT_PDAT_TOT(x) ((x) << S_OUT_PDAT_TOT)
5068 #define G_OUT_PDAT_TOT(x) (((x) >> S_OUT_PDAT_TOT) & M_OUT_PDAT_TOT)
5069 
5070 #define S_GBIF_MAX_WRSIZE    6
5071 #define M_GBIF_MAX_WRSIZE    0x7U
5072 #define V_GBIF_MAX_WRSIZE(x) ((x) << S_GBIF_MAX_WRSIZE)
5073 #define G_GBIF_MAX_WRSIZE(x) (((x) >> S_GBIF_MAX_WRSIZE) & M_GBIF_MAX_WRSIZE)
5074 
5075 #define S_GBIF_MAX_RDSIZE    3
5076 #define M_GBIF_MAX_RDSIZE    0x7U
5077 #define V_GBIF_MAX_RDSIZE(x) ((x) << S_GBIF_MAX_RDSIZE)
5078 #define G_GBIF_MAX_RDSIZE(x) (((x) >> S_GBIF_MAX_RDSIZE) & M_GBIF_MAX_RDSIZE)
5079 
5080 #define S_PCIE_MAX_RDSIZE    0
5081 #define M_PCIE_MAX_RDSIZE    0x7U
5082 #define V_PCIE_MAX_RDSIZE(x) ((x) << S_PCIE_MAX_RDSIZE)
5083 #define G_PCIE_MAX_RDSIZE(x) (((x) >> S_PCIE_MAX_RDSIZE) & M_PCIE_MAX_RDSIZE)
5084 
5085 #define S_AUXPOWER_DETECTED    27
5086 #define V_AUXPOWER_DETECTED(x) ((x) << S_AUXPOWER_DETECTED)
5087 #define F_AUXPOWER_DETECTED    V_AUXPOWER_DETECTED(1U)
5088 
5089 #define A_PCIE_STATIC_CFG2 0x30e8
5090 
5091 #define S_PL_CONTROL    16
5092 #define M_PL_CONTROL    0xffffU
5093 #define V_PL_CONTROL(x) ((x) << S_PL_CONTROL)
5094 #define G_PL_CONTROL(x) (((x) >> S_PL_CONTROL) & M_PL_CONTROL)
5095 
5096 #define S_STATIC_SPARE3    0
5097 #define M_STATIC_SPARE3    0x3fffU
5098 #define V_STATIC_SPARE3(x) ((x) << S_STATIC_SPARE3)
5099 #define G_STATIC_SPARE3(x) (((x) >> S_STATIC_SPARE3) & M_STATIC_SPARE3)
5100 
5101 #define A_PCIE_DBG_INDIR_REQ 0x30ec
5102 
5103 #define S_DBGENABLE    31
5104 #define V_DBGENABLE(x) ((x) << S_DBGENABLE)
5105 #define F_DBGENABLE    V_DBGENABLE(1U)
5106 
5107 #define S_DBGAUTOINC    30
5108 #define V_DBGAUTOINC(x) ((x) << S_DBGAUTOINC)
5109 #define F_DBGAUTOINC    V_DBGAUTOINC(1U)
5110 
5111 #define S_POINTER    8
5112 #define M_POINTER    0xffffU
5113 #define V_POINTER(x) ((x) << S_POINTER)
5114 #define G_POINTER(x) (((x) >> S_POINTER) & M_POINTER)
5115 
5116 #define S_SELECT    0
5117 #define M_SELECT    0xfU
5118 #define V_SELECT(x) ((x) << S_SELECT)
5119 #define G_SELECT(x) (((x) >> S_SELECT) & M_SELECT)
5120 
5121 #define A_PCIE_DBG_INDIR_DATA_0 0x30f0
5122 #define A_PCIE_DBG_INDIR_DATA_1 0x30f4
5123 #define A_PCIE_DBG_INDIR_DATA_2 0x30f8
5124 #define A_PCIE_DBG_INDIR_DATA_3 0x30fc
5125 #define A_PCIE_FUNC_INT_CFG 0x3100
5126 
5127 #define S_PBAOFST    28
5128 #define M_PBAOFST    0xfU
5129 #define V_PBAOFST(x) ((x) << S_PBAOFST)
5130 #define G_PBAOFST(x) (((x) >> S_PBAOFST) & M_PBAOFST)
5131 
5132 #define S_TABOFST    24
5133 #define M_TABOFST    0xfU
5134 #define V_TABOFST(x) ((x) << S_TABOFST)
5135 #define G_TABOFST(x) (((x) >> S_TABOFST) & M_TABOFST)
5136 
5137 #define S_VECNUM    12
5138 #define M_VECNUM    0x3ffU
5139 #define V_VECNUM(x) ((x) << S_VECNUM)
5140 #define G_VECNUM(x) (((x) >> S_VECNUM) & M_VECNUM)
5141 
5142 #define S_VECBASE    0
5143 #define M_VECBASE    0x7ffU
5144 #define V_VECBASE(x) ((x) << S_VECBASE)
5145 #define G_VECBASE(x) (((x) >> S_VECBASE) & M_VECBASE)
5146 
5147 #define A_PCIE_FUNC_CTL_STAT 0x3104
5148 
5149 #define S_SENDFLRRSP    31
5150 #define V_SENDFLRRSP(x) ((x) << S_SENDFLRRSP)
5151 #define F_SENDFLRRSP    V_SENDFLRRSP(1U)
5152 
5153 #define S_IMMFLRRSP    24
5154 #define V_IMMFLRRSP(x) ((x) << S_IMMFLRRSP)
5155 #define F_IMMFLRRSP    V_IMMFLRRSP(1U)
5156 
5157 #define S_TXNDISABLE    20
5158 #define V_TXNDISABLE(x) ((x) << S_TXNDISABLE)
5159 #define F_TXNDISABLE    V_TXNDISABLE(1U)
5160 
5161 #define S_PNDTXNS    8
5162 #define M_PNDTXNS    0x3ffU
5163 #define V_PNDTXNS(x) ((x) << S_PNDTXNS)
5164 #define G_PNDTXNS(x) (((x) >> S_PNDTXNS) & M_PNDTXNS)
5165 
5166 #define S_VFVLD    3
5167 #define V_VFVLD(x) ((x) << S_VFVLD)
5168 #define F_VFVLD    V_VFVLD(1U)
5169 
5170 #define S_PFNUM    0
5171 #define M_PFNUM    0x7U
5172 #define V_PFNUM(x) ((x) << S_PFNUM)
5173 #define G_PFNUM(x) (((x) >> S_PFNUM) & M_PFNUM)
5174 
5175 #define A_PCIE_PF_INT_CFG 0x3140
5176 #define A_PCIE_PF_INT_CFG2 0x3144
5177 #define A_PCIE_VF_INT_CFG 0x3180
5178 #define A_PCIE_VF_INT_CFG2 0x3184
5179 #define A_PCIE_PF_MSI_EN 0x35a8
5180 
5181 #define S_PFMSIEN_7_0    0
5182 #define M_PFMSIEN_7_0    0xffU
5183 #define V_PFMSIEN_7_0(x) ((x) << S_PFMSIEN_7_0)
5184 #define G_PFMSIEN_7_0(x) (((x) >> S_PFMSIEN_7_0) & M_PFMSIEN_7_0)
5185 
5186 #define A_PCIE_VF_MSI_EN_0 0x35ac
5187 #define A_PCIE_VF_MSI_EN_1 0x35b0
5188 #define A_PCIE_VF_MSI_EN_2 0x35b4
5189 #define A_PCIE_VF_MSI_EN_3 0x35b8
5190 #define A_PCIE_PF_MSIX_EN 0x35bc
5191 
5192 #define S_PFMSIXEN_7_0    0
5193 #define M_PFMSIXEN_7_0    0xffU
5194 #define V_PFMSIXEN_7_0(x) ((x) << S_PFMSIXEN_7_0)
5195 #define G_PFMSIXEN_7_0(x) (((x) >> S_PFMSIXEN_7_0) & M_PFMSIXEN_7_0)
5196 
5197 #define A_PCIE_VF_MSIX_EN_0 0x35c0
5198 #define A_PCIE_VF_MSIX_EN_1 0x35c4
5199 #define A_PCIE_VF_MSIX_EN_2 0x35c8
5200 #define A_PCIE_VF_MSIX_EN_3 0x35cc
5201 #define A_PCIE_FID_VFID_SEL 0x35ec
5202 
5203 #define S_FID_VFID_SEL_SELECT    0
5204 #define M_FID_VFID_SEL_SELECT    0x3U
5205 #define V_FID_VFID_SEL_SELECT(x) ((x) << S_FID_VFID_SEL_SELECT)
5206 #define G_FID_VFID_SEL_SELECT(x) (((x) >> S_FID_VFID_SEL_SELECT) & M_FID_VFID_SEL_SELECT)
5207 
5208 #define A_PCIE_FID_VFID 0x3600
5209 
5210 #define S_FID_VFID_SELECT    30
5211 #define M_FID_VFID_SELECT    0x3U
5212 #define V_FID_VFID_SELECT(x) ((x) << S_FID_VFID_SELECT)
5213 #define G_FID_VFID_SELECT(x) (((x) >> S_FID_VFID_SELECT) & M_FID_VFID_SELECT)
5214 
5215 #define S_IDO    24
5216 #define V_IDO(x) ((x) << S_IDO)
5217 #define F_IDO    V_IDO(1U)
5218 
5219 #define S_FID_VFID_VFID    16
5220 #define M_FID_VFID_VFID    0xffU
5221 #define V_FID_VFID_VFID(x) ((x) << S_FID_VFID_VFID)
5222 #define G_FID_VFID_VFID(x) (((x) >> S_FID_VFID_VFID) & M_FID_VFID_VFID)
5223 
5224 #define S_FID_VFID_TC    11
5225 #define M_FID_VFID_TC    0x7U
5226 #define V_FID_VFID_TC(x) ((x) << S_FID_VFID_TC)
5227 #define G_FID_VFID_TC(x) (((x) >> S_FID_VFID_TC) & M_FID_VFID_TC)
5228 
5229 #define S_FID_VFID_VFVLD    10
5230 #define V_FID_VFID_VFVLD(x) ((x) << S_FID_VFID_VFVLD)
5231 #define F_FID_VFID_VFVLD    V_FID_VFID_VFVLD(1U)
5232 
5233 #define S_FID_VFID_PF    7
5234 #define M_FID_VFID_PF    0x7U
5235 #define V_FID_VFID_PF(x) ((x) << S_FID_VFID_PF)
5236 #define G_FID_VFID_PF(x) (((x) >> S_FID_VFID_PF) & M_FID_VFID_PF)
5237 
5238 #define S_FID_VFID_RVF    0
5239 #define M_FID_VFID_RVF    0x7fU
5240 #define V_FID_VFID_RVF(x) ((x) << S_FID_VFID_RVF)
5241 #define G_FID_VFID_RVF(x) (((x) >> S_FID_VFID_RVF) & M_FID_VFID_RVF)
5242 
5243 #define S_T6_FID_VFID_VFID    15
5244 #define M_T6_FID_VFID_VFID    0x1ffU
5245 #define V_T6_FID_VFID_VFID(x) ((x) << S_T6_FID_VFID_VFID)
5246 #define G_T6_FID_VFID_VFID(x) (((x) >> S_T6_FID_VFID_VFID) & M_T6_FID_VFID_VFID)
5247 
5248 #define S_T6_FID_VFID_TC    12
5249 #define M_T6_FID_VFID_TC    0x7U
5250 #define V_T6_FID_VFID_TC(x) ((x) << S_T6_FID_VFID_TC)
5251 #define G_T6_FID_VFID_TC(x) (((x) >> S_T6_FID_VFID_TC) & M_T6_FID_VFID_TC)
5252 
5253 #define S_T6_FID_VFID_VFVLD    11
5254 #define V_T6_FID_VFID_VFVLD(x) ((x) << S_T6_FID_VFID_VFVLD)
5255 #define F_T6_FID_VFID_VFVLD    V_T6_FID_VFID_VFVLD(1U)
5256 
5257 #define S_T6_FID_VFID_PF    8
5258 #define M_T6_FID_VFID_PF    0x7U
5259 #define V_T6_FID_VFID_PF(x) ((x) << S_T6_FID_VFID_PF)
5260 #define G_T6_FID_VFID_PF(x) (((x) >> S_T6_FID_VFID_PF) & M_T6_FID_VFID_PF)
5261 
5262 #define S_T6_FID_VFID_RVF    0
5263 #define M_T6_FID_VFID_RVF    0xffU
5264 #define V_T6_FID_VFID_RVF(x) ((x) << S_T6_FID_VFID_RVF)
5265 #define G_T6_FID_VFID_RVF(x) (((x) >> S_T6_FID_VFID_RVF) & M_T6_FID_VFID_RVF)
5266 
5267 #define A_PCIE_FID 0x3900
5268 
5269 #define S_PAD    11
5270 #define V_PAD(x) ((x) << S_PAD)
5271 #define F_PAD    V_PAD(1U)
5272 
5273 #define S_TC    8
5274 #define M_TC    0x7U
5275 #define V_TC(x) ((x) << S_TC)
5276 #define G_TC(x) (((x) >> S_TC) & M_TC)
5277 
5278 #define S_FUNC    0
5279 #define M_FUNC    0xffU
5280 #define V_FUNC(x) ((x) << S_FUNC)
5281 #define G_FUNC(x) (((x) >> S_FUNC) & M_FUNC)
5282 
5283 #define A_PCIE_COOKIE_STAT 0x5600
5284 
5285 #define S_COOKIEB    16
5286 #define M_COOKIEB    0x3ffU
5287 #define V_COOKIEB(x) ((x) << S_COOKIEB)
5288 #define G_COOKIEB(x) (((x) >> S_COOKIEB) & M_COOKIEB)
5289 
5290 #define S_COOKIEA    0
5291 #define M_COOKIEA    0x3ffU
5292 #define V_COOKIEA(x) ((x) << S_COOKIEA)
5293 #define G_COOKIEA(x) (((x) >> S_COOKIEA) & M_COOKIEA)
5294 
5295 #define A_PCIE_FLR_PIO 0x5620
5296 
5297 #define S_RCVDBAR2COOKIE    24
5298 #define M_RCVDBAR2COOKIE    0xffU
5299 #define V_RCVDBAR2COOKIE(x) ((x) << S_RCVDBAR2COOKIE)
5300 #define G_RCVDBAR2COOKIE(x) (((x) >> S_RCVDBAR2COOKIE) & M_RCVDBAR2COOKIE)
5301 
5302 #define S_RCVDMARSPCOOKIE    16
5303 #define M_RCVDMARSPCOOKIE    0xffU
5304 #define V_RCVDMARSPCOOKIE(x) ((x) << S_RCVDMARSPCOOKIE)
5305 #define G_RCVDMARSPCOOKIE(x) (((x) >> S_RCVDMARSPCOOKIE) & M_RCVDMARSPCOOKIE)
5306 
5307 #define S_RCVDPIORSPCOOKIE    8
5308 #define M_RCVDPIORSPCOOKIE    0xffU
5309 #define V_RCVDPIORSPCOOKIE(x) ((x) << S_RCVDPIORSPCOOKIE)
5310 #define G_RCVDPIORSPCOOKIE(x) (((x) >> S_RCVDPIORSPCOOKIE) & M_RCVDPIORSPCOOKIE)
5311 
5312 #define S_EXPDCOOKIE    0
5313 #define M_EXPDCOOKIE    0xffU
5314 #define V_EXPDCOOKIE(x) ((x) << S_EXPDCOOKIE)
5315 #define G_EXPDCOOKIE(x) (((x) >> S_EXPDCOOKIE) & M_EXPDCOOKIE)
5316 
5317 #define A_PCIE_FLR_PIO2 0x5624
5318 
5319 #define S_RCVDMAREQCOOKIE    16
5320 #define M_RCVDMAREQCOOKIE    0xffU
5321 #define V_RCVDMAREQCOOKIE(x) ((x) << S_RCVDMAREQCOOKIE)
5322 #define G_RCVDMAREQCOOKIE(x) (((x) >> S_RCVDMAREQCOOKIE) & M_RCVDMAREQCOOKIE)
5323 
5324 #define S_RCVDPIOREQCOOKIE    8
5325 #define M_RCVDPIOREQCOOKIE    0xffU
5326 #define V_RCVDPIOREQCOOKIE(x) ((x) << S_RCVDPIOREQCOOKIE)
5327 #define G_RCVDPIOREQCOOKIE(x) (((x) >> S_RCVDPIOREQCOOKIE) & M_RCVDPIOREQCOOKIE)
5328 
5329 #define S_RCVDVDMRXCOOKIE    24
5330 #define M_RCVDVDMRXCOOKIE    0xffU
5331 #define V_RCVDVDMRXCOOKIE(x) ((x) << S_RCVDVDMRXCOOKIE)
5332 #define G_RCVDVDMRXCOOKIE(x) (((x) >> S_RCVDVDMRXCOOKIE) & M_RCVDVDMRXCOOKIE)
5333 
5334 #define S_RCVDVDMTXCOOKIE    16
5335 #define M_RCVDVDMTXCOOKIE    0xffU
5336 #define V_RCVDVDMTXCOOKIE(x) ((x) << S_RCVDVDMTXCOOKIE)
5337 #define G_RCVDVDMTXCOOKIE(x) (((x) >> S_RCVDVDMTXCOOKIE) & M_RCVDVDMTXCOOKIE)
5338 
5339 #define S_T6_RCVDMAREQCOOKIE    8
5340 #define M_T6_RCVDMAREQCOOKIE    0xffU
5341 #define V_T6_RCVDMAREQCOOKIE(x) ((x) << S_T6_RCVDMAREQCOOKIE)
5342 #define G_T6_RCVDMAREQCOOKIE(x) (((x) >> S_T6_RCVDMAREQCOOKIE) & M_T6_RCVDMAREQCOOKIE)
5343 
5344 #define S_T6_RCVDPIOREQCOOKIE    0
5345 #define M_T6_RCVDPIOREQCOOKIE    0xffU
5346 #define V_T6_RCVDPIOREQCOOKIE(x) ((x) << S_T6_RCVDPIOREQCOOKIE)
5347 #define G_T6_RCVDPIOREQCOOKIE(x) (((x) >> S_T6_RCVDPIOREQCOOKIE) & M_T6_RCVDPIOREQCOOKIE)
5348 
5349 #define A_PCIE_VC0_CDTS0 0x56cc
5350 
5351 #define S_CPLD0    20
5352 #define M_CPLD0    0xfffU
5353 #define V_CPLD0(x) ((x) << S_CPLD0)
5354 #define G_CPLD0(x) (((x) >> S_CPLD0) & M_CPLD0)
5355 
5356 #define S_PH0    12
5357 #define M_PH0    0xffU
5358 #define V_PH0(x) ((x) << S_PH0)
5359 #define G_PH0(x) (((x) >> S_PH0) & M_PH0)
5360 
5361 #define S_PD0    0
5362 #define M_PD0    0xfffU
5363 #define V_PD0(x) ((x) << S_PD0)
5364 #define G_PD0(x) (((x) >> S_PD0) & M_PD0)
5365 
5366 #define A_PCIE_VC0_CDTS1 0x56d0
5367 
5368 #define S_CPLH0    20
5369 #define M_CPLH0    0xffU
5370 #define V_CPLH0(x) ((x) << S_CPLH0)
5371 #define G_CPLH0(x) (((x) >> S_CPLH0) & M_CPLH0)
5372 
5373 #define S_NPH0    12
5374 #define M_NPH0    0xffU
5375 #define V_NPH0(x) ((x) << S_NPH0)
5376 #define G_NPH0(x) (((x) >> S_NPH0) & M_NPH0)
5377 
5378 #define S_NPD0    0
5379 #define M_NPD0    0xfffU
5380 #define V_NPD0(x) ((x) << S_NPD0)
5381 #define G_NPD0(x) (((x) >> S_NPD0) & M_NPD0)
5382 
5383 #define A_PCIE_VC1_CDTS0 0x56d4
5384 
5385 #define S_CPLD1    20
5386 #define M_CPLD1    0xfffU
5387 #define V_CPLD1(x) ((x) << S_CPLD1)
5388 #define G_CPLD1(x) (((x) >> S_CPLD1) & M_CPLD1)
5389 
5390 #define S_PH1    12
5391 #define M_PH1    0xffU
5392 #define V_PH1(x) ((x) << S_PH1)
5393 #define G_PH1(x) (((x) >> S_PH1) & M_PH1)
5394 
5395 #define S_PD1    0
5396 #define M_PD1    0xfffU
5397 #define V_PD1(x) ((x) << S_PD1)
5398 #define G_PD1(x) (((x) >> S_PD1) & M_PD1)
5399 
5400 #define A_PCIE_VC1_CDTS1 0x56d8
5401 
5402 #define S_CPLH1    20
5403 #define M_CPLH1    0xffU
5404 #define V_CPLH1(x) ((x) << S_CPLH1)
5405 #define G_CPLH1(x) (((x) >> S_CPLH1) & M_CPLH1)
5406 
5407 #define S_NPH1    12
5408 #define M_NPH1    0xffU
5409 #define V_NPH1(x) ((x) << S_NPH1)
5410 #define G_NPH1(x) (((x) >> S_NPH1) & M_NPH1)
5411 
5412 #define S_NPD1    0
5413 #define M_NPD1    0xfffU
5414 #define V_NPD1(x) ((x) << S_NPD1)
5415 #define G_NPD1(x) (((x) >> S_NPD1) & M_NPD1)
5416 
5417 #define A_PCIE_FLR_PF_STATUS 0x56dc
5418 #define A_PCIE_FLR_VF0_STATUS 0x56e0
5419 #define A_PCIE_FLR_VF1_STATUS 0x56e4
5420 #define A_PCIE_FLR_VF2_STATUS 0x56e8
5421 #define A_PCIE_FLR_VF3_STATUS 0x56ec
5422 #define A_PCIE_STAT 0x56f4
5423 
5424 #define S_PM_STATUS    24
5425 #define M_PM_STATUS    0xffU
5426 #define V_PM_STATUS(x) ((x) << S_PM_STATUS)
5427 #define G_PM_STATUS(x) (((x) >> S_PM_STATUS) & M_PM_STATUS)
5428 
5429 #define S_PM_CURRENTSTATE    20
5430 #define M_PM_CURRENTSTATE    0x7U
5431 #define V_PM_CURRENTSTATE(x) ((x) << S_PM_CURRENTSTATE)
5432 #define G_PM_CURRENTSTATE(x) (((x) >> S_PM_CURRENTSTATE) & M_PM_CURRENTSTATE)
5433 
5434 #define S_LTSSMENABLE    12
5435 #define V_LTSSMENABLE(x) ((x) << S_LTSSMENABLE)
5436 #define F_LTSSMENABLE    V_LTSSMENABLE(1U)
5437 
5438 #define S_STATECFGINITF    4
5439 #define M_STATECFGINITF    0x7fU
5440 #define V_STATECFGINITF(x) ((x) << S_STATECFGINITF)
5441 #define G_STATECFGINITF(x) (((x) >> S_STATECFGINITF) & M_STATECFGINITF)
5442 
5443 #define S_STATECFGINIT    0
5444 #define M_STATECFGINIT    0xfU
5445 #define V_STATECFGINIT(x) ((x) << S_STATECFGINIT)
5446 #define G_STATECFGINIT(x) (((x) >> S_STATECFGINIT) & M_STATECFGINIT)
5447 
5448 #define S_LTSSMENABLE_PCIE    12
5449 #define V_LTSSMENABLE_PCIE(x) ((x) << S_LTSSMENABLE_PCIE)
5450 #define F_LTSSMENABLE_PCIE    V_LTSSMENABLE_PCIE(1U)
5451 
5452 #define S_STATECFGINITF_PCIE    4
5453 #define M_STATECFGINITF_PCIE    0xffU
5454 #define V_STATECFGINITF_PCIE(x) ((x) << S_STATECFGINITF_PCIE)
5455 #define G_STATECFGINITF_PCIE(x) (((x) >> S_STATECFGINITF_PCIE) & M_STATECFGINITF_PCIE)
5456 
5457 #define S_STATECFGINIT_PCIE    0
5458 #define M_STATECFGINIT_PCIE    0xfU
5459 #define V_STATECFGINIT_PCIE(x) ((x) << S_STATECFGINIT_PCIE)
5460 #define G_STATECFGINIT_PCIE(x) (((x) >> S_STATECFGINIT_PCIE) & M_STATECFGINIT_PCIE)
5461 
5462 #define A_PCIE_CRS 0x56f8
5463 
5464 #define S_CRS_ENABLE    0
5465 #define V_CRS_ENABLE(x) ((x) << S_CRS_ENABLE)
5466 #define F_CRS_ENABLE    V_CRS_ENABLE(1U)
5467 
5468 #define A_PCIE_LTSSM 0x56fc
5469 
5470 #define S_LTSSM_ENABLE    0
5471 #define V_LTSSM_ENABLE(x) ((x) << S_LTSSM_ENABLE)
5472 #define F_LTSSM_ENABLE    V_LTSSM_ENABLE(1U)
5473 
5474 #define S_LTSSM_STALL_DISABLE    1
5475 #define V_LTSSM_STALL_DISABLE(x) ((x) << S_LTSSM_STALL_DISABLE)
5476 #define F_LTSSM_STALL_DISABLE    V_LTSSM_STALL_DISABLE(1U)
5477 
5478 #define A_PCIE_CORE_ACK_LATENCY_TIMER_REPLAY_TIMER 0x5700
5479 
5480 #define S_REPLAY_TIME_LIMIT    16
5481 #define M_REPLAY_TIME_LIMIT    0xffffU
5482 #define V_REPLAY_TIME_LIMIT(x) ((x) << S_REPLAY_TIME_LIMIT)
5483 #define G_REPLAY_TIME_LIMIT(x) (((x) >> S_REPLAY_TIME_LIMIT) & M_REPLAY_TIME_LIMIT)
5484 
5485 #define S_ACK_LATENCY_TIMER_LIMIT    0
5486 #define M_ACK_LATENCY_TIMER_LIMIT    0xffffU
5487 #define V_ACK_LATENCY_TIMER_LIMIT(x) ((x) << S_ACK_LATENCY_TIMER_LIMIT)
5488 #define G_ACK_LATENCY_TIMER_LIMIT(x) (((x) >> S_ACK_LATENCY_TIMER_LIMIT) & M_ACK_LATENCY_TIMER_LIMIT)
5489 
5490 #define A_PCIE_CORE_VENDOR_SPECIFIC_DLLP 0x5704
5491 #define A_PCIE_CORE_PORT_FORCE_LINK 0x5708
5492 
5493 #define S_LOW_POWER_ENTRANCE_COUNT    24
5494 #define M_LOW_POWER_ENTRANCE_COUNT    0xffU
5495 #define V_LOW_POWER_ENTRANCE_COUNT(x) ((x) << S_LOW_POWER_ENTRANCE_COUNT)
5496 #define G_LOW_POWER_ENTRANCE_COUNT(x) (((x) >> S_LOW_POWER_ENTRANCE_COUNT) & M_LOW_POWER_ENTRANCE_COUNT)
5497 
5498 #define S_LINK_STATE    16
5499 #define M_LINK_STATE    0x3fU
5500 #define V_LINK_STATE(x) ((x) << S_LINK_STATE)
5501 #define G_LINK_STATE(x) (((x) >> S_LINK_STATE) & M_LINK_STATE)
5502 
5503 #define S_FORCE_LINK    15
5504 #define V_FORCE_LINK(x) ((x) << S_FORCE_LINK)
5505 #define F_FORCE_LINK    V_FORCE_LINK(1U)
5506 
5507 #define S_LINK_NUMBER    0
5508 #define M_LINK_NUMBER    0xffU
5509 #define V_LINK_NUMBER(x) ((x) << S_LINK_NUMBER)
5510 #define G_LINK_NUMBER(x) (((x) >> S_LINK_NUMBER) & M_LINK_NUMBER)
5511 
5512 #define A_PCIE_CORE_ACK_FREQUENCY_L0L1_ASPM_CONTROL 0x570c
5513 
5514 #define S_ENTER_ASPM_L1_WO_L0S    30
5515 #define V_ENTER_ASPM_L1_WO_L0S(x) ((x) << S_ENTER_ASPM_L1_WO_L0S)
5516 #define F_ENTER_ASPM_L1_WO_L0S    V_ENTER_ASPM_L1_WO_L0S(1U)
5517 
5518 #define S_L1_ENTRANCE_LATENCY    27
5519 #define M_L1_ENTRANCE_LATENCY    0x7U
5520 #define V_L1_ENTRANCE_LATENCY(x) ((x) << S_L1_ENTRANCE_LATENCY)
5521 #define G_L1_ENTRANCE_LATENCY(x) (((x) >> S_L1_ENTRANCE_LATENCY) & M_L1_ENTRANCE_LATENCY)
5522 
5523 #define S_L0S_ENTRANCE_LATENCY    24
5524 #define M_L0S_ENTRANCE_LATENCY    0x7U
5525 #define V_L0S_ENTRANCE_LATENCY(x) ((x) << S_L0S_ENTRANCE_LATENCY)
5526 #define G_L0S_ENTRANCE_LATENCY(x) (((x) >> S_L0S_ENTRANCE_LATENCY) & M_L0S_ENTRANCE_LATENCY)
5527 
5528 #define S_COMMON_CLOCK_N_FTS    16
5529 #define M_COMMON_CLOCK_N_FTS    0xffU
5530 #define V_COMMON_CLOCK_N_FTS(x) ((x) << S_COMMON_CLOCK_N_FTS)
5531 #define G_COMMON_CLOCK_N_FTS(x) (((x) >> S_COMMON_CLOCK_N_FTS) & M_COMMON_CLOCK_N_FTS)
5532 
5533 #define S_N_FTS    8
5534 #define M_N_FTS    0xffU
5535 #define V_N_FTS(x) ((x) << S_N_FTS)
5536 #define G_N_FTS(x) (((x) >> S_N_FTS) & M_N_FTS)
5537 
5538 #define S_ACK_FREQUENCY    0
5539 #define M_ACK_FREQUENCY    0xffU
5540 #define V_ACK_FREQUENCY(x) ((x) << S_ACK_FREQUENCY)
5541 #define G_ACK_FREQUENCY(x) (((x) >> S_ACK_FREQUENCY) & M_ACK_FREQUENCY)
5542 
5543 #define A_PCIE_CORE_PORT_LINK_CONTROL 0x5710
5544 
5545 #define S_CROSSLINK_ACTIVE    23
5546 #define V_CROSSLINK_ACTIVE(x) ((x) << S_CROSSLINK_ACTIVE)
5547 #define F_CROSSLINK_ACTIVE    V_CROSSLINK_ACTIVE(1U)
5548 
5549 #define S_CROSSLINK_ENABLE    22
5550 #define V_CROSSLINK_ENABLE(x) ((x) << S_CROSSLINK_ENABLE)
5551 #define F_CROSSLINK_ENABLE    V_CROSSLINK_ENABLE(1U)
5552 
5553 #define S_LINK_MODE_ENABLE    16
5554 #define M_LINK_MODE_ENABLE    0x3fU
5555 #define V_LINK_MODE_ENABLE(x) ((x) << S_LINK_MODE_ENABLE)
5556 #define G_LINK_MODE_ENABLE(x) (((x) >> S_LINK_MODE_ENABLE) & M_LINK_MODE_ENABLE)
5557 
5558 #define S_FAST_LINK_MODE    7
5559 #define V_FAST_LINK_MODE(x) ((x) << S_FAST_LINK_MODE)
5560 #define F_FAST_LINK_MODE    V_FAST_LINK_MODE(1U)
5561 
5562 #define S_DLL_LINK_ENABLE    5
5563 #define V_DLL_LINK_ENABLE(x) ((x) << S_DLL_LINK_ENABLE)
5564 #define F_DLL_LINK_ENABLE    V_DLL_LINK_ENABLE(1U)
5565 
5566 #define S_RESET_ASSERT    3
5567 #define V_RESET_ASSERT(x) ((x) << S_RESET_ASSERT)
5568 #define F_RESET_ASSERT    V_RESET_ASSERT(1U)
5569 
5570 #define S_LOOPBACK_ENABLE    2
5571 #define V_LOOPBACK_ENABLE(x) ((x) << S_LOOPBACK_ENABLE)
5572 #define F_LOOPBACK_ENABLE    V_LOOPBACK_ENABLE(1U)
5573 
5574 #define S_SCRAMBLE_DISABLE    1
5575 #define V_SCRAMBLE_DISABLE(x) ((x) << S_SCRAMBLE_DISABLE)
5576 #define F_SCRAMBLE_DISABLE    V_SCRAMBLE_DISABLE(1U)
5577 
5578 #define S_VENDOR_SPECIFIC_DLLP_REQUEST    0
5579 #define V_VENDOR_SPECIFIC_DLLP_REQUEST(x) ((x) << S_VENDOR_SPECIFIC_DLLP_REQUEST)
5580 #define F_VENDOR_SPECIFIC_DLLP_REQUEST    V_VENDOR_SPECIFIC_DLLP_REQUEST(1U)
5581 
5582 #define A_PCIE_CORE_LANE_SKEW 0x5714
5583 
5584 #define S_DISABLE_DESKEW    31
5585 #define V_DISABLE_DESKEW(x) ((x) << S_DISABLE_DESKEW)
5586 #define F_DISABLE_DESKEW    V_DISABLE_DESKEW(1U)
5587 
5588 #define S_ACK_NAK_DISABLE    25
5589 #define V_ACK_NAK_DISABLE(x) ((x) << S_ACK_NAK_DISABLE)
5590 #define F_ACK_NAK_DISABLE    V_ACK_NAK_DISABLE(1U)
5591 
5592 #define S_FLOW_CONTROL_DISABLE    24
5593 #define V_FLOW_CONTROL_DISABLE(x) ((x) << S_FLOW_CONTROL_DISABLE)
5594 #define F_FLOW_CONTROL_DISABLE    V_FLOW_CONTROL_DISABLE(1U)
5595 
5596 #define S_INSERT_TXSKEW    0
5597 #define M_INSERT_TXSKEW    0xffffffU
5598 #define V_INSERT_TXSKEW(x) ((x) << S_INSERT_TXSKEW)
5599 #define G_INSERT_TXSKEW(x) (((x) >> S_INSERT_TXSKEW) & M_INSERT_TXSKEW)
5600 
5601 #define A_PCIE_CORE_SYMBOL_NUMBER 0x5718
5602 
5603 #define S_FLOW_CONTROL_TIMER_MODIFIER    24
5604 #define M_FLOW_CONTROL_TIMER_MODIFIER    0x1fU
5605 #define V_FLOW_CONTROL_TIMER_MODIFIER(x) ((x) << S_FLOW_CONTROL_TIMER_MODIFIER)
5606 #define G_FLOW_CONTROL_TIMER_MODIFIER(x) (((x) >> S_FLOW_CONTROL_TIMER_MODIFIER) & M_FLOW_CONTROL_TIMER_MODIFIER)
5607 
5608 #define S_ACK_NAK_TIMER_MODIFIER    19
5609 #define M_ACK_NAK_TIMER_MODIFIER    0x1fU
5610 #define V_ACK_NAK_TIMER_MODIFIER(x) ((x) << S_ACK_NAK_TIMER_MODIFIER)
5611 #define G_ACK_NAK_TIMER_MODIFIER(x) (((x) >> S_ACK_NAK_TIMER_MODIFIER) & M_ACK_NAK_TIMER_MODIFIER)
5612 
5613 #define S_REPLAY_TIMER_MODIFIER    14
5614 #define M_REPLAY_TIMER_MODIFIER    0x1fU
5615 #define V_REPLAY_TIMER_MODIFIER(x) ((x) << S_REPLAY_TIMER_MODIFIER)
5616 #define G_REPLAY_TIMER_MODIFIER(x) (((x) >> S_REPLAY_TIMER_MODIFIER) & M_REPLAY_TIMER_MODIFIER)
5617 
5618 #define S_MAXFUNC    0
5619 #define M_MAXFUNC    0x7U
5620 #define V_MAXFUNC(x) ((x) << S_MAXFUNC)
5621 #define G_MAXFUNC(x) (((x) >> S_MAXFUNC) & M_MAXFUNC)
5622 
5623 #define A_PCIE_CORE_SYMBOL_TIMER_FILTER_MASK1 0x571c
5624 
5625 #define S_MASK_RADM_FILTER    16
5626 #define M_MASK_RADM_FILTER    0xffffU
5627 #define V_MASK_RADM_FILTER(x) ((x) << S_MASK_RADM_FILTER)
5628 #define G_MASK_RADM_FILTER(x) (((x) >> S_MASK_RADM_FILTER) & M_MASK_RADM_FILTER)
5629 
5630 #define S_DISABLE_FC_WATCHDOG    15
5631 #define V_DISABLE_FC_WATCHDOG(x) ((x) << S_DISABLE_FC_WATCHDOG)
5632 #define F_DISABLE_FC_WATCHDOG    V_DISABLE_FC_WATCHDOG(1U)
5633 
5634 #define S_SKP_INTERVAL    0
5635 #define M_SKP_INTERVAL    0x7ffU
5636 #define V_SKP_INTERVAL(x) ((x) << S_SKP_INTERVAL)
5637 #define G_SKP_INTERVAL(x) (((x) >> S_SKP_INTERVAL) & M_SKP_INTERVAL)
5638 
5639 #define A_PCIE_CORE_FILTER_MASK2 0x5720
5640 #define A_PCIE_CORE_DEBUG_0 0x5728
5641 #define A_PCIE_CORE_DEBUG_1 0x572c
5642 #define A_PCIE_CORE_TRANSMIT_POSTED_FC_CREDIT_STATUS 0x5730
5643 
5644 #define S_TXPH_FC    12
5645 #define M_TXPH_FC    0xffU
5646 #define V_TXPH_FC(x) ((x) << S_TXPH_FC)
5647 #define G_TXPH_FC(x) (((x) >> S_TXPH_FC) & M_TXPH_FC)
5648 
5649 #define S_TXPD_FC    0
5650 #define M_TXPD_FC    0xfffU
5651 #define V_TXPD_FC(x) ((x) << S_TXPD_FC)
5652 #define G_TXPD_FC(x) (((x) >> S_TXPD_FC) & M_TXPD_FC)
5653 
5654 #define A_PCIE_CORE_TRANSMIT_NONPOSTED_FC_CREDIT_STATUS 0x5734
5655 
5656 #define S_TXNPH_FC    12
5657 #define M_TXNPH_FC    0xffU
5658 #define V_TXNPH_FC(x) ((x) << S_TXNPH_FC)
5659 #define G_TXNPH_FC(x) (((x) >> S_TXNPH_FC) & M_TXNPH_FC)
5660 
5661 #define S_TXNPD_FC    0
5662 #define M_TXNPD_FC    0xfffU
5663 #define V_TXNPD_FC(x) ((x) << S_TXNPD_FC)
5664 #define G_TXNPD_FC(x) (((x) >> S_TXNPD_FC) & M_TXNPD_FC)
5665 
5666 #define A_PCIE_CORE_TRANSMIT_COMPLETION_FC_CREDIT_STATUS 0x5738
5667 
5668 #define S_TXCPLH_FC    12
5669 #define M_TXCPLH_FC    0xffU
5670 #define V_TXCPLH_FC(x) ((x) << S_TXCPLH_FC)
5671 #define G_TXCPLH_FC(x) (((x) >> S_TXCPLH_FC) & M_TXCPLH_FC)
5672 
5673 #define S_TXCPLD_FC    0
5674 #define M_TXCPLD_FC    0xfffU
5675 #define V_TXCPLD_FC(x) ((x) << S_TXCPLD_FC)
5676 #define G_TXCPLD_FC(x) (((x) >> S_TXCPLD_FC) & M_TXCPLD_FC)
5677 
5678 #define A_PCIE_CORE_QUEUE_STATUS 0x573c
5679 
5680 #define S_RXQUEUE_NOT_EMPTY    2
5681 #define V_RXQUEUE_NOT_EMPTY(x) ((x) << S_RXQUEUE_NOT_EMPTY)
5682 #define F_RXQUEUE_NOT_EMPTY    V_RXQUEUE_NOT_EMPTY(1U)
5683 
5684 #define S_TXRETRYBUF_NOT_EMPTY    1
5685 #define V_TXRETRYBUF_NOT_EMPTY(x) ((x) << S_TXRETRYBUF_NOT_EMPTY)
5686 #define F_TXRETRYBUF_NOT_EMPTY    V_TXRETRYBUF_NOT_EMPTY(1U)
5687 
5688 #define S_RXTLP_FC_NOT_RETURNED    0
5689 #define V_RXTLP_FC_NOT_RETURNED(x) ((x) << S_RXTLP_FC_NOT_RETURNED)
5690 #define F_RXTLP_FC_NOT_RETURNED    V_RXTLP_FC_NOT_RETURNED(1U)
5691 
5692 #define A_PCIE_CORE_VC_TRANSMIT_ARBITRATION_1 0x5740
5693 
5694 #define S_VC3_WRR    24
5695 #define M_VC3_WRR    0xffU
5696 #define V_VC3_WRR(x) ((x) << S_VC3_WRR)
5697 #define G_VC3_WRR(x) (((x) >> S_VC3_WRR) & M_VC3_WRR)
5698 
5699 #define S_VC2_WRR    16
5700 #define M_VC2_WRR    0xffU
5701 #define V_VC2_WRR(x) ((x) << S_VC2_WRR)
5702 #define G_VC2_WRR(x) (((x) >> S_VC2_WRR) & M_VC2_WRR)
5703 
5704 #define S_VC1_WRR    8
5705 #define M_VC1_WRR    0xffU
5706 #define V_VC1_WRR(x) ((x) << S_VC1_WRR)
5707 #define G_VC1_WRR(x) (((x) >> S_VC1_WRR) & M_VC1_WRR)
5708 
5709 #define S_VC0_WRR    0
5710 #define M_VC0_WRR    0xffU
5711 #define V_VC0_WRR(x) ((x) << S_VC0_WRR)
5712 #define G_VC0_WRR(x) (((x) >> S_VC0_WRR) & M_VC0_WRR)
5713 
5714 #define A_PCIE_CORE_VC_TRANSMIT_ARBITRATION_2 0x5744
5715 
5716 #define S_VC7_WRR    24
5717 #define M_VC7_WRR    0xffU
5718 #define V_VC7_WRR(x) ((x) << S_VC7_WRR)
5719 #define G_VC7_WRR(x) (((x) >> S_VC7_WRR) & M_VC7_WRR)
5720 
5721 #define S_VC6_WRR    16
5722 #define M_VC6_WRR    0xffU
5723 #define V_VC6_WRR(x) ((x) << S_VC6_WRR)
5724 #define G_VC6_WRR(x) (((x) >> S_VC6_WRR) & M_VC6_WRR)
5725 
5726 #define S_VC5_WRR    8
5727 #define M_VC5_WRR    0xffU
5728 #define V_VC5_WRR(x) ((x) << S_VC5_WRR)
5729 #define G_VC5_WRR(x) (((x) >> S_VC5_WRR) & M_VC5_WRR)
5730 
5731 #define S_VC4_WRR    0
5732 #define M_VC4_WRR    0xffU
5733 #define V_VC4_WRR(x) ((x) << S_VC4_WRR)
5734 #define G_VC4_WRR(x) (((x) >> S_VC4_WRR) & M_VC4_WRR)
5735 
5736 #define A_PCIE_CORE_VC0_POSTED_RECEIVE_QUEUE_CONTROL 0x5748
5737 
5738 #define S_VC0_RX_ORDERING    31
5739 #define V_VC0_RX_ORDERING(x) ((x) << S_VC0_RX_ORDERING)
5740 #define F_VC0_RX_ORDERING    V_VC0_RX_ORDERING(1U)
5741 
5742 #define S_VC0_TLP_ORDERING    30
5743 #define V_VC0_TLP_ORDERING(x) ((x) << S_VC0_TLP_ORDERING)
5744 #define F_VC0_TLP_ORDERING    V_VC0_TLP_ORDERING(1U)
5745 
5746 #define S_VC0_PTLP_QUEUE_MODE    21
5747 #define M_VC0_PTLP_QUEUE_MODE    0x7U
5748 #define V_VC0_PTLP_QUEUE_MODE(x) ((x) << S_VC0_PTLP_QUEUE_MODE)
5749 #define G_VC0_PTLP_QUEUE_MODE(x) (((x) >> S_VC0_PTLP_QUEUE_MODE) & M_VC0_PTLP_QUEUE_MODE)
5750 
5751 #define S_VC0_PH_CREDITS    12
5752 #define M_VC0_PH_CREDITS    0xffU
5753 #define V_VC0_PH_CREDITS(x) ((x) << S_VC0_PH_CREDITS)
5754 #define G_VC0_PH_CREDITS(x) (((x) >> S_VC0_PH_CREDITS) & M_VC0_PH_CREDITS)
5755 
5756 #define S_VC0_PD_CREDITS    0
5757 #define M_VC0_PD_CREDITS    0xfffU
5758 #define V_VC0_PD_CREDITS(x) ((x) << S_VC0_PD_CREDITS)
5759 #define G_VC0_PD_CREDITS(x) (((x) >> S_VC0_PD_CREDITS) & M_VC0_PD_CREDITS)
5760 
5761 #define A_PCIE_CORE_VC0_NONPOSTED_RECEIVE_QUEUE_CONTROL 0x574c
5762 
5763 #define S_VC0_NPTLP_QUEUE_MODE    21
5764 #define M_VC0_NPTLP_QUEUE_MODE    0x7U
5765 #define V_VC0_NPTLP_QUEUE_MODE(x) ((x) << S_VC0_NPTLP_QUEUE_MODE)
5766 #define G_VC0_NPTLP_QUEUE_MODE(x) (((x) >> S_VC0_NPTLP_QUEUE_MODE) & M_VC0_NPTLP_QUEUE_MODE)
5767 
5768 #define S_VC0_NPH_CREDITS    12
5769 #define M_VC0_NPH_CREDITS    0xffU
5770 #define V_VC0_NPH_CREDITS(x) ((x) << S_VC0_NPH_CREDITS)
5771 #define G_VC0_NPH_CREDITS(x) (((x) >> S_VC0_NPH_CREDITS) & M_VC0_NPH_CREDITS)
5772 
5773 #define S_VC0_NPD_CREDITS    0
5774 #define M_VC0_NPD_CREDITS    0xfffU
5775 #define V_VC0_NPD_CREDITS(x) ((x) << S_VC0_NPD_CREDITS)
5776 #define G_VC0_NPD_CREDITS(x) (((x) >> S_VC0_NPD_CREDITS) & M_VC0_NPD_CREDITS)
5777 
5778 #define A_PCIE_CORE_VC0_COMPLETION_RECEIVE_QUEUE_CONTROL 0x5750
5779 
5780 #define S_VC0_CPLTLP_QUEUE_MODE    21
5781 #define M_VC0_CPLTLP_QUEUE_MODE    0x7U
5782 #define V_VC0_CPLTLP_QUEUE_MODE(x) ((x) << S_VC0_CPLTLP_QUEUE_MODE)
5783 #define G_VC0_CPLTLP_QUEUE_MODE(x) (((x) >> S_VC0_CPLTLP_QUEUE_MODE) & M_VC0_CPLTLP_QUEUE_MODE)
5784 
5785 #define S_VC0_CPLH_CREDITS    12
5786 #define M_VC0_CPLH_CREDITS    0xffU
5787 #define V_VC0_CPLH_CREDITS(x) ((x) << S_VC0_CPLH_CREDITS)
5788 #define G_VC0_CPLH_CREDITS(x) (((x) >> S_VC0_CPLH_CREDITS) & M_VC0_CPLH_CREDITS)
5789 
5790 #define S_VC0_CPLD_CREDITS    0
5791 #define M_VC0_CPLD_CREDITS    0xfffU
5792 #define V_VC0_CPLD_CREDITS(x) ((x) << S_VC0_CPLD_CREDITS)
5793 #define G_VC0_CPLD_CREDITS(x) (((x) >> S_VC0_CPLD_CREDITS) & M_VC0_CPLD_CREDITS)
5794 
5795 #define A_PCIE_CORE_VC1_POSTED_RECEIVE_QUEUE_CONTROL 0x5754
5796 
5797 #define S_VC1_TLP_ORDERING    30
5798 #define V_VC1_TLP_ORDERING(x) ((x) << S_VC1_TLP_ORDERING)
5799 #define F_VC1_TLP_ORDERING    V_VC1_TLP_ORDERING(1U)
5800 
5801 #define S_VC1_PTLP_QUEUE_MODE    21
5802 #define M_VC1_PTLP_QUEUE_MODE    0x7U
5803 #define V_VC1_PTLP_QUEUE_MODE(x) ((x) << S_VC1_PTLP_QUEUE_MODE)
5804 #define G_VC1_PTLP_QUEUE_MODE(x) (((x) >> S_VC1_PTLP_QUEUE_MODE) & M_VC1_PTLP_QUEUE_MODE)
5805 
5806 #define S_VC1_PH_CREDITS    12
5807 #define M_VC1_PH_CREDITS    0xffU
5808 #define V_VC1_PH_CREDITS(x) ((x) << S_VC1_PH_CREDITS)
5809 #define G_VC1_PH_CREDITS(x) (((x) >> S_VC1_PH_CREDITS) & M_VC1_PH_CREDITS)
5810 
5811 #define S_VC1_PD_CREDITS    0
5812 #define M_VC1_PD_CREDITS    0xfffU
5813 #define V_VC1_PD_CREDITS(x) ((x) << S_VC1_PD_CREDITS)
5814 #define G_VC1_PD_CREDITS(x) (((x) >> S_VC1_PD_CREDITS) & M_VC1_PD_CREDITS)
5815 
5816 #define A_PCIE_CORE_VC1_NONPOSTED_RECEIVE_QUEUE_CONTROL 0x5758
5817 
5818 #define S_VC1_NPTLP_QUEUE_MODE    21
5819 #define M_VC1_NPTLP_QUEUE_MODE    0x7U
5820 #define V_VC1_NPTLP_QUEUE_MODE(x) ((x) << S_VC1_NPTLP_QUEUE_MODE)
5821 #define G_VC1_NPTLP_QUEUE_MODE(x) (((x) >> S_VC1_NPTLP_QUEUE_MODE) & M_VC1_NPTLP_QUEUE_MODE)
5822 
5823 #define S_VC1_NPH_CREDITS    12
5824 #define M_VC1_NPH_CREDITS    0xffU
5825 #define V_VC1_NPH_CREDITS(x) ((x) << S_VC1_NPH_CREDITS)
5826 #define G_VC1_NPH_CREDITS(x) (((x) >> S_VC1_NPH_CREDITS) & M_VC1_NPH_CREDITS)
5827 
5828 #define S_VC1_NPD_CREDITS    0
5829 #define M_VC1_NPD_CREDITS    0xfffU
5830 #define V_VC1_NPD_CREDITS(x) ((x) << S_VC1_NPD_CREDITS)
5831 #define G_VC1_NPD_CREDITS(x) (((x) >> S_VC1_NPD_CREDITS) & M_VC1_NPD_CREDITS)
5832 
5833 #define A_PCIE_CORE_VC1_COMPLETION_RECEIVE_QUEUE_CONTROL 0x575c
5834 
5835 #define S_VC1_CPLTLP_QUEUE_MODE    21
5836 #define M_VC1_CPLTLP_QUEUE_MODE    0x7U
5837 #define V_VC1_CPLTLP_QUEUE_MODE(x) ((x) << S_VC1_CPLTLP_QUEUE_MODE)
5838 #define G_VC1_CPLTLP_QUEUE_MODE(x) (((x) >> S_VC1_CPLTLP_QUEUE_MODE) & M_VC1_CPLTLP_QUEUE_MODE)
5839 
5840 #define S_VC1_CPLH_CREDITS    12
5841 #define M_VC1_CPLH_CREDITS    0xffU
5842 #define V_VC1_CPLH_CREDITS(x) ((x) << S_VC1_CPLH_CREDITS)
5843 #define G_VC1_CPLH_CREDITS(x) (((x) >> S_VC1_CPLH_CREDITS) & M_VC1_CPLH_CREDITS)
5844 
5845 #define S_VC1_CPLD_CREDITS    0
5846 #define M_VC1_CPLD_CREDITS    0xfffU
5847 #define V_VC1_CPLD_CREDITS(x) ((x) << S_VC1_CPLD_CREDITS)
5848 #define G_VC1_CPLD_CREDITS(x) (((x) >> S_VC1_CPLD_CREDITS) & M_VC1_CPLD_CREDITS)
5849 
5850 #define A_PCIE_CORE_LINK_WIDTH_SPEED_CHANGE 0x580c
5851 
5852 #define S_SEL_DEEMPHASIS    20
5853 #define V_SEL_DEEMPHASIS(x) ((x) << S_SEL_DEEMPHASIS)
5854 #define F_SEL_DEEMPHASIS    V_SEL_DEEMPHASIS(1U)
5855 
5856 #define S_TXCMPLRCV    19
5857 #define V_TXCMPLRCV(x) ((x) << S_TXCMPLRCV)
5858 #define F_TXCMPLRCV    V_TXCMPLRCV(1U)
5859 
5860 #define S_PHYTXSWING    18
5861 #define V_PHYTXSWING(x) ((x) << S_PHYTXSWING)
5862 #define F_PHYTXSWING    V_PHYTXSWING(1U)
5863 
5864 #define S_DIRSPDCHANGE    17
5865 #define V_DIRSPDCHANGE(x) ((x) << S_DIRSPDCHANGE)
5866 #define F_DIRSPDCHANGE    V_DIRSPDCHANGE(1U)
5867 
5868 #define S_NUM_LANES    8
5869 #define M_NUM_LANES    0x1ffU
5870 #define V_NUM_LANES(x) ((x) << S_NUM_LANES)
5871 #define G_NUM_LANES(x) (((x) >> S_NUM_LANES) & M_NUM_LANES)
5872 
5873 #define S_NFTS_GEN2_3    0
5874 #define M_NFTS_GEN2_3    0xffU
5875 #define V_NFTS_GEN2_3(x) ((x) << S_NFTS_GEN2_3)
5876 #define G_NFTS_GEN2_3(x) (((x) >> S_NFTS_GEN2_3) & M_NFTS_GEN2_3)
5877 
5878 #define S_AUTO_LANE_FLIP_CTRL_EN    16
5879 #define V_AUTO_LANE_FLIP_CTRL_EN(x) ((x) << S_AUTO_LANE_FLIP_CTRL_EN)
5880 #define F_AUTO_LANE_FLIP_CTRL_EN    V_AUTO_LANE_FLIP_CTRL_EN(1U)
5881 
5882 #define S_T6_NUM_LANES    8
5883 #define M_T6_NUM_LANES    0x1fU
5884 #define V_T6_NUM_LANES(x) ((x) << S_T6_NUM_LANES)
5885 #define G_T6_NUM_LANES(x) (((x) >> S_T6_NUM_LANES) & M_T6_NUM_LANES)
5886 
5887 #define A_PCIE_CORE_PHY_STATUS 0x5810
5888 #define A_PCIE_CORE_PHY_CONTROL 0x5814
5889 #define A_PCIE_CORE_GEN3_CONTROL 0x5890
5890 
5891 #define S_DC_BALANCE_DISABLE    18
5892 #define V_DC_BALANCE_DISABLE(x) ((x) << S_DC_BALANCE_DISABLE)
5893 #define F_DC_BALANCE_DISABLE    V_DC_BALANCE_DISABLE(1U)
5894 
5895 #define S_DLLP_DELAY_DISABLE    17
5896 #define V_DLLP_DELAY_DISABLE(x) ((x) << S_DLLP_DELAY_DISABLE)
5897 #define F_DLLP_DELAY_DISABLE    V_DLLP_DELAY_DISABLE(1U)
5898 
5899 #define S_EQL_DISABLE    16
5900 #define V_EQL_DISABLE(x) ((x) << S_EQL_DISABLE)
5901 #define F_EQL_DISABLE    V_EQL_DISABLE(1U)
5902 
5903 #define S_EQL_REDO_DISABLE    11
5904 #define V_EQL_REDO_DISABLE(x) ((x) << S_EQL_REDO_DISABLE)
5905 #define F_EQL_REDO_DISABLE    V_EQL_REDO_DISABLE(1U)
5906 
5907 #define S_EQL_EIEOS_CNTRST_DISABLE    10
5908 #define V_EQL_EIEOS_CNTRST_DISABLE(x) ((x) << S_EQL_EIEOS_CNTRST_DISABLE)
5909 #define F_EQL_EIEOS_CNTRST_DISABLE    V_EQL_EIEOS_CNTRST_DISABLE(1U)
5910 
5911 #define S_EQL_PH2_PH3_DISABLE    9
5912 #define V_EQL_PH2_PH3_DISABLE(x) ((x) << S_EQL_PH2_PH3_DISABLE)
5913 #define F_EQL_PH2_PH3_DISABLE    V_EQL_PH2_PH3_DISABLE(1U)
5914 
5915 #define S_DISABLE_SCRAMBLER    8
5916 #define V_DISABLE_SCRAMBLER(x) ((x) << S_DISABLE_SCRAMBLER)
5917 #define F_DISABLE_SCRAMBLER    V_DISABLE_SCRAMBLER(1U)
5918 
5919 #define A_PCIE_CORE_GEN3_EQ_FS_LF 0x5894
5920 
5921 #define S_FULL_SWING    6
5922 #define M_FULL_SWING    0x3fU
5923 #define V_FULL_SWING(x) ((x) << S_FULL_SWING)
5924 #define G_FULL_SWING(x) (((x) >> S_FULL_SWING) & M_FULL_SWING)
5925 
5926 #define S_LOW_FREQUENCY    0
5927 #define M_LOW_FREQUENCY    0x3fU
5928 #define V_LOW_FREQUENCY(x) ((x) << S_LOW_FREQUENCY)
5929 #define G_LOW_FREQUENCY(x) (((x) >> S_LOW_FREQUENCY) & M_LOW_FREQUENCY)
5930 
5931 #define A_PCIE_CORE_GEN3_EQ_PRESET_COEFF 0x5898
5932 
5933 #define S_POSTCURSOR    12
5934 #define M_POSTCURSOR    0x3fU
5935 #define V_POSTCURSOR(x) ((x) << S_POSTCURSOR)
5936 #define G_POSTCURSOR(x) (((x) >> S_POSTCURSOR) & M_POSTCURSOR)
5937 
5938 #define S_CURSOR    6
5939 #define M_CURSOR    0x3fU
5940 #define V_CURSOR(x) ((x) << S_CURSOR)
5941 #define G_CURSOR(x) (((x) >> S_CURSOR) & M_CURSOR)
5942 
5943 #define S_PRECURSOR    0
5944 #define M_PRECURSOR    0x3fU
5945 #define V_PRECURSOR(x) ((x) << S_PRECURSOR)
5946 #define G_PRECURSOR(x) (((x) >> S_PRECURSOR) & M_PRECURSOR)
5947 
5948 #define A_PCIE_CORE_GEN3_EQ_PRESET_INDEX 0x589c
5949 
5950 #define S_INDEX    0
5951 #define M_INDEX    0xfU
5952 #define V_INDEX(x) ((x) << S_INDEX)
5953 #define G_INDEX(x) (((x) >> S_INDEX) & M_INDEX)
5954 
5955 #define A_PCIE_CORE_GEN3_EQ_STATUS 0x58a4
5956 
5957 #define S_LEGALITY_STATUS    0
5958 #define V_LEGALITY_STATUS(x) ((x) << S_LEGALITY_STATUS)
5959 #define F_LEGALITY_STATUS    V_LEGALITY_STATUS(1U)
5960 
5961 #define A_PCIE_CORE_GEN3_EQ_CONTROL 0x58a8
5962 
5963 #define S_INCLUDE_INITIAL_FOM    24
5964 #define V_INCLUDE_INITIAL_FOM(x) ((x) << S_INCLUDE_INITIAL_FOM)
5965 #define F_INCLUDE_INITIAL_FOM    V_INCLUDE_INITIAL_FOM(1U)
5966 
5967 #define S_PRESET_REQUEST_VECTOR    8
5968 #define M_PRESET_REQUEST_VECTOR    0xffffU
5969 #define V_PRESET_REQUEST_VECTOR(x) ((x) << S_PRESET_REQUEST_VECTOR)
5970 #define G_PRESET_REQUEST_VECTOR(x) (((x) >> S_PRESET_REQUEST_VECTOR) & M_PRESET_REQUEST_VECTOR)
5971 
5972 #define S_PHASE23_2MS_TIMEOUT_DISABLE    5
5973 #define V_PHASE23_2MS_TIMEOUT_DISABLE(x) ((x) << S_PHASE23_2MS_TIMEOUT_DISABLE)
5974 #define F_PHASE23_2MS_TIMEOUT_DISABLE    V_PHASE23_2MS_TIMEOUT_DISABLE(1U)
5975 
5976 #define S_AFTER24MS    4
5977 #define V_AFTER24MS(x) ((x) << S_AFTER24MS)
5978 #define F_AFTER24MS    V_AFTER24MS(1U)
5979 
5980 #define S_FEEDBACK_MODE    0
5981 #define M_FEEDBACK_MODE    0xfU
5982 #define V_FEEDBACK_MODE(x) ((x) << S_FEEDBACK_MODE)
5983 #define G_FEEDBACK_MODE(x) (((x) >> S_FEEDBACK_MODE) & M_FEEDBACK_MODE)
5984 
5985 #define A_PCIE_CORE_GEN3_EQ_DIRCHANGE_FEEDBACK 0x58ac
5986 
5987 #define S_WINAPERTURE_CPLUS1    14
5988 #define M_WINAPERTURE_CPLUS1    0xfU
5989 #define V_WINAPERTURE_CPLUS1(x) ((x) << S_WINAPERTURE_CPLUS1)
5990 #define G_WINAPERTURE_CPLUS1(x) (((x) >> S_WINAPERTURE_CPLUS1) & M_WINAPERTURE_CPLUS1)
5991 
5992 #define S_WINAPERTURE_CMINS1    10
5993 #define M_WINAPERTURE_CMINS1    0xfU
5994 #define V_WINAPERTURE_CMINS1(x) ((x) << S_WINAPERTURE_CMINS1)
5995 #define G_WINAPERTURE_CMINS1(x) (((x) >> S_WINAPERTURE_CMINS1) & M_WINAPERTURE_CMINS1)
5996 
5997 #define S_CONVERGENCE_WINDEPTH    5
5998 #define M_CONVERGENCE_WINDEPTH    0x1fU
5999 #define V_CONVERGENCE_WINDEPTH(x) ((x) << S_CONVERGENCE_WINDEPTH)
6000 #define G_CONVERGENCE_WINDEPTH(x) (((x) >> S_CONVERGENCE_WINDEPTH) & M_CONVERGENCE_WINDEPTH)
6001 
6002 #define S_EQMASTERPHASE_MINTIME    0
6003 #define M_EQMASTERPHASE_MINTIME    0x1fU
6004 #define V_EQMASTERPHASE_MINTIME(x) ((x) << S_EQMASTERPHASE_MINTIME)
6005 #define G_EQMASTERPHASE_MINTIME(x) (((x) >> S_EQMASTERPHASE_MINTIME) & M_EQMASTERPHASE_MINTIME)
6006 
6007 #define A_PCIE_CORE_PIPE_CONTROL 0x58b8
6008 
6009 #define S_PIPE_LOOPBACK_EN    0
6010 #define V_PIPE_LOOPBACK_EN(x) ((x) << S_PIPE_LOOPBACK_EN)
6011 #define F_PIPE_LOOPBACK_EN    V_PIPE_LOOPBACK_EN(1U)
6012 
6013 #define S_T6_PIPE_LOOPBACK_EN    31
6014 #define V_T6_PIPE_LOOPBACK_EN(x) ((x) << S_T6_PIPE_LOOPBACK_EN)
6015 #define F_T6_PIPE_LOOPBACK_EN    V_T6_PIPE_LOOPBACK_EN(1U)
6016 
6017 #define A_PCIE_CORE_DBI_RO_WE 0x58bc
6018 
6019 #define S_READONLY_WRITEEN    0
6020 #define V_READONLY_WRITEEN(x) ((x) << S_READONLY_WRITEEN)
6021 #define F_READONLY_WRITEEN    V_READONLY_WRITEEN(1U)
6022 
6023 #define A_PCIE_CORE_UTL_SYSTEM_BUS_CONTROL 0x5900
6024 
6025 #define S_SMTD    27
6026 #define V_SMTD(x) ((x) << S_SMTD)
6027 #define F_SMTD    V_SMTD(1U)
6028 
6029 #define S_SSTD    26
6030 #define V_SSTD(x) ((x) << S_SSTD)
6031 #define F_SSTD    V_SSTD(1U)
6032 
6033 #define S_SWD0    23
6034 #define V_SWD0(x) ((x) << S_SWD0)
6035 #define F_SWD0    V_SWD0(1U)
6036 
6037 #define S_SWD1    22
6038 #define V_SWD1(x) ((x) << S_SWD1)
6039 #define F_SWD1    V_SWD1(1U)
6040 
6041 #define S_SWD2    21
6042 #define V_SWD2(x) ((x) << S_SWD2)
6043 #define F_SWD2    V_SWD2(1U)
6044 
6045 #define S_SWD3    20
6046 #define V_SWD3(x) ((x) << S_SWD3)
6047 #define F_SWD3    V_SWD3(1U)
6048 
6049 #define S_SWD4    19
6050 #define V_SWD4(x) ((x) << S_SWD4)
6051 #define F_SWD4    V_SWD4(1U)
6052 
6053 #define S_SWD5    18
6054 #define V_SWD5(x) ((x) << S_SWD5)
6055 #define F_SWD5    V_SWD5(1U)
6056 
6057 #define S_SWD6    17
6058 #define V_SWD6(x) ((x) << S_SWD6)
6059 #define F_SWD6    V_SWD6(1U)
6060 
6061 #define S_SWD7    16
6062 #define V_SWD7(x) ((x) << S_SWD7)
6063 #define F_SWD7    V_SWD7(1U)
6064 
6065 #define S_SWD8    15
6066 #define V_SWD8(x) ((x) << S_SWD8)
6067 #define F_SWD8    V_SWD8(1U)
6068 
6069 #define S_SRD0    13
6070 #define V_SRD0(x) ((x) << S_SRD0)
6071 #define F_SRD0    V_SRD0(1U)
6072 
6073 #define S_SRD1    12
6074 #define V_SRD1(x) ((x) << S_SRD1)
6075 #define F_SRD1    V_SRD1(1U)
6076 
6077 #define S_SRD2    11
6078 #define V_SRD2(x) ((x) << S_SRD2)
6079 #define F_SRD2    V_SRD2(1U)
6080 
6081 #define S_SRD3    10
6082 #define V_SRD3(x) ((x) << S_SRD3)
6083 #define F_SRD3    V_SRD3(1U)
6084 
6085 #define S_SRD4    9
6086 #define V_SRD4(x) ((x) << S_SRD4)
6087 #define F_SRD4    V_SRD4(1U)
6088 
6089 #define S_SRD5    8
6090 #define V_SRD5(x) ((x) << S_SRD5)
6091 #define F_SRD5    V_SRD5(1U)
6092 
6093 #define S_SRD6    7
6094 #define V_SRD6(x) ((x) << S_SRD6)
6095 #define F_SRD6    V_SRD6(1U)
6096 
6097 #define S_SRD7    6
6098 #define V_SRD7(x) ((x) << S_SRD7)
6099 #define F_SRD7    V_SRD7(1U)
6100 
6101 #define S_SRD8    5
6102 #define V_SRD8(x) ((x) << S_SRD8)
6103 #define F_SRD8    V_SRD8(1U)
6104 
6105 #define S_CRRE    3
6106 #define V_CRRE(x) ((x) << S_CRRE)
6107 #define F_CRRE    V_CRRE(1U)
6108 
6109 #define S_CRMC    0
6110 #define M_CRMC    0x7U
6111 #define V_CRMC(x) ((x) << S_CRMC)
6112 #define G_CRMC(x) (((x) >> S_CRMC) & M_CRMC)
6113 
6114 #define A_PCIE_CORE_UTL_STATUS 0x5904
6115 
6116 #define S_USBP    31
6117 #define V_USBP(x) ((x) << S_USBP)
6118 #define F_USBP    V_USBP(1U)
6119 
6120 #define S_UPEP    30
6121 #define V_UPEP(x) ((x) << S_UPEP)
6122 #define F_UPEP    V_UPEP(1U)
6123 
6124 #define S_RCEP    29
6125 #define V_RCEP(x) ((x) << S_RCEP)
6126 #define F_RCEP    V_RCEP(1U)
6127 
6128 #define S_EPEP    28
6129 #define V_EPEP(x) ((x) << S_EPEP)
6130 #define F_EPEP    V_EPEP(1U)
6131 
6132 #define S_USBS    27
6133 #define V_USBS(x) ((x) << S_USBS)
6134 #define F_USBS    V_USBS(1U)
6135 
6136 #define S_UPES    26
6137 #define V_UPES(x) ((x) << S_UPES)
6138 #define F_UPES    V_UPES(1U)
6139 
6140 #define S_RCES    25
6141 #define V_RCES(x) ((x) << S_RCES)
6142 #define F_RCES    V_RCES(1U)
6143 
6144 #define S_EPES    24
6145 #define V_EPES(x) ((x) << S_EPES)
6146 #define F_EPES    V_EPES(1U)
6147 
6148 #define A_PCIE_CORE_UTL_SYSTEM_BUS_AGENT_STATUS 0x5908
6149 
6150 #define S_RNPP    31
6151 #define V_RNPP(x) ((x) << S_RNPP)
6152 #define F_RNPP    V_RNPP(1U)
6153 
6154 #define S_RPCP    29
6155 #define V_RPCP(x) ((x) << S_RPCP)
6156 #define F_RPCP    V_RPCP(1U)
6157 
6158 #define S_RCIP    27
6159 #define V_RCIP(x) ((x) << S_RCIP)
6160 #define F_RCIP    V_RCIP(1U)
6161 
6162 #define S_RCCP    26
6163 #define V_RCCP(x) ((x) << S_RCCP)
6164 #define F_RCCP    V_RCCP(1U)
6165 
6166 #define S_RFTP    23
6167 #define V_RFTP(x) ((x) << S_RFTP)
6168 #define F_RFTP    V_RFTP(1U)
6169 
6170 #define S_PTRP    20
6171 #define V_PTRP(x) ((x) << S_PTRP)
6172 #define F_PTRP    V_PTRP(1U)
6173 
6174 #define A_PCIE_CORE_UTL_SYSTEM_BUS_AGENT_ERROR_SEVERITY 0x590c
6175 
6176 #define S_RNPS    31
6177 #define V_RNPS(x) ((x) << S_RNPS)
6178 #define F_RNPS    V_RNPS(1U)
6179 
6180 #define S_RPCS    29
6181 #define V_RPCS(x) ((x) << S_RPCS)
6182 #define F_RPCS    V_RPCS(1U)
6183 
6184 #define S_RCIS    27
6185 #define V_RCIS(x) ((x) << S_RCIS)
6186 #define F_RCIS    V_RCIS(1U)
6187 
6188 #define S_RCCS    26
6189 #define V_RCCS(x) ((x) << S_RCCS)
6190 #define F_RCCS    V_RCCS(1U)
6191 
6192 #define S_RFTS    23
6193 #define V_RFTS(x) ((x) << S_RFTS)
6194 #define F_RFTS    V_RFTS(1U)
6195 
6196 #define A_PCIE_CORE_UTL_SYSTEM_BUS_AGENT_INTERRUPT_ENABLE 0x5910
6197 
6198 #define S_RNPI    31
6199 #define V_RNPI(x) ((x) << S_RNPI)
6200 #define F_RNPI    V_RNPI(1U)
6201 
6202 #define S_RPCI    29
6203 #define V_RPCI(x) ((x) << S_RPCI)
6204 #define F_RPCI    V_RPCI(1U)
6205 
6206 #define S_RCII    27
6207 #define V_RCII(x) ((x) << S_RCII)
6208 #define F_RCII    V_RCII(1U)
6209 
6210 #define S_RCCI    26
6211 #define V_RCCI(x) ((x) << S_RCCI)
6212 #define F_RCCI    V_RCCI(1U)
6213 
6214 #define S_RFTI    23
6215 #define V_RFTI(x) ((x) << S_RFTI)
6216 #define F_RFTI    V_RFTI(1U)
6217 
6218 #define A_PCIE_CORE_SYSTEM_BUS_BURST_SIZE_CONFIGURATION 0x5920
6219 
6220 #define S_SBRS    28
6221 #define M_SBRS    0x7U
6222 #define V_SBRS(x) ((x) << S_SBRS)
6223 #define G_SBRS(x) (((x) >> S_SBRS) & M_SBRS)
6224 
6225 #define S_OTWS    20
6226 #define M_OTWS    0x7U
6227 #define V_OTWS(x) ((x) << S_OTWS)
6228 #define G_OTWS(x) (((x) >> S_OTWS) & M_OTWS)
6229 
6230 #define A_PCIE_CORE_REVISION_ID 0x5924
6231 
6232 #define S_RVID    20
6233 #define M_RVID    0xfffU
6234 #define V_RVID(x) ((x) << S_RVID)
6235 #define G_RVID(x) (((x) >> S_RVID) & M_RVID)
6236 
6237 #define S_BRVN    12
6238 #define M_BRVN    0xffU
6239 #define V_BRVN(x) ((x) << S_BRVN)
6240 #define G_BRVN(x) (((x) >> S_BRVN) & M_BRVN)
6241 
6242 #define A_PCIE_T5_DMA_CFG 0x5940
6243 
6244 #define S_T5_DMA_MAXREQCNT    20
6245 #define M_T5_DMA_MAXREQCNT    0xffU
6246 #define V_T5_DMA_MAXREQCNT(x) ((x) << S_T5_DMA_MAXREQCNT)
6247 #define G_T5_DMA_MAXREQCNT(x) (((x) >> S_T5_DMA_MAXREQCNT) & M_T5_DMA_MAXREQCNT)
6248 
6249 #define S_T5_DMA_MAXRDREQSIZE    17
6250 #define M_T5_DMA_MAXRDREQSIZE    0x7U
6251 #define V_T5_DMA_MAXRDREQSIZE(x) ((x) << S_T5_DMA_MAXRDREQSIZE)
6252 #define G_T5_DMA_MAXRDREQSIZE(x) (((x) >> S_T5_DMA_MAXRDREQSIZE) & M_T5_DMA_MAXRDREQSIZE)
6253 
6254 #define S_T5_DMA_MAXRSPCNT    8
6255 #define M_T5_DMA_MAXRSPCNT    0x1ffU
6256 #define V_T5_DMA_MAXRSPCNT(x) ((x) << S_T5_DMA_MAXRSPCNT)
6257 #define G_T5_DMA_MAXRSPCNT(x) (((x) >> S_T5_DMA_MAXRSPCNT) & M_T5_DMA_MAXRSPCNT)
6258 
6259 #define S_SEQCHKDIS    7
6260 #define V_SEQCHKDIS(x) ((x) << S_SEQCHKDIS)
6261 #define F_SEQCHKDIS    V_SEQCHKDIS(1U)
6262 
6263 #define S_MINTAG    0
6264 #define M_MINTAG    0x7fU
6265 #define V_MINTAG(x) ((x) << S_MINTAG)
6266 #define G_MINTAG(x) (((x) >> S_MINTAG) & M_MINTAG)
6267 
6268 #define S_T6_T5_DMA_MAXREQCNT    20
6269 #define M_T6_T5_DMA_MAXREQCNT    0x7fU
6270 #define V_T6_T5_DMA_MAXREQCNT(x) ((x) << S_T6_T5_DMA_MAXREQCNT)
6271 #define G_T6_T5_DMA_MAXREQCNT(x) (((x) >> S_T6_T5_DMA_MAXREQCNT) & M_T6_T5_DMA_MAXREQCNT)
6272 
6273 #define S_T6_T5_DMA_MAXRSPCNT    9
6274 #define M_T6_T5_DMA_MAXRSPCNT    0xffU
6275 #define V_T6_T5_DMA_MAXRSPCNT(x) ((x) << S_T6_T5_DMA_MAXRSPCNT)
6276 #define G_T6_T5_DMA_MAXRSPCNT(x) (((x) >> S_T6_T5_DMA_MAXRSPCNT) & M_T6_T5_DMA_MAXRSPCNT)
6277 
6278 #define S_T6_SEQCHKDIS    8
6279 #define V_T6_SEQCHKDIS(x) ((x) << S_T6_SEQCHKDIS)
6280 #define F_T6_SEQCHKDIS    V_T6_SEQCHKDIS(1U)
6281 
6282 #define S_T6_MINTAG    0
6283 #define M_T6_MINTAG    0xffU
6284 #define V_T6_MINTAG(x) ((x) << S_T6_MINTAG)
6285 #define G_T6_MINTAG(x) (((x) >> S_T6_MINTAG) & M_T6_MINTAG)
6286 
6287 #define A_PCIE_T5_DMA_STAT 0x5944
6288 
6289 #define S_DMA_RESPCNT    20
6290 #define M_DMA_RESPCNT    0xfffU
6291 #define V_DMA_RESPCNT(x) ((x) << S_DMA_RESPCNT)
6292 #define G_DMA_RESPCNT(x) (((x) >> S_DMA_RESPCNT) & M_DMA_RESPCNT)
6293 
6294 #define S_DMA_RDREQCNT    12
6295 #define M_DMA_RDREQCNT    0xffU
6296 #define V_DMA_RDREQCNT(x) ((x) << S_DMA_RDREQCNT)
6297 #define G_DMA_RDREQCNT(x) (((x) >> S_DMA_RDREQCNT) & M_DMA_RDREQCNT)
6298 
6299 #define S_DMA_WRREQCNT    0
6300 #define M_DMA_WRREQCNT    0x7ffU
6301 #define V_DMA_WRREQCNT(x) ((x) << S_DMA_WRREQCNT)
6302 #define G_DMA_WRREQCNT(x) (((x) >> S_DMA_WRREQCNT) & M_DMA_WRREQCNT)
6303 
6304 #define S_T6_DMA_RESPCNT    20
6305 #define M_T6_DMA_RESPCNT    0x3ffU
6306 #define V_T6_DMA_RESPCNT(x) ((x) << S_T6_DMA_RESPCNT)
6307 #define G_T6_DMA_RESPCNT(x) (((x) >> S_T6_DMA_RESPCNT) & M_T6_DMA_RESPCNT)
6308 
6309 #define S_T6_DMA_RDREQCNT    12
6310 #define M_T6_DMA_RDREQCNT    0x3fU
6311 #define V_T6_DMA_RDREQCNT(x) ((x) << S_T6_DMA_RDREQCNT)
6312 #define G_T6_DMA_RDREQCNT(x) (((x) >> S_T6_DMA_RDREQCNT) & M_T6_DMA_RDREQCNT)
6313 
6314 #define S_T6_DMA_WRREQCNT    0
6315 #define M_T6_DMA_WRREQCNT    0x1ffU
6316 #define V_T6_DMA_WRREQCNT(x) ((x) << S_T6_DMA_WRREQCNT)
6317 #define G_T6_DMA_WRREQCNT(x) (((x) >> S_T6_DMA_WRREQCNT) & M_T6_DMA_WRREQCNT)
6318 
6319 #define A_PCIE_T5_DMA_STAT2 0x5948
6320 
6321 #define S_COOKIECNT    24
6322 #define M_COOKIECNT    0xfU
6323 #define V_COOKIECNT(x) ((x) << S_COOKIECNT)
6324 #define G_COOKIECNT(x) (((x) >> S_COOKIECNT) & M_COOKIECNT)
6325 
6326 #define S_RDSEQNUMUPDCNT    20
6327 #define M_RDSEQNUMUPDCNT    0xfU
6328 #define V_RDSEQNUMUPDCNT(x) ((x) << S_RDSEQNUMUPDCNT)
6329 #define G_RDSEQNUMUPDCNT(x) (((x) >> S_RDSEQNUMUPDCNT) & M_RDSEQNUMUPDCNT)
6330 
6331 #define S_SIREQCNT    16
6332 #define M_SIREQCNT    0xfU
6333 #define V_SIREQCNT(x) ((x) << S_SIREQCNT)
6334 #define G_SIREQCNT(x) (((x) >> S_SIREQCNT) & M_SIREQCNT)
6335 
6336 #define S_WREOPMATCHSOP    12
6337 #define V_WREOPMATCHSOP(x) ((x) << S_WREOPMATCHSOP)
6338 #define F_WREOPMATCHSOP    V_WREOPMATCHSOP(1U)
6339 
6340 #define S_WRSOPCNT    8
6341 #define M_WRSOPCNT    0xfU
6342 #define V_WRSOPCNT(x) ((x) << S_WRSOPCNT)
6343 #define G_WRSOPCNT(x) (((x) >> S_WRSOPCNT) & M_WRSOPCNT)
6344 
6345 #define S_RDSOPCNT    0
6346 #define M_RDSOPCNT    0xffU
6347 #define V_RDSOPCNT(x) ((x) << S_RDSOPCNT)
6348 #define G_RDSOPCNT(x) (((x) >> S_RDSOPCNT) & M_RDSOPCNT)
6349 
6350 #define A_PCIE_T5_DMA_STAT3 0x594c
6351 
6352 #define S_ATMREQSOPCNT    24
6353 #define M_ATMREQSOPCNT    0xffU
6354 #define V_ATMREQSOPCNT(x) ((x) << S_ATMREQSOPCNT)
6355 #define G_ATMREQSOPCNT(x) (((x) >> S_ATMREQSOPCNT) & M_ATMREQSOPCNT)
6356 
6357 #define S_ATMEOPMATCHSOP    17
6358 #define V_ATMEOPMATCHSOP(x) ((x) << S_ATMEOPMATCHSOP)
6359 #define F_ATMEOPMATCHSOP    V_ATMEOPMATCHSOP(1U)
6360 
6361 #define S_RSPEOPMATCHSOP    16
6362 #define V_RSPEOPMATCHSOP(x) ((x) << S_RSPEOPMATCHSOP)
6363 #define F_RSPEOPMATCHSOP    V_RSPEOPMATCHSOP(1U)
6364 
6365 #define S_RSPERRCNT    8
6366 #define M_RSPERRCNT    0xffU
6367 #define V_RSPERRCNT(x) ((x) << S_RSPERRCNT)
6368 #define G_RSPERRCNT(x) (((x) >> S_RSPERRCNT) & M_RSPERRCNT)
6369 
6370 #define S_RSPSOPCNT    0
6371 #define M_RSPSOPCNT    0xffU
6372 #define V_RSPSOPCNT(x) ((x) << S_RSPSOPCNT)
6373 #define G_RSPSOPCNT(x) (((x) >> S_RSPSOPCNT) & M_RSPSOPCNT)
6374 
6375 #define A_PCIE_CORE_OUTBOUND_POSTED_HEADER_BUFFER_ALLOCATION 0x5960
6376 
6377 #define S_OP0H    24
6378 #define M_OP0H    0xfU
6379 #define V_OP0H(x) ((x) << S_OP0H)
6380 #define G_OP0H(x) (((x) >> S_OP0H) & M_OP0H)
6381 
6382 #define S_OP1H    16
6383 #define M_OP1H    0xfU
6384 #define V_OP1H(x) ((x) << S_OP1H)
6385 #define G_OP1H(x) (((x) >> S_OP1H) & M_OP1H)
6386 
6387 #define S_OP2H    8
6388 #define M_OP2H    0xfU
6389 #define V_OP2H(x) ((x) << S_OP2H)
6390 #define G_OP2H(x) (((x) >> S_OP2H) & M_OP2H)
6391 
6392 #define S_OP3H    0
6393 #define M_OP3H    0xfU
6394 #define V_OP3H(x) ((x) << S_OP3H)
6395 #define G_OP3H(x) (((x) >> S_OP3H) & M_OP3H)
6396 
6397 #define A_PCIE_CORE_OUTBOUND_POSTED_DATA_BUFFER_ALLOCATION 0x5968
6398 
6399 #define S_OP0D    24
6400 #define M_OP0D    0x7fU
6401 #define V_OP0D(x) ((x) << S_OP0D)
6402 #define G_OP0D(x) (((x) >> S_OP0D) & M_OP0D)
6403 
6404 #define S_OP1D    16
6405 #define M_OP1D    0x7fU
6406 #define V_OP1D(x) ((x) << S_OP1D)
6407 #define G_OP1D(x) (((x) >> S_OP1D) & M_OP1D)
6408 
6409 #define S_OP2D    8
6410 #define M_OP2D    0x7fU
6411 #define V_OP2D(x) ((x) << S_OP2D)
6412 #define G_OP2D(x) (((x) >> S_OP2D) & M_OP2D)
6413 
6414 #define S_OP3D    0
6415 #define M_OP3D    0x7fU
6416 #define V_OP3D(x) ((x) << S_OP3D)
6417 #define G_OP3D(x) (((x) >> S_OP3D) & M_OP3D)
6418 
6419 #define A_PCIE_CORE_INBOUND_POSTED_HEADER_BUFFER_ALLOCATION 0x5970
6420 
6421 #define S_IP0H    24
6422 #define M_IP0H    0x3fU
6423 #define V_IP0H(x) ((x) << S_IP0H)
6424 #define G_IP0H(x) (((x) >> S_IP0H) & M_IP0H)
6425 
6426 #define S_IP1H    16
6427 #define M_IP1H    0x3fU
6428 #define V_IP1H(x) ((x) << S_IP1H)
6429 #define G_IP1H(x) (((x) >> S_IP1H) & M_IP1H)
6430 
6431 #define S_IP2H    8
6432 #define M_IP2H    0x3fU
6433 #define V_IP2H(x) ((x) << S_IP2H)
6434 #define G_IP2H(x) (((x) >> S_IP2H) & M_IP2H)
6435 
6436 #define S_IP3H    0
6437 #define M_IP3H    0x3fU
6438 #define V_IP3H(x) ((x) << S_IP3H)
6439 #define G_IP3H(x) (((x) >> S_IP3H) & M_IP3H)
6440 
6441 #define A_PCIE_CORE_INBOUND_POSTED_DATA_BUFFER_ALLOCATION 0x5978
6442 
6443 #define S_IP0D    24
6444 #define M_IP0D    0xffU
6445 #define V_IP0D(x) ((x) << S_IP0D)
6446 #define G_IP0D(x) (((x) >> S_IP0D) & M_IP0D)
6447 
6448 #define S_IP1D    16
6449 #define M_IP1D    0xffU
6450 #define V_IP1D(x) ((x) << S_IP1D)
6451 #define G_IP1D(x) (((x) >> S_IP1D) & M_IP1D)
6452 
6453 #define S_IP2D    8
6454 #define M_IP2D    0xffU
6455 #define V_IP2D(x) ((x) << S_IP2D)
6456 #define G_IP2D(x) (((x) >> S_IP2D) & M_IP2D)
6457 
6458 #define S_IP3D    0
6459 #define M_IP3D    0xffU
6460 #define V_IP3D(x) ((x) << S_IP3D)
6461 #define G_IP3D(x) (((x) >> S_IP3D) & M_IP3D)
6462 
6463 #define A_PCIE_CORE_OUTBOUND_NON_POSTED_BUFFER_ALLOCATION 0x5980
6464 
6465 #define S_ON0H    24
6466 #define M_ON0H    0xfU
6467 #define V_ON0H(x) ((x) << S_ON0H)
6468 #define G_ON0H(x) (((x) >> S_ON0H) & M_ON0H)
6469 
6470 #define S_ON1H    16
6471 #define M_ON1H    0xfU
6472 #define V_ON1H(x) ((x) << S_ON1H)
6473 #define G_ON1H(x) (((x) >> S_ON1H) & M_ON1H)
6474 
6475 #define S_ON2H    8
6476 #define M_ON2H    0xfU
6477 #define V_ON2H(x) ((x) << S_ON2H)
6478 #define G_ON2H(x) (((x) >> S_ON2H) & M_ON2H)
6479 
6480 #define S_ON3H    0
6481 #define M_ON3H    0xfU
6482 #define V_ON3H(x) ((x) << S_ON3H)
6483 #define G_ON3H(x) (((x) >> S_ON3H) & M_ON3H)
6484 
6485 #define A_PCIE_T5_CMD_CFG 0x5980
6486 
6487 #define S_T5_CMD_MAXRDREQSIZE    17
6488 #define M_T5_CMD_MAXRDREQSIZE    0x7U
6489 #define V_T5_CMD_MAXRDREQSIZE(x) ((x) << S_T5_CMD_MAXRDREQSIZE)
6490 #define G_T5_CMD_MAXRDREQSIZE(x) (((x) >> S_T5_CMD_MAXRDREQSIZE) & M_T5_CMD_MAXRDREQSIZE)
6491 
6492 #define S_T5_CMD_MAXRSPCNT    8
6493 #define M_T5_CMD_MAXRSPCNT    0xffU
6494 #define V_T5_CMD_MAXRSPCNT(x) ((x) << S_T5_CMD_MAXRSPCNT)
6495 #define G_T5_CMD_MAXRSPCNT(x) (((x) >> S_T5_CMD_MAXRSPCNT) & M_T5_CMD_MAXRSPCNT)
6496 
6497 #define S_USECMDPOOL    7
6498 #define V_USECMDPOOL(x) ((x) << S_USECMDPOOL)
6499 #define F_USECMDPOOL    V_USECMDPOOL(1U)
6500 
6501 #define S_T6_T5_CMD_MAXRSPCNT    9
6502 #define M_T6_T5_CMD_MAXRSPCNT    0x3fU
6503 #define V_T6_T5_CMD_MAXRSPCNT(x) ((x) << S_T6_T5_CMD_MAXRSPCNT)
6504 #define G_T6_T5_CMD_MAXRSPCNT(x) (((x) >> S_T6_T5_CMD_MAXRSPCNT) & M_T6_T5_CMD_MAXRSPCNT)
6505 
6506 #define S_T6_USECMDPOOL    8
6507 #define V_T6_USECMDPOOL(x) ((x) << S_T6_USECMDPOOL)
6508 #define F_T6_USECMDPOOL    V_T6_USECMDPOOL(1U)
6509 
6510 #define S_T6_MINTAG    0
6511 #define M_T6_MINTAG    0xffU
6512 #define V_T6_MINTAG(x) ((x) << S_T6_MINTAG)
6513 #define G_T6_MINTAG(x) (((x) >> S_T6_MINTAG) & M_T6_MINTAG)
6514 
6515 #define A_PCIE_T5_CMD_STAT 0x5984
6516 
6517 #define S_T5_STAT_RSPCNT    20
6518 #define M_T5_STAT_RSPCNT    0x7ffU
6519 #define V_T5_STAT_RSPCNT(x) ((x) << S_T5_STAT_RSPCNT)
6520 #define G_T5_STAT_RSPCNT(x) (((x) >> S_T5_STAT_RSPCNT) & M_T5_STAT_RSPCNT)
6521 
6522 #define S_RDREQCNT    12
6523 #define M_RDREQCNT    0x1fU
6524 #define V_RDREQCNT(x) ((x) << S_RDREQCNT)
6525 #define G_RDREQCNT(x) (((x) >> S_RDREQCNT) & M_RDREQCNT)
6526 
6527 #define S_T6_T5_STAT_RSPCNT    20
6528 #define M_T6_T5_STAT_RSPCNT    0xffU
6529 #define V_T6_T5_STAT_RSPCNT(x) ((x) << S_T6_T5_STAT_RSPCNT)
6530 #define G_T6_T5_STAT_RSPCNT(x) (((x) >> S_T6_T5_STAT_RSPCNT) & M_T6_T5_STAT_RSPCNT)
6531 
6532 #define S_T6_RDREQCNT    12
6533 #define M_T6_RDREQCNT    0xfU
6534 #define V_T6_RDREQCNT(x) ((x) << S_T6_RDREQCNT)
6535 #define G_T6_RDREQCNT(x) (((x) >> S_T6_RDREQCNT) & M_T6_RDREQCNT)
6536 
6537 #define A_PCIE_CORE_INBOUND_NON_POSTED_REQUESTS_BUFFER_ALLOCATION 0x5988
6538 
6539 #define S_IN0H    24
6540 #define M_IN0H    0x3fU
6541 #define V_IN0H(x) ((x) << S_IN0H)
6542 #define G_IN0H(x) (((x) >> S_IN0H) & M_IN0H)
6543 
6544 #define S_IN1H    16
6545 #define M_IN1H    0x3fU
6546 #define V_IN1H(x) ((x) << S_IN1H)
6547 #define G_IN1H(x) (((x) >> S_IN1H) & M_IN1H)
6548 
6549 #define S_IN2H    8
6550 #define M_IN2H    0x3fU
6551 #define V_IN2H(x) ((x) << S_IN2H)
6552 #define G_IN2H(x) (((x) >> S_IN2H) & M_IN2H)
6553 
6554 #define S_IN3H    0
6555 #define M_IN3H    0x3fU
6556 #define V_IN3H(x) ((x) << S_IN3H)
6557 #define G_IN3H(x) (((x) >> S_IN3H) & M_IN3H)
6558 
6559 #define A_PCIE_T5_CMD_STAT2 0x5988
6560 #define A_PCIE_T5_CMD_STAT3 0x598c
6561 #define A_PCIE_CORE_PCI_EXPRESS_TAGS_ALLOCATION 0x5990
6562 
6563 #define S_OC0T    24
6564 #define M_OC0T    0xffU
6565 #define V_OC0T(x) ((x) << S_OC0T)
6566 #define G_OC0T(x) (((x) >> S_OC0T) & M_OC0T)
6567 
6568 #define S_OC1T    16
6569 #define M_OC1T    0xffU
6570 #define V_OC1T(x) ((x) << S_OC1T)
6571 #define G_OC1T(x) (((x) >> S_OC1T) & M_OC1T)
6572 
6573 #define S_OC2T    8
6574 #define M_OC2T    0xffU
6575 #define V_OC2T(x) ((x) << S_OC2T)
6576 #define G_OC2T(x) (((x) >> S_OC2T) & M_OC2T)
6577 
6578 #define S_OC3T    0
6579 #define M_OC3T    0xffU
6580 #define V_OC3T(x) ((x) << S_OC3T)
6581 #define G_OC3T(x) (((x) >> S_OC3T) & M_OC3T)
6582 
6583 #define A_PCIE_CORE_GBIF_READ_TAGS_ALLOCATION 0x5998
6584 
6585 #define S_IC0T    24
6586 #define M_IC0T    0x3fU
6587 #define V_IC0T(x) ((x) << S_IC0T)
6588 #define G_IC0T(x) (((x) >> S_IC0T) & M_IC0T)
6589 
6590 #define S_IC1T    16
6591 #define M_IC1T    0x3fU
6592 #define V_IC1T(x) ((x) << S_IC1T)
6593 #define G_IC1T(x) (((x) >> S_IC1T) & M_IC1T)
6594 
6595 #define S_IC2T    8
6596 #define M_IC2T    0x3fU
6597 #define V_IC2T(x) ((x) << S_IC2T)
6598 #define G_IC2T(x) (((x) >> S_IC2T) & M_IC2T)
6599 
6600 #define S_IC3T    0
6601 #define M_IC3T    0x3fU
6602 #define V_IC3T(x) ((x) << S_IC3T)
6603 #define G_IC3T(x) (((x) >> S_IC3T) & M_IC3T)
6604 
6605 #define A_PCIE_CORE_UTL_PCI_EXPRESS_PORT_CONTROL 0x59a0
6606 
6607 #define S_VRB0    31
6608 #define V_VRB0(x) ((x) << S_VRB0)
6609 #define F_VRB0    V_VRB0(1U)
6610 
6611 #define S_VRB1    30
6612 #define V_VRB1(x) ((x) << S_VRB1)
6613 #define F_VRB1    V_VRB1(1U)
6614 
6615 #define S_VRB2    29
6616 #define V_VRB2(x) ((x) << S_VRB2)
6617 #define F_VRB2    V_VRB2(1U)
6618 
6619 #define S_VRB3    28
6620 #define V_VRB3(x) ((x) << S_VRB3)
6621 #define F_VRB3    V_VRB3(1U)
6622 
6623 #define S_PSFE    26
6624 #define V_PSFE(x) ((x) << S_PSFE)
6625 #define F_PSFE    V_PSFE(1U)
6626 
6627 #define S_RVDE    25
6628 #define V_RVDE(x) ((x) << S_RVDE)
6629 #define F_RVDE    V_RVDE(1U)
6630 
6631 #define S_TXE0    23
6632 #define V_TXE0(x) ((x) << S_TXE0)
6633 #define F_TXE0    V_TXE0(1U)
6634 
6635 #define S_TXE1    22
6636 #define V_TXE1(x) ((x) << S_TXE1)
6637 #define F_TXE1    V_TXE1(1U)
6638 
6639 #define S_TXE2    21
6640 #define V_TXE2(x) ((x) << S_TXE2)
6641 #define F_TXE2    V_TXE2(1U)
6642 
6643 #define S_TXE3    20
6644 #define V_TXE3(x) ((x) << S_TXE3)
6645 #define F_TXE3    V_TXE3(1U)
6646 
6647 #define S_RPAM    13
6648 #define V_RPAM(x) ((x) << S_RPAM)
6649 #define F_RPAM    V_RPAM(1U)
6650 
6651 #define S_RTOS    4
6652 #define M_RTOS    0xfU
6653 #define V_RTOS(x) ((x) << S_RTOS)
6654 #define G_RTOS(x) (((x) >> S_RTOS) & M_RTOS)
6655 
6656 #define A_PCIE_CORE_UTL_PCI_EXPRESS_PORT_STATUS 0x59a4
6657 
6658 #define S_TPCP    30
6659 #define V_TPCP(x) ((x) << S_TPCP)
6660 #define F_TPCP    V_TPCP(1U)
6661 
6662 #define S_TNPP    29
6663 #define V_TNPP(x) ((x) << S_TNPP)
6664 #define F_TNPP    V_TNPP(1U)
6665 
6666 #define S_TFTP    28
6667 #define V_TFTP(x) ((x) << S_TFTP)
6668 #define F_TFTP    V_TFTP(1U)
6669 
6670 #define S_TCAP    27
6671 #define V_TCAP(x) ((x) << S_TCAP)
6672 #define F_TCAP    V_TCAP(1U)
6673 
6674 #define S_TCIP    26
6675 #define V_TCIP(x) ((x) << S_TCIP)
6676 #define F_TCIP    V_TCIP(1U)
6677 
6678 #define S_RCAP    25
6679 #define V_RCAP(x) ((x) << S_RCAP)
6680 #define F_RCAP    V_RCAP(1U)
6681 
6682 #define S_PLUP    23
6683 #define V_PLUP(x) ((x) << S_PLUP)
6684 #define F_PLUP    V_PLUP(1U)
6685 
6686 #define S_PLDN    22
6687 #define V_PLDN(x) ((x) << S_PLDN)
6688 #define F_PLDN    V_PLDN(1U)
6689 
6690 #define S_OTDD    21
6691 #define V_OTDD(x) ((x) << S_OTDD)
6692 #define F_OTDD    V_OTDD(1U)
6693 
6694 #define S_GTRP    20
6695 #define V_GTRP(x) ((x) << S_GTRP)
6696 #define F_GTRP    V_GTRP(1U)
6697 
6698 #define S_RDPE    18
6699 #define V_RDPE(x) ((x) << S_RDPE)
6700 #define F_RDPE    V_RDPE(1U)
6701 
6702 #define S_TDCE    17
6703 #define V_TDCE(x) ((x) << S_TDCE)
6704 #define F_TDCE    V_TDCE(1U)
6705 
6706 #define S_TDUE    16
6707 #define V_TDUE(x) ((x) << S_TDUE)
6708 #define F_TDUE    V_TDUE(1U)
6709 
6710 #define A_PCIE_CORE_UTL_PCI_EXPRESS_PORT_ERROR_SEVERITY 0x59a8
6711 
6712 #define S_TPCS    30
6713 #define V_TPCS(x) ((x) << S_TPCS)
6714 #define F_TPCS    V_TPCS(1U)
6715 
6716 #define S_TNPS    29
6717 #define V_TNPS(x) ((x) << S_TNPS)
6718 #define F_TNPS    V_TNPS(1U)
6719 
6720 #define S_TFTS    28
6721 #define V_TFTS(x) ((x) << S_TFTS)
6722 #define F_TFTS    V_TFTS(1U)
6723 
6724 #define S_TCAS    27
6725 #define V_TCAS(x) ((x) << S_TCAS)
6726 #define F_TCAS    V_TCAS(1U)
6727 
6728 #define S_TCIS    26
6729 #define V_TCIS(x) ((x) << S_TCIS)
6730 #define F_TCIS    V_TCIS(1U)
6731 
6732 #define S_RCAS    25
6733 #define V_RCAS(x) ((x) << S_RCAS)
6734 #define F_RCAS    V_RCAS(1U)
6735 
6736 #define S_PLUS    23
6737 #define V_PLUS(x) ((x) << S_PLUS)
6738 #define F_PLUS    V_PLUS(1U)
6739 
6740 #define S_PLDS    22
6741 #define V_PLDS(x) ((x) << S_PLDS)
6742 #define F_PLDS    V_PLDS(1U)
6743 
6744 #define S_OTDS    21
6745 #define V_OTDS(x) ((x) << S_OTDS)
6746 #define F_OTDS    V_OTDS(1U)
6747 
6748 #define S_RDPS    18
6749 #define V_RDPS(x) ((x) << S_RDPS)
6750 #define F_RDPS    V_RDPS(1U)
6751 
6752 #define S_TDCS    17
6753 #define V_TDCS(x) ((x) << S_TDCS)
6754 #define F_TDCS    V_TDCS(1U)
6755 
6756 #define S_TDUS    16
6757 #define V_TDUS(x) ((x) << S_TDUS)
6758 #define F_TDUS    V_TDUS(1U)
6759 
6760 #define A_PCIE_CORE_UTL_PCI_EXPRESS_PORT_INTERRUPT_ENABLE 0x59ac
6761 
6762 #define S_TPCI    30
6763 #define V_TPCI(x) ((x) << S_TPCI)
6764 #define F_TPCI    V_TPCI(1U)
6765 
6766 #define S_TNPI    29
6767 #define V_TNPI(x) ((x) << S_TNPI)
6768 #define F_TNPI    V_TNPI(1U)
6769 
6770 #define S_TFTI    28
6771 #define V_TFTI(x) ((x) << S_TFTI)
6772 #define F_TFTI    V_TFTI(1U)
6773 
6774 #define S_TCAI    27
6775 #define V_TCAI(x) ((x) << S_TCAI)
6776 #define F_TCAI    V_TCAI(1U)
6777 
6778 #define S_TCII    26
6779 #define V_TCII(x) ((x) << S_TCII)
6780 #define F_TCII    V_TCII(1U)
6781 
6782 #define S_RCAI    25
6783 #define V_RCAI(x) ((x) << S_RCAI)
6784 #define F_RCAI    V_RCAI(1U)
6785 
6786 #define S_PLUI    23
6787 #define V_PLUI(x) ((x) << S_PLUI)
6788 #define F_PLUI    V_PLUI(1U)
6789 
6790 #define S_PLDI    22
6791 #define V_PLDI(x) ((x) << S_PLDI)
6792 #define F_PLDI    V_PLDI(1U)
6793 
6794 #define S_OTDI    21
6795 #define V_OTDI(x) ((x) << S_OTDI)
6796 #define F_OTDI    V_OTDI(1U)
6797 
6798 #define A_PCIE_CORE_ROOT_COMPLEX_STATUS 0x59b0
6799 
6800 #define S_RLCE    31
6801 #define V_RLCE(x) ((x) << S_RLCE)
6802 #define F_RLCE    V_RLCE(1U)
6803 
6804 #define S_RLNE    30
6805 #define V_RLNE(x) ((x) << S_RLNE)
6806 #define F_RLNE    V_RLNE(1U)
6807 
6808 #define S_RLFE    29
6809 #define V_RLFE(x) ((x) << S_RLFE)
6810 #define F_RLFE    V_RLFE(1U)
6811 
6812 #define S_RCPE    25
6813 #define V_RCPE(x) ((x) << S_RCPE)
6814 #define F_RCPE    V_RCPE(1U)
6815 
6816 #define S_RCTO    24
6817 #define V_RCTO(x) ((x) << S_RCTO)
6818 #define F_RCTO    V_RCTO(1U)
6819 
6820 #define S_PINA    23
6821 #define V_PINA(x) ((x) << S_PINA)
6822 #define F_PINA    V_PINA(1U)
6823 
6824 #define S_PINB    22
6825 #define V_PINB(x) ((x) << S_PINB)
6826 #define F_PINB    V_PINB(1U)
6827 
6828 #define S_PINC    21
6829 #define V_PINC(x) ((x) << S_PINC)
6830 #define F_PINC    V_PINC(1U)
6831 
6832 #define S_PIND    20
6833 #define V_PIND(x) ((x) << S_PIND)
6834 #define F_PIND    V_PIND(1U)
6835 
6836 #define S_ALER    19
6837 #define V_ALER(x) ((x) << S_ALER)
6838 #define F_ALER    V_ALER(1U)
6839 
6840 #define S_CRSE    18
6841 #define V_CRSE(x) ((x) << S_CRSE)
6842 #define F_CRSE    V_CRSE(1U)
6843 
6844 #define A_PCIE_T5_HMA_CFG 0x59b0
6845 
6846 #define S_HMA_MAXREQCNT    20
6847 #define M_HMA_MAXREQCNT    0x1fU
6848 #define V_HMA_MAXREQCNT(x) ((x) << S_HMA_MAXREQCNT)
6849 #define G_HMA_MAXREQCNT(x) (((x) >> S_HMA_MAXREQCNT) & M_HMA_MAXREQCNT)
6850 
6851 #define S_T5_HMA_MAXRDREQSIZE    17
6852 #define M_T5_HMA_MAXRDREQSIZE    0x7U
6853 #define V_T5_HMA_MAXRDREQSIZE(x) ((x) << S_T5_HMA_MAXRDREQSIZE)
6854 #define G_T5_HMA_MAXRDREQSIZE(x) (((x) >> S_T5_HMA_MAXRDREQSIZE) & M_T5_HMA_MAXRDREQSIZE)
6855 
6856 #define S_T5_HMA_MAXRSPCNT    8
6857 #define M_T5_HMA_MAXRSPCNT    0x1fU
6858 #define V_T5_HMA_MAXRSPCNT(x) ((x) << S_T5_HMA_MAXRSPCNT)
6859 #define G_T5_HMA_MAXRSPCNT(x) (((x) >> S_T5_HMA_MAXRSPCNT) & M_T5_HMA_MAXRSPCNT)
6860 
6861 #define S_T6_HMA_MAXREQCNT    20
6862 #define M_T6_HMA_MAXREQCNT    0x7fU
6863 #define V_T6_HMA_MAXREQCNT(x) ((x) << S_T6_HMA_MAXREQCNT)
6864 #define G_T6_HMA_MAXREQCNT(x) (((x) >> S_T6_HMA_MAXREQCNT) & M_T6_HMA_MAXREQCNT)
6865 
6866 #define S_T6_T5_HMA_MAXRSPCNT    9
6867 #define M_T6_T5_HMA_MAXRSPCNT    0xffU
6868 #define V_T6_T5_HMA_MAXRSPCNT(x) ((x) << S_T6_T5_HMA_MAXRSPCNT)
6869 #define G_T6_T5_HMA_MAXRSPCNT(x) (((x) >> S_T6_T5_HMA_MAXRSPCNT) & M_T6_T5_HMA_MAXRSPCNT)
6870 
6871 #define S_T6_SEQCHKDIS    8
6872 #define V_T6_SEQCHKDIS(x) ((x) << S_T6_SEQCHKDIS)
6873 #define F_T6_SEQCHKDIS    V_T6_SEQCHKDIS(1U)
6874 
6875 #define S_T6_MINTAG    0
6876 #define M_T6_MINTAG    0xffU
6877 #define V_T6_MINTAG(x) ((x) << S_T6_MINTAG)
6878 #define G_T6_MINTAG(x) (((x) >> S_T6_MINTAG) & M_T6_MINTAG)
6879 
6880 #define A_PCIE_CORE_ROOT_COMPLEX_ERROR_SEVERITY 0x59b4
6881 
6882 #define S_RLCS    31
6883 #define V_RLCS(x) ((x) << S_RLCS)
6884 #define F_RLCS    V_RLCS(1U)
6885 
6886 #define S_RLNS    30
6887 #define V_RLNS(x) ((x) << S_RLNS)
6888 #define F_RLNS    V_RLNS(1U)
6889 
6890 #define S_RLFS    29
6891 #define V_RLFS(x) ((x) << S_RLFS)
6892 #define F_RLFS    V_RLFS(1U)
6893 
6894 #define S_RCPS    25
6895 #define V_RCPS(x) ((x) << S_RCPS)
6896 #define F_RCPS    V_RCPS(1U)
6897 
6898 #define S_RCTS    24
6899 #define V_RCTS(x) ((x) << S_RCTS)
6900 #define F_RCTS    V_RCTS(1U)
6901 
6902 #define S_PAAS    23
6903 #define V_PAAS(x) ((x) << S_PAAS)
6904 #define F_PAAS    V_PAAS(1U)
6905 
6906 #define S_PABS    22
6907 #define V_PABS(x) ((x) << S_PABS)
6908 #define F_PABS    V_PABS(1U)
6909 
6910 #define S_PACS    21
6911 #define V_PACS(x) ((x) << S_PACS)
6912 #define F_PACS    V_PACS(1U)
6913 
6914 #define S_PADS    20
6915 #define V_PADS(x) ((x) << S_PADS)
6916 #define F_PADS    V_PADS(1U)
6917 
6918 #define S_ALES    19
6919 #define V_ALES(x) ((x) << S_ALES)
6920 #define F_ALES    V_ALES(1U)
6921 
6922 #define S_CRSS    18
6923 #define V_CRSS(x) ((x) << S_CRSS)
6924 #define F_CRSS    V_CRSS(1U)
6925 
6926 #define A_PCIE_T5_HMA_STAT 0x59b4
6927 
6928 #define S_HMA_RESPCNT    20
6929 #define M_HMA_RESPCNT    0x1ffU
6930 #define V_HMA_RESPCNT(x) ((x) << S_HMA_RESPCNT)
6931 #define G_HMA_RESPCNT(x) (((x) >> S_HMA_RESPCNT) & M_HMA_RESPCNT)
6932 
6933 #define S_HMA_RDREQCNT    12
6934 #define M_HMA_RDREQCNT    0x3fU
6935 #define V_HMA_RDREQCNT(x) ((x) << S_HMA_RDREQCNT)
6936 #define G_HMA_RDREQCNT(x) (((x) >> S_HMA_RDREQCNT) & M_HMA_RDREQCNT)
6937 
6938 #define S_HMA_WRREQCNT    0
6939 #define M_HMA_WRREQCNT    0x1ffU
6940 #define V_HMA_WRREQCNT(x) ((x) << S_HMA_WRREQCNT)
6941 #define G_HMA_WRREQCNT(x) (((x) >> S_HMA_WRREQCNT) & M_HMA_WRREQCNT)
6942 
6943 #define S_T6_HMA_RESPCNT    20
6944 #define M_T6_HMA_RESPCNT    0x3ffU
6945 #define V_T6_HMA_RESPCNT(x) ((x) << S_T6_HMA_RESPCNT)
6946 #define G_T6_HMA_RESPCNT(x) (((x) >> S_T6_HMA_RESPCNT) & M_T6_HMA_RESPCNT)
6947 
6948 #define A_PCIE_CORE_ROOT_COMPLEX_INTERRUPT_ENABLE 0x59b8
6949 
6950 #define S_RLCI    31
6951 #define V_RLCI(x) ((x) << S_RLCI)
6952 #define F_RLCI    V_RLCI(1U)
6953 
6954 #define S_RLNI    30
6955 #define V_RLNI(x) ((x) << S_RLNI)
6956 #define F_RLNI    V_RLNI(1U)
6957 
6958 #define S_RLFI    29
6959 #define V_RLFI(x) ((x) << S_RLFI)
6960 #define F_RLFI    V_RLFI(1U)
6961 
6962 #define S_RCPI    25
6963 #define V_RCPI(x) ((x) << S_RCPI)
6964 #define F_RCPI    V_RCPI(1U)
6965 
6966 #define S_RCTI    24
6967 #define V_RCTI(x) ((x) << S_RCTI)
6968 #define F_RCTI    V_RCTI(1U)
6969 
6970 #define S_PAAI    23
6971 #define V_PAAI(x) ((x) << S_PAAI)
6972 #define F_PAAI    V_PAAI(1U)
6973 
6974 #define S_PABI    22
6975 #define V_PABI(x) ((x) << S_PABI)
6976 #define F_PABI    V_PABI(1U)
6977 
6978 #define S_PACI    21
6979 #define V_PACI(x) ((x) << S_PACI)
6980 #define F_PACI    V_PACI(1U)
6981 
6982 #define S_PADI    20
6983 #define V_PADI(x) ((x) << S_PADI)
6984 #define F_PADI    V_PADI(1U)
6985 
6986 #define S_ALEI    19
6987 #define V_ALEI(x) ((x) << S_ALEI)
6988 #define F_ALEI    V_ALEI(1U)
6989 
6990 #define S_CRSI    18
6991 #define V_CRSI(x) ((x) << S_CRSI)
6992 #define F_CRSI    V_CRSI(1U)
6993 
6994 #define A_PCIE_T5_HMA_STAT2 0x59b8
6995 #define A_PCIE_CORE_ENDPOINT_STATUS 0x59bc
6996 
6997 #define S_PTOM    31
6998 #define V_PTOM(x) ((x) << S_PTOM)
6999 #define F_PTOM    V_PTOM(1U)
7000 
7001 #define S_ALEA    29
7002 #define V_ALEA(x) ((x) << S_ALEA)
7003 #define F_ALEA    V_ALEA(1U)
7004 
7005 #define S_PMC0    23
7006 #define V_PMC0(x) ((x) << S_PMC0)
7007 #define F_PMC0    V_PMC0(1U)
7008 
7009 #define S_PMC1    22
7010 #define V_PMC1(x) ((x) << S_PMC1)
7011 #define F_PMC1    V_PMC1(1U)
7012 
7013 #define S_PMC2    21
7014 #define V_PMC2(x) ((x) << S_PMC2)
7015 #define F_PMC2    V_PMC2(1U)
7016 
7017 #define S_PMC3    20
7018 #define V_PMC3(x) ((x) << S_PMC3)
7019 #define F_PMC3    V_PMC3(1U)
7020 
7021 #define S_PMC4    19
7022 #define V_PMC4(x) ((x) << S_PMC4)
7023 #define F_PMC4    V_PMC4(1U)
7024 
7025 #define S_PMC5    18
7026 #define V_PMC5(x) ((x) << S_PMC5)
7027 #define F_PMC5    V_PMC5(1U)
7028 
7029 #define S_PMC6    17
7030 #define V_PMC6(x) ((x) << S_PMC6)
7031 #define F_PMC6    V_PMC6(1U)
7032 
7033 #define S_PMC7    16
7034 #define V_PMC7(x) ((x) << S_PMC7)
7035 #define F_PMC7    V_PMC7(1U)
7036 
7037 #define A_PCIE_T5_HMA_STAT3 0x59bc
7038 #define A_PCIE_CORE_ENDPOINT_ERROR_SEVERITY 0x59c0
7039 
7040 #define S_PTOS    31
7041 #define V_PTOS(x) ((x) << S_PTOS)
7042 #define F_PTOS    V_PTOS(1U)
7043 
7044 #define S_AENS    29
7045 #define V_AENS(x) ((x) << S_AENS)
7046 #define F_AENS    V_AENS(1U)
7047 
7048 #define S_PC0S    23
7049 #define V_PC0S(x) ((x) << S_PC0S)
7050 #define F_PC0S    V_PC0S(1U)
7051 
7052 #define S_PC1S    22
7053 #define V_PC1S(x) ((x) << S_PC1S)
7054 #define F_PC1S    V_PC1S(1U)
7055 
7056 #define S_PC2S    21
7057 #define V_PC2S(x) ((x) << S_PC2S)
7058 #define F_PC2S    V_PC2S(1U)
7059 
7060 #define S_PC3S    20
7061 #define V_PC3S(x) ((x) << S_PC3S)
7062 #define F_PC3S    V_PC3S(1U)
7063 
7064 #define S_PC4S    19
7065 #define V_PC4S(x) ((x) << S_PC4S)
7066 #define F_PC4S    V_PC4S(1U)
7067 
7068 #define S_PC5S    18
7069 #define V_PC5S(x) ((x) << S_PC5S)
7070 #define F_PC5S    V_PC5S(1U)
7071 
7072 #define S_PC6S    17
7073 #define V_PC6S(x) ((x) << S_PC6S)
7074 #define F_PC6S    V_PC6S(1U)
7075 
7076 #define S_PC7S    16
7077 #define V_PC7S(x) ((x) << S_PC7S)
7078 #define F_PC7S    V_PC7S(1U)
7079 
7080 #define S_PME0    15
7081 #define V_PME0(x) ((x) << S_PME0)
7082 #define F_PME0    V_PME0(1U)
7083 
7084 #define S_PME1    14
7085 #define V_PME1(x) ((x) << S_PME1)
7086 #define F_PME1    V_PME1(1U)
7087 
7088 #define S_PME2    13
7089 #define V_PME2(x) ((x) << S_PME2)
7090 #define F_PME2    V_PME2(1U)
7091 
7092 #define S_PME3    12
7093 #define V_PME3(x) ((x) << S_PME3)
7094 #define F_PME3    V_PME3(1U)
7095 
7096 #define S_PME4    11
7097 #define V_PME4(x) ((x) << S_PME4)
7098 #define F_PME4    V_PME4(1U)
7099 
7100 #define S_PME5    10
7101 #define V_PME5(x) ((x) << S_PME5)
7102 #define F_PME5    V_PME5(1U)
7103 
7104 #define S_PME6    9
7105 #define V_PME6(x) ((x) << S_PME6)
7106 #define F_PME6    V_PME6(1U)
7107 
7108 #define S_PME7    8
7109 #define V_PME7(x) ((x) << S_PME7)
7110 #define F_PME7    V_PME7(1U)
7111 
7112 #define A_PCIE_CGEN 0x59c0
7113 
7114 #define S_VPD_DYNAMIC_CGEN    26
7115 #define V_VPD_DYNAMIC_CGEN(x) ((x) << S_VPD_DYNAMIC_CGEN)
7116 #define F_VPD_DYNAMIC_CGEN    V_VPD_DYNAMIC_CGEN(1U)
7117 
7118 #define S_MA_DYNAMIC_CGEN    25
7119 #define V_MA_DYNAMIC_CGEN(x) ((x) << S_MA_DYNAMIC_CGEN)
7120 #define F_MA_DYNAMIC_CGEN    V_MA_DYNAMIC_CGEN(1U)
7121 
7122 #define S_TAGQ_DYNAMIC_CGEN    24
7123 #define V_TAGQ_DYNAMIC_CGEN(x) ((x) << S_TAGQ_DYNAMIC_CGEN)
7124 #define F_TAGQ_DYNAMIC_CGEN    V_TAGQ_DYNAMIC_CGEN(1U)
7125 
7126 #define S_REQCTL_DYNAMIC_CGEN    23
7127 #define V_REQCTL_DYNAMIC_CGEN(x) ((x) << S_REQCTL_DYNAMIC_CGEN)
7128 #define F_REQCTL_DYNAMIC_CGEN    V_REQCTL_DYNAMIC_CGEN(1U)
7129 
7130 #define S_RSPDATAPROC_DYNAMIC_CGEN    22
7131 #define V_RSPDATAPROC_DYNAMIC_CGEN(x) ((x) << S_RSPDATAPROC_DYNAMIC_CGEN)
7132 #define F_RSPDATAPROC_DYNAMIC_CGEN    V_RSPDATAPROC_DYNAMIC_CGEN(1U)
7133 
7134 #define S_RSPRDQ_DYNAMIC_CGEN    21
7135 #define V_RSPRDQ_DYNAMIC_CGEN(x) ((x) << S_RSPRDQ_DYNAMIC_CGEN)
7136 #define F_RSPRDQ_DYNAMIC_CGEN    V_RSPRDQ_DYNAMIC_CGEN(1U)
7137 
7138 #define S_RSPIPIF_DYNAMIC_CGEN    20
7139 #define V_RSPIPIF_DYNAMIC_CGEN(x) ((x) << S_RSPIPIF_DYNAMIC_CGEN)
7140 #define F_RSPIPIF_DYNAMIC_CGEN    V_RSPIPIF_DYNAMIC_CGEN(1U)
7141 
7142 #define S_HMA_STATIC_CGEN    19
7143 #define V_HMA_STATIC_CGEN(x) ((x) << S_HMA_STATIC_CGEN)
7144 #define F_HMA_STATIC_CGEN    V_HMA_STATIC_CGEN(1U)
7145 
7146 #define S_HMA_DYNAMIC_CGEN    18
7147 #define V_HMA_DYNAMIC_CGEN(x) ((x) << S_HMA_DYNAMIC_CGEN)
7148 #define F_HMA_DYNAMIC_CGEN    V_HMA_DYNAMIC_CGEN(1U)
7149 
7150 #define S_CMD_STATIC_CGEN    16
7151 #define V_CMD_STATIC_CGEN(x) ((x) << S_CMD_STATIC_CGEN)
7152 #define F_CMD_STATIC_CGEN    V_CMD_STATIC_CGEN(1U)
7153 
7154 #define S_CMD_DYNAMIC_CGEN    15
7155 #define V_CMD_DYNAMIC_CGEN(x) ((x) << S_CMD_DYNAMIC_CGEN)
7156 #define F_CMD_DYNAMIC_CGEN    V_CMD_DYNAMIC_CGEN(1U)
7157 
7158 #define S_DMA_STATIC_CGEN    13
7159 #define V_DMA_STATIC_CGEN(x) ((x) << S_DMA_STATIC_CGEN)
7160 #define F_DMA_STATIC_CGEN    V_DMA_STATIC_CGEN(1U)
7161 
7162 #define S_DMA_DYNAMIC_CGEN    12
7163 #define V_DMA_DYNAMIC_CGEN(x) ((x) << S_DMA_DYNAMIC_CGEN)
7164 #define F_DMA_DYNAMIC_CGEN    V_DMA_DYNAMIC_CGEN(1U)
7165 
7166 #define S_VFID_SLEEPSTATUS    10
7167 #define V_VFID_SLEEPSTATUS(x) ((x) << S_VFID_SLEEPSTATUS)
7168 #define F_VFID_SLEEPSTATUS    V_VFID_SLEEPSTATUS(1U)
7169 
7170 #define S_VC1_SLEEPSTATUS    9
7171 #define V_VC1_SLEEPSTATUS(x) ((x) << S_VC1_SLEEPSTATUS)
7172 #define F_VC1_SLEEPSTATUS    V_VC1_SLEEPSTATUS(1U)
7173 
7174 #define S_STI_SLEEPSTATUS    8
7175 #define V_STI_SLEEPSTATUS(x) ((x) << S_STI_SLEEPSTATUS)
7176 #define F_STI_SLEEPSTATUS    V_STI_SLEEPSTATUS(1U)
7177 
7178 #define S_VFID_SLEEPREQ    2
7179 #define V_VFID_SLEEPREQ(x) ((x) << S_VFID_SLEEPREQ)
7180 #define F_VFID_SLEEPREQ    V_VFID_SLEEPREQ(1U)
7181 
7182 #define S_VC1_SLEEPREQ    1
7183 #define V_VC1_SLEEPREQ(x) ((x) << S_VC1_SLEEPREQ)
7184 #define F_VC1_SLEEPREQ    V_VC1_SLEEPREQ(1U)
7185 
7186 #define S_STI_SLEEPREQ    0
7187 #define V_STI_SLEEPREQ(x) ((x) << S_STI_SLEEPREQ)
7188 #define F_STI_SLEEPREQ    V_STI_SLEEPREQ(1U)
7189 
7190 #define A_PCIE_CORE_ENDPOINT_INTERRUPT_ENABLE 0x59c4
7191 
7192 #define S_PTOI    31
7193 #define V_PTOI(x) ((x) << S_PTOI)
7194 #define F_PTOI    V_PTOI(1U)
7195 
7196 #define S_AENI    29
7197 #define V_AENI(x) ((x) << S_AENI)
7198 #define F_AENI    V_AENI(1U)
7199 
7200 #define S_PC0I    23
7201 #define V_PC0I(x) ((x) << S_PC0I)
7202 #define F_PC0I    V_PC0I(1U)
7203 
7204 #define S_PC1I    22
7205 #define V_PC1I(x) ((x) << S_PC1I)
7206 #define F_PC1I    V_PC1I(1U)
7207 
7208 #define S_PC2I    21
7209 #define V_PC2I(x) ((x) << S_PC2I)
7210 #define F_PC2I    V_PC2I(1U)
7211 
7212 #define S_PC3I    20
7213 #define V_PC3I(x) ((x) << S_PC3I)
7214 #define F_PC3I    V_PC3I(1U)
7215 
7216 #define S_PC4I    19
7217 #define V_PC4I(x) ((x) << S_PC4I)
7218 #define F_PC4I    V_PC4I(1U)
7219 
7220 #define S_PC5I    18
7221 #define V_PC5I(x) ((x) << S_PC5I)
7222 #define F_PC5I    V_PC5I(1U)
7223 
7224 #define S_PC6I    17
7225 #define V_PC6I(x) ((x) << S_PC6I)
7226 #define F_PC6I    V_PC6I(1U)
7227 
7228 #define S_PC7I    16
7229 #define V_PC7I(x) ((x) << S_PC7I)
7230 #define F_PC7I    V_PC7I(1U)
7231 
7232 #define A_PCIE_MA_RSP 0x59c4
7233 
7234 #define S_TIMERVALUE    8
7235 #define M_TIMERVALUE    0xffffffU
7236 #define V_TIMERVALUE(x) ((x) << S_TIMERVALUE)
7237 #define G_TIMERVALUE(x) (((x) >> S_TIMERVALUE) & M_TIMERVALUE)
7238 
7239 #define S_MAREQTIMEREN    1
7240 #define V_MAREQTIMEREN(x) ((x) << S_MAREQTIMEREN)
7241 #define F_MAREQTIMEREN    V_MAREQTIMEREN(1U)
7242 
7243 #define S_MARSPTIMEREN    0
7244 #define V_MARSPTIMEREN(x) ((x) << S_MARSPTIMEREN)
7245 #define F_MARSPTIMEREN    V_MARSPTIMEREN(1U)
7246 
7247 #define A_PCIE_CORE_PCI_POWER_MANAGEMENT_CONTROL_1 0x59c8
7248 
7249 #define S_TOAK    31
7250 #define V_TOAK(x) ((x) << S_TOAK)
7251 #define F_TOAK    V_TOAK(1U)
7252 
7253 #define S_L1RS    23
7254 #define V_L1RS(x) ((x) << S_L1RS)
7255 #define F_L1RS    V_L1RS(1U)
7256 
7257 #define S_L23S    22
7258 #define V_L23S(x) ((x) << S_L23S)
7259 #define F_L23S    V_L23S(1U)
7260 
7261 #define S_AL1S    21
7262 #define V_AL1S(x) ((x) << S_AL1S)
7263 #define F_AL1S    V_AL1S(1U)
7264 
7265 #define S_ALET    19
7266 #define V_ALET(x) ((x) << S_ALET)
7267 #define F_ALET    V_ALET(1U)
7268 
7269 #define A_PCIE_HPRD 0x59c8
7270 
7271 #define S_NPH_CREDITSAVAILVC0    19
7272 #define M_NPH_CREDITSAVAILVC0    0x3U
7273 #define V_NPH_CREDITSAVAILVC0(x) ((x) << S_NPH_CREDITSAVAILVC0)
7274 #define G_NPH_CREDITSAVAILVC0(x) (((x) >> S_NPH_CREDITSAVAILVC0) & M_NPH_CREDITSAVAILVC0)
7275 
7276 #define S_NPD_CREDITSAVAILVC0    17
7277 #define M_NPD_CREDITSAVAILVC0    0x3U
7278 #define V_NPD_CREDITSAVAILVC0(x) ((x) << S_NPD_CREDITSAVAILVC0)
7279 #define G_NPD_CREDITSAVAILVC0(x) (((x) >> S_NPD_CREDITSAVAILVC0) & M_NPD_CREDITSAVAILVC0)
7280 
7281 #define S_NPH_CREDITSAVAILVC1    15
7282 #define M_NPH_CREDITSAVAILVC1    0x3U
7283 #define V_NPH_CREDITSAVAILVC1(x) ((x) << S_NPH_CREDITSAVAILVC1)
7284 #define G_NPH_CREDITSAVAILVC1(x) (((x) >> S_NPH_CREDITSAVAILVC1) & M_NPH_CREDITSAVAILVC1)
7285 
7286 #define S_NPD_CREDITSAVAILVC1    13
7287 #define M_NPD_CREDITSAVAILVC1    0x3U
7288 #define V_NPD_CREDITSAVAILVC1(x) ((x) << S_NPD_CREDITSAVAILVC1)
7289 #define G_NPD_CREDITSAVAILVC1(x) (((x) >> S_NPD_CREDITSAVAILVC1) & M_NPD_CREDITSAVAILVC1)
7290 
7291 #define S_NPH_CREDITSREQUIRED    11
7292 #define M_NPH_CREDITSREQUIRED    0x3U
7293 #define V_NPH_CREDITSREQUIRED(x) ((x) << S_NPH_CREDITSREQUIRED)
7294 #define G_NPH_CREDITSREQUIRED(x) (((x) >> S_NPH_CREDITSREQUIRED) & M_NPH_CREDITSREQUIRED)
7295 
7296 #define S_NPD_CREDITSREQUIRED    9
7297 #define M_NPD_CREDITSREQUIRED    0x3U
7298 #define V_NPD_CREDITSREQUIRED(x) ((x) << S_NPD_CREDITSREQUIRED)
7299 #define G_NPD_CREDITSREQUIRED(x) (((x) >> S_NPD_CREDITSREQUIRED) & M_NPD_CREDITSREQUIRED)
7300 
7301 #define S_REQBURSTCOUNT    5
7302 #define M_REQBURSTCOUNT    0xfU
7303 #define V_REQBURSTCOUNT(x) ((x) << S_REQBURSTCOUNT)
7304 #define G_REQBURSTCOUNT(x) (((x) >> S_REQBURSTCOUNT) & M_REQBURSTCOUNT)
7305 
7306 #define S_REQBURSTFREQUENCY    1
7307 #define M_REQBURSTFREQUENCY    0xfU
7308 #define V_REQBURSTFREQUENCY(x) ((x) << S_REQBURSTFREQUENCY)
7309 #define G_REQBURSTFREQUENCY(x) (((x) >> S_REQBURSTFREQUENCY) & M_REQBURSTFREQUENCY)
7310 
7311 #define S_ENABLEVC1    0
7312 #define V_ENABLEVC1(x) ((x) << S_ENABLEVC1)
7313 #define F_ENABLEVC1    V_ENABLEVC1(1U)
7314 
7315 #define A_PCIE_CORE_PCI_POWER_MANAGEMENT_CONTROL_2 0x59cc
7316 
7317 #define S_CPM0    30
7318 #define M_CPM0    0x3U
7319 #define V_CPM0(x) ((x) << S_CPM0)
7320 #define G_CPM0(x) (((x) >> S_CPM0) & M_CPM0)
7321 
7322 #define S_CPM1    28
7323 #define M_CPM1    0x3U
7324 #define V_CPM1(x) ((x) << S_CPM1)
7325 #define G_CPM1(x) (((x) >> S_CPM1) & M_CPM1)
7326 
7327 #define S_CPM2    26
7328 #define M_CPM2    0x3U
7329 #define V_CPM2(x) ((x) << S_CPM2)
7330 #define G_CPM2(x) (((x) >> S_CPM2) & M_CPM2)
7331 
7332 #define S_CPM3    24
7333 #define M_CPM3    0x3U
7334 #define V_CPM3(x) ((x) << S_CPM3)
7335 #define G_CPM3(x) (((x) >> S_CPM3) & M_CPM3)
7336 
7337 #define S_CPM4    22
7338 #define M_CPM4    0x3U
7339 #define V_CPM4(x) ((x) << S_CPM4)
7340 #define G_CPM4(x) (((x) >> S_CPM4) & M_CPM4)
7341 
7342 #define S_CPM5    20
7343 #define M_CPM5    0x3U
7344 #define V_CPM5(x) ((x) << S_CPM5)
7345 #define G_CPM5(x) (((x) >> S_CPM5) & M_CPM5)
7346 
7347 #define S_CPM6    18
7348 #define M_CPM6    0x3U
7349 #define V_CPM6(x) ((x) << S_CPM6)
7350 #define G_CPM6(x) (((x) >> S_CPM6) & M_CPM6)
7351 
7352 #define S_CPM7    16
7353 #define M_CPM7    0x3U
7354 #define V_CPM7(x) ((x) << S_CPM7)
7355 #define G_CPM7(x) (((x) >> S_CPM7) & M_CPM7)
7356 
7357 #define S_OPM0    14
7358 #define M_OPM0    0x3U
7359 #define V_OPM0(x) ((x) << S_OPM0)
7360 #define G_OPM0(x) (((x) >> S_OPM0) & M_OPM0)
7361 
7362 #define S_OPM1    12
7363 #define M_OPM1    0x3U
7364 #define V_OPM1(x) ((x) << S_OPM1)
7365 #define G_OPM1(x) (((x) >> S_OPM1) & M_OPM1)
7366 
7367 #define S_OPM2    10
7368 #define M_OPM2    0x3U
7369 #define V_OPM2(x) ((x) << S_OPM2)
7370 #define G_OPM2(x) (((x) >> S_OPM2) & M_OPM2)
7371 
7372 #define S_OPM3    8
7373 #define M_OPM3    0x3U
7374 #define V_OPM3(x) ((x) << S_OPM3)
7375 #define G_OPM3(x) (((x) >> S_OPM3) & M_OPM3)
7376 
7377 #define S_OPM4    6
7378 #define M_OPM4    0x3U
7379 #define V_OPM4(x) ((x) << S_OPM4)
7380 #define G_OPM4(x) (((x) >> S_OPM4) & M_OPM4)
7381 
7382 #define S_OPM5    4
7383 #define M_OPM5    0x3U
7384 #define V_OPM5(x) ((x) << S_OPM5)
7385 #define G_OPM5(x) (((x) >> S_OPM5) & M_OPM5)
7386 
7387 #define S_OPM6    2
7388 #define M_OPM6    0x3U
7389 #define V_OPM6(x) ((x) << S_OPM6)
7390 #define G_OPM6(x) (((x) >> S_OPM6) & M_OPM6)
7391 
7392 #define S_OPM7    0
7393 #define M_OPM7    0x3U
7394 #define V_OPM7(x) ((x) << S_OPM7)
7395 #define G_OPM7(x) (((x) >> S_OPM7) & M_OPM7)
7396 
7397 #define A_PCIE_CORE_GENERAL_PURPOSE_CONTROL_1 0x59d0
7398 #define A_PCIE_PERR_GROUP 0x59d0
7399 
7400 #define S_MST_DATAPATHPERR    25
7401 #define V_MST_DATAPATHPERR(x) ((x) << S_MST_DATAPATHPERR)
7402 #define F_MST_DATAPATHPERR    V_MST_DATAPATHPERR(1U)
7403 
7404 #define S_MST_RSPRDQPERR    24
7405 #define V_MST_RSPRDQPERR(x) ((x) << S_MST_RSPRDQPERR)
7406 #define F_MST_RSPRDQPERR    V_MST_RSPRDQPERR(1U)
7407 
7408 #define S_IP_RXPERR    23
7409 #define V_IP_RXPERR(x) ((x) << S_IP_RXPERR)
7410 #define F_IP_RXPERR    V_IP_RXPERR(1U)
7411 
7412 #define S_IP_BACKTXPERR    22
7413 #define V_IP_BACKTXPERR(x) ((x) << S_IP_BACKTXPERR)
7414 #define F_IP_BACKTXPERR    V_IP_BACKTXPERR(1U)
7415 
7416 #define S_IP_FRONTTXPERR    21
7417 #define V_IP_FRONTTXPERR(x) ((x) << S_IP_FRONTTXPERR)
7418 #define F_IP_FRONTTXPERR    V_IP_FRONTTXPERR(1U)
7419 
7420 #define S_TRGT1_FIDLKUPHDRPERR    20
7421 #define V_TRGT1_FIDLKUPHDRPERR(x) ((x) << S_TRGT1_FIDLKUPHDRPERR)
7422 #define F_TRGT1_FIDLKUPHDRPERR    V_TRGT1_FIDLKUPHDRPERR(1U)
7423 
7424 #define S_TRGT1_ALINDDATAPERR    19
7425 #define V_TRGT1_ALINDDATAPERR(x) ((x) << S_TRGT1_ALINDDATAPERR)
7426 #define F_TRGT1_ALINDDATAPERR    V_TRGT1_ALINDDATAPERR(1U)
7427 
7428 #define S_TRGT1_UNALINDATAPERR    18
7429 #define V_TRGT1_UNALINDATAPERR(x) ((x) << S_TRGT1_UNALINDATAPERR)
7430 #define F_TRGT1_UNALINDATAPERR    V_TRGT1_UNALINDATAPERR(1U)
7431 
7432 #define S_TRGT1_REQDATAPERR    17
7433 #define V_TRGT1_REQDATAPERR(x) ((x) << S_TRGT1_REQDATAPERR)
7434 #define F_TRGT1_REQDATAPERR    V_TRGT1_REQDATAPERR(1U)
7435 
7436 #define S_TRGT1_REQHDRPERR    16
7437 #define V_TRGT1_REQHDRPERR(x) ((x) << S_TRGT1_REQHDRPERR)
7438 #define F_TRGT1_REQHDRPERR    V_TRGT1_REQHDRPERR(1U)
7439 
7440 #define S_IPRXDATA_VC1PERR    15
7441 #define V_IPRXDATA_VC1PERR(x) ((x) << S_IPRXDATA_VC1PERR)
7442 #define F_IPRXDATA_VC1PERR    V_IPRXDATA_VC1PERR(1U)
7443 
7444 #define S_IPRXDATA_VC0PERR    14
7445 #define V_IPRXDATA_VC0PERR(x) ((x) << S_IPRXDATA_VC0PERR)
7446 #define F_IPRXDATA_VC0PERR    V_IPRXDATA_VC0PERR(1U)
7447 
7448 #define S_IPRXHDR_VC1PERR    13
7449 #define V_IPRXHDR_VC1PERR(x) ((x) << S_IPRXHDR_VC1PERR)
7450 #define F_IPRXHDR_VC1PERR    V_IPRXHDR_VC1PERR(1U)
7451 
7452 #define S_IPRXHDR_VC0PERR    12
7453 #define V_IPRXHDR_VC0PERR(x) ((x) << S_IPRXHDR_VC0PERR)
7454 #define F_IPRXHDR_VC0PERR    V_IPRXHDR_VC0PERR(1U)
7455 
7456 #define S_MA_RSPDATAPERR    11
7457 #define V_MA_RSPDATAPERR(x) ((x) << S_MA_RSPDATAPERR)
7458 #define F_MA_RSPDATAPERR    V_MA_RSPDATAPERR(1U)
7459 
7460 #define S_MA_CPLTAGQPERR    10
7461 #define V_MA_CPLTAGQPERR(x) ((x) << S_MA_CPLTAGQPERR)
7462 #define F_MA_CPLTAGQPERR    V_MA_CPLTAGQPERR(1U)
7463 
7464 #define S_MA_REQTAGQPERR    9
7465 #define V_MA_REQTAGQPERR(x) ((x) << S_MA_REQTAGQPERR)
7466 #define F_MA_REQTAGQPERR    V_MA_REQTAGQPERR(1U)
7467 
7468 #define S_PIOREQ_BAR2CTLPERR    8
7469 #define V_PIOREQ_BAR2CTLPERR(x) ((x) << S_PIOREQ_BAR2CTLPERR)
7470 #define F_PIOREQ_BAR2CTLPERR    V_PIOREQ_BAR2CTLPERR(1U)
7471 
7472 #define S_PIOREQ_MEMCTLPERR    7
7473 #define V_PIOREQ_MEMCTLPERR(x) ((x) << S_PIOREQ_MEMCTLPERR)
7474 #define F_PIOREQ_MEMCTLPERR    V_PIOREQ_MEMCTLPERR(1U)
7475 
7476 #define S_PIOREQ_PLMCTLPERR    6
7477 #define V_PIOREQ_PLMCTLPERR(x) ((x) << S_PIOREQ_PLMCTLPERR)
7478 #define F_PIOREQ_PLMCTLPERR    V_PIOREQ_PLMCTLPERR(1U)
7479 
7480 #define S_PIOREQ_BAR2DATAPERR    5
7481 #define V_PIOREQ_BAR2DATAPERR(x) ((x) << S_PIOREQ_BAR2DATAPERR)
7482 #define F_PIOREQ_BAR2DATAPERR    V_PIOREQ_BAR2DATAPERR(1U)
7483 
7484 #define S_PIOREQ_MEMDATAPERR    4
7485 #define V_PIOREQ_MEMDATAPERR(x) ((x) << S_PIOREQ_MEMDATAPERR)
7486 #define F_PIOREQ_MEMDATAPERR    V_PIOREQ_MEMDATAPERR(1U)
7487 
7488 #define S_PIOREQ_PLMDATAPERR    3
7489 #define V_PIOREQ_PLMDATAPERR(x) ((x) << S_PIOREQ_PLMDATAPERR)
7490 #define F_PIOREQ_PLMDATAPERR    V_PIOREQ_PLMDATAPERR(1U)
7491 
7492 #define S_PIOCPL_CTLPERR    2
7493 #define V_PIOCPL_CTLPERR(x) ((x) << S_PIOCPL_CTLPERR)
7494 #define F_PIOCPL_CTLPERR    V_PIOCPL_CTLPERR(1U)
7495 
7496 #define S_PIOCPL_DATAPERR    1
7497 #define V_PIOCPL_DATAPERR(x) ((x) << S_PIOCPL_DATAPERR)
7498 #define F_PIOCPL_DATAPERR    V_PIOCPL_DATAPERR(1U)
7499 
7500 #define S_PIOCPL_PLMRSPPERR    0
7501 #define V_PIOCPL_PLMRSPPERR(x) ((x) << S_PIOCPL_PLMRSPPERR)
7502 #define F_PIOCPL_PLMRSPPERR    V_PIOCPL_PLMRSPPERR(1U)
7503 
7504 #define S_MA_RSPCTLPERR    26
7505 #define V_MA_RSPCTLPERR(x) ((x) << S_MA_RSPCTLPERR)
7506 #define F_MA_RSPCTLPERR    V_MA_RSPCTLPERR(1U)
7507 
7508 #define S_T6_IPRXDATA_VC0PERR    15
7509 #define V_T6_IPRXDATA_VC0PERR(x) ((x) << S_T6_IPRXDATA_VC0PERR)
7510 #define F_T6_IPRXDATA_VC0PERR    V_T6_IPRXDATA_VC0PERR(1U)
7511 
7512 #define S_T6_IPRXHDR_VC0PERR    14
7513 #define V_T6_IPRXHDR_VC0PERR(x) ((x) << S_T6_IPRXHDR_VC0PERR)
7514 #define F_T6_IPRXHDR_VC0PERR    V_T6_IPRXHDR_VC0PERR(1U)
7515 
7516 #define S_PIOCPL_VDMTXCTLPERR    13
7517 #define V_PIOCPL_VDMTXCTLPERR(x) ((x) << S_PIOCPL_VDMTXCTLPERR)
7518 #define F_PIOCPL_VDMTXCTLPERR    V_PIOCPL_VDMTXCTLPERR(1U)
7519 
7520 #define S_PIOCPL_VDMTXDATAPERR    12
7521 #define V_PIOCPL_VDMTXDATAPERR(x) ((x) << S_PIOCPL_VDMTXDATAPERR)
7522 #define F_PIOCPL_VDMTXDATAPERR    V_PIOCPL_VDMTXDATAPERR(1U)
7523 
7524 #define A_PCIE_CORE_GENERAL_PURPOSE_CONTROL_2 0x59d4
7525 #define A_PCIE_RSP_ERR_INT_LOG_EN 0x59d4
7526 
7527 #define S_CPLSTATUSINTEN    12
7528 #define V_CPLSTATUSINTEN(x) ((x) << S_CPLSTATUSINTEN)
7529 #define F_CPLSTATUSINTEN    V_CPLSTATUSINTEN(1U)
7530 
7531 #define S_REQTIMEOUTINTEN    11
7532 #define V_REQTIMEOUTINTEN(x) ((x) << S_REQTIMEOUTINTEN)
7533 #define F_REQTIMEOUTINTEN    V_REQTIMEOUTINTEN(1U)
7534 
7535 #define S_DISABLEDINTEN    10
7536 #define V_DISABLEDINTEN(x) ((x) << S_DISABLEDINTEN)
7537 #define F_DISABLEDINTEN    V_DISABLEDINTEN(1U)
7538 
7539 #define S_RSPDROPFLRINTEN    9
7540 #define V_RSPDROPFLRINTEN(x) ((x) << S_RSPDROPFLRINTEN)
7541 #define F_RSPDROPFLRINTEN    V_RSPDROPFLRINTEN(1U)
7542 
7543 #define S_REQUNDERFLRINTEN    8
7544 #define V_REQUNDERFLRINTEN(x) ((x) << S_REQUNDERFLRINTEN)
7545 #define F_REQUNDERFLRINTEN    V_REQUNDERFLRINTEN(1U)
7546 
7547 #define S_CPLSTATUSLOGEN    4
7548 #define V_CPLSTATUSLOGEN(x) ((x) << S_CPLSTATUSLOGEN)
7549 #define F_CPLSTATUSLOGEN    V_CPLSTATUSLOGEN(1U)
7550 
7551 #define S_TIMEOUTLOGEN    3
7552 #define V_TIMEOUTLOGEN(x) ((x) << S_TIMEOUTLOGEN)
7553 #define F_TIMEOUTLOGEN    V_TIMEOUTLOGEN(1U)
7554 
7555 #define S_DISABLEDLOGEN    2
7556 #define V_DISABLEDLOGEN(x) ((x) << S_DISABLEDLOGEN)
7557 #define F_DISABLEDLOGEN    V_DISABLEDLOGEN(1U)
7558 
7559 #define S_RSPDROPFLRLOGEN    1
7560 #define V_RSPDROPFLRLOGEN(x) ((x) << S_RSPDROPFLRLOGEN)
7561 #define F_RSPDROPFLRLOGEN    V_RSPDROPFLRLOGEN(1U)
7562 
7563 #define S_REQUNDERFLRLOGEN    0
7564 #define V_REQUNDERFLRLOGEN(x) ((x) << S_REQUNDERFLRLOGEN)
7565 #define F_REQUNDERFLRLOGEN    V_REQUNDERFLRLOGEN(1U)
7566 
7567 #define A_PCIE_RSP_ERR_LOG1 0x59d8
7568 
7569 #define S_REQTAG    25
7570 #define M_REQTAG    0x7fU
7571 #define V_REQTAG(x) ((x) << S_REQTAG)
7572 #define G_REQTAG(x) (((x) >> S_REQTAG) & M_REQTAG)
7573 
7574 #define S_CID    22
7575 #define M_CID    0x7U
7576 #define V_CID(x) ((x) << S_CID)
7577 #define G_CID(x) (((x) >> S_CID) & M_CID)
7578 
7579 #define S_CHNUM    19
7580 #define M_CHNUM    0x7U
7581 #define V_CHNUM(x) ((x) << S_CHNUM)
7582 #define G_CHNUM(x) (((x) >> S_CHNUM) & M_CHNUM)
7583 
7584 #define S_BYTELEN    6
7585 #define M_BYTELEN    0x1fffU
7586 #define V_BYTELEN(x) ((x) << S_BYTELEN)
7587 #define G_BYTELEN(x) (((x) >> S_BYTELEN) & M_BYTELEN)
7588 
7589 #define S_REASON    3
7590 #define M_REASON    0x7U
7591 #define V_REASON(x) ((x) << S_REASON)
7592 #define G_REASON(x) (((x) >> S_REASON) & M_REASON)
7593 
7594 #define S_CPLSTATUS    0
7595 #define M_CPLSTATUS    0x7U
7596 #define V_CPLSTATUS(x) ((x) << S_CPLSTATUS)
7597 #define G_CPLSTATUS(x) (((x) >> S_CPLSTATUS) & M_CPLSTATUS)
7598 
7599 #define A_PCIE_RSP_ERR_LOG2 0x59dc
7600 
7601 #define S_LOGVALID    31
7602 #define V_LOGVALID(x) ((x) << S_LOGVALID)
7603 #define F_LOGVALID    V_LOGVALID(1U)
7604 
7605 #define S_ADDR10B    8
7606 #define M_ADDR10B    0x3ffU
7607 #define V_ADDR10B(x) ((x) << S_ADDR10B)
7608 #define G_ADDR10B(x) (((x) >> S_ADDR10B) & M_ADDR10B)
7609 
7610 #define S_REQVFID    0
7611 #define M_REQVFID    0xffU
7612 #define V_REQVFID(x) ((x) << S_REQVFID)
7613 #define G_REQVFID(x) (((x) >> S_REQVFID) & M_REQVFID)
7614 
7615 #define S_T6_ADDR10B    9
7616 #define M_T6_ADDR10B    0x3ffU
7617 #define V_T6_ADDR10B(x) ((x) << S_T6_ADDR10B)
7618 #define G_T6_ADDR10B(x) (((x) >> S_T6_ADDR10B) & M_T6_ADDR10B)
7619 
7620 #define S_T6_REQVFID    0
7621 #define M_T6_REQVFID    0x1ffU
7622 #define V_T6_REQVFID(x) ((x) << S_T6_REQVFID)
7623 #define G_T6_REQVFID(x) (((x) >> S_T6_REQVFID) & M_T6_REQVFID)
7624 
7625 #define A_PCIE_CHANGESET 0x59fc
7626 #define A_PCIE_REVISION 0x5a00
7627 #define A_PCIE_PDEBUG_INDEX 0x5a04
7628 
7629 #define S_PDEBUGSELH    16
7630 #define M_PDEBUGSELH    0x3fU
7631 #define V_PDEBUGSELH(x) ((x) << S_PDEBUGSELH)
7632 #define G_PDEBUGSELH(x) (((x) >> S_PDEBUGSELH) & M_PDEBUGSELH)
7633 
7634 #define S_PDEBUGSELL    0
7635 #define M_PDEBUGSELL    0x3fU
7636 #define V_PDEBUGSELL(x) ((x) << S_PDEBUGSELL)
7637 #define G_PDEBUGSELL(x) (((x) >> S_PDEBUGSELL) & M_PDEBUGSELL)
7638 
7639 #define S_T6_PDEBUGSELH    16
7640 #define M_T6_PDEBUGSELH    0x7fU
7641 #define V_T6_PDEBUGSELH(x) ((x) << S_T6_PDEBUGSELH)
7642 #define G_T6_PDEBUGSELH(x) (((x) >> S_T6_PDEBUGSELH) & M_T6_PDEBUGSELH)
7643 
7644 #define S_T6_PDEBUGSELL    0
7645 #define M_T6_PDEBUGSELL    0x7fU
7646 #define V_T6_PDEBUGSELL(x) ((x) << S_T6_PDEBUGSELL)
7647 #define G_T6_PDEBUGSELL(x) (((x) >> S_T6_PDEBUGSELL) & M_T6_PDEBUGSELL)
7648 
7649 #define A_PCIE_PDEBUG_DATA_HIGH 0x5a08
7650 #define A_PCIE_PDEBUG_DATA_LOW 0x5a0c
7651 #define A_PCIE_CDEBUG_INDEX 0x5a10
7652 
7653 #define S_CDEBUGSELH    16
7654 #define M_CDEBUGSELH    0xffU
7655 #define V_CDEBUGSELH(x) ((x) << S_CDEBUGSELH)
7656 #define G_CDEBUGSELH(x) (((x) >> S_CDEBUGSELH) & M_CDEBUGSELH)
7657 
7658 #define S_CDEBUGSELL    0
7659 #define M_CDEBUGSELL    0xffU
7660 #define V_CDEBUGSELL(x) ((x) << S_CDEBUGSELL)
7661 #define G_CDEBUGSELL(x) (((x) >> S_CDEBUGSELL) & M_CDEBUGSELL)
7662 
7663 #define A_PCIE_CDEBUG_DATA_HIGH 0x5a14
7664 #define A_PCIE_CDEBUG_DATA_LOW 0x5a18
7665 #define A_PCIE_DMAW_SOP_CNT 0x5a1c
7666 
7667 #define S_CH3    24
7668 #define M_CH3    0xffU
7669 #define V_CH3(x) ((x) << S_CH3)
7670 #define G_CH3(x) (((x) >> S_CH3) & M_CH3)
7671 
7672 #define S_CH2    16
7673 #define M_CH2    0xffU
7674 #define V_CH2(x) ((x) << S_CH2)
7675 #define G_CH2(x) (((x) >> S_CH2) & M_CH2)
7676 
7677 #define S_CH1    8
7678 #define M_CH1    0xffU
7679 #define V_CH1(x) ((x) << S_CH1)
7680 #define G_CH1(x) (((x) >> S_CH1) & M_CH1)
7681 
7682 #define S_CH0    0
7683 #define M_CH0    0xffU
7684 #define V_CH0(x) ((x) << S_CH0)
7685 #define G_CH0(x) (((x) >> S_CH0) & M_CH0)
7686 
7687 #define A_PCIE_DMAW_EOP_CNT 0x5a20
7688 #define A_PCIE_DMAR_REQ_CNT 0x5a24
7689 #define A_PCIE_DMAR_RSP_SOP_CNT 0x5a28
7690 #define A_PCIE_DMAR_RSP_EOP_CNT 0x5a2c
7691 #define A_PCIE_DMAR_RSP_ERR_CNT 0x5a30
7692 #define A_PCIE_DMAI_CNT 0x5a34
7693 #define A_PCIE_CMDW_CNT 0x5a38
7694 
7695 #define S_CH1_EOP    24
7696 #define M_CH1_EOP    0xffU
7697 #define V_CH1_EOP(x) ((x) << S_CH1_EOP)
7698 #define G_CH1_EOP(x) (((x) >> S_CH1_EOP) & M_CH1_EOP)
7699 
7700 #define S_CH1_SOP    16
7701 #define M_CH1_SOP    0xffU
7702 #define V_CH1_SOP(x) ((x) << S_CH1_SOP)
7703 #define G_CH1_SOP(x) (((x) >> S_CH1_SOP) & M_CH1_SOP)
7704 
7705 #define S_CH0_EOP    8
7706 #define M_CH0_EOP    0xffU
7707 #define V_CH0_EOP(x) ((x) << S_CH0_EOP)
7708 #define G_CH0_EOP(x) (((x) >> S_CH0_EOP) & M_CH0_EOP)
7709 
7710 #define S_CH0_SOP    0
7711 #define M_CH0_SOP    0xffU
7712 #define V_CH0_SOP(x) ((x) << S_CH0_SOP)
7713 #define G_CH0_SOP(x) (((x) >> S_CH0_SOP) & M_CH0_SOP)
7714 
7715 #define A_PCIE_CMDR_REQ_CNT 0x5a3c
7716 #define A_PCIE_CMDR_RSP_CNT 0x5a40
7717 #define A_PCIE_CMDR_RSP_ERR_CNT 0x5a44
7718 #define A_PCIE_HMA_REQ_CNT 0x5a48
7719 
7720 #define S_CH0_READ    16
7721 #define M_CH0_READ    0xffU
7722 #define V_CH0_READ(x) ((x) << S_CH0_READ)
7723 #define G_CH0_READ(x) (((x) >> S_CH0_READ) & M_CH0_READ)
7724 
7725 #define S_CH0_WEOP    8
7726 #define M_CH0_WEOP    0xffU
7727 #define V_CH0_WEOP(x) ((x) << S_CH0_WEOP)
7728 #define G_CH0_WEOP(x) (((x) >> S_CH0_WEOP) & M_CH0_WEOP)
7729 
7730 #define S_CH0_WSOP    0
7731 #define M_CH0_WSOP    0xffU
7732 #define V_CH0_WSOP(x) ((x) << S_CH0_WSOP)
7733 #define G_CH0_WSOP(x) (((x) >> S_CH0_WSOP) & M_CH0_WSOP)
7734 
7735 #define A_PCIE_HMA_RSP_CNT 0x5a4c
7736 #define A_PCIE_DMA10_RSP_FREE 0x5a50
7737 
7738 #define S_CH1_RSP_FREE    16
7739 #define M_CH1_RSP_FREE    0xfffU
7740 #define V_CH1_RSP_FREE(x) ((x) << S_CH1_RSP_FREE)
7741 #define G_CH1_RSP_FREE(x) (((x) >> S_CH1_RSP_FREE) & M_CH1_RSP_FREE)
7742 
7743 #define S_CH0_RSP_FREE    0
7744 #define M_CH0_RSP_FREE    0xfffU
7745 #define V_CH0_RSP_FREE(x) ((x) << S_CH0_RSP_FREE)
7746 #define G_CH0_RSP_FREE(x) (((x) >> S_CH0_RSP_FREE) & M_CH0_RSP_FREE)
7747 
7748 #define A_PCIE_DMA32_RSP_FREE 0x5a54
7749 
7750 #define S_CH3_RSP_FREE    16
7751 #define M_CH3_RSP_FREE    0xfffU
7752 #define V_CH3_RSP_FREE(x) ((x) << S_CH3_RSP_FREE)
7753 #define G_CH3_RSP_FREE(x) (((x) >> S_CH3_RSP_FREE) & M_CH3_RSP_FREE)
7754 
7755 #define S_CH2_RSP_FREE    0
7756 #define M_CH2_RSP_FREE    0xfffU
7757 #define V_CH2_RSP_FREE(x) ((x) << S_CH2_RSP_FREE)
7758 #define G_CH2_RSP_FREE(x) (((x) >> S_CH2_RSP_FREE) & M_CH2_RSP_FREE)
7759 
7760 #define A_PCIE_CMD_RSP_FREE 0x5a58
7761 
7762 #define S_CMD_CH1_RSP_FREE    16
7763 #define M_CMD_CH1_RSP_FREE    0x7fU
7764 #define V_CMD_CH1_RSP_FREE(x) ((x) << S_CMD_CH1_RSP_FREE)
7765 #define G_CMD_CH1_RSP_FREE(x) (((x) >> S_CMD_CH1_RSP_FREE) & M_CMD_CH1_RSP_FREE)
7766 
7767 #define S_CMD_CH0_RSP_FREE    0
7768 #define M_CMD_CH0_RSP_FREE    0x7fU
7769 #define V_CMD_CH0_RSP_FREE(x) ((x) << S_CMD_CH0_RSP_FREE)
7770 #define G_CMD_CH0_RSP_FREE(x) (((x) >> S_CMD_CH0_RSP_FREE) & M_CMD_CH0_RSP_FREE)
7771 
7772 #define A_PCIE_HMA_RSP_FREE 0x5a5c
7773 #define A_PCIE_BUS_MST_STAT_0 0x5a60
7774 #define A_PCIE_BUS_MST_STAT_1 0x5a64
7775 #define A_PCIE_BUS_MST_STAT_2 0x5a68
7776 #define A_PCIE_BUS_MST_STAT_3 0x5a6c
7777 #define A_PCIE_BUS_MST_STAT_4 0x5a70
7778 
7779 #define S_BUSMST_135_128    0
7780 #define M_BUSMST_135_128    0xffU
7781 #define V_BUSMST_135_128(x) ((x) << S_BUSMST_135_128)
7782 #define G_BUSMST_135_128(x) (((x) >> S_BUSMST_135_128) & M_BUSMST_135_128)
7783 
7784 #define A_PCIE_BUS_MST_STAT_5 0x5a74
7785 #define A_PCIE_BUS_MST_STAT_6 0x5a78
7786 #define A_PCIE_BUS_MST_STAT_7 0x5a7c
7787 #define A_PCIE_RSP_ERR_STAT_0 0x5a80
7788 #define A_PCIE_RSP_ERR_STAT_1 0x5a84
7789 #define A_PCIE_RSP_ERR_STAT_2 0x5a88
7790 #define A_PCIE_RSP_ERR_STAT_3 0x5a8c
7791 #define A_PCIE_RSP_ERR_STAT_4 0x5a90
7792 
7793 #define S_RSPERR_135_128    0
7794 #define M_RSPERR_135_128    0xffU
7795 #define V_RSPERR_135_128(x) ((x) << S_RSPERR_135_128)
7796 #define G_RSPERR_135_128(x) (((x) >> S_RSPERR_135_128) & M_RSPERR_135_128)
7797 
7798 #define A_PCIE_RSP_ERR_STAT_5 0x5a94
7799 #define A_PCIE_DBI_TIMEOUT_CTL 0x5a94
7800 
7801 #define S_DBI_TIMER    0
7802 #define M_DBI_TIMER    0xffffU
7803 #define V_DBI_TIMER(x) ((x) << S_DBI_TIMER)
7804 #define G_DBI_TIMER(x) (((x) >> S_DBI_TIMER) & M_DBI_TIMER)
7805 
7806 #define A_PCIE_RSP_ERR_STAT_6 0x5a98
7807 #define A_PCIE_DBI_TIMEOUT_STATUS0 0x5a98
7808 #define A_PCIE_RSP_ERR_STAT_7 0x5a9c
7809 #define A_PCIE_DBI_TIMEOUT_STATUS1 0x5a9c
7810 
7811 #define S_SOURCE    16
7812 #define M_SOURCE    0x3U
7813 #define V_SOURCE(x) ((x) << S_SOURCE)
7814 #define G_SOURCE(x) (((x) >> S_SOURCE) & M_SOURCE)
7815 
7816 #define S_DBI_WRITE    12
7817 #define M_DBI_WRITE    0xfU
7818 #define V_DBI_WRITE(x) ((x) << S_DBI_WRITE)
7819 #define G_DBI_WRITE(x) (((x) >> S_DBI_WRITE) & M_DBI_WRITE)
7820 
7821 #define S_DBI_CS2    11
7822 #define V_DBI_CS2(x) ((x) << S_DBI_CS2)
7823 #define F_DBI_CS2    V_DBI_CS2(1U)
7824 
7825 #define S_DBI_PF    8
7826 #define M_DBI_PF    0x7U
7827 #define V_DBI_PF(x) ((x) << S_DBI_PF)
7828 #define G_DBI_PF(x) (((x) >> S_DBI_PF) & M_DBI_PF)
7829 
7830 #define S_PL_TOVFVLD    7
7831 #define V_PL_TOVFVLD(x) ((x) << S_PL_TOVFVLD)
7832 #define F_PL_TOVFVLD    V_PL_TOVFVLD(1U)
7833 
7834 #define S_PL_TOVF    0
7835 #define M_PL_TOVF    0x7fU
7836 #define V_PL_TOVF(x) ((x) << S_PL_TOVF)
7837 #define G_PL_TOVF(x) (((x) >> S_PL_TOVF) & M_PL_TOVF)
7838 
7839 #define S_T6_SOURCE    17
7840 #define M_T6_SOURCE    0x3U
7841 #define V_T6_SOURCE(x) ((x) << S_T6_SOURCE)
7842 #define G_T6_SOURCE(x) (((x) >> S_T6_SOURCE) & M_T6_SOURCE)
7843 
7844 #define S_T6_DBI_WRITE    13
7845 #define M_T6_DBI_WRITE    0xfU
7846 #define V_T6_DBI_WRITE(x) ((x) << S_T6_DBI_WRITE)
7847 #define G_T6_DBI_WRITE(x) (((x) >> S_T6_DBI_WRITE) & M_T6_DBI_WRITE)
7848 
7849 #define S_T6_DBI_CS2    12
7850 #define V_T6_DBI_CS2(x) ((x) << S_T6_DBI_CS2)
7851 #define F_T6_DBI_CS2    V_T6_DBI_CS2(1U)
7852 
7853 #define S_T6_DBI_PF    9
7854 #define M_T6_DBI_PF    0x7U
7855 #define V_T6_DBI_PF(x) ((x) << S_T6_DBI_PF)
7856 #define G_T6_DBI_PF(x) (((x) >> S_T6_DBI_PF) & M_T6_DBI_PF)
7857 
7858 #define S_T6_PL_TOVFVLD    8
7859 #define V_T6_PL_TOVFVLD(x) ((x) << S_T6_PL_TOVFVLD)
7860 #define F_T6_PL_TOVFVLD    V_T6_PL_TOVFVLD(1U)
7861 
7862 #define S_T6_PL_TOVF    0
7863 #define M_T6_PL_TOVF    0xffU
7864 #define V_T6_PL_TOVF(x) ((x) << S_T6_PL_TOVF)
7865 #define G_T6_PL_TOVF(x) (((x) >> S_T6_PL_TOVF) & M_T6_PL_TOVF)
7866 
7867 #define A_PCIE_MSI_EN_0 0x5aa0
7868 #define A_PCIE_MSI_EN_1 0x5aa4
7869 #define A_PCIE_MSI_EN_2 0x5aa8
7870 #define A_PCIE_MSI_EN_3 0x5aac
7871 #define A_PCIE_MSI_EN_4 0x5ab0
7872 #define A_PCIE_MSI_EN_5 0x5ab4
7873 #define A_PCIE_MSI_EN_6 0x5ab8
7874 #define A_PCIE_MSI_EN_7 0x5abc
7875 #define A_PCIE_MSIX_EN_0 0x5ac0
7876 #define A_PCIE_MSIX_EN_1 0x5ac4
7877 #define A_PCIE_MSIX_EN_2 0x5ac8
7878 #define A_PCIE_MSIX_EN_3 0x5acc
7879 #define A_PCIE_MSIX_EN_4 0x5ad0
7880 #define A_PCIE_MSIX_EN_5 0x5ad4
7881 #define A_PCIE_MSIX_EN_6 0x5ad8
7882 #define A_PCIE_MSIX_EN_7 0x5adc
7883 #define A_PCIE_DMA_BUF_CTL 0x5ae0
7884 
7885 #define S_BUFRDCNT    18
7886 #define M_BUFRDCNT    0x3fffU
7887 #define V_BUFRDCNT(x) ((x) << S_BUFRDCNT)
7888 #define G_BUFRDCNT(x) (((x) >> S_BUFRDCNT) & M_BUFRDCNT)
7889 
7890 #define S_BUFWRCNT    9
7891 #define M_BUFWRCNT    0x1ffU
7892 #define V_BUFWRCNT(x) ((x) << S_BUFWRCNT)
7893 #define G_BUFWRCNT(x) (((x) >> S_BUFWRCNT) & M_BUFWRCNT)
7894 
7895 #define S_MAXBUFWRREQ    0
7896 #define M_MAXBUFWRREQ    0x1ffU
7897 #define V_MAXBUFWRREQ(x) ((x) << S_MAXBUFWRREQ)
7898 #define G_MAXBUFWRREQ(x) (((x) >> S_MAXBUFWRREQ) & M_MAXBUFWRREQ)
7899 
7900 #define A_PCIE_PB_CTL 0x5b94
7901 
7902 #define S_PB_SEL    16
7903 #define M_PB_SEL    0xffU
7904 #define V_PB_SEL(x) ((x) << S_PB_SEL)
7905 #define G_PB_SEL(x) (((x) >> S_PB_SEL) & M_PB_SEL)
7906 
7907 #define S_PB_SELREG    8
7908 #define M_PB_SELREG    0xffU
7909 #define V_PB_SELREG(x) ((x) << S_PB_SELREG)
7910 #define G_PB_SELREG(x) (((x) >> S_PB_SELREG) & M_PB_SELREG)
7911 
7912 #define S_PB_FUNC    0
7913 #define M_PB_FUNC    0x7U
7914 #define V_PB_FUNC(x) ((x) << S_PB_FUNC)
7915 #define G_PB_FUNC(x) (((x) >> S_PB_FUNC) & M_PB_FUNC)
7916 
7917 #define A_PCIE_PB_DATA 0x5b98
7918 #define A_PCIE_CUR_LINK 0x5b9c
7919 
7920 #define S_CFGINITCOEFFDONESEEN    22
7921 #define V_CFGINITCOEFFDONESEEN(x) ((x) << S_CFGINITCOEFFDONESEEN)
7922 #define F_CFGINITCOEFFDONESEEN    V_CFGINITCOEFFDONESEEN(1U)
7923 
7924 #define S_CFGINITCOEFFDONE    21
7925 #define V_CFGINITCOEFFDONE(x) ((x) << S_CFGINITCOEFFDONE)
7926 #define F_CFGINITCOEFFDONE    V_CFGINITCOEFFDONE(1U)
7927 
7928 #define S_XMLH_LINK_UP    20
7929 #define V_XMLH_LINK_UP(x) ((x) << S_XMLH_LINK_UP)
7930 #define F_XMLH_LINK_UP    V_XMLH_LINK_UP(1U)
7931 
7932 #define S_PM_LINKST_IN_L0S    19
7933 #define V_PM_LINKST_IN_L0S(x) ((x) << S_PM_LINKST_IN_L0S)
7934 #define F_PM_LINKST_IN_L0S    V_PM_LINKST_IN_L0S(1U)
7935 
7936 #define S_PM_LINKST_IN_L1    18
7937 #define V_PM_LINKST_IN_L1(x) ((x) << S_PM_LINKST_IN_L1)
7938 #define F_PM_LINKST_IN_L1    V_PM_LINKST_IN_L1(1U)
7939 
7940 #define S_PM_LINKST_IN_L2    17
7941 #define V_PM_LINKST_IN_L2(x) ((x) << S_PM_LINKST_IN_L2)
7942 #define F_PM_LINKST_IN_L2    V_PM_LINKST_IN_L2(1U)
7943 
7944 #define S_PM_LINKST_L2_EXIT    16
7945 #define V_PM_LINKST_L2_EXIT(x) ((x) << S_PM_LINKST_L2_EXIT)
7946 #define F_PM_LINKST_L2_EXIT    V_PM_LINKST_L2_EXIT(1U)
7947 
7948 #define S_XMLH_IN_RL0S    15
7949 #define V_XMLH_IN_RL0S(x) ((x) << S_XMLH_IN_RL0S)
7950 #define F_XMLH_IN_RL0S    V_XMLH_IN_RL0S(1U)
7951 
7952 #define S_XMLH_LTSSM_STATE_RCVRY_EQ    14
7953 #define V_XMLH_LTSSM_STATE_RCVRY_EQ(x) ((x) << S_XMLH_LTSSM_STATE_RCVRY_EQ)
7954 #define F_XMLH_LTSSM_STATE_RCVRY_EQ    V_XMLH_LTSSM_STATE_RCVRY_EQ(1U)
7955 
7956 #define S_NEGOTIATEDWIDTH    8
7957 #define M_NEGOTIATEDWIDTH    0x3fU
7958 #define V_NEGOTIATEDWIDTH(x) ((x) << S_NEGOTIATEDWIDTH)
7959 #define G_NEGOTIATEDWIDTH(x) (((x) >> S_NEGOTIATEDWIDTH) & M_NEGOTIATEDWIDTH)
7960 
7961 #define S_ACTIVELANES    0
7962 #define M_ACTIVELANES    0xffU
7963 #define V_ACTIVELANES(x) ((x) << S_ACTIVELANES)
7964 #define G_ACTIVELANES(x) (((x) >> S_ACTIVELANES) & M_ACTIVELANES)
7965 
7966 #define A_PCIE_PHY_REQRXPWR 0x5ba0
7967 
7968 #define S_LNH_RXSTATEDONE    31
7969 #define V_LNH_RXSTATEDONE(x) ((x) << S_LNH_RXSTATEDONE)
7970 #define F_LNH_RXSTATEDONE    V_LNH_RXSTATEDONE(1U)
7971 
7972 #define S_LNH_RXSTATEREQ    30
7973 #define V_LNH_RXSTATEREQ(x) ((x) << S_LNH_RXSTATEREQ)
7974 #define F_LNH_RXSTATEREQ    V_LNH_RXSTATEREQ(1U)
7975 
7976 #define S_LNH_RXPWRSTATE    28
7977 #define M_LNH_RXPWRSTATE    0x3U
7978 #define V_LNH_RXPWRSTATE(x) ((x) << S_LNH_RXPWRSTATE)
7979 #define G_LNH_RXPWRSTATE(x) (((x) >> S_LNH_RXPWRSTATE) & M_LNH_RXPWRSTATE)
7980 
7981 #define S_LNG_RXSTATEDONE    27
7982 #define V_LNG_RXSTATEDONE(x) ((x) << S_LNG_RXSTATEDONE)
7983 #define F_LNG_RXSTATEDONE    V_LNG_RXSTATEDONE(1U)
7984 
7985 #define S_LNG_RXSTATEREQ    26
7986 #define V_LNG_RXSTATEREQ(x) ((x) << S_LNG_RXSTATEREQ)
7987 #define F_LNG_RXSTATEREQ    V_LNG_RXSTATEREQ(1U)
7988 
7989 #define S_LNG_RXPWRSTATE    24
7990 #define M_LNG_RXPWRSTATE    0x3U
7991 #define V_LNG_RXPWRSTATE(x) ((x) << S_LNG_RXPWRSTATE)
7992 #define G_LNG_RXPWRSTATE(x) (((x) >> S_LNG_RXPWRSTATE) & M_LNG_RXPWRSTATE)
7993 
7994 #define S_LNF_RXSTATEDONE    23
7995 #define V_LNF_RXSTATEDONE(x) ((x) << S_LNF_RXSTATEDONE)
7996 #define F_LNF_RXSTATEDONE    V_LNF_RXSTATEDONE(1U)
7997 
7998 #define S_LNF_RXSTATEREQ    22
7999 #define V_LNF_RXSTATEREQ(x) ((x) << S_LNF_RXSTATEREQ)
8000 #define F_LNF_RXSTATEREQ    V_LNF_RXSTATEREQ(1U)
8001 
8002 #define S_LNF_RXPWRSTATE    20
8003 #define M_LNF_RXPWRSTATE    0x3U
8004 #define V_LNF_RXPWRSTATE(x) ((x) << S_LNF_RXPWRSTATE)
8005 #define G_LNF_RXPWRSTATE(x) (((x) >> S_LNF_RXPWRSTATE) & M_LNF_RXPWRSTATE)
8006 
8007 #define S_LNE_RXSTATEDONE    19
8008 #define V_LNE_RXSTATEDONE(x) ((x) << S_LNE_RXSTATEDONE)
8009 #define F_LNE_RXSTATEDONE    V_LNE_RXSTATEDONE(1U)
8010 
8011 #define S_LNE_RXSTATEREQ    18
8012 #define V_LNE_RXSTATEREQ(x) ((x) << S_LNE_RXSTATEREQ)
8013 #define F_LNE_RXSTATEREQ    V_LNE_RXSTATEREQ(1U)
8014 
8015 #define S_LNE_RXPWRSTATE    16
8016 #define M_LNE_RXPWRSTATE    0x3U
8017 #define V_LNE_RXPWRSTATE(x) ((x) << S_LNE_RXPWRSTATE)
8018 #define G_LNE_RXPWRSTATE(x) (((x) >> S_LNE_RXPWRSTATE) & M_LNE_RXPWRSTATE)
8019 
8020 #define S_LND_RXSTATEDONE    15
8021 #define V_LND_RXSTATEDONE(x) ((x) << S_LND_RXSTATEDONE)
8022 #define F_LND_RXSTATEDONE    V_LND_RXSTATEDONE(1U)
8023 
8024 #define S_LND_RXSTATEREQ    14
8025 #define V_LND_RXSTATEREQ(x) ((x) << S_LND_RXSTATEREQ)
8026 #define F_LND_RXSTATEREQ    V_LND_RXSTATEREQ(1U)
8027 
8028 #define S_LND_RXPWRSTATE    12
8029 #define M_LND_RXPWRSTATE    0x3U
8030 #define V_LND_RXPWRSTATE(x) ((x) << S_LND_RXPWRSTATE)
8031 #define G_LND_RXPWRSTATE(x) (((x) >> S_LND_RXPWRSTATE) & M_LND_RXPWRSTATE)
8032 
8033 #define S_LNC_RXSTATEDONE    11
8034 #define V_LNC_RXSTATEDONE(x) ((x) << S_LNC_RXSTATEDONE)
8035 #define F_LNC_RXSTATEDONE    V_LNC_RXSTATEDONE(1U)
8036 
8037 #define S_LNC_RXSTATEREQ    10
8038 #define V_LNC_RXSTATEREQ(x) ((x) << S_LNC_RXSTATEREQ)
8039 #define F_LNC_RXSTATEREQ    V_LNC_RXSTATEREQ(1U)
8040 
8041 #define S_LNC_RXPWRSTATE    8
8042 #define M_LNC_RXPWRSTATE    0x3U
8043 #define V_LNC_RXPWRSTATE(x) ((x) << S_LNC_RXPWRSTATE)
8044 #define G_LNC_RXPWRSTATE(x) (((x) >> S_LNC_RXPWRSTATE) & M_LNC_RXPWRSTATE)
8045 
8046 #define S_LNB_RXSTATEDONE    7
8047 #define V_LNB_RXSTATEDONE(x) ((x) << S_LNB_RXSTATEDONE)
8048 #define F_LNB_RXSTATEDONE    V_LNB_RXSTATEDONE(1U)
8049 
8050 #define S_LNB_RXSTATEREQ    6
8051 #define V_LNB_RXSTATEREQ(x) ((x) << S_LNB_RXSTATEREQ)
8052 #define F_LNB_RXSTATEREQ    V_LNB_RXSTATEREQ(1U)
8053 
8054 #define S_LNB_RXPWRSTATE    4
8055 #define M_LNB_RXPWRSTATE    0x3U
8056 #define V_LNB_RXPWRSTATE(x) ((x) << S_LNB_RXPWRSTATE)
8057 #define G_LNB_RXPWRSTATE(x) (((x) >> S_LNB_RXPWRSTATE) & M_LNB_RXPWRSTATE)
8058 
8059 #define S_LNA_RXSTATEDONE    3
8060 #define V_LNA_RXSTATEDONE(x) ((x) << S_LNA_RXSTATEDONE)
8061 #define F_LNA_RXSTATEDONE    V_LNA_RXSTATEDONE(1U)
8062 
8063 #define S_LNA_RXSTATEREQ    2
8064 #define V_LNA_RXSTATEREQ(x) ((x) << S_LNA_RXSTATEREQ)
8065 #define F_LNA_RXSTATEREQ    V_LNA_RXSTATEREQ(1U)
8066 
8067 #define S_LNA_RXPWRSTATE    0
8068 #define M_LNA_RXPWRSTATE    0x3U
8069 #define V_LNA_RXPWRSTATE(x) ((x) << S_LNA_RXPWRSTATE)
8070 #define G_LNA_RXPWRSTATE(x) (((x) >> S_LNA_RXPWRSTATE) & M_LNA_RXPWRSTATE)
8071 
8072 #define S_REQ_LNH_RXSTATEDONE    31
8073 #define V_REQ_LNH_RXSTATEDONE(x) ((x) << S_REQ_LNH_RXSTATEDONE)
8074 #define F_REQ_LNH_RXSTATEDONE    V_REQ_LNH_RXSTATEDONE(1U)
8075 
8076 #define S_REQ_LNH_RXSTATEREQ    30
8077 #define V_REQ_LNH_RXSTATEREQ(x) ((x) << S_REQ_LNH_RXSTATEREQ)
8078 #define F_REQ_LNH_RXSTATEREQ    V_REQ_LNH_RXSTATEREQ(1U)
8079 
8080 #define S_REQ_LNH_RXPWRSTATE    28
8081 #define M_REQ_LNH_RXPWRSTATE    0x3U
8082 #define V_REQ_LNH_RXPWRSTATE(x) ((x) << S_REQ_LNH_RXPWRSTATE)
8083 #define G_REQ_LNH_RXPWRSTATE(x) (((x) >> S_REQ_LNH_RXPWRSTATE) & M_REQ_LNH_RXPWRSTATE)
8084 
8085 #define S_REQ_LNG_RXSTATEDONE    27
8086 #define V_REQ_LNG_RXSTATEDONE(x) ((x) << S_REQ_LNG_RXSTATEDONE)
8087 #define F_REQ_LNG_RXSTATEDONE    V_REQ_LNG_RXSTATEDONE(1U)
8088 
8089 #define S_REQ_LNG_RXSTATEREQ    26
8090 #define V_REQ_LNG_RXSTATEREQ(x) ((x) << S_REQ_LNG_RXSTATEREQ)
8091 #define F_REQ_LNG_RXSTATEREQ    V_REQ_LNG_RXSTATEREQ(1U)
8092 
8093 #define S_REQ_LNG_RXPWRSTATE    24
8094 #define M_REQ_LNG_RXPWRSTATE    0x3U
8095 #define V_REQ_LNG_RXPWRSTATE(x) ((x) << S_REQ_LNG_RXPWRSTATE)
8096 #define G_REQ_LNG_RXPWRSTATE(x) (((x) >> S_REQ_LNG_RXPWRSTATE) & M_REQ_LNG_RXPWRSTATE)
8097 
8098 #define S_REQ_LNF_RXSTATEDONE    23
8099 #define V_REQ_LNF_RXSTATEDONE(x) ((x) << S_REQ_LNF_RXSTATEDONE)
8100 #define F_REQ_LNF_RXSTATEDONE    V_REQ_LNF_RXSTATEDONE(1U)
8101 
8102 #define S_REQ_LNF_RXSTATEREQ    22
8103 #define V_REQ_LNF_RXSTATEREQ(x) ((x) << S_REQ_LNF_RXSTATEREQ)
8104 #define F_REQ_LNF_RXSTATEREQ    V_REQ_LNF_RXSTATEREQ(1U)
8105 
8106 #define S_REQ_LNF_RXPWRSTATE    20
8107 #define M_REQ_LNF_RXPWRSTATE    0x3U
8108 #define V_REQ_LNF_RXPWRSTATE(x) ((x) << S_REQ_LNF_RXPWRSTATE)
8109 #define G_REQ_LNF_RXPWRSTATE(x) (((x) >> S_REQ_LNF_RXPWRSTATE) & M_REQ_LNF_RXPWRSTATE)
8110 
8111 #define S_REQ_LNE_RXSTATEDONE    19
8112 #define V_REQ_LNE_RXSTATEDONE(x) ((x) << S_REQ_LNE_RXSTATEDONE)
8113 #define F_REQ_LNE_RXSTATEDONE    V_REQ_LNE_RXSTATEDONE(1U)
8114 
8115 #define S_REQ_LNE_RXSTATEREQ    18
8116 #define V_REQ_LNE_RXSTATEREQ(x) ((x) << S_REQ_LNE_RXSTATEREQ)
8117 #define F_REQ_LNE_RXSTATEREQ    V_REQ_LNE_RXSTATEREQ(1U)
8118 
8119 #define S_REQ_LNE_RXPWRSTATE    16
8120 #define M_REQ_LNE_RXPWRSTATE    0x3U
8121 #define V_REQ_LNE_RXPWRSTATE(x) ((x) << S_REQ_LNE_RXPWRSTATE)
8122 #define G_REQ_LNE_RXPWRSTATE(x) (((x) >> S_REQ_LNE_RXPWRSTATE) & M_REQ_LNE_RXPWRSTATE)
8123 
8124 #define S_REQ_LND_RXSTATEDONE    15
8125 #define V_REQ_LND_RXSTATEDONE(x) ((x) << S_REQ_LND_RXSTATEDONE)
8126 #define F_REQ_LND_RXSTATEDONE    V_REQ_LND_RXSTATEDONE(1U)
8127 
8128 #define S_REQ_LND_RXSTATEREQ    14
8129 #define V_REQ_LND_RXSTATEREQ(x) ((x) << S_REQ_LND_RXSTATEREQ)
8130 #define F_REQ_LND_RXSTATEREQ    V_REQ_LND_RXSTATEREQ(1U)
8131 
8132 #define S_REQ_LND_RXPWRSTATE    12
8133 #define M_REQ_LND_RXPWRSTATE    0x3U
8134 #define V_REQ_LND_RXPWRSTATE(x) ((x) << S_REQ_LND_RXPWRSTATE)
8135 #define G_REQ_LND_RXPWRSTATE(x) (((x) >> S_REQ_LND_RXPWRSTATE) & M_REQ_LND_RXPWRSTATE)
8136 
8137 #define S_REQ_LNC_RXSTATEDONE    11
8138 #define V_REQ_LNC_RXSTATEDONE(x) ((x) << S_REQ_LNC_RXSTATEDONE)
8139 #define F_REQ_LNC_RXSTATEDONE    V_REQ_LNC_RXSTATEDONE(1U)
8140 
8141 #define S_REQ_LNC_RXSTATEREQ    10
8142 #define V_REQ_LNC_RXSTATEREQ(x) ((x) << S_REQ_LNC_RXSTATEREQ)
8143 #define F_REQ_LNC_RXSTATEREQ    V_REQ_LNC_RXSTATEREQ(1U)
8144 
8145 #define S_REQ_LNC_RXPWRSTATE    8
8146 #define M_REQ_LNC_RXPWRSTATE    0x3U
8147 #define V_REQ_LNC_RXPWRSTATE(x) ((x) << S_REQ_LNC_RXPWRSTATE)
8148 #define G_REQ_LNC_RXPWRSTATE(x) (((x) >> S_REQ_LNC_RXPWRSTATE) & M_REQ_LNC_RXPWRSTATE)
8149 
8150 #define S_REQ_LNB_RXSTATEDONE    7
8151 #define V_REQ_LNB_RXSTATEDONE(x) ((x) << S_REQ_LNB_RXSTATEDONE)
8152 #define F_REQ_LNB_RXSTATEDONE    V_REQ_LNB_RXSTATEDONE(1U)
8153 
8154 #define S_REQ_LNB_RXSTATEREQ    6
8155 #define V_REQ_LNB_RXSTATEREQ(x) ((x) << S_REQ_LNB_RXSTATEREQ)
8156 #define F_REQ_LNB_RXSTATEREQ    V_REQ_LNB_RXSTATEREQ(1U)
8157 
8158 #define S_REQ_LNB_RXPWRSTATE    4
8159 #define M_REQ_LNB_RXPWRSTATE    0x3U
8160 #define V_REQ_LNB_RXPWRSTATE(x) ((x) << S_REQ_LNB_RXPWRSTATE)
8161 #define G_REQ_LNB_RXPWRSTATE(x) (((x) >> S_REQ_LNB_RXPWRSTATE) & M_REQ_LNB_RXPWRSTATE)
8162 
8163 #define S_REQ_LNA_RXSTATEDONE    3
8164 #define V_REQ_LNA_RXSTATEDONE(x) ((x) << S_REQ_LNA_RXSTATEDONE)
8165 #define F_REQ_LNA_RXSTATEDONE    V_REQ_LNA_RXSTATEDONE(1U)
8166 
8167 #define S_REQ_LNA_RXSTATEREQ    2
8168 #define V_REQ_LNA_RXSTATEREQ(x) ((x) << S_REQ_LNA_RXSTATEREQ)
8169 #define F_REQ_LNA_RXSTATEREQ    V_REQ_LNA_RXSTATEREQ(1U)
8170 
8171 #define S_REQ_LNA_RXPWRSTATE    0
8172 #define M_REQ_LNA_RXPWRSTATE    0x3U
8173 #define V_REQ_LNA_RXPWRSTATE(x) ((x) << S_REQ_LNA_RXPWRSTATE)
8174 #define G_REQ_LNA_RXPWRSTATE(x) (((x) >> S_REQ_LNA_RXPWRSTATE) & M_REQ_LNA_RXPWRSTATE)
8175 
8176 #define A_PCIE_PHY_CURRXPWR 0x5ba4
8177 
8178 #define S_T5_LNH_RXPWRSTATE    28
8179 #define M_T5_LNH_RXPWRSTATE    0x7U
8180 #define V_T5_LNH_RXPWRSTATE(x) ((x) << S_T5_LNH_RXPWRSTATE)
8181 #define G_T5_LNH_RXPWRSTATE(x) (((x) >> S_T5_LNH_RXPWRSTATE) & M_T5_LNH_RXPWRSTATE)
8182 
8183 #define S_T5_LNG_RXPWRSTATE    24
8184 #define M_T5_LNG_RXPWRSTATE    0x7U
8185 #define V_T5_LNG_RXPWRSTATE(x) ((x) << S_T5_LNG_RXPWRSTATE)
8186 #define G_T5_LNG_RXPWRSTATE(x) (((x) >> S_T5_LNG_RXPWRSTATE) & M_T5_LNG_RXPWRSTATE)
8187 
8188 #define S_T5_LNF_RXPWRSTATE    20
8189 #define M_T5_LNF_RXPWRSTATE    0x7U
8190 #define V_T5_LNF_RXPWRSTATE(x) ((x) << S_T5_LNF_RXPWRSTATE)
8191 #define G_T5_LNF_RXPWRSTATE(x) (((x) >> S_T5_LNF_RXPWRSTATE) & M_T5_LNF_RXPWRSTATE)
8192 
8193 #define S_T5_LNE_RXPWRSTATE    16
8194 #define M_T5_LNE_RXPWRSTATE    0x7U
8195 #define V_T5_LNE_RXPWRSTATE(x) ((x) << S_T5_LNE_RXPWRSTATE)
8196 #define G_T5_LNE_RXPWRSTATE(x) (((x) >> S_T5_LNE_RXPWRSTATE) & M_T5_LNE_RXPWRSTATE)
8197 
8198 #define S_T5_LND_RXPWRSTATE    12
8199 #define M_T5_LND_RXPWRSTATE    0x7U
8200 #define V_T5_LND_RXPWRSTATE(x) ((x) << S_T5_LND_RXPWRSTATE)
8201 #define G_T5_LND_RXPWRSTATE(x) (((x) >> S_T5_LND_RXPWRSTATE) & M_T5_LND_RXPWRSTATE)
8202 
8203 #define S_T5_LNC_RXPWRSTATE    8
8204 #define M_T5_LNC_RXPWRSTATE    0x7U
8205 #define V_T5_LNC_RXPWRSTATE(x) ((x) << S_T5_LNC_RXPWRSTATE)
8206 #define G_T5_LNC_RXPWRSTATE(x) (((x) >> S_T5_LNC_RXPWRSTATE) & M_T5_LNC_RXPWRSTATE)
8207 
8208 #define S_T5_LNB_RXPWRSTATE    4
8209 #define M_T5_LNB_RXPWRSTATE    0x7U
8210 #define V_T5_LNB_RXPWRSTATE(x) ((x) << S_T5_LNB_RXPWRSTATE)
8211 #define G_T5_LNB_RXPWRSTATE(x) (((x) >> S_T5_LNB_RXPWRSTATE) & M_T5_LNB_RXPWRSTATE)
8212 
8213 #define S_T5_LNA_RXPWRSTATE    0
8214 #define M_T5_LNA_RXPWRSTATE    0x7U
8215 #define V_T5_LNA_RXPWRSTATE(x) ((x) << S_T5_LNA_RXPWRSTATE)
8216 #define G_T5_LNA_RXPWRSTATE(x) (((x) >> S_T5_LNA_RXPWRSTATE) & M_T5_LNA_RXPWRSTATE)
8217 
8218 #define S_CUR_LNH_RXPWRSTATE    28
8219 #define M_CUR_LNH_RXPWRSTATE    0x7U
8220 #define V_CUR_LNH_RXPWRSTATE(x) ((x) << S_CUR_LNH_RXPWRSTATE)
8221 #define G_CUR_LNH_RXPWRSTATE(x) (((x) >> S_CUR_LNH_RXPWRSTATE) & M_CUR_LNH_RXPWRSTATE)
8222 
8223 #define S_CUR_LNG_RXPWRSTATE    24
8224 #define M_CUR_LNG_RXPWRSTATE    0x7U
8225 #define V_CUR_LNG_RXPWRSTATE(x) ((x) << S_CUR_LNG_RXPWRSTATE)
8226 #define G_CUR_LNG_RXPWRSTATE(x) (((x) >> S_CUR_LNG_RXPWRSTATE) & M_CUR_LNG_RXPWRSTATE)
8227 
8228 #define S_CUR_LNF_RXPWRSTATE    20
8229 #define M_CUR_LNF_RXPWRSTATE    0x7U
8230 #define V_CUR_LNF_RXPWRSTATE(x) ((x) << S_CUR_LNF_RXPWRSTATE)
8231 #define G_CUR_LNF_RXPWRSTATE(x) (((x) >> S_CUR_LNF_RXPWRSTATE) & M_CUR_LNF_RXPWRSTATE)
8232 
8233 #define S_CUR_LNE_RXPWRSTATE    16
8234 #define M_CUR_LNE_RXPWRSTATE    0x7U
8235 #define V_CUR_LNE_RXPWRSTATE(x) ((x) << S_CUR_LNE_RXPWRSTATE)
8236 #define G_CUR_LNE_RXPWRSTATE(x) (((x) >> S_CUR_LNE_RXPWRSTATE) & M_CUR_LNE_RXPWRSTATE)
8237 
8238 #define S_CUR_LND_RXPWRSTATE    12
8239 #define M_CUR_LND_RXPWRSTATE    0x7U
8240 #define V_CUR_LND_RXPWRSTATE(x) ((x) << S_CUR_LND_RXPWRSTATE)
8241 #define G_CUR_LND_RXPWRSTATE(x) (((x) >> S_CUR_LND_RXPWRSTATE) & M_CUR_LND_RXPWRSTATE)
8242 
8243 #define S_CUR_LNC_RXPWRSTATE    8
8244 #define M_CUR_LNC_RXPWRSTATE    0x7U
8245 #define V_CUR_LNC_RXPWRSTATE(x) ((x) << S_CUR_LNC_RXPWRSTATE)
8246 #define G_CUR_LNC_RXPWRSTATE(x) (((x) >> S_CUR_LNC_RXPWRSTATE) & M_CUR_LNC_RXPWRSTATE)
8247 
8248 #define S_CUR_LNB_RXPWRSTATE    4
8249 #define M_CUR_LNB_RXPWRSTATE    0x7U
8250 #define V_CUR_LNB_RXPWRSTATE(x) ((x) << S_CUR_LNB_RXPWRSTATE)
8251 #define G_CUR_LNB_RXPWRSTATE(x) (((x) >> S_CUR_LNB_RXPWRSTATE) & M_CUR_LNB_RXPWRSTATE)
8252 
8253 #define S_CUR_LNA_RXPWRSTATE    0
8254 #define M_CUR_LNA_RXPWRSTATE    0x7U
8255 #define V_CUR_LNA_RXPWRSTATE(x) ((x) << S_CUR_LNA_RXPWRSTATE)
8256 #define G_CUR_LNA_RXPWRSTATE(x) (((x) >> S_CUR_LNA_RXPWRSTATE) & M_CUR_LNA_RXPWRSTATE)
8257 
8258 #define A_PCIE_PHY_GEN3_AE0 0x5ba8
8259 
8260 #define S_LND_STAT    28
8261 #define M_LND_STAT    0x7U
8262 #define V_LND_STAT(x) ((x) << S_LND_STAT)
8263 #define G_LND_STAT(x) (((x) >> S_LND_STAT) & M_LND_STAT)
8264 
8265 #define S_LND_CMD    24
8266 #define M_LND_CMD    0x7U
8267 #define V_LND_CMD(x) ((x) << S_LND_CMD)
8268 #define G_LND_CMD(x) (((x) >> S_LND_CMD) & M_LND_CMD)
8269 
8270 #define S_LNC_STAT    20
8271 #define M_LNC_STAT    0x7U
8272 #define V_LNC_STAT(x) ((x) << S_LNC_STAT)
8273 #define G_LNC_STAT(x) (((x) >> S_LNC_STAT) & M_LNC_STAT)
8274 
8275 #define S_LNC_CMD    16
8276 #define M_LNC_CMD    0x7U
8277 #define V_LNC_CMD(x) ((x) << S_LNC_CMD)
8278 #define G_LNC_CMD(x) (((x) >> S_LNC_CMD) & M_LNC_CMD)
8279 
8280 #define S_LNB_STAT    12
8281 #define M_LNB_STAT    0x7U
8282 #define V_LNB_STAT(x) ((x) << S_LNB_STAT)
8283 #define G_LNB_STAT(x) (((x) >> S_LNB_STAT) & M_LNB_STAT)
8284 
8285 #define S_LNB_CMD    8
8286 #define M_LNB_CMD    0x7U
8287 #define V_LNB_CMD(x) ((x) << S_LNB_CMD)
8288 #define G_LNB_CMD(x) (((x) >> S_LNB_CMD) & M_LNB_CMD)
8289 
8290 #define S_LNA_STAT    4
8291 #define M_LNA_STAT    0x7U
8292 #define V_LNA_STAT(x) ((x) << S_LNA_STAT)
8293 #define G_LNA_STAT(x) (((x) >> S_LNA_STAT) & M_LNA_STAT)
8294 
8295 #define S_LNA_CMD    0
8296 #define M_LNA_CMD    0x7U
8297 #define V_LNA_CMD(x) ((x) << S_LNA_CMD)
8298 #define G_LNA_CMD(x) (((x) >> S_LNA_CMD) & M_LNA_CMD)
8299 
8300 #define A_PCIE_PHY_GEN3_AE1 0x5bac
8301 
8302 #define S_LNH_STAT    28
8303 #define M_LNH_STAT    0x7U
8304 #define V_LNH_STAT(x) ((x) << S_LNH_STAT)
8305 #define G_LNH_STAT(x) (((x) >> S_LNH_STAT) & M_LNH_STAT)
8306 
8307 #define S_LNH_CMD    24
8308 #define M_LNH_CMD    0x7U
8309 #define V_LNH_CMD(x) ((x) << S_LNH_CMD)
8310 #define G_LNH_CMD(x) (((x) >> S_LNH_CMD) & M_LNH_CMD)
8311 
8312 #define S_LNG_STAT    20
8313 #define M_LNG_STAT    0x7U
8314 #define V_LNG_STAT(x) ((x) << S_LNG_STAT)
8315 #define G_LNG_STAT(x) (((x) >> S_LNG_STAT) & M_LNG_STAT)
8316 
8317 #define S_LNG_CMD    16
8318 #define M_LNG_CMD    0x7U
8319 #define V_LNG_CMD(x) ((x) << S_LNG_CMD)
8320 #define G_LNG_CMD(x) (((x) >> S_LNG_CMD) & M_LNG_CMD)
8321 
8322 #define S_LNF_STAT    12
8323 #define M_LNF_STAT    0x7U
8324 #define V_LNF_STAT(x) ((x) << S_LNF_STAT)
8325 #define G_LNF_STAT(x) (((x) >> S_LNF_STAT) & M_LNF_STAT)
8326 
8327 #define S_LNF_CMD    8
8328 #define M_LNF_CMD    0x7U
8329 #define V_LNF_CMD(x) ((x) << S_LNF_CMD)
8330 #define G_LNF_CMD(x) (((x) >> S_LNF_CMD) & M_LNF_CMD)
8331 
8332 #define S_LNE_STAT    4
8333 #define M_LNE_STAT    0x7U
8334 #define V_LNE_STAT(x) ((x) << S_LNE_STAT)
8335 #define G_LNE_STAT(x) (((x) >> S_LNE_STAT) & M_LNE_STAT)
8336 
8337 #define S_LNE_CMD    0
8338 #define M_LNE_CMD    0x7U
8339 #define V_LNE_CMD(x) ((x) << S_LNE_CMD)
8340 #define G_LNE_CMD(x) (((x) >> S_LNE_CMD) & M_LNE_CMD)
8341 
8342 #define A_PCIE_PHY_FS_LF0 0x5bb0
8343 
8344 #define S_LANE1LF    24
8345 #define M_LANE1LF    0x3fU
8346 #define V_LANE1LF(x) ((x) << S_LANE1LF)
8347 #define G_LANE1LF(x) (((x) >> S_LANE1LF) & M_LANE1LF)
8348 
8349 #define S_LANE1FS    16
8350 #define M_LANE1FS    0x3fU
8351 #define V_LANE1FS(x) ((x) << S_LANE1FS)
8352 #define G_LANE1FS(x) (((x) >> S_LANE1FS) & M_LANE1FS)
8353 
8354 #define S_LANE0LF    8
8355 #define M_LANE0LF    0x3fU
8356 #define V_LANE0LF(x) ((x) << S_LANE0LF)
8357 #define G_LANE0LF(x) (((x) >> S_LANE0LF) & M_LANE0LF)
8358 
8359 #define S_LANE0FS    0
8360 #define M_LANE0FS    0x3fU
8361 #define V_LANE0FS(x) ((x) << S_LANE0FS)
8362 #define G_LANE0FS(x) (((x) >> S_LANE0FS) & M_LANE0FS)
8363 
8364 #define A_PCIE_PHY_FS_LF1 0x5bb4
8365 
8366 #define S_LANE3LF    24
8367 #define M_LANE3LF    0x3fU
8368 #define V_LANE3LF(x) ((x) << S_LANE3LF)
8369 #define G_LANE3LF(x) (((x) >> S_LANE3LF) & M_LANE3LF)
8370 
8371 #define S_LANE3FS    16
8372 #define M_LANE3FS    0x3fU
8373 #define V_LANE3FS(x) ((x) << S_LANE3FS)
8374 #define G_LANE3FS(x) (((x) >> S_LANE3FS) & M_LANE3FS)
8375 
8376 #define S_LANE2LF    8
8377 #define M_LANE2LF    0x3fU
8378 #define V_LANE2LF(x) ((x) << S_LANE2LF)
8379 #define G_LANE2LF(x) (((x) >> S_LANE2LF) & M_LANE2LF)
8380 
8381 #define S_LANE2FS    0
8382 #define M_LANE2FS    0x3fU
8383 #define V_LANE2FS(x) ((x) << S_LANE2FS)
8384 #define G_LANE2FS(x) (((x) >> S_LANE2FS) & M_LANE2FS)
8385 
8386 #define A_PCIE_PHY_FS_LF2 0x5bb8
8387 
8388 #define S_LANE5LF    24
8389 #define M_LANE5LF    0x3fU
8390 #define V_LANE5LF(x) ((x) << S_LANE5LF)
8391 #define G_LANE5LF(x) (((x) >> S_LANE5LF) & M_LANE5LF)
8392 
8393 #define S_LANE5FS    16
8394 #define M_LANE5FS    0x3fU
8395 #define V_LANE5FS(x) ((x) << S_LANE5FS)
8396 #define G_LANE5FS(x) (((x) >> S_LANE5FS) & M_LANE5FS)
8397 
8398 #define S_LANE4LF    8
8399 #define M_LANE4LF    0x3fU
8400 #define V_LANE4LF(x) ((x) << S_LANE4LF)
8401 #define G_LANE4LF(x) (((x) >> S_LANE4LF) & M_LANE4LF)
8402 
8403 #define S_LANE4FS    0
8404 #define M_LANE4FS    0x3fU
8405 #define V_LANE4FS(x) ((x) << S_LANE4FS)
8406 #define G_LANE4FS(x) (((x) >> S_LANE4FS) & M_LANE4FS)
8407 
8408 #define A_PCIE_PHY_FS_LF3 0x5bbc
8409 
8410 #define S_LANE7LF    24
8411 #define M_LANE7LF    0x3fU
8412 #define V_LANE7LF(x) ((x) << S_LANE7LF)
8413 #define G_LANE7LF(x) (((x) >> S_LANE7LF) & M_LANE7LF)
8414 
8415 #define S_LANE7FS    16
8416 #define M_LANE7FS    0x3fU
8417 #define V_LANE7FS(x) ((x) << S_LANE7FS)
8418 #define G_LANE7FS(x) (((x) >> S_LANE7FS) & M_LANE7FS)
8419 
8420 #define S_LANE6LF    8
8421 #define M_LANE6LF    0x3fU
8422 #define V_LANE6LF(x) ((x) << S_LANE6LF)
8423 #define G_LANE6LF(x) (((x) >> S_LANE6LF) & M_LANE6LF)
8424 
8425 #define S_LANE6FS    0
8426 #define M_LANE6FS    0x3fU
8427 #define V_LANE6FS(x) ((x) << S_LANE6FS)
8428 #define G_LANE6FS(x) (((x) >> S_LANE6FS) & M_LANE6FS)
8429 
8430 #define A_PCIE_PHY_PRESET_REQ 0x5bc0
8431 
8432 #define S_COEFFDONE    16
8433 #define V_COEFFDONE(x) ((x) << S_COEFFDONE)
8434 #define F_COEFFDONE    V_COEFFDONE(1U)
8435 
8436 #define S_COEFFLANE    8
8437 #define M_COEFFLANE    0x7U
8438 #define V_COEFFLANE(x) ((x) << S_COEFFLANE)
8439 #define G_COEFFLANE(x) (((x) >> S_COEFFLANE) & M_COEFFLANE)
8440 
8441 #define S_COEFFSTART    0
8442 #define V_COEFFSTART(x) ((x) << S_COEFFSTART)
8443 #define F_COEFFSTART    V_COEFFSTART(1U)
8444 
8445 #define S_T6_COEFFLANE    8
8446 #define M_T6_COEFFLANE    0xfU
8447 #define V_T6_COEFFLANE(x) ((x) << S_T6_COEFFLANE)
8448 #define G_T6_COEFFLANE(x) (((x) >> S_T6_COEFFLANE) & M_T6_COEFFLANE)
8449 
8450 #define A_PCIE_PHY_PRESET_COEFF 0x5bc4
8451 
8452 #define S_COEFF    0
8453 #define M_COEFF    0x3ffffU
8454 #define V_COEFF(x) ((x) << S_COEFF)
8455 #define G_COEFF(x) (((x) >> S_COEFF) & M_COEFF)
8456 
8457 #define A_PCIE_PHY_INDIR_REQ 0x5bf0
8458 
8459 #define S_PHYENABLE    31
8460 #define V_PHYENABLE(x) ((x) << S_PHYENABLE)
8461 #define F_PHYENABLE    V_PHYENABLE(1U)
8462 
8463 #define S_PCIE_PHY_REGADDR    0
8464 #define M_PCIE_PHY_REGADDR    0xffffU
8465 #define V_PCIE_PHY_REGADDR(x) ((x) << S_PCIE_PHY_REGADDR)
8466 #define G_PCIE_PHY_REGADDR(x) (((x) >> S_PCIE_PHY_REGADDR) & M_PCIE_PHY_REGADDR)
8467 
8468 #define A_PCIE_PHY_INDIR_DATA 0x5bf4
8469 #define A_PCIE_STATIC_SPARE1 0x5bf8
8470 #define A_PCIE_STATIC_SPARE2 0x5bfc
8471 #define A_PCIE_KDOORBELL_GTS_PF_BASE_LEN 0x5c10
8472 
8473 #define S_KDB_PF_LEN    24
8474 #define M_KDB_PF_LEN    0x1fU
8475 #define V_KDB_PF_LEN(x) ((x) << S_KDB_PF_LEN)
8476 #define G_KDB_PF_LEN(x) (((x) >> S_KDB_PF_LEN) & M_KDB_PF_LEN)
8477 
8478 #define S_KDB_PF_BASEADDR    0
8479 #define M_KDB_PF_BASEADDR    0xfffffU
8480 #define V_KDB_PF_BASEADDR(x) ((x) << S_KDB_PF_BASEADDR)
8481 #define G_KDB_PF_BASEADDR(x) (((x) >> S_KDB_PF_BASEADDR) & M_KDB_PF_BASEADDR)
8482 
8483 #define A_PCIE_KDOORBELL_GTS_VF_BASE_LEN 0x5c14
8484 
8485 #define S_KDB_VF_LEN    24
8486 #define M_KDB_VF_LEN    0x1fU
8487 #define V_KDB_VF_LEN(x) ((x) << S_KDB_VF_LEN)
8488 #define G_KDB_VF_LEN(x) (((x) >> S_KDB_VF_LEN) & M_KDB_VF_LEN)
8489 
8490 #define S_KDB_VF_BASEADDR    0
8491 #define M_KDB_VF_BASEADDR    0xfffffU
8492 #define V_KDB_VF_BASEADDR(x) ((x) << S_KDB_VF_BASEADDR)
8493 #define G_KDB_VF_BASEADDR(x) (((x) >> S_KDB_VF_BASEADDR) & M_KDB_VF_BASEADDR)
8494 
8495 #define A_PCIE_KDOORBELL_GTS_VF_OFFSET 0x5c18
8496 
8497 #define S_KDB_VF_MODOFST    0
8498 #define M_KDB_VF_MODOFST    0xfffU
8499 #define V_KDB_VF_MODOFST(x) ((x) << S_KDB_VF_MODOFST)
8500 #define G_KDB_VF_MODOFST(x) (((x) >> S_KDB_VF_MODOFST) & M_KDB_VF_MODOFST)
8501 
8502 #define A_PCIE_PHY_REQRXPWR1 0x5c1c
8503 
8504 #define S_REQ_LNP_RXSTATEDONE    31
8505 #define V_REQ_LNP_RXSTATEDONE(x) ((x) << S_REQ_LNP_RXSTATEDONE)
8506 #define F_REQ_LNP_RXSTATEDONE    V_REQ_LNP_RXSTATEDONE(1U)
8507 
8508 #define S_REQ_LNP_RXSTATEREQ    30
8509 #define V_REQ_LNP_RXSTATEREQ(x) ((x) << S_REQ_LNP_RXSTATEREQ)
8510 #define F_REQ_LNP_RXSTATEREQ    V_REQ_LNP_RXSTATEREQ(1U)
8511 
8512 #define S_REQ_LNP_RXPWRSTATE    28
8513 #define M_REQ_LNP_RXPWRSTATE    0x3U
8514 #define V_REQ_LNP_RXPWRSTATE(x) ((x) << S_REQ_LNP_RXPWRSTATE)
8515 #define G_REQ_LNP_RXPWRSTATE(x) (((x) >> S_REQ_LNP_RXPWRSTATE) & M_REQ_LNP_RXPWRSTATE)
8516 
8517 #define S_REQ_LNO_RXSTATEDONE    27
8518 #define V_REQ_LNO_RXSTATEDONE(x) ((x) << S_REQ_LNO_RXSTATEDONE)
8519 #define F_REQ_LNO_RXSTATEDONE    V_REQ_LNO_RXSTATEDONE(1U)
8520 
8521 #define S_REQ_LNO_RXSTATEREQ    26
8522 #define V_REQ_LNO_RXSTATEREQ(x) ((x) << S_REQ_LNO_RXSTATEREQ)
8523 #define F_REQ_LNO_RXSTATEREQ    V_REQ_LNO_RXSTATEREQ(1U)
8524 
8525 #define S_REQ_LNO_RXPWRSTATE    24
8526 #define M_REQ_LNO_RXPWRSTATE    0x3U
8527 #define V_REQ_LNO_RXPWRSTATE(x) ((x) << S_REQ_LNO_RXPWRSTATE)
8528 #define G_REQ_LNO_RXPWRSTATE(x) (((x) >> S_REQ_LNO_RXPWRSTATE) & M_REQ_LNO_RXPWRSTATE)
8529 
8530 #define S_REQ_LNN_RXSTATEDONE    23
8531 #define V_REQ_LNN_RXSTATEDONE(x) ((x) << S_REQ_LNN_RXSTATEDONE)
8532 #define F_REQ_LNN_RXSTATEDONE    V_REQ_LNN_RXSTATEDONE(1U)
8533 
8534 #define S_REQ_LNN_RXSTATEREQ    22
8535 #define V_REQ_LNN_RXSTATEREQ(x) ((x) << S_REQ_LNN_RXSTATEREQ)
8536 #define F_REQ_LNN_RXSTATEREQ    V_REQ_LNN_RXSTATEREQ(1U)
8537 
8538 #define S_REQ_LNN_RXPWRSTATE    20
8539 #define M_REQ_LNN_RXPWRSTATE    0x3U
8540 #define V_REQ_LNN_RXPWRSTATE(x) ((x) << S_REQ_LNN_RXPWRSTATE)
8541 #define G_REQ_LNN_RXPWRSTATE(x) (((x) >> S_REQ_LNN_RXPWRSTATE) & M_REQ_LNN_RXPWRSTATE)
8542 
8543 #define S_REQ_LNM_RXSTATEDONE    19
8544 #define V_REQ_LNM_RXSTATEDONE(x) ((x) << S_REQ_LNM_RXSTATEDONE)
8545 #define F_REQ_LNM_RXSTATEDONE    V_REQ_LNM_RXSTATEDONE(1U)
8546 
8547 #define S_REQ_LNM_RXSTATEREQ    18
8548 #define V_REQ_LNM_RXSTATEREQ(x) ((x) << S_REQ_LNM_RXSTATEREQ)
8549 #define F_REQ_LNM_RXSTATEREQ    V_REQ_LNM_RXSTATEREQ(1U)
8550 
8551 #define S_REQ_LNM_RXPWRSTATE    16
8552 #define M_REQ_LNM_RXPWRSTATE    0x3U
8553 #define V_REQ_LNM_RXPWRSTATE(x) ((x) << S_REQ_LNM_RXPWRSTATE)
8554 #define G_REQ_LNM_RXPWRSTATE(x) (((x) >> S_REQ_LNM_RXPWRSTATE) & M_REQ_LNM_RXPWRSTATE)
8555 
8556 #define S_REQ_LNL_RXSTATEDONE    15
8557 #define V_REQ_LNL_RXSTATEDONE(x) ((x) << S_REQ_LNL_RXSTATEDONE)
8558 #define F_REQ_LNL_RXSTATEDONE    V_REQ_LNL_RXSTATEDONE(1U)
8559 
8560 #define S_REQ_LNL_RXSTATEREQ    14
8561 #define V_REQ_LNL_RXSTATEREQ(x) ((x) << S_REQ_LNL_RXSTATEREQ)
8562 #define F_REQ_LNL_RXSTATEREQ    V_REQ_LNL_RXSTATEREQ(1U)
8563 
8564 #define S_REQ_LNL_RXPWRSTATE    12
8565 #define M_REQ_LNL_RXPWRSTATE    0x3U
8566 #define V_REQ_LNL_RXPWRSTATE(x) ((x) << S_REQ_LNL_RXPWRSTATE)
8567 #define G_REQ_LNL_RXPWRSTATE(x) (((x) >> S_REQ_LNL_RXPWRSTATE) & M_REQ_LNL_RXPWRSTATE)
8568 
8569 #define S_REQ_LNK_RXSTATEDONE    11
8570 #define V_REQ_LNK_RXSTATEDONE(x) ((x) << S_REQ_LNK_RXSTATEDONE)
8571 #define F_REQ_LNK_RXSTATEDONE    V_REQ_LNK_RXSTATEDONE(1U)
8572 
8573 #define S_REQ_LNK_RXSTATEREQ    10
8574 #define V_REQ_LNK_RXSTATEREQ(x) ((x) << S_REQ_LNK_RXSTATEREQ)
8575 #define F_REQ_LNK_RXSTATEREQ    V_REQ_LNK_RXSTATEREQ(1U)
8576 
8577 #define S_REQ_LNK_RXPWRSTATE    8
8578 #define M_REQ_LNK_RXPWRSTATE    0x3U
8579 #define V_REQ_LNK_RXPWRSTATE(x) ((x) << S_REQ_LNK_RXPWRSTATE)
8580 #define G_REQ_LNK_RXPWRSTATE(x) (((x) >> S_REQ_LNK_RXPWRSTATE) & M_REQ_LNK_RXPWRSTATE)
8581 
8582 #define S_REQ_LNJ_RXSTATEDONE    7
8583 #define V_REQ_LNJ_RXSTATEDONE(x) ((x) << S_REQ_LNJ_RXSTATEDONE)
8584 #define F_REQ_LNJ_RXSTATEDONE    V_REQ_LNJ_RXSTATEDONE(1U)
8585 
8586 #define S_REQ_LNJ_RXSTATEREQ    6
8587 #define V_REQ_LNJ_RXSTATEREQ(x) ((x) << S_REQ_LNJ_RXSTATEREQ)
8588 #define F_REQ_LNJ_RXSTATEREQ    V_REQ_LNJ_RXSTATEREQ(1U)
8589 
8590 #define S_REQ_LNJ_RXPWRSTATE    4
8591 #define M_REQ_LNJ_RXPWRSTATE    0x3U
8592 #define V_REQ_LNJ_RXPWRSTATE(x) ((x) << S_REQ_LNJ_RXPWRSTATE)
8593 #define G_REQ_LNJ_RXPWRSTATE(x) (((x) >> S_REQ_LNJ_RXPWRSTATE) & M_REQ_LNJ_RXPWRSTATE)
8594 
8595 #define S_REQ_LNI_RXSTATEDONE    3
8596 #define V_REQ_LNI_RXSTATEDONE(x) ((x) << S_REQ_LNI_RXSTATEDONE)
8597 #define F_REQ_LNI_RXSTATEDONE    V_REQ_LNI_RXSTATEDONE(1U)
8598 
8599 #define S_REQ_LNI_RXSTATEREQ    2
8600 #define V_REQ_LNI_RXSTATEREQ(x) ((x) << S_REQ_LNI_RXSTATEREQ)
8601 #define F_REQ_LNI_RXSTATEREQ    V_REQ_LNI_RXSTATEREQ(1U)
8602 
8603 #define S_REQ_LNI_RXPWRSTATE    0
8604 #define M_REQ_LNI_RXPWRSTATE    0x3U
8605 #define V_REQ_LNI_RXPWRSTATE(x) ((x) << S_REQ_LNI_RXPWRSTATE)
8606 #define G_REQ_LNI_RXPWRSTATE(x) (((x) >> S_REQ_LNI_RXPWRSTATE) & M_REQ_LNI_RXPWRSTATE)
8607 
8608 #define A_PCIE_PHY_CURRXPWR1 0x5c20
8609 
8610 #define S_CUR_LNP_RXPWRSTATE    28
8611 #define M_CUR_LNP_RXPWRSTATE    0x7U
8612 #define V_CUR_LNP_RXPWRSTATE(x) ((x) << S_CUR_LNP_RXPWRSTATE)
8613 #define G_CUR_LNP_RXPWRSTATE(x) (((x) >> S_CUR_LNP_RXPWRSTATE) & M_CUR_LNP_RXPWRSTATE)
8614 
8615 #define S_CUR_LNO_RXPWRSTATE    24
8616 #define M_CUR_LNO_RXPWRSTATE    0x7U
8617 #define V_CUR_LNO_RXPWRSTATE(x) ((x) << S_CUR_LNO_RXPWRSTATE)
8618 #define G_CUR_LNO_RXPWRSTATE(x) (((x) >> S_CUR_LNO_RXPWRSTATE) & M_CUR_LNO_RXPWRSTATE)
8619 
8620 #define S_CUR_LNN_RXPWRSTATE    20
8621 #define M_CUR_LNN_RXPWRSTATE    0x7U
8622 #define V_CUR_LNN_RXPWRSTATE(x) ((x) << S_CUR_LNN_RXPWRSTATE)
8623 #define G_CUR_LNN_RXPWRSTATE(x) (((x) >> S_CUR_LNN_RXPWRSTATE) & M_CUR_LNN_RXPWRSTATE)
8624 
8625 #define S_CUR_LNM_RXPWRSTATE    16
8626 #define M_CUR_LNM_RXPWRSTATE    0x7U
8627 #define V_CUR_LNM_RXPWRSTATE(x) ((x) << S_CUR_LNM_RXPWRSTATE)
8628 #define G_CUR_LNM_RXPWRSTATE(x) (((x) >> S_CUR_LNM_RXPWRSTATE) & M_CUR_LNM_RXPWRSTATE)
8629 
8630 #define S_CUR_LNL_RXPWRSTATE    12
8631 #define M_CUR_LNL_RXPWRSTATE    0x7U
8632 #define V_CUR_LNL_RXPWRSTATE(x) ((x) << S_CUR_LNL_RXPWRSTATE)
8633 #define G_CUR_LNL_RXPWRSTATE(x) (((x) >> S_CUR_LNL_RXPWRSTATE) & M_CUR_LNL_RXPWRSTATE)
8634 
8635 #define S_CUR_LNK_RXPWRSTATE    8
8636 #define M_CUR_LNK_RXPWRSTATE    0x7U
8637 #define V_CUR_LNK_RXPWRSTATE(x) ((x) << S_CUR_LNK_RXPWRSTATE)
8638 #define G_CUR_LNK_RXPWRSTATE(x) (((x) >> S_CUR_LNK_RXPWRSTATE) & M_CUR_LNK_RXPWRSTATE)
8639 
8640 #define S_CUR_LNJ_RXPWRSTATE    4
8641 #define M_CUR_LNJ_RXPWRSTATE    0x7U
8642 #define V_CUR_LNJ_RXPWRSTATE(x) ((x) << S_CUR_LNJ_RXPWRSTATE)
8643 #define G_CUR_LNJ_RXPWRSTATE(x) (((x) >> S_CUR_LNJ_RXPWRSTATE) & M_CUR_LNJ_RXPWRSTATE)
8644 
8645 #define S_CUR_LNI_RXPWRSTATE    0
8646 #define M_CUR_LNI_RXPWRSTATE    0x7U
8647 #define V_CUR_LNI_RXPWRSTATE(x) ((x) << S_CUR_LNI_RXPWRSTATE)
8648 #define G_CUR_LNI_RXPWRSTATE(x) (((x) >> S_CUR_LNI_RXPWRSTATE) & M_CUR_LNI_RXPWRSTATE)
8649 
8650 #define A_PCIE_PHY_GEN3_AE2 0x5c24
8651 
8652 #define S_LNL_STAT    28
8653 #define M_LNL_STAT    0x7U
8654 #define V_LNL_STAT(x) ((x) << S_LNL_STAT)
8655 #define G_LNL_STAT(x) (((x) >> S_LNL_STAT) & M_LNL_STAT)
8656 
8657 #define S_LNL_CMD    24
8658 #define M_LNL_CMD    0x7U
8659 #define V_LNL_CMD(x) ((x) << S_LNL_CMD)
8660 #define G_LNL_CMD(x) (((x) >> S_LNL_CMD) & M_LNL_CMD)
8661 
8662 #define S_LNK_STAT    20
8663 #define M_LNK_STAT    0x7U
8664 #define V_LNK_STAT(x) ((x) << S_LNK_STAT)
8665 #define G_LNK_STAT(x) (((x) >> S_LNK_STAT) & M_LNK_STAT)
8666 
8667 #define S_LNK_CMD    16
8668 #define M_LNK_CMD    0x7U
8669 #define V_LNK_CMD(x) ((x) << S_LNK_CMD)
8670 #define G_LNK_CMD(x) (((x) >> S_LNK_CMD) & M_LNK_CMD)
8671 
8672 #define S_LNJ_STAT    12
8673 #define M_LNJ_STAT    0x7U
8674 #define V_LNJ_STAT(x) ((x) << S_LNJ_STAT)
8675 #define G_LNJ_STAT(x) (((x) >> S_LNJ_STAT) & M_LNJ_STAT)
8676 
8677 #define S_LNJ_CMD    8
8678 #define M_LNJ_CMD    0x7U
8679 #define V_LNJ_CMD(x) ((x) << S_LNJ_CMD)
8680 #define G_LNJ_CMD(x) (((x) >> S_LNJ_CMD) & M_LNJ_CMD)
8681 
8682 #define S_LNI_STAT    4
8683 #define M_LNI_STAT    0x7U
8684 #define V_LNI_STAT(x) ((x) << S_LNI_STAT)
8685 #define G_LNI_STAT(x) (((x) >> S_LNI_STAT) & M_LNI_STAT)
8686 
8687 #define S_LNI_CMD    0
8688 #define M_LNI_CMD    0x7U
8689 #define V_LNI_CMD(x) ((x) << S_LNI_CMD)
8690 #define G_LNI_CMD(x) (((x) >> S_LNI_CMD) & M_LNI_CMD)
8691 
8692 #define A_PCIE_PHY_GEN3_AE3 0x5c28
8693 
8694 #define S_LNP_STAT    28
8695 #define M_LNP_STAT    0x7U
8696 #define V_LNP_STAT(x) ((x) << S_LNP_STAT)
8697 #define G_LNP_STAT(x) (((x) >> S_LNP_STAT) & M_LNP_STAT)
8698 
8699 #define S_LNP_CMD    24
8700 #define M_LNP_CMD    0x7U
8701 #define V_LNP_CMD(x) ((x) << S_LNP_CMD)
8702 #define G_LNP_CMD(x) (((x) >> S_LNP_CMD) & M_LNP_CMD)
8703 
8704 #define S_LNO_STAT    20
8705 #define M_LNO_STAT    0x7U
8706 #define V_LNO_STAT(x) ((x) << S_LNO_STAT)
8707 #define G_LNO_STAT(x) (((x) >> S_LNO_STAT) & M_LNO_STAT)
8708 
8709 #define S_LNO_CMD    16
8710 #define M_LNO_CMD    0x7U
8711 #define V_LNO_CMD(x) ((x) << S_LNO_CMD)
8712 #define G_LNO_CMD(x) (((x) >> S_LNO_CMD) & M_LNO_CMD)
8713 
8714 #define S_LNN_STAT    12
8715 #define M_LNN_STAT    0x7U
8716 #define V_LNN_STAT(x) ((x) << S_LNN_STAT)
8717 #define G_LNN_STAT(x) (((x) >> S_LNN_STAT) & M_LNN_STAT)
8718 
8719 #define S_LNN_CMD    8
8720 #define M_LNN_CMD    0x7U
8721 #define V_LNN_CMD(x) ((x) << S_LNN_CMD)
8722 #define G_LNN_CMD(x) (((x) >> S_LNN_CMD) & M_LNN_CMD)
8723 
8724 #define S_LNM_STAT    4
8725 #define M_LNM_STAT    0x7U
8726 #define V_LNM_STAT(x) ((x) << S_LNM_STAT)
8727 #define G_LNM_STAT(x) (((x) >> S_LNM_STAT) & M_LNM_STAT)
8728 
8729 #define S_LNM_CMD    0
8730 #define M_LNM_CMD    0x7U
8731 #define V_LNM_CMD(x) ((x) << S_LNM_CMD)
8732 #define G_LNM_CMD(x) (((x) >> S_LNM_CMD) & M_LNM_CMD)
8733 
8734 #define A_PCIE_PHY_FS_LF4 0x5c2c
8735 
8736 #define S_LANE9LF    24
8737 #define M_LANE9LF    0x3fU
8738 #define V_LANE9LF(x) ((x) << S_LANE9LF)
8739 #define G_LANE9LF(x) (((x) >> S_LANE9LF) & M_LANE9LF)
8740 
8741 #define S_LANE9FS    16
8742 #define M_LANE9FS    0x3fU
8743 #define V_LANE9FS(x) ((x) << S_LANE9FS)
8744 #define G_LANE9FS(x) (((x) >> S_LANE9FS) & M_LANE9FS)
8745 
8746 #define S_LANE8LF    8
8747 #define M_LANE8LF    0x3fU
8748 #define V_LANE8LF(x) ((x) << S_LANE8LF)
8749 #define G_LANE8LF(x) (((x) >> S_LANE8LF) & M_LANE8LF)
8750 
8751 #define S_LANE8FS    0
8752 #define M_LANE8FS    0x3fU
8753 #define V_LANE8FS(x) ((x) << S_LANE8FS)
8754 #define G_LANE8FS(x) (((x) >> S_LANE8FS) & M_LANE8FS)
8755 
8756 #define A_PCIE_PHY_FS_LF5 0x5c30
8757 
8758 #define S_LANE11LF    24
8759 #define M_LANE11LF    0x3fU
8760 #define V_LANE11LF(x) ((x) << S_LANE11LF)
8761 #define G_LANE11LF(x) (((x) >> S_LANE11LF) & M_LANE11LF)
8762 
8763 #define S_LANE11FS    16
8764 #define M_LANE11FS    0x3fU
8765 #define V_LANE11FS(x) ((x) << S_LANE11FS)
8766 #define G_LANE11FS(x) (((x) >> S_LANE11FS) & M_LANE11FS)
8767 
8768 #define S_LANE10LF    8
8769 #define M_LANE10LF    0x3fU
8770 #define V_LANE10LF(x) ((x) << S_LANE10LF)
8771 #define G_LANE10LF(x) (((x) >> S_LANE10LF) & M_LANE10LF)
8772 
8773 #define S_LANE10FS    0
8774 #define M_LANE10FS    0x3fU
8775 #define V_LANE10FS(x) ((x) << S_LANE10FS)
8776 #define G_LANE10FS(x) (((x) >> S_LANE10FS) & M_LANE10FS)
8777 
8778 #define A_PCIE_PHY_FS_LF6 0x5c34
8779 
8780 #define S_LANE13LF    24
8781 #define M_LANE13LF    0x3fU
8782 #define V_LANE13LF(x) ((x) << S_LANE13LF)
8783 #define G_LANE13LF(x) (((x) >> S_LANE13LF) & M_LANE13LF)
8784 
8785 #define S_LANE13FS    16
8786 #define M_LANE13FS    0x3fU
8787 #define V_LANE13FS(x) ((x) << S_LANE13FS)
8788 #define G_LANE13FS(x) (((x) >> S_LANE13FS) & M_LANE13FS)
8789 
8790 #define S_LANE12LF    8
8791 #define M_LANE12LF    0x3fU
8792 #define V_LANE12LF(x) ((x) << S_LANE12LF)
8793 #define G_LANE12LF(x) (((x) >> S_LANE12LF) & M_LANE12LF)
8794 
8795 #define S_LANE12FS    0
8796 #define M_LANE12FS    0x3fU
8797 #define V_LANE12FS(x) ((x) << S_LANE12FS)
8798 #define G_LANE12FS(x) (((x) >> S_LANE12FS) & M_LANE12FS)
8799 
8800 #define A_PCIE_PHY_FS_LF7 0x5c38
8801 
8802 #define S_LANE15LF    24
8803 #define M_LANE15LF    0x3fU
8804 #define V_LANE15LF(x) ((x) << S_LANE15LF)
8805 #define G_LANE15LF(x) (((x) >> S_LANE15LF) & M_LANE15LF)
8806 
8807 #define S_LANE15FS    16
8808 #define M_LANE15FS    0x3fU
8809 #define V_LANE15FS(x) ((x) << S_LANE15FS)
8810 #define G_LANE15FS(x) (((x) >> S_LANE15FS) & M_LANE15FS)
8811 
8812 #define S_LANE14LF    8
8813 #define M_LANE14LF    0x3fU
8814 #define V_LANE14LF(x) ((x) << S_LANE14LF)
8815 #define G_LANE14LF(x) (((x) >> S_LANE14LF) & M_LANE14LF)
8816 
8817 #define S_LANE14FS    0
8818 #define M_LANE14FS    0x3fU
8819 #define V_LANE14FS(x) ((x) << S_LANE14FS)
8820 #define G_LANE14FS(x) (((x) >> S_LANE14FS) & M_LANE14FS)
8821 
8822 #define A_PCIE_MULTI_PHY_INDIR_REQ 0x5c3c
8823 
8824 #define S_PHY_REG_ENABLE    31
8825 #define V_PHY_REG_ENABLE(x) ((x) << S_PHY_REG_ENABLE)
8826 #define F_PHY_REG_ENABLE    V_PHY_REG_ENABLE(1U)
8827 
8828 #define S_PHY_REG_SELECT    22
8829 #define M_PHY_REG_SELECT    0x3U
8830 #define V_PHY_REG_SELECT(x) ((x) << S_PHY_REG_SELECT)
8831 #define G_PHY_REG_SELECT(x) (((x) >> S_PHY_REG_SELECT) & M_PHY_REG_SELECT)
8832 
8833 #define S_PHY_REG_REGADDR    0
8834 #define M_PHY_REG_REGADDR    0xffffU
8835 #define V_PHY_REG_REGADDR(x) ((x) << S_PHY_REG_REGADDR)
8836 #define G_PHY_REG_REGADDR(x) (((x) >> S_PHY_REG_REGADDR) & M_PHY_REG_REGADDR)
8837 
8838 #define A_PCIE_MULTI_PHY_INDIR_DATA 0x5c40
8839 
8840 #define S_PHY_REG_DATA    0
8841 #define M_PHY_REG_DATA    0xffffU
8842 #define V_PHY_REG_DATA(x) ((x) << S_PHY_REG_DATA)
8843 #define G_PHY_REG_DATA(x) (((x) >> S_PHY_REG_DATA) & M_PHY_REG_DATA)
8844 
8845 #define A_PCIE_VF_INT_INDIR_REQ 0x5c44
8846 
8847 #define S_ENABLE_VF    24
8848 #define V_ENABLE_VF(x) ((x) << S_ENABLE_VF)
8849 #define F_ENABLE_VF    V_ENABLE_VF(1U)
8850 
8851 #define S_AI_VF    23
8852 #define V_AI_VF(x) ((x) << S_AI_VF)
8853 #define F_AI_VF    V_AI_VF(1U)
8854 
8855 #define S_VFID_PCIE    0
8856 #define M_VFID_PCIE    0x3ffU
8857 #define V_VFID_PCIE(x) ((x) << S_VFID_PCIE)
8858 #define G_VFID_PCIE(x) (((x) >> S_VFID_PCIE) & M_VFID_PCIE)
8859 
8860 #define A_PCIE_VF_INT_INDIR_DATA 0x5c48
8861 #define A_PCIE_VF_256_INT_CFG2 0x5c4c
8862 #define A_PCIE_VF_MSI_EN_4 0x5e50
8863 #define A_PCIE_VF_MSI_EN_5 0x5e54
8864 #define A_PCIE_VF_MSI_EN_6 0x5e58
8865 #define A_PCIE_VF_MSI_EN_7 0x5e5c
8866 #define A_PCIE_VF_MSIX_EN_4 0x5e60
8867 #define A_PCIE_VF_MSIX_EN_5 0x5e64
8868 #define A_PCIE_VF_MSIX_EN_6 0x5e68
8869 #define A_PCIE_VF_MSIX_EN_7 0x5e6c
8870 #define A_PCIE_FLR_VF4_STATUS 0x5e70
8871 #define A_PCIE_FLR_VF5_STATUS 0x5e74
8872 #define A_PCIE_FLR_VF6_STATUS 0x5e78
8873 #define A_PCIE_FLR_VF7_STATUS 0x5e7c
8874 #define A_T6_PCIE_BUS_MST_STAT_4 0x5e80
8875 #define A_T6_PCIE_BUS_MST_STAT_5 0x5e84
8876 #define A_T6_PCIE_BUS_MST_STAT_6 0x5e88
8877 #define A_T6_PCIE_BUS_MST_STAT_7 0x5e8c
8878 #define A_PCIE_BUS_MST_STAT_8 0x5e90
8879 
8880 #define S_BUSMST_263_256    0
8881 #define M_BUSMST_263_256    0xffU
8882 #define V_BUSMST_263_256(x) ((x) << S_BUSMST_263_256)
8883 #define G_BUSMST_263_256(x) (((x) >> S_BUSMST_263_256) & M_BUSMST_263_256)
8884 
8885 #define A_PCIE_TGT_SKID_FIFO 0x5e94
8886 
8887 #define S_HDRFREECNT    16
8888 #define M_HDRFREECNT    0xfffU
8889 #define V_HDRFREECNT(x) ((x) << S_HDRFREECNT)
8890 #define G_HDRFREECNT(x) (((x) >> S_HDRFREECNT) & M_HDRFREECNT)
8891 
8892 #define S_DATAFREECNT    0
8893 #define M_DATAFREECNT    0xfffU
8894 #define V_DATAFREECNT(x) ((x) << S_DATAFREECNT)
8895 #define G_DATAFREECNT(x) (((x) >> S_DATAFREECNT) & M_DATAFREECNT)
8896 
8897 #define A_T6_PCIE_RSP_ERR_STAT_4 0x5ea0
8898 #define A_T6_PCIE_RSP_ERR_STAT_5 0x5ea4
8899 #define A_T6_PCIE_RSP_ERR_STAT_6 0x5ea8
8900 #define A_T6_PCIE_RSP_ERR_STAT_7 0x5eac
8901 #define A_PCIE_RSP_ERR_STAT_8 0x5eb0
8902 
8903 #define S_RSPERR_263_256    0
8904 #define M_RSPERR_263_256    0xffU
8905 #define V_RSPERR_263_256(x) ((x) << S_RSPERR_263_256)
8906 #define G_RSPERR_263_256(x) (((x) >> S_RSPERR_263_256) & M_RSPERR_263_256)
8907 
8908 #define A_PCIE_PHY_STAT1 0x5ec0
8909 
8910 #define S_PHY0_RTUNE_ACK    31
8911 #define V_PHY0_RTUNE_ACK(x) ((x) << S_PHY0_RTUNE_ACK)
8912 #define F_PHY0_RTUNE_ACK    V_PHY0_RTUNE_ACK(1U)
8913 
8914 #define S_PHY1_RTUNE_ACK    30
8915 #define V_PHY1_RTUNE_ACK(x) ((x) << S_PHY1_RTUNE_ACK)
8916 #define F_PHY1_RTUNE_ACK    V_PHY1_RTUNE_ACK(1U)
8917 
8918 #define A_PCIE_PHY_CTRL1 0x5ec4
8919 
8920 #define S_PHY0_RTUNE_REQ    31
8921 #define V_PHY0_RTUNE_REQ(x) ((x) << S_PHY0_RTUNE_REQ)
8922 #define F_PHY0_RTUNE_REQ    V_PHY0_RTUNE_REQ(1U)
8923 
8924 #define S_PHY1_RTUNE_REQ    30
8925 #define V_PHY1_RTUNE_REQ(x) ((x) << S_PHY1_RTUNE_REQ)
8926 #define F_PHY1_RTUNE_REQ    V_PHY1_RTUNE_REQ(1U)
8927 
8928 #define S_TXDEEMPH_GEN1    16
8929 #define M_TXDEEMPH_GEN1    0xffU
8930 #define V_TXDEEMPH_GEN1(x) ((x) << S_TXDEEMPH_GEN1)
8931 #define G_TXDEEMPH_GEN1(x) (((x) >> S_TXDEEMPH_GEN1) & M_TXDEEMPH_GEN1)
8932 
8933 #define S_TXDEEMPH_GEN2_3P5DB    8
8934 #define M_TXDEEMPH_GEN2_3P5DB    0xffU
8935 #define V_TXDEEMPH_GEN2_3P5DB(x) ((x) << S_TXDEEMPH_GEN2_3P5DB)
8936 #define G_TXDEEMPH_GEN2_3P5DB(x) (((x) >> S_TXDEEMPH_GEN2_3P5DB) & M_TXDEEMPH_GEN2_3P5DB)
8937 
8938 #define S_TXDEEMPH_GEN2_6DB    0
8939 #define M_TXDEEMPH_GEN2_6DB    0xffU
8940 #define V_TXDEEMPH_GEN2_6DB(x) ((x) << S_TXDEEMPH_GEN2_6DB)
8941 #define G_TXDEEMPH_GEN2_6DB(x) (((x) >> S_TXDEEMPH_GEN2_6DB) & M_TXDEEMPH_GEN2_6DB)
8942 
8943 #define A_PCIE_PCIE_SPARE0 0x5ec8
8944 #define A_PCIE_RESET_STAT 0x5ecc
8945 
8946 #define S_PON_RST_STATE_FLAG    11
8947 #define V_PON_RST_STATE_FLAG(x) ((x) << S_PON_RST_STATE_FLAG)
8948 #define F_PON_RST_STATE_FLAG    V_PON_RST_STATE_FLAG(1U)
8949 
8950 #define S_BUS_RST_STATE_FLAG    10
8951 #define V_BUS_RST_STATE_FLAG(x) ((x) << S_BUS_RST_STATE_FLAG)
8952 #define F_BUS_RST_STATE_FLAG    V_BUS_RST_STATE_FLAG(1U)
8953 
8954 #define S_DL_DOWN_PCIECRST_MODE0_STATE_FLAG    9
8955 #define V_DL_DOWN_PCIECRST_MODE0_STATE_FLAG(x) ((x) << S_DL_DOWN_PCIECRST_MODE0_STATE_FLAG)
8956 #define F_DL_DOWN_PCIECRST_MODE0_STATE_FLAG    V_DL_DOWN_PCIECRST_MODE0_STATE_FLAG(1U)
8957 
8958 #define S_DL_DOWN_PCIECRST_MODE1_STATE_FLAG    8
8959 #define V_DL_DOWN_PCIECRST_MODE1_STATE_FLAG(x) ((x) << S_DL_DOWN_PCIECRST_MODE1_STATE_FLAG)
8960 #define F_DL_DOWN_PCIECRST_MODE1_STATE_FLAG    V_DL_DOWN_PCIECRST_MODE1_STATE_FLAG(1U)
8961 
8962 #define S_PCIE_WARM_RST_MODE0_STATE_FLAG    7
8963 #define V_PCIE_WARM_RST_MODE0_STATE_FLAG(x) ((x) << S_PCIE_WARM_RST_MODE0_STATE_FLAG)
8964 #define F_PCIE_WARM_RST_MODE0_STATE_FLAG    V_PCIE_WARM_RST_MODE0_STATE_FLAG(1U)
8965 
8966 #define S_PCIE_WARM_RST_MODE1_STATE_FLAG    6
8967 #define V_PCIE_WARM_RST_MODE1_STATE_FLAG(x) ((x) << S_PCIE_WARM_RST_MODE1_STATE_FLAG)
8968 #define F_PCIE_WARM_RST_MODE1_STATE_FLAG    V_PCIE_WARM_RST_MODE1_STATE_FLAG(1U)
8969 
8970 #define S_PIO_WARM_RST_MODE0_STATE_FLAG    5
8971 #define V_PIO_WARM_RST_MODE0_STATE_FLAG(x) ((x) << S_PIO_WARM_RST_MODE0_STATE_FLAG)
8972 #define F_PIO_WARM_RST_MODE0_STATE_FLAG    V_PIO_WARM_RST_MODE0_STATE_FLAG(1U)
8973 
8974 #define S_PIO_WARM_RST_MODE1_STATE_FLAG    4
8975 #define V_PIO_WARM_RST_MODE1_STATE_FLAG(x) ((x) << S_PIO_WARM_RST_MODE1_STATE_FLAG)
8976 #define F_PIO_WARM_RST_MODE1_STATE_FLAG    V_PIO_WARM_RST_MODE1_STATE_FLAG(1U)
8977 
8978 #define S_LASTRESETSTATE    0
8979 #define M_LASTRESETSTATE    0x7U
8980 #define V_LASTRESETSTATE(x) ((x) << S_LASTRESETSTATE)
8981 #define G_LASTRESETSTATE(x) (((x) >> S_LASTRESETSTATE) & M_LASTRESETSTATE)
8982 
8983 #define A_PCIE_FUNC_DSTATE 0x5ed0
8984 
8985 #define S_PF7_DSTATE    21
8986 #define M_PF7_DSTATE    0x7U
8987 #define V_PF7_DSTATE(x) ((x) << S_PF7_DSTATE)
8988 #define G_PF7_DSTATE(x) (((x) >> S_PF7_DSTATE) & M_PF7_DSTATE)
8989 
8990 #define S_PF6_DSTATE    18
8991 #define M_PF6_DSTATE    0x7U
8992 #define V_PF6_DSTATE(x) ((x) << S_PF6_DSTATE)
8993 #define G_PF6_DSTATE(x) (((x) >> S_PF6_DSTATE) & M_PF6_DSTATE)
8994 
8995 #define S_PF5_DSTATE    15
8996 #define M_PF5_DSTATE    0x7U
8997 #define V_PF5_DSTATE(x) ((x) << S_PF5_DSTATE)
8998 #define G_PF5_DSTATE(x) (((x) >> S_PF5_DSTATE) & M_PF5_DSTATE)
8999 
9000 #define S_PF4_DSTATE    12
9001 #define M_PF4_DSTATE    0x7U
9002 #define V_PF4_DSTATE(x) ((x) << S_PF4_DSTATE)
9003 #define G_PF4_DSTATE(x) (((x) >> S_PF4_DSTATE) & M_PF4_DSTATE)
9004 
9005 #define S_PF3_DSTATE    9
9006 #define M_PF3_DSTATE    0x7U
9007 #define V_PF3_DSTATE(x) ((x) << S_PF3_DSTATE)
9008 #define G_PF3_DSTATE(x) (((x) >> S_PF3_DSTATE) & M_PF3_DSTATE)
9009 
9010 #define S_PF2_DSTATE    6
9011 #define M_PF2_DSTATE    0x7U
9012 #define V_PF2_DSTATE(x) ((x) << S_PF2_DSTATE)
9013 #define G_PF2_DSTATE(x) (((x) >> S_PF2_DSTATE) & M_PF2_DSTATE)
9014 
9015 #define S_PF1_DSTATE    3
9016 #define M_PF1_DSTATE    0x7U
9017 #define V_PF1_DSTATE(x) ((x) << S_PF1_DSTATE)
9018 #define G_PF1_DSTATE(x) (((x) >> S_PF1_DSTATE) & M_PF1_DSTATE)
9019 
9020 #define S_PF0_DSTATE    0
9021 #define M_PF0_DSTATE    0x7U
9022 #define V_PF0_DSTATE(x) ((x) << S_PF0_DSTATE)
9023 #define G_PF0_DSTATE(x) (((x) >> S_PF0_DSTATE) & M_PF0_DSTATE)
9024 
9025 #define A_PCIE_DEBUG_ADDR_RANGE1 0x5ee0
9026 #define A_PCIE_DEBUG_ADDR_RANGE2 0x5ef0
9027 #define A_PCIE_DEBUG_ADDR_RANGE_CNT 0x5f00
9028 #define A_PCIE_PDEBUG_REG_0X0 0x0
9029 #define A_PCIE_PDEBUG_REG_0X1 0x1
9030 #define A_PCIE_PDEBUG_REG_0X2 0x2
9031 
9032 #define S_TAGQ_CH0_TAGS_USED    11
9033 #define M_TAGQ_CH0_TAGS_USED    0xffU
9034 #define V_TAGQ_CH0_TAGS_USED(x) ((x) << S_TAGQ_CH0_TAGS_USED)
9035 #define G_TAGQ_CH0_TAGS_USED(x) (((x) >> S_TAGQ_CH0_TAGS_USED) & M_TAGQ_CH0_TAGS_USED)
9036 
9037 #define S_REQ_CH0_DATA_EMPTY    10
9038 #define V_REQ_CH0_DATA_EMPTY(x) ((x) << S_REQ_CH0_DATA_EMPTY)
9039 #define F_REQ_CH0_DATA_EMPTY    V_REQ_CH0_DATA_EMPTY(1U)
9040 
9041 #define S_RDQ_CH0_REQ_EMPTY    9
9042 #define V_RDQ_CH0_REQ_EMPTY(x) ((x) << S_RDQ_CH0_REQ_EMPTY)
9043 #define F_RDQ_CH0_REQ_EMPTY    V_RDQ_CH0_REQ_EMPTY(1U)
9044 
9045 #define S_REQ_CTL_RD_CH0_WAIT_FOR_TAGTQ    8
9046 #define V_REQ_CTL_RD_CH0_WAIT_FOR_TAGTQ(x) ((x) << S_REQ_CTL_RD_CH0_WAIT_FOR_TAGTQ)
9047 #define F_REQ_CTL_RD_CH0_WAIT_FOR_TAGTQ    V_REQ_CTL_RD_CH0_WAIT_FOR_TAGTQ(1U)
9048 
9049 #define S_REQ_CTL_RD_CH0_WAIT_FOR_CMD    7
9050 #define V_REQ_CTL_RD_CH0_WAIT_FOR_CMD(x) ((x) << S_REQ_CTL_RD_CH0_WAIT_FOR_CMD)
9051 #define F_REQ_CTL_RD_CH0_WAIT_FOR_CMD    V_REQ_CTL_RD_CH0_WAIT_FOR_CMD(1U)
9052 
9053 #define S_REQ_CTL_RD_CH0_WAIT_FOR_DATA_MEM    6
9054 #define V_REQ_CTL_RD_CH0_WAIT_FOR_DATA_MEM(x) ((x) << S_REQ_CTL_RD_CH0_WAIT_FOR_DATA_MEM)
9055 #define F_REQ_CTL_RD_CH0_WAIT_FOR_DATA_MEM    V_REQ_CTL_RD_CH0_WAIT_FOR_DATA_MEM(1U)
9056 
9057 #define S_REQ_CTL_RD_CH0_WAIT_FOR_RDQ    5
9058 #define V_REQ_CTL_RD_CH0_WAIT_FOR_RDQ(x) ((x) << S_REQ_CTL_RD_CH0_WAIT_FOR_RDQ)
9059 #define F_REQ_CTL_RD_CH0_WAIT_FOR_RDQ    V_REQ_CTL_RD_CH0_WAIT_FOR_RDQ(1U)
9060 
9061 #define S_REQ_CTL_RD_CH0_WAIT_FOR_TXN_DISABLE_FIFO    4
9062 #define V_REQ_CTL_RD_CH0_WAIT_FOR_TXN_DISABLE_FIFO(x) ((x) << S_REQ_CTL_RD_CH0_WAIT_FOR_TXN_DISABLE_FIFO)
9063 #define F_REQ_CTL_RD_CH0_WAIT_FOR_TXN_DISABLE_FIFO    V_REQ_CTL_RD_CH0_WAIT_FOR_TXN_DISABLE_FIFO(1U)
9064 
9065 #define S_REQ_CTL_RD_CH0_EXIT_BOT_VLD_STARTED    3
9066 #define V_REQ_CTL_RD_CH0_EXIT_BOT_VLD_STARTED(x) ((x) << S_REQ_CTL_RD_CH0_EXIT_BOT_VLD_STARTED)
9067 #define F_REQ_CTL_RD_CH0_EXIT_BOT_VLD_STARTED    V_REQ_CTL_RD_CH0_EXIT_BOT_VLD_STARTED(1U)
9068 
9069 #define S_REQ_CTL_RD_CH0_EXIT_TOP_VLD_STARTED    2
9070 #define V_REQ_CTL_RD_CH0_EXIT_TOP_VLD_STARTED(x) ((x) << S_REQ_CTL_RD_CH0_EXIT_TOP_VLD_STARTED)
9071 #define F_REQ_CTL_RD_CH0_EXIT_TOP_VLD_STARTED    V_REQ_CTL_RD_CH0_EXIT_TOP_VLD_STARTED(1U)
9072 
9073 #define S_REQ_CTL_RD_CH0_WAIT_FOR_PAUSE    1
9074 #define V_REQ_CTL_RD_CH0_WAIT_FOR_PAUSE(x) ((x) << S_REQ_CTL_RD_CH0_WAIT_FOR_PAUSE)
9075 #define F_REQ_CTL_RD_CH0_WAIT_FOR_PAUSE    V_REQ_CTL_RD_CH0_WAIT_FOR_PAUSE(1U)
9076 
9077 #define S_REQ_CTL_RD_CH0_WAIT_FOR_FIFO_DATA    0
9078 #define V_REQ_CTL_RD_CH0_WAIT_FOR_FIFO_DATA(x) ((x) << S_REQ_CTL_RD_CH0_WAIT_FOR_FIFO_DATA)
9079 #define F_REQ_CTL_RD_CH0_WAIT_FOR_FIFO_DATA    V_REQ_CTL_RD_CH0_WAIT_FOR_FIFO_DATA(1U)
9080 
9081 #define A_PCIE_PDEBUG_REG_0X3 0x3
9082 
9083 #define S_TAGQ_CH1_TAGS_USED    11
9084 #define M_TAGQ_CH1_TAGS_USED    0xffU
9085 #define V_TAGQ_CH1_TAGS_USED(x) ((x) << S_TAGQ_CH1_TAGS_USED)
9086 #define G_TAGQ_CH1_TAGS_USED(x) (((x) >> S_TAGQ_CH1_TAGS_USED) & M_TAGQ_CH1_TAGS_USED)
9087 
9088 #define S_REQ_CH1_DATA_EMPTY    10
9089 #define V_REQ_CH1_DATA_EMPTY(x) ((x) << S_REQ_CH1_DATA_EMPTY)
9090 #define F_REQ_CH1_DATA_EMPTY    V_REQ_CH1_DATA_EMPTY(1U)
9091 
9092 #define S_RDQ_CH1_REQ_EMPTY    9
9093 #define V_RDQ_CH1_REQ_EMPTY(x) ((x) << S_RDQ_CH1_REQ_EMPTY)
9094 #define F_RDQ_CH1_REQ_EMPTY    V_RDQ_CH1_REQ_EMPTY(1U)
9095 
9096 #define S_REQ_CTL_RD_CH1_WAIT_FOR_TAGTQ    8
9097 #define V_REQ_CTL_RD_CH1_WAIT_FOR_TAGTQ(x) ((x) << S_REQ_CTL_RD_CH1_WAIT_FOR_TAGTQ)
9098 #define F_REQ_CTL_RD_CH1_WAIT_FOR_TAGTQ    V_REQ_CTL_RD_CH1_WAIT_FOR_TAGTQ(1U)
9099 
9100 #define S_REQ_CTL_RD_CH1_WAIT_FOR_CMD    7
9101 #define V_REQ_CTL_RD_CH1_WAIT_FOR_CMD(x) ((x) << S_REQ_CTL_RD_CH1_WAIT_FOR_CMD)
9102 #define F_REQ_CTL_RD_CH1_WAIT_FOR_CMD    V_REQ_CTL_RD_CH1_WAIT_FOR_CMD(1U)
9103 
9104 #define S_REQ_CTL_RD_CH1_WAIT_FOR_DATA_MEM    6
9105 #define V_REQ_CTL_RD_CH1_WAIT_FOR_DATA_MEM(x) ((x) << S_REQ_CTL_RD_CH1_WAIT_FOR_DATA_MEM)
9106 #define F_REQ_CTL_RD_CH1_WAIT_FOR_DATA_MEM    V_REQ_CTL_RD_CH1_WAIT_FOR_DATA_MEM(1U)
9107 
9108 #define S_REQ_CTL_RD_CH1_WAIT_FOR_RDQ    5
9109 #define V_REQ_CTL_RD_CH1_WAIT_FOR_RDQ(x) ((x) << S_REQ_CTL_RD_CH1_WAIT_FOR_RDQ)
9110 #define F_REQ_CTL_RD_CH1_WAIT_FOR_RDQ    V_REQ_CTL_RD_CH1_WAIT_FOR_RDQ(1U)
9111 
9112 #define S_REQ_CTL_RD_CH1_WAIT_FOR_TXN_DISABLE_FIFO    4
9113 #define V_REQ_CTL_RD_CH1_WAIT_FOR_TXN_DISABLE_FIFO(x) ((x) << S_REQ_CTL_RD_CH1_WAIT_FOR_TXN_DISABLE_FIFO)
9114 #define F_REQ_CTL_RD_CH1_WAIT_FOR_TXN_DISABLE_FIFO    V_REQ_CTL_RD_CH1_WAIT_FOR_TXN_DISABLE_FIFO(1U)
9115 
9116 #define S_REQ_CTL_RD_CH1_EXIT_BOT_VLD_STARTED    3
9117 #define V_REQ_CTL_RD_CH1_EXIT_BOT_VLD_STARTED(x) ((x) << S_REQ_CTL_RD_CH1_EXIT_BOT_VLD_STARTED)
9118 #define F_REQ_CTL_RD_CH1_EXIT_BOT_VLD_STARTED    V_REQ_CTL_RD_CH1_EXIT_BOT_VLD_STARTED(1U)
9119 
9120 #define S_REQ_CTL_RD_CH1_EXIT_TOP_VLD_STARTED    2
9121 #define V_REQ_CTL_RD_CH1_EXIT_TOP_VLD_STARTED(x) ((x) << S_REQ_CTL_RD_CH1_EXIT_TOP_VLD_STARTED)
9122 #define F_REQ_CTL_RD_CH1_EXIT_TOP_VLD_STARTED    V_REQ_CTL_RD_CH1_EXIT_TOP_VLD_STARTED(1U)
9123 
9124 #define S_REQ_CTL_RD_CH1_WAIT_FOR_PAUSE    1
9125 #define V_REQ_CTL_RD_CH1_WAIT_FOR_PAUSE(x) ((x) << S_REQ_CTL_RD_CH1_WAIT_FOR_PAUSE)
9126 #define F_REQ_CTL_RD_CH1_WAIT_FOR_PAUSE    V_REQ_CTL_RD_CH1_WAIT_FOR_PAUSE(1U)
9127 
9128 #define S_REQ_CTL_RD_CH1_WAIT_FOR_FIFO_DATA    0
9129 #define V_REQ_CTL_RD_CH1_WAIT_FOR_FIFO_DATA(x) ((x) << S_REQ_CTL_RD_CH1_WAIT_FOR_FIFO_DATA)
9130 #define F_REQ_CTL_RD_CH1_WAIT_FOR_FIFO_DATA    V_REQ_CTL_RD_CH1_WAIT_FOR_FIFO_DATA(1U)
9131 
9132 #define A_PCIE_PDEBUG_REG_0X4 0x4
9133 
9134 #define S_TAGQ_CH2_TAGS_USED    11
9135 #define M_TAGQ_CH2_TAGS_USED    0xffU
9136 #define V_TAGQ_CH2_TAGS_USED(x) ((x) << S_TAGQ_CH2_TAGS_USED)
9137 #define G_TAGQ_CH2_TAGS_USED(x) (((x) >> S_TAGQ_CH2_TAGS_USED) & M_TAGQ_CH2_TAGS_USED)
9138 
9139 #define S_REQ_CH2_DATA_EMPTY    10
9140 #define V_REQ_CH2_DATA_EMPTY(x) ((x) << S_REQ_CH2_DATA_EMPTY)
9141 #define F_REQ_CH2_DATA_EMPTY    V_REQ_CH2_DATA_EMPTY(1U)
9142 
9143 #define S_RDQ_CH2_REQ_EMPTY    9
9144 #define V_RDQ_CH2_REQ_EMPTY(x) ((x) << S_RDQ_CH2_REQ_EMPTY)
9145 #define F_RDQ_CH2_REQ_EMPTY    V_RDQ_CH2_REQ_EMPTY(1U)
9146 
9147 #define S_REQ_CTL_RD_CH2_WAIT_FOR_TAGTQ    8
9148 #define V_REQ_CTL_RD_CH2_WAIT_FOR_TAGTQ(x) ((x) << S_REQ_CTL_RD_CH2_WAIT_FOR_TAGTQ)
9149 #define F_REQ_CTL_RD_CH2_WAIT_FOR_TAGTQ    V_REQ_CTL_RD_CH2_WAIT_FOR_TAGTQ(1U)
9150 
9151 #define S_REQ_CTL_RD_CH2_WAIT_FOR_CMD    7
9152 #define V_REQ_CTL_RD_CH2_WAIT_FOR_CMD(x) ((x) << S_REQ_CTL_RD_CH2_WAIT_FOR_CMD)
9153 #define F_REQ_CTL_RD_CH2_WAIT_FOR_CMD    V_REQ_CTL_RD_CH2_WAIT_FOR_CMD(1U)
9154 
9155 #define S_REQ_CTL_RD_CH2_WAIT_FOR_DATA_MEM    6
9156 #define V_REQ_CTL_RD_CH2_WAIT_FOR_DATA_MEM(x) ((x) << S_REQ_CTL_RD_CH2_WAIT_FOR_DATA_MEM)
9157 #define F_REQ_CTL_RD_CH2_WAIT_FOR_DATA_MEM    V_REQ_CTL_RD_CH2_WAIT_FOR_DATA_MEM(1U)
9158 
9159 #define S_REQ_CTL_RD_CH2_WAIT_FOR_RDQ    5
9160 #define V_REQ_CTL_RD_CH2_WAIT_FOR_RDQ(x) ((x) << S_REQ_CTL_RD_CH2_WAIT_FOR_RDQ)
9161 #define F_REQ_CTL_RD_CH2_WAIT_FOR_RDQ    V_REQ_CTL_RD_CH2_WAIT_FOR_RDQ(1U)
9162 
9163 #define S_REQ_CTL_RD_CH2_WAIT_FOR_TXN_DISABLE_FIFO    4
9164 #define V_REQ_CTL_RD_CH2_WAIT_FOR_TXN_DISABLE_FIFO(x) ((x) << S_REQ_CTL_RD_CH2_WAIT_FOR_TXN_DISABLE_FIFO)
9165 #define F_REQ_CTL_RD_CH2_WAIT_FOR_TXN_DISABLE_FIFO    V_REQ_CTL_RD_CH2_WAIT_FOR_TXN_DISABLE_FIFO(1U)
9166 
9167 #define S_REQ_CTL_RD_CH2_EXIT_BOT_VLD_STARTED    3
9168 #define V_REQ_CTL_RD_CH2_EXIT_BOT_VLD_STARTED(x) ((x) << S_REQ_CTL_RD_CH2_EXIT_BOT_VLD_STARTED)
9169 #define F_REQ_CTL_RD_CH2_EXIT_BOT_VLD_STARTED    V_REQ_CTL_RD_CH2_EXIT_BOT_VLD_STARTED(1U)
9170 
9171 #define S_REQ_CTL_RD_CH2_EXIT_TOP_VLD_STARTED    2
9172 #define V_REQ_CTL_RD_CH2_EXIT_TOP_VLD_STARTED(x) ((x) << S_REQ_CTL_RD_CH2_EXIT_TOP_VLD_STARTED)
9173 #define F_REQ_CTL_RD_CH2_EXIT_TOP_VLD_STARTED    V_REQ_CTL_RD_CH2_EXIT_TOP_VLD_STARTED(1U)
9174 
9175 #define S_REQ_CTL_RD_CH2_WAIT_FOR_PAUSE    1
9176 #define V_REQ_CTL_RD_CH2_WAIT_FOR_PAUSE(x) ((x) << S_REQ_CTL_RD_CH2_WAIT_FOR_PAUSE)
9177 #define F_REQ_CTL_RD_CH2_WAIT_FOR_PAUSE    V_REQ_CTL_RD_CH2_WAIT_FOR_PAUSE(1U)
9178 
9179 #define S_REQ_CTL_RD_CH2_WAIT_FOR_FIFO_DATA    0
9180 #define V_REQ_CTL_RD_CH2_WAIT_FOR_FIFO_DATA(x) ((x) << S_REQ_CTL_RD_CH2_WAIT_FOR_FIFO_DATA)
9181 #define F_REQ_CTL_RD_CH2_WAIT_FOR_FIFO_DATA    V_REQ_CTL_RD_CH2_WAIT_FOR_FIFO_DATA(1U)
9182 
9183 #define A_PCIE_PDEBUG_REG_0X5 0x5
9184 
9185 #define S_TAGQ_CH3_TAGS_USED    11
9186 #define M_TAGQ_CH3_TAGS_USED    0xffU
9187 #define V_TAGQ_CH3_TAGS_USED(x) ((x) << S_TAGQ_CH3_TAGS_USED)
9188 #define G_TAGQ_CH3_TAGS_USED(x) (((x) >> S_TAGQ_CH3_TAGS_USED) & M_TAGQ_CH3_TAGS_USED)
9189 
9190 #define S_REQ_CH3_DATA_EMPTY    10
9191 #define V_REQ_CH3_DATA_EMPTY(x) ((x) << S_REQ_CH3_DATA_EMPTY)
9192 #define F_REQ_CH3_DATA_EMPTY    V_REQ_CH3_DATA_EMPTY(1U)
9193 
9194 #define S_RDQ_CH3_REQ_EMPTY    9
9195 #define V_RDQ_CH3_REQ_EMPTY(x) ((x) << S_RDQ_CH3_REQ_EMPTY)
9196 #define F_RDQ_CH3_REQ_EMPTY    V_RDQ_CH3_REQ_EMPTY(1U)
9197 
9198 #define S_REQ_CTL_RD_CH3_WAIT_FOR_TAGTQ    8
9199 #define V_REQ_CTL_RD_CH3_WAIT_FOR_TAGTQ(x) ((x) << S_REQ_CTL_RD_CH3_WAIT_FOR_TAGTQ)
9200 #define F_REQ_CTL_RD_CH3_WAIT_FOR_TAGTQ    V_REQ_CTL_RD_CH3_WAIT_FOR_TAGTQ(1U)
9201 
9202 #define S_REQ_CTL_RD_CH3_WAIT_FOR_CMD    7
9203 #define V_REQ_CTL_RD_CH3_WAIT_FOR_CMD(x) ((x) << S_REQ_CTL_RD_CH3_WAIT_FOR_CMD)
9204 #define F_REQ_CTL_RD_CH3_WAIT_FOR_CMD    V_REQ_CTL_RD_CH3_WAIT_FOR_CMD(1U)
9205 
9206 #define S_REQ_CTL_RD_CH3_WAIT_FOR_DATA_MEM    6
9207 #define V_REQ_CTL_RD_CH3_WAIT_FOR_DATA_MEM(x) ((x) << S_REQ_CTL_RD_CH3_WAIT_FOR_DATA_MEM)
9208 #define F_REQ_CTL_RD_CH3_WAIT_FOR_DATA_MEM    V_REQ_CTL_RD_CH3_WAIT_FOR_DATA_MEM(1U)
9209 
9210 #define S_REQ_CTL_RD_CH3_WAIT_FOR_RDQ    5
9211 #define V_REQ_CTL_RD_CH3_WAIT_FOR_RDQ(x) ((x) << S_REQ_CTL_RD_CH3_WAIT_FOR_RDQ)
9212 #define F_REQ_CTL_RD_CH3_WAIT_FOR_RDQ    V_REQ_CTL_RD_CH3_WAIT_FOR_RDQ(1U)
9213 
9214 #define S_REQ_CTL_RD_CH3_WAIT_FOR_TXN_DISABLE_FIFO    4
9215 #define V_REQ_CTL_RD_CH3_WAIT_FOR_TXN_DISABLE_FIFO(x) ((x) << S_REQ_CTL_RD_CH3_WAIT_FOR_TXN_DISABLE_FIFO)
9216 #define F_REQ_CTL_RD_CH3_WAIT_FOR_TXN_DISABLE_FIFO    V_REQ_CTL_RD_CH3_WAIT_FOR_TXN_DISABLE_FIFO(1U)
9217 
9218 #define S_REQ_CTL_RD_CH3_EXIT_BOT_VLD_STARTED    3
9219 #define V_REQ_CTL_RD_CH3_EXIT_BOT_VLD_STARTED(x) ((x) << S_REQ_CTL_RD_CH3_EXIT_BOT_VLD_STARTED)
9220 #define F_REQ_CTL_RD_CH3_EXIT_BOT_VLD_STARTED    V_REQ_CTL_RD_CH3_EXIT_BOT_VLD_STARTED(1U)
9221 
9222 #define S_REQ_CTL_RD_CH3_EXIT_TOP_VLD_STARTED    2
9223 #define V_REQ_CTL_RD_CH3_EXIT_TOP_VLD_STARTED(x) ((x) << S_REQ_CTL_RD_CH3_EXIT_TOP_VLD_STARTED)
9224 #define F_REQ_CTL_RD_CH3_EXIT_TOP_VLD_STARTED    V_REQ_CTL_RD_CH3_EXIT_TOP_VLD_STARTED(1U)
9225 
9226 #define S_REQ_CTL_RD_CH3_WAIT_FOR_PAUSE    1
9227 #define V_REQ_CTL_RD_CH3_WAIT_FOR_PAUSE(x) ((x) << S_REQ_CTL_RD_CH3_WAIT_FOR_PAUSE)
9228 #define F_REQ_CTL_RD_CH3_WAIT_FOR_PAUSE    V_REQ_CTL_RD_CH3_WAIT_FOR_PAUSE(1U)
9229 
9230 #define S_REQ_CTL_RD_CH3_WAIT_FOR_FIFO_DATA    0
9231 #define V_REQ_CTL_RD_CH3_WAIT_FOR_FIFO_DATA(x) ((x) << S_REQ_CTL_RD_CH3_WAIT_FOR_FIFO_DATA)
9232 #define F_REQ_CTL_RD_CH3_WAIT_FOR_FIFO_DATA    V_REQ_CTL_RD_CH3_WAIT_FOR_FIFO_DATA(1U)
9233 
9234 #define A_PCIE_PDEBUG_REG_0X6 0x6
9235 
9236 #define S_TAGQ_CH4_TAGS_USED    11
9237 #define M_TAGQ_CH4_TAGS_USED    0xffU
9238 #define V_TAGQ_CH4_TAGS_USED(x) ((x) << S_TAGQ_CH4_TAGS_USED)
9239 #define G_TAGQ_CH4_TAGS_USED(x) (((x) >> S_TAGQ_CH4_TAGS_USED) & M_TAGQ_CH4_TAGS_USED)
9240 
9241 #define S_REQ_CH4_DATA_EMPTY    10
9242 #define V_REQ_CH4_DATA_EMPTY(x) ((x) << S_REQ_CH4_DATA_EMPTY)
9243 #define F_REQ_CH4_DATA_EMPTY    V_REQ_CH4_DATA_EMPTY(1U)
9244 
9245 #define S_RDQ_CH4_REQ_EMPTY    9
9246 #define V_RDQ_CH4_REQ_EMPTY(x) ((x) << S_RDQ_CH4_REQ_EMPTY)
9247 #define F_RDQ_CH4_REQ_EMPTY    V_RDQ_CH4_REQ_EMPTY(1U)
9248 
9249 #define S_REQ_CTL_RD_CH4_WAIT_FOR_TAGTQ    8
9250 #define V_REQ_CTL_RD_CH4_WAIT_FOR_TAGTQ(x) ((x) << S_REQ_CTL_RD_CH4_WAIT_FOR_TAGTQ)
9251 #define F_REQ_CTL_RD_CH4_WAIT_FOR_TAGTQ    V_REQ_CTL_RD_CH4_WAIT_FOR_TAGTQ(1U)
9252 
9253 #define S_REQ_CTL_RD_CH4_WAIT_FOR_CMD    7
9254 #define V_REQ_CTL_RD_CH4_WAIT_FOR_CMD(x) ((x) << S_REQ_CTL_RD_CH4_WAIT_FOR_CMD)
9255 #define F_REQ_CTL_RD_CH4_WAIT_FOR_CMD    V_REQ_CTL_RD_CH4_WAIT_FOR_CMD(1U)
9256 
9257 #define S_REQ_CTL_RD_CH4_WAIT_FOR_DATA_MEM    6
9258 #define V_REQ_CTL_RD_CH4_WAIT_FOR_DATA_MEM(x) ((x) << S_REQ_CTL_RD_CH4_WAIT_FOR_DATA_MEM)
9259 #define F_REQ_CTL_RD_CH4_WAIT_FOR_DATA_MEM    V_REQ_CTL_RD_CH4_WAIT_FOR_DATA_MEM(1U)
9260 
9261 #define S_REQ_CTL_RD_CH4_WAIT_FOR_RDQ    5
9262 #define V_REQ_CTL_RD_CH4_WAIT_FOR_RDQ(x) ((x) << S_REQ_CTL_RD_CH4_WAIT_FOR_RDQ)
9263 #define F_REQ_CTL_RD_CH4_WAIT_FOR_RDQ    V_REQ_CTL_RD_CH4_WAIT_FOR_RDQ(1U)
9264 
9265 #define S_REQ_CTL_RD_CH4_WAIT_FOR_TXN_DISABLE_FIFO    4
9266 #define V_REQ_CTL_RD_CH4_WAIT_FOR_TXN_DISABLE_FIFO(x) ((x) << S_REQ_CTL_RD_CH4_WAIT_FOR_TXN_DISABLE_FIFO)
9267 #define F_REQ_CTL_RD_CH4_WAIT_FOR_TXN_DISABLE_FIFO    V_REQ_CTL_RD_CH4_WAIT_FOR_TXN_DISABLE_FIFO(1U)
9268 
9269 #define S_REQ_CTL_RD_CH4_EXIT_BOT_VLD_STARTED    3
9270 #define V_REQ_CTL_RD_CH4_EXIT_BOT_VLD_STARTED(x) ((x) << S_REQ_CTL_RD_CH4_EXIT_BOT_VLD_STARTED)
9271 #define F_REQ_CTL_RD_CH4_EXIT_BOT_VLD_STARTED    V_REQ_CTL_RD_CH4_EXIT_BOT_VLD_STARTED(1U)
9272 
9273 #define S_REQ_CTL_RD_CH4_EXIT_TOP_VLD_STARTED    2
9274 #define V_REQ_CTL_RD_CH4_EXIT_TOP_VLD_STARTED(x) ((x) << S_REQ_CTL_RD_CH4_EXIT_TOP_VLD_STARTED)
9275 #define F_REQ_CTL_RD_CH4_EXIT_TOP_VLD_STARTED    V_REQ_CTL_RD_CH4_EXIT_TOP_VLD_STARTED(1U)
9276 
9277 #define S_REQ_CTL_RD_CH4_WAIT_FOR_PAUSE    1
9278 #define V_REQ_CTL_RD_CH4_WAIT_FOR_PAUSE(x) ((x) << S_REQ_CTL_RD_CH4_WAIT_FOR_PAUSE)
9279 #define F_REQ_CTL_RD_CH4_WAIT_FOR_PAUSE    V_REQ_CTL_RD_CH4_WAIT_FOR_PAUSE(1U)
9280 
9281 #define S_REQ_CTL_RD_CH4_WAIT_FOR_FIFO_DATA    0
9282 #define V_REQ_CTL_RD_CH4_WAIT_FOR_FIFO_DATA(x) ((x) << S_REQ_CTL_RD_CH4_WAIT_FOR_FIFO_DATA)
9283 #define F_REQ_CTL_RD_CH4_WAIT_FOR_FIFO_DATA    V_REQ_CTL_RD_CH4_WAIT_FOR_FIFO_DATA(1U)
9284 
9285 #define A_PCIE_PDEBUG_REG_0X7 0x7
9286 
9287 #define S_TAGQ_CH5_TAGS_USED    11
9288 #define M_TAGQ_CH5_TAGS_USED    0xffU
9289 #define V_TAGQ_CH5_TAGS_USED(x) ((x) << S_TAGQ_CH5_TAGS_USED)
9290 #define G_TAGQ_CH5_TAGS_USED(x) (((x) >> S_TAGQ_CH5_TAGS_USED) & M_TAGQ_CH5_TAGS_USED)
9291 
9292 #define S_REQ_CH5_DATA_EMPTY    10
9293 #define V_REQ_CH5_DATA_EMPTY(x) ((x) << S_REQ_CH5_DATA_EMPTY)
9294 #define F_REQ_CH5_DATA_EMPTY    V_REQ_CH5_DATA_EMPTY(1U)
9295 
9296 #define S_RDQ_CH5_REQ_EMPTY    9
9297 #define V_RDQ_CH5_REQ_EMPTY(x) ((x) << S_RDQ_CH5_REQ_EMPTY)
9298 #define F_RDQ_CH5_REQ_EMPTY    V_RDQ_CH5_REQ_EMPTY(1U)
9299 
9300 #define S_REQ_CTL_RD_CH5_WAIT_FOR_TAGTQ    8
9301 #define V_REQ_CTL_RD_CH5_WAIT_FOR_TAGTQ(x) ((x) << S_REQ_CTL_RD_CH5_WAIT_FOR_TAGTQ)
9302 #define F_REQ_CTL_RD_CH5_WAIT_FOR_TAGTQ    V_REQ_CTL_RD_CH5_WAIT_FOR_TAGTQ(1U)
9303 
9304 #define S_REQ_CTL_RD_CH5_WAIT_FOR_CMD    7
9305 #define V_REQ_CTL_RD_CH5_WAIT_FOR_CMD(x) ((x) << S_REQ_CTL_RD_CH5_WAIT_FOR_CMD)
9306 #define F_REQ_CTL_RD_CH5_WAIT_FOR_CMD    V_REQ_CTL_RD_CH5_WAIT_FOR_CMD(1U)
9307 
9308 #define S_REQ_CTL_RD_CH5_WAIT_FOR_DATA_MEM    6
9309 #define V_REQ_CTL_RD_CH5_WAIT_FOR_DATA_MEM(x) ((x) << S_REQ_CTL_RD_CH5_WAIT_FOR_DATA_MEM)
9310 #define F_REQ_CTL_RD_CH5_WAIT_FOR_DATA_MEM    V_REQ_CTL_RD_CH5_WAIT_FOR_DATA_MEM(1U)
9311 
9312 #define S_REQ_CTL_RD_CH5_WAIT_FOR_RDQ    5
9313 #define V_REQ_CTL_RD_CH5_WAIT_FOR_RDQ(x) ((x) << S_REQ_CTL_RD_CH5_WAIT_FOR_RDQ)
9314 #define F_REQ_CTL_RD_CH5_WAIT_FOR_RDQ    V_REQ_CTL_RD_CH5_WAIT_FOR_RDQ(1U)
9315 
9316 #define S_REQ_CTL_RD_CH5_WAIT_FOR_TXN_DISABLE_FIFO    4
9317 #define V_REQ_CTL_RD_CH5_WAIT_FOR_TXN_DISABLE_FIFO(x) ((x) << S_REQ_CTL_RD_CH5_WAIT_FOR_TXN_DISABLE_FIFO)
9318 #define F_REQ_CTL_RD_CH5_WAIT_FOR_TXN_DISABLE_FIFO    V_REQ_CTL_RD_CH5_WAIT_FOR_TXN_DISABLE_FIFO(1U)
9319 
9320 #define S_REQ_CTL_RD_CH5_EXIT_BOT_VLD_STARTED    3
9321 #define V_REQ_CTL_RD_CH5_EXIT_BOT_VLD_STARTED(x) ((x) << S_REQ_CTL_RD_CH5_EXIT_BOT_VLD_STARTED)
9322 #define F_REQ_CTL_RD_CH5_EXIT_BOT_VLD_STARTED    V_REQ_CTL_RD_CH5_EXIT_BOT_VLD_STARTED(1U)
9323 
9324 #define S_REQ_CTL_RD_CH5_EXIT_TOP_VLD_STARTED    2
9325 #define V_REQ_CTL_RD_CH5_EXIT_TOP_VLD_STARTED(x) ((x) << S_REQ_CTL_RD_CH5_EXIT_TOP_VLD_STARTED)
9326 #define F_REQ_CTL_RD_CH5_EXIT_TOP_VLD_STARTED    V_REQ_CTL_RD_CH5_EXIT_TOP_VLD_STARTED(1U)
9327 
9328 #define S_REQ_CTL_RD_CH5_WAIT_FOR_PAUSE    1
9329 #define V_REQ_CTL_RD_CH5_WAIT_FOR_PAUSE(x) ((x) << S_REQ_CTL_RD_CH5_WAIT_FOR_PAUSE)
9330 #define F_REQ_CTL_RD_CH5_WAIT_FOR_PAUSE    V_REQ_CTL_RD_CH5_WAIT_FOR_PAUSE(1U)
9331 
9332 #define S_REQ_CTL_RD_CH5_WAIT_FOR_FIFO_DATA    0
9333 #define V_REQ_CTL_RD_CH5_WAIT_FOR_FIFO_DATA(x) ((x) << S_REQ_CTL_RD_CH5_WAIT_FOR_FIFO_DATA)
9334 #define F_REQ_CTL_RD_CH5_WAIT_FOR_FIFO_DATA    V_REQ_CTL_RD_CH5_WAIT_FOR_FIFO_DATA(1U)
9335 
9336 #define A_PCIE_PDEBUG_REG_0X8 0x8
9337 
9338 #define S_TAGQ_CH6_TAGS_USED    11
9339 #define M_TAGQ_CH6_TAGS_USED    0xffU
9340 #define V_TAGQ_CH6_TAGS_USED(x) ((x) << S_TAGQ_CH6_TAGS_USED)
9341 #define G_TAGQ_CH6_TAGS_USED(x) (((x) >> S_TAGQ_CH6_TAGS_USED) & M_TAGQ_CH6_TAGS_USED)
9342 
9343 #define S_REQ_CH6_DATA_EMPTY    10
9344 #define V_REQ_CH6_DATA_EMPTY(x) ((x) << S_REQ_CH6_DATA_EMPTY)
9345 #define F_REQ_CH6_DATA_EMPTY    V_REQ_CH6_DATA_EMPTY(1U)
9346 
9347 #define S_RDQ_CH6_REQ_EMPTY    9
9348 #define V_RDQ_CH6_REQ_EMPTY(x) ((x) << S_RDQ_CH6_REQ_EMPTY)
9349 #define F_RDQ_CH6_REQ_EMPTY    V_RDQ_CH6_REQ_EMPTY(1U)
9350 
9351 #define S_REQ_CTL_RD_CH6_WAIT_FOR_TAGTQ    8
9352 #define V_REQ_CTL_RD_CH6_WAIT_FOR_TAGTQ(x) ((x) << S_REQ_CTL_RD_CH6_WAIT_FOR_TAGTQ)
9353 #define F_REQ_CTL_RD_CH6_WAIT_FOR_TAGTQ    V_REQ_CTL_RD_CH6_WAIT_FOR_TAGTQ(1U)
9354 
9355 #define S_REQ_CTL_RD_CH6_WAIT_FOR_CMD    7
9356 #define V_REQ_CTL_RD_CH6_WAIT_FOR_CMD(x) ((x) << S_REQ_CTL_RD_CH6_WAIT_FOR_CMD)
9357 #define F_REQ_CTL_RD_CH6_WAIT_FOR_CMD    V_REQ_CTL_RD_CH6_WAIT_FOR_CMD(1U)
9358 
9359 #define S_REQ_CTL_RD_CH6_WAIT_FOR_DATA_MEM    6
9360 #define V_REQ_CTL_RD_CH6_WAIT_FOR_DATA_MEM(x) ((x) << S_REQ_CTL_RD_CH6_WAIT_FOR_DATA_MEM)
9361 #define F_REQ_CTL_RD_CH6_WAIT_FOR_DATA_MEM    V_REQ_CTL_RD_CH6_WAIT_FOR_DATA_MEM(1U)
9362 
9363 #define S_REQ_CTL_RD_CH6_WAIT_FOR_RDQ    5
9364 #define V_REQ_CTL_RD_CH6_WAIT_FOR_RDQ(x) ((x) << S_REQ_CTL_RD_CH6_WAIT_FOR_RDQ)
9365 #define F_REQ_CTL_RD_CH6_WAIT_FOR_RDQ    V_REQ_CTL_RD_CH6_WAIT_FOR_RDQ(1U)
9366 
9367 #define S_REQ_CTL_RD_CH6_WAIT_FOR_TXN_DISABLE_FIFO    4
9368 #define V_REQ_CTL_RD_CH6_WAIT_FOR_TXN_DISABLE_FIFO(x) ((x) << S_REQ_CTL_RD_CH6_WAIT_FOR_TXN_DISABLE_FIFO)
9369 #define F_REQ_CTL_RD_CH6_WAIT_FOR_TXN_DISABLE_FIFO    V_REQ_CTL_RD_CH6_WAIT_FOR_TXN_DISABLE_FIFO(1U)
9370 
9371 #define S_REQ_CTL_RD_CH6_EXIT_BOT_VLD_STARTED    3
9372 #define V_REQ_CTL_RD_CH6_EXIT_BOT_VLD_STARTED(x) ((x) << S_REQ_CTL_RD_CH6_EXIT_BOT_VLD_STARTED)
9373 #define F_REQ_CTL_RD_CH6_EXIT_BOT_VLD_STARTED    V_REQ_CTL_RD_CH6_EXIT_BOT_VLD_STARTED(1U)
9374 
9375 #define S_REQ_CTL_RD_CH6_EXIT_TOP_VLD_STARTED    2
9376 #define V_REQ_CTL_RD_CH6_EXIT_TOP_VLD_STARTED(x) ((x) << S_REQ_CTL_RD_CH6_EXIT_TOP_VLD_STARTED)
9377 #define F_REQ_CTL_RD_CH6_EXIT_TOP_VLD_STARTED    V_REQ_CTL_RD_CH6_EXIT_TOP_VLD_STARTED(1U)
9378 
9379 #define S_REQ_CTL_RD_CH6_WAIT_FOR_PAUSE    1
9380 #define V_REQ_CTL_RD_CH6_WAIT_FOR_PAUSE(x) ((x) << S_REQ_CTL_RD_CH6_WAIT_FOR_PAUSE)
9381 #define F_REQ_CTL_RD_CH6_WAIT_FOR_PAUSE    V_REQ_CTL_RD_CH6_WAIT_FOR_PAUSE(1U)
9382 
9383 #define S_REQ_CTL_RD_CH6_WAIT_FOR_FIFO_DATA    0
9384 #define V_REQ_CTL_RD_CH6_WAIT_FOR_FIFO_DATA(x) ((x) << S_REQ_CTL_RD_CH6_WAIT_FOR_FIFO_DATA)
9385 #define F_REQ_CTL_RD_CH6_WAIT_FOR_FIFO_DATA    V_REQ_CTL_RD_CH6_WAIT_FOR_FIFO_DATA(1U)
9386 
9387 #define A_PCIE_PDEBUG_REG_0X9 0x9
9388 
9389 #define S_TAGQ_CH7_TAGS_USED    11
9390 #define M_TAGQ_CH7_TAGS_USED    0xffU
9391 #define V_TAGQ_CH7_TAGS_USED(x) ((x) << S_TAGQ_CH7_TAGS_USED)
9392 #define G_TAGQ_CH7_TAGS_USED(x) (((x) >> S_TAGQ_CH7_TAGS_USED) & M_TAGQ_CH7_TAGS_USED)
9393 
9394 #define S_REQ_CH7_DATA_EMPTY    10
9395 #define V_REQ_CH7_DATA_EMPTY(x) ((x) << S_REQ_CH7_DATA_EMPTY)
9396 #define F_REQ_CH7_DATA_EMPTY    V_REQ_CH7_DATA_EMPTY(1U)
9397 
9398 #define S_RDQ_CH7_REQ_EMPTY    9
9399 #define V_RDQ_CH7_REQ_EMPTY(x) ((x) << S_RDQ_CH7_REQ_EMPTY)
9400 #define F_RDQ_CH7_REQ_EMPTY    V_RDQ_CH7_REQ_EMPTY(1U)
9401 
9402 #define S_REQ_CTL_RD_CH7_WAIT_FOR_TAGTQ    8
9403 #define V_REQ_CTL_RD_CH7_WAIT_FOR_TAGTQ(x) ((x) << S_REQ_CTL_RD_CH7_WAIT_FOR_TAGTQ)
9404 #define F_REQ_CTL_RD_CH7_WAIT_FOR_TAGTQ    V_REQ_CTL_RD_CH7_WAIT_FOR_TAGTQ(1U)
9405 
9406 #define S_REQ_CTL_RD_CH7_WAIT_FOR_CMD    7
9407 #define V_REQ_CTL_RD_CH7_WAIT_FOR_CMD(x) ((x) << S_REQ_CTL_RD_CH7_WAIT_FOR_CMD)
9408 #define F_REQ_CTL_RD_CH7_WAIT_FOR_CMD    V_REQ_CTL_RD_CH7_WAIT_FOR_CMD(1U)
9409 
9410 #define S_REQ_CTL_RD_CH7_WAIT_FOR_DATA_MEM    6
9411 #define V_REQ_CTL_RD_CH7_WAIT_FOR_DATA_MEM(x) ((x) << S_REQ_CTL_RD_CH7_WAIT_FOR_DATA_MEM)
9412 #define F_REQ_CTL_RD_CH7_WAIT_FOR_DATA_MEM    V_REQ_CTL_RD_CH7_WAIT_FOR_DATA_MEM(1U)
9413 
9414 #define S_REQ_CTL_RD_CH7_WAIT_FOR_RDQ    5
9415 #define V_REQ_CTL_RD_CH7_WAIT_FOR_RDQ(x) ((x) << S_REQ_CTL_RD_CH7_WAIT_FOR_RDQ)
9416 #define F_REQ_CTL_RD_CH7_WAIT_FOR_RDQ    V_REQ_CTL_RD_CH7_WAIT_FOR_RDQ(1U)
9417 
9418 #define S_REQ_CTL_RD_CH7_WAIT_FOR_TXN_DISABLE_FIFO    4
9419 #define V_REQ_CTL_RD_CH7_WAIT_FOR_TXN_DISABLE_FIFO(x) ((x) << S_REQ_CTL_RD_CH7_WAIT_FOR_TXN_DISABLE_FIFO)
9420 #define F_REQ_CTL_RD_CH7_WAIT_FOR_TXN_DISABLE_FIFO    V_REQ_CTL_RD_CH7_WAIT_FOR_TXN_DISABLE_FIFO(1U)
9421 
9422 #define S_REQ_CTL_RD_CH7_EXIT_BOT_VLD_STARTED    3
9423 #define V_REQ_CTL_RD_CH7_EXIT_BOT_VLD_STARTED(x) ((x) << S_REQ_CTL_RD_CH7_EXIT_BOT_VLD_STARTED)
9424 #define F_REQ_CTL_RD_CH7_EXIT_BOT_VLD_STARTED    V_REQ_CTL_RD_CH7_EXIT_BOT_VLD_STARTED(1U)
9425 
9426 #define S_REQ_CTL_RD_CH7_EXIT_TOP_VLD_STARTED    2
9427 #define V_REQ_CTL_RD_CH7_EXIT_TOP_VLD_STARTED(x) ((x) << S_REQ_CTL_RD_CH7_EXIT_TOP_VLD_STARTED)
9428 #define F_REQ_CTL_RD_CH7_EXIT_TOP_VLD_STARTED    V_REQ_CTL_RD_CH7_EXIT_TOP_VLD_STARTED(1U)
9429 
9430 #define S_REQ_CTL_RD_CH7_WAIT_FOR_PAUSE    1
9431 #define V_REQ_CTL_RD_CH7_WAIT_FOR_PAUSE(x) ((x) << S_REQ_CTL_RD_CH7_WAIT_FOR_PAUSE)
9432 #define F_REQ_CTL_RD_CH7_WAIT_FOR_PAUSE    V_REQ_CTL_RD_CH7_WAIT_FOR_PAUSE(1U)
9433 
9434 #define S_REQ_CTL_RD_CH7_WAIT_FOR_FIFO_DATA    0
9435 #define V_REQ_CTL_RD_CH7_WAIT_FOR_FIFO_DATA(x) ((x) << S_REQ_CTL_RD_CH7_WAIT_FOR_FIFO_DATA)
9436 #define F_REQ_CTL_RD_CH7_WAIT_FOR_FIFO_DATA    V_REQ_CTL_RD_CH7_WAIT_FOR_FIFO_DATA(1U)
9437 
9438 #define A_PCIE_PDEBUG_REG_0XA 0xa
9439 
9440 #define S_REQ_CTL_RD_CH0_WAIT_FOR_SEQNUM    27
9441 #define V_REQ_CTL_RD_CH0_WAIT_FOR_SEQNUM(x) ((x) << S_REQ_CTL_RD_CH0_WAIT_FOR_SEQNUM)
9442 #define F_REQ_CTL_RD_CH0_WAIT_FOR_SEQNUM    V_REQ_CTL_RD_CH0_WAIT_FOR_SEQNUM(1U)
9443 
9444 #define S_REQ_CTL_WR_CH0_SEQNUM    19
9445 #define M_REQ_CTL_WR_CH0_SEQNUM    0xffU
9446 #define V_REQ_CTL_WR_CH0_SEQNUM(x) ((x) << S_REQ_CTL_WR_CH0_SEQNUM)
9447 #define G_REQ_CTL_WR_CH0_SEQNUM(x) (((x) >> S_REQ_CTL_WR_CH0_SEQNUM) & M_REQ_CTL_WR_CH0_SEQNUM)
9448 
9449 #define S_REQ_CTL_RD_CH0_SEQNUM    11
9450 #define M_REQ_CTL_RD_CH0_SEQNUM    0xffU
9451 #define V_REQ_CTL_RD_CH0_SEQNUM(x) ((x) << S_REQ_CTL_RD_CH0_SEQNUM)
9452 #define G_REQ_CTL_RD_CH0_SEQNUM(x) (((x) >> S_REQ_CTL_RD_CH0_SEQNUM) & M_REQ_CTL_RD_CH0_SEQNUM)
9453 
9454 #define S_REQ_CTL_WR_CH0_WAIT_FOR_SI_FIFO    4
9455 #define V_REQ_CTL_WR_CH0_WAIT_FOR_SI_FIFO(x) ((x) << S_REQ_CTL_WR_CH0_WAIT_FOR_SI_FIFO)
9456 #define F_REQ_CTL_WR_CH0_WAIT_FOR_SI_FIFO    V_REQ_CTL_WR_CH0_WAIT_FOR_SI_FIFO(1U)
9457 
9458 #define S_REQ_CTL_WR_CH0_EXIT_BOT_VLD_STARTED    3
9459 #define V_REQ_CTL_WR_CH0_EXIT_BOT_VLD_STARTED(x) ((x) << S_REQ_CTL_WR_CH0_EXIT_BOT_VLD_STARTED)
9460 #define F_REQ_CTL_WR_CH0_EXIT_BOT_VLD_STARTED    V_REQ_CTL_WR_CH0_EXIT_BOT_VLD_STARTED(1U)
9461 
9462 #define S_REQ_CTL_WR_CH0_EXIT_TOP_VLD_STARTED    2
9463 #define V_REQ_CTL_WR_CH0_EXIT_TOP_VLD_STARTED(x) ((x) << S_REQ_CTL_WR_CH0_EXIT_TOP_VLD_STARTED)
9464 #define F_REQ_CTL_WR_CH0_EXIT_TOP_VLD_STARTED    V_REQ_CTL_WR_CH0_EXIT_TOP_VLD_STARTED(1U)
9465 
9466 #define S_REQ_CTL_WR_CH0_WAIT_FOR_PAUSE    1
9467 #define V_REQ_CTL_WR_CH0_WAIT_FOR_PAUSE(x) ((x) << S_REQ_CTL_WR_CH0_WAIT_FOR_PAUSE)
9468 #define F_REQ_CTL_WR_CH0_WAIT_FOR_PAUSE    V_REQ_CTL_WR_CH0_WAIT_FOR_PAUSE(1U)
9469 
9470 #define S_REQ_CTL_WR_CH0_WAIT_FOR_FIFO_DATA    0
9471 #define V_REQ_CTL_WR_CH0_WAIT_FOR_FIFO_DATA(x) ((x) << S_REQ_CTL_WR_CH0_WAIT_FOR_FIFO_DATA)
9472 #define F_REQ_CTL_WR_CH0_WAIT_FOR_FIFO_DATA    V_REQ_CTL_WR_CH0_WAIT_FOR_FIFO_DATA(1U)
9473 
9474 #define A_PCIE_PDEBUG_REG_0XB 0xb
9475 
9476 #define S_REQ_CTL_RD_CH1_WAIT_FOR_SEQNUM    27
9477 #define V_REQ_CTL_RD_CH1_WAIT_FOR_SEQNUM(x) ((x) << S_REQ_CTL_RD_CH1_WAIT_FOR_SEQNUM)
9478 #define F_REQ_CTL_RD_CH1_WAIT_FOR_SEQNUM    V_REQ_CTL_RD_CH1_WAIT_FOR_SEQNUM(1U)
9479 
9480 #define S_REQ_CTL_WR_CH1_SEQNUM    19
9481 #define M_REQ_CTL_WR_CH1_SEQNUM    0xffU
9482 #define V_REQ_CTL_WR_CH1_SEQNUM(x) ((x) << S_REQ_CTL_WR_CH1_SEQNUM)
9483 #define G_REQ_CTL_WR_CH1_SEQNUM(x) (((x) >> S_REQ_CTL_WR_CH1_SEQNUM) & M_REQ_CTL_WR_CH1_SEQNUM)
9484 
9485 #define S_REQ_CTL_RD_CH1_SEQNUM    11
9486 #define M_REQ_CTL_RD_CH1_SEQNUM    0xffU
9487 #define V_REQ_CTL_RD_CH1_SEQNUM(x) ((x) << S_REQ_CTL_RD_CH1_SEQNUM)
9488 #define G_REQ_CTL_RD_CH1_SEQNUM(x) (((x) >> S_REQ_CTL_RD_CH1_SEQNUM) & M_REQ_CTL_RD_CH1_SEQNUM)
9489 
9490 #define S_REQ_CTL_WR_CH1_WAIT_FOR_SI_FIFO    4
9491 #define V_REQ_CTL_WR_CH1_WAIT_FOR_SI_FIFO(x) ((x) << S_REQ_CTL_WR_CH1_WAIT_FOR_SI_FIFO)
9492 #define F_REQ_CTL_WR_CH1_WAIT_FOR_SI_FIFO    V_REQ_CTL_WR_CH1_WAIT_FOR_SI_FIFO(1U)
9493 
9494 #define S_REQ_CTL_WR_CH1_EXIT_BOT_VLD_STARTED    3
9495 #define V_REQ_CTL_WR_CH1_EXIT_BOT_VLD_STARTED(x) ((x) << S_REQ_CTL_WR_CH1_EXIT_BOT_VLD_STARTED)
9496 #define F_REQ_CTL_WR_CH1_EXIT_BOT_VLD_STARTED    V_REQ_CTL_WR_CH1_EXIT_BOT_VLD_STARTED(1U)
9497 
9498 #define S_REQ_CTL_WR_CH1_EXIT_TOP_VLD_STARTED    2
9499 #define V_REQ_CTL_WR_CH1_EXIT_TOP_VLD_STARTED(x) ((x) << S_REQ_CTL_WR_CH1_EXIT_TOP_VLD_STARTED)
9500 #define F_REQ_CTL_WR_CH1_EXIT_TOP_VLD_STARTED    V_REQ_CTL_WR_CH1_EXIT_TOP_VLD_STARTED(1U)
9501 
9502 #define S_REQ_CTL_WR_CH1_WAIT_FOR_PAUSE    1
9503 #define V_REQ_CTL_WR_CH1_WAIT_FOR_PAUSE(x) ((x) << S_REQ_CTL_WR_CH1_WAIT_FOR_PAUSE)
9504 #define F_REQ_CTL_WR_CH1_WAIT_FOR_PAUSE    V_REQ_CTL_WR_CH1_WAIT_FOR_PAUSE(1U)
9505 
9506 #define S_REQ_CTL_WR_CH1_WAIT_FOR_FIFO_DATA    0
9507 #define V_REQ_CTL_WR_CH1_WAIT_FOR_FIFO_DATA(x) ((x) << S_REQ_CTL_WR_CH1_WAIT_FOR_FIFO_DATA)
9508 #define F_REQ_CTL_WR_CH1_WAIT_FOR_FIFO_DATA    V_REQ_CTL_WR_CH1_WAIT_FOR_FIFO_DATA(1U)
9509 
9510 #define A_PCIE_PDEBUG_REG_0XC 0xc
9511 
9512 #define S_REQ_CTL_RD_CH2_WAIT_FOR_SEQNUM    27
9513 #define V_REQ_CTL_RD_CH2_WAIT_FOR_SEQNUM(x) ((x) << S_REQ_CTL_RD_CH2_WAIT_FOR_SEQNUM)
9514 #define F_REQ_CTL_RD_CH2_WAIT_FOR_SEQNUM    V_REQ_CTL_RD_CH2_WAIT_FOR_SEQNUM(1U)
9515 
9516 #define S_REQ_CTL_WR_CH2_SEQNUM    19
9517 #define M_REQ_CTL_WR_CH2_SEQNUM    0xffU
9518 #define V_REQ_CTL_WR_CH2_SEQNUM(x) ((x) << S_REQ_CTL_WR_CH2_SEQNUM)
9519 #define G_REQ_CTL_WR_CH2_SEQNUM(x) (((x) >> S_REQ_CTL_WR_CH2_SEQNUM) & M_REQ_CTL_WR_CH2_SEQNUM)
9520 
9521 #define S_REQ_CTL_RD_CH2_SEQNUM    11
9522 #define M_REQ_CTL_RD_CH2_SEQNUM    0xffU
9523 #define V_REQ_CTL_RD_CH2_SEQNUM(x) ((x) << S_REQ_CTL_RD_CH2_SEQNUM)
9524 #define G_REQ_CTL_RD_CH2_SEQNUM(x) (((x) >> S_REQ_CTL_RD_CH2_SEQNUM) & M_REQ_CTL_RD_CH2_SEQNUM)
9525 
9526 #define S_REQ_CTL_WR_CH2_WAIT_FOR_SI_FIFO    4
9527 #define V_REQ_CTL_WR_CH2_WAIT_FOR_SI_FIFO(x) ((x) << S_REQ_CTL_WR_CH2_WAIT_FOR_SI_FIFO)
9528 #define F_REQ_CTL_WR_CH2_WAIT_FOR_SI_FIFO    V_REQ_CTL_WR_CH2_WAIT_FOR_SI_FIFO(1U)
9529 
9530 #define S_REQ_CTL_WR_CH2_EXIT_BOT_VLD_STARTED    3
9531 #define V_REQ_CTL_WR_CH2_EXIT_BOT_VLD_STARTED(x) ((x) << S_REQ_CTL_WR_CH2_EXIT_BOT_VLD_STARTED)
9532 #define F_REQ_CTL_WR_CH2_EXIT_BOT_VLD_STARTED    V_REQ_CTL_WR_CH2_EXIT_BOT_VLD_STARTED(1U)
9533 
9534 #define S_REQ_CTL_WR_CH2_EXIT_TOP_VLD_STARTED    2
9535 #define V_REQ_CTL_WR_CH2_EXIT_TOP_VLD_STARTED(x) ((x) << S_REQ_CTL_WR_CH2_EXIT_TOP_VLD_STARTED)
9536 #define F_REQ_CTL_WR_CH2_EXIT_TOP_VLD_STARTED    V_REQ_CTL_WR_CH2_EXIT_TOP_VLD_STARTED(1U)
9537 
9538 #define S_REQ_CTL_WR_CH2_WAIT_FOR_PAUSE    1
9539 #define V_REQ_CTL_WR_CH2_WAIT_FOR_PAUSE(x) ((x) << S_REQ_CTL_WR_CH2_WAIT_FOR_PAUSE)
9540 #define F_REQ_CTL_WR_CH2_WAIT_FOR_PAUSE    V_REQ_CTL_WR_CH2_WAIT_FOR_PAUSE(1U)
9541 
9542 #define S_REQ_CTL_WR_CH2_WAIT_FOR_FIFO_DATA    0
9543 #define V_REQ_CTL_WR_CH2_WAIT_FOR_FIFO_DATA(x) ((x) << S_REQ_CTL_WR_CH2_WAIT_FOR_FIFO_DATA)
9544 #define F_REQ_CTL_WR_CH2_WAIT_FOR_FIFO_DATA    V_REQ_CTL_WR_CH2_WAIT_FOR_FIFO_DATA(1U)
9545 
9546 #define A_PCIE_PDEBUG_REG_0XD 0xd
9547 
9548 #define S_REQ_CTL_RD_CH3_WAIT_FOR_SEQNUM    27
9549 #define V_REQ_CTL_RD_CH3_WAIT_FOR_SEQNUM(x) ((x) << S_REQ_CTL_RD_CH3_WAIT_FOR_SEQNUM)
9550 #define F_REQ_CTL_RD_CH3_WAIT_FOR_SEQNUM    V_REQ_CTL_RD_CH3_WAIT_FOR_SEQNUM(1U)
9551 
9552 #define S_REQ_CTL_WR_CH3_SEQNUM    19
9553 #define M_REQ_CTL_WR_CH3_SEQNUM    0xffU
9554 #define V_REQ_CTL_WR_CH3_SEQNUM(x) ((x) << S_REQ_CTL_WR_CH3_SEQNUM)
9555 #define G_REQ_CTL_WR_CH3_SEQNUM(x) (((x) >> S_REQ_CTL_WR_CH3_SEQNUM) & M_REQ_CTL_WR_CH3_SEQNUM)
9556 
9557 #define S_REQ_CTL_RD_CH3_SEQNUM    11
9558 #define M_REQ_CTL_RD_CH3_SEQNUM    0xffU
9559 #define V_REQ_CTL_RD_CH3_SEQNUM(x) ((x) << S_REQ_CTL_RD_CH3_SEQNUM)
9560 #define G_REQ_CTL_RD_CH3_SEQNUM(x) (((x) >> S_REQ_CTL_RD_CH3_SEQNUM) & M_REQ_CTL_RD_CH3_SEQNUM)
9561 
9562 #define S_REQ_CTL_WR_CH3_WAIT_FOR_SI_FIFO    4
9563 #define V_REQ_CTL_WR_CH3_WAIT_FOR_SI_FIFO(x) ((x) << S_REQ_CTL_WR_CH3_WAIT_FOR_SI_FIFO)
9564 #define F_REQ_CTL_WR_CH3_WAIT_FOR_SI_FIFO    V_REQ_CTL_WR_CH3_WAIT_FOR_SI_FIFO(1U)
9565 
9566 #define S_REQ_CTL_WR_CH3_EXIT_BOT_VLD_STARTED    3
9567 #define V_REQ_CTL_WR_CH3_EXIT_BOT_VLD_STARTED(x) ((x) << S_REQ_CTL_WR_CH3_EXIT_BOT_VLD_STARTED)
9568 #define F_REQ_CTL_WR_CH3_EXIT_BOT_VLD_STARTED    V_REQ_CTL_WR_CH3_EXIT_BOT_VLD_STARTED(1U)
9569 
9570 #define S_REQ_CTL_WR_CH3_EXIT_TOP_VLD_STARTED    2
9571 #define V_REQ_CTL_WR_CH3_EXIT_TOP_VLD_STARTED(x) ((x) << S_REQ_CTL_WR_CH3_EXIT_TOP_VLD_STARTED)
9572 #define F_REQ_CTL_WR_CH3_EXIT_TOP_VLD_STARTED    V_REQ_CTL_WR_CH3_EXIT_TOP_VLD_STARTED(1U)
9573 
9574 #define S_REQ_CTL_WR_CH3_WAIT_FOR_PAUSE    1
9575 #define V_REQ_CTL_WR_CH3_WAIT_FOR_PAUSE(x) ((x) << S_REQ_CTL_WR_CH3_WAIT_FOR_PAUSE)
9576 #define F_REQ_CTL_WR_CH3_WAIT_FOR_PAUSE    V_REQ_CTL_WR_CH3_WAIT_FOR_PAUSE(1U)
9577 
9578 #define S_REQ_CTL_WR_CH3_WAIT_FOR_FIFO_DATA    0
9579 #define V_REQ_CTL_WR_CH3_WAIT_FOR_FIFO_DATA(x) ((x) << S_REQ_CTL_WR_CH3_WAIT_FOR_FIFO_DATA)
9580 #define F_REQ_CTL_WR_CH3_WAIT_FOR_FIFO_DATA    V_REQ_CTL_WR_CH3_WAIT_FOR_FIFO_DATA(1U)
9581 
9582 #define A_PCIE_PDEBUG_REG_0XE 0xe
9583 
9584 #define S_REQ_CTL_RD_CH4_WAIT_FOR_SEQNUM    27
9585 #define V_REQ_CTL_RD_CH4_WAIT_FOR_SEQNUM(x) ((x) << S_REQ_CTL_RD_CH4_WAIT_FOR_SEQNUM)
9586 #define F_REQ_CTL_RD_CH4_WAIT_FOR_SEQNUM    V_REQ_CTL_RD_CH4_WAIT_FOR_SEQNUM(1U)
9587 
9588 #define S_REQ_CTL_WR_CH4_SEQNUM    19
9589 #define M_REQ_CTL_WR_CH4_SEQNUM    0xffU
9590 #define V_REQ_CTL_WR_CH4_SEQNUM(x) ((x) << S_REQ_CTL_WR_CH4_SEQNUM)
9591 #define G_REQ_CTL_WR_CH4_SEQNUM(x) (((x) >> S_REQ_CTL_WR_CH4_SEQNUM) & M_REQ_CTL_WR_CH4_SEQNUM)
9592 
9593 #define S_REQ_CTL_RD_CH4_SEQNUM    11
9594 #define M_REQ_CTL_RD_CH4_SEQNUM    0xffU
9595 #define V_REQ_CTL_RD_CH4_SEQNUM(x) ((x) << S_REQ_CTL_RD_CH4_SEQNUM)
9596 #define G_REQ_CTL_RD_CH4_SEQNUM(x) (((x) >> S_REQ_CTL_RD_CH4_SEQNUM) & M_REQ_CTL_RD_CH4_SEQNUM)
9597 
9598 #define S_REQ_CTL_WR_CH4_WAIT_FOR_SI_FIFO    4
9599 #define V_REQ_CTL_WR_CH4_WAIT_FOR_SI_FIFO(x) ((x) << S_REQ_CTL_WR_CH4_WAIT_FOR_SI_FIFO)
9600 #define F_REQ_CTL_WR_CH4_WAIT_FOR_SI_FIFO    V_REQ_CTL_WR_CH4_WAIT_FOR_SI_FIFO(1U)
9601 
9602 #define S_REQ_CTL_WR_CH4_EXIT_BOT_VLD_STARTED    3
9603 #define V_REQ_CTL_WR_CH4_EXIT_BOT_VLD_STARTED(x) ((x) << S_REQ_CTL_WR_CH4_EXIT_BOT_VLD_STARTED)
9604 #define F_REQ_CTL_WR_CH4_EXIT_BOT_VLD_STARTED    V_REQ_CTL_WR_CH4_EXIT_BOT_VLD_STARTED(1U)
9605 
9606 #define S_REQ_CTL_WR_CH4_EXIT_TOP_VLD_STARTED    2
9607 #define V_REQ_CTL_WR_CH4_EXIT_TOP_VLD_STARTED(x) ((x) << S_REQ_CTL_WR_CH4_EXIT_TOP_VLD_STARTED)
9608 #define F_REQ_CTL_WR_CH4_EXIT_TOP_VLD_STARTED    V_REQ_CTL_WR_CH4_EXIT_TOP_VLD_STARTED(1U)
9609 
9610 #define S_REQ_CTL_WR_CH4_WAIT_FOR_PAUSE    1
9611 #define V_REQ_CTL_WR_CH4_WAIT_FOR_PAUSE(x) ((x) << S_REQ_CTL_WR_CH4_WAIT_FOR_PAUSE)
9612 #define F_REQ_CTL_WR_CH4_WAIT_FOR_PAUSE    V_REQ_CTL_WR_CH4_WAIT_FOR_PAUSE(1U)
9613 
9614 #define S_REQ_CTL_WR_CH4_WAIT_FOR_FIFO_DATA    0
9615 #define V_REQ_CTL_WR_CH4_WAIT_FOR_FIFO_DATA(x) ((x) << S_REQ_CTL_WR_CH4_WAIT_FOR_FIFO_DATA)
9616 #define F_REQ_CTL_WR_CH4_WAIT_FOR_FIFO_DATA    V_REQ_CTL_WR_CH4_WAIT_FOR_FIFO_DATA(1U)
9617 
9618 #define A_PCIE_PDEBUG_REG_0XF 0xf
9619 #define A_PCIE_PDEBUG_REG_0X10 0x10
9620 
9621 #define S_PIPE0_TX3_DATAK_0    31
9622 #define V_PIPE0_TX3_DATAK_0(x) ((x) << S_PIPE0_TX3_DATAK_0)
9623 #define F_PIPE0_TX3_DATAK_0    V_PIPE0_TX3_DATAK_0(1U)
9624 
9625 #define S_PIPE0_TX3_DATA_6_0    24
9626 #define M_PIPE0_TX3_DATA_6_0    0x7fU
9627 #define V_PIPE0_TX3_DATA_6_0(x) ((x) << S_PIPE0_TX3_DATA_6_0)
9628 #define G_PIPE0_TX3_DATA_6_0(x) (((x) >> S_PIPE0_TX3_DATA_6_0) & M_PIPE0_TX3_DATA_6_0)
9629 
9630 #define S_PIPE0_TX2_DATA_7_0    16
9631 #define M_PIPE0_TX2_DATA_7_0    0xffU
9632 #define V_PIPE0_TX2_DATA_7_0(x) ((x) << S_PIPE0_TX2_DATA_7_0)
9633 #define G_PIPE0_TX2_DATA_7_0(x) (((x) >> S_PIPE0_TX2_DATA_7_0) & M_PIPE0_TX2_DATA_7_0)
9634 
9635 #define S_PIPE0_TX1_DATA_7_0    8
9636 #define M_PIPE0_TX1_DATA_7_0    0xffU
9637 #define V_PIPE0_TX1_DATA_7_0(x) ((x) << S_PIPE0_TX1_DATA_7_0)
9638 #define G_PIPE0_TX1_DATA_7_0(x) (((x) >> S_PIPE0_TX1_DATA_7_0) & M_PIPE0_TX1_DATA_7_0)
9639 
9640 #define S_PIPE0_TX0_DATAK_0    7
9641 #define V_PIPE0_TX0_DATAK_0(x) ((x) << S_PIPE0_TX0_DATAK_0)
9642 #define F_PIPE0_TX0_DATAK_0    V_PIPE0_TX0_DATAK_0(1U)
9643 
9644 #define S_PIPE0_TX0_DATA_6_0    0
9645 #define M_PIPE0_TX0_DATA_6_0    0x7fU
9646 #define V_PIPE0_TX0_DATA_6_0(x) ((x) << S_PIPE0_TX0_DATA_6_0)
9647 #define G_PIPE0_TX0_DATA_6_0(x) (((x) >> S_PIPE0_TX0_DATA_6_0) & M_PIPE0_TX0_DATA_6_0)
9648 
9649 #define A_PCIE_PDEBUG_REG_0X11 0x11
9650 
9651 #define S_PIPE0_TX3_DATAK_1    31
9652 #define V_PIPE0_TX3_DATAK_1(x) ((x) << S_PIPE0_TX3_DATAK_1)
9653 #define F_PIPE0_TX3_DATAK_1    V_PIPE0_TX3_DATAK_1(1U)
9654 
9655 #define S_PIPE0_TX3_DATA_14_8    24
9656 #define M_PIPE0_TX3_DATA_14_8    0x7fU
9657 #define V_PIPE0_TX3_DATA_14_8(x) ((x) << S_PIPE0_TX3_DATA_14_8)
9658 #define G_PIPE0_TX3_DATA_14_8(x) (((x) >> S_PIPE0_TX3_DATA_14_8) & M_PIPE0_TX3_DATA_14_8)
9659 
9660 #define S_PIPE0_TX2_DATA_15_8    16
9661 #define M_PIPE0_TX2_DATA_15_8    0xffU
9662 #define V_PIPE0_TX2_DATA_15_8(x) ((x) << S_PIPE0_TX2_DATA_15_8)
9663 #define G_PIPE0_TX2_DATA_15_8(x) (((x) >> S_PIPE0_TX2_DATA_15_8) & M_PIPE0_TX2_DATA_15_8)
9664 
9665 #define S_PIPE0_TX1_DATA_15_8    8
9666 #define M_PIPE0_TX1_DATA_15_8    0xffU
9667 #define V_PIPE0_TX1_DATA_15_8(x) ((x) << S_PIPE0_TX1_DATA_15_8)
9668 #define G_PIPE0_TX1_DATA_15_8(x) (((x) >> S_PIPE0_TX1_DATA_15_8) & M_PIPE0_TX1_DATA_15_8)
9669 
9670 #define S_PIPE0_TX0_DATAK_1    7
9671 #define V_PIPE0_TX0_DATAK_1(x) ((x) << S_PIPE0_TX0_DATAK_1)
9672 #define F_PIPE0_TX0_DATAK_1    V_PIPE0_TX0_DATAK_1(1U)
9673 
9674 #define S_PIPE0_TX0_DATA_14_8    0
9675 #define M_PIPE0_TX0_DATA_14_8    0x7fU
9676 #define V_PIPE0_TX0_DATA_14_8(x) ((x) << S_PIPE0_TX0_DATA_14_8)
9677 #define G_PIPE0_TX0_DATA_14_8(x) (((x) >> S_PIPE0_TX0_DATA_14_8) & M_PIPE0_TX0_DATA_14_8)
9678 
9679 #define A_PCIE_PDEBUG_REG_0X12 0x12
9680 
9681 #define S_PIPE0_TX7_DATAK_0    31
9682 #define V_PIPE0_TX7_DATAK_0(x) ((x) << S_PIPE0_TX7_DATAK_0)
9683 #define F_PIPE0_TX7_DATAK_0    V_PIPE0_TX7_DATAK_0(1U)
9684 
9685 #define S_PIPE0_TX7_DATA_6_0    24
9686 #define M_PIPE0_TX7_DATA_6_0    0x7fU
9687 #define V_PIPE0_TX7_DATA_6_0(x) ((x) << S_PIPE0_TX7_DATA_6_0)
9688 #define G_PIPE0_TX7_DATA_6_0(x) (((x) >> S_PIPE0_TX7_DATA_6_0) & M_PIPE0_TX7_DATA_6_0)
9689 
9690 #define S_PIPE0_TX6_DATA_7_0    16
9691 #define M_PIPE0_TX6_DATA_7_0    0xffU
9692 #define V_PIPE0_TX6_DATA_7_0(x) ((x) << S_PIPE0_TX6_DATA_7_0)
9693 #define G_PIPE0_TX6_DATA_7_0(x) (((x) >> S_PIPE0_TX6_DATA_7_0) & M_PIPE0_TX6_DATA_7_0)
9694 
9695 #define S_PIPE0_TX5_DATA_7_0    8
9696 #define M_PIPE0_TX5_DATA_7_0    0xffU
9697 #define V_PIPE0_TX5_DATA_7_0(x) ((x) << S_PIPE0_TX5_DATA_7_0)
9698 #define G_PIPE0_TX5_DATA_7_0(x) (((x) >> S_PIPE0_TX5_DATA_7_0) & M_PIPE0_TX5_DATA_7_0)
9699 
9700 #define S_PIPE0_TX4_DATAK_0    7
9701 #define V_PIPE0_TX4_DATAK_0(x) ((x) << S_PIPE0_TX4_DATAK_0)
9702 #define F_PIPE0_TX4_DATAK_0    V_PIPE0_TX4_DATAK_0(1U)
9703 
9704 #define S_PIPE0_TX4_DATA_6_0    0
9705 #define M_PIPE0_TX4_DATA_6_0    0x7fU
9706 #define V_PIPE0_TX4_DATA_6_0(x) ((x) << S_PIPE0_TX4_DATA_6_0)
9707 #define G_PIPE0_TX4_DATA_6_0(x) (((x) >> S_PIPE0_TX4_DATA_6_0) & M_PIPE0_TX4_DATA_6_0)
9708 
9709 #define A_PCIE_PDEBUG_REG_0X13 0x13
9710 
9711 #define S_PIPE0_TX7_DATAK_1    31
9712 #define V_PIPE0_TX7_DATAK_1(x) ((x) << S_PIPE0_TX7_DATAK_1)
9713 #define F_PIPE0_TX7_DATAK_1    V_PIPE0_TX7_DATAK_1(1U)
9714 
9715 #define S_PIPE0_TX7_DATA_14_8    24
9716 #define M_PIPE0_TX7_DATA_14_8    0x7fU
9717 #define V_PIPE0_TX7_DATA_14_8(x) ((x) << S_PIPE0_TX7_DATA_14_8)
9718 #define G_PIPE0_TX7_DATA_14_8(x) (((x) >> S_PIPE0_TX7_DATA_14_8) & M_PIPE0_TX7_DATA_14_8)
9719 
9720 #define S_PIPE0_TX6_DATA_15_8    16
9721 #define M_PIPE0_TX6_DATA_15_8    0xffU
9722 #define V_PIPE0_TX6_DATA_15_8(x) ((x) << S_PIPE0_TX6_DATA_15_8)
9723 #define G_PIPE0_TX6_DATA_15_8(x) (((x) >> S_PIPE0_TX6_DATA_15_8) & M_PIPE0_TX6_DATA_15_8)
9724 
9725 #define S_PIPE0_TX5_DATA_15_8    8
9726 #define M_PIPE0_TX5_DATA_15_8    0xffU
9727 #define V_PIPE0_TX5_DATA_15_8(x) ((x) << S_PIPE0_TX5_DATA_15_8)
9728 #define G_PIPE0_TX5_DATA_15_8(x) (((x) >> S_PIPE0_TX5_DATA_15_8) & M_PIPE0_TX5_DATA_15_8)
9729 
9730 #define S_PIPE0_TX4_DATAK_1    7
9731 #define V_PIPE0_TX4_DATAK_1(x) ((x) << S_PIPE0_TX4_DATAK_1)
9732 #define F_PIPE0_TX4_DATAK_1    V_PIPE0_TX4_DATAK_1(1U)
9733 
9734 #define S_PIPE0_TX4_DATA_14_8    0
9735 #define M_PIPE0_TX4_DATA_14_8    0x7fU
9736 #define V_PIPE0_TX4_DATA_14_8(x) ((x) << S_PIPE0_TX4_DATA_14_8)
9737 #define G_PIPE0_TX4_DATA_14_8(x) (((x) >> S_PIPE0_TX4_DATA_14_8) & M_PIPE0_TX4_DATA_14_8)
9738 
9739 #define A_PCIE_PDEBUG_REG_0X14 0x14
9740 
9741 #define S_PIPE0_RX3_VALID_14    31
9742 #define V_PIPE0_RX3_VALID_14(x) ((x) << S_PIPE0_RX3_VALID_14)
9743 #define F_PIPE0_RX3_VALID_14    V_PIPE0_RX3_VALID_14(1U)
9744 
9745 #define S_PIPE0_RX3_VALID2_14    24
9746 #define M_PIPE0_RX3_VALID2_14    0x7fU
9747 #define V_PIPE0_RX3_VALID2_14(x) ((x) << S_PIPE0_RX3_VALID2_14)
9748 #define G_PIPE0_RX3_VALID2_14(x) (((x) >> S_PIPE0_RX3_VALID2_14) & M_PIPE0_RX3_VALID2_14)
9749 
9750 #define S_PIPE0_RX2_VALID_14    16
9751 #define M_PIPE0_RX2_VALID_14    0xffU
9752 #define V_PIPE0_RX2_VALID_14(x) ((x) << S_PIPE0_RX2_VALID_14)
9753 #define G_PIPE0_RX2_VALID_14(x) (((x) >> S_PIPE0_RX2_VALID_14) & M_PIPE0_RX2_VALID_14)
9754 
9755 #define S_PIPE0_RX1_VALID_14    8
9756 #define M_PIPE0_RX1_VALID_14    0xffU
9757 #define V_PIPE0_RX1_VALID_14(x) ((x) << S_PIPE0_RX1_VALID_14)
9758 #define G_PIPE0_RX1_VALID_14(x) (((x) >> S_PIPE0_RX1_VALID_14) & M_PIPE0_RX1_VALID_14)
9759 
9760 #define S_PIPE0_RX0_VALID_14    7
9761 #define V_PIPE0_RX0_VALID_14(x) ((x) << S_PIPE0_RX0_VALID_14)
9762 #define F_PIPE0_RX0_VALID_14    V_PIPE0_RX0_VALID_14(1U)
9763 
9764 #define S_PIPE0_RX0_VALID2_14    0
9765 #define M_PIPE0_RX0_VALID2_14    0x7fU
9766 #define V_PIPE0_RX0_VALID2_14(x) ((x) << S_PIPE0_RX0_VALID2_14)
9767 #define G_PIPE0_RX0_VALID2_14(x) (((x) >> S_PIPE0_RX0_VALID2_14) & M_PIPE0_RX0_VALID2_14)
9768 
9769 #define A_PCIE_PDEBUG_REG_0X15 0x15
9770 
9771 #define S_PIPE0_RX3_VALID_15    31
9772 #define V_PIPE0_RX3_VALID_15(x) ((x) << S_PIPE0_RX3_VALID_15)
9773 #define F_PIPE0_RX3_VALID_15    V_PIPE0_RX3_VALID_15(1U)
9774 
9775 #define S_PIPE0_RX3_VALID2_15    24
9776 #define M_PIPE0_RX3_VALID2_15    0x7fU
9777 #define V_PIPE0_RX3_VALID2_15(x) ((x) << S_PIPE0_RX3_VALID2_15)
9778 #define G_PIPE0_RX3_VALID2_15(x) (((x) >> S_PIPE0_RX3_VALID2_15) & M_PIPE0_RX3_VALID2_15)
9779 
9780 #define S_PIPE0_RX2_VALID_15    16
9781 #define M_PIPE0_RX2_VALID_15    0xffU
9782 #define V_PIPE0_RX2_VALID_15(x) ((x) << S_PIPE0_RX2_VALID_15)
9783 #define G_PIPE0_RX2_VALID_15(x) (((x) >> S_PIPE0_RX2_VALID_15) & M_PIPE0_RX2_VALID_15)
9784 
9785 #define S_PIPE0_RX1_VALID_15    8
9786 #define M_PIPE0_RX1_VALID_15    0xffU
9787 #define V_PIPE0_RX1_VALID_15(x) ((x) << S_PIPE0_RX1_VALID_15)
9788 #define G_PIPE0_RX1_VALID_15(x) (((x) >> S_PIPE0_RX1_VALID_15) & M_PIPE0_RX1_VALID_15)
9789 
9790 #define S_PIPE0_RX0_VALID_15    7
9791 #define V_PIPE0_RX0_VALID_15(x) ((x) << S_PIPE0_RX0_VALID_15)
9792 #define F_PIPE0_RX0_VALID_15    V_PIPE0_RX0_VALID_15(1U)
9793 
9794 #define S_PIPE0_RX0_VALID2_15    0
9795 #define M_PIPE0_RX0_VALID2_15    0x7fU
9796 #define V_PIPE0_RX0_VALID2_15(x) ((x) << S_PIPE0_RX0_VALID2_15)
9797 #define G_PIPE0_RX0_VALID2_15(x) (((x) >> S_PIPE0_RX0_VALID2_15) & M_PIPE0_RX0_VALID2_15)
9798 
9799 #define A_PCIE_PDEBUG_REG_0X16 0x16
9800 
9801 #define S_PIPE0_RX7_VALID_16    31
9802 #define V_PIPE0_RX7_VALID_16(x) ((x) << S_PIPE0_RX7_VALID_16)
9803 #define F_PIPE0_RX7_VALID_16    V_PIPE0_RX7_VALID_16(1U)
9804 
9805 #define S_PIPE0_RX7_VALID2_16    24
9806 #define M_PIPE0_RX7_VALID2_16    0x7fU
9807 #define V_PIPE0_RX7_VALID2_16(x) ((x) << S_PIPE0_RX7_VALID2_16)
9808 #define G_PIPE0_RX7_VALID2_16(x) (((x) >> S_PIPE0_RX7_VALID2_16) & M_PIPE0_RX7_VALID2_16)
9809 
9810 #define S_PIPE0_RX6_VALID_16    16
9811 #define M_PIPE0_RX6_VALID_16    0xffU
9812 #define V_PIPE0_RX6_VALID_16(x) ((x) << S_PIPE0_RX6_VALID_16)
9813 #define G_PIPE0_RX6_VALID_16(x) (((x) >> S_PIPE0_RX6_VALID_16) & M_PIPE0_RX6_VALID_16)
9814 
9815 #define S_PIPE0_RX5_VALID_16    8
9816 #define M_PIPE0_RX5_VALID_16    0xffU
9817 #define V_PIPE0_RX5_VALID_16(x) ((x) << S_PIPE0_RX5_VALID_16)
9818 #define G_PIPE0_RX5_VALID_16(x) (((x) >> S_PIPE0_RX5_VALID_16) & M_PIPE0_RX5_VALID_16)
9819 
9820 #define S_PIPE0_RX4_VALID_16    7
9821 #define V_PIPE0_RX4_VALID_16(x) ((x) << S_PIPE0_RX4_VALID_16)
9822 #define F_PIPE0_RX4_VALID_16    V_PIPE0_RX4_VALID_16(1U)
9823 
9824 #define S_PIPE0_RX4_VALID2_16    0
9825 #define M_PIPE0_RX4_VALID2_16    0x7fU
9826 #define V_PIPE0_RX4_VALID2_16(x) ((x) << S_PIPE0_RX4_VALID2_16)
9827 #define G_PIPE0_RX4_VALID2_16(x) (((x) >> S_PIPE0_RX4_VALID2_16) & M_PIPE0_RX4_VALID2_16)
9828 
9829 #define A_PCIE_PDEBUG_REG_0X17 0x17
9830 
9831 #define S_PIPE0_RX7_VALID_17    31
9832 #define V_PIPE0_RX7_VALID_17(x) ((x) << S_PIPE0_RX7_VALID_17)
9833 #define F_PIPE0_RX7_VALID_17    V_PIPE0_RX7_VALID_17(1U)
9834 
9835 #define S_PIPE0_RX7_VALID2_17    24
9836 #define M_PIPE0_RX7_VALID2_17    0x7fU
9837 #define V_PIPE0_RX7_VALID2_17(x) ((x) << S_PIPE0_RX7_VALID2_17)
9838 #define G_PIPE0_RX7_VALID2_17(x) (((x) >> S_PIPE0_RX7_VALID2_17) & M_PIPE0_RX7_VALID2_17)
9839 
9840 #define S_PIPE0_RX6_VALID_17    16
9841 #define M_PIPE0_RX6_VALID_17    0xffU
9842 #define V_PIPE0_RX6_VALID_17(x) ((x) << S_PIPE0_RX6_VALID_17)
9843 #define G_PIPE0_RX6_VALID_17(x) (((x) >> S_PIPE0_RX6_VALID_17) & M_PIPE0_RX6_VALID_17)
9844 
9845 #define S_PIPE0_RX5_VALID_17    8
9846 #define M_PIPE0_RX5_VALID_17    0xffU
9847 #define V_PIPE0_RX5_VALID_17(x) ((x) << S_PIPE0_RX5_VALID_17)
9848 #define G_PIPE0_RX5_VALID_17(x) (((x) >> S_PIPE0_RX5_VALID_17) & M_PIPE0_RX5_VALID_17)
9849 
9850 #define S_PIPE0_RX4_VALID_17    7
9851 #define V_PIPE0_RX4_VALID_17(x) ((x) << S_PIPE0_RX4_VALID_17)
9852 #define F_PIPE0_RX4_VALID_17    V_PIPE0_RX4_VALID_17(1U)
9853 
9854 #define S_PIPE0_RX4_VALID2_17    0
9855 #define M_PIPE0_RX4_VALID2_17    0x7fU
9856 #define V_PIPE0_RX4_VALID2_17(x) ((x) << S_PIPE0_RX4_VALID2_17)
9857 #define G_PIPE0_RX4_VALID2_17(x) (((x) >> S_PIPE0_RX4_VALID2_17) & M_PIPE0_RX4_VALID2_17)
9858 
9859 #define A_PCIE_PDEBUG_REG_0X18 0x18
9860 
9861 #define S_PIPE0_RX7_POLARITY    31
9862 #define V_PIPE0_RX7_POLARITY(x) ((x) << S_PIPE0_RX7_POLARITY)
9863 #define F_PIPE0_RX7_POLARITY    V_PIPE0_RX7_POLARITY(1U)
9864 
9865 #define S_PIPE0_RX7_STATUS    28
9866 #define M_PIPE0_RX7_STATUS    0x7U
9867 #define V_PIPE0_RX7_STATUS(x) ((x) << S_PIPE0_RX7_STATUS)
9868 #define G_PIPE0_RX7_STATUS(x) (((x) >> S_PIPE0_RX7_STATUS) & M_PIPE0_RX7_STATUS)
9869 
9870 #define S_PIPE0_RX6_POLARITY    27
9871 #define V_PIPE0_RX6_POLARITY(x) ((x) << S_PIPE0_RX6_POLARITY)
9872 #define F_PIPE0_RX6_POLARITY    V_PIPE0_RX6_POLARITY(1U)
9873 
9874 #define S_PIPE0_RX6_STATUS    24
9875 #define M_PIPE0_RX6_STATUS    0x7U
9876 #define V_PIPE0_RX6_STATUS(x) ((x) << S_PIPE0_RX6_STATUS)
9877 #define G_PIPE0_RX6_STATUS(x) (((x) >> S_PIPE0_RX6_STATUS) & M_PIPE0_RX6_STATUS)
9878 
9879 #define S_PIPE0_RX5_POLARITY    23
9880 #define V_PIPE0_RX5_POLARITY(x) ((x) << S_PIPE0_RX5_POLARITY)
9881 #define F_PIPE0_RX5_POLARITY    V_PIPE0_RX5_POLARITY(1U)
9882 
9883 #define S_PIPE0_RX5_STATUS    20
9884 #define M_PIPE0_RX5_STATUS    0x7U
9885 #define V_PIPE0_RX5_STATUS(x) ((x) << S_PIPE0_RX5_STATUS)
9886 #define G_PIPE0_RX5_STATUS(x) (((x) >> S_PIPE0_RX5_STATUS) & M_PIPE0_RX5_STATUS)
9887 
9888 #define S_PIPE0_RX4_POLARITY    19
9889 #define V_PIPE0_RX4_POLARITY(x) ((x) << S_PIPE0_RX4_POLARITY)
9890 #define F_PIPE0_RX4_POLARITY    V_PIPE0_RX4_POLARITY(1U)
9891 
9892 #define S_PIPE0_RX4_STATUS    16
9893 #define M_PIPE0_RX4_STATUS    0x7U
9894 #define V_PIPE0_RX4_STATUS(x) ((x) << S_PIPE0_RX4_STATUS)
9895 #define G_PIPE0_RX4_STATUS(x) (((x) >> S_PIPE0_RX4_STATUS) & M_PIPE0_RX4_STATUS)
9896 
9897 #define S_PIPE0_RX3_POLARITY    15
9898 #define V_PIPE0_RX3_POLARITY(x) ((x) << S_PIPE0_RX3_POLARITY)
9899 #define F_PIPE0_RX3_POLARITY    V_PIPE0_RX3_POLARITY(1U)
9900 
9901 #define S_PIPE0_RX3_STATUS    12
9902 #define M_PIPE0_RX3_STATUS    0x7U
9903 #define V_PIPE0_RX3_STATUS(x) ((x) << S_PIPE0_RX3_STATUS)
9904 #define G_PIPE0_RX3_STATUS(x) (((x) >> S_PIPE0_RX3_STATUS) & M_PIPE0_RX3_STATUS)
9905 
9906 #define S_PIPE0_RX2_POLARITY    11
9907 #define V_PIPE0_RX2_POLARITY(x) ((x) << S_PIPE0_RX2_POLARITY)
9908 #define F_PIPE0_RX2_POLARITY    V_PIPE0_RX2_POLARITY(1U)
9909 
9910 #define S_PIPE0_RX2_STATUS    8
9911 #define M_PIPE0_RX2_STATUS    0x7U
9912 #define V_PIPE0_RX2_STATUS(x) ((x) << S_PIPE0_RX2_STATUS)
9913 #define G_PIPE0_RX2_STATUS(x) (((x) >> S_PIPE0_RX2_STATUS) & M_PIPE0_RX2_STATUS)
9914 
9915 #define S_PIPE0_RX1_POLARITY    7
9916 #define V_PIPE0_RX1_POLARITY(x) ((x) << S_PIPE0_RX1_POLARITY)
9917 #define F_PIPE0_RX1_POLARITY    V_PIPE0_RX1_POLARITY(1U)
9918 
9919 #define S_PIPE0_RX1_STATUS    4
9920 #define M_PIPE0_RX1_STATUS    0x7U
9921 #define V_PIPE0_RX1_STATUS(x) ((x) << S_PIPE0_RX1_STATUS)
9922 #define G_PIPE0_RX1_STATUS(x) (((x) >> S_PIPE0_RX1_STATUS) & M_PIPE0_RX1_STATUS)
9923 
9924 #define S_PIPE0_RX0_POLARITY    3
9925 #define V_PIPE0_RX0_POLARITY(x) ((x) << S_PIPE0_RX0_POLARITY)
9926 #define F_PIPE0_RX0_POLARITY    V_PIPE0_RX0_POLARITY(1U)
9927 
9928 #define S_PIPE0_RX0_STATUS    0
9929 #define M_PIPE0_RX0_STATUS    0x7U
9930 #define V_PIPE0_RX0_STATUS(x) ((x) << S_PIPE0_RX0_STATUS)
9931 #define G_PIPE0_RX0_STATUS(x) (((x) >> S_PIPE0_RX0_STATUS) & M_PIPE0_RX0_STATUS)
9932 
9933 #define A_PCIE_PDEBUG_REG_0X19 0x19
9934 
9935 #define S_PIPE0_TX7_COMPLIANCE    31
9936 #define V_PIPE0_TX7_COMPLIANCE(x) ((x) << S_PIPE0_TX7_COMPLIANCE)
9937 #define F_PIPE0_TX7_COMPLIANCE    V_PIPE0_TX7_COMPLIANCE(1U)
9938 
9939 #define S_PIPE0_TX6_COMPLIANCE    30
9940 #define V_PIPE0_TX6_COMPLIANCE(x) ((x) << S_PIPE0_TX6_COMPLIANCE)
9941 #define F_PIPE0_TX6_COMPLIANCE    V_PIPE0_TX6_COMPLIANCE(1U)
9942 
9943 #define S_PIPE0_TX5_COMPLIANCE    29
9944 #define V_PIPE0_TX5_COMPLIANCE(x) ((x) << S_PIPE0_TX5_COMPLIANCE)
9945 #define F_PIPE0_TX5_COMPLIANCE    V_PIPE0_TX5_COMPLIANCE(1U)
9946 
9947 #define S_PIPE0_TX4_COMPLIANCE    28
9948 #define V_PIPE0_TX4_COMPLIANCE(x) ((x) << S_PIPE0_TX4_COMPLIANCE)
9949 #define F_PIPE0_TX4_COMPLIANCE    V_PIPE0_TX4_COMPLIANCE(1U)
9950 
9951 #define S_PIPE0_TX3_COMPLIANCE    27
9952 #define V_PIPE0_TX3_COMPLIANCE(x) ((x) << S_PIPE0_TX3_COMPLIANCE)
9953 #define F_PIPE0_TX3_COMPLIANCE    V_PIPE0_TX3_COMPLIANCE(1U)
9954 
9955 #define S_PIPE0_TX2_COMPLIANCE    26
9956 #define V_PIPE0_TX2_COMPLIANCE(x) ((x) << S_PIPE0_TX2_COMPLIANCE)
9957 #define F_PIPE0_TX2_COMPLIANCE    V_PIPE0_TX2_COMPLIANCE(1U)
9958 
9959 #define S_PIPE0_TX1_COMPLIANCE    25
9960 #define V_PIPE0_TX1_COMPLIANCE(x) ((x) << S_PIPE0_TX1_COMPLIANCE)
9961 #define F_PIPE0_TX1_COMPLIANCE    V_PIPE0_TX1_COMPLIANCE(1U)
9962 
9963 #define S_PIPE0_TX0_COMPLIANCE    24
9964 #define V_PIPE0_TX0_COMPLIANCE(x) ((x) << S_PIPE0_TX0_COMPLIANCE)
9965 #define F_PIPE0_TX0_COMPLIANCE    V_PIPE0_TX0_COMPLIANCE(1U)
9966 
9967 #define S_PIPE0_TX7_ELECIDLE    23
9968 #define V_PIPE0_TX7_ELECIDLE(x) ((x) << S_PIPE0_TX7_ELECIDLE)
9969 #define F_PIPE0_TX7_ELECIDLE    V_PIPE0_TX7_ELECIDLE(1U)
9970 
9971 #define S_PIPE0_TX6_ELECIDLE    22
9972 #define V_PIPE0_TX6_ELECIDLE(x) ((x) << S_PIPE0_TX6_ELECIDLE)
9973 #define F_PIPE0_TX6_ELECIDLE    V_PIPE0_TX6_ELECIDLE(1U)
9974 
9975 #define S_PIPE0_TX5_ELECIDLE    21
9976 #define V_PIPE0_TX5_ELECIDLE(x) ((x) << S_PIPE0_TX5_ELECIDLE)
9977 #define F_PIPE0_TX5_ELECIDLE    V_PIPE0_TX5_ELECIDLE(1U)
9978 
9979 #define S_PIPE0_TX4_ELECIDLE    20
9980 #define V_PIPE0_TX4_ELECIDLE(x) ((x) << S_PIPE0_TX4_ELECIDLE)
9981 #define F_PIPE0_TX4_ELECIDLE    V_PIPE0_TX4_ELECIDLE(1U)
9982 
9983 #define S_PIPE0_TX3_ELECIDLE    19
9984 #define V_PIPE0_TX3_ELECIDLE(x) ((x) << S_PIPE0_TX3_ELECIDLE)
9985 #define F_PIPE0_TX3_ELECIDLE    V_PIPE0_TX3_ELECIDLE(1U)
9986 
9987 #define S_PIPE0_TX2_ELECIDLE    18
9988 #define V_PIPE0_TX2_ELECIDLE(x) ((x) << S_PIPE0_TX2_ELECIDLE)
9989 #define F_PIPE0_TX2_ELECIDLE    V_PIPE0_TX2_ELECIDLE(1U)
9990 
9991 #define S_PIPE0_TX1_ELECIDLE    17
9992 #define V_PIPE0_TX1_ELECIDLE(x) ((x) << S_PIPE0_TX1_ELECIDLE)
9993 #define F_PIPE0_TX1_ELECIDLE    V_PIPE0_TX1_ELECIDLE(1U)
9994 
9995 #define S_PIPE0_TX0_ELECIDLE    16
9996 #define V_PIPE0_TX0_ELECIDLE(x) ((x) << S_PIPE0_TX0_ELECIDLE)
9997 #define F_PIPE0_TX0_ELECIDLE    V_PIPE0_TX0_ELECIDLE(1U)
9998 
9999 #define S_PIPE0_RX7_POLARITY_19    15
10000 #define V_PIPE0_RX7_POLARITY_19(x) ((x) << S_PIPE0_RX7_POLARITY_19)
10001 #define F_PIPE0_RX7_POLARITY_19    V_PIPE0_RX7_POLARITY_19(1U)
10002 
10003 #define S_PIPE0_RX6_POLARITY_19    14
10004 #define V_PIPE0_RX6_POLARITY_19(x) ((x) << S_PIPE0_RX6_POLARITY_19)
10005 #define F_PIPE0_RX6_POLARITY_19    V_PIPE0_RX6_POLARITY_19(1U)
10006 
10007 #define S_PIPE0_RX5_POLARITY_19    13
10008 #define V_PIPE0_RX5_POLARITY_19(x) ((x) << S_PIPE0_RX5_POLARITY_19)
10009 #define F_PIPE0_RX5_POLARITY_19    V_PIPE0_RX5_POLARITY_19(1U)
10010 
10011 #define S_PIPE0_RX4_POLARITY_19    12
10012 #define V_PIPE0_RX4_POLARITY_19(x) ((x) << S_PIPE0_RX4_POLARITY_19)
10013 #define F_PIPE0_RX4_POLARITY_19    V_PIPE0_RX4_POLARITY_19(1U)
10014 
10015 #define S_PIPE0_RX3_POLARITY_19    11
10016 #define V_PIPE0_RX3_POLARITY_19(x) ((x) << S_PIPE0_RX3_POLARITY_19)
10017 #define F_PIPE0_RX3_POLARITY_19    V_PIPE0_RX3_POLARITY_19(1U)
10018 
10019 #define S_PIPE0_RX2_POLARITY_19    10
10020 #define V_PIPE0_RX2_POLARITY_19(x) ((x) << S_PIPE0_RX2_POLARITY_19)
10021 #define F_PIPE0_RX2_POLARITY_19    V_PIPE0_RX2_POLARITY_19(1U)
10022 
10023 #define S_PIPE0_RX1_POLARITY_19    9
10024 #define V_PIPE0_RX1_POLARITY_19(x) ((x) << S_PIPE0_RX1_POLARITY_19)
10025 #define F_PIPE0_RX1_POLARITY_19    V_PIPE0_RX1_POLARITY_19(1U)
10026 
10027 #define S_PIPE0_RX0_POLARITY_19    8
10028 #define V_PIPE0_RX0_POLARITY_19(x) ((x) << S_PIPE0_RX0_POLARITY_19)
10029 #define F_PIPE0_RX0_POLARITY_19    V_PIPE0_RX0_POLARITY_19(1U)
10030 
10031 #define S_PIPE0_RX7_ELECIDLE    7
10032 #define V_PIPE0_RX7_ELECIDLE(x) ((x) << S_PIPE0_RX7_ELECIDLE)
10033 #define F_PIPE0_RX7_ELECIDLE    V_PIPE0_RX7_ELECIDLE(1U)
10034 
10035 #define S_PIPE0_RX6_ELECIDLE    6
10036 #define V_PIPE0_RX6_ELECIDLE(x) ((x) << S_PIPE0_RX6_ELECIDLE)
10037 #define F_PIPE0_RX6_ELECIDLE    V_PIPE0_RX6_ELECIDLE(1U)
10038 
10039 #define S_PIPE0_RX5_ELECIDLE    5
10040 #define V_PIPE0_RX5_ELECIDLE(x) ((x) << S_PIPE0_RX5_ELECIDLE)
10041 #define F_PIPE0_RX5_ELECIDLE    V_PIPE0_RX5_ELECIDLE(1U)
10042 
10043 #define S_PIPE0_RX4_ELECIDLE    4
10044 #define V_PIPE0_RX4_ELECIDLE(x) ((x) << S_PIPE0_RX4_ELECIDLE)
10045 #define F_PIPE0_RX4_ELECIDLE    V_PIPE0_RX4_ELECIDLE(1U)
10046 
10047 #define S_PIPE0_RX3_ELECIDLE    3
10048 #define V_PIPE0_RX3_ELECIDLE(x) ((x) << S_PIPE0_RX3_ELECIDLE)
10049 #define F_PIPE0_RX3_ELECIDLE    V_PIPE0_RX3_ELECIDLE(1U)
10050 
10051 #define S_PIPE0_RX2_ELECIDLE    2
10052 #define V_PIPE0_RX2_ELECIDLE(x) ((x) << S_PIPE0_RX2_ELECIDLE)
10053 #define F_PIPE0_RX2_ELECIDLE    V_PIPE0_RX2_ELECIDLE(1U)
10054 
10055 #define S_PIPE0_RX1_ELECIDLE    1
10056 #define V_PIPE0_RX1_ELECIDLE(x) ((x) << S_PIPE0_RX1_ELECIDLE)
10057 #define F_PIPE0_RX1_ELECIDLE    V_PIPE0_RX1_ELECIDLE(1U)
10058 
10059 #define S_PIPE0_RX0_ELECIDLE    0
10060 #define V_PIPE0_RX0_ELECIDLE(x) ((x) << S_PIPE0_RX0_ELECIDLE)
10061 #define F_PIPE0_RX0_ELECIDLE    V_PIPE0_RX0_ELECIDLE(1U)
10062 
10063 #define A_PCIE_PDEBUG_REG_0X1A 0x1a
10064 
10065 #define S_PIPE0_RESET_N    21
10066 #define V_PIPE0_RESET_N(x) ((x) << S_PIPE0_RESET_N)
10067 #define F_PIPE0_RESET_N    V_PIPE0_RESET_N(1U)
10068 
10069 #define S_PCS_COMMON_CLOCKS    20
10070 #define V_PCS_COMMON_CLOCKS(x) ((x) << S_PCS_COMMON_CLOCKS)
10071 #define F_PCS_COMMON_CLOCKS    V_PCS_COMMON_CLOCKS(1U)
10072 
10073 #define S_PCS_CLK_REQ    19
10074 #define V_PCS_CLK_REQ(x) ((x) << S_PCS_CLK_REQ)
10075 #define F_PCS_CLK_REQ    V_PCS_CLK_REQ(1U)
10076 
10077 #define S_PIPE_CLKREQ_N    18
10078 #define V_PIPE_CLKREQ_N(x) ((x) << S_PIPE_CLKREQ_N)
10079 #define F_PIPE_CLKREQ_N    V_PIPE_CLKREQ_N(1U)
10080 
10081 #define S_MAC_CLKREQ_N_TO_MUX    17
10082 #define V_MAC_CLKREQ_N_TO_MUX(x) ((x) << S_MAC_CLKREQ_N_TO_MUX)
10083 #define F_MAC_CLKREQ_N_TO_MUX    V_MAC_CLKREQ_N_TO_MUX(1U)
10084 
10085 #define S_PIPE0_TX2RX_LOOPBK    16
10086 #define V_PIPE0_TX2RX_LOOPBK(x) ((x) << S_PIPE0_TX2RX_LOOPBK)
10087 #define F_PIPE0_TX2RX_LOOPBK    V_PIPE0_TX2RX_LOOPBK(1U)
10088 
10089 #define S_PIPE0_TX_SWING    15
10090 #define V_PIPE0_TX_SWING(x) ((x) << S_PIPE0_TX_SWING)
10091 #define F_PIPE0_TX_SWING    V_PIPE0_TX_SWING(1U)
10092 
10093 #define S_PIPE0_TX_MARGIN    12
10094 #define M_PIPE0_TX_MARGIN    0x7U
10095 #define V_PIPE0_TX_MARGIN(x) ((x) << S_PIPE0_TX_MARGIN)
10096 #define G_PIPE0_TX_MARGIN(x) (((x) >> S_PIPE0_TX_MARGIN) & M_PIPE0_TX_MARGIN)
10097 
10098 #define S_PIPE0_TX_DEEMPH    11
10099 #define V_PIPE0_TX_DEEMPH(x) ((x) << S_PIPE0_TX_DEEMPH)
10100 #define F_PIPE0_TX_DEEMPH    V_PIPE0_TX_DEEMPH(1U)
10101 
10102 #define S_PIPE0_TX_DETECTRX    10
10103 #define V_PIPE0_TX_DETECTRX(x) ((x) << S_PIPE0_TX_DETECTRX)
10104 #define F_PIPE0_TX_DETECTRX    V_PIPE0_TX_DETECTRX(1U)
10105 
10106 #define S_PIPE0_POWERDOWN    8
10107 #define M_PIPE0_POWERDOWN    0x3U
10108 #define V_PIPE0_POWERDOWN(x) ((x) << S_PIPE0_POWERDOWN)
10109 #define G_PIPE0_POWERDOWN(x) (((x) >> S_PIPE0_POWERDOWN) & M_PIPE0_POWERDOWN)
10110 
10111 #define S_PHY_MAC_PHYSTATUS    0
10112 #define M_PHY_MAC_PHYSTATUS    0xffU
10113 #define V_PHY_MAC_PHYSTATUS(x) ((x) << S_PHY_MAC_PHYSTATUS)
10114 #define G_PHY_MAC_PHYSTATUS(x) (((x) >> S_PHY_MAC_PHYSTATUS) & M_PHY_MAC_PHYSTATUS)
10115 
10116 #define A_PCIE_PDEBUG_REG_0X1B 0x1b
10117 
10118 #define S_PIPE0_RX7_EQ_IN_PROG    31
10119 #define V_PIPE0_RX7_EQ_IN_PROG(x) ((x) << S_PIPE0_RX7_EQ_IN_PROG)
10120 #define F_PIPE0_RX7_EQ_IN_PROG    V_PIPE0_RX7_EQ_IN_PROG(1U)
10121 
10122 #define S_PIPE0_RX7_EQ_INVLD_REQ    30
10123 #define V_PIPE0_RX7_EQ_INVLD_REQ(x) ((x) << S_PIPE0_RX7_EQ_INVLD_REQ)
10124 #define F_PIPE0_RX7_EQ_INVLD_REQ    V_PIPE0_RX7_EQ_INVLD_REQ(1U)
10125 
10126 #define S_PIPE0_RX7_SYNCHEADER    28
10127 #define M_PIPE0_RX7_SYNCHEADER    0x3U
10128 #define V_PIPE0_RX7_SYNCHEADER(x) ((x) << S_PIPE0_RX7_SYNCHEADER)
10129 #define G_PIPE0_RX7_SYNCHEADER(x) (((x) >> S_PIPE0_RX7_SYNCHEADER) & M_PIPE0_RX7_SYNCHEADER)
10130 
10131 #define S_PIPE0_RX6_EQ_IN_PROG    27
10132 #define V_PIPE0_RX6_EQ_IN_PROG(x) ((x) << S_PIPE0_RX6_EQ_IN_PROG)
10133 #define F_PIPE0_RX6_EQ_IN_PROG    V_PIPE0_RX6_EQ_IN_PROG(1U)
10134 
10135 #define S_PIPE0_RX6_EQ_INVLD_REQ    26
10136 #define V_PIPE0_RX6_EQ_INVLD_REQ(x) ((x) << S_PIPE0_RX6_EQ_INVLD_REQ)
10137 #define F_PIPE0_RX6_EQ_INVLD_REQ    V_PIPE0_RX6_EQ_INVLD_REQ(1U)
10138 
10139 #define S_PIPE0_RX6_SYNCHEADER    24
10140 #define M_PIPE0_RX6_SYNCHEADER    0x3U
10141 #define V_PIPE0_RX6_SYNCHEADER(x) ((x) << S_PIPE0_RX6_SYNCHEADER)
10142 #define G_PIPE0_RX6_SYNCHEADER(x) (((x) >> S_PIPE0_RX6_SYNCHEADER) & M_PIPE0_RX6_SYNCHEADER)
10143 
10144 #define S_PIPE0_RX5_EQ_IN_PROG    23
10145 #define V_PIPE0_RX5_EQ_IN_PROG(x) ((x) << S_PIPE0_RX5_EQ_IN_PROG)
10146 #define F_PIPE0_RX5_EQ_IN_PROG    V_PIPE0_RX5_EQ_IN_PROG(1U)
10147 
10148 #define S_PIPE0_RX5_EQ_INVLD_REQ    22
10149 #define V_PIPE0_RX5_EQ_INVLD_REQ(x) ((x) << S_PIPE0_RX5_EQ_INVLD_REQ)
10150 #define F_PIPE0_RX5_EQ_INVLD_REQ    V_PIPE0_RX5_EQ_INVLD_REQ(1U)
10151 
10152 #define S_PIPE0_RX5_SYNCHEADER    20
10153 #define M_PIPE0_RX5_SYNCHEADER    0x3U
10154 #define V_PIPE0_RX5_SYNCHEADER(x) ((x) << S_PIPE0_RX5_SYNCHEADER)
10155 #define G_PIPE0_RX5_SYNCHEADER(x) (((x) >> S_PIPE0_RX5_SYNCHEADER) & M_PIPE0_RX5_SYNCHEADER)
10156 
10157 #define S_PIPE0_RX4_EQ_IN_PROG    19
10158 #define V_PIPE0_RX4_EQ_IN_PROG(x) ((x) << S_PIPE0_RX4_EQ_IN_PROG)
10159 #define F_PIPE0_RX4_EQ_IN_PROG    V_PIPE0_RX4_EQ_IN_PROG(1U)
10160 
10161 #define S_PIPE0_RX4_EQ_INVLD_REQ    18
10162 #define V_PIPE0_RX4_EQ_INVLD_REQ(x) ((x) << S_PIPE0_RX4_EQ_INVLD_REQ)
10163 #define F_PIPE0_RX4_EQ_INVLD_REQ    V_PIPE0_RX4_EQ_INVLD_REQ(1U)
10164 
10165 #define S_PIPE0_RX4_SYNCHEADER    16
10166 #define M_PIPE0_RX4_SYNCHEADER    0x3U
10167 #define V_PIPE0_RX4_SYNCHEADER(x) ((x) << S_PIPE0_RX4_SYNCHEADER)
10168 #define G_PIPE0_RX4_SYNCHEADER(x) (((x) >> S_PIPE0_RX4_SYNCHEADER) & M_PIPE0_RX4_SYNCHEADER)
10169 
10170 #define S_PIPE0_RX3_EQ_IN_PROG    15
10171 #define V_PIPE0_RX3_EQ_IN_PROG(x) ((x) << S_PIPE0_RX3_EQ_IN_PROG)
10172 #define F_PIPE0_RX3_EQ_IN_PROG    V_PIPE0_RX3_EQ_IN_PROG(1U)
10173 
10174 #define S_PIPE0_RX3_EQ_INVLD_REQ    14
10175 #define V_PIPE0_RX3_EQ_INVLD_REQ(x) ((x) << S_PIPE0_RX3_EQ_INVLD_REQ)
10176 #define F_PIPE0_RX3_EQ_INVLD_REQ    V_PIPE0_RX3_EQ_INVLD_REQ(1U)
10177 
10178 #define S_PIPE0_RX3_SYNCHEADER    12
10179 #define M_PIPE0_RX3_SYNCHEADER    0x3U
10180 #define V_PIPE0_RX3_SYNCHEADER(x) ((x) << S_PIPE0_RX3_SYNCHEADER)
10181 #define G_PIPE0_RX3_SYNCHEADER(x) (((x) >> S_PIPE0_RX3_SYNCHEADER) & M_PIPE0_RX3_SYNCHEADER)
10182 
10183 #define S_PIPE0_RX2_EQ_IN_PROG    11
10184 #define V_PIPE0_RX2_EQ_IN_PROG(x) ((x) << S_PIPE0_RX2_EQ_IN_PROG)
10185 #define F_PIPE0_RX2_EQ_IN_PROG    V_PIPE0_RX2_EQ_IN_PROG(1U)
10186 
10187 #define S_PIPE0_RX2_EQ_INVLD_REQ    10
10188 #define V_PIPE0_RX2_EQ_INVLD_REQ(x) ((x) << S_PIPE0_RX2_EQ_INVLD_REQ)
10189 #define F_PIPE0_RX2_EQ_INVLD_REQ    V_PIPE0_RX2_EQ_INVLD_REQ(1U)
10190 
10191 #define S_PIPE0_RX2_SYNCHEADER    8
10192 #define M_PIPE0_RX2_SYNCHEADER    0x3U
10193 #define V_PIPE0_RX2_SYNCHEADER(x) ((x) << S_PIPE0_RX2_SYNCHEADER)
10194 #define G_PIPE0_RX2_SYNCHEADER(x) (((x) >> S_PIPE0_RX2_SYNCHEADER) & M_PIPE0_RX2_SYNCHEADER)
10195 
10196 #define S_PIPE0_RX1_EQ_IN_PROG    7
10197 #define V_PIPE0_RX1_EQ_IN_PROG(x) ((x) << S_PIPE0_RX1_EQ_IN_PROG)
10198 #define F_PIPE0_RX1_EQ_IN_PROG    V_PIPE0_RX1_EQ_IN_PROG(1U)
10199 
10200 #define S_PIPE0_RX1_EQ_INVLD_REQ    6
10201 #define V_PIPE0_RX1_EQ_INVLD_REQ(x) ((x) << S_PIPE0_RX1_EQ_INVLD_REQ)
10202 #define F_PIPE0_RX1_EQ_INVLD_REQ    V_PIPE0_RX1_EQ_INVLD_REQ(1U)
10203 
10204 #define S_PIPE0_RX1_SYNCHEADER    4
10205 #define M_PIPE0_RX1_SYNCHEADER    0x3U
10206 #define V_PIPE0_RX1_SYNCHEADER(x) ((x) << S_PIPE0_RX1_SYNCHEADER)
10207 #define G_PIPE0_RX1_SYNCHEADER(x) (((x) >> S_PIPE0_RX1_SYNCHEADER) & M_PIPE0_RX1_SYNCHEADER)
10208 
10209 #define S_PIPE0_RX0_EQ_IN_PROG    3
10210 #define V_PIPE0_RX0_EQ_IN_PROG(x) ((x) << S_PIPE0_RX0_EQ_IN_PROG)
10211 #define F_PIPE0_RX0_EQ_IN_PROG    V_PIPE0_RX0_EQ_IN_PROG(1U)
10212 
10213 #define S_PIPE0_RX0_EQ_INVLD_REQ    2
10214 #define V_PIPE0_RX0_EQ_INVLD_REQ(x) ((x) << S_PIPE0_RX0_EQ_INVLD_REQ)
10215 #define F_PIPE0_RX0_EQ_INVLD_REQ    V_PIPE0_RX0_EQ_INVLD_REQ(1U)
10216 
10217 #define S_PIPE0_RX0_SYNCHEADER    0
10218 #define M_PIPE0_RX0_SYNCHEADER    0x3U
10219 #define V_PIPE0_RX0_SYNCHEADER(x) ((x) << S_PIPE0_RX0_SYNCHEADER)
10220 #define G_PIPE0_RX0_SYNCHEADER(x) (((x) >> S_PIPE0_RX0_SYNCHEADER) & M_PIPE0_RX0_SYNCHEADER)
10221 
10222 #define A_PCIE_PDEBUG_REG_0X1C 0x1c
10223 
10224 #define S_SI_REQVFID    24
10225 #define M_SI_REQVFID    0xffU
10226 #define V_SI_REQVFID(x) ((x) << S_SI_REQVFID)
10227 #define G_SI_REQVFID(x) (((x) >> S_SI_REQVFID) & M_SI_REQVFID)
10228 
10229 #define S_SI_REQVEC    13
10230 #define M_SI_REQVEC    0x7ffU
10231 #define V_SI_REQVEC(x) ((x) << S_SI_REQVEC)
10232 #define G_SI_REQVEC(x) (((x) >> S_SI_REQVEC) & M_SI_REQVEC)
10233 
10234 #define S_SI_REQTCVAL    10
10235 #define M_SI_REQTCVAL    0x7U
10236 #define V_SI_REQTCVAL(x) ((x) << S_SI_REQTCVAL)
10237 #define G_SI_REQTCVAL(x) (((x) >> S_SI_REQTCVAL) & M_SI_REQTCVAL)
10238 
10239 #define S_SI_REQRDY    9
10240 #define V_SI_REQRDY(x) ((x) << S_SI_REQRDY)
10241 #define F_SI_REQRDY    V_SI_REQRDY(1U)
10242 
10243 #define S_SI_REQVLD    8
10244 #define V_SI_REQVLD(x) ((x) << S_SI_REQVLD)
10245 #define F_SI_REQVLD    V_SI_REQVLD(1U)
10246 
10247 #define S_T5_AI    0
10248 #define M_T5_AI    0xffU
10249 #define V_T5_AI(x) ((x) << S_T5_AI)
10250 #define G_T5_AI(x) (((x) >> S_T5_AI) & M_T5_AI)
10251 
10252 #define A_PCIE_PDEBUG_REG_0X1D 0x1d
10253 
10254 #define S_GNTSI    31
10255 #define V_GNTSI(x) ((x) << S_GNTSI)
10256 #define F_GNTSI    V_GNTSI(1U)
10257 
10258 #define S_DROPINTFORFLR    30
10259 #define V_DROPINTFORFLR(x) ((x) << S_DROPINTFORFLR)
10260 #define F_DROPINTFORFLR    V_DROPINTFORFLR(1U)
10261 
10262 #define S_SMARB    27
10263 #define M_SMARB    0x7U
10264 #define V_SMARB(x) ((x) << S_SMARB)
10265 #define G_SMARB(x) (((x) >> S_SMARB) & M_SMARB)
10266 
10267 #define S_SMDEFR    24
10268 #define M_SMDEFR    0x7U
10269 #define V_SMDEFR(x) ((x) << S_SMDEFR)
10270 #define G_SMDEFR(x) (((x) >> S_SMDEFR) & M_SMDEFR)
10271 
10272 #define S_SYS_INT    16
10273 #define M_SYS_INT    0xffU
10274 #define V_SYS_INT(x) ((x) << S_SYS_INT)
10275 #define G_SYS_INT(x) (((x) >> S_SYS_INT) & M_SYS_INT)
10276 
10277 #define S_CFG_INTXCLR    8
10278 #define M_CFG_INTXCLR    0xffU
10279 #define V_CFG_INTXCLR(x) ((x) << S_CFG_INTXCLR)
10280 #define G_CFG_INTXCLR(x) (((x) >> S_CFG_INTXCLR) & M_CFG_INTXCLR)
10281 
10282 #define S_PIO_INTXCLR    0
10283 #define M_PIO_INTXCLR    0xffU
10284 #define V_PIO_INTXCLR(x) ((x) << S_PIO_INTXCLR)
10285 #define G_PIO_INTXCLR(x) (((x) >> S_PIO_INTXCLR) & M_PIO_INTXCLR)
10286 
10287 #define A_PCIE_PDEBUG_REG_0X1E 0x1e
10288 
10289 #define S_PLI_TABDATWREN    31
10290 #define V_PLI_TABDATWREN(x) ((x) << S_PLI_TABDATWREN)
10291 #define F_PLI_TABDATWREN    V_PLI_TABDATWREN(1U)
10292 
10293 #define S_TAB_RDENA    30
10294 #define V_TAB_RDENA(x) ((x) << S_TAB_RDENA)
10295 #define F_TAB_RDENA    V_TAB_RDENA(1U)
10296 
10297 #define S_TAB_RDENA2    19
10298 #define M_TAB_RDENA2    0x7ffU
10299 #define V_TAB_RDENA2(x) ((x) << S_TAB_RDENA2)
10300 #define G_TAB_RDENA2(x) (((x) >> S_TAB_RDENA2) & M_TAB_RDENA2)
10301 
10302 #define S_PLI_REQADDR    10
10303 #define M_PLI_REQADDR    0x1ffU
10304 #define V_PLI_REQADDR(x) ((x) << S_PLI_REQADDR)
10305 #define G_PLI_REQADDR(x) (((x) >> S_PLI_REQADDR) & M_PLI_REQADDR)
10306 
10307 #define S_PLI_REQVFID    2
10308 #define M_PLI_REQVFID    0xffU
10309 #define V_PLI_REQVFID(x) ((x) << S_PLI_REQVFID)
10310 #define G_PLI_REQVFID(x) (((x) >> S_PLI_REQVFID) & M_PLI_REQVFID)
10311 
10312 #define S_PLI_REQTABHIT    1
10313 #define V_PLI_REQTABHIT(x) ((x) << S_PLI_REQTABHIT)
10314 #define F_PLI_REQTABHIT    V_PLI_REQTABHIT(1U)
10315 
10316 #define S_PLI_REQRDVLD    0
10317 #define V_PLI_REQRDVLD(x) ((x) << S_PLI_REQRDVLD)
10318 #define F_PLI_REQRDVLD    V_PLI_REQRDVLD(1U)
10319 
10320 #define A_PCIE_PDEBUG_REG_0X1F 0x1f
10321 #define A_PCIE_PDEBUG_REG_0X20 0x20
10322 #define A_PCIE_PDEBUG_REG_0X21 0x21
10323 
10324 #define S_PLI_REQPBASTART    20
10325 #define M_PLI_REQPBASTART    0xfffU
10326 #define V_PLI_REQPBASTART(x) ((x) << S_PLI_REQPBASTART)
10327 #define G_PLI_REQPBASTART(x) (((x) >> S_PLI_REQPBASTART) & M_PLI_REQPBASTART)
10328 
10329 #define S_PLI_REQPBAEND    9
10330 #define M_PLI_REQPBAEND    0x7ffU
10331 #define V_PLI_REQPBAEND(x) ((x) << S_PLI_REQPBAEND)
10332 #define G_PLI_REQPBAEND(x) (((x) >> S_PLI_REQPBAEND) & M_PLI_REQPBAEND)
10333 
10334 #define S_T5_PLI_REQVFID    2
10335 #define M_T5_PLI_REQVFID    0x7fU
10336 #define V_T5_PLI_REQVFID(x) ((x) << S_T5_PLI_REQVFID)
10337 #define G_T5_PLI_REQVFID(x) (((x) >> S_T5_PLI_REQVFID) & M_T5_PLI_REQVFID)
10338 
10339 #define S_PLI_REQPBAHIT    1
10340 #define V_PLI_REQPBAHIT(x) ((x) << S_PLI_REQPBAHIT)
10341 #define F_PLI_REQPBAHIT    V_PLI_REQPBAHIT(1U)
10342 
10343 #define A_PCIE_PDEBUG_REG_0X22 0x22
10344 
10345 #define S_GNTSI1    31
10346 #define V_GNTSI1(x) ((x) << S_GNTSI1)
10347 #define F_GNTSI1    V_GNTSI1(1U)
10348 
10349 #define S_GNTSI2    30
10350 #define V_GNTSI2(x) ((x) << S_GNTSI2)
10351 #define F_GNTSI2    V_GNTSI2(1U)
10352 
10353 #define S_GNTSI3    27
10354 #define M_GNTSI3    0x7U
10355 #define V_GNTSI3(x) ((x) << S_GNTSI3)
10356 #define G_GNTSI3(x) (((x) >> S_GNTSI3) & M_GNTSI3)
10357 
10358 #define S_GNTSI4    16
10359 #define M_GNTSI4    0x7ffU
10360 #define V_GNTSI4(x) ((x) << S_GNTSI4)
10361 #define G_GNTSI4(x) (((x) >> S_GNTSI4) & M_GNTSI4)
10362 
10363 #define S_GNTSI5    8
10364 #define M_GNTSI5    0xffU
10365 #define V_GNTSI5(x) ((x) << S_GNTSI5)
10366 #define G_GNTSI5(x) (((x) >> S_GNTSI5) & M_GNTSI5)
10367 
10368 #define S_GNTSI6    7
10369 #define V_GNTSI6(x) ((x) << S_GNTSI6)
10370 #define F_GNTSI6    V_GNTSI6(1U)
10371 
10372 #define S_GNTSI7    6
10373 #define V_GNTSI7(x) ((x) << S_GNTSI7)
10374 #define F_GNTSI7    V_GNTSI7(1U)
10375 
10376 #define S_GNTSI8    5
10377 #define V_GNTSI8(x) ((x) << S_GNTSI8)
10378 #define F_GNTSI8    V_GNTSI8(1U)
10379 
10380 #define S_GNTSI9    4
10381 #define V_GNTSI9(x) ((x) << S_GNTSI9)
10382 #define F_GNTSI9    V_GNTSI9(1U)
10383 
10384 #define S_GNTSIA    3
10385 #define V_GNTSIA(x) ((x) << S_GNTSIA)
10386 #define F_GNTSIA    V_GNTSIA(1U)
10387 
10388 #define S_GNTAI    2
10389 #define V_GNTAI(x) ((x) << S_GNTAI)
10390 #define F_GNTAI    V_GNTAI(1U)
10391 
10392 #define S_GNTDB    1
10393 #define V_GNTDB(x) ((x) << S_GNTDB)
10394 #define F_GNTDB    V_GNTDB(1U)
10395 
10396 #define S_GNTDI    0
10397 #define V_GNTDI(x) ((x) << S_GNTDI)
10398 #define F_GNTDI    V_GNTDI(1U)
10399 
10400 #define A_PCIE_PDEBUG_REG_0X23 0x23
10401 
10402 #define S_DI_REQVLD    31
10403 #define V_DI_REQVLD(x) ((x) << S_DI_REQVLD)
10404 #define F_DI_REQVLD    V_DI_REQVLD(1U)
10405 
10406 #define S_DI_REQRDY    30
10407 #define V_DI_REQRDY(x) ((x) << S_DI_REQRDY)
10408 #define F_DI_REQRDY    V_DI_REQRDY(1U)
10409 
10410 #define S_DI_REQWREN    19
10411 #define M_DI_REQWREN    0x7ffU
10412 #define V_DI_REQWREN(x) ((x) << S_DI_REQWREN)
10413 #define G_DI_REQWREN(x) (((x) >> S_DI_REQWREN) & M_DI_REQWREN)
10414 
10415 #define S_DI_REQMSIEN    18
10416 #define V_DI_REQMSIEN(x) ((x) << S_DI_REQMSIEN)
10417 #define F_DI_REQMSIEN    V_DI_REQMSIEN(1U)
10418 
10419 #define S_DI_REQMSXEN    17
10420 #define V_DI_REQMSXEN(x) ((x) << S_DI_REQMSXEN)
10421 #define F_DI_REQMSXEN    V_DI_REQMSXEN(1U)
10422 
10423 #define S_DI_REQMSXVFIDMSK    16
10424 #define V_DI_REQMSXVFIDMSK(x) ((x) << S_DI_REQMSXVFIDMSK)
10425 #define F_DI_REQMSXVFIDMSK    V_DI_REQMSXVFIDMSK(1U)
10426 
10427 #define S_DI_REQWREN2    2
10428 #define M_DI_REQWREN2    0x3fffU
10429 #define V_DI_REQWREN2(x) ((x) << S_DI_REQWREN2)
10430 #define G_DI_REQWREN2(x) (((x) >> S_DI_REQWREN2) & M_DI_REQWREN2)
10431 
10432 #define S_DI_REQRDEN    1
10433 #define V_DI_REQRDEN(x) ((x) << S_DI_REQRDEN)
10434 #define F_DI_REQRDEN    V_DI_REQRDEN(1U)
10435 
10436 #define S_DI_REQWREN3    0
10437 #define V_DI_REQWREN3(x) ((x) << S_DI_REQWREN3)
10438 #define F_DI_REQWREN3    V_DI_REQWREN3(1U)
10439 
10440 #define A_PCIE_PDEBUG_REG_0X24 0x24
10441 #define A_PCIE_PDEBUG_REG_0X25 0x25
10442 #define A_PCIE_PDEBUG_REG_0X26 0x26
10443 #define A_PCIE_PDEBUG_REG_0X27 0x27
10444 
10445 #define S_FID_STI_RSPVLD    31
10446 #define V_FID_STI_RSPVLD(x) ((x) << S_FID_STI_RSPVLD)
10447 #define F_FID_STI_RSPVLD    V_FID_STI_RSPVLD(1U)
10448 
10449 #define S_TAB_STIRDENA    30
10450 #define V_TAB_STIRDENA(x) ((x) << S_TAB_STIRDENA)
10451 #define F_TAB_STIRDENA    V_TAB_STIRDENA(1U)
10452 
10453 #define S_TAB_STIWRENA    29
10454 #define V_TAB_STIWRENA(x) ((x) << S_TAB_STIWRENA)
10455 #define F_TAB_STIWRENA    V_TAB_STIWRENA(1U)
10456 
10457 #define S_TAB_STIRDENA2    18
10458 #define M_TAB_STIRDENA2    0x7ffU
10459 #define V_TAB_STIRDENA2(x) ((x) << S_TAB_STIRDENA2)
10460 #define G_TAB_STIRDENA2(x) (((x) >> S_TAB_STIRDENA2) & M_TAB_STIRDENA2)
10461 
10462 #define S_T5_PLI_REQTABHIT    7
10463 #define M_T5_PLI_REQTABHIT    0x7ffU
10464 #define V_T5_PLI_REQTABHIT(x) ((x) << S_T5_PLI_REQTABHIT)
10465 #define G_T5_PLI_REQTABHIT(x) (((x) >> S_T5_PLI_REQTABHIT) & M_T5_PLI_REQTABHIT)
10466 
10467 #define S_T5_GNTSI    0
10468 #define M_T5_GNTSI    0x7fU
10469 #define V_T5_GNTSI(x) ((x) << S_T5_GNTSI)
10470 #define G_T5_GNTSI(x) (((x) >> S_T5_GNTSI) & M_T5_GNTSI)
10471 
10472 #define A_PCIE_PDEBUG_REG_0X28 0x28
10473 
10474 #define S_PLI_REQWRVLD    31
10475 #define V_PLI_REQWRVLD(x) ((x) << S_PLI_REQWRVLD)
10476 #define F_PLI_REQWRVLD    V_PLI_REQWRVLD(1U)
10477 
10478 #define S_T5_PLI_REQPBAHIT    30
10479 #define V_T5_PLI_REQPBAHIT(x) ((x) << S_T5_PLI_REQPBAHIT)
10480 #define F_T5_PLI_REQPBAHIT    V_T5_PLI_REQPBAHIT(1U)
10481 
10482 #define S_PLI_TABADDRLWREN    29
10483 #define V_PLI_TABADDRLWREN(x) ((x) << S_PLI_TABADDRLWREN)
10484 #define F_PLI_TABADDRLWREN    V_PLI_TABADDRLWREN(1U)
10485 
10486 #define S_PLI_TABADDRHWREN    28
10487 #define V_PLI_TABADDRHWREN(x) ((x) << S_PLI_TABADDRHWREN)
10488 #define F_PLI_TABADDRHWREN    V_PLI_TABADDRHWREN(1U)
10489 
10490 #define S_T5_PLI_TABDATWREN    27
10491 #define V_T5_PLI_TABDATWREN(x) ((x) << S_T5_PLI_TABDATWREN)
10492 #define F_T5_PLI_TABDATWREN    V_T5_PLI_TABDATWREN(1U)
10493 
10494 #define S_PLI_TABMSKWREN    26
10495 #define V_PLI_TABMSKWREN(x) ((x) << S_PLI_TABMSKWREN)
10496 #define F_PLI_TABMSKWREN    V_PLI_TABMSKWREN(1U)
10497 
10498 #define S_AI_REQVLD    23
10499 #define M_AI_REQVLD    0x7U
10500 #define V_AI_REQVLD(x) ((x) << S_AI_REQVLD)
10501 #define G_AI_REQVLD(x) (((x) >> S_AI_REQVLD) & M_AI_REQVLD)
10502 
10503 #define S_AI_REQVLD2    22
10504 #define V_AI_REQVLD2(x) ((x) << S_AI_REQVLD2)
10505 #define F_AI_REQVLD2    V_AI_REQVLD2(1U)
10506 
10507 #define S_AI_REQRDY    21
10508 #define V_AI_REQRDY(x) ((x) << S_AI_REQRDY)
10509 #define F_AI_REQRDY    V_AI_REQRDY(1U)
10510 
10511 #define S_VEN_MSI_REQ_28    18
10512 #define M_VEN_MSI_REQ_28    0x7U
10513 #define V_VEN_MSI_REQ_28(x) ((x) << S_VEN_MSI_REQ_28)
10514 #define G_VEN_MSI_REQ_28(x) (((x) >> S_VEN_MSI_REQ_28) & M_VEN_MSI_REQ_28)
10515 
10516 #define S_VEN_MSI_REQ2    11
10517 #define M_VEN_MSI_REQ2    0x7fU
10518 #define V_VEN_MSI_REQ2(x) ((x) << S_VEN_MSI_REQ2)
10519 #define G_VEN_MSI_REQ2(x) (((x) >> S_VEN_MSI_REQ2) & M_VEN_MSI_REQ2)
10520 
10521 #define S_VEN_MSI_REQ3    6
10522 #define M_VEN_MSI_REQ3    0x1fU
10523 #define V_VEN_MSI_REQ3(x) ((x) << S_VEN_MSI_REQ3)
10524 #define G_VEN_MSI_REQ3(x) (((x) >> S_VEN_MSI_REQ3) & M_VEN_MSI_REQ3)
10525 
10526 #define S_VEN_MSI_REQ4    3
10527 #define M_VEN_MSI_REQ4    0x7U
10528 #define V_VEN_MSI_REQ4(x) ((x) << S_VEN_MSI_REQ4)
10529 #define G_VEN_MSI_REQ4(x) (((x) >> S_VEN_MSI_REQ4) & M_VEN_MSI_REQ4)
10530 
10531 #define S_VEN_MSI_REQ5    2
10532 #define V_VEN_MSI_REQ5(x) ((x) << S_VEN_MSI_REQ5)
10533 #define F_VEN_MSI_REQ5    V_VEN_MSI_REQ5(1U)
10534 
10535 #define S_VEN_MSI_GRANT    1
10536 #define V_VEN_MSI_GRANT(x) ((x) << S_VEN_MSI_GRANT)
10537 #define F_VEN_MSI_GRANT    V_VEN_MSI_GRANT(1U)
10538 
10539 #define S_VEN_MSI_REQ6    0
10540 #define V_VEN_MSI_REQ6(x) ((x) << S_VEN_MSI_REQ6)
10541 #define F_VEN_MSI_REQ6    V_VEN_MSI_REQ6(1U)
10542 
10543 #define A_PCIE_PDEBUG_REG_0X29 0x29
10544 
10545 #define S_TRGT1_REQDATAVLD    16
10546 #define M_TRGT1_REQDATAVLD    0xffffU
10547 #define V_TRGT1_REQDATAVLD(x) ((x) << S_TRGT1_REQDATAVLD)
10548 #define G_TRGT1_REQDATAVLD(x) (((x) >> S_TRGT1_REQDATAVLD) & M_TRGT1_REQDATAVLD)
10549 
10550 #define S_TRGT1_REQDATAVLD2    12
10551 #define M_TRGT1_REQDATAVLD2    0xfU
10552 #define V_TRGT1_REQDATAVLD2(x) ((x) << S_TRGT1_REQDATAVLD2)
10553 #define G_TRGT1_REQDATAVLD2(x) (((x) >> S_TRGT1_REQDATAVLD2) & M_TRGT1_REQDATAVLD2)
10554 
10555 #define S_TRGT1_REQDATAVLD3    11
10556 #define V_TRGT1_REQDATAVLD3(x) ((x) << S_TRGT1_REQDATAVLD3)
10557 #define F_TRGT1_REQDATAVLD3    V_TRGT1_REQDATAVLD3(1U)
10558 
10559 #define S_TRGT1_REQDATAVLD4    10
10560 #define V_TRGT1_REQDATAVLD4(x) ((x) << S_TRGT1_REQDATAVLD4)
10561 #define F_TRGT1_REQDATAVLD4    V_TRGT1_REQDATAVLD4(1U)
10562 
10563 #define S_TRGT1_REQDATAVLD5    9
10564 #define V_TRGT1_REQDATAVLD5(x) ((x) << S_TRGT1_REQDATAVLD5)
10565 #define F_TRGT1_REQDATAVLD5    V_TRGT1_REQDATAVLD5(1U)
10566 
10567 #define S_TRGT1_REQDATAVLD6    8
10568 #define V_TRGT1_REQDATAVLD6(x) ((x) << S_TRGT1_REQDATAVLD6)
10569 #define F_TRGT1_REQDATAVLD6    V_TRGT1_REQDATAVLD6(1U)
10570 
10571 #define S_TRGT1_REQDATAVLD7    4
10572 #define M_TRGT1_REQDATAVLD7    0xfU
10573 #define V_TRGT1_REQDATAVLD7(x) ((x) << S_TRGT1_REQDATAVLD7)
10574 #define G_TRGT1_REQDATAVLD7(x) (((x) >> S_TRGT1_REQDATAVLD7) & M_TRGT1_REQDATAVLD7)
10575 
10576 #define S_TRGT1_REQDATAVLD8    2
10577 #define M_TRGT1_REQDATAVLD8    0x3U
10578 #define V_TRGT1_REQDATAVLD8(x) ((x) << S_TRGT1_REQDATAVLD8)
10579 #define G_TRGT1_REQDATAVLD8(x) (((x) >> S_TRGT1_REQDATAVLD8) & M_TRGT1_REQDATAVLD8)
10580 
10581 #define S_TRGT1_REQDATARDY    1
10582 #define V_TRGT1_REQDATARDY(x) ((x) << S_TRGT1_REQDATARDY)
10583 #define F_TRGT1_REQDATARDY    V_TRGT1_REQDATARDY(1U)
10584 
10585 #define S_TRGT1_REQDATAVLD0    0
10586 #define V_TRGT1_REQDATAVLD0(x) ((x) << S_TRGT1_REQDATAVLD0)
10587 #define F_TRGT1_REQDATAVLD0    V_TRGT1_REQDATAVLD0(1U)
10588 
10589 #define A_PCIE_PDEBUG_REG_0X2A 0x2a
10590 #define A_PCIE_PDEBUG_REG_0X2B 0x2b
10591 
10592 #define S_RADM_TRGT1_ADDR    20
10593 #define M_RADM_TRGT1_ADDR    0xfffU
10594 #define V_RADM_TRGT1_ADDR(x) ((x) << S_RADM_TRGT1_ADDR)
10595 #define G_RADM_TRGT1_ADDR(x) (((x) >> S_RADM_TRGT1_ADDR) & M_RADM_TRGT1_ADDR)
10596 
10597 #define S_RADM_TRGT1_DWEN    16
10598 #define M_RADM_TRGT1_DWEN    0xfU
10599 #define V_RADM_TRGT1_DWEN(x) ((x) << S_RADM_TRGT1_DWEN)
10600 #define G_RADM_TRGT1_DWEN(x) (((x) >> S_RADM_TRGT1_DWEN) & M_RADM_TRGT1_DWEN)
10601 
10602 #define S_RADM_TRGT1_FMT    14
10603 #define M_RADM_TRGT1_FMT    0x3U
10604 #define V_RADM_TRGT1_FMT(x) ((x) << S_RADM_TRGT1_FMT)
10605 #define G_RADM_TRGT1_FMT(x) (((x) >> S_RADM_TRGT1_FMT) & M_RADM_TRGT1_FMT)
10606 
10607 #define S_RADM_TRGT1_TYPE    9
10608 #define M_RADM_TRGT1_TYPE    0x1fU
10609 #define V_RADM_TRGT1_TYPE(x) ((x) << S_RADM_TRGT1_TYPE)
10610 #define G_RADM_TRGT1_TYPE(x) (((x) >> S_RADM_TRGT1_TYPE) & M_RADM_TRGT1_TYPE)
10611 
10612 #define S_RADM_TRGT1_IN_MEMBAR_RANGE    6
10613 #define M_RADM_TRGT1_IN_MEMBAR_RANGE    0x7U
10614 #define V_RADM_TRGT1_IN_MEMBAR_RANGE(x) ((x) << S_RADM_TRGT1_IN_MEMBAR_RANGE)
10615 #define G_RADM_TRGT1_IN_MEMBAR_RANGE(x) (((x) >> S_RADM_TRGT1_IN_MEMBAR_RANGE) & M_RADM_TRGT1_IN_MEMBAR_RANGE)
10616 
10617 #define S_RADM_TRGT1_ECRC_ERR    5
10618 #define V_RADM_TRGT1_ECRC_ERR(x) ((x) << S_RADM_TRGT1_ECRC_ERR)
10619 #define F_RADM_TRGT1_ECRC_ERR    V_RADM_TRGT1_ECRC_ERR(1U)
10620 
10621 #define S_RADM_TRGT1_DLLP_ABORT    4
10622 #define V_RADM_TRGT1_DLLP_ABORT(x) ((x) << S_RADM_TRGT1_DLLP_ABORT)
10623 #define F_RADM_TRGT1_DLLP_ABORT    V_RADM_TRGT1_DLLP_ABORT(1U)
10624 
10625 #define S_RADM_TRGT1_TLP_ABORT    3
10626 #define V_RADM_TRGT1_TLP_ABORT(x) ((x) << S_RADM_TRGT1_TLP_ABORT)
10627 #define F_RADM_TRGT1_TLP_ABORT    V_RADM_TRGT1_TLP_ABORT(1U)
10628 
10629 #define S_RADM_TRGT1_EOT    2
10630 #define V_RADM_TRGT1_EOT(x) ((x) << S_RADM_TRGT1_EOT)
10631 #define F_RADM_TRGT1_EOT    V_RADM_TRGT1_EOT(1U)
10632 
10633 #define S_RADM_TRGT1_DV_2B    1
10634 #define V_RADM_TRGT1_DV_2B(x) ((x) << S_RADM_TRGT1_DV_2B)
10635 #define F_RADM_TRGT1_DV_2B    V_RADM_TRGT1_DV_2B(1U)
10636 
10637 #define S_RADM_TRGT1_HV_2B    0
10638 #define V_RADM_TRGT1_HV_2B(x) ((x) << S_RADM_TRGT1_HV_2B)
10639 #define F_RADM_TRGT1_HV_2B    V_RADM_TRGT1_HV_2B(1U)
10640 
10641 #define A_PCIE_PDEBUG_REG_0X2C 0x2c
10642 
10643 #define S_STATEMPIO    29
10644 #define M_STATEMPIO    0x7U
10645 #define V_STATEMPIO(x) ((x) << S_STATEMPIO)
10646 #define G_STATEMPIO(x) (((x) >> S_STATEMPIO) & M_STATEMPIO)
10647 
10648 #define S_STATECPL    25
10649 #define M_STATECPL    0xfU
10650 #define V_STATECPL(x) ((x) << S_STATECPL)
10651 #define G_STATECPL(x) (((x) >> S_STATECPL) & M_STATECPL)
10652 
10653 #define S_STATEALIN    22
10654 #define M_STATEALIN    0x7U
10655 #define V_STATEALIN(x) ((x) << S_STATEALIN)
10656 #define G_STATEALIN(x) (((x) >> S_STATEALIN) & M_STATEALIN)
10657 
10658 #define S_STATEPL    19
10659 #define M_STATEPL    0x7U
10660 #define V_STATEPL(x) ((x) << S_STATEPL)
10661 #define G_STATEPL(x) (((x) >> S_STATEPL) & M_STATEPL)
10662 
10663 #define S_STATEMARSP    18
10664 #define V_STATEMARSP(x) ((x) << S_STATEMARSP)
10665 #define F_STATEMARSP    V_STATEMARSP(1U)
10666 
10667 #define S_MA_TAGSINUSE    11
10668 #define M_MA_TAGSINUSE    0x7fU
10669 #define V_MA_TAGSINUSE(x) ((x) << S_MA_TAGSINUSE)
10670 #define G_MA_TAGSINUSE(x) (((x) >> S_MA_TAGSINUSE) & M_MA_TAGSINUSE)
10671 
10672 #define S_RADM_TRGT1_HSRDY    10
10673 #define V_RADM_TRGT1_HSRDY(x) ((x) << S_RADM_TRGT1_HSRDY)
10674 #define F_RADM_TRGT1_HSRDY    V_RADM_TRGT1_HSRDY(1U)
10675 
10676 #define S_RADM_TRGT1_DSRDY    9
10677 #define V_RADM_TRGT1_DSRDY(x) ((x) << S_RADM_TRGT1_DSRDY)
10678 #define F_RADM_TRGT1_DSRDY    V_RADM_TRGT1_DSRDY(1U)
10679 
10680 #define S_ALIND_REQWRDATAVLD    8
10681 #define V_ALIND_REQWRDATAVLD(x) ((x) << S_ALIND_REQWRDATAVLD)
10682 #define F_ALIND_REQWRDATAVLD    V_ALIND_REQWRDATAVLD(1U)
10683 
10684 #define S_FID_LKUPWRHDRVLD    7
10685 #define V_FID_LKUPWRHDRVLD(x) ((x) << S_FID_LKUPWRHDRVLD)
10686 #define F_FID_LKUPWRHDRVLD    V_FID_LKUPWRHDRVLD(1U)
10687 
10688 #define S_MPIO_WRVLD    6
10689 #define V_MPIO_WRVLD(x) ((x) << S_MPIO_WRVLD)
10690 #define F_MPIO_WRVLD    V_MPIO_WRVLD(1U)
10691 
10692 #define S_TRGT1_RADM_HALT    5
10693 #define V_TRGT1_RADM_HALT(x) ((x) << S_TRGT1_RADM_HALT)
10694 #define F_TRGT1_RADM_HALT    V_TRGT1_RADM_HALT(1U)
10695 
10696 #define S_RADM_TRGT1_DV_2C    4
10697 #define V_RADM_TRGT1_DV_2C(x) ((x) << S_RADM_TRGT1_DV_2C)
10698 #define F_RADM_TRGT1_DV_2C    V_RADM_TRGT1_DV_2C(1U)
10699 
10700 #define S_RADM_TRGT1_DV_2C_2    3
10701 #define V_RADM_TRGT1_DV_2C_2(x) ((x) << S_RADM_TRGT1_DV_2C_2)
10702 #define F_RADM_TRGT1_DV_2C_2    V_RADM_TRGT1_DV_2C_2(1U)
10703 
10704 #define S_RADM_TRGT1_TLP_ABORT_2C    2
10705 #define V_RADM_TRGT1_TLP_ABORT_2C(x) ((x) << S_RADM_TRGT1_TLP_ABORT_2C)
10706 #define F_RADM_TRGT1_TLP_ABORT_2C    V_RADM_TRGT1_TLP_ABORT_2C(1U)
10707 
10708 #define S_RADM_TRGT1_DLLP_ABORT_2C    1
10709 #define V_RADM_TRGT1_DLLP_ABORT_2C(x) ((x) << S_RADM_TRGT1_DLLP_ABORT_2C)
10710 #define F_RADM_TRGT1_DLLP_ABORT_2C    V_RADM_TRGT1_DLLP_ABORT_2C(1U)
10711 
10712 #define S_RADM_TRGT1_ECRC_ERR_2C    0
10713 #define V_RADM_TRGT1_ECRC_ERR_2C(x) ((x) << S_RADM_TRGT1_ECRC_ERR_2C)
10714 #define F_RADM_TRGT1_ECRC_ERR_2C    V_RADM_TRGT1_ECRC_ERR_2C(1U)
10715 
10716 #define A_PCIE_PDEBUG_REG_0X2D 0x2d
10717 
10718 #define S_RADM_TRGT1_HV_2D    31
10719 #define V_RADM_TRGT1_HV_2D(x) ((x) << S_RADM_TRGT1_HV_2D)
10720 #define F_RADM_TRGT1_HV_2D    V_RADM_TRGT1_HV_2D(1U)
10721 
10722 #define S_RADM_TRGT1_DV_2D    30
10723 #define V_RADM_TRGT1_DV_2D(x) ((x) << S_RADM_TRGT1_DV_2D)
10724 #define F_RADM_TRGT1_DV_2D    V_RADM_TRGT1_DV_2D(1U)
10725 
10726 #define S_RADM_TRGT1_HV2    23
10727 #define M_RADM_TRGT1_HV2    0x7fU
10728 #define V_RADM_TRGT1_HV2(x) ((x) << S_RADM_TRGT1_HV2)
10729 #define G_RADM_TRGT1_HV2(x) (((x) >> S_RADM_TRGT1_HV2) & M_RADM_TRGT1_HV2)
10730 
10731 #define S_RADM_TRGT1_HV3    20
10732 #define M_RADM_TRGT1_HV3    0x7U
10733 #define V_RADM_TRGT1_HV3(x) ((x) << S_RADM_TRGT1_HV3)
10734 #define G_RADM_TRGT1_HV3(x) (((x) >> S_RADM_TRGT1_HV3) & M_RADM_TRGT1_HV3)
10735 
10736 #define S_RADM_TRGT1_HV4    16
10737 #define M_RADM_TRGT1_HV4    0xfU
10738 #define V_RADM_TRGT1_HV4(x) ((x) << S_RADM_TRGT1_HV4)
10739 #define G_RADM_TRGT1_HV4(x) (((x) >> S_RADM_TRGT1_HV4) & M_RADM_TRGT1_HV4)
10740 
10741 #define S_RADM_TRGT1_HV5    12
10742 #define M_RADM_TRGT1_HV5    0xfU
10743 #define V_RADM_TRGT1_HV5(x) ((x) << S_RADM_TRGT1_HV5)
10744 #define G_RADM_TRGT1_HV5(x) (((x) >> S_RADM_TRGT1_HV5) & M_RADM_TRGT1_HV5)
10745 
10746 #define S_RADM_TRGT1_HV6    11
10747 #define V_RADM_TRGT1_HV6(x) ((x) << S_RADM_TRGT1_HV6)
10748 #define F_RADM_TRGT1_HV6    V_RADM_TRGT1_HV6(1U)
10749 
10750 #define S_RADM_TRGT1_HV7    10
10751 #define V_RADM_TRGT1_HV7(x) ((x) << S_RADM_TRGT1_HV7)
10752 #define F_RADM_TRGT1_HV7    V_RADM_TRGT1_HV7(1U)
10753 
10754 #define S_RADM_TRGT1_HV8    7
10755 #define M_RADM_TRGT1_HV8    0x7U
10756 #define V_RADM_TRGT1_HV8(x) ((x) << S_RADM_TRGT1_HV8)
10757 #define G_RADM_TRGT1_HV8(x) (((x) >> S_RADM_TRGT1_HV8) & M_RADM_TRGT1_HV8)
10758 
10759 #define S_RADM_TRGT1_HV9    6
10760 #define V_RADM_TRGT1_HV9(x) ((x) << S_RADM_TRGT1_HV9)
10761 #define F_RADM_TRGT1_HV9    V_RADM_TRGT1_HV9(1U)
10762 
10763 #define S_RADM_TRGT1_HVA    5
10764 #define V_RADM_TRGT1_HVA(x) ((x) << S_RADM_TRGT1_HVA)
10765 #define F_RADM_TRGT1_HVA    V_RADM_TRGT1_HVA(1U)
10766 
10767 #define S_RADM_TRGT1_DSRDY_2D    4
10768 #define V_RADM_TRGT1_DSRDY_2D(x) ((x) << S_RADM_TRGT1_DSRDY_2D)
10769 #define F_RADM_TRGT1_DSRDY_2D    V_RADM_TRGT1_DSRDY_2D(1U)
10770 
10771 #define S_RADM_TRGT1_WRCNT    0
10772 #define M_RADM_TRGT1_WRCNT    0xfU
10773 #define V_RADM_TRGT1_WRCNT(x) ((x) << S_RADM_TRGT1_WRCNT)
10774 #define G_RADM_TRGT1_WRCNT(x) (((x) >> S_RADM_TRGT1_WRCNT) & M_RADM_TRGT1_WRCNT)
10775 
10776 #define A_PCIE_PDEBUG_REG_0X2E 0x2e
10777 
10778 #define S_RADM_TRGT1_HV_2E    30
10779 #define M_RADM_TRGT1_HV_2E    0x3U
10780 #define V_RADM_TRGT1_HV_2E(x) ((x) << S_RADM_TRGT1_HV_2E)
10781 #define G_RADM_TRGT1_HV_2E(x) (((x) >> S_RADM_TRGT1_HV_2E) & M_RADM_TRGT1_HV_2E)
10782 
10783 #define S_RADM_TRGT1_HV_2E_2    20
10784 #define M_RADM_TRGT1_HV_2E_2    0x3ffU
10785 #define V_RADM_TRGT1_HV_2E_2(x) ((x) << S_RADM_TRGT1_HV_2E_2)
10786 #define G_RADM_TRGT1_HV_2E_2(x) (((x) >> S_RADM_TRGT1_HV_2E_2) & M_RADM_TRGT1_HV_2E_2)
10787 
10788 #define S_RADM_TRGT1_HV_WE_3    12
10789 #define M_RADM_TRGT1_HV_WE_3    0xffU
10790 #define V_RADM_TRGT1_HV_WE_3(x) ((x) << S_RADM_TRGT1_HV_WE_3)
10791 #define G_RADM_TRGT1_HV_WE_3(x) (((x) >> S_RADM_TRGT1_HV_WE_3) & M_RADM_TRGT1_HV_WE_3)
10792 
10793 #define S_ALIN_REQDATAVLD4    8
10794 #define M_ALIN_REQDATAVLD4    0xfU
10795 #define V_ALIN_REQDATAVLD4(x) ((x) << S_ALIN_REQDATAVLD4)
10796 #define G_ALIN_REQDATAVLD4(x) (((x) >> S_ALIN_REQDATAVLD4) & M_ALIN_REQDATAVLD4)
10797 
10798 #define S_ALIN_REQDATAVLD5    7
10799 #define V_ALIN_REQDATAVLD5(x) ((x) << S_ALIN_REQDATAVLD5)
10800 #define F_ALIN_REQDATAVLD5    V_ALIN_REQDATAVLD5(1U)
10801 
10802 #define S_ALIN_REQDATAVLD6    6
10803 #define V_ALIN_REQDATAVLD6(x) ((x) << S_ALIN_REQDATAVLD6)
10804 #define F_ALIN_REQDATAVLD6    V_ALIN_REQDATAVLD6(1U)
10805 
10806 #define S_ALIN_REQDATAVLD7    4
10807 #define M_ALIN_REQDATAVLD7    0x3U
10808 #define V_ALIN_REQDATAVLD7(x) ((x) << S_ALIN_REQDATAVLD7)
10809 #define G_ALIN_REQDATAVLD7(x) (((x) >> S_ALIN_REQDATAVLD7) & M_ALIN_REQDATAVLD7)
10810 
10811 #define S_ALIN_REQDATAVLD8    3
10812 #define V_ALIN_REQDATAVLD8(x) ((x) << S_ALIN_REQDATAVLD8)
10813 #define F_ALIN_REQDATAVLD8    V_ALIN_REQDATAVLD8(1U)
10814 
10815 #define S_ALIN_REQDATAVLD9    2
10816 #define V_ALIN_REQDATAVLD9(x) ((x) << S_ALIN_REQDATAVLD9)
10817 #define F_ALIN_REQDATAVLD9    V_ALIN_REQDATAVLD9(1U)
10818 
10819 #define S_ALIN_REQDATARDY    1
10820 #define V_ALIN_REQDATARDY(x) ((x) << S_ALIN_REQDATARDY)
10821 #define F_ALIN_REQDATARDY    V_ALIN_REQDATARDY(1U)
10822 
10823 #define S_ALIN_REQDATAVLDA    0
10824 #define V_ALIN_REQDATAVLDA(x) ((x) << S_ALIN_REQDATAVLDA)
10825 #define F_ALIN_REQDATAVLDA    V_ALIN_REQDATAVLDA(1U)
10826 
10827 #define A_PCIE_PDEBUG_REG_0X2F 0x2f
10828 #define A_PCIE_PDEBUG_REG_0X30 0x30
10829 
10830 #define S_RADM_TRGT1_HV_30    25
10831 #define M_RADM_TRGT1_HV_30    0x7fU
10832 #define V_RADM_TRGT1_HV_30(x) ((x) << S_RADM_TRGT1_HV_30)
10833 #define G_RADM_TRGT1_HV_30(x) (((x) >> S_RADM_TRGT1_HV_30) & M_RADM_TRGT1_HV_30)
10834 
10835 #define S_PIO_WRCNT    15
10836 #define M_PIO_WRCNT    0x3ffU
10837 #define V_PIO_WRCNT(x) ((x) << S_PIO_WRCNT)
10838 #define G_PIO_WRCNT(x) (((x) >> S_PIO_WRCNT) & M_PIO_WRCNT)
10839 
10840 #define S_ALIND_REQWRCNT    12
10841 #define M_ALIND_REQWRCNT    0x7U
10842 #define V_ALIND_REQWRCNT(x) ((x) << S_ALIND_REQWRCNT)
10843 #define G_ALIND_REQWRCNT(x) (((x) >> S_ALIND_REQWRCNT) & M_ALIND_REQWRCNT)
10844 
10845 #define S_FID_LKUPWRCNT    9
10846 #define M_FID_LKUPWRCNT    0x7U
10847 #define V_FID_LKUPWRCNT(x) ((x) << S_FID_LKUPWRCNT)
10848 #define G_FID_LKUPWRCNT(x) (((x) >> S_FID_LKUPWRCNT) & M_FID_LKUPWRCNT)
10849 
10850 #define S_ALIND_REQRDDATAVLD    8
10851 #define V_ALIND_REQRDDATAVLD(x) ((x) << S_ALIND_REQRDDATAVLD)
10852 #define F_ALIND_REQRDDATAVLD    V_ALIND_REQRDDATAVLD(1U)
10853 
10854 #define S_ALIND_REQRDDATARDY    7
10855 #define V_ALIND_REQRDDATARDY(x) ((x) << S_ALIND_REQRDDATARDY)
10856 #define F_ALIND_REQRDDATARDY    V_ALIND_REQRDDATARDY(1U)
10857 
10858 #define S_ALIND_REQRDDATAVLD2    6
10859 #define V_ALIND_REQRDDATAVLD2(x) ((x) << S_ALIND_REQRDDATAVLD2)
10860 #define F_ALIND_REQRDDATAVLD2    V_ALIND_REQRDDATAVLD2(1U)
10861 
10862 #define S_ALIND_REQWRDATAVLD3    3
10863 #define M_ALIND_REQWRDATAVLD3    0x7U
10864 #define V_ALIND_REQWRDATAVLD3(x) ((x) << S_ALIND_REQWRDATAVLD3)
10865 #define G_ALIND_REQWRDATAVLD3(x) (((x) >> S_ALIND_REQWRDATAVLD3) & M_ALIND_REQWRDATAVLD3)
10866 
10867 #define S_ALIND_REQWRDATAVLD4    2
10868 #define V_ALIND_REQWRDATAVLD4(x) ((x) << S_ALIND_REQWRDATAVLD4)
10869 #define F_ALIND_REQWRDATAVLD4    V_ALIND_REQWRDATAVLD4(1U)
10870 
10871 #define S_ALIND_REQWRDATARDYOPEN    1
10872 #define V_ALIND_REQWRDATARDYOPEN(x) ((x) << S_ALIND_REQWRDATARDYOPEN)
10873 #define F_ALIND_REQWRDATARDYOPEN    V_ALIND_REQWRDATARDYOPEN(1U)
10874 
10875 #define S_ALIND_REQWRDATAVLD5    0
10876 #define V_ALIND_REQWRDATAVLD5(x) ((x) << S_ALIND_REQWRDATAVLD5)
10877 #define F_ALIND_REQWRDATAVLD5    V_ALIND_REQWRDATAVLD5(1U)
10878 
10879 #define A_PCIE_PDEBUG_REG_0X31 0x31
10880 #define A_PCIE_PDEBUG_REG_0X32 0x32
10881 #define A_PCIE_PDEBUG_REG_0X33 0x33
10882 #define A_PCIE_PDEBUG_REG_0X34 0x34
10883 #define A_PCIE_PDEBUG_REG_0X35 0x35
10884 
10885 #define S_T5_MPIO_WRVLD    19
10886 #define M_T5_MPIO_WRVLD    0x1fffU
10887 #define V_T5_MPIO_WRVLD(x) ((x) << S_T5_MPIO_WRVLD)
10888 #define G_T5_MPIO_WRVLD(x) (((x) >> S_T5_MPIO_WRVLD) & M_T5_MPIO_WRVLD)
10889 
10890 #define S_FID_LKUPRDHDRVLD    18
10891 #define V_FID_LKUPRDHDRVLD(x) ((x) << S_FID_LKUPRDHDRVLD)
10892 #define F_FID_LKUPRDHDRVLD    V_FID_LKUPRDHDRVLD(1U)
10893 
10894 #define S_FID_LKUPRDHDRVLD2    17
10895 #define V_FID_LKUPRDHDRVLD2(x) ((x) << S_FID_LKUPRDHDRVLD2)
10896 #define F_FID_LKUPRDHDRVLD2    V_FID_LKUPRDHDRVLD2(1U)
10897 
10898 #define S_FID_LKUPRDHDRVLD3    16
10899 #define V_FID_LKUPRDHDRVLD3(x) ((x) << S_FID_LKUPRDHDRVLD3)
10900 #define F_FID_LKUPRDHDRVLD3    V_FID_LKUPRDHDRVLD3(1U)
10901 
10902 #define S_FID_LKUPRDHDRVLD4    15
10903 #define V_FID_LKUPRDHDRVLD4(x) ((x) << S_FID_LKUPRDHDRVLD4)
10904 #define F_FID_LKUPRDHDRVLD4    V_FID_LKUPRDHDRVLD4(1U)
10905 
10906 #define S_FID_LKUPRDHDRVLD5    14
10907 #define V_FID_LKUPRDHDRVLD5(x) ((x) << S_FID_LKUPRDHDRVLD5)
10908 #define F_FID_LKUPRDHDRVLD5    V_FID_LKUPRDHDRVLD5(1U)
10909 
10910 #define S_FID_LKUPRDHDRVLD6    13
10911 #define V_FID_LKUPRDHDRVLD6(x) ((x) << S_FID_LKUPRDHDRVLD6)
10912 #define F_FID_LKUPRDHDRVLD6    V_FID_LKUPRDHDRVLD6(1U)
10913 
10914 #define S_FID_LKUPRDHDRVLD7    12
10915 #define V_FID_LKUPRDHDRVLD7(x) ((x) << S_FID_LKUPRDHDRVLD7)
10916 #define F_FID_LKUPRDHDRVLD7    V_FID_LKUPRDHDRVLD7(1U)
10917 
10918 #define S_FID_LKUPRDHDRVLD8    11
10919 #define V_FID_LKUPRDHDRVLD8(x) ((x) << S_FID_LKUPRDHDRVLD8)
10920 #define F_FID_LKUPRDHDRVLD8    V_FID_LKUPRDHDRVLD8(1U)
10921 
10922 #define S_FID_LKUPRDHDRVLD9    10
10923 #define V_FID_LKUPRDHDRVLD9(x) ((x) << S_FID_LKUPRDHDRVLD9)
10924 #define F_FID_LKUPRDHDRVLD9    V_FID_LKUPRDHDRVLD9(1U)
10925 
10926 #define S_FID_LKUPRDHDRVLDA    9
10927 #define V_FID_LKUPRDHDRVLDA(x) ((x) << S_FID_LKUPRDHDRVLDA)
10928 #define F_FID_LKUPRDHDRVLDA    V_FID_LKUPRDHDRVLDA(1U)
10929 
10930 #define S_FID_LKUPRDHDRVLDB    8
10931 #define V_FID_LKUPRDHDRVLDB(x) ((x) << S_FID_LKUPRDHDRVLDB)
10932 #define F_FID_LKUPRDHDRVLDB    V_FID_LKUPRDHDRVLDB(1U)
10933 
10934 #define S_FID_LKUPRDHDRVLDC    7
10935 #define V_FID_LKUPRDHDRVLDC(x) ((x) << S_FID_LKUPRDHDRVLDC)
10936 #define F_FID_LKUPRDHDRVLDC    V_FID_LKUPRDHDRVLDC(1U)
10937 
10938 #define S_MPIO_WRVLD1    6
10939 #define V_MPIO_WRVLD1(x) ((x) << S_MPIO_WRVLD1)
10940 #define F_MPIO_WRVLD1    V_MPIO_WRVLD1(1U)
10941 
10942 #define S_MPIO_WRVLD2    5
10943 #define V_MPIO_WRVLD2(x) ((x) << S_MPIO_WRVLD2)
10944 #define F_MPIO_WRVLD2    V_MPIO_WRVLD2(1U)
10945 
10946 #define S_MPIO_WRVLD3    4
10947 #define V_MPIO_WRVLD3(x) ((x) << S_MPIO_WRVLD3)
10948 #define F_MPIO_WRVLD3    V_MPIO_WRVLD3(1U)
10949 
10950 #define S_MPIO_WRVLD4    0
10951 #define M_MPIO_WRVLD4    0xfU
10952 #define V_MPIO_WRVLD4(x) ((x) << S_MPIO_WRVLD4)
10953 #define G_MPIO_WRVLD4(x) (((x) >> S_MPIO_WRVLD4) & M_MPIO_WRVLD4)
10954 
10955 #define A_PCIE_PDEBUG_REG_0X36 0x36
10956 #define A_PCIE_PDEBUG_REG_0X37 0x37
10957 #define A_PCIE_PDEBUG_REG_0X38 0x38
10958 #define A_PCIE_PDEBUG_REG_0X39 0x39
10959 #define A_PCIE_PDEBUG_REG_0X3A 0x3a
10960 
10961 #define S_CLIENT0_TLP_VFUNC_ACTIVE    31
10962 #define V_CLIENT0_TLP_VFUNC_ACTIVE(x) ((x) << S_CLIENT0_TLP_VFUNC_ACTIVE)
10963 #define F_CLIENT0_TLP_VFUNC_ACTIVE    V_CLIENT0_TLP_VFUNC_ACTIVE(1U)
10964 
10965 #define S_CLIENT0_TLP_VFUNC_NUM    24
10966 #define M_CLIENT0_TLP_VFUNC_NUM    0x7fU
10967 #define V_CLIENT0_TLP_VFUNC_NUM(x) ((x) << S_CLIENT0_TLP_VFUNC_NUM)
10968 #define G_CLIENT0_TLP_VFUNC_NUM(x) (((x) >> S_CLIENT0_TLP_VFUNC_NUM) & M_CLIENT0_TLP_VFUNC_NUM)
10969 
10970 #define S_CLIENT0_TLP_FUNC_NUM    21
10971 #define M_CLIENT0_TLP_FUNC_NUM    0x7U
10972 #define V_CLIENT0_TLP_FUNC_NUM(x) ((x) << S_CLIENT0_TLP_FUNC_NUM)
10973 #define G_CLIENT0_TLP_FUNC_NUM(x) (((x) >> S_CLIENT0_TLP_FUNC_NUM) & M_CLIENT0_TLP_FUNC_NUM)
10974 
10975 #define S_CLIENT0_TLP_BYTE_EN    13
10976 #define M_CLIENT0_TLP_BYTE_EN    0xffU
10977 #define V_CLIENT0_TLP_BYTE_EN(x) ((x) << S_CLIENT0_TLP_BYTE_EN)
10978 #define G_CLIENT0_TLP_BYTE_EN(x) (((x) >> S_CLIENT0_TLP_BYTE_EN) & M_CLIENT0_TLP_BYTE_EN)
10979 
10980 #define S_CLIENT0_TLP_BYTE_LEN    0
10981 #define M_CLIENT0_TLP_BYTE_LEN    0x1fffU
10982 #define V_CLIENT0_TLP_BYTE_LEN(x) ((x) << S_CLIENT0_TLP_BYTE_LEN)
10983 #define G_CLIENT0_TLP_BYTE_LEN(x) (((x) >> S_CLIENT0_TLP_BYTE_LEN) & M_CLIENT0_TLP_BYTE_LEN)
10984 
10985 #define A_PCIE_PDEBUG_REG_0X3B 0x3b
10986 
10987 #define S_XADM_CLIENT0_HALT    31
10988 #define V_XADM_CLIENT0_HALT(x) ((x) << S_XADM_CLIENT0_HALT)
10989 #define F_XADM_CLIENT0_HALT    V_XADM_CLIENT0_HALT(1U)
10990 
10991 #define S_CLIENT0_TLP_DV    30
10992 #define V_CLIENT0_TLP_DV(x) ((x) << S_CLIENT0_TLP_DV)
10993 #define F_CLIENT0_TLP_DV    V_CLIENT0_TLP_DV(1U)
10994 
10995 #define S_CLIENT0_ADDR_ALIGN_EN    29
10996 #define V_CLIENT0_ADDR_ALIGN_EN(x) ((x) << S_CLIENT0_ADDR_ALIGN_EN)
10997 #define F_CLIENT0_ADDR_ALIGN_EN    V_CLIENT0_ADDR_ALIGN_EN(1U)
10998 
10999 #define S_CLIENT0_CPL_BCM    28
11000 #define V_CLIENT0_CPL_BCM(x) ((x) << S_CLIENT0_CPL_BCM)
11001 #define F_CLIENT0_CPL_BCM    V_CLIENT0_CPL_BCM(1U)
11002 
11003 #define S_CLIENT0_TLP_EP    27
11004 #define V_CLIENT0_TLP_EP(x) ((x) << S_CLIENT0_TLP_EP)
11005 #define F_CLIENT0_TLP_EP    V_CLIENT0_TLP_EP(1U)
11006 
11007 #define S_CLIENT0_CPL_STATUS    24
11008 #define M_CLIENT0_CPL_STATUS    0x7U
11009 #define V_CLIENT0_CPL_STATUS(x) ((x) << S_CLIENT0_CPL_STATUS)
11010 #define G_CLIENT0_CPL_STATUS(x) (((x) >> S_CLIENT0_CPL_STATUS) & M_CLIENT0_CPL_STATUS)
11011 
11012 #define S_CLIENT0_TLP_TD    23
11013 #define V_CLIENT0_TLP_TD(x) ((x) << S_CLIENT0_TLP_TD)
11014 #define F_CLIENT0_TLP_TD    V_CLIENT0_TLP_TD(1U)
11015 
11016 #define S_CLIENT0_TLP_TYPE    18
11017 #define M_CLIENT0_TLP_TYPE    0x1fU
11018 #define V_CLIENT0_TLP_TYPE(x) ((x) << S_CLIENT0_TLP_TYPE)
11019 #define G_CLIENT0_TLP_TYPE(x) (((x) >> S_CLIENT0_TLP_TYPE) & M_CLIENT0_TLP_TYPE)
11020 
11021 #define S_CLIENT0_TLP_FMT    16
11022 #define M_CLIENT0_TLP_FMT    0x3U
11023 #define V_CLIENT0_TLP_FMT(x) ((x) << S_CLIENT0_TLP_FMT)
11024 #define G_CLIENT0_TLP_FMT(x) (((x) >> S_CLIENT0_TLP_FMT) & M_CLIENT0_TLP_FMT)
11025 
11026 #define S_CLIENT0_TLP_BAD_EOT    15
11027 #define V_CLIENT0_TLP_BAD_EOT(x) ((x) << S_CLIENT0_TLP_BAD_EOT)
11028 #define F_CLIENT0_TLP_BAD_EOT    V_CLIENT0_TLP_BAD_EOT(1U)
11029 
11030 #define S_CLIENT0_TLP_EOT    14
11031 #define V_CLIENT0_TLP_EOT(x) ((x) << S_CLIENT0_TLP_EOT)
11032 #define F_CLIENT0_TLP_EOT    V_CLIENT0_TLP_EOT(1U)
11033 
11034 #define S_CLIENT0_TLP_ATTR    11
11035 #define M_CLIENT0_TLP_ATTR    0x7U
11036 #define V_CLIENT0_TLP_ATTR(x) ((x) << S_CLIENT0_TLP_ATTR)
11037 #define G_CLIENT0_TLP_ATTR(x) (((x) >> S_CLIENT0_TLP_ATTR) & M_CLIENT0_TLP_ATTR)
11038 
11039 #define S_CLIENT0_TLP_TC    8
11040 #define M_CLIENT0_TLP_TC    0x7U
11041 #define V_CLIENT0_TLP_TC(x) ((x) << S_CLIENT0_TLP_TC)
11042 #define G_CLIENT0_TLP_TC(x) (((x) >> S_CLIENT0_TLP_TC) & M_CLIENT0_TLP_TC)
11043 
11044 #define S_CLIENT0_TLP_TID    0
11045 #define M_CLIENT0_TLP_TID    0xffU
11046 #define V_CLIENT0_TLP_TID(x) ((x) << S_CLIENT0_TLP_TID)
11047 #define G_CLIENT0_TLP_TID(x) (((x) >> S_CLIENT0_TLP_TID) & M_CLIENT0_TLP_TID)
11048 
11049 #define A_PCIE_PDEBUG_REG_0X3C 0x3c
11050 
11051 #define S_MEM_RSPRRAVLD    31
11052 #define V_MEM_RSPRRAVLD(x) ((x) << S_MEM_RSPRRAVLD)
11053 #define F_MEM_RSPRRAVLD    V_MEM_RSPRRAVLD(1U)
11054 
11055 #define S_MEM_RSPRRARDY    30
11056 #define V_MEM_RSPRRARDY(x) ((x) << S_MEM_RSPRRARDY)
11057 #define F_MEM_RSPRRARDY    V_MEM_RSPRRARDY(1U)
11058 
11059 #define S_PIO_RSPRRAVLD    29
11060 #define V_PIO_RSPRRAVLD(x) ((x) << S_PIO_RSPRRAVLD)
11061 #define F_PIO_RSPRRAVLD    V_PIO_RSPRRAVLD(1U)
11062 
11063 #define S_PIO_RSPRRARDY    28
11064 #define V_PIO_RSPRRARDY(x) ((x) << S_PIO_RSPRRARDY)
11065 #define F_PIO_RSPRRARDY    V_PIO_RSPRRARDY(1U)
11066 
11067 #define S_MEM_RSPRDVLD    27
11068 #define V_MEM_RSPRDVLD(x) ((x) << S_MEM_RSPRDVLD)
11069 #define F_MEM_RSPRDVLD    V_MEM_RSPRDVLD(1U)
11070 
11071 #define S_MEM_RSPRDRRARDY    26
11072 #define V_MEM_RSPRDRRARDY(x) ((x) << S_MEM_RSPRDRRARDY)
11073 #define F_MEM_RSPRDRRARDY    V_MEM_RSPRDRRARDY(1U)
11074 
11075 #define S_PIO_RSPRDVLD    25
11076 #define V_PIO_RSPRDVLD(x) ((x) << S_PIO_RSPRDVLD)
11077 #define F_PIO_RSPRDVLD    V_PIO_RSPRDVLD(1U)
11078 
11079 #define S_PIO_RSPRDRRARDY    24
11080 #define V_PIO_RSPRDRRARDY(x) ((x) << S_PIO_RSPRDRRARDY)
11081 #define F_PIO_RSPRDRRARDY    V_PIO_RSPRDRRARDY(1U)
11082 
11083 #define S_TGT_TAGQ_RDVLD    16
11084 #define M_TGT_TAGQ_RDVLD    0xffU
11085 #define V_TGT_TAGQ_RDVLD(x) ((x) << S_TGT_TAGQ_RDVLD)
11086 #define G_TGT_TAGQ_RDVLD(x) (((x) >> S_TGT_TAGQ_RDVLD) & M_TGT_TAGQ_RDVLD)
11087 
11088 #define S_CPLTXNDISABLE    8
11089 #define M_CPLTXNDISABLE    0xffU
11090 #define V_CPLTXNDISABLE(x) ((x) << S_CPLTXNDISABLE)
11091 #define G_CPLTXNDISABLE(x) (((x) >> S_CPLTXNDISABLE) & M_CPLTXNDISABLE)
11092 
11093 #define S_CPLTXNDISABLE2    7
11094 #define V_CPLTXNDISABLE2(x) ((x) << S_CPLTXNDISABLE2)
11095 #define F_CPLTXNDISABLE2    V_CPLTXNDISABLE2(1U)
11096 
11097 #define S_CLIENT0_TLP_HV    0
11098 #define M_CLIENT0_TLP_HV    0x7fU
11099 #define V_CLIENT0_TLP_HV(x) ((x) << S_CLIENT0_TLP_HV)
11100 #define G_CLIENT0_TLP_HV(x) (((x) >> S_CLIENT0_TLP_HV) & M_CLIENT0_TLP_HV)
11101 
11102 #define A_PCIE_PDEBUG_REG_0X3D 0x3d
11103 #define A_PCIE_PDEBUG_REG_0X3E 0x3e
11104 #define A_PCIE_PDEBUG_REG_0X3F 0x3f
11105 #define A_PCIE_PDEBUG_REG_0X40 0x40
11106 #define A_PCIE_PDEBUG_REG_0X41 0x41
11107 #define A_PCIE_PDEBUG_REG_0X42 0x42
11108 #define A_PCIE_PDEBUG_REG_0X43 0x43
11109 #define A_PCIE_PDEBUG_REG_0X44 0x44
11110 #define A_PCIE_PDEBUG_REG_0X45 0x45
11111 #define A_PCIE_PDEBUG_REG_0X46 0x46
11112 #define A_PCIE_PDEBUG_REG_0X47 0x47
11113 #define A_PCIE_PDEBUG_REG_0X48 0x48
11114 #define A_PCIE_PDEBUG_REG_0X49 0x49
11115 #define A_PCIE_PDEBUG_REG_0X4A 0x4a
11116 #define A_PCIE_PDEBUG_REG_0X4B 0x4b
11117 #define A_PCIE_PDEBUG_REG_0X4C 0x4c
11118 #define A_PCIE_PDEBUG_REG_0X4D 0x4d
11119 #define A_PCIE_PDEBUG_REG_0X4E 0x4e
11120 #define A_PCIE_PDEBUG_REG_0X4F 0x4f
11121 #define A_PCIE_PDEBUG_REG_0X50 0x50
11122 #define A_PCIE_CDEBUG_REG_0X0 0x0
11123 #define A_PCIE_CDEBUG_REG_0X1 0x1
11124 #define A_PCIE_CDEBUG_REG_0X2 0x2
11125 
11126 #define S_FLR_REQVLD    31
11127 #define V_FLR_REQVLD(x) ((x) << S_FLR_REQVLD)
11128 #define F_FLR_REQVLD    V_FLR_REQVLD(1U)
11129 
11130 #define S_D_RSPVLD    28
11131 #define M_D_RSPVLD    0x7U
11132 #define V_D_RSPVLD(x) ((x) << S_D_RSPVLD)
11133 #define G_D_RSPVLD(x) (((x) >> S_D_RSPVLD) & M_D_RSPVLD)
11134 
11135 #define S_D_RSPVLD2    27
11136 #define V_D_RSPVLD2(x) ((x) << S_D_RSPVLD2)
11137 #define F_D_RSPVLD2    V_D_RSPVLD2(1U)
11138 
11139 #define S_D_RSPVLD3    26
11140 #define V_D_RSPVLD3(x) ((x) << S_D_RSPVLD3)
11141 #define F_D_RSPVLD3    V_D_RSPVLD3(1U)
11142 
11143 #define S_D_RSPVLD4    25
11144 #define V_D_RSPVLD4(x) ((x) << S_D_RSPVLD4)
11145 #define F_D_RSPVLD4    V_D_RSPVLD4(1U)
11146 
11147 #define S_D_RSPVLD5    24
11148 #define V_D_RSPVLD5(x) ((x) << S_D_RSPVLD5)
11149 #define F_D_RSPVLD5    V_D_RSPVLD5(1U)
11150 
11151 #define S_D_RSPVLD6    20
11152 #define M_D_RSPVLD6    0xfU
11153 #define V_D_RSPVLD6(x) ((x) << S_D_RSPVLD6)
11154 #define G_D_RSPVLD6(x) (((x) >> S_D_RSPVLD6) & M_D_RSPVLD6)
11155 
11156 #define S_D_RSPAFULL    16
11157 #define M_D_RSPAFULL    0xfU
11158 #define V_D_RSPAFULL(x) ((x) << S_D_RSPAFULL)
11159 #define G_D_RSPAFULL(x) (((x) >> S_D_RSPAFULL) & M_D_RSPAFULL)
11160 
11161 #define S_D_RDREQVLD    12
11162 #define M_D_RDREQVLD    0xfU
11163 #define V_D_RDREQVLD(x) ((x) << S_D_RDREQVLD)
11164 #define G_D_RDREQVLD(x) (((x) >> S_D_RDREQVLD) & M_D_RDREQVLD)
11165 
11166 #define S_D_RDREQAFULL    8
11167 #define M_D_RDREQAFULL    0xfU
11168 #define V_D_RDREQAFULL(x) ((x) << S_D_RDREQAFULL)
11169 #define G_D_RDREQAFULL(x) (((x) >> S_D_RDREQAFULL) & M_D_RDREQAFULL)
11170 
11171 #define S_D_WRREQVLD    4
11172 #define M_D_WRREQVLD    0xfU
11173 #define V_D_WRREQVLD(x) ((x) << S_D_WRREQVLD)
11174 #define G_D_WRREQVLD(x) (((x) >> S_D_WRREQVLD) & M_D_WRREQVLD)
11175 
11176 #define S_D_WRREQAFULL    0
11177 #define M_D_WRREQAFULL    0xfU
11178 #define V_D_WRREQAFULL(x) ((x) << S_D_WRREQAFULL)
11179 #define G_D_WRREQAFULL(x) (((x) >> S_D_WRREQAFULL) & M_D_WRREQAFULL)
11180 
11181 #define A_PCIE_CDEBUG_REG_0X3 0x3
11182 
11183 #define S_C_REQVLD    19
11184 #define M_C_REQVLD    0x1fffU
11185 #define V_C_REQVLD(x) ((x) << S_C_REQVLD)
11186 #define G_C_REQVLD(x) (((x) >> S_C_REQVLD) & M_C_REQVLD)
11187 
11188 #define S_C_RSPVLD2    16
11189 #define M_C_RSPVLD2    0x7U
11190 #define V_C_RSPVLD2(x) ((x) << S_C_RSPVLD2)
11191 #define G_C_RSPVLD2(x) (((x) >> S_C_RSPVLD2) & M_C_RSPVLD2)
11192 
11193 #define S_C_RSPVLD3    15
11194 #define V_C_RSPVLD3(x) ((x) << S_C_RSPVLD3)
11195 #define F_C_RSPVLD3    V_C_RSPVLD3(1U)
11196 
11197 #define S_C_RSPVLD4    14
11198 #define V_C_RSPVLD4(x) ((x) << S_C_RSPVLD4)
11199 #define F_C_RSPVLD4    V_C_RSPVLD4(1U)
11200 
11201 #define S_C_RSPVLD5    13
11202 #define V_C_RSPVLD5(x) ((x) << S_C_RSPVLD5)
11203 #define F_C_RSPVLD5    V_C_RSPVLD5(1U)
11204 
11205 #define S_C_RSPVLD6    12
11206 #define V_C_RSPVLD6(x) ((x) << S_C_RSPVLD6)
11207 #define F_C_RSPVLD6    V_C_RSPVLD6(1U)
11208 
11209 #define S_C_RSPVLD7    9
11210 #define M_C_RSPVLD7    0x7U
11211 #define V_C_RSPVLD7(x) ((x) << S_C_RSPVLD7)
11212 #define G_C_RSPVLD7(x) (((x) >> S_C_RSPVLD7) & M_C_RSPVLD7)
11213 
11214 #define S_C_RSPAFULL    6
11215 #define M_C_RSPAFULL    0x7U
11216 #define V_C_RSPAFULL(x) ((x) << S_C_RSPAFULL)
11217 #define G_C_RSPAFULL(x) (((x) >> S_C_RSPAFULL) & M_C_RSPAFULL)
11218 
11219 #define S_C_REQVLD8    3
11220 #define M_C_REQVLD8    0x7U
11221 #define V_C_REQVLD8(x) ((x) << S_C_REQVLD8)
11222 #define G_C_REQVLD8(x) (((x) >> S_C_REQVLD8) & M_C_REQVLD8)
11223 
11224 #define S_C_REQAFULL    0
11225 #define M_C_REQAFULL    0x7U
11226 #define V_C_REQAFULL(x) ((x) << S_C_REQAFULL)
11227 #define G_C_REQAFULL(x) (((x) >> S_C_REQAFULL) & M_C_REQAFULL)
11228 
11229 #define A_PCIE_CDEBUG_REG_0X4 0x4
11230 
11231 #define S_H_REQVLD    7
11232 #define M_H_REQVLD    0x1ffffffU
11233 #define V_H_REQVLD(x) ((x) << S_H_REQVLD)
11234 #define G_H_REQVLD(x) (((x) >> S_H_REQVLD) & M_H_REQVLD)
11235 
11236 #define S_H_RSPVLD    6
11237 #define V_H_RSPVLD(x) ((x) << S_H_RSPVLD)
11238 #define F_H_RSPVLD    V_H_RSPVLD(1U)
11239 
11240 #define S_H_RSPVLD2    5
11241 #define V_H_RSPVLD2(x) ((x) << S_H_RSPVLD2)
11242 #define F_H_RSPVLD2    V_H_RSPVLD2(1U)
11243 
11244 #define S_H_RSPVLD3    4
11245 #define V_H_RSPVLD3(x) ((x) << S_H_RSPVLD3)
11246 #define F_H_RSPVLD3    V_H_RSPVLD3(1U)
11247 
11248 #define S_H_RSPVLD4    3
11249 #define V_H_RSPVLD4(x) ((x) << S_H_RSPVLD4)
11250 #define F_H_RSPVLD4    V_H_RSPVLD4(1U)
11251 
11252 #define S_H_RSPAFULL    2
11253 #define V_H_RSPAFULL(x) ((x) << S_H_RSPAFULL)
11254 #define F_H_RSPAFULL    V_H_RSPAFULL(1U)
11255 
11256 #define S_H_REQVLD2    1
11257 #define V_H_REQVLD2(x) ((x) << S_H_REQVLD2)
11258 #define F_H_REQVLD2    V_H_REQVLD2(1U)
11259 
11260 #define S_H_REQAFULL    0
11261 #define V_H_REQAFULL(x) ((x) << S_H_REQAFULL)
11262 #define F_H_REQAFULL    V_H_REQAFULL(1U)
11263 
11264 #define A_PCIE_CDEBUG_REG_0X5 0x5
11265 
11266 #define S_ER_RSPVLD    16
11267 #define M_ER_RSPVLD    0xffffU
11268 #define V_ER_RSPVLD(x) ((x) << S_ER_RSPVLD)
11269 #define G_ER_RSPVLD(x) (((x) >> S_ER_RSPVLD) & M_ER_RSPVLD)
11270 
11271 #define S_ER_REQVLD2    5
11272 #define M_ER_REQVLD2    0x7ffU
11273 #define V_ER_REQVLD2(x) ((x) << S_ER_REQVLD2)
11274 #define G_ER_REQVLD2(x) (((x) >> S_ER_REQVLD2) & M_ER_REQVLD2)
11275 
11276 #define S_ER_REQVLD3    2
11277 #define M_ER_REQVLD3    0x7U
11278 #define V_ER_REQVLD3(x) ((x) << S_ER_REQVLD3)
11279 #define G_ER_REQVLD3(x) (((x) >> S_ER_REQVLD3) & M_ER_REQVLD3)
11280 
11281 #define S_ER_RSPVLD4    1
11282 #define V_ER_RSPVLD4(x) ((x) << S_ER_RSPVLD4)
11283 #define F_ER_RSPVLD4    V_ER_RSPVLD4(1U)
11284 
11285 #define S_ER_REQVLD5    0
11286 #define V_ER_REQVLD5(x) ((x) << S_ER_REQVLD5)
11287 #define F_ER_REQVLD5    V_ER_REQVLD5(1U)
11288 
11289 #define A_PCIE_CDEBUG_REG_0X6 0x6
11290 
11291 #define S_PL_BAR2_REQVLD    4
11292 #define M_PL_BAR2_REQVLD    0xfffffffU
11293 #define V_PL_BAR2_REQVLD(x) ((x) << S_PL_BAR2_REQVLD)
11294 #define G_PL_BAR2_REQVLD(x) (((x) >> S_PL_BAR2_REQVLD) & M_PL_BAR2_REQVLD)
11295 
11296 #define S_PL_BAR2_REQVLD2    3
11297 #define V_PL_BAR2_REQVLD2(x) ((x) << S_PL_BAR2_REQVLD2)
11298 #define F_PL_BAR2_REQVLD2    V_PL_BAR2_REQVLD2(1U)
11299 
11300 #define S_PL_BAR2_REQVLDE    2
11301 #define V_PL_BAR2_REQVLDE(x) ((x) << S_PL_BAR2_REQVLDE)
11302 #define F_PL_BAR2_REQVLDE    V_PL_BAR2_REQVLDE(1U)
11303 
11304 #define S_PL_BAR2_REQFULL    1
11305 #define V_PL_BAR2_REQFULL(x) ((x) << S_PL_BAR2_REQFULL)
11306 #define F_PL_BAR2_REQFULL    V_PL_BAR2_REQFULL(1U)
11307 
11308 #define S_PL_BAR2_REQVLD4    0
11309 #define V_PL_BAR2_REQVLD4(x) ((x) << S_PL_BAR2_REQVLD4)
11310 #define F_PL_BAR2_REQVLD4    V_PL_BAR2_REQVLD4(1U)
11311 
11312 #define A_PCIE_CDEBUG_REG_0X7 0x7
11313 #define A_PCIE_CDEBUG_REG_0X8 0x8
11314 #define A_PCIE_CDEBUG_REG_0X9 0x9
11315 #define A_PCIE_CDEBUG_REG_0XA 0xa
11316 
11317 #define S_VPD_RSPVLD    20
11318 #define M_VPD_RSPVLD    0xfffU
11319 #define V_VPD_RSPVLD(x) ((x) << S_VPD_RSPVLD)
11320 #define G_VPD_RSPVLD(x) (((x) >> S_VPD_RSPVLD) & M_VPD_RSPVLD)
11321 
11322 #define S_VPD_REQVLD2    9
11323 #define M_VPD_REQVLD2    0x7ffU
11324 #define V_VPD_REQVLD2(x) ((x) << S_VPD_REQVLD2)
11325 #define G_VPD_REQVLD2(x) (((x) >> S_VPD_REQVLD2) & M_VPD_REQVLD2)
11326 
11327 #define S_VPD_REQVLD3    6
11328 #define M_VPD_REQVLD3    0x7U
11329 #define V_VPD_REQVLD3(x) ((x) << S_VPD_REQVLD3)
11330 #define G_VPD_REQVLD3(x) (((x) >> S_VPD_REQVLD3) & M_VPD_REQVLD3)
11331 
11332 #define S_VPD_REQVLD4    5
11333 #define V_VPD_REQVLD4(x) ((x) << S_VPD_REQVLD4)
11334 #define F_VPD_REQVLD4    V_VPD_REQVLD4(1U)
11335 
11336 #define S_VPD_REQVLD5    3
11337 #define M_VPD_REQVLD5    0x3U
11338 #define V_VPD_REQVLD5(x) ((x) << S_VPD_REQVLD5)
11339 #define G_VPD_REQVLD5(x) (((x) >> S_VPD_REQVLD5) & M_VPD_REQVLD5)
11340 
11341 #define S_VPD_RSPVLD2    2
11342 #define V_VPD_RSPVLD2(x) ((x) << S_VPD_RSPVLD2)
11343 #define F_VPD_RSPVLD2    V_VPD_RSPVLD2(1U)
11344 
11345 #define S_VPD_RSPVLD3    1
11346 #define V_VPD_RSPVLD3(x) ((x) << S_VPD_RSPVLD3)
11347 #define F_VPD_RSPVLD3    V_VPD_RSPVLD3(1U)
11348 
11349 #define S_VPD_REQVLD6    0
11350 #define V_VPD_REQVLD6(x) ((x) << S_VPD_REQVLD6)
11351 #define F_VPD_REQVLD6    V_VPD_REQVLD6(1U)
11352 
11353 #define A_PCIE_CDEBUG_REG_0XB 0xb
11354 
11355 #define S_MA_REQDATAVLD    28
11356 #define M_MA_REQDATAVLD    0xfU
11357 #define V_MA_REQDATAVLD(x) ((x) << S_MA_REQDATAVLD)
11358 #define G_MA_REQDATAVLD(x) (((x) >> S_MA_REQDATAVLD) & M_MA_REQDATAVLD)
11359 
11360 #define S_MA_REQADDRVLD    27
11361 #define V_MA_REQADDRVLD(x) ((x) << S_MA_REQADDRVLD)
11362 #define F_MA_REQADDRVLD    V_MA_REQADDRVLD(1U)
11363 
11364 #define S_MA_REQADDRVLD2    26
11365 #define V_MA_REQADDRVLD2(x) ((x) << S_MA_REQADDRVLD2)
11366 #define F_MA_REQADDRVLD2    V_MA_REQADDRVLD2(1U)
11367 
11368 #define S_MA_RSPDATAVLD2    22
11369 #define M_MA_RSPDATAVLD2    0xfU
11370 #define V_MA_RSPDATAVLD2(x) ((x) << S_MA_RSPDATAVLD2)
11371 #define G_MA_RSPDATAVLD2(x) (((x) >> S_MA_RSPDATAVLD2) & M_MA_RSPDATAVLD2)
11372 
11373 #define S_MA_REQADDRVLD3    20
11374 #define M_MA_REQADDRVLD3    0x3U
11375 #define V_MA_REQADDRVLD3(x) ((x) << S_MA_REQADDRVLD3)
11376 #define G_MA_REQADDRVLD3(x) (((x) >> S_MA_REQADDRVLD3) & M_MA_REQADDRVLD3)
11377 
11378 #define S_MA_REQADDRVLD4    4
11379 #define M_MA_REQADDRVLD4    0xffffU
11380 #define V_MA_REQADDRVLD4(x) ((x) << S_MA_REQADDRVLD4)
11381 #define G_MA_REQADDRVLD4(x) (((x) >> S_MA_REQADDRVLD4) & M_MA_REQADDRVLD4)
11382 
11383 #define S_MA_REQADDRVLD5    3
11384 #define V_MA_REQADDRVLD5(x) ((x) << S_MA_REQADDRVLD5)
11385 #define F_MA_REQADDRVLD5    V_MA_REQADDRVLD5(1U)
11386 
11387 #define S_MA_REQADDRVLD6    2
11388 #define V_MA_REQADDRVLD6(x) ((x) << S_MA_REQADDRVLD6)
11389 #define F_MA_REQADDRVLD6    V_MA_REQADDRVLD6(1U)
11390 
11391 #define S_MA_REQADDRRDY    1
11392 #define V_MA_REQADDRRDY(x) ((x) << S_MA_REQADDRRDY)
11393 #define F_MA_REQADDRRDY    V_MA_REQADDRRDY(1U)
11394 
11395 #define S_MA_REQADDRVLD7    0
11396 #define V_MA_REQADDRVLD7(x) ((x) << S_MA_REQADDRVLD7)
11397 #define F_MA_REQADDRVLD7    V_MA_REQADDRVLD7(1U)
11398 
11399 #define A_PCIE_CDEBUG_REG_0XC 0xc
11400 #define A_PCIE_CDEBUG_REG_0XD 0xd
11401 #define A_PCIE_CDEBUG_REG_0XE 0xe
11402 #define A_PCIE_CDEBUG_REG_0XF 0xf
11403 #define A_PCIE_CDEBUG_REG_0X10 0x10
11404 #define A_PCIE_CDEBUG_REG_0X11 0x11
11405 #define A_PCIE_CDEBUG_REG_0X12 0x12
11406 #define A_PCIE_CDEBUG_REG_0X13 0x13
11407 #define A_PCIE_CDEBUG_REG_0X14 0x14
11408 #define A_PCIE_CDEBUG_REG_0X15 0x15
11409 
11410 #define S_PLM_REQVLD    19
11411 #define M_PLM_REQVLD    0x1fffU
11412 #define V_PLM_REQVLD(x) ((x) << S_PLM_REQVLD)
11413 #define G_PLM_REQVLD(x) (((x) >> S_PLM_REQVLD) & M_PLM_REQVLD)
11414 
11415 #define S_PLM_REQVLD2    18
11416 #define V_PLM_REQVLD2(x) ((x) << S_PLM_REQVLD2)
11417 #define F_PLM_REQVLD2    V_PLM_REQVLD2(1U)
11418 
11419 #define S_PLM_RSPVLD3    17
11420 #define V_PLM_RSPVLD3(x) ((x) << S_PLM_RSPVLD3)
11421 #define F_PLM_RSPVLD3    V_PLM_RSPVLD3(1U)
11422 
11423 #define S_PLM_REQVLD4    16
11424 #define V_PLM_REQVLD4(x) ((x) << S_PLM_REQVLD4)
11425 #define F_PLM_REQVLD4    V_PLM_REQVLD4(1U)
11426 
11427 #define S_PLM_REQVLD5    15
11428 #define V_PLM_REQVLD5(x) ((x) << S_PLM_REQVLD5)
11429 #define F_PLM_REQVLD5    V_PLM_REQVLD5(1U)
11430 
11431 #define S_PLM_REQVLD6    14
11432 #define V_PLM_REQVLD6(x) ((x) << S_PLM_REQVLD6)
11433 #define F_PLM_REQVLD6    V_PLM_REQVLD6(1U)
11434 
11435 #define S_PLM_REQVLD7    13
11436 #define V_PLM_REQVLD7(x) ((x) << S_PLM_REQVLD7)
11437 #define F_PLM_REQVLD7    V_PLM_REQVLD7(1U)
11438 
11439 #define S_PLM_REQVLD8    12
11440 #define V_PLM_REQVLD8(x) ((x) << S_PLM_REQVLD8)
11441 #define F_PLM_REQVLD8    V_PLM_REQVLD8(1U)
11442 
11443 #define S_PLM_REQVLD9    4
11444 #define M_PLM_REQVLD9    0xffU
11445 #define V_PLM_REQVLD9(x) ((x) << S_PLM_REQVLD9)
11446 #define G_PLM_REQVLD9(x) (((x) >> S_PLM_REQVLD9) & M_PLM_REQVLD9)
11447 
11448 #define S_PLM_REQVLDA    1
11449 #define M_PLM_REQVLDA    0x7U
11450 #define V_PLM_REQVLDA(x) ((x) << S_PLM_REQVLDA)
11451 #define G_PLM_REQVLDA(x) (((x) >> S_PLM_REQVLDA) & M_PLM_REQVLDA)
11452 
11453 #define S_PLM_REQVLDB    0
11454 #define V_PLM_REQVLDB(x) ((x) << S_PLM_REQVLDB)
11455 #define F_PLM_REQVLDB    V_PLM_REQVLDB(1U)
11456 
11457 #define A_PCIE_CDEBUG_REG_0X16 0x16
11458 #define A_PCIE_CDEBUG_REG_0X17 0x17
11459 #define A_PCIE_CDEBUG_REG_0X18 0x18
11460 #define A_PCIE_CDEBUG_REG_0X19 0x19
11461 #define A_PCIE_CDEBUG_REG_0X1A 0x1a
11462 #define A_PCIE_CDEBUG_REG_0X1B 0x1b
11463 #define A_PCIE_CDEBUG_REG_0X1C 0x1c
11464 #define A_PCIE_CDEBUG_REG_0X1D 0x1d
11465 #define A_PCIE_CDEBUG_REG_0X1E 0x1e
11466 #define A_PCIE_CDEBUG_REG_0X1F 0x1f
11467 #define A_PCIE_CDEBUG_REG_0X20 0x20
11468 #define A_PCIE_CDEBUG_REG_0X21 0x21
11469 #define A_PCIE_CDEBUG_REG_0X22 0x22
11470 #define A_PCIE_CDEBUG_REG_0X23 0x23
11471 #define A_PCIE_CDEBUG_REG_0X24 0x24
11472 #define A_PCIE_CDEBUG_REG_0X25 0x25
11473 #define A_PCIE_CDEBUG_REG_0X26 0x26
11474 #define A_PCIE_CDEBUG_REG_0X27 0x27
11475 #define A_PCIE_CDEBUG_REG_0X28 0x28
11476 #define A_PCIE_CDEBUG_REG_0X29 0x29
11477 #define A_PCIE_CDEBUG_REG_0X2A 0x2a
11478 #define A_PCIE_CDEBUG_REG_0X2B 0x2b
11479 #define A_PCIE_CDEBUG_REG_0X2C 0x2c
11480 #define A_PCIE_CDEBUG_REG_0X2D 0x2d
11481 #define A_PCIE_CDEBUG_REG_0X2E 0x2e
11482 #define A_PCIE_CDEBUG_REG_0X2F 0x2f
11483 #define A_PCIE_CDEBUG_REG_0X30 0x30
11484 #define A_PCIE_CDEBUG_REG_0X31 0x31
11485 #define A_PCIE_CDEBUG_REG_0X32 0x32
11486 #define A_PCIE_CDEBUG_REG_0X33 0x33
11487 #define A_PCIE_CDEBUG_REG_0X34 0x34
11488 #define A_PCIE_CDEBUG_REG_0X35 0x35
11489 #define A_PCIE_CDEBUG_REG_0X36 0x36
11490 #define A_PCIE_CDEBUG_REG_0X37 0x37
11491 
11492 /* registers for module DBG */
11493 #define DBG_BASE_ADDR 0x6000
11494 
11495 #define A_DBG_DBG0_CFG 0x6000
11496 
11497 #define S_MODULESELECT    12
11498 #define M_MODULESELECT    0xffU
11499 #define V_MODULESELECT(x) ((x) << S_MODULESELECT)
11500 #define G_MODULESELECT(x) (((x) >> S_MODULESELECT) & M_MODULESELECT)
11501 
11502 #define S_REGSELECT    4
11503 #define M_REGSELECT    0xffU
11504 #define V_REGSELECT(x) ((x) << S_REGSELECT)
11505 #define G_REGSELECT(x) (((x) >> S_REGSELECT) & M_REGSELECT)
11506 
11507 #define S_CLKSELECT    0
11508 #define M_CLKSELECT    0xfU
11509 #define V_CLKSELECT(x) ((x) << S_CLKSELECT)
11510 #define G_CLKSELECT(x) (((x) >> S_CLKSELECT) & M_CLKSELECT)
11511 
11512 #define A_DBG_DBG0_EN 0x6004
11513 
11514 #define S_PORTEN_PONR    16
11515 #define V_PORTEN_PONR(x) ((x) << S_PORTEN_PONR)
11516 #define F_PORTEN_PONR    V_PORTEN_PONR(1U)
11517 
11518 #define S_PORTEN_POND    12
11519 #define V_PORTEN_POND(x) ((x) << S_PORTEN_POND)
11520 #define F_PORTEN_POND    V_PORTEN_POND(1U)
11521 
11522 #define S_SDRHALFWORD0    8
11523 #define V_SDRHALFWORD0(x) ((x) << S_SDRHALFWORD0)
11524 #define F_SDRHALFWORD0    V_SDRHALFWORD0(1U)
11525 
11526 #define S_DDREN    4
11527 #define V_DDREN(x) ((x) << S_DDREN)
11528 #define F_DDREN    V_DDREN(1U)
11529 
11530 #define S_DBG_PORTEN    0
11531 #define V_DBG_PORTEN(x) ((x) << S_DBG_PORTEN)
11532 #define F_DBG_PORTEN    V_DBG_PORTEN(1U)
11533 
11534 #define A_DBG_DBG1_CFG 0x6008
11535 #define A_DBG_DBG1_EN 0x600c
11536 
11537 #define S_CLK_EN_ON_DBG1    20
11538 #define V_CLK_EN_ON_DBG1(x) ((x) << S_CLK_EN_ON_DBG1)
11539 #define F_CLK_EN_ON_DBG1    V_CLK_EN_ON_DBG1(1U)
11540 
11541 #define A_DBG_GPIO_EN 0x6010
11542 
11543 #define S_GPIO15_OEN    31
11544 #define V_GPIO15_OEN(x) ((x) << S_GPIO15_OEN)
11545 #define F_GPIO15_OEN    V_GPIO15_OEN(1U)
11546 
11547 #define S_GPIO14_OEN    30
11548 #define V_GPIO14_OEN(x) ((x) << S_GPIO14_OEN)
11549 #define F_GPIO14_OEN    V_GPIO14_OEN(1U)
11550 
11551 #define S_GPIO13_OEN    29
11552 #define V_GPIO13_OEN(x) ((x) << S_GPIO13_OEN)
11553 #define F_GPIO13_OEN    V_GPIO13_OEN(1U)
11554 
11555 #define S_GPIO12_OEN    28
11556 #define V_GPIO12_OEN(x) ((x) << S_GPIO12_OEN)
11557 #define F_GPIO12_OEN    V_GPIO12_OEN(1U)
11558 
11559 #define S_GPIO11_OEN    27
11560 #define V_GPIO11_OEN(x) ((x) << S_GPIO11_OEN)
11561 #define F_GPIO11_OEN    V_GPIO11_OEN(1U)
11562 
11563 #define S_GPIO10_OEN    26
11564 #define V_GPIO10_OEN(x) ((x) << S_GPIO10_OEN)
11565 #define F_GPIO10_OEN    V_GPIO10_OEN(1U)
11566 
11567 #define S_GPIO9_OEN    25
11568 #define V_GPIO9_OEN(x) ((x) << S_GPIO9_OEN)
11569 #define F_GPIO9_OEN    V_GPIO9_OEN(1U)
11570 
11571 #define S_GPIO8_OEN    24
11572 #define V_GPIO8_OEN(x) ((x) << S_GPIO8_OEN)
11573 #define F_GPIO8_OEN    V_GPIO8_OEN(1U)
11574 
11575 #define S_GPIO7_OEN    23
11576 #define V_GPIO7_OEN(x) ((x) << S_GPIO7_OEN)
11577 #define F_GPIO7_OEN    V_GPIO7_OEN(1U)
11578 
11579 #define S_GPIO6_OEN    22
11580 #define V_GPIO6_OEN(x) ((x) << S_GPIO6_OEN)
11581 #define F_GPIO6_OEN    V_GPIO6_OEN(1U)
11582 
11583 #define S_GPIO5_OEN    21
11584 #define V_GPIO5_OEN(x) ((x) << S_GPIO5_OEN)
11585 #define F_GPIO5_OEN    V_GPIO5_OEN(1U)
11586 
11587 #define S_GPIO4_OEN    20
11588 #define V_GPIO4_OEN(x) ((x) << S_GPIO4_OEN)
11589 #define F_GPIO4_OEN    V_GPIO4_OEN(1U)
11590 
11591 #define S_GPIO3_OEN    19
11592 #define V_GPIO3_OEN(x) ((x) << S_GPIO3_OEN)
11593 #define F_GPIO3_OEN    V_GPIO3_OEN(1U)
11594 
11595 #define S_GPIO2_OEN    18
11596 #define V_GPIO2_OEN(x) ((x) << S_GPIO2_OEN)
11597 #define F_GPIO2_OEN    V_GPIO2_OEN(1U)
11598 
11599 #define S_GPIO1_OEN    17
11600 #define V_GPIO1_OEN(x) ((x) << S_GPIO1_OEN)
11601 #define F_GPIO1_OEN    V_GPIO1_OEN(1U)
11602 
11603 #define S_GPIO0_OEN    16
11604 #define V_GPIO0_OEN(x) ((x) << S_GPIO0_OEN)
11605 #define F_GPIO0_OEN    V_GPIO0_OEN(1U)
11606 
11607 #define S_GPIO15_OUT_VAL    15
11608 #define V_GPIO15_OUT_VAL(x) ((x) << S_GPIO15_OUT_VAL)
11609 #define F_GPIO15_OUT_VAL    V_GPIO15_OUT_VAL(1U)
11610 
11611 #define S_GPIO14_OUT_VAL    14
11612 #define V_GPIO14_OUT_VAL(x) ((x) << S_GPIO14_OUT_VAL)
11613 #define F_GPIO14_OUT_VAL    V_GPIO14_OUT_VAL(1U)
11614 
11615 #define S_GPIO13_OUT_VAL    13
11616 #define V_GPIO13_OUT_VAL(x) ((x) << S_GPIO13_OUT_VAL)
11617 #define F_GPIO13_OUT_VAL    V_GPIO13_OUT_VAL(1U)
11618 
11619 #define S_GPIO12_OUT_VAL    12
11620 #define V_GPIO12_OUT_VAL(x) ((x) << S_GPIO12_OUT_VAL)
11621 #define F_GPIO12_OUT_VAL    V_GPIO12_OUT_VAL(1U)
11622 
11623 #define S_GPIO11_OUT_VAL    11
11624 #define V_GPIO11_OUT_VAL(x) ((x) << S_GPIO11_OUT_VAL)
11625 #define F_GPIO11_OUT_VAL    V_GPIO11_OUT_VAL(1U)
11626 
11627 #define S_GPIO10_OUT_VAL    10
11628 #define V_GPIO10_OUT_VAL(x) ((x) << S_GPIO10_OUT_VAL)
11629 #define F_GPIO10_OUT_VAL    V_GPIO10_OUT_VAL(1U)
11630 
11631 #define S_GPIO9_OUT_VAL    9
11632 #define V_GPIO9_OUT_VAL(x) ((x) << S_GPIO9_OUT_VAL)
11633 #define F_GPIO9_OUT_VAL    V_GPIO9_OUT_VAL(1U)
11634 
11635 #define S_GPIO8_OUT_VAL    8
11636 #define V_GPIO8_OUT_VAL(x) ((x) << S_GPIO8_OUT_VAL)
11637 #define F_GPIO8_OUT_VAL    V_GPIO8_OUT_VAL(1U)
11638 
11639 #define S_GPIO7_OUT_VAL    7
11640 #define V_GPIO7_OUT_VAL(x) ((x) << S_GPIO7_OUT_VAL)
11641 #define F_GPIO7_OUT_VAL    V_GPIO7_OUT_VAL(1U)
11642 
11643 #define S_GPIO6_OUT_VAL    6
11644 #define V_GPIO6_OUT_VAL(x) ((x) << S_GPIO6_OUT_VAL)
11645 #define F_GPIO6_OUT_VAL    V_GPIO6_OUT_VAL(1U)
11646 
11647 #define S_GPIO5_OUT_VAL    5
11648 #define V_GPIO5_OUT_VAL(x) ((x) << S_GPIO5_OUT_VAL)
11649 #define F_GPIO5_OUT_VAL    V_GPIO5_OUT_VAL(1U)
11650 
11651 #define S_GPIO4_OUT_VAL    4
11652 #define V_GPIO4_OUT_VAL(x) ((x) << S_GPIO4_OUT_VAL)
11653 #define F_GPIO4_OUT_VAL    V_GPIO4_OUT_VAL(1U)
11654 
11655 #define S_GPIO3_OUT_VAL    3
11656 #define V_GPIO3_OUT_VAL(x) ((x) << S_GPIO3_OUT_VAL)
11657 #define F_GPIO3_OUT_VAL    V_GPIO3_OUT_VAL(1U)
11658 
11659 #define S_GPIO2_OUT_VAL    2
11660 #define V_GPIO2_OUT_VAL(x) ((x) << S_GPIO2_OUT_VAL)
11661 #define F_GPIO2_OUT_VAL    V_GPIO2_OUT_VAL(1U)
11662 
11663 #define S_GPIO1_OUT_VAL    1
11664 #define V_GPIO1_OUT_VAL(x) ((x) << S_GPIO1_OUT_VAL)
11665 #define F_GPIO1_OUT_VAL    V_GPIO1_OUT_VAL(1U)
11666 
11667 #define S_GPIO0_OUT_VAL    0
11668 #define V_GPIO0_OUT_VAL(x) ((x) << S_GPIO0_OUT_VAL)
11669 #define F_GPIO0_OUT_VAL    V_GPIO0_OUT_VAL(1U)
11670 
11671 #define A_DBG_GPIO_IN 0x6014
11672 
11673 #define S_GPIO15_CHG_DET    31
11674 #define V_GPIO15_CHG_DET(x) ((x) << S_GPIO15_CHG_DET)
11675 #define F_GPIO15_CHG_DET    V_GPIO15_CHG_DET(1U)
11676 
11677 #define S_GPIO14_CHG_DET    30
11678 #define V_GPIO14_CHG_DET(x) ((x) << S_GPIO14_CHG_DET)
11679 #define F_GPIO14_CHG_DET    V_GPIO14_CHG_DET(1U)
11680 
11681 #define S_GPIO13_CHG_DET    29
11682 #define V_GPIO13_CHG_DET(x) ((x) << S_GPIO13_CHG_DET)
11683 #define F_GPIO13_CHG_DET    V_GPIO13_CHG_DET(1U)
11684 
11685 #define S_GPIO12_CHG_DET    28
11686 #define V_GPIO12_CHG_DET(x) ((x) << S_GPIO12_CHG_DET)
11687 #define F_GPIO12_CHG_DET    V_GPIO12_CHG_DET(1U)
11688 
11689 #define S_GPIO11_CHG_DET    27
11690 #define V_GPIO11_CHG_DET(x) ((x) << S_GPIO11_CHG_DET)
11691 #define F_GPIO11_CHG_DET    V_GPIO11_CHG_DET(1U)
11692 
11693 #define S_GPIO10_CHG_DET    26
11694 #define V_GPIO10_CHG_DET(x) ((x) << S_GPIO10_CHG_DET)
11695 #define F_GPIO10_CHG_DET    V_GPIO10_CHG_DET(1U)
11696 
11697 #define S_GPIO9_CHG_DET    25
11698 #define V_GPIO9_CHG_DET(x) ((x) << S_GPIO9_CHG_DET)
11699 #define F_GPIO9_CHG_DET    V_GPIO9_CHG_DET(1U)
11700 
11701 #define S_GPIO8_CHG_DET    24
11702 #define V_GPIO8_CHG_DET(x) ((x) << S_GPIO8_CHG_DET)
11703 #define F_GPIO8_CHG_DET    V_GPIO8_CHG_DET(1U)
11704 
11705 #define S_GPIO7_CHG_DET    23
11706 #define V_GPIO7_CHG_DET(x) ((x) << S_GPIO7_CHG_DET)
11707 #define F_GPIO7_CHG_DET    V_GPIO7_CHG_DET(1U)
11708 
11709 #define S_GPIO6_CHG_DET    22
11710 #define V_GPIO6_CHG_DET(x) ((x) << S_GPIO6_CHG_DET)
11711 #define F_GPIO6_CHG_DET    V_GPIO6_CHG_DET(1U)
11712 
11713 #define S_GPIO5_CHG_DET    21
11714 #define V_GPIO5_CHG_DET(x) ((x) << S_GPIO5_CHG_DET)
11715 #define F_GPIO5_CHG_DET    V_GPIO5_CHG_DET(1U)
11716 
11717 #define S_GPIO4_CHG_DET    20
11718 #define V_GPIO4_CHG_DET(x) ((x) << S_GPIO4_CHG_DET)
11719 #define F_GPIO4_CHG_DET    V_GPIO4_CHG_DET(1U)
11720 
11721 #define S_GPIO3_CHG_DET    19
11722 #define V_GPIO3_CHG_DET(x) ((x) << S_GPIO3_CHG_DET)
11723 #define F_GPIO3_CHG_DET    V_GPIO3_CHG_DET(1U)
11724 
11725 #define S_GPIO2_CHG_DET    18
11726 #define V_GPIO2_CHG_DET(x) ((x) << S_GPIO2_CHG_DET)
11727 #define F_GPIO2_CHG_DET    V_GPIO2_CHG_DET(1U)
11728 
11729 #define S_GPIO1_CHG_DET    17
11730 #define V_GPIO1_CHG_DET(x) ((x) << S_GPIO1_CHG_DET)
11731 #define F_GPIO1_CHG_DET    V_GPIO1_CHG_DET(1U)
11732 
11733 #define S_GPIO0_CHG_DET    16
11734 #define V_GPIO0_CHG_DET(x) ((x) << S_GPIO0_CHG_DET)
11735 #define F_GPIO0_CHG_DET    V_GPIO0_CHG_DET(1U)
11736 
11737 #define S_GPIO15_IN    15
11738 #define V_GPIO15_IN(x) ((x) << S_GPIO15_IN)
11739 #define F_GPIO15_IN    V_GPIO15_IN(1U)
11740 
11741 #define S_GPIO14_IN    14
11742 #define V_GPIO14_IN(x) ((x) << S_GPIO14_IN)
11743 #define F_GPIO14_IN    V_GPIO14_IN(1U)
11744 
11745 #define S_GPIO13_IN    13
11746 #define V_GPIO13_IN(x) ((x) << S_GPIO13_IN)
11747 #define F_GPIO13_IN    V_GPIO13_IN(1U)
11748 
11749 #define S_GPIO12_IN    12
11750 #define V_GPIO12_IN(x) ((x) << S_GPIO12_IN)
11751 #define F_GPIO12_IN    V_GPIO12_IN(1U)
11752 
11753 #define S_GPIO11_IN    11
11754 #define V_GPIO11_IN(x) ((x) << S_GPIO11_IN)
11755 #define F_GPIO11_IN    V_GPIO11_IN(1U)
11756 
11757 #define S_GPIO10_IN    10
11758 #define V_GPIO10_IN(x) ((x) << S_GPIO10_IN)
11759 #define F_GPIO10_IN    V_GPIO10_IN(1U)
11760 
11761 #define S_GPIO9_IN    9
11762 #define V_GPIO9_IN(x) ((x) << S_GPIO9_IN)
11763 #define F_GPIO9_IN    V_GPIO9_IN(1U)
11764 
11765 #define S_GPIO8_IN    8
11766 #define V_GPIO8_IN(x) ((x) << S_GPIO8_IN)
11767 #define F_GPIO8_IN    V_GPIO8_IN(1U)
11768 
11769 #define S_GPIO7_IN    7
11770 #define V_GPIO7_IN(x) ((x) << S_GPIO7_IN)
11771 #define F_GPIO7_IN    V_GPIO7_IN(1U)
11772 
11773 #define S_GPIO6_IN    6
11774 #define V_GPIO6_IN(x) ((x) << S_GPIO6_IN)
11775 #define F_GPIO6_IN    V_GPIO6_IN(1U)
11776 
11777 #define S_GPIO5_IN    5
11778 #define V_GPIO5_IN(x) ((x) << S_GPIO5_IN)
11779 #define F_GPIO5_IN    V_GPIO5_IN(1U)
11780 
11781 #define S_GPIO4_IN    4
11782 #define V_GPIO4_IN(x) ((x) << S_GPIO4_IN)
11783 #define F_GPIO4_IN    V_GPIO4_IN(1U)
11784 
11785 #define S_GPIO3_IN    3
11786 #define V_GPIO3_IN(x) ((x) << S_GPIO3_IN)
11787 #define F_GPIO3_IN    V_GPIO3_IN(1U)
11788 
11789 #define S_GPIO2_IN    2
11790 #define V_GPIO2_IN(x) ((x) << S_GPIO2_IN)
11791 #define F_GPIO2_IN    V_GPIO2_IN(1U)
11792 
11793 #define S_GPIO1_IN    1
11794 #define V_GPIO1_IN(x) ((x) << S_GPIO1_IN)
11795 #define F_GPIO1_IN    V_GPIO1_IN(1U)
11796 
11797 #define S_GPIO0_IN    0
11798 #define V_GPIO0_IN(x) ((x) << S_GPIO0_IN)
11799 #define F_GPIO0_IN    V_GPIO0_IN(1U)
11800 
11801 #define A_DBG_INT_ENABLE 0x6018
11802 
11803 #define S_IBM_FDL_FAIL_INT_ENBL    25
11804 #define V_IBM_FDL_FAIL_INT_ENBL(x) ((x) << S_IBM_FDL_FAIL_INT_ENBL)
11805 #define F_IBM_FDL_FAIL_INT_ENBL    V_IBM_FDL_FAIL_INT_ENBL(1U)
11806 
11807 #define S_ARM_FAIL_INT_ENBL    24
11808 #define V_ARM_FAIL_INT_ENBL(x) ((x) << S_ARM_FAIL_INT_ENBL)
11809 #define F_ARM_FAIL_INT_ENBL    V_ARM_FAIL_INT_ENBL(1U)
11810 
11811 #define S_ARM_ERROR_OUT_INT_ENBL    23
11812 #define V_ARM_ERROR_OUT_INT_ENBL(x) ((x) << S_ARM_ERROR_OUT_INT_ENBL)
11813 #define F_ARM_ERROR_OUT_INT_ENBL    V_ARM_ERROR_OUT_INT_ENBL(1U)
11814 
11815 #define S_PLL_LOCK_LOST_INT_ENBL    22
11816 #define V_PLL_LOCK_LOST_INT_ENBL(x) ((x) << S_PLL_LOCK_LOST_INT_ENBL)
11817 #define F_PLL_LOCK_LOST_INT_ENBL    V_PLL_LOCK_LOST_INT_ENBL(1U)
11818 
11819 #define S_C_LOCK    21
11820 #define V_C_LOCK(x) ((x) << S_C_LOCK)
11821 #define F_C_LOCK    V_C_LOCK(1U)
11822 
11823 #define S_M_LOCK    20
11824 #define V_M_LOCK(x) ((x) << S_M_LOCK)
11825 #define F_M_LOCK    V_M_LOCK(1U)
11826 
11827 #define S_U_LOCK    19
11828 #define V_U_LOCK(x) ((x) << S_U_LOCK)
11829 #define F_U_LOCK    V_U_LOCK(1U)
11830 
11831 #define S_PCIE_LOCK    18
11832 #define V_PCIE_LOCK(x) ((x) << S_PCIE_LOCK)
11833 #define F_PCIE_LOCK    V_PCIE_LOCK(1U)
11834 
11835 #define S_KX_LOCK    17
11836 #define V_KX_LOCK(x) ((x) << S_KX_LOCK)
11837 #define F_KX_LOCK    V_KX_LOCK(1U)
11838 
11839 #define S_KR_LOCK    16
11840 #define V_KR_LOCK(x) ((x) << S_KR_LOCK)
11841 #define F_KR_LOCK    V_KR_LOCK(1U)
11842 
11843 #define S_GPIO15    15
11844 #define V_GPIO15(x) ((x) << S_GPIO15)
11845 #define F_GPIO15    V_GPIO15(1U)
11846 
11847 #define S_GPIO14    14
11848 #define V_GPIO14(x) ((x) << S_GPIO14)
11849 #define F_GPIO14    V_GPIO14(1U)
11850 
11851 #define S_GPIO13    13
11852 #define V_GPIO13(x) ((x) << S_GPIO13)
11853 #define F_GPIO13    V_GPIO13(1U)
11854 
11855 #define S_GPIO12    12
11856 #define V_GPIO12(x) ((x) << S_GPIO12)
11857 #define F_GPIO12    V_GPIO12(1U)
11858 
11859 #define S_GPIO11    11
11860 #define V_GPIO11(x) ((x) << S_GPIO11)
11861 #define F_GPIO11    V_GPIO11(1U)
11862 
11863 #define S_GPIO10    10
11864 #define V_GPIO10(x) ((x) << S_GPIO10)
11865 #define F_GPIO10    V_GPIO10(1U)
11866 
11867 #define S_GPIO9    9
11868 #define V_GPIO9(x) ((x) << S_GPIO9)
11869 #define F_GPIO9    V_GPIO9(1U)
11870 
11871 #define S_GPIO8    8
11872 #define V_GPIO8(x) ((x) << S_GPIO8)
11873 #define F_GPIO8    V_GPIO8(1U)
11874 
11875 #define S_GPIO7    7
11876 #define V_GPIO7(x) ((x) << S_GPIO7)
11877 #define F_GPIO7    V_GPIO7(1U)
11878 
11879 #define S_GPIO6    6
11880 #define V_GPIO6(x) ((x) << S_GPIO6)
11881 #define F_GPIO6    V_GPIO6(1U)
11882 
11883 #define S_GPIO5    5
11884 #define V_GPIO5(x) ((x) << S_GPIO5)
11885 #define F_GPIO5    V_GPIO5(1U)
11886 
11887 #define S_GPIO4    4
11888 #define V_GPIO4(x) ((x) << S_GPIO4)
11889 #define F_GPIO4    V_GPIO4(1U)
11890 
11891 #define S_GPIO3    3
11892 #define V_GPIO3(x) ((x) << S_GPIO3)
11893 #define F_GPIO3    V_GPIO3(1U)
11894 
11895 #define S_GPIO2    2
11896 #define V_GPIO2(x) ((x) << S_GPIO2)
11897 #define F_GPIO2    V_GPIO2(1U)
11898 
11899 #define S_GPIO1    1
11900 #define V_GPIO1(x) ((x) << S_GPIO1)
11901 #define F_GPIO1    V_GPIO1(1U)
11902 
11903 #define S_GPIO0    0
11904 #define V_GPIO0(x) ((x) << S_GPIO0)
11905 #define F_GPIO0    V_GPIO0(1U)
11906 
11907 #define S_GPIO19    29
11908 #define V_GPIO19(x) ((x) << S_GPIO19)
11909 #define F_GPIO19    V_GPIO19(1U)
11910 
11911 #define S_GPIO18    28
11912 #define V_GPIO18(x) ((x) << S_GPIO18)
11913 #define F_GPIO18    V_GPIO18(1U)
11914 
11915 #define S_GPIO17    27
11916 #define V_GPIO17(x) ((x) << S_GPIO17)
11917 #define F_GPIO17    V_GPIO17(1U)
11918 
11919 #define S_GPIO16    26
11920 #define V_GPIO16(x) ((x) << S_GPIO16)
11921 #define F_GPIO16    V_GPIO16(1U)
11922 
11923 #define A_DBG_INT_CAUSE 0x601c
11924 
11925 #define S_IBM_FDL_FAIL_INT_CAUSE    25
11926 #define V_IBM_FDL_FAIL_INT_CAUSE(x) ((x) << S_IBM_FDL_FAIL_INT_CAUSE)
11927 #define F_IBM_FDL_FAIL_INT_CAUSE    V_IBM_FDL_FAIL_INT_CAUSE(1U)
11928 
11929 #define S_ARM_FAIL_INT_CAUSE    24
11930 #define V_ARM_FAIL_INT_CAUSE(x) ((x) << S_ARM_FAIL_INT_CAUSE)
11931 #define F_ARM_FAIL_INT_CAUSE    V_ARM_FAIL_INT_CAUSE(1U)
11932 
11933 #define S_ARM_ERROR_OUT_INT_CAUSE    23
11934 #define V_ARM_ERROR_OUT_INT_CAUSE(x) ((x) << S_ARM_ERROR_OUT_INT_CAUSE)
11935 #define F_ARM_ERROR_OUT_INT_CAUSE    V_ARM_ERROR_OUT_INT_CAUSE(1U)
11936 
11937 #define S_PLL_LOCK_LOST_INT_CAUSE    22
11938 #define V_PLL_LOCK_LOST_INT_CAUSE(x) ((x) << S_PLL_LOCK_LOST_INT_CAUSE)
11939 #define F_PLL_LOCK_LOST_INT_CAUSE    V_PLL_LOCK_LOST_INT_CAUSE(1U)
11940 
11941 #define A_DBG_DBG0_RST_VALUE 0x6020
11942 
11943 #define S_DEBUGDATA    0
11944 #define M_DEBUGDATA    0xffffU
11945 #define V_DEBUGDATA(x) ((x) << S_DEBUGDATA)
11946 #define G_DEBUGDATA(x) (((x) >> S_DEBUGDATA) & M_DEBUGDATA)
11947 
11948 #define A_DBG_OVERWRSERCFG_EN 0x6024
11949 
11950 #define S_OVERWRSERCFG_EN    0
11951 #define V_OVERWRSERCFG_EN(x) ((x) << S_OVERWRSERCFG_EN)
11952 #define F_OVERWRSERCFG_EN    V_OVERWRSERCFG_EN(1U)
11953 
11954 #define A_DBG_PLL_OCLK_PAD_EN 0x6028
11955 
11956 #define S_PCIE_OCLK_EN    20
11957 #define V_PCIE_OCLK_EN(x) ((x) << S_PCIE_OCLK_EN)
11958 #define F_PCIE_OCLK_EN    V_PCIE_OCLK_EN(1U)
11959 
11960 #define S_KX_OCLK_EN    16
11961 #define V_KX_OCLK_EN(x) ((x) << S_KX_OCLK_EN)
11962 #define F_KX_OCLK_EN    V_KX_OCLK_EN(1U)
11963 
11964 #define S_U_OCLK_EN    12
11965 #define V_U_OCLK_EN(x) ((x) << S_U_OCLK_EN)
11966 #define F_U_OCLK_EN    V_U_OCLK_EN(1U)
11967 
11968 #define S_KR_OCLK_EN    8
11969 #define V_KR_OCLK_EN(x) ((x) << S_KR_OCLK_EN)
11970 #define F_KR_OCLK_EN    V_KR_OCLK_EN(1U)
11971 
11972 #define S_M_OCLK_EN    4
11973 #define V_M_OCLK_EN(x) ((x) << S_M_OCLK_EN)
11974 #define F_M_OCLK_EN    V_M_OCLK_EN(1U)
11975 
11976 #define S_C_OCLK_EN    0
11977 #define V_C_OCLK_EN(x) ((x) << S_C_OCLK_EN)
11978 #define F_C_OCLK_EN    V_C_OCLK_EN(1U)
11979 
11980 #define A_DBG_PLL_LOCK 0x602c
11981 
11982 #define S_PLL_P_LOCK    20
11983 #define V_PLL_P_LOCK(x) ((x) << S_PLL_P_LOCK)
11984 #define F_PLL_P_LOCK    V_PLL_P_LOCK(1U)
11985 
11986 #define S_PLL_KX_LOCK    16
11987 #define V_PLL_KX_LOCK(x) ((x) << S_PLL_KX_LOCK)
11988 #define F_PLL_KX_LOCK    V_PLL_KX_LOCK(1U)
11989 
11990 #define S_PLL_U_LOCK    12
11991 #define V_PLL_U_LOCK(x) ((x) << S_PLL_U_LOCK)
11992 #define F_PLL_U_LOCK    V_PLL_U_LOCK(1U)
11993 
11994 #define S_PLL_KR_LOCK    8
11995 #define V_PLL_KR_LOCK(x) ((x) << S_PLL_KR_LOCK)
11996 #define F_PLL_KR_LOCK    V_PLL_KR_LOCK(1U)
11997 
11998 #define S_PLL_M_LOCK    4
11999 #define V_PLL_M_LOCK(x) ((x) << S_PLL_M_LOCK)
12000 #define F_PLL_M_LOCK    V_PLL_M_LOCK(1U)
12001 
12002 #define S_PLL_C_LOCK    0
12003 #define V_PLL_C_LOCK(x) ((x) << S_PLL_C_LOCK)
12004 #define F_PLL_C_LOCK    V_PLL_C_LOCK(1U)
12005 
12006 #define A_DBG_GPIO_ACT_LOW 0x6030
12007 
12008 #define S_P_LOCK_ACT_LOW    21
12009 #define V_P_LOCK_ACT_LOW(x) ((x) << S_P_LOCK_ACT_LOW)
12010 #define F_P_LOCK_ACT_LOW    V_P_LOCK_ACT_LOW(1U)
12011 
12012 #define S_C_LOCK_ACT_LOW    20
12013 #define V_C_LOCK_ACT_LOW(x) ((x) << S_C_LOCK_ACT_LOW)
12014 #define F_C_LOCK_ACT_LOW    V_C_LOCK_ACT_LOW(1U)
12015 
12016 #define S_M_LOCK_ACT_LOW    19
12017 #define V_M_LOCK_ACT_LOW(x) ((x) << S_M_LOCK_ACT_LOW)
12018 #define F_M_LOCK_ACT_LOW    V_M_LOCK_ACT_LOW(1U)
12019 
12020 #define S_U_LOCK_ACT_LOW    18
12021 #define V_U_LOCK_ACT_LOW(x) ((x) << S_U_LOCK_ACT_LOW)
12022 #define F_U_LOCK_ACT_LOW    V_U_LOCK_ACT_LOW(1U)
12023 
12024 #define S_KR_LOCK_ACT_LOW    17
12025 #define V_KR_LOCK_ACT_LOW(x) ((x) << S_KR_LOCK_ACT_LOW)
12026 #define F_KR_LOCK_ACT_LOW    V_KR_LOCK_ACT_LOW(1U)
12027 
12028 #define S_KX_LOCK_ACT_LOW    16
12029 #define V_KX_LOCK_ACT_LOW(x) ((x) << S_KX_LOCK_ACT_LOW)
12030 #define F_KX_LOCK_ACT_LOW    V_KX_LOCK_ACT_LOW(1U)
12031 
12032 #define S_GPIO15_ACT_LOW    15
12033 #define V_GPIO15_ACT_LOW(x) ((x) << S_GPIO15_ACT_LOW)
12034 #define F_GPIO15_ACT_LOW    V_GPIO15_ACT_LOW(1U)
12035 
12036 #define S_GPIO14_ACT_LOW    14
12037 #define V_GPIO14_ACT_LOW(x) ((x) << S_GPIO14_ACT_LOW)
12038 #define F_GPIO14_ACT_LOW    V_GPIO14_ACT_LOW(1U)
12039 
12040 #define S_GPIO13_ACT_LOW    13
12041 #define V_GPIO13_ACT_LOW(x) ((x) << S_GPIO13_ACT_LOW)
12042 #define F_GPIO13_ACT_LOW    V_GPIO13_ACT_LOW(1U)
12043 
12044 #define S_GPIO12_ACT_LOW    12
12045 #define V_GPIO12_ACT_LOW(x) ((x) << S_GPIO12_ACT_LOW)
12046 #define F_GPIO12_ACT_LOW    V_GPIO12_ACT_LOW(1U)
12047 
12048 #define S_GPIO11_ACT_LOW    11
12049 #define V_GPIO11_ACT_LOW(x) ((x) << S_GPIO11_ACT_LOW)
12050 #define F_GPIO11_ACT_LOW    V_GPIO11_ACT_LOW(1U)
12051 
12052 #define S_GPIO10_ACT_LOW    10
12053 #define V_GPIO10_ACT_LOW(x) ((x) << S_GPIO10_ACT_LOW)
12054 #define F_GPIO10_ACT_LOW    V_GPIO10_ACT_LOW(1U)
12055 
12056 #define S_GPIO9_ACT_LOW    9
12057 #define V_GPIO9_ACT_LOW(x) ((x) << S_GPIO9_ACT_LOW)
12058 #define F_GPIO9_ACT_LOW    V_GPIO9_ACT_LOW(1U)
12059 
12060 #define S_GPIO8_ACT_LOW    8
12061 #define V_GPIO8_ACT_LOW(x) ((x) << S_GPIO8_ACT_LOW)
12062 #define F_GPIO8_ACT_LOW    V_GPIO8_ACT_LOW(1U)
12063 
12064 #define S_GPIO7_ACT_LOW    7
12065 #define V_GPIO7_ACT_LOW(x) ((x) << S_GPIO7_ACT_LOW)
12066 #define F_GPIO7_ACT_LOW    V_GPIO7_ACT_LOW(1U)
12067 
12068 #define S_GPIO6_ACT_LOW    6
12069 #define V_GPIO6_ACT_LOW(x) ((x) << S_GPIO6_ACT_LOW)
12070 #define F_GPIO6_ACT_LOW    V_GPIO6_ACT_LOW(1U)
12071 
12072 #define S_GPIO5_ACT_LOW    5
12073 #define V_GPIO5_ACT_LOW(x) ((x) << S_GPIO5_ACT_LOW)
12074 #define F_GPIO5_ACT_LOW    V_GPIO5_ACT_LOW(1U)
12075 
12076 #define S_GPIO4_ACT_LOW    4
12077 #define V_GPIO4_ACT_LOW(x) ((x) << S_GPIO4_ACT_LOW)
12078 #define F_GPIO4_ACT_LOW    V_GPIO4_ACT_LOW(1U)
12079 
12080 #define S_GPIO3_ACT_LOW    3
12081 #define V_GPIO3_ACT_LOW(x) ((x) << S_GPIO3_ACT_LOW)
12082 #define F_GPIO3_ACT_LOW    V_GPIO3_ACT_LOW(1U)
12083 
12084 #define S_GPIO2_ACT_LOW    2
12085 #define V_GPIO2_ACT_LOW(x) ((x) << S_GPIO2_ACT_LOW)
12086 #define F_GPIO2_ACT_LOW    V_GPIO2_ACT_LOW(1U)
12087 
12088 #define S_GPIO1_ACT_LOW    1
12089 #define V_GPIO1_ACT_LOW(x) ((x) << S_GPIO1_ACT_LOW)
12090 #define F_GPIO1_ACT_LOW    V_GPIO1_ACT_LOW(1U)
12091 
12092 #define S_GPIO0_ACT_LOW    0
12093 #define V_GPIO0_ACT_LOW(x) ((x) << S_GPIO0_ACT_LOW)
12094 #define F_GPIO0_ACT_LOW    V_GPIO0_ACT_LOW(1U)
12095 
12096 #define S_GPIO19_ACT_LOW    25
12097 #define V_GPIO19_ACT_LOW(x) ((x) << S_GPIO19_ACT_LOW)
12098 #define F_GPIO19_ACT_LOW    V_GPIO19_ACT_LOW(1U)
12099 
12100 #define S_GPIO18_ACT_LOW    24
12101 #define V_GPIO18_ACT_LOW(x) ((x) << S_GPIO18_ACT_LOW)
12102 #define F_GPIO18_ACT_LOW    V_GPIO18_ACT_LOW(1U)
12103 
12104 #define S_GPIO17_ACT_LOW    23
12105 #define V_GPIO17_ACT_LOW(x) ((x) << S_GPIO17_ACT_LOW)
12106 #define F_GPIO17_ACT_LOW    V_GPIO17_ACT_LOW(1U)
12107 
12108 #define S_GPIO16_ACT_LOW    22
12109 #define V_GPIO16_ACT_LOW(x) ((x) << S_GPIO16_ACT_LOW)
12110 #define F_GPIO16_ACT_LOW    V_GPIO16_ACT_LOW(1U)
12111 
12112 #define A_DBG_EFUSE_BYTE0_3 0x6034
12113 #define A_DBG_EFUSE_BYTE4_7 0x6038
12114 #define A_DBG_EFUSE_BYTE8_11 0x603c
12115 #define A_DBG_EFUSE_BYTE12_15 0x6040
12116 #define A_DBG_STATIC_U_PLL_CONF 0x6044
12117 
12118 #define S_STATIC_U_PLL_MULT    23
12119 #define M_STATIC_U_PLL_MULT    0x1ffU
12120 #define V_STATIC_U_PLL_MULT(x) ((x) << S_STATIC_U_PLL_MULT)
12121 #define G_STATIC_U_PLL_MULT(x) (((x) >> S_STATIC_U_PLL_MULT) & M_STATIC_U_PLL_MULT)
12122 
12123 #define S_STATIC_U_PLL_PREDIV    18
12124 #define M_STATIC_U_PLL_PREDIV    0x1fU
12125 #define V_STATIC_U_PLL_PREDIV(x) ((x) << S_STATIC_U_PLL_PREDIV)
12126 #define G_STATIC_U_PLL_PREDIV(x) (((x) >> S_STATIC_U_PLL_PREDIV) & M_STATIC_U_PLL_PREDIV)
12127 
12128 #define S_STATIC_U_PLL_RANGEA    14
12129 #define M_STATIC_U_PLL_RANGEA    0xfU
12130 #define V_STATIC_U_PLL_RANGEA(x) ((x) << S_STATIC_U_PLL_RANGEA)
12131 #define G_STATIC_U_PLL_RANGEA(x) (((x) >> S_STATIC_U_PLL_RANGEA) & M_STATIC_U_PLL_RANGEA)
12132 
12133 #define S_STATIC_U_PLL_RANGEB    10
12134 #define M_STATIC_U_PLL_RANGEB    0xfU
12135 #define V_STATIC_U_PLL_RANGEB(x) ((x) << S_STATIC_U_PLL_RANGEB)
12136 #define G_STATIC_U_PLL_RANGEB(x) (((x) >> S_STATIC_U_PLL_RANGEB) & M_STATIC_U_PLL_RANGEB)
12137 
12138 #define S_STATIC_U_PLL_TUNE    0
12139 #define M_STATIC_U_PLL_TUNE    0x3ffU
12140 #define V_STATIC_U_PLL_TUNE(x) ((x) << S_STATIC_U_PLL_TUNE)
12141 #define G_STATIC_U_PLL_TUNE(x) (((x) >> S_STATIC_U_PLL_TUNE) & M_STATIC_U_PLL_TUNE)
12142 
12143 #define A_DBG_STATIC_C_PLL_CONF 0x6048
12144 
12145 #define S_STATIC_C_PLL_MULT    23
12146 #define M_STATIC_C_PLL_MULT    0x1ffU
12147 #define V_STATIC_C_PLL_MULT(x) ((x) << S_STATIC_C_PLL_MULT)
12148 #define G_STATIC_C_PLL_MULT(x) (((x) >> S_STATIC_C_PLL_MULT) & M_STATIC_C_PLL_MULT)
12149 
12150 #define S_STATIC_C_PLL_PREDIV    18
12151 #define M_STATIC_C_PLL_PREDIV    0x1fU
12152 #define V_STATIC_C_PLL_PREDIV(x) ((x) << S_STATIC_C_PLL_PREDIV)
12153 #define G_STATIC_C_PLL_PREDIV(x) (((x) >> S_STATIC_C_PLL_PREDIV) & M_STATIC_C_PLL_PREDIV)
12154 
12155 #define S_STATIC_C_PLL_RANGEA    14
12156 #define M_STATIC_C_PLL_RANGEA    0xfU
12157 #define V_STATIC_C_PLL_RANGEA(x) ((x) << S_STATIC_C_PLL_RANGEA)
12158 #define G_STATIC_C_PLL_RANGEA(x) (((x) >> S_STATIC_C_PLL_RANGEA) & M_STATIC_C_PLL_RANGEA)
12159 
12160 #define S_STATIC_C_PLL_RANGEB    10
12161 #define M_STATIC_C_PLL_RANGEB    0xfU
12162 #define V_STATIC_C_PLL_RANGEB(x) ((x) << S_STATIC_C_PLL_RANGEB)
12163 #define G_STATIC_C_PLL_RANGEB(x) (((x) >> S_STATIC_C_PLL_RANGEB) & M_STATIC_C_PLL_RANGEB)
12164 
12165 #define S_STATIC_C_PLL_TUNE    0
12166 #define M_STATIC_C_PLL_TUNE    0x3ffU
12167 #define V_STATIC_C_PLL_TUNE(x) ((x) << S_STATIC_C_PLL_TUNE)
12168 #define G_STATIC_C_PLL_TUNE(x) (((x) >> S_STATIC_C_PLL_TUNE) & M_STATIC_C_PLL_TUNE)
12169 
12170 #define A_DBG_STATIC_M_PLL_CONF 0x604c
12171 
12172 #define S_STATIC_M_PLL_MULT    23
12173 #define M_STATIC_M_PLL_MULT    0x1ffU
12174 #define V_STATIC_M_PLL_MULT(x) ((x) << S_STATIC_M_PLL_MULT)
12175 #define G_STATIC_M_PLL_MULT(x) (((x) >> S_STATIC_M_PLL_MULT) & M_STATIC_M_PLL_MULT)
12176 
12177 #define S_STATIC_M_PLL_PREDIV    18
12178 #define M_STATIC_M_PLL_PREDIV    0x1fU
12179 #define V_STATIC_M_PLL_PREDIV(x) ((x) << S_STATIC_M_PLL_PREDIV)
12180 #define G_STATIC_M_PLL_PREDIV(x) (((x) >> S_STATIC_M_PLL_PREDIV) & M_STATIC_M_PLL_PREDIV)
12181 
12182 #define S_STATIC_M_PLL_RANGEA    14
12183 #define M_STATIC_M_PLL_RANGEA    0xfU
12184 #define V_STATIC_M_PLL_RANGEA(x) ((x) << S_STATIC_M_PLL_RANGEA)
12185 #define G_STATIC_M_PLL_RANGEA(x) (((x) >> S_STATIC_M_PLL_RANGEA) & M_STATIC_M_PLL_RANGEA)
12186 
12187 #define S_STATIC_M_PLL_RANGEB    10
12188 #define M_STATIC_M_PLL_RANGEB    0xfU
12189 #define V_STATIC_M_PLL_RANGEB(x) ((x) << S_STATIC_M_PLL_RANGEB)
12190 #define G_STATIC_M_PLL_RANGEB(x) (((x) >> S_STATIC_M_PLL_RANGEB) & M_STATIC_M_PLL_RANGEB)
12191 
12192 #define S_STATIC_M_PLL_TUNE    0
12193 #define M_STATIC_M_PLL_TUNE    0x3ffU
12194 #define V_STATIC_M_PLL_TUNE(x) ((x) << S_STATIC_M_PLL_TUNE)
12195 #define G_STATIC_M_PLL_TUNE(x) (((x) >> S_STATIC_M_PLL_TUNE) & M_STATIC_M_PLL_TUNE)
12196 
12197 #define A_DBG_STATIC_KX_PLL_CONF 0x6050
12198 
12199 #define S_STATIC_KX_PLL_C    21
12200 #define M_STATIC_KX_PLL_C    0xffU
12201 #define V_STATIC_KX_PLL_C(x) ((x) << S_STATIC_KX_PLL_C)
12202 #define G_STATIC_KX_PLL_C(x) (((x) >> S_STATIC_KX_PLL_C) & M_STATIC_KX_PLL_C)
12203 
12204 #define S_STATIC_KX_PLL_M    15
12205 #define M_STATIC_KX_PLL_M    0x3fU
12206 #define V_STATIC_KX_PLL_M(x) ((x) << S_STATIC_KX_PLL_M)
12207 #define G_STATIC_KX_PLL_M(x) (((x) >> S_STATIC_KX_PLL_M) & M_STATIC_KX_PLL_M)
12208 
12209 #define S_STATIC_KX_PLL_N1    11
12210 #define M_STATIC_KX_PLL_N1    0xfU
12211 #define V_STATIC_KX_PLL_N1(x) ((x) << S_STATIC_KX_PLL_N1)
12212 #define G_STATIC_KX_PLL_N1(x) (((x) >> S_STATIC_KX_PLL_N1) & M_STATIC_KX_PLL_N1)
12213 
12214 #define S_STATIC_KX_PLL_N2    7
12215 #define M_STATIC_KX_PLL_N2    0xfU
12216 #define V_STATIC_KX_PLL_N2(x) ((x) << S_STATIC_KX_PLL_N2)
12217 #define G_STATIC_KX_PLL_N2(x) (((x) >> S_STATIC_KX_PLL_N2) & M_STATIC_KX_PLL_N2)
12218 
12219 #define S_STATIC_KX_PLL_N3    3
12220 #define M_STATIC_KX_PLL_N3    0xfU
12221 #define V_STATIC_KX_PLL_N3(x) ((x) << S_STATIC_KX_PLL_N3)
12222 #define G_STATIC_KX_PLL_N3(x) (((x) >> S_STATIC_KX_PLL_N3) & M_STATIC_KX_PLL_N3)
12223 
12224 #define S_STATIC_KX_PLL_P    0
12225 #define M_STATIC_KX_PLL_P    0x7U
12226 #define V_STATIC_KX_PLL_P(x) ((x) << S_STATIC_KX_PLL_P)
12227 #define G_STATIC_KX_PLL_P(x) (((x) >> S_STATIC_KX_PLL_P) & M_STATIC_KX_PLL_P)
12228 
12229 #define A_DBG_STATIC_KR_PLL_CONF 0x6054
12230 
12231 #define S_STATIC_KR_PLL_C    21
12232 #define M_STATIC_KR_PLL_C    0xffU
12233 #define V_STATIC_KR_PLL_C(x) ((x) << S_STATIC_KR_PLL_C)
12234 #define G_STATIC_KR_PLL_C(x) (((x) >> S_STATIC_KR_PLL_C) & M_STATIC_KR_PLL_C)
12235 
12236 #define S_STATIC_KR_PLL_M    15
12237 #define M_STATIC_KR_PLL_M    0x3fU
12238 #define V_STATIC_KR_PLL_M(x) ((x) << S_STATIC_KR_PLL_M)
12239 #define G_STATIC_KR_PLL_M(x) (((x) >> S_STATIC_KR_PLL_M) & M_STATIC_KR_PLL_M)
12240 
12241 #define S_STATIC_KR_PLL_N1    11
12242 #define M_STATIC_KR_PLL_N1    0xfU
12243 #define V_STATIC_KR_PLL_N1(x) ((x) << S_STATIC_KR_PLL_N1)
12244 #define G_STATIC_KR_PLL_N1(x) (((x) >> S_STATIC_KR_PLL_N1) & M_STATIC_KR_PLL_N1)
12245 
12246 #define S_STATIC_KR_PLL_N2    7
12247 #define M_STATIC_KR_PLL_N2    0xfU
12248 #define V_STATIC_KR_PLL_N2(x) ((x) << S_STATIC_KR_PLL_N2)
12249 #define G_STATIC_KR_PLL_N2(x) (((x) >> S_STATIC_KR_PLL_N2) & M_STATIC_KR_PLL_N2)
12250 
12251 #define S_STATIC_KR_PLL_N3    3
12252 #define M_STATIC_KR_PLL_N3    0xfU
12253 #define V_STATIC_KR_PLL_N3(x) ((x) << S_STATIC_KR_PLL_N3)
12254 #define G_STATIC_KR_PLL_N3(x) (((x) >> S_STATIC_KR_PLL_N3) & M_STATIC_KR_PLL_N3)
12255 
12256 #define S_STATIC_KR_PLL_P    0
12257 #define M_STATIC_KR_PLL_P    0x7U
12258 #define V_STATIC_KR_PLL_P(x) ((x) << S_STATIC_KR_PLL_P)
12259 #define G_STATIC_KR_PLL_P(x) (((x) >> S_STATIC_KR_PLL_P) & M_STATIC_KR_PLL_P)
12260 
12261 #define A_DBG_EXTRA_STATIC_BITS_CONF 0x6058
12262 
12263 #define S_STATIC_M_PLL_RESET    30
12264 #define V_STATIC_M_PLL_RESET(x) ((x) << S_STATIC_M_PLL_RESET)
12265 #define F_STATIC_M_PLL_RESET    V_STATIC_M_PLL_RESET(1U)
12266 
12267 #define S_STATIC_M_PLL_SLEEP    29
12268 #define V_STATIC_M_PLL_SLEEP(x) ((x) << S_STATIC_M_PLL_SLEEP)
12269 #define F_STATIC_M_PLL_SLEEP    V_STATIC_M_PLL_SLEEP(1U)
12270 
12271 #define S_STATIC_M_PLL_BYPASS    28
12272 #define V_STATIC_M_PLL_BYPASS(x) ((x) << S_STATIC_M_PLL_BYPASS)
12273 #define F_STATIC_M_PLL_BYPASS    V_STATIC_M_PLL_BYPASS(1U)
12274 
12275 #define S_STATIC_MPLL_CLK_SEL    27
12276 #define V_STATIC_MPLL_CLK_SEL(x) ((x) << S_STATIC_MPLL_CLK_SEL)
12277 #define F_STATIC_MPLL_CLK_SEL    V_STATIC_MPLL_CLK_SEL(1U)
12278 
12279 #define S_STATIC_U_PLL_SLEEP    26
12280 #define V_STATIC_U_PLL_SLEEP(x) ((x) << S_STATIC_U_PLL_SLEEP)
12281 #define F_STATIC_U_PLL_SLEEP    V_STATIC_U_PLL_SLEEP(1U)
12282 
12283 #define S_STATIC_C_PLL_SLEEP    25
12284 #define V_STATIC_C_PLL_SLEEP(x) ((x) << S_STATIC_C_PLL_SLEEP)
12285 #define F_STATIC_C_PLL_SLEEP    V_STATIC_C_PLL_SLEEP(1U)
12286 
12287 #define S_STATIC_LVDS_CLKOUT_SEL    23
12288 #define M_STATIC_LVDS_CLKOUT_SEL    0x3U
12289 #define V_STATIC_LVDS_CLKOUT_SEL(x) ((x) << S_STATIC_LVDS_CLKOUT_SEL)
12290 #define G_STATIC_LVDS_CLKOUT_SEL(x) (((x) >> S_STATIC_LVDS_CLKOUT_SEL) & M_STATIC_LVDS_CLKOUT_SEL)
12291 
12292 #define S_STATIC_LVDS_CLKOUT_EN    22
12293 #define V_STATIC_LVDS_CLKOUT_EN(x) ((x) << S_STATIC_LVDS_CLKOUT_EN)
12294 #define F_STATIC_LVDS_CLKOUT_EN    V_STATIC_LVDS_CLKOUT_EN(1U)
12295 
12296 #define S_STATIC_CCLK_FREQ_SEL    20
12297 #define M_STATIC_CCLK_FREQ_SEL    0x3U
12298 #define V_STATIC_CCLK_FREQ_SEL(x) ((x) << S_STATIC_CCLK_FREQ_SEL)
12299 #define G_STATIC_CCLK_FREQ_SEL(x) (((x) >> S_STATIC_CCLK_FREQ_SEL) & M_STATIC_CCLK_FREQ_SEL)
12300 
12301 #define S_STATIC_UCLK_FREQ_SEL    18
12302 #define M_STATIC_UCLK_FREQ_SEL    0x3U
12303 #define V_STATIC_UCLK_FREQ_SEL(x) ((x) << S_STATIC_UCLK_FREQ_SEL)
12304 #define G_STATIC_UCLK_FREQ_SEL(x) (((x) >> S_STATIC_UCLK_FREQ_SEL) & M_STATIC_UCLK_FREQ_SEL)
12305 
12306 #define S_EXPHYCLK_SEL_EN    17
12307 #define V_EXPHYCLK_SEL_EN(x) ((x) << S_EXPHYCLK_SEL_EN)
12308 #define F_EXPHYCLK_SEL_EN    V_EXPHYCLK_SEL_EN(1U)
12309 
12310 #define S_EXPHYCLK_SEL    15
12311 #define M_EXPHYCLK_SEL    0x3U
12312 #define V_EXPHYCLK_SEL(x) ((x) << S_EXPHYCLK_SEL)
12313 #define G_EXPHYCLK_SEL(x) (((x) >> S_EXPHYCLK_SEL) & M_EXPHYCLK_SEL)
12314 
12315 #define S_STATIC_U_PLL_BYPASS    14
12316 #define V_STATIC_U_PLL_BYPASS(x) ((x) << S_STATIC_U_PLL_BYPASS)
12317 #define F_STATIC_U_PLL_BYPASS    V_STATIC_U_PLL_BYPASS(1U)
12318 
12319 #define S_STATIC_C_PLL_BYPASS    13
12320 #define V_STATIC_C_PLL_BYPASS(x) ((x) << S_STATIC_C_PLL_BYPASS)
12321 #define F_STATIC_C_PLL_BYPASS    V_STATIC_C_PLL_BYPASS(1U)
12322 
12323 #define S_STATIC_KR_PLL_BYPASS    12
12324 #define V_STATIC_KR_PLL_BYPASS(x) ((x) << S_STATIC_KR_PLL_BYPASS)
12325 #define F_STATIC_KR_PLL_BYPASS    V_STATIC_KR_PLL_BYPASS(1U)
12326 
12327 #define S_STATIC_KX_PLL_BYPASS    11
12328 #define V_STATIC_KX_PLL_BYPASS(x) ((x) << S_STATIC_KX_PLL_BYPASS)
12329 #define F_STATIC_KX_PLL_BYPASS    V_STATIC_KX_PLL_BYPASS(1U)
12330 
12331 #define S_STATIC_KX_PLL_V    7
12332 #define M_STATIC_KX_PLL_V    0xfU
12333 #define V_STATIC_KX_PLL_V(x) ((x) << S_STATIC_KX_PLL_V)
12334 #define G_STATIC_KX_PLL_V(x) (((x) >> S_STATIC_KX_PLL_V) & M_STATIC_KX_PLL_V)
12335 
12336 #define S_STATIC_KR_PLL_V    3
12337 #define M_STATIC_KR_PLL_V    0xfU
12338 #define V_STATIC_KR_PLL_V(x) ((x) << S_STATIC_KR_PLL_V)
12339 #define G_STATIC_KR_PLL_V(x) (((x) >> S_STATIC_KR_PLL_V) & M_STATIC_KR_PLL_V)
12340 
12341 #define S_PSRO_SEL    0
12342 #define M_PSRO_SEL    0x7U
12343 #define V_PSRO_SEL(x) ((x) << S_PSRO_SEL)
12344 #define G_PSRO_SEL(x) (((x) >> S_PSRO_SEL) & M_PSRO_SEL)
12345 
12346 #define A_DBG_STATIC_OCLK_MUXSEL_CONF 0x605c
12347 
12348 #define S_M_OCLK_MUXSEL    12
12349 #define V_M_OCLK_MUXSEL(x) ((x) << S_M_OCLK_MUXSEL)
12350 #define F_M_OCLK_MUXSEL    V_M_OCLK_MUXSEL(1U)
12351 
12352 #define S_C_OCLK_MUXSEL    10
12353 #define M_C_OCLK_MUXSEL    0x3U
12354 #define V_C_OCLK_MUXSEL(x) ((x) << S_C_OCLK_MUXSEL)
12355 #define G_C_OCLK_MUXSEL(x) (((x) >> S_C_OCLK_MUXSEL) & M_C_OCLK_MUXSEL)
12356 
12357 #define S_U_OCLK_MUXSEL    8
12358 #define M_U_OCLK_MUXSEL    0x3U
12359 #define V_U_OCLK_MUXSEL(x) ((x) << S_U_OCLK_MUXSEL)
12360 #define G_U_OCLK_MUXSEL(x) (((x) >> S_U_OCLK_MUXSEL) & M_U_OCLK_MUXSEL)
12361 
12362 #define S_P_OCLK_MUXSEL    6
12363 #define M_P_OCLK_MUXSEL    0x3U
12364 #define V_P_OCLK_MUXSEL(x) ((x) << S_P_OCLK_MUXSEL)
12365 #define G_P_OCLK_MUXSEL(x) (((x) >> S_P_OCLK_MUXSEL) & M_P_OCLK_MUXSEL)
12366 
12367 #define S_KX_OCLK_MUXSEL    3
12368 #define M_KX_OCLK_MUXSEL    0x7U
12369 #define V_KX_OCLK_MUXSEL(x) ((x) << S_KX_OCLK_MUXSEL)
12370 #define G_KX_OCLK_MUXSEL(x) (((x) >> S_KX_OCLK_MUXSEL) & M_KX_OCLK_MUXSEL)
12371 
12372 #define S_KR_OCLK_MUXSEL    0
12373 #define M_KR_OCLK_MUXSEL    0x7U
12374 #define V_KR_OCLK_MUXSEL(x) ((x) << S_KR_OCLK_MUXSEL)
12375 #define G_KR_OCLK_MUXSEL(x) (((x) >> S_KR_OCLK_MUXSEL) & M_KR_OCLK_MUXSEL)
12376 
12377 #define S_T5_P_OCLK_MUXSEL    13
12378 #define M_T5_P_OCLK_MUXSEL    0xfU
12379 #define V_T5_P_OCLK_MUXSEL(x) ((x) << S_T5_P_OCLK_MUXSEL)
12380 #define G_T5_P_OCLK_MUXSEL(x) (((x) >> S_T5_P_OCLK_MUXSEL) & M_T5_P_OCLK_MUXSEL)
12381 
12382 #define S_T6_P_OCLK_MUXSEL    13
12383 #define M_T6_P_OCLK_MUXSEL    0xfU
12384 #define V_T6_P_OCLK_MUXSEL(x) ((x) << S_T6_P_OCLK_MUXSEL)
12385 #define G_T6_P_OCLK_MUXSEL(x) (((x) >> S_T6_P_OCLK_MUXSEL) & M_T6_P_OCLK_MUXSEL)
12386 
12387 #define A_DBG_TRACE0_CONF_COMPREG0 0x6060
12388 #define A_DBG_TRACE0_CONF_COMPREG1 0x6064
12389 #define A_DBG_TRACE1_CONF_COMPREG0 0x6068
12390 #define A_DBG_TRACE1_CONF_COMPREG1 0x606c
12391 #define A_DBG_TRACE0_CONF_MASKREG0 0x6070
12392 #define A_DBG_TRACE0_CONF_MASKREG1 0x6074
12393 #define A_DBG_TRACE1_CONF_MASKREG0 0x6078
12394 #define A_DBG_TRACE1_CONF_MASKREG1 0x607c
12395 #define A_DBG_TRACE_COUNTER 0x6080
12396 
12397 #define S_COUNTER1    16
12398 #define M_COUNTER1    0xffffU
12399 #define V_COUNTER1(x) ((x) << S_COUNTER1)
12400 #define G_COUNTER1(x) (((x) >> S_COUNTER1) & M_COUNTER1)
12401 
12402 #define S_COUNTER0    0
12403 #define M_COUNTER0    0xffffU
12404 #define V_COUNTER0(x) ((x) << S_COUNTER0)
12405 #define G_COUNTER0(x) (((x) >> S_COUNTER0) & M_COUNTER0)
12406 
12407 #define A_DBG_STATIC_REFCLK_PERIOD 0x6084
12408 
12409 #define S_STATIC_REFCLK_PERIOD    0
12410 #define M_STATIC_REFCLK_PERIOD    0xffffU
12411 #define V_STATIC_REFCLK_PERIOD(x) ((x) << S_STATIC_REFCLK_PERIOD)
12412 #define G_STATIC_REFCLK_PERIOD(x) (((x) >> S_STATIC_REFCLK_PERIOD) & M_STATIC_REFCLK_PERIOD)
12413 
12414 #define A_DBG_TRACE_CONF 0x6088
12415 
12416 #define S_DBG_TRACE_OPERATE_WITH_TRG    5
12417 #define V_DBG_TRACE_OPERATE_WITH_TRG(x) ((x) << S_DBG_TRACE_OPERATE_WITH_TRG)
12418 #define F_DBG_TRACE_OPERATE_WITH_TRG    V_DBG_TRACE_OPERATE_WITH_TRG(1U)
12419 
12420 #define S_DBG_TRACE_OPERATE_EN    4
12421 #define V_DBG_TRACE_OPERATE_EN(x) ((x) << S_DBG_TRACE_OPERATE_EN)
12422 #define F_DBG_TRACE_OPERATE_EN    V_DBG_TRACE_OPERATE_EN(1U)
12423 
12424 #define S_DBG_OPERATE_INDV_COMBINED    3
12425 #define V_DBG_OPERATE_INDV_COMBINED(x) ((x) << S_DBG_OPERATE_INDV_COMBINED)
12426 #define F_DBG_OPERATE_INDV_COMBINED    V_DBG_OPERATE_INDV_COMBINED(1U)
12427 
12428 #define S_DBG_OPERATE_ORDER_OF_TRIGGER    2
12429 #define V_DBG_OPERATE_ORDER_OF_TRIGGER(x) ((x) << S_DBG_OPERATE_ORDER_OF_TRIGGER)
12430 #define F_DBG_OPERATE_ORDER_OF_TRIGGER    V_DBG_OPERATE_ORDER_OF_TRIGGER(1U)
12431 
12432 #define S_DBG_OPERATE_SGL_DBL_TRIGGER    1
12433 #define V_DBG_OPERATE_SGL_DBL_TRIGGER(x) ((x) << S_DBG_OPERATE_SGL_DBL_TRIGGER)
12434 #define F_DBG_OPERATE_SGL_DBL_TRIGGER    V_DBG_OPERATE_SGL_DBL_TRIGGER(1U)
12435 
12436 #define S_DBG_OPERATE0_OR_1    0
12437 #define V_DBG_OPERATE0_OR_1(x) ((x) << S_DBG_OPERATE0_OR_1)
12438 #define F_DBG_OPERATE0_OR_1    V_DBG_OPERATE0_OR_1(1U)
12439 
12440 #define A_DBG_TRACE_RDEN 0x608c
12441 
12442 #define S_RD_ADDR1    10
12443 #define M_RD_ADDR1    0xffU
12444 #define V_RD_ADDR1(x) ((x) << S_RD_ADDR1)
12445 #define G_RD_ADDR1(x) (((x) >> S_RD_ADDR1) & M_RD_ADDR1)
12446 
12447 #define S_RD_ADDR0    2
12448 #define M_RD_ADDR0    0xffU
12449 #define V_RD_ADDR0(x) ((x) << S_RD_ADDR0)
12450 #define G_RD_ADDR0(x) (((x) >> S_RD_ADDR0) & M_RD_ADDR0)
12451 
12452 #define S_RD_EN1    1
12453 #define V_RD_EN1(x) ((x) << S_RD_EN1)
12454 #define F_RD_EN1    V_RD_EN1(1U)
12455 
12456 #define S_RD_EN0    0
12457 #define V_RD_EN0(x) ((x) << S_RD_EN0)
12458 #define F_RD_EN0    V_RD_EN0(1U)
12459 
12460 #define S_T5_RD_ADDR1    11
12461 #define M_T5_RD_ADDR1    0x1ffU
12462 #define V_T5_RD_ADDR1(x) ((x) << S_T5_RD_ADDR1)
12463 #define G_T5_RD_ADDR1(x) (((x) >> S_T5_RD_ADDR1) & M_T5_RD_ADDR1)
12464 
12465 #define S_T5_RD_ADDR0    2
12466 #define M_T5_RD_ADDR0    0x1ffU
12467 #define V_T5_RD_ADDR0(x) ((x) << S_T5_RD_ADDR0)
12468 #define G_T5_RD_ADDR0(x) (((x) >> S_T5_RD_ADDR0) & M_T5_RD_ADDR0)
12469 
12470 #define S_T6_RD_ADDR1    11
12471 #define M_T6_RD_ADDR1    0x1ffU
12472 #define V_T6_RD_ADDR1(x) ((x) << S_T6_RD_ADDR1)
12473 #define G_T6_RD_ADDR1(x) (((x) >> S_T6_RD_ADDR1) & M_T6_RD_ADDR1)
12474 
12475 #define S_T6_RD_ADDR0    2
12476 #define M_T6_RD_ADDR0    0x1ffU
12477 #define V_T6_RD_ADDR0(x) ((x) << S_T6_RD_ADDR0)
12478 #define G_T6_RD_ADDR0(x) (((x) >> S_T6_RD_ADDR0) & M_T6_RD_ADDR0)
12479 
12480 #define A_DBG_TRACE_WRADDR 0x6090
12481 
12482 #define S_WR_POINTER_ADDR1    16
12483 #define M_WR_POINTER_ADDR1    0xffU
12484 #define V_WR_POINTER_ADDR1(x) ((x) << S_WR_POINTER_ADDR1)
12485 #define G_WR_POINTER_ADDR1(x) (((x) >> S_WR_POINTER_ADDR1) & M_WR_POINTER_ADDR1)
12486 
12487 #define S_WR_POINTER_ADDR0    0
12488 #define M_WR_POINTER_ADDR0    0xffU
12489 #define V_WR_POINTER_ADDR0(x) ((x) << S_WR_POINTER_ADDR0)
12490 #define G_WR_POINTER_ADDR0(x) (((x) >> S_WR_POINTER_ADDR0) & M_WR_POINTER_ADDR0)
12491 
12492 #define S_T5_WR_POINTER_ADDR1    16
12493 #define M_T5_WR_POINTER_ADDR1    0x1ffU
12494 #define V_T5_WR_POINTER_ADDR1(x) ((x) << S_T5_WR_POINTER_ADDR1)
12495 #define G_T5_WR_POINTER_ADDR1(x) (((x) >> S_T5_WR_POINTER_ADDR1) & M_T5_WR_POINTER_ADDR1)
12496 
12497 #define S_T5_WR_POINTER_ADDR0    0
12498 #define M_T5_WR_POINTER_ADDR0    0x1ffU
12499 #define V_T5_WR_POINTER_ADDR0(x) ((x) << S_T5_WR_POINTER_ADDR0)
12500 #define G_T5_WR_POINTER_ADDR0(x) (((x) >> S_T5_WR_POINTER_ADDR0) & M_T5_WR_POINTER_ADDR0)
12501 
12502 #define S_T6_WR_POINTER_ADDR1    16
12503 #define M_T6_WR_POINTER_ADDR1    0x1ffU
12504 #define V_T6_WR_POINTER_ADDR1(x) ((x) << S_T6_WR_POINTER_ADDR1)
12505 #define G_T6_WR_POINTER_ADDR1(x) (((x) >> S_T6_WR_POINTER_ADDR1) & M_T6_WR_POINTER_ADDR1)
12506 
12507 #define S_T6_WR_POINTER_ADDR0    0
12508 #define M_T6_WR_POINTER_ADDR0    0x1ffU
12509 #define V_T6_WR_POINTER_ADDR0(x) ((x) << S_T6_WR_POINTER_ADDR0)
12510 #define G_T6_WR_POINTER_ADDR0(x) (((x) >> S_T6_WR_POINTER_ADDR0) & M_T6_WR_POINTER_ADDR0)
12511 
12512 #define A_DBG_TRACE0_DATA_OUT 0x6094
12513 #define A_DBG_TRACE1_DATA_OUT 0x6098
12514 #define A_DBG_FUSE_SENSE_DONE 0x609c
12515 
12516 #define S_STATIC_JTAG_VERSIONNR    5
12517 #define M_STATIC_JTAG_VERSIONNR    0xfU
12518 #define V_STATIC_JTAG_VERSIONNR(x) ((x) << S_STATIC_JTAG_VERSIONNR)
12519 #define G_STATIC_JTAG_VERSIONNR(x) (((x) >> S_STATIC_JTAG_VERSIONNR) & M_STATIC_JTAG_VERSIONNR)
12520 
12521 #define S_UNQ0    1
12522 #define M_UNQ0    0xfU
12523 #define V_UNQ0(x) ((x) << S_UNQ0)
12524 #define G_UNQ0(x) (((x) >> S_UNQ0) & M_UNQ0)
12525 
12526 #define S_FUSE_DONE_SENSE    0
12527 #define V_FUSE_DONE_SENSE(x) ((x) << S_FUSE_DONE_SENSE)
12528 #define F_FUSE_DONE_SENSE    V_FUSE_DONE_SENSE(1U)
12529 
12530 #define A_DBG_TVSENSE_EN 0x60a8
12531 
12532 #define S_MCIMPED1_OUT    29
12533 #define V_MCIMPED1_OUT(x) ((x) << S_MCIMPED1_OUT)
12534 #define F_MCIMPED1_OUT    V_MCIMPED1_OUT(1U)
12535 
12536 #define S_MCIMPED2_OUT    28
12537 #define V_MCIMPED2_OUT(x) ((x) << S_MCIMPED2_OUT)
12538 #define F_MCIMPED2_OUT    V_MCIMPED2_OUT(1U)
12539 
12540 #define S_TVSENSE_SNSOUT    17
12541 #define M_TVSENSE_SNSOUT    0x1ffU
12542 #define V_TVSENSE_SNSOUT(x) ((x) << S_TVSENSE_SNSOUT)
12543 #define G_TVSENSE_SNSOUT(x) (((x) >> S_TVSENSE_SNSOUT) & M_TVSENSE_SNSOUT)
12544 
12545 #define S_TVSENSE_OUTPUTVALID    16
12546 #define V_TVSENSE_OUTPUTVALID(x) ((x) << S_TVSENSE_OUTPUTVALID)
12547 #define F_TVSENSE_OUTPUTVALID    V_TVSENSE_OUTPUTVALID(1U)
12548 
12549 #define S_TVSENSE_SLEEP    10
12550 #define V_TVSENSE_SLEEP(x) ((x) << S_TVSENSE_SLEEP)
12551 #define F_TVSENSE_SLEEP    V_TVSENSE_SLEEP(1U)
12552 
12553 #define S_TVSENSE_SENSV    9
12554 #define V_TVSENSE_SENSV(x) ((x) << S_TVSENSE_SENSV)
12555 #define F_TVSENSE_SENSV    V_TVSENSE_SENSV(1U)
12556 
12557 #define S_TVSENSE_RST    8
12558 #define V_TVSENSE_RST(x) ((x) << S_TVSENSE_RST)
12559 #define F_TVSENSE_RST    V_TVSENSE_RST(1U)
12560 
12561 #define S_TVSENSE_RATIO    0
12562 #define M_TVSENSE_RATIO    0xffU
12563 #define V_TVSENSE_RATIO(x) ((x) << S_TVSENSE_RATIO)
12564 #define G_TVSENSE_RATIO(x) (((x) >> S_TVSENSE_RATIO) & M_TVSENSE_RATIO)
12565 
12566 #define S_T6_TVSENSE_SLEEP    11
12567 #define V_T6_TVSENSE_SLEEP(x) ((x) << S_T6_TVSENSE_SLEEP)
12568 #define F_T6_TVSENSE_SLEEP    V_T6_TVSENSE_SLEEP(1U)
12569 
12570 #define S_T6_TVSENSE_SENSV    10
12571 #define V_T6_TVSENSE_SENSV(x) ((x) << S_T6_TVSENSE_SENSV)
12572 #define F_T6_TVSENSE_SENSV    V_T6_TVSENSE_SENSV(1U)
12573 
12574 #define S_T6_TVSENSE_RST    9
12575 #define V_T6_TVSENSE_RST(x) ((x) << S_T6_TVSENSE_RST)
12576 #define F_T6_TVSENSE_RST    V_T6_TVSENSE_RST(1U)
12577 
12578 #define A_DBG_CUST_EFUSE_OUT_EN 0x60ac
12579 #define A_DBG_CUST_EFUSE_SEL1_EN 0x60b0
12580 #define A_DBG_CUST_EFUSE_SEL2_EN 0x60b4
12581 
12582 #define S_DBG_FEENABLE    29
12583 #define V_DBG_FEENABLE(x) ((x) << S_DBG_FEENABLE)
12584 #define F_DBG_FEENABLE    V_DBG_FEENABLE(1U)
12585 
12586 #define S_DBG_FEF    23
12587 #define M_DBG_FEF    0x3fU
12588 #define V_DBG_FEF(x) ((x) << S_DBG_FEF)
12589 #define G_DBG_FEF(x) (((x) >> S_DBG_FEF) & M_DBG_FEF)
12590 
12591 #define S_DBG_FEMIMICN    22
12592 #define V_DBG_FEMIMICN(x) ((x) << S_DBG_FEMIMICN)
12593 #define F_DBG_FEMIMICN    V_DBG_FEMIMICN(1U)
12594 
12595 #define S_DBG_FEGATEC    21
12596 #define V_DBG_FEGATEC(x) ((x) << S_DBG_FEGATEC)
12597 #define F_DBG_FEGATEC    V_DBG_FEGATEC(1U)
12598 
12599 #define S_DBG_FEPROGP    20
12600 #define V_DBG_FEPROGP(x) ((x) << S_DBG_FEPROGP)
12601 #define F_DBG_FEPROGP    V_DBG_FEPROGP(1U)
12602 
12603 #define S_DBG_FEREADCLK    19
12604 #define V_DBG_FEREADCLK(x) ((x) << S_DBG_FEREADCLK)
12605 #define F_DBG_FEREADCLK    V_DBG_FEREADCLK(1U)
12606 
12607 #define S_DBG_FERSEL    3
12608 #define M_DBG_FERSEL    0xffffU
12609 #define V_DBG_FERSEL(x) ((x) << S_DBG_FERSEL)
12610 #define G_DBG_FERSEL(x) (((x) >> S_DBG_FERSEL) & M_DBG_FERSEL)
12611 
12612 #define S_DBG_FETIME    0
12613 #define M_DBG_FETIME    0x7U
12614 #define V_DBG_FETIME(x) ((x) << S_DBG_FETIME)
12615 #define G_DBG_FETIME(x) (((x) >> S_DBG_FETIME) & M_DBG_FETIME)
12616 
12617 #define A_DBG_T5_STATIC_M_PLL_CONF1 0x60b8
12618 
12619 #define S_T5_STATIC_M_PLL_MULTFRAC    8
12620 #define M_T5_STATIC_M_PLL_MULTFRAC    0xffffffU
12621 #define V_T5_STATIC_M_PLL_MULTFRAC(x) ((x) << S_T5_STATIC_M_PLL_MULTFRAC)
12622 #define G_T5_STATIC_M_PLL_MULTFRAC(x) (((x) >> S_T5_STATIC_M_PLL_MULTFRAC) & M_T5_STATIC_M_PLL_MULTFRAC)
12623 
12624 #define S_T5_STATIC_M_PLL_FFSLEWRATE    0
12625 #define M_T5_STATIC_M_PLL_FFSLEWRATE    0xffU
12626 #define V_T5_STATIC_M_PLL_FFSLEWRATE(x) ((x) << S_T5_STATIC_M_PLL_FFSLEWRATE)
12627 #define G_T5_STATIC_M_PLL_FFSLEWRATE(x) (((x) >> S_T5_STATIC_M_PLL_FFSLEWRATE) & M_T5_STATIC_M_PLL_FFSLEWRATE)
12628 
12629 #define A_DBG_STATIC_M_PLL_CONF1 0x60b8
12630 
12631 #define S_STATIC_M_PLL_MULTFRAC    8
12632 #define M_STATIC_M_PLL_MULTFRAC    0xffffffU
12633 #define V_STATIC_M_PLL_MULTFRAC(x) ((x) << S_STATIC_M_PLL_MULTFRAC)
12634 #define G_STATIC_M_PLL_MULTFRAC(x) (((x) >> S_STATIC_M_PLL_MULTFRAC) & M_STATIC_M_PLL_MULTFRAC)
12635 
12636 #define S_STATIC_M_PLL_FFSLEWRATE    0
12637 #define M_STATIC_M_PLL_FFSLEWRATE    0xffU
12638 #define V_STATIC_M_PLL_FFSLEWRATE(x) ((x) << S_STATIC_M_PLL_FFSLEWRATE)
12639 #define G_STATIC_M_PLL_FFSLEWRATE(x) (((x) >> S_STATIC_M_PLL_FFSLEWRATE) & M_STATIC_M_PLL_FFSLEWRATE)
12640 
12641 #define A_DBG_T5_STATIC_M_PLL_CONF2 0x60bc
12642 
12643 #define S_T5_STATIC_M_PLL_DCO_BYPASS    23
12644 #define V_T5_STATIC_M_PLL_DCO_BYPASS(x) ((x) << S_T5_STATIC_M_PLL_DCO_BYPASS)
12645 #define F_T5_STATIC_M_PLL_DCO_BYPASS    V_T5_STATIC_M_PLL_DCO_BYPASS(1U)
12646 
12647 #define S_T5_STATIC_M_PLL_SDORDER    21
12648 #define M_T5_STATIC_M_PLL_SDORDER    0x3U
12649 #define V_T5_STATIC_M_PLL_SDORDER(x) ((x) << S_T5_STATIC_M_PLL_SDORDER)
12650 #define G_T5_STATIC_M_PLL_SDORDER(x) (((x) >> S_T5_STATIC_M_PLL_SDORDER) & M_T5_STATIC_M_PLL_SDORDER)
12651 
12652 #define S_T5_STATIC_M_PLL_FFENABLE    20
12653 #define V_T5_STATIC_M_PLL_FFENABLE(x) ((x) << S_T5_STATIC_M_PLL_FFENABLE)
12654 #define F_T5_STATIC_M_PLL_FFENABLE    V_T5_STATIC_M_PLL_FFENABLE(1U)
12655 
12656 #define S_T5_STATIC_M_PLL_STOPCLKB    19
12657 #define V_T5_STATIC_M_PLL_STOPCLKB(x) ((x) << S_T5_STATIC_M_PLL_STOPCLKB)
12658 #define F_T5_STATIC_M_PLL_STOPCLKB    V_T5_STATIC_M_PLL_STOPCLKB(1U)
12659 
12660 #define S_T5_STATIC_M_PLL_STOPCLKA    18
12661 #define V_T5_STATIC_M_PLL_STOPCLKA(x) ((x) << S_T5_STATIC_M_PLL_STOPCLKA)
12662 #define F_T5_STATIC_M_PLL_STOPCLKA    V_T5_STATIC_M_PLL_STOPCLKA(1U)
12663 
12664 #define S_T5_STATIC_M_PLL_SLEEP    17
12665 #define V_T5_STATIC_M_PLL_SLEEP(x) ((x) << S_T5_STATIC_M_PLL_SLEEP)
12666 #define F_T5_STATIC_M_PLL_SLEEP    V_T5_STATIC_M_PLL_SLEEP(1U)
12667 
12668 #define S_T5_STATIC_M_PLL_BYPASS    16
12669 #define V_T5_STATIC_M_PLL_BYPASS(x) ((x) << S_T5_STATIC_M_PLL_BYPASS)
12670 #define F_T5_STATIC_M_PLL_BYPASS    V_T5_STATIC_M_PLL_BYPASS(1U)
12671 
12672 #define S_T5_STATIC_M_PLL_LOCKTUNE    0
12673 #define M_T5_STATIC_M_PLL_LOCKTUNE    0xffffU
12674 #define V_T5_STATIC_M_PLL_LOCKTUNE(x) ((x) << S_T5_STATIC_M_PLL_LOCKTUNE)
12675 #define G_T5_STATIC_M_PLL_LOCKTUNE(x) (((x) >> S_T5_STATIC_M_PLL_LOCKTUNE) & M_T5_STATIC_M_PLL_LOCKTUNE)
12676 
12677 #define A_DBG_STATIC_M_PLL_CONF2 0x60bc
12678 
12679 #define S_T6_STATIC_M_PLL_PREDIV    24
12680 #define M_T6_STATIC_M_PLL_PREDIV    0x3fU
12681 #define V_T6_STATIC_M_PLL_PREDIV(x) ((x) << S_T6_STATIC_M_PLL_PREDIV)
12682 #define G_T6_STATIC_M_PLL_PREDIV(x) (((x) >> S_T6_STATIC_M_PLL_PREDIV) & M_T6_STATIC_M_PLL_PREDIV)
12683 
12684 #define S_STATIC_M_PLL_DCO_BYPASS    23
12685 #define V_STATIC_M_PLL_DCO_BYPASS(x) ((x) << S_STATIC_M_PLL_DCO_BYPASS)
12686 #define F_STATIC_M_PLL_DCO_BYPASS    V_STATIC_M_PLL_DCO_BYPASS(1U)
12687 
12688 #define S_STATIC_M_PLL_SDORDER    21
12689 #define M_STATIC_M_PLL_SDORDER    0x3U
12690 #define V_STATIC_M_PLL_SDORDER(x) ((x) << S_STATIC_M_PLL_SDORDER)
12691 #define G_STATIC_M_PLL_SDORDER(x) (((x) >> S_STATIC_M_PLL_SDORDER) & M_STATIC_M_PLL_SDORDER)
12692 
12693 #define S_STATIC_M_PLL_FFENABLE    20
12694 #define V_STATIC_M_PLL_FFENABLE(x) ((x) << S_STATIC_M_PLL_FFENABLE)
12695 #define F_STATIC_M_PLL_FFENABLE    V_STATIC_M_PLL_FFENABLE(1U)
12696 
12697 #define S_STATIC_M_PLL_STOPCLKB    19
12698 #define V_STATIC_M_PLL_STOPCLKB(x) ((x) << S_STATIC_M_PLL_STOPCLKB)
12699 #define F_STATIC_M_PLL_STOPCLKB    V_STATIC_M_PLL_STOPCLKB(1U)
12700 
12701 #define S_STATIC_M_PLL_STOPCLKA    18
12702 #define V_STATIC_M_PLL_STOPCLKA(x) ((x) << S_STATIC_M_PLL_STOPCLKA)
12703 #define F_STATIC_M_PLL_STOPCLKA    V_STATIC_M_PLL_STOPCLKA(1U)
12704 
12705 #define S_T6_STATIC_M_PLL_SLEEP    17
12706 #define V_T6_STATIC_M_PLL_SLEEP(x) ((x) << S_T6_STATIC_M_PLL_SLEEP)
12707 #define F_T6_STATIC_M_PLL_SLEEP    V_T6_STATIC_M_PLL_SLEEP(1U)
12708 
12709 #define S_T6_STATIC_M_PLL_BYPASS    16
12710 #define V_T6_STATIC_M_PLL_BYPASS(x) ((x) << S_T6_STATIC_M_PLL_BYPASS)
12711 #define F_T6_STATIC_M_PLL_BYPASS    V_T6_STATIC_M_PLL_BYPASS(1U)
12712 
12713 #define S_STATIC_M_PLL_LOCKTUNE    0
12714 #define M_STATIC_M_PLL_LOCKTUNE    0x1fU
12715 #define V_STATIC_M_PLL_LOCKTUNE(x) ((x) << S_STATIC_M_PLL_LOCKTUNE)
12716 #define G_STATIC_M_PLL_LOCKTUNE(x) (((x) >> S_STATIC_M_PLL_LOCKTUNE) & M_STATIC_M_PLL_LOCKTUNE)
12717 
12718 #define A_DBG_T5_STATIC_M_PLL_CONF3 0x60c0
12719 
12720 #define S_T5_STATIC_M_PLL_MULTPRE    30
12721 #define M_T5_STATIC_M_PLL_MULTPRE    0x3U
12722 #define V_T5_STATIC_M_PLL_MULTPRE(x) ((x) << S_T5_STATIC_M_PLL_MULTPRE)
12723 #define G_T5_STATIC_M_PLL_MULTPRE(x) (((x) >> S_T5_STATIC_M_PLL_MULTPRE) & M_T5_STATIC_M_PLL_MULTPRE)
12724 
12725 #define S_T5_STATIC_M_PLL_LOCKSEL    28
12726 #define M_T5_STATIC_M_PLL_LOCKSEL    0x3U
12727 #define V_T5_STATIC_M_PLL_LOCKSEL(x) ((x) << S_T5_STATIC_M_PLL_LOCKSEL)
12728 #define G_T5_STATIC_M_PLL_LOCKSEL(x) (((x) >> S_T5_STATIC_M_PLL_LOCKSEL) & M_T5_STATIC_M_PLL_LOCKSEL)
12729 
12730 #define S_T5_STATIC_M_PLL_FFTUNE    12
12731 #define M_T5_STATIC_M_PLL_FFTUNE    0xffffU
12732 #define V_T5_STATIC_M_PLL_FFTUNE(x) ((x) << S_T5_STATIC_M_PLL_FFTUNE)
12733 #define G_T5_STATIC_M_PLL_FFTUNE(x) (((x) >> S_T5_STATIC_M_PLL_FFTUNE) & M_T5_STATIC_M_PLL_FFTUNE)
12734 
12735 #define S_T5_STATIC_M_PLL_RANGEPRE    10
12736 #define M_T5_STATIC_M_PLL_RANGEPRE    0x3U
12737 #define V_T5_STATIC_M_PLL_RANGEPRE(x) ((x) << S_T5_STATIC_M_PLL_RANGEPRE)
12738 #define G_T5_STATIC_M_PLL_RANGEPRE(x) (((x) >> S_T5_STATIC_M_PLL_RANGEPRE) & M_T5_STATIC_M_PLL_RANGEPRE)
12739 
12740 #define S_T5_STATIC_M_PLL_RANGEB    5
12741 #define M_T5_STATIC_M_PLL_RANGEB    0x1fU
12742 #define V_T5_STATIC_M_PLL_RANGEB(x) ((x) << S_T5_STATIC_M_PLL_RANGEB)
12743 #define G_T5_STATIC_M_PLL_RANGEB(x) (((x) >> S_T5_STATIC_M_PLL_RANGEB) & M_T5_STATIC_M_PLL_RANGEB)
12744 
12745 #define S_T5_STATIC_M_PLL_RANGEA    0
12746 #define M_T5_STATIC_M_PLL_RANGEA    0x1fU
12747 #define V_T5_STATIC_M_PLL_RANGEA(x) ((x) << S_T5_STATIC_M_PLL_RANGEA)
12748 #define G_T5_STATIC_M_PLL_RANGEA(x) (((x) >> S_T5_STATIC_M_PLL_RANGEA) & M_T5_STATIC_M_PLL_RANGEA)
12749 
12750 #define A_DBG_STATIC_M_PLL_CONF3 0x60c0
12751 
12752 #define S_STATIC_M_PLL_MULTPRE    30
12753 #define M_STATIC_M_PLL_MULTPRE    0x3U
12754 #define V_STATIC_M_PLL_MULTPRE(x) ((x) << S_STATIC_M_PLL_MULTPRE)
12755 #define G_STATIC_M_PLL_MULTPRE(x) (((x) >> S_STATIC_M_PLL_MULTPRE) & M_STATIC_M_PLL_MULTPRE)
12756 
12757 #define S_STATIC_M_PLL_LOCKSEL    28
12758 #define V_STATIC_M_PLL_LOCKSEL(x) ((x) << S_STATIC_M_PLL_LOCKSEL)
12759 #define F_STATIC_M_PLL_LOCKSEL    V_STATIC_M_PLL_LOCKSEL(1U)
12760 
12761 #define S_STATIC_M_PLL_FFTUNE    12
12762 #define M_STATIC_M_PLL_FFTUNE    0xffffU
12763 #define V_STATIC_M_PLL_FFTUNE(x) ((x) << S_STATIC_M_PLL_FFTUNE)
12764 #define G_STATIC_M_PLL_FFTUNE(x) (((x) >> S_STATIC_M_PLL_FFTUNE) & M_STATIC_M_PLL_FFTUNE)
12765 
12766 #define S_STATIC_M_PLL_RANGEPRE    10
12767 #define M_STATIC_M_PLL_RANGEPRE    0x3U
12768 #define V_STATIC_M_PLL_RANGEPRE(x) ((x) << S_STATIC_M_PLL_RANGEPRE)
12769 #define G_STATIC_M_PLL_RANGEPRE(x) (((x) >> S_STATIC_M_PLL_RANGEPRE) & M_STATIC_M_PLL_RANGEPRE)
12770 
12771 #define S_T6_STATIC_M_PLL_RANGEB    5
12772 #define M_T6_STATIC_M_PLL_RANGEB    0x1fU
12773 #define V_T6_STATIC_M_PLL_RANGEB(x) ((x) << S_T6_STATIC_M_PLL_RANGEB)
12774 #define G_T6_STATIC_M_PLL_RANGEB(x) (((x) >> S_T6_STATIC_M_PLL_RANGEB) & M_T6_STATIC_M_PLL_RANGEB)
12775 
12776 #define S_T6_STATIC_M_PLL_RANGEA    0
12777 #define M_T6_STATIC_M_PLL_RANGEA    0x1fU
12778 #define V_T6_STATIC_M_PLL_RANGEA(x) ((x) << S_T6_STATIC_M_PLL_RANGEA)
12779 #define G_T6_STATIC_M_PLL_RANGEA(x) (((x) >> S_T6_STATIC_M_PLL_RANGEA) & M_T6_STATIC_M_PLL_RANGEA)
12780 
12781 #define A_DBG_T5_STATIC_M_PLL_CONF4 0x60c4
12782 #define A_DBG_STATIC_M_PLL_CONF4 0x60c4
12783 #define A_DBG_T5_STATIC_M_PLL_CONF5 0x60c8
12784 
12785 #define S_T5_STATIC_M_PLL_VCVTUNE    24
12786 #define M_T5_STATIC_M_PLL_VCVTUNE    0x7U
12787 #define V_T5_STATIC_M_PLL_VCVTUNE(x) ((x) << S_T5_STATIC_M_PLL_VCVTUNE)
12788 #define G_T5_STATIC_M_PLL_VCVTUNE(x) (((x) >> S_T5_STATIC_M_PLL_VCVTUNE) & M_T5_STATIC_M_PLL_VCVTUNE)
12789 
12790 #define S_T5_STATIC_M_PLL_RESET    23
12791 #define V_T5_STATIC_M_PLL_RESET(x) ((x) << S_T5_STATIC_M_PLL_RESET)
12792 #define F_T5_STATIC_M_PLL_RESET    V_T5_STATIC_M_PLL_RESET(1U)
12793 
12794 #define S_T5_STATIC_MPLL_REFCLK_SEL    22
12795 #define V_T5_STATIC_MPLL_REFCLK_SEL(x) ((x) << S_T5_STATIC_MPLL_REFCLK_SEL)
12796 #define F_T5_STATIC_MPLL_REFCLK_SEL    V_T5_STATIC_MPLL_REFCLK_SEL(1U)
12797 
12798 #define S_T5_STATIC_M_PLL_LFTUNE_32_40    13
12799 #define M_T5_STATIC_M_PLL_LFTUNE_32_40    0x1ffU
12800 #define V_T5_STATIC_M_PLL_LFTUNE_32_40(x) ((x) << S_T5_STATIC_M_PLL_LFTUNE_32_40)
12801 #define G_T5_STATIC_M_PLL_LFTUNE_32_40(x) (((x) >> S_T5_STATIC_M_PLL_LFTUNE_32_40) & M_T5_STATIC_M_PLL_LFTUNE_32_40)
12802 
12803 #define S_T5_STATIC_M_PLL_PREDIV    8
12804 #define M_T5_STATIC_M_PLL_PREDIV    0x1fU
12805 #define V_T5_STATIC_M_PLL_PREDIV(x) ((x) << S_T5_STATIC_M_PLL_PREDIV)
12806 #define G_T5_STATIC_M_PLL_PREDIV(x) (((x) >> S_T5_STATIC_M_PLL_PREDIV) & M_T5_STATIC_M_PLL_PREDIV)
12807 
12808 #define S_T5_STATIC_M_PLL_MULT    0
12809 #define M_T5_STATIC_M_PLL_MULT    0xffU
12810 #define V_T5_STATIC_M_PLL_MULT(x) ((x) << S_T5_STATIC_M_PLL_MULT)
12811 #define G_T5_STATIC_M_PLL_MULT(x) (((x) >> S_T5_STATIC_M_PLL_MULT) & M_T5_STATIC_M_PLL_MULT)
12812 
12813 #define A_DBG_STATIC_M_PLL_CONF5 0x60c8
12814 
12815 #define S_STATIC_M_PLL_VCVTUNE    24
12816 #define M_STATIC_M_PLL_VCVTUNE    0x7U
12817 #define V_STATIC_M_PLL_VCVTUNE(x) ((x) << S_STATIC_M_PLL_VCVTUNE)
12818 #define G_STATIC_M_PLL_VCVTUNE(x) (((x) >> S_STATIC_M_PLL_VCVTUNE) & M_STATIC_M_PLL_VCVTUNE)
12819 
12820 #define S_T6_STATIC_M_PLL_RESET    23
12821 #define V_T6_STATIC_M_PLL_RESET(x) ((x) << S_T6_STATIC_M_PLL_RESET)
12822 #define F_T6_STATIC_M_PLL_RESET    V_T6_STATIC_M_PLL_RESET(1U)
12823 
12824 #define S_STATIC_MPLL_REFCLK_SEL    22
12825 #define V_STATIC_MPLL_REFCLK_SEL(x) ((x) << S_STATIC_MPLL_REFCLK_SEL)
12826 #define F_STATIC_MPLL_REFCLK_SEL    V_STATIC_MPLL_REFCLK_SEL(1U)
12827 
12828 #define S_STATIC_M_PLL_LFTUNE_32_40    13
12829 #define M_STATIC_M_PLL_LFTUNE_32_40    0x1ffU
12830 #define V_STATIC_M_PLL_LFTUNE_32_40(x) ((x) << S_STATIC_M_PLL_LFTUNE_32_40)
12831 #define G_STATIC_M_PLL_LFTUNE_32_40(x) (((x) >> S_STATIC_M_PLL_LFTUNE_32_40) & M_STATIC_M_PLL_LFTUNE_32_40)
12832 
12833 #define S_T6_STATIC_M_PLL_MULT    0
12834 #define M_T6_STATIC_M_PLL_MULT    0xffU
12835 #define V_T6_STATIC_M_PLL_MULT(x) ((x) << S_T6_STATIC_M_PLL_MULT)
12836 #define G_T6_STATIC_M_PLL_MULT(x) (((x) >> S_T6_STATIC_M_PLL_MULT) & M_T6_STATIC_M_PLL_MULT)
12837 
12838 #define A_DBG_T5_STATIC_M_PLL_CONF6 0x60cc
12839 
12840 #define S_T5_STATIC_PHY0RECRST_    5
12841 #define V_T5_STATIC_PHY0RECRST_(x) ((x) << S_T5_STATIC_PHY0RECRST_)
12842 #define F_T5_STATIC_PHY0RECRST_    V_T5_STATIC_PHY0RECRST_(1U)
12843 
12844 #define S_T5_STATIC_PHY1RECRST_    4
12845 #define V_T5_STATIC_PHY1RECRST_(x) ((x) << S_T5_STATIC_PHY1RECRST_)
12846 #define F_T5_STATIC_PHY1RECRST_    V_T5_STATIC_PHY1RECRST_(1U)
12847 
12848 #define S_T5_STATIC_SWMC0RST_    3
12849 #define V_T5_STATIC_SWMC0RST_(x) ((x) << S_T5_STATIC_SWMC0RST_)
12850 #define F_T5_STATIC_SWMC0RST_    V_T5_STATIC_SWMC0RST_(1U)
12851 
12852 #define S_T5_STATIC_SWMC0CFGRST_    2
12853 #define V_T5_STATIC_SWMC0CFGRST_(x) ((x) << S_T5_STATIC_SWMC0CFGRST_)
12854 #define F_T5_STATIC_SWMC0CFGRST_    V_T5_STATIC_SWMC0CFGRST_(1U)
12855 
12856 #define S_T5_STATIC_SWMC1RST_    1
12857 #define V_T5_STATIC_SWMC1RST_(x) ((x) << S_T5_STATIC_SWMC1RST_)
12858 #define F_T5_STATIC_SWMC1RST_    V_T5_STATIC_SWMC1RST_(1U)
12859 
12860 #define S_T5_STATIC_SWMC1CFGRST_    0
12861 #define V_T5_STATIC_SWMC1CFGRST_(x) ((x) << S_T5_STATIC_SWMC1CFGRST_)
12862 #define F_T5_STATIC_SWMC1CFGRST_    V_T5_STATIC_SWMC1CFGRST_(1U)
12863 
12864 #define A_DBG_STATIC_M_PLL_CONF6 0x60cc
12865 
12866 #define S_STATIC_M_PLL_DIVCHANGE    30
12867 #define V_STATIC_M_PLL_DIVCHANGE(x) ((x) << S_STATIC_M_PLL_DIVCHANGE)
12868 #define F_STATIC_M_PLL_DIVCHANGE    V_STATIC_M_PLL_DIVCHANGE(1U)
12869 
12870 #define S_STATIC_M_PLL_FRAMESTOP    29
12871 #define V_STATIC_M_PLL_FRAMESTOP(x) ((x) << S_STATIC_M_PLL_FRAMESTOP)
12872 #define F_STATIC_M_PLL_FRAMESTOP    V_STATIC_M_PLL_FRAMESTOP(1U)
12873 
12874 #define S_STATIC_M_PLL_FASTSTOP    28
12875 #define V_STATIC_M_PLL_FASTSTOP(x) ((x) << S_STATIC_M_PLL_FASTSTOP)
12876 #define F_STATIC_M_PLL_FASTSTOP    V_STATIC_M_PLL_FASTSTOP(1U)
12877 
12878 #define S_STATIC_M_PLL_FFBYPASS    27
12879 #define V_STATIC_M_PLL_FFBYPASS(x) ((x) << S_STATIC_M_PLL_FFBYPASS)
12880 #define F_STATIC_M_PLL_FFBYPASS    V_STATIC_M_PLL_FFBYPASS(1U)
12881 
12882 #define S_STATIC_M_PLL_STARTUP    25
12883 #define M_STATIC_M_PLL_STARTUP    0x3U
12884 #define V_STATIC_M_PLL_STARTUP(x) ((x) << S_STATIC_M_PLL_STARTUP)
12885 #define G_STATIC_M_PLL_STARTUP(x) (((x) >> S_STATIC_M_PLL_STARTUP) & M_STATIC_M_PLL_STARTUP)
12886 
12887 #define S_STATIC_M_PLL_VREGTUNE    6
12888 #define M_STATIC_M_PLL_VREGTUNE    0x7ffffU
12889 #define V_STATIC_M_PLL_VREGTUNE(x) ((x) << S_STATIC_M_PLL_VREGTUNE)
12890 #define G_STATIC_M_PLL_VREGTUNE(x) (((x) >> S_STATIC_M_PLL_VREGTUNE) & M_STATIC_M_PLL_VREGTUNE)
12891 
12892 #define S_STATIC_PHY0RECRST_    5
12893 #define V_STATIC_PHY0RECRST_(x) ((x) << S_STATIC_PHY0RECRST_)
12894 #define F_STATIC_PHY0RECRST_    V_STATIC_PHY0RECRST_(1U)
12895 
12896 #define S_STATIC_PHY1RECRST_    4
12897 #define V_STATIC_PHY1RECRST_(x) ((x) << S_STATIC_PHY1RECRST_)
12898 #define F_STATIC_PHY1RECRST_    V_STATIC_PHY1RECRST_(1U)
12899 
12900 #define S_STATIC_SWMC0RST_    3
12901 #define V_STATIC_SWMC0RST_(x) ((x) << S_STATIC_SWMC0RST_)
12902 #define F_STATIC_SWMC0RST_    V_STATIC_SWMC0RST_(1U)
12903 
12904 #define S_STATIC_SWMC0CFGRST_    2
12905 #define V_STATIC_SWMC0CFGRST_(x) ((x) << S_STATIC_SWMC0CFGRST_)
12906 #define F_STATIC_SWMC0CFGRST_    V_STATIC_SWMC0CFGRST_(1U)
12907 
12908 #define S_STATIC_SWMC1RST_    1
12909 #define V_STATIC_SWMC1RST_(x) ((x) << S_STATIC_SWMC1RST_)
12910 #define F_STATIC_SWMC1RST_    V_STATIC_SWMC1RST_(1U)
12911 
12912 #define S_STATIC_SWMC1CFGRST_    0
12913 #define V_STATIC_SWMC1CFGRST_(x) ((x) << S_STATIC_SWMC1CFGRST_)
12914 #define F_STATIC_SWMC1CFGRST_    V_STATIC_SWMC1CFGRST_(1U)
12915 
12916 #define A_DBG_T5_STATIC_C_PLL_CONF1 0x60d0
12917 
12918 #define S_T5_STATIC_C_PLL_MULTFRAC    8
12919 #define M_T5_STATIC_C_PLL_MULTFRAC    0xffffffU
12920 #define V_T5_STATIC_C_PLL_MULTFRAC(x) ((x) << S_T5_STATIC_C_PLL_MULTFRAC)
12921 #define G_T5_STATIC_C_PLL_MULTFRAC(x) (((x) >> S_T5_STATIC_C_PLL_MULTFRAC) & M_T5_STATIC_C_PLL_MULTFRAC)
12922 
12923 #define S_T5_STATIC_C_PLL_FFSLEWRATE    0
12924 #define M_T5_STATIC_C_PLL_FFSLEWRATE    0xffU
12925 #define V_T5_STATIC_C_PLL_FFSLEWRATE(x) ((x) << S_T5_STATIC_C_PLL_FFSLEWRATE)
12926 #define G_T5_STATIC_C_PLL_FFSLEWRATE(x) (((x) >> S_T5_STATIC_C_PLL_FFSLEWRATE) & M_T5_STATIC_C_PLL_FFSLEWRATE)
12927 
12928 #define A_DBG_STATIC_C_PLL_CONF1 0x60d0
12929 
12930 #define S_STATIC_C_PLL_MULTFRAC    8
12931 #define M_STATIC_C_PLL_MULTFRAC    0xffffffU
12932 #define V_STATIC_C_PLL_MULTFRAC(x) ((x) << S_STATIC_C_PLL_MULTFRAC)
12933 #define G_STATIC_C_PLL_MULTFRAC(x) (((x) >> S_STATIC_C_PLL_MULTFRAC) & M_STATIC_C_PLL_MULTFRAC)
12934 
12935 #define S_STATIC_C_PLL_FFSLEWRATE    0
12936 #define M_STATIC_C_PLL_FFSLEWRATE    0xffU
12937 #define V_STATIC_C_PLL_FFSLEWRATE(x) ((x) << S_STATIC_C_PLL_FFSLEWRATE)
12938 #define G_STATIC_C_PLL_FFSLEWRATE(x) (((x) >> S_STATIC_C_PLL_FFSLEWRATE) & M_STATIC_C_PLL_FFSLEWRATE)
12939 
12940 #define A_DBG_T5_STATIC_C_PLL_CONF2 0x60d4
12941 
12942 #define S_T5_STATIC_C_PLL_DCO_BYPASS    23
12943 #define V_T5_STATIC_C_PLL_DCO_BYPASS(x) ((x) << S_T5_STATIC_C_PLL_DCO_BYPASS)
12944 #define F_T5_STATIC_C_PLL_DCO_BYPASS    V_T5_STATIC_C_PLL_DCO_BYPASS(1U)
12945 
12946 #define S_T5_STATIC_C_PLL_SDORDER    21
12947 #define M_T5_STATIC_C_PLL_SDORDER    0x3U
12948 #define V_T5_STATIC_C_PLL_SDORDER(x) ((x) << S_T5_STATIC_C_PLL_SDORDER)
12949 #define G_T5_STATIC_C_PLL_SDORDER(x) (((x) >> S_T5_STATIC_C_PLL_SDORDER) & M_T5_STATIC_C_PLL_SDORDER)
12950 
12951 #define S_T5_STATIC_C_PLL_FFENABLE    20
12952 #define V_T5_STATIC_C_PLL_FFENABLE(x) ((x) << S_T5_STATIC_C_PLL_FFENABLE)
12953 #define F_T5_STATIC_C_PLL_FFENABLE    V_T5_STATIC_C_PLL_FFENABLE(1U)
12954 
12955 #define S_T5_STATIC_C_PLL_STOPCLKB    19
12956 #define V_T5_STATIC_C_PLL_STOPCLKB(x) ((x) << S_T5_STATIC_C_PLL_STOPCLKB)
12957 #define F_T5_STATIC_C_PLL_STOPCLKB    V_T5_STATIC_C_PLL_STOPCLKB(1U)
12958 
12959 #define S_T5_STATIC_C_PLL_STOPCLKA    18
12960 #define V_T5_STATIC_C_PLL_STOPCLKA(x) ((x) << S_T5_STATIC_C_PLL_STOPCLKA)
12961 #define F_T5_STATIC_C_PLL_STOPCLKA    V_T5_STATIC_C_PLL_STOPCLKA(1U)
12962 
12963 #define S_T5_STATIC_C_PLL_SLEEP    17
12964 #define V_T5_STATIC_C_PLL_SLEEP(x) ((x) << S_T5_STATIC_C_PLL_SLEEP)
12965 #define F_T5_STATIC_C_PLL_SLEEP    V_T5_STATIC_C_PLL_SLEEP(1U)
12966 
12967 #define S_T5_STATIC_C_PLL_BYPASS    16
12968 #define V_T5_STATIC_C_PLL_BYPASS(x) ((x) << S_T5_STATIC_C_PLL_BYPASS)
12969 #define F_T5_STATIC_C_PLL_BYPASS    V_T5_STATIC_C_PLL_BYPASS(1U)
12970 
12971 #define S_T5_STATIC_C_PLL_LOCKTUNE    0
12972 #define M_T5_STATIC_C_PLL_LOCKTUNE    0xffffU
12973 #define V_T5_STATIC_C_PLL_LOCKTUNE(x) ((x) << S_T5_STATIC_C_PLL_LOCKTUNE)
12974 #define G_T5_STATIC_C_PLL_LOCKTUNE(x) (((x) >> S_T5_STATIC_C_PLL_LOCKTUNE) & M_T5_STATIC_C_PLL_LOCKTUNE)
12975 
12976 #define A_DBG_STATIC_C_PLL_CONF2 0x60d4
12977 
12978 #define S_T6_STATIC_C_PLL_PREDIV    26
12979 #define M_T6_STATIC_C_PLL_PREDIV    0x3fU
12980 #define V_T6_STATIC_C_PLL_PREDIV(x) ((x) << S_T6_STATIC_C_PLL_PREDIV)
12981 #define G_T6_STATIC_C_PLL_PREDIV(x) (((x) >> S_T6_STATIC_C_PLL_PREDIV) & M_T6_STATIC_C_PLL_PREDIV)
12982 
12983 #define S_STATIC_C_PLL_STARTUP    24
12984 #define M_STATIC_C_PLL_STARTUP    0x3U
12985 #define V_STATIC_C_PLL_STARTUP(x) ((x) << S_STATIC_C_PLL_STARTUP)
12986 #define G_STATIC_C_PLL_STARTUP(x) (((x) >> S_STATIC_C_PLL_STARTUP) & M_STATIC_C_PLL_STARTUP)
12987 
12988 #define S_STATIC_C_PLL_DCO_BYPASS    23
12989 #define V_STATIC_C_PLL_DCO_BYPASS(x) ((x) << S_STATIC_C_PLL_DCO_BYPASS)
12990 #define F_STATIC_C_PLL_DCO_BYPASS    V_STATIC_C_PLL_DCO_BYPASS(1U)
12991 
12992 #define S_STATIC_C_PLL_SDORDER    21
12993 #define M_STATIC_C_PLL_SDORDER    0x3U
12994 #define V_STATIC_C_PLL_SDORDER(x) ((x) << S_STATIC_C_PLL_SDORDER)
12995 #define G_STATIC_C_PLL_SDORDER(x) (((x) >> S_STATIC_C_PLL_SDORDER) & M_STATIC_C_PLL_SDORDER)
12996 
12997 #define S_STATIC_C_PLL_DIVCHANGE    20
12998 #define V_STATIC_C_PLL_DIVCHANGE(x) ((x) << S_STATIC_C_PLL_DIVCHANGE)
12999 #define F_STATIC_C_PLL_DIVCHANGE    V_STATIC_C_PLL_DIVCHANGE(1U)
13000 
13001 #define S_STATIC_C_PLL_STOPCLKB    19
13002 #define V_STATIC_C_PLL_STOPCLKB(x) ((x) << S_STATIC_C_PLL_STOPCLKB)
13003 #define F_STATIC_C_PLL_STOPCLKB    V_STATIC_C_PLL_STOPCLKB(1U)
13004 
13005 #define S_STATIC_C_PLL_STOPCLKA    18
13006 #define V_STATIC_C_PLL_STOPCLKA(x) ((x) << S_STATIC_C_PLL_STOPCLKA)
13007 #define F_STATIC_C_PLL_STOPCLKA    V_STATIC_C_PLL_STOPCLKA(1U)
13008 
13009 #define S_T6_STATIC_C_PLL_SLEEP    17
13010 #define V_T6_STATIC_C_PLL_SLEEP(x) ((x) << S_T6_STATIC_C_PLL_SLEEP)
13011 #define F_T6_STATIC_C_PLL_SLEEP    V_T6_STATIC_C_PLL_SLEEP(1U)
13012 
13013 #define S_T6_STATIC_C_PLL_BYPASS    16
13014 #define V_T6_STATIC_C_PLL_BYPASS(x) ((x) << S_T6_STATIC_C_PLL_BYPASS)
13015 #define F_T6_STATIC_C_PLL_BYPASS    V_T6_STATIC_C_PLL_BYPASS(1U)
13016 
13017 #define S_STATIC_C_PLL_LOCKTUNE    0
13018 #define M_STATIC_C_PLL_LOCKTUNE    0x1fU
13019 #define V_STATIC_C_PLL_LOCKTUNE(x) ((x) << S_STATIC_C_PLL_LOCKTUNE)
13020 #define G_STATIC_C_PLL_LOCKTUNE(x) (((x) >> S_STATIC_C_PLL_LOCKTUNE) & M_STATIC_C_PLL_LOCKTUNE)
13021 
13022 #define A_DBG_T5_STATIC_C_PLL_CONF3 0x60d8
13023 
13024 #define S_T5_STATIC_C_PLL_MULTPRE    30
13025 #define M_T5_STATIC_C_PLL_MULTPRE    0x3U
13026 #define V_T5_STATIC_C_PLL_MULTPRE(x) ((x) << S_T5_STATIC_C_PLL_MULTPRE)
13027 #define G_T5_STATIC_C_PLL_MULTPRE(x) (((x) >> S_T5_STATIC_C_PLL_MULTPRE) & M_T5_STATIC_C_PLL_MULTPRE)
13028 
13029 #define S_T5_STATIC_C_PLL_LOCKSEL    28
13030 #define M_T5_STATIC_C_PLL_LOCKSEL    0x3U
13031 #define V_T5_STATIC_C_PLL_LOCKSEL(x) ((x) << S_T5_STATIC_C_PLL_LOCKSEL)
13032 #define G_T5_STATIC_C_PLL_LOCKSEL(x) (((x) >> S_T5_STATIC_C_PLL_LOCKSEL) & M_T5_STATIC_C_PLL_LOCKSEL)
13033 
13034 #define S_T5_STATIC_C_PLL_FFTUNE    12
13035 #define M_T5_STATIC_C_PLL_FFTUNE    0xffffU
13036 #define V_T5_STATIC_C_PLL_FFTUNE(x) ((x) << S_T5_STATIC_C_PLL_FFTUNE)
13037 #define G_T5_STATIC_C_PLL_FFTUNE(x) (((x) >> S_T5_STATIC_C_PLL_FFTUNE) & M_T5_STATIC_C_PLL_FFTUNE)
13038 
13039 #define S_T5_STATIC_C_PLL_RANGEPRE    10
13040 #define M_T5_STATIC_C_PLL_RANGEPRE    0x3U
13041 #define V_T5_STATIC_C_PLL_RANGEPRE(x) ((x) << S_T5_STATIC_C_PLL_RANGEPRE)
13042 #define G_T5_STATIC_C_PLL_RANGEPRE(x) (((x) >> S_T5_STATIC_C_PLL_RANGEPRE) & M_T5_STATIC_C_PLL_RANGEPRE)
13043 
13044 #define S_T5_STATIC_C_PLL_RANGEB    5
13045 #define M_T5_STATIC_C_PLL_RANGEB    0x1fU
13046 #define V_T5_STATIC_C_PLL_RANGEB(x) ((x) << S_T5_STATIC_C_PLL_RANGEB)
13047 #define G_T5_STATIC_C_PLL_RANGEB(x) (((x) >> S_T5_STATIC_C_PLL_RANGEB) & M_T5_STATIC_C_PLL_RANGEB)
13048 
13049 #define S_T5_STATIC_C_PLL_RANGEA    0
13050 #define M_T5_STATIC_C_PLL_RANGEA    0x1fU
13051 #define V_T5_STATIC_C_PLL_RANGEA(x) ((x) << S_T5_STATIC_C_PLL_RANGEA)
13052 #define G_T5_STATIC_C_PLL_RANGEA(x) (((x) >> S_T5_STATIC_C_PLL_RANGEA) & M_T5_STATIC_C_PLL_RANGEA)
13053 
13054 #define A_DBG_STATIC_C_PLL_CONF3 0x60d8
13055 
13056 #define S_STATIC_C_PLL_MULTPRE    30
13057 #define M_STATIC_C_PLL_MULTPRE    0x3U
13058 #define V_STATIC_C_PLL_MULTPRE(x) ((x) << S_STATIC_C_PLL_MULTPRE)
13059 #define G_STATIC_C_PLL_MULTPRE(x) (((x) >> S_STATIC_C_PLL_MULTPRE) & M_STATIC_C_PLL_MULTPRE)
13060 
13061 #define S_STATIC_C_PLL_LOCKSEL    28
13062 #define V_STATIC_C_PLL_LOCKSEL(x) ((x) << S_STATIC_C_PLL_LOCKSEL)
13063 #define F_STATIC_C_PLL_LOCKSEL    V_STATIC_C_PLL_LOCKSEL(1U)
13064 
13065 #define S_STATIC_C_PLL_FFTUNE    12
13066 #define M_STATIC_C_PLL_FFTUNE    0xffffU
13067 #define V_STATIC_C_PLL_FFTUNE(x) ((x) << S_STATIC_C_PLL_FFTUNE)
13068 #define G_STATIC_C_PLL_FFTUNE(x) (((x) >> S_STATIC_C_PLL_FFTUNE) & M_STATIC_C_PLL_FFTUNE)
13069 
13070 #define S_STATIC_C_PLL_RANGEPRE    10
13071 #define M_STATIC_C_PLL_RANGEPRE    0x3U
13072 #define V_STATIC_C_PLL_RANGEPRE(x) ((x) << S_STATIC_C_PLL_RANGEPRE)
13073 #define G_STATIC_C_PLL_RANGEPRE(x) (((x) >> S_STATIC_C_PLL_RANGEPRE) & M_STATIC_C_PLL_RANGEPRE)
13074 
13075 #define S_T6_STATIC_C_PLL_RANGEB    5
13076 #define M_T6_STATIC_C_PLL_RANGEB    0x1fU
13077 #define V_T6_STATIC_C_PLL_RANGEB(x) ((x) << S_T6_STATIC_C_PLL_RANGEB)
13078 #define G_T6_STATIC_C_PLL_RANGEB(x) (((x) >> S_T6_STATIC_C_PLL_RANGEB) & M_T6_STATIC_C_PLL_RANGEB)
13079 
13080 #define S_T6_STATIC_C_PLL_RANGEA    0
13081 #define M_T6_STATIC_C_PLL_RANGEA    0x1fU
13082 #define V_T6_STATIC_C_PLL_RANGEA(x) ((x) << S_T6_STATIC_C_PLL_RANGEA)
13083 #define G_T6_STATIC_C_PLL_RANGEA(x) (((x) >> S_T6_STATIC_C_PLL_RANGEA) & M_T6_STATIC_C_PLL_RANGEA)
13084 
13085 #define A_DBG_T5_STATIC_C_PLL_CONF4 0x60dc
13086 #define A_DBG_STATIC_C_PLL_CONF4 0x60dc
13087 #define A_DBG_T5_STATIC_C_PLL_CONF5 0x60e0
13088 
13089 #define S_T5_STATIC_C_PLL_VCVTUNE    22
13090 #define M_T5_STATIC_C_PLL_VCVTUNE    0x7U
13091 #define V_T5_STATIC_C_PLL_VCVTUNE(x) ((x) << S_T5_STATIC_C_PLL_VCVTUNE)
13092 #define G_T5_STATIC_C_PLL_VCVTUNE(x) (((x) >> S_T5_STATIC_C_PLL_VCVTUNE) & M_T5_STATIC_C_PLL_VCVTUNE)
13093 
13094 #define S_T5_STATIC_C_PLL_LFTUNE_32_40    13
13095 #define M_T5_STATIC_C_PLL_LFTUNE_32_40    0x1ffU
13096 #define V_T5_STATIC_C_PLL_LFTUNE_32_40(x) ((x) << S_T5_STATIC_C_PLL_LFTUNE_32_40)
13097 #define G_T5_STATIC_C_PLL_LFTUNE_32_40(x) (((x) >> S_T5_STATIC_C_PLL_LFTUNE_32_40) & M_T5_STATIC_C_PLL_LFTUNE_32_40)
13098 
13099 #define S_T5_STATIC_C_PLL_PREDIV    8
13100 #define M_T5_STATIC_C_PLL_PREDIV    0x1fU
13101 #define V_T5_STATIC_C_PLL_PREDIV(x) ((x) << S_T5_STATIC_C_PLL_PREDIV)
13102 #define G_T5_STATIC_C_PLL_PREDIV(x) (((x) >> S_T5_STATIC_C_PLL_PREDIV) & M_T5_STATIC_C_PLL_PREDIV)
13103 
13104 #define S_T5_STATIC_C_PLL_MULT    0
13105 #define M_T5_STATIC_C_PLL_MULT    0xffU
13106 #define V_T5_STATIC_C_PLL_MULT(x) ((x) << S_T5_STATIC_C_PLL_MULT)
13107 #define G_T5_STATIC_C_PLL_MULT(x) (((x) >> S_T5_STATIC_C_PLL_MULT) & M_T5_STATIC_C_PLL_MULT)
13108 
13109 #define A_DBG_STATIC_C_PLL_CONF5 0x60e0
13110 
13111 #define S_STATIC_C_PLL_FFBYPASS    27
13112 #define V_STATIC_C_PLL_FFBYPASS(x) ((x) << S_STATIC_C_PLL_FFBYPASS)
13113 #define F_STATIC_C_PLL_FFBYPASS    V_STATIC_C_PLL_FFBYPASS(1U)
13114 
13115 #define S_STATIC_C_PLL_FASTSTOP    26
13116 #define V_STATIC_C_PLL_FASTSTOP(x) ((x) << S_STATIC_C_PLL_FASTSTOP)
13117 #define F_STATIC_C_PLL_FASTSTOP    V_STATIC_C_PLL_FASTSTOP(1U)
13118 
13119 #define S_STATIC_C_PLL_FRAMESTOP    25
13120 #define V_STATIC_C_PLL_FRAMESTOP(x) ((x) << S_STATIC_C_PLL_FRAMESTOP)
13121 #define F_STATIC_C_PLL_FRAMESTOP    V_STATIC_C_PLL_FRAMESTOP(1U)
13122 
13123 #define S_STATIC_C_PLL_VCVTUNE    22
13124 #define M_STATIC_C_PLL_VCVTUNE    0x7U
13125 #define V_STATIC_C_PLL_VCVTUNE(x) ((x) << S_STATIC_C_PLL_VCVTUNE)
13126 #define G_STATIC_C_PLL_VCVTUNE(x) (((x) >> S_STATIC_C_PLL_VCVTUNE) & M_STATIC_C_PLL_VCVTUNE)
13127 
13128 #define S_STATIC_C_PLL_LFTUNE_32_40    13
13129 #define M_STATIC_C_PLL_LFTUNE_32_40    0x1ffU
13130 #define V_STATIC_C_PLL_LFTUNE_32_40(x) ((x) << S_STATIC_C_PLL_LFTUNE_32_40)
13131 #define G_STATIC_C_PLL_LFTUNE_32_40(x) (((x) >> S_STATIC_C_PLL_LFTUNE_32_40) & M_STATIC_C_PLL_LFTUNE_32_40)
13132 
13133 #define S_STATIC_C_PLL_PREDIV_CNF5    8
13134 #define M_STATIC_C_PLL_PREDIV_CNF5    0x1fU
13135 #define V_STATIC_C_PLL_PREDIV_CNF5(x) ((x) << S_STATIC_C_PLL_PREDIV_CNF5)
13136 #define G_STATIC_C_PLL_PREDIV_CNF5(x) (((x) >> S_STATIC_C_PLL_PREDIV_CNF5) & M_STATIC_C_PLL_PREDIV_CNF5)
13137 
13138 #define S_T6_STATIC_C_PLL_MULT    0
13139 #define M_T6_STATIC_C_PLL_MULT    0xffU
13140 #define V_T6_STATIC_C_PLL_MULT(x) ((x) << S_T6_STATIC_C_PLL_MULT)
13141 #define G_T6_STATIC_C_PLL_MULT(x) (((x) >> S_T6_STATIC_C_PLL_MULT) & M_T6_STATIC_C_PLL_MULT)
13142 
13143 #define A_DBG_T5_STATIC_U_PLL_CONF1 0x60e4
13144 
13145 #define S_T5_STATIC_U_PLL_MULTFRAC    8
13146 #define M_T5_STATIC_U_PLL_MULTFRAC    0xffffffU
13147 #define V_T5_STATIC_U_PLL_MULTFRAC(x) ((x) << S_T5_STATIC_U_PLL_MULTFRAC)
13148 #define G_T5_STATIC_U_PLL_MULTFRAC(x) (((x) >> S_T5_STATIC_U_PLL_MULTFRAC) & M_T5_STATIC_U_PLL_MULTFRAC)
13149 
13150 #define S_T5_STATIC_U_PLL_FFSLEWRATE    0
13151 #define M_T5_STATIC_U_PLL_FFSLEWRATE    0xffU
13152 #define V_T5_STATIC_U_PLL_FFSLEWRATE(x) ((x) << S_T5_STATIC_U_PLL_FFSLEWRATE)
13153 #define G_T5_STATIC_U_PLL_FFSLEWRATE(x) (((x) >> S_T5_STATIC_U_PLL_FFSLEWRATE) & M_T5_STATIC_U_PLL_FFSLEWRATE)
13154 
13155 #define A_DBG_STATIC_U_PLL_CONF1 0x60e4
13156 
13157 #define S_STATIC_U_PLL_MULTFRAC    8
13158 #define M_STATIC_U_PLL_MULTFRAC    0xffffffU
13159 #define V_STATIC_U_PLL_MULTFRAC(x) ((x) << S_STATIC_U_PLL_MULTFRAC)
13160 #define G_STATIC_U_PLL_MULTFRAC(x) (((x) >> S_STATIC_U_PLL_MULTFRAC) & M_STATIC_U_PLL_MULTFRAC)
13161 
13162 #define S_STATIC_U_PLL_FFSLEWRATE    0
13163 #define M_STATIC_U_PLL_FFSLEWRATE    0xffU
13164 #define V_STATIC_U_PLL_FFSLEWRATE(x) ((x) << S_STATIC_U_PLL_FFSLEWRATE)
13165 #define G_STATIC_U_PLL_FFSLEWRATE(x) (((x) >> S_STATIC_U_PLL_FFSLEWRATE) & M_STATIC_U_PLL_FFSLEWRATE)
13166 
13167 #define A_DBG_T5_STATIC_U_PLL_CONF2 0x60e8
13168 
13169 #define S_T5_STATIC_U_PLL_DCO_BYPASS    23
13170 #define V_T5_STATIC_U_PLL_DCO_BYPASS(x) ((x) << S_T5_STATIC_U_PLL_DCO_BYPASS)
13171 #define F_T5_STATIC_U_PLL_DCO_BYPASS    V_T5_STATIC_U_PLL_DCO_BYPASS(1U)
13172 
13173 #define S_T5_STATIC_U_PLL_SDORDER    21
13174 #define M_T5_STATIC_U_PLL_SDORDER    0x3U
13175 #define V_T5_STATIC_U_PLL_SDORDER(x) ((x) << S_T5_STATIC_U_PLL_SDORDER)
13176 #define G_T5_STATIC_U_PLL_SDORDER(x) (((x) >> S_T5_STATIC_U_PLL_SDORDER) & M_T5_STATIC_U_PLL_SDORDER)
13177 
13178 #define S_T5_STATIC_U_PLL_FFENABLE    20
13179 #define V_T5_STATIC_U_PLL_FFENABLE(x) ((x) << S_T5_STATIC_U_PLL_FFENABLE)
13180 #define F_T5_STATIC_U_PLL_FFENABLE    V_T5_STATIC_U_PLL_FFENABLE(1U)
13181 
13182 #define S_T5_STATIC_U_PLL_STOPCLKB    19
13183 #define V_T5_STATIC_U_PLL_STOPCLKB(x) ((x) << S_T5_STATIC_U_PLL_STOPCLKB)
13184 #define F_T5_STATIC_U_PLL_STOPCLKB    V_T5_STATIC_U_PLL_STOPCLKB(1U)
13185 
13186 #define S_T5_STATIC_U_PLL_STOPCLKA    18
13187 #define V_T5_STATIC_U_PLL_STOPCLKA(x) ((x) << S_T5_STATIC_U_PLL_STOPCLKA)
13188 #define F_T5_STATIC_U_PLL_STOPCLKA    V_T5_STATIC_U_PLL_STOPCLKA(1U)
13189 
13190 #define S_T5_STATIC_U_PLL_SLEEP    17
13191 #define V_T5_STATIC_U_PLL_SLEEP(x) ((x) << S_T5_STATIC_U_PLL_SLEEP)
13192 #define F_T5_STATIC_U_PLL_SLEEP    V_T5_STATIC_U_PLL_SLEEP(1U)
13193 
13194 #define S_T5_STATIC_U_PLL_BYPASS    16
13195 #define V_T5_STATIC_U_PLL_BYPASS(x) ((x) << S_T5_STATIC_U_PLL_BYPASS)
13196 #define F_T5_STATIC_U_PLL_BYPASS    V_T5_STATIC_U_PLL_BYPASS(1U)
13197 
13198 #define S_T5_STATIC_U_PLL_LOCKTUNE    0
13199 #define M_T5_STATIC_U_PLL_LOCKTUNE    0xffffU
13200 #define V_T5_STATIC_U_PLL_LOCKTUNE(x) ((x) << S_T5_STATIC_U_PLL_LOCKTUNE)
13201 #define G_T5_STATIC_U_PLL_LOCKTUNE(x) (((x) >> S_T5_STATIC_U_PLL_LOCKTUNE) & M_T5_STATIC_U_PLL_LOCKTUNE)
13202 
13203 #define A_DBG_STATIC_U_PLL_CONF2 0x60e8
13204 
13205 #define S_T6_STATIC_U_PLL_PREDIV    26
13206 #define M_T6_STATIC_U_PLL_PREDIV    0x3fU
13207 #define V_T6_STATIC_U_PLL_PREDIV(x) ((x) << S_T6_STATIC_U_PLL_PREDIV)
13208 #define G_T6_STATIC_U_PLL_PREDIV(x) (((x) >> S_T6_STATIC_U_PLL_PREDIV) & M_T6_STATIC_U_PLL_PREDIV)
13209 
13210 #define S_STATIC_U_PLL_STARTUP    24
13211 #define M_STATIC_U_PLL_STARTUP    0x3U
13212 #define V_STATIC_U_PLL_STARTUP(x) ((x) << S_STATIC_U_PLL_STARTUP)
13213 #define G_STATIC_U_PLL_STARTUP(x) (((x) >> S_STATIC_U_PLL_STARTUP) & M_STATIC_U_PLL_STARTUP)
13214 
13215 #define S_STATIC_U_PLL_DCO_BYPASS    23
13216 #define V_STATIC_U_PLL_DCO_BYPASS(x) ((x) << S_STATIC_U_PLL_DCO_BYPASS)
13217 #define F_STATIC_U_PLL_DCO_BYPASS    V_STATIC_U_PLL_DCO_BYPASS(1U)
13218 
13219 #define S_STATIC_U_PLL_SDORDER    21
13220 #define M_STATIC_U_PLL_SDORDER    0x3U
13221 #define V_STATIC_U_PLL_SDORDER(x) ((x) << S_STATIC_U_PLL_SDORDER)
13222 #define G_STATIC_U_PLL_SDORDER(x) (((x) >> S_STATIC_U_PLL_SDORDER) & M_STATIC_U_PLL_SDORDER)
13223 
13224 #define S_STATIC_U_PLL_DIVCHANGE    20
13225 #define V_STATIC_U_PLL_DIVCHANGE(x) ((x) << S_STATIC_U_PLL_DIVCHANGE)
13226 #define F_STATIC_U_PLL_DIVCHANGE    V_STATIC_U_PLL_DIVCHANGE(1U)
13227 
13228 #define S_STATIC_U_PLL_STOPCLKB    19
13229 #define V_STATIC_U_PLL_STOPCLKB(x) ((x) << S_STATIC_U_PLL_STOPCLKB)
13230 #define F_STATIC_U_PLL_STOPCLKB    V_STATIC_U_PLL_STOPCLKB(1U)
13231 
13232 #define S_STATIC_U_PLL_STOPCLKA    18
13233 #define V_STATIC_U_PLL_STOPCLKA(x) ((x) << S_STATIC_U_PLL_STOPCLKA)
13234 #define F_STATIC_U_PLL_STOPCLKA    V_STATIC_U_PLL_STOPCLKA(1U)
13235 
13236 #define S_T6_STATIC_U_PLL_SLEEP    17
13237 #define V_T6_STATIC_U_PLL_SLEEP(x) ((x) << S_T6_STATIC_U_PLL_SLEEP)
13238 #define F_T6_STATIC_U_PLL_SLEEP    V_T6_STATIC_U_PLL_SLEEP(1U)
13239 
13240 #define S_T6_STATIC_U_PLL_BYPASS    16
13241 #define V_T6_STATIC_U_PLL_BYPASS(x) ((x) << S_T6_STATIC_U_PLL_BYPASS)
13242 #define F_T6_STATIC_U_PLL_BYPASS    V_T6_STATIC_U_PLL_BYPASS(1U)
13243 
13244 #define S_STATIC_U_PLL_LOCKTUNE    0
13245 #define M_STATIC_U_PLL_LOCKTUNE    0x1fU
13246 #define V_STATIC_U_PLL_LOCKTUNE(x) ((x) << S_STATIC_U_PLL_LOCKTUNE)
13247 #define G_STATIC_U_PLL_LOCKTUNE(x) (((x) >> S_STATIC_U_PLL_LOCKTUNE) & M_STATIC_U_PLL_LOCKTUNE)
13248 
13249 #define A_DBG_T5_STATIC_U_PLL_CONF3 0x60ec
13250 
13251 #define S_T5_STATIC_U_PLL_MULTPRE    30
13252 #define M_T5_STATIC_U_PLL_MULTPRE    0x3U
13253 #define V_T5_STATIC_U_PLL_MULTPRE(x) ((x) << S_T5_STATIC_U_PLL_MULTPRE)
13254 #define G_T5_STATIC_U_PLL_MULTPRE(x) (((x) >> S_T5_STATIC_U_PLL_MULTPRE) & M_T5_STATIC_U_PLL_MULTPRE)
13255 
13256 #define S_T5_STATIC_U_PLL_LOCKSEL    28
13257 #define M_T5_STATIC_U_PLL_LOCKSEL    0x3U
13258 #define V_T5_STATIC_U_PLL_LOCKSEL(x) ((x) << S_T5_STATIC_U_PLL_LOCKSEL)
13259 #define G_T5_STATIC_U_PLL_LOCKSEL(x) (((x) >> S_T5_STATIC_U_PLL_LOCKSEL) & M_T5_STATIC_U_PLL_LOCKSEL)
13260 
13261 #define S_T5_STATIC_U_PLL_FFTUNE    12
13262 #define M_T5_STATIC_U_PLL_FFTUNE    0xffffU
13263 #define V_T5_STATIC_U_PLL_FFTUNE(x) ((x) << S_T5_STATIC_U_PLL_FFTUNE)
13264 #define G_T5_STATIC_U_PLL_FFTUNE(x) (((x) >> S_T5_STATIC_U_PLL_FFTUNE) & M_T5_STATIC_U_PLL_FFTUNE)
13265 
13266 #define S_T5_STATIC_U_PLL_RANGEPRE    10
13267 #define M_T5_STATIC_U_PLL_RANGEPRE    0x3U
13268 #define V_T5_STATIC_U_PLL_RANGEPRE(x) ((x) << S_T5_STATIC_U_PLL_RANGEPRE)
13269 #define G_T5_STATIC_U_PLL_RANGEPRE(x) (((x) >> S_T5_STATIC_U_PLL_RANGEPRE) & M_T5_STATIC_U_PLL_RANGEPRE)
13270 
13271 #define S_T5_STATIC_U_PLL_RANGEB    5
13272 #define M_T5_STATIC_U_PLL_RANGEB    0x1fU
13273 #define V_T5_STATIC_U_PLL_RANGEB(x) ((x) << S_T5_STATIC_U_PLL_RANGEB)
13274 #define G_T5_STATIC_U_PLL_RANGEB(x) (((x) >> S_T5_STATIC_U_PLL_RANGEB) & M_T5_STATIC_U_PLL_RANGEB)
13275 
13276 #define S_T5_STATIC_U_PLL_RANGEA    0
13277 #define M_T5_STATIC_U_PLL_RANGEA    0x1fU
13278 #define V_T5_STATIC_U_PLL_RANGEA(x) ((x) << S_T5_STATIC_U_PLL_RANGEA)
13279 #define G_T5_STATIC_U_PLL_RANGEA(x) (((x) >> S_T5_STATIC_U_PLL_RANGEA) & M_T5_STATIC_U_PLL_RANGEA)
13280 
13281 #define A_DBG_STATIC_U_PLL_CONF3 0x60ec
13282 
13283 #define S_STATIC_U_PLL_MULTPRE    30
13284 #define M_STATIC_U_PLL_MULTPRE    0x3U
13285 #define V_STATIC_U_PLL_MULTPRE(x) ((x) << S_STATIC_U_PLL_MULTPRE)
13286 #define G_STATIC_U_PLL_MULTPRE(x) (((x) >> S_STATIC_U_PLL_MULTPRE) & M_STATIC_U_PLL_MULTPRE)
13287 
13288 #define S_STATIC_U_PLL_LOCKSEL    28
13289 #define V_STATIC_U_PLL_LOCKSEL(x) ((x) << S_STATIC_U_PLL_LOCKSEL)
13290 #define F_STATIC_U_PLL_LOCKSEL    V_STATIC_U_PLL_LOCKSEL(1U)
13291 
13292 #define S_STATIC_U_PLL_FFTUNE    12
13293 #define M_STATIC_U_PLL_FFTUNE    0xffffU
13294 #define V_STATIC_U_PLL_FFTUNE(x) ((x) << S_STATIC_U_PLL_FFTUNE)
13295 #define G_STATIC_U_PLL_FFTUNE(x) (((x) >> S_STATIC_U_PLL_FFTUNE) & M_STATIC_U_PLL_FFTUNE)
13296 
13297 #define S_STATIC_U_PLL_RANGEPRE    10
13298 #define M_STATIC_U_PLL_RANGEPRE    0x3U
13299 #define V_STATIC_U_PLL_RANGEPRE(x) ((x) << S_STATIC_U_PLL_RANGEPRE)
13300 #define G_STATIC_U_PLL_RANGEPRE(x) (((x) >> S_STATIC_U_PLL_RANGEPRE) & M_STATIC_U_PLL_RANGEPRE)
13301 
13302 #define S_T6_STATIC_U_PLL_RANGEB    5
13303 #define M_T6_STATIC_U_PLL_RANGEB    0x1fU
13304 #define V_T6_STATIC_U_PLL_RANGEB(x) ((x) << S_T6_STATIC_U_PLL_RANGEB)
13305 #define G_T6_STATIC_U_PLL_RANGEB(x) (((x) >> S_T6_STATIC_U_PLL_RANGEB) & M_T6_STATIC_U_PLL_RANGEB)
13306 
13307 #define S_T6_STATIC_U_PLL_RANGEA    0
13308 #define M_T6_STATIC_U_PLL_RANGEA    0x1fU
13309 #define V_T6_STATIC_U_PLL_RANGEA(x) ((x) << S_T6_STATIC_U_PLL_RANGEA)
13310 #define G_T6_STATIC_U_PLL_RANGEA(x) (((x) >> S_T6_STATIC_U_PLL_RANGEA) & M_T6_STATIC_U_PLL_RANGEA)
13311 
13312 #define A_DBG_T5_STATIC_U_PLL_CONF4 0x60f0
13313 #define A_DBG_STATIC_U_PLL_CONF4 0x60f0
13314 #define A_DBG_T5_STATIC_U_PLL_CONF5 0x60f4
13315 
13316 #define S_T5_STATIC_U_PLL_VCVTUNE    22
13317 #define M_T5_STATIC_U_PLL_VCVTUNE    0x7U
13318 #define V_T5_STATIC_U_PLL_VCVTUNE(x) ((x) << S_T5_STATIC_U_PLL_VCVTUNE)
13319 #define G_T5_STATIC_U_PLL_VCVTUNE(x) (((x) >> S_T5_STATIC_U_PLL_VCVTUNE) & M_T5_STATIC_U_PLL_VCVTUNE)
13320 
13321 #define S_T5_STATIC_U_PLL_LFTUNE_32_40    13
13322 #define M_T5_STATIC_U_PLL_LFTUNE_32_40    0x1ffU
13323 #define V_T5_STATIC_U_PLL_LFTUNE_32_40(x) ((x) << S_T5_STATIC_U_PLL_LFTUNE_32_40)
13324 #define G_T5_STATIC_U_PLL_LFTUNE_32_40(x) (((x) >> S_T5_STATIC_U_PLL_LFTUNE_32_40) & M_T5_STATIC_U_PLL_LFTUNE_32_40)
13325 
13326 #define S_T5_STATIC_U_PLL_PREDIV    8
13327 #define M_T5_STATIC_U_PLL_PREDIV    0x1fU
13328 #define V_T5_STATIC_U_PLL_PREDIV(x) ((x) << S_T5_STATIC_U_PLL_PREDIV)
13329 #define G_T5_STATIC_U_PLL_PREDIV(x) (((x) >> S_T5_STATIC_U_PLL_PREDIV) & M_T5_STATIC_U_PLL_PREDIV)
13330 
13331 #define S_T5_STATIC_U_PLL_MULT    0
13332 #define M_T5_STATIC_U_PLL_MULT    0xffU
13333 #define V_T5_STATIC_U_PLL_MULT(x) ((x) << S_T5_STATIC_U_PLL_MULT)
13334 #define G_T5_STATIC_U_PLL_MULT(x) (((x) >> S_T5_STATIC_U_PLL_MULT) & M_T5_STATIC_U_PLL_MULT)
13335 
13336 #define A_DBG_STATIC_U_PLL_CONF5 0x60f4
13337 
13338 #define S_STATIC_U_PLL_FFBYPASS    27
13339 #define V_STATIC_U_PLL_FFBYPASS(x) ((x) << S_STATIC_U_PLL_FFBYPASS)
13340 #define F_STATIC_U_PLL_FFBYPASS    V_STATIC_U_PLL_FFBYPASS(1U)
13341 
13342 #define S_STATIC_U_PLL_FASTSTOP    26
13343 #define V_STATIC_U_PLL_FASTSTOP(x) ((x) << S_STATIC_U_PLL_FASTSTOP)
13344 #define F_STATIC_U_PLL_FASTSTOP    V_STATIC_U_PLL_FASTSTOP(1U)
13345 
13346 #define S_STATIC_U_PLL_FRAMESTOP    25
13347 #define V_STATIC_U_PLL_FRAMESTOP(x) ((x) << S_STATIC_U_PLL_FRAMESTOP)
13348 #define F_STATIC_U_PLL_FRAMESTOP    V_STATIC_U_PLL_FRAMESTOP(1U)
13349 
13350 #define S_STATIC_U_PLL_VCVTUNE    22
13351 #define M_STATIC_U_PLL_VCVTUNE    0x7U
13352 #define V_STATIC_U_PLL_VCVTUNE(x) ((x) << S_STATIC_U_PLL_VCVTUNE)
13353 #define G_STATIC_U_PLL_VCVTUNE(x) (((x) >> S_STATIC_U_PLL_VCVTUNE) & M_STATIC_U_PLL_VCVTUNE)
13354 
13355 #define S_STATIC_U_PLL_LFTUNE_32_40    13
13356 #define M_STATIC_U_PLL_LFTUNE_32_40    0x1ffU
13357 #define V_STATIC_U_PLL_LFTUNE_32_40(x) ((x) << S_STATIC_U_PLL_LFTUNE_32_40)
13358 #define G_STATIC_U_PLL_LFTUNE_32_40(x) (((x) >> S_STATIC_U_PLL_LFTUNE_32_40) & M_STATIC_U_PLL_LFTUNE_32_40)
13359 
13360 #define S_STATIC_U_PLL_PREDIV_CNF5    8
13361 #define M_STATIC_U_PLL_PREDIV_CNF5    0x1fU
13362 #define V_STATIC_U_PLL_PREDIV_CNF5(x) ((x) << S_STATIC_U_PLL_PREDIV_CNF5)
13363 #define G_STATIC_U_PLL_PREDIV_CNF5(x) (((x) >> S_STATIC_U_PLL_PREDIV_CNF5) & M_STATIC_U_PLL_PREDIV_CNF5)
13364 
13365 #define S_T6_STATIC_U_PLL_MULT    0
13366 #define M_T6_STATIC_U_PLL_MULT    0xffU
13367 #define V_T6_STATIC_U_PLL_MULT(x) ((x) << S_T6_STATIC_U_PLL_MULT)
13368 #define G_T6_STATIC_U_PLL_MULT(x) (((x) >> S_T6_STATIC_U_PLL_MULT) & M_T6_STATIC_U_PLL_MULT)
13369 
13370 #define A_DBG_T5_STATIC_KR_PLL_CONF1 0x60f8
13371 
13372 #define S_T5_STATIC_KR_PLL_BYPASS    30
13373 #define V_T5_STATIC_KR_PLL_BYPASS(x) ((x) << S_T5_STATIC_KR_PLL_BYPASS)
13374 #define F_T5_STATIC_KR_PLL_BYPASS    V_T5_STATIC_KR_PLL_BYPASS(1U)
13375 
13376 #define S_T5_STATIC_KR_PLL_VBOOSTDIV    27
13377 #define M_T5_STATIC_KR_PLL_VBOOSTDIV    0x7U
13378 #define V_T5_STATIC_KR_PLL_VBOOSTDIV(x) ((x) << S_T5_STATIC_KR_PLL_VBOOSTDIV)
13379 #define G_T5_STATIC_KR_PLL_VBOOSTDIV(x) (((x) >> S_T5_STATIC_KR_PLL_VBOOSTDIV) & M_T5_STATIC_KR_PLL_VBOOSTDIV)
13380 
13381 #define S_T5_STATIC_KR_PLL_CPISEL    24
13382 #define M_T5_STATIC_KR_PLL_CPISEL    0x7U
13383 #define V_T5_STATIC_KR_PLL_CPISEL(x) ((x) << S_T5_STATIC_KR_PLL_CPISEL)
13384 #define G_T5_STATIC_KR_PLL_CPISEL(x) (((x) >> S_T5_STATIC_KR_PLL_CPISEL) & M_T5_STATIC_KR_PLL_CPISEL)
13385 
13386 #define S_T5_STATIC_KR_PLL_CCALMETHOD    23
13387 #define V_T5_STATIC_KR_PLL_CCALMETHOD(x) ((x) << S_T5_STATIC_KR_PLL_CCALMETHOD)
13388 #define F_T5_STATIC_KR_PLL_CCALMETHOD    V_T5_STATIC_KR_PLL_CCALMETHOD(1U)
13389 
13390 #define S_T5_STATIC_KR_PLL_CCALLOAD    22
13391 #define V_T5_STATIC_KR_PLL_CCALLOAD(x) ((x) << S_T5_STATIC_KR_PLL_CCALLOAD)
13392 #define F_T5_STATIC_KR_PLL_CCALLOAD    V_T5_STATIC_KR_PLL_CCALLOAD(1U)
13393 
13394 #define S_T5_STATIC_KR_PLL_CCALFMIN    21
13395 #define V_T5_STATIC_KR_PLL_CCALFMIN(x) ((x) << S_T5_STATIC_KR_PLL_CCALFMIN)
13396 #define F_T5_STATIC_KR_PLL_CCALFMIN    V_T5_STATIC_KR_PLL_CCALFMIN(1U)
13397 
13398 #define S_T5_STATIC_KR_PLL_CCALFMAX    20
13399 #define V_T5_STATIC_KR_PLL_CCALFMAX(x) ((x) << S_T5_STATIC_KR_PLL_CCALFMAX)
13400 #define F_T5_STATIC_KR_PLL_CCALFMAX    V_T5_STATIC_KR_PLL_CCALFMAX(1U)
13401 
13402 #define S_T5_STATIC_KR_PLL_CCALCVHOLD    19
13403 #define V_T5_STATIC_KR_PLL_CCALCVHOLD(x) ((x) << S_T5_STATIC_KR_PLL_CCALCVHOLD)
13404 #define F_T5_STATIC_KR_PLL_CCALCVHOLD    V_T5_STATIC_KR_PLL_CCALCVHOLD(1U)
13405 
13406 #define S_T5_STATIC_KR_PLL_CCALBANDSEL    15
13407 #define M_T5_STATIC_KR_PLL_CCALBANDSEL    0xfU
13408 #define V_T5_STATIC_KR_PLL_CCALBANDSEL(x) ((x) << S_T5_STATIC_KR_PLL_CCALBANDSEL)
13409 #define G_T5_STATIC_KR_PLL_CCALBANDSEL(x) (((x) >> S_T5_STATIC_KR_PLL_CCALBANDSEL) & M_T5_STATIC_KR_PLL_CCALBANDSEL)
13410 
13411 #define S_T5_STATIC_KR_PLL_BGOFFSET    11
13412 #define M_T5_STATIC_KR_PLL_BGOFFSET    0xfU
13413 #define V_T5_STATIC_KR_PLL_BGOFFSET(x) ((x) << S_T5_STATIC_KR_PLL_BGOFFSET)
13414 #define G_T5_STATIC_KR_PLL_BGOFFSET(x) (((x) >> S_T5_STATIC_KR_PLL_BGOFFSET) & M_T5_STATIC_KR_PLL_BGOFFSET)
13415 
13416 #define S_T5_STATIC_KR_PLL_P    8
13417 #define M_T5_STATIC_KR_PLL_P    0x7U
13418 #define V_T5_STATIC_KR_PLL_P(x) ((x) << S_T5_STATIC_KR_PLL_P)
13419 #define G_T5_STATIC_KR_PLL_P(x) (((x) >> S_T5_STATIC_KR_PLL_P) & M_T5_STATIC_KR_PLL_P)
13420 
13421 #define S_T5_STATIC_KR_PLL_N2    4
13422 #define M_T5_STATIC_KR_PLL_N2    0xfU
13423 #define V_T5_STATIC_KR_PLL_N2(x) ((x) << S_T5_STATIC_KR_PLL_N2)
13424 #define G_T5_STATIC_KR_PLL_N2(x) (((x) >> S_T5_STATIC_KR_PLL_N2) & M_T5_STATIC_KR_PLL_N2)
13425 
13426 #define S_T5_STATIC_KR_PLL_N1    0
13427 #define M_T5_STATIC_KR_PLL_N1    0xfU
13428 #define V_T5_STATIC_KR_PLL_N1(x) ((x) << S_T5_STATIC_KR_PLL_N1)
13429 #define G_T5_STATIC_KR_PLL_N1(x) (((x) >> S_T5_STATIC_KR_PLL_N1) & M_T5_STATIC_KR_PLL_N1)
13430 
13431 #define A_DBG_STATIC_KR_PLL_CONF1 0x60f8
13432 
13433 #define S_T6_STATIC_KR_PLL_BYPASS    30
13434 #define V_T6_STATIC_KR_PLL_BYPASS(x) ((x) << S_T6_STATIC_KR_PLL_BYPASS)
13435 #define F_T6_STATIC_KR_PLL_BYPASS    V_T6_STATIC_KR_PLL_BYPASS(1U)
13436 
13437 #define S_STATIC_KR_PLL_VBOOSTDIV    27
13438 #define M_STATIC_KR_PLL_VBOOSTDIV    0x7U
13439 #define V_STATIC_KR_PLL_VBOOSTDIV(x) ((x) << S_STATIC_KR_PLL_VBOOSTDIV)
13440 #define G_STATIC_KR_PLL_VBOOSTDIV(x) (((x) >> S_STATIC_KR_PLL_VBOOSTDIV) & M_STATIC_KR_PLL_VBOOSTDIV)
13441 
13442 #define S_STATIC_KR_PLL_CPISEL    24
13443 #define M_STATIC_KR_PLL_CPISEL    0x7U
13444 #define V_STATIC_KR_PLL_CPISEL(x) ((x) << S_STATIC_KR_PLL_CPISEL)
13445 #define G_STATIC_KR_PLL_CPISEL(x) (((x) >> S_STATIC_KR_PLL_CPISEL) & M_STATIC_KR_PLL_CPISEL)
13446 
13447 #define S_STATIC_KR_PLL_CCALMETHOD    23
13448 #define V_STATIC_KR_PLL_CCALMETHOD(x) ((x) << S_STATIC_KR_PLL_CCALMETHOD)
13449 #define F_STATIC_KR_PLL_CCALMETHOD    V_STATIC_KR_PLL_CCALMETHOD(1U)
13450 
13451 #define S_STATIC_KR_PLL_CCALLOAD    22
13452 #define V_STATIC_KR_PLL_CCALLOAD(x) ((x) << S_STATIC_KR_PLL_CCALLOAD)
13453 #define F_STATIC_KR_PLL_CCALLOAD    V_STATIC_KR_PLL_CCALLOAD(1U)
13454 
13455 #define S_STATIC_KR_PLL_CCALFMIN    21
13456 #define V_STATIC_KR_PLL_CCALFMIN(x) ((x) << S_STATIC_KR_PLL_CCALFMIN)
13457 #define F_STATIC_KR_PLL_CCALFMIN    V_STATIC_KR_PLL_CCALFMIN(1U)
13458 
13459 #define S_STATIC_KR_PLL_CCALFMAX    20
13460 #define V_STATIC_KR_PLL_CCALFMAX(x) ((x) << S_STATIC_KR_PLL_CCALFMAX)
13461 #define F_STATIC_KR_PLL_CCALFMAX    V_STATIC_KR_PLL_CCALFMAX(1U)
13462 
13463 #define S_STATIC_KR_PLL_CCALCVHOLD    19
13464 #define V_STATIC_KR_PLL_CCALCVHOLD(x) ((x) << S_STATIC_KR_PLL_CCALCVHOLD)
13465 #define F_STATIC_KR_PLL_CCALCVHOLD    V_STATIC_KR_PLL_CCALCVHOLD(1U)
13466 
13467 #define S_STATIC_KR_PLL_CCALBANDSEL    15
13468 #define M_STATIC_KR_PLL_CCALBANDSEL    0xfU
13469 #define V_STATIC_KR_PLL_CCALBANDSEL(x) ((x) << S_STATIC_KR_PLL_CCALBANDSEL)
13470 #define G_STATIC_KR_PLL_CCALBANDSEL(x) (((x) >> S_STATIC_KR_PLL_CCALBANDSEL) & M_STATIC_KR_PLL_CCALBANDSEL)
13471 
13472 #define S_STATIC_KR_PLL_BGOFFSET    11
13473 #define M_STATIC_KR_PLL_BGOFFSET    0xfU
13474 #define V_STATIC_KR_PLL_BGOFFSET(x) ((x) << S_STATIC_KR_PLL_BGOFFSET)
13475 #define G_STATIC_KR_PLL_BGOFFSET(x) (((x) >> S_STATIC_KR_PLL_BGOFFSET) & M_STATIC_KR_PLL_BGOFFSET)
13476 
13477 #define S_T6_STATIC_KR_PLL_P    8
13478 #define M_T6_STATIC_KR_PLL_P    0x7U
13479 #define V_T6_STATIC_KR_PLL_P(x) ((x) << S_T6_STATIC_KR_PLL_P)
13480 #define G_T6_STATIC_KR_PLL_P(x) (((x) >> S_T6_STATIC_KR_PLL_P) & M_T6_STATIC_KR_PLL_P)
13481 
13482 #define S_T6_STATIC_KR_PLL_N2    4
13483 #define M_T6_STATIC_KR_PLL_N2    0xfU
13484 #define V_T6_STATIC_KR_PLL_N2(x) ((x) << S_T6_STATIC_KR_PLL_N2)
13485 #define G_T6_STATIC_KR_PLL_N2(x) (((x) >> S_T6_STATIC_KR_PLL_N2) & M_T6_STATIC_KR_PLL_N2)
13486 
13487 #define S_T6_STATIC_KR_PLL_N1    0
13488 #define M_T6_STATIC_KR_PLL_N1    0xfU
13489 #define V_T6_STATIC_KR_PLL_N1(x) ((x) << S_T6_STATIC_KR_PLL_N1)
13490 #define G_T6_STATIC_KR_PLL_N1(x) (((x) >> S_T6_STATIC_KR_PLL_N1) & M_T6_STATIC_KR_PLL_N1)
13491 
13492 #define A_DBG_T5_STATIC_KR_PLL_CONF2 0x60fc
13493 
13494 #define S_T5_STATIC_KR_PLL_M    11
13495 #define M_T5_STATIC_KR_PLL_M    0x1ffU
13496 #define V_T5_STATIC_KR_PLL_M(x) ((x) << S_T5_STATIC_KR_PLL_M)
13497 #define G_T5_STATIC_KR_PLL_M(x) (((x) >> S_T5_STATIC_KR_PLL_M) & M_T5_STATIC_KR_PLL_M)
13498 
13499 #define S_T5_STATIC_KR_PLL_ANALOGTUNE    0
13500 #define M_T5_STATIC_KR_PLL_ANALOGTUNE    0x7ffU
13501 #define V_T5_STATIC_KR_PLL_ANALOGTUNE(x) ((x) << S_T5_STATIC_KR_PLL_ANALOGTUNE)
13502 #define G_T5_STATIC_KR_PLL_ANALOGTUNE(x) (((x) >> S_T5_STATIC_KR_PLL_ANALOGTUNE) & M_T5_STATIC_KR_PLL_ANALOGTUNE)
13503 
13504 #define A_DBG_STATIC_KR_PLL_CONF2 0x60fc
13505 
13506 #define S_T6_STATIC_KR_PLL_M    11
13507 #define M_T6_STATIC_KR_PLL_M    0x1ffU
13508 #define V_T6_STATIC_KR_PLL_M(x) ((x) << S_T6_STATIC_KR_PLL_M)
13509 #define G_T6_STATIC_KR_PLL_M(x) (((x) >> S_T6_STATIC_KR_PLL_M) & M_T6_STATIC_KR_PLL_M)
13510 
13511 #define S_STATIC_KR_PLL_ANALOGTUNE    0
13512 #define M_STATIC_KR_PLL_ANALOGTUNE    0x7ffU
13513 #define V_STATIC_KR_PLL_ANALOGTUNE(x) ((x) << S_STATIC_KR_PLL_ANALOGTUNE)
13514 #define G_STATIC_KR_PLL_ANALOGTUNE(x) (((x) >> S_STATIC_KR_PLL_ANALOGTUNE) & M_STATIC_KR_PLL_ANALOGTUNE)
13515 
13516 #define A_DBG_PVT_REG_CALIBRATE_CTL 0x6100
13517 
13518 #define S_HALT_CALIBRATE    1
13519 #define V_HALT_CALIBRATE(x) ((x) << S_HALT_CALIBRATE)
13520 #define F_HALT_CALIBRATE    V_HALT_CALIBRATE(1U)
13521 
13522 #define S_RESET_CALIBRATE    0
13523 #define V_RESET_CALIBRATE(x) ((x) << S_RESET_CALIBRATE)
13524 #define F_RESET_CALIBRATE    V_RESET_CALIBRATE(1U)
13525 
13526 #define A_DBG_GPIO_EN_NEW 0x6100
13527 
13528 #define S_GPIO16_OEN    7
13529 #define V_GPIO16_OEN(x) ((x) << S_GPIO16_OEN)
13530 #define F_GPIO16_OEN    V_GPIO16_OEN(1U)
13531 
13532 #define S_GPIO17_OEN    6
13533 #define V_GPIO17_OEN(x) ((x) << S_GPIO17_OEN)
13534 #define F_GPIO17_OEN    V_GPIO17_OEN(1U)
13535 
13536 #define S_GPIO18_OEN    5
13537 #define V_GPIO18_OEN(x) ((x) << S_GPIO18_OEN)
13538 #define F_GPIO18_OEN    V_GPIO18_OEN(1U)
13539 
13540 #define S_GPIO19_OEN    4
13541 #define V_GPIO19_OEN(x) ((x) << S_GPIO19_OEN)
13542 #define F_GPIO19_OEN    V_GPIO19_OEN(1U)
13543 
13544 #define S_GPIO16_OUT_VAL    3
13545 #define V_GPIO16_OUT_VAL(x) ((x) << S_GPIO16_OUT_VAL)
13546 #define F_GPIO16_OUT_VAL    V_GPIO16_OUT_VAL(1U)
13547 
13548 #define S_GPIO17_OUT_VAL    2
13549 #define V_GPIO17_OUT_VAL(x) ((x) << S_GPIO17_OUT_VAL)
13550 #define F_GPIO17_OUT_VAL    V_GPIO17_OUT_VAL(1U)
13551 
13552 #define S_GPIO18_OUT_VAL    1
13553 #define V_GPIO18_OUT_VAL(x) ((x) << S_GPIO18_OUT_VAL)
13554 #define F_GPIO18_OUT_VAL    V_GPIO18_OUT_VAL(1U)
13555 
13556 #define S_GPIO19_OUT_VAL    0
13557 #define V_GPIO19_OUT_VAL(x) ((x) << S_GPIO19_OUT_VAL)
13558 #define F_GPIO19_OUT_VAL    V_GPIO19_OUT_VAL(1U)
13559 
13560 #define A_DBG_PVT_REG_UPDATE_CTL 0x6104
13561 
13562 #define S_FAST_UPDATE    8
13563 #define V_FAST_UPDATE(x) ((x) << S_FAST_UPDATE)
13564 #define F_FAST_UPDATE    V_FAST_UPDATE(1U)
13565 
13566 #define S_FORCE_REG_IN_VALUE    2
13567 #define V_FORCE_REG_IN_VALUE(x) ((x) << S_FORCE_REG_IN_VALUE)
13568 #define F_FORCE_REG_IN_VALUE    V_FORCE_REG_IN_VALUE(1U)
13569 
13570 #define S_HALT_UPDATE    1
13571 #define V_HALT_UPDATE(x) ((x) << S_HALT_UPDATE)
13572 #define F_HALT_UPDATE    V_HALT_UPDATE(1U)
13573 
13574 #define A_DBG_GPIO_IN_NEW 0x6104
13575 
13576 #define S_GPIO16_CHG_DET    7
13577 #define V_GPIO16_CHG_DET(x) ((x) << S_GPIO16_CHG_DET)
13578 #define F_GPIO16_CHG_DET    V_GPIO16_CHG_DET(1U)
13579 
13580 #define S_GPIO17_CHG_DET    6
13581 #define V_GPIO17_CHG_DET(x) ((x) << S_GPIO17_CHG_DET)
13582 #define F_GPIO17_CHG_DET    V_GPIO17_CHG_DET(1U)
13583 
13584 #define S_GPIO18_CHG_DET    5
13585 #define V_GPIO18_CHG_DET(x) ((x) << S_GPIO18_CHG_DET)
13586 #define F_GPIO18_CHG_DET    V_GPIO18_CHG_DET(1U)
13587 
13588 #define S_GPIO19_CHG_DET    4
13589 #define V_GPIO19_CHG_DET(x) ((x) << S_GPIO19_CHG_DET)
13590 #define F_GPIO19_CHG_DET    V_GPIO19_CHG_DET(1U)
13591 
13592 #define S_GPIO19_IN    3
13593 #define V_GPIO19_IN(x) ((x) << S_GPIO19_IN)
13594 #define F_GPIO19_IN    V_GPIO19_IN(1U)
13595 
13596 #define S_GPIO18_IN    2
13597 #define V_GPIO18_IN(x) ((x) << S_GPIO18_IN)
13598 #define F_GPIO18_IN    V_GPIO18_IN(1U)
13599 
13600 #define S_GPIO17_IN    1
13601 #define V_GPIO17_IN(x) ((x) << S_GPIO17_IN)
13602 #define F_GPIO17_IN    V_GPIO17_IN(1U)
13603 
13604 #define S_GPIO16_IN    0
13605 #define V_GPIO16_IN(x) ((x) << S_GPIO16_IN)
13606 #define F_GPIO16_IN    V_GPIO16_IN(1U)
13607 
13608 #define A_DBG_PVT_REG_LAST_MEASUREMENT 0x6108
13609 
13610 #define S_LAST_MEASUREMENT_SELECT    8
13611 #define M_LAST_MEASUREMENT_SELECT    0x3U
13612 #define V_LAST_MEASUREMENT_SELECT(x) ((x) << S_LAST_MEASUREMENT_SELECT)
13613 #define G_LAST_MEASUREMENT_SELECT(x) (((x) >> S_LAST_MEASUREMENT_SELECT) & M_LAST_MEASUREMENT_SELECT)
13614 
13615 #define S_LAST_MEASUREMENT_RESULT_BANK_B    4
13616 #define M_LAST_MEASUREMENT_RESULT_BANK_B    0xfU
13617 #define V_LAST_MEASUREMENT_RESULT_BANK_B(x) ((x) << S_LAST_MEASUREMENT_RESULT_BANK_B)
13618 #define G_LAST_MEASUREMENT_RESULT_BANK_B(x) (((x) >> S_LAST_MEASUREMENT_RESULT_BANK_B) & M_LAST_MEASUREMENT_RESULT_BANK_B)
13619 
13620 #define S_LAST_MEASUREMENT_RESULT_BANK_A    0
13621 #define M_LAST_MEASUREMENT_RESULT_BANK_A    0xfU
13622 #define V_LAST_MEASUREMENT_RESULT_BANK_A(x) ((x) << S_LAST_MEASUREMENT_RESULT_BANK_A)
13623 #define G_LAST_MEASUREMENT_RESULT_BANK_A(x) (((x) >> S_LAST_MEASUREMENT_RESULT_BANK_A) & M_LAST_MEASUREMENT_RESULT_BANK_A)
13624 
13625 #define A_DBG_T5_STATIC_KX_PLL_CONF1 0x6108
13626 
13627 #define S_T5_STATIC_KX_PLL_BYPASS    30
13628 #define V_T5_STATIC_KX_PLL_BYPASS(x) ((x) << S_T5_STATIC_KX_PLL_BYPASS)
13629 #define F_T5_STATIC_KX_PLL_BYPASS    V_T5_STATIC_KX_PLL_BYPASS(1U)
13630 
13631 #define S_T5_STATIC_KX_PLL_VBOOSTDIV    27
13632 #define M_T5_STATIC_KX_PLL_VBOOSTDIV    0x7U
13633 #define V_T5_STATIC_KX_PLL_VBOOSTDIV(x) ((x) << S_T5_STATIC_KX_PLL_VBOOSTDIV)
13634 #define G_T5_STATIC_KX_PLL_VBOOSTDIV(x) (((x) >> S_T5_STATIC_KX_PLL_VBOOSTDIV) & M_T5_STATIC_KX_PLL_VBOOSTDIV)
13635 
13636 #define S_T5_STATIC_KX_PLL_CPISEL    24
13637 #define M_T5_STATIC_KX_PLL_CPISEL    0x7U
13638 #define V_T5_STATIC_KX_PLL_CPISEL(x) ((x) << S_T5_STATIC_KX_PLL_CPISEL)
13639 #define G_T5_STATIC_KX_PLL_CPISEL(x) (((x) >> S_T5_STATIC_KX_PLL_CPISEL) & M_T5_STATIC_KX_PLL_CPISEL)
13640 
13641 #define S_T5_STATIC_KX_PLL_CCALMETHOD    23
13642 #define V_T5_STATIC_KX_PLL_CCALMETHOD(x) ((x) << S_T5_STATIC_KX_PLL_CCALMETHOD)
13643 #define F_T5_STATIC_KX_PLL_CCALMETHOD    V_T5_STATIC_KX_PLL_CCALMETHOD(1U)
13644 
13645 #define S_T5_STATIC_KX_PLL_CCALLOAD    22
13646 #define V_T5_STATIC_KX_PLL_CCALLOAD(x) ((x) << S_T5_STATIC_KX_PLL_CCALLOAD)
13647 #define F_T5_STATIC_KX_PLL_CCALLOAD    V_T5_STATIC_KX_PLL_CCALLOAD(1U)
13648 
13649 #define S_T5_STATIC_KX_PLL_CCALFMIN    21
13650 #define V_T5_STATIC_KX_PLL_CCALFMIN(x) ((x) << S_T5_STATIC_KX_PLL_CCALFMIN)
13651 #define F_T5_STATIC_KX_PLL_CCALFMIN    V_T5_STATIC_KX_PLL_CCALFMIN(1U)
13652 
13653 #define S_T5_STATIC_KX_PLL_CCALFMAX    20
13654 #define V_T5_STATIC_KX_PLL_CCALFMAX(x) ((x) << S_T5_STATIC_KX_PLL_CCALFMAX)
13655 #define F_T5_STATIC_KX_PLL_CCALFMAX    V_T5_STATIC_KX_PLL_CCALFMAX(1U)
13656 
13657 #define S_T5_STATIC_KX_PLL_CCALCVHOLD    19
13658 #define V_T5_STATIC_KX_PLL_CCALCVHOLD(x) ((x) << S_T5_STATIC_KX_PLL_CCALCVHOLD)
13659 #define F_T5_STATIC_KX_PLL_CCALCVHOLD    V_T5_STATIC_KX_PLL_CCALCVHOLD(1U)
13660 
13661 #define S_T5_STATIC_KX_PLL_CCALBANDSEL    15
13662 #define M_T5_STATIC_KX_PLL_CCALBANDSEL    0xfU
13663 #define V_T5_STATIC_KX_PLL_CCALBANDSEL(x) ((x) << S_T5_STATIC_KX_PLL_CCALBANDSEL)
13664 #define G_T5_STATIC_KX_PLL_CCALBANDSEL(x) (((x) >> S_T5_STATIC_KX_PLL_CCALBANDSEL) & M_T5_STATIC_KX_PLL_CCALBANDSEL)
13665 
13666 #define S_T5_STATIC_KX_PLL_BGOFFSET    11
13667 #define M_T5_STATIC_KX_PLL_BGOFFSET    0xfU
13668 #define V_T5_STATIC_KX_PLL_BGOFFSET(x) ((x) << S_T5_STATIC_KX_PLL_BGOFFSET)
13669 #define G_T5_STATIC_KX_PLL_BGOFFSET(x) (((x) >> S_T5_STATIC_KX_PLL_BGOFFSET) & M_T5_STATIC_KX_PLL_BGOFFSET)
13670 
13671 #define S_T5_STATIC_KX_PLL_P    8
13672 #define M_T5_STATIC_KX_PLL_P    0x7U
13673 #define V_T5_STATIC_KX_PLL_P(x) ((x) << S_T5_STATIC_KX_PLL_P)
13674 #define G_T5_STATIC_KX_PLL_P(x) (((x) >> S_T5_STATIC_KX_PLL_P) & M_T5_STATIC_KX_PLL_P)
13675 
13676 #define S_T5_STATIC_KX_PLL_N2    4
13677 #define M_T5_STATIC_KX_PLL_N2    0xfU
13678 #define V_T5_STATIC_KX_PLL_N2(x) ((x) << S_T5_STATIC_KX_PLL_N2)
13679 #define G_T5_STATIC_KX_PLL_N2(x) (((x) >> S_T5_STATIC_KX_PLL_N2) & M_T5_STATIC_KX_PLL_N2)
13680 
13681 #define S_T5_STATIC_KX_PLL_N1    0
13682 #define M_T5_STATIC_KX_PLL_N1    0xfU
13683 #define V_T5_STATIC_KX_PLL_N1(x) ((x) << S_T5_STATIC_KX_PLL_N1)
13684 #define G_T5_STATIC_KX_PLL_N1(x) (((x) >> S_T5_STATIC_KX_PLL_N1) & M_T5_STATIC_KX_PLL_N1)
13685 
13686 #define A_DBG_STATIC_KX_PLL_CONF1 0x6108
13687 
13688 #define S_T6_STATIC_KX_PLL_BYPASS    30
13689 #define V_T6_STATIC_KX_PLL_BYPASS(x) ((x) << S_T6_STATIC_KX_PLL_BYPASS)
13690 #define F_T6_STATIC_KX_PLL_BYPASS    V_T6_STATIC_KX_PLL_BYPASS(1U)
13691 
13692 #define S_STATIC_KX_PLL_VBOOSTDIV    27
13693 #define M_STATIC_KX_PLL_VBOOSTDIV    0x7U
13694 #define V_STATIC_KX_PLL_VBOOSTDIV(x) ((x) << S_STATIC_KX_PLL_VBOOSTDIV)
13695 #define G_STATIC_KX_PLL_VBOOSTDIV(x) (((x) >> S_STATIC_KX_PLL_VBOOSTDIV) & M_STATIC_KX_PLL_VBOOSTDIV)
13696 
13697 #define S_STATIC_KX_PLL_CPISEL    24
13698 #define M_STATIC_KX_PLL_CPISEL    0x7U
13699 #define V_STATIC_KX_PLL_CPISEL(x) ((x) << S_STATIC_KX_PLL_CPISEL)
13700 #define G_STATIC_KX_PLL_CPISEL(x) (((x) >> S_STATIC_KX_PLL_CPISEL) & M_STATIC_KX_PLL_CPISEL)
13701 
13702 #define S_STATIC_KX_PLL_CCALMETHOD    23
13703 #define V_STATIC_KX_PLL_CCALMETHOD(x) ((x) << S_STATIC_KX_PLL_CCALMETHOD)
13704 #define F_STATIC_KX_PLL_CCALMETHOD    V_STATIC_KX_PLL_CCALMETHOD(1U)
13705 
13706 #define S_STATIC_KX_PLL_CCALLOAD    22
13707 #define V_STATIC_KX_PLL_CCALLOAD(x) ((x) << S_STATIC_KX_PLL_CCALLOAD)
13708 #define F_STATIC_KX_PLL_CCALLOAD    V_STATIC_KX_PLL_CCALLOAD(1U)
13709 
13710 #define S_STATIC_KX_PLL_CCALFMIN    21
13711 #define V_STATIC_KX_PLL_CCALFMIN(x) ((x) << S_STATIC_KX_PLL_CCALFMIN)
13712 #define F_STATIC_KX_PLL_CCALFMIN    V_STATIC_KX_PLL_CCALFMIN(1U)
13713 
13714 #define S_STATIC_KX_PLL_CCALFMAX    20
13715 #define V_STATIC_KX_PLL_CCALFMAX(x) ((x) << S_STATIC_KX_PLL_CCALFMAX)
13716 #define F_STATIC_KX_PLL_CCALFMAX    V_STATIC_KX_PLL_CCALFMAX(1U)
13717 
13718 #define S_STATIC_KX_PLL_CCALCVHOLD    19
13719 #define V_STATIC_KX_PLL_CCALCVHOLD(x) ((x) << S_STATIC_KX_PLL_CCALCVHOLD)
13720 #define F_STATIC_KX_PLL_CCALCVHOLD    V_STATIC_KX_PLL_CCALCVHOLD(1U)
13721 
13722 #define S_STATIC_KX_PLL_CCALBANDSEL    15
13723 #define M_STATIC_KX_PLL_CCALBANDSEL    0xfU
13724 #define V_STATIC_KX_PLL_CCALBANDSEL(x) ((x) << S_STATIC_KX_PLL_CCALBANDSEL)
13725 #define G_STATIC_KX_PLL_CCALBANDSEL(x) (((x) >> S_STATIC_KX_PLL_CCALBANDSEL) & M_STATIC_KX_PLL_CCALBANDSEL)
13726 
13727 #define S_STATIC_KX_PLL_BGOFFSET    11
13728 #define M_STATIC_KX_PLL_BGOFFSET    0xfU
13729 #define V_STATIC_KX_PLL_BGOFFSET(x) ((x) << S_STATIC_KX_PLL_BGOFFSET)
13730 #define G_STATIC_KX_PLL_BGOFFSET(x) (((x) >> S_STATIC_KX_PLL_BGOFFSET) & M_STATIC_KX_PLL_BGOFFSET)
13731 
13732 #define S_T6_STATIC_KX_PLL_P    8
13733 #define M_T6_STATIC_KX_PLL_P    0x7U
13734 #define V_T6_STATIC_KX_PLL_P(x) ((x) << S_T6_STATIC_KX_PLL_P)
13735 #define G_T6_STATIC_KX_PLL_P(x) (((x) >> S_T6_STATIC_KX_PLL_P) & M_T6_STATIC_KX_PLL_P)
13736 
13737 #define S_T6_STATIC_KX_PLL_N2    4
13738 #define M_T6_STATIC_KX_PLL_N2    0xfU
13739 #define V_T6_STATIC_KX_PLL_N2(x) ((x) << S_T6_STATIC_KX_PLL_N2)
13740 #define G_T6_STATIC_KX_PLL_N2(x) (((x) >> S_T6_STATIC_KX_PLL_N2) & M_T6_STATIC_KX_PLL_N2)
13741 
13742 #define S_T6_STATIC_KX_PLL_N1    0
13743 #define M_T6_STATIC_KX_PLL_N1    0xfU
13744 #define V_T6_STATIC_KX_PLL_N1(x) ((x) << S_T6_STATIC_KX_PLL_N1)
13745 #define G_T6_STATIC_KX_PLL_N1(x) (((x) >> S_T6_STATIC_KX_PLL_N1) & M_T6_STATIC_KX_PLL_N1)
13746 
13747 #define A_DBG_PVT_REG_DRVN 0x610c
13748 
13749 #define S_PVT_REG_DRVN_EN    8
13750 #define V_PVT_REG_DRVN_EN(x) ((x) << S_PVT_REG_DRVN_EN)
13751 #define F_PVT_REG_DRVN_EN    V_PVT_REG_DRVN_EN(1U)
13752 
13753 #define S_PVT_REG_DRVN_B    4
13754 #define M_PVT_REG_DRVN_B    0xfU
13755 #define V_PVT_REG_DRVN_B(x) ((x) << S_PVT_REG_DRVN_B)
13756 #define G_PVT_REG_DRVN_B(x) (((x) >> S_PVT_REG_DRVN_B) & M_PVT_REG_DRVN_B)
13757 
13758 #define S_PVT_REG_DRVN_A    0
13759 #define M_PVT_REG_DRVN_A    0xfU
13760 #define V_PVT_REG_DRVN_A(x) ((x) << S_PVT_REG_DRVN_A)
13761 #define G_PVT_REG_DRVN_A(x) (((x) >> S_PVT_REG_DRVN_A) & M_PVT_REG_DRVN_A)
13762 
13763 #define A_DBG_T5_STATIC_KX_PLL_CONF2 0x610c
13764 
13765 #define S_T5_STATIC_KX_PLL_M    11
13766 #define M_T5_STATIC_KX_PLL_M    0x1ffU
13767 #define V_T5_STATIC_KX_PLL_M(x) ((x) << S_T5_STATIC_KX_PLL_M)
13768 #define G_T5_STATIC_KX_PLL_M(x) (((x) >> S_T5_STATIC_KX_PLL_M) & M_T5_STATIC_KX_PLL_M)
13769 
13770 #define S_T5_STATIC_KX_PLL_ANALOGTUNE    0
13771 #define M_T5_STATIC_KX_PLL_ANALOGTUNE    0x7ffU
13772 #define V_T5_STATIC_KX_PLL_ANALOGTUNE(x) ((x) << S_T5_STATIC_KX_PLL_ANALOGTUNE)
13773 #define G_T5_STATIC_KX_PLL_ANALOGTUNE(x) (((x) >> S_T5_STATIC_KX_PLL_ANALOGTUNE) & M_T5_STATIC_KX_PLL_ANALOGTUNE)
13774 
13775 #define A_DBG_STATIC_KX_PLL_CONF2 0x610c
13776 
13777 #define S_T6_STATIC_KX_PLL_M    11
13778 #define M_T6_STATIC_KX_PLL_M    0x1ffU
13779 #define V_T6_STATIC_KX_PLL_M(x) ((x) << S_T6_STATIC_KX_PLL_M)
13780 #define G_T6_STATIC_KX_PLL_M(x) (((x) >> S_T6_STATIC_KX_PLL_M) & M_T6_STATIC_KX_PLL_M)
13781 
13782 #define S_STATIC_KX_PLL_ANALOGTUNE    0
13783 #define M_STATIC_KX_PLL_ANALOGTUNE    0x7ffU
13784 #define V_STATIC_KX_PLL_ANALOGTUNE(x) ((x) << S_STATIC_KX_PLL_ANALOGTUNE)
13785 #define G_STATIC_KX_PLL_ANALOGTUNE(x) (((x) >> S_STATIC_KX_PLL_ANALOGTUNE) & M_STATIC_KX_PLL_ANALOGTUNE)
13786 
13787 #define A_DBG_PVT_REG_DRVP 0x6110
13788 
13789 #define S_PVT_REG_DRVP_EN    8
13790 #define V_PVT_REG_DRVP_EN(x) ((x) << S_PVT_REG_DRVP_EN)
13791 #define F_PVT_REG_DRVP_EN    V_PVT_REG_DRVP_EN(1U)
13792 
13793 #define S_PVT_REG_DRVP_B    4
13794 #define M_PVT_REG_DRVP_B    0xfU
13795 #define V_PVT_REG_DRVP_B(x) ((x) << S_PVT_REG_DRVP_B)
13796 #define G_PVT_REG_DRVP_B(x) (((x) >> S_PVT_REG_DRVP_B) & M_PVT_REG_DRVP_B)
13797 
13798 #define S_PVT_REG_DRVP_A    0
13799 #define M_PVT_REG_DRVP_A    0xfU
13800 #define V_PVT_REG_DRVP_A(x) ((x) << S_PVT_REG_DRVP_A)
13801 #define G_PVT_REG_DRVP_A(x) (((x) >> S_PVT_REG_DRVP_A) & M_PVT_REG_DRVP_A)
13802 
13803 #define A_DBG_T5_STATIC_C_DFS_CONF 0x6110
13804 
13805 #define S_STATIC_C_DFS_RANGEA    8
13806 #define M_STATIC_C_DFS_RANGEA    0x1fU
13807 #define V_STATIC_C_DFS_RANGEA(x) ((x) << S_STATIC_C_DFS_RANGEA)
13808 #define G_STATIC_C_DFS_RANGEA(x) (((x) >> S_STATIC_C_DFS_RANGEA) & M_STATIC_C_DFS_RANGEA)
13809 
13810 #define S_STATIC_C_DFS_RANGEB    3
13811 #define M_STATIC_C_DFS_RANGEB    0x1fU
13812 #define V_STATIC_C_DFS_RANGEB(x) ((x) << S_STATIC_C_DFS_RANGEB)
13813 #define G_STATIC_C_DFS_RANGEB(x) (((x) >> S_STATIC_C_DFS_RANGEB) & M_STATIC_C_DFS_RANGEB)
13814 
13815 #define S_STATIC_C_DFS_FFTUNE4    2
13816 #define V_STATIC_C_DFS_FFTUNE4(x) ((x) << S_STATIC_C_DFS_FFTUNE4)
13817 #define F_STATIC_C_DFS_FFTUNE4    V_STATIC_C_DFS_FFTUNE4(1U)
13818 
13819 #define S_STATIC_C_DFS_FFTUNE5    1
13820 #define V_STATIC_C_DFS_FFTUNE5(x) ((x) << S_STATIC_C_DFS_FFTUNE5)
13821 #define F_STATIC_C_DFS_FFTUNE5    V_STATIC_C_DFS_FFTUNE5(1U)
13822 
13823 #define S_STATIC_C_DFS_ENABLE    0
13824 #define V_STATIC_C_DFS_ENABLE(x) ((x) << S_STATIC_C_DFS_ENABLE)
13825 #define F_STATIC_C_DFS_ENABLE    V_STATIC_C_DFS_ENABLE(1U)
13826 
13827 #define A_DBG_STATIC_C_DFS_CONF 0x6110
13828 #define A_DBG_PVT_REG_TERMN 0x6114
13829 
13830 #define S_PVT_REG_TERMN_EN    8
13831 #define V_PVT_REG_TERMN_EN(x) ((x) << S_PVT_REG_TERMN_EN)
13832 #define F_PVT_REG_TERMN_EN    V_PVT_REG_TERMN_EN(1U)
13833 
13834 #define S_PVT_REG_TERMN_B    4
13835 #define M_PVT_REG_TERMN_B    0xfU
13836 #define V_PVT_REG_TERMN_B(x) ((x) << S_PVT_REG_TERMN_B)
13837 #define G_PVT_REG_TERMN_B(x) (((x) >> S_PVT_REG_TERMN_B) & M_PVT_REG_TERMN_B)
13838 
13839 #define S_PVT_REG_TERMN_A    0
13840 #define M_PVT_REG_TERMN_A    0xfU
13841 #define V_PVT_REG_TERMN_A(x) ((x) << S_PVT_REG_TERMN_A)
13842 #define G_PVT_REG_TERMN_A(x) (((x) >> S_PVT_REG_TERMN_A) & M_PVT_REG_TERMN_A)
13843 
13844 #define A_DBG_T5_STATIC_U_DFS_CONF 0x6114
13845 
13846 #define S_STATIC_U_DFS_RANGEA    8
13847 #define M_STATIC_U_DFS_RANGEA    0x1fU
13848 #define V_STATIC_U_DFS_RANGEA(x) ((x) << S_STATIC_U_DFS_RANGEA)
13849 #define G_STATIC_U_DFS_RANGEA(x) (((x) >> S_STATIC_U_DFS_RANGEA) & M_STATIC_U_DFS_RANGEA)
13850 
13851 #define S_STATIC_U_DFS_RANGEB    3
13852 #define M_STATIC_U_DFS_RANGEB    0x1fU
13853 #define V_STATIC_U_DFS_RANGEB(x) ((x) << S_STATIC_U_DFS_RANGEB)
13854 #define G_STATIC_U_DFS_RANGEB(x) (((x) >> S_STATIC_U_DFS_RANGEB) & M_STATIC_U_DFS_RANGEB)
13855 
13856 #define S_STATIC_U_DFS_FFTUNE4    2
13857 #define V_STATIC_U_DFS_FFTUNE4(x) ((x) << S_STATIC_U_DFS_FFTUNE4)
13858 #define F_STATIC_U_DFS_FFTUNE4    V_STATIC_U_DFS_FFTUNE4(1U)
13859 
13860 #define S_STATIC_U_DFS_FFTUNE5    1
13861 #define V_STATIC_U_DFS_FFTUNE5(x) ((x) << S_STATIC_U_DFS_FFTUNE5)
13862 #define F_STATIC_U_DFS_FFTUNE5    V_STATIC_U_DFS_FFTUNE5(1U)
13863 
13864 #define S_STATIC_U_DFS_ENABLE    0
13865 #define V_STATIC_U_DFS_ENABLE(x) ((x) << S_STATIC_U_DFS_ENABLE)
13866 #define F_STATIC_U_DFS_ENABLE    V_STATIC_U_DFS_ENABLE(1U)
13867 
13868 #define A_DBG_STATIC_U_DFS_CONF 0x6114
13869 #define A_DBG_PVT_REG_TERMP 0x6118
13870 
13871 #define S_PVT_REG_TERMP_EN    8
13872 #define V_PVT_REG_TERMP_EN(x) ((x) << S_PVT_REG_TERMP_EN)
13873 #define F_PVT_REG_TERMP_EN    V_PVT_REG_TERMP_EN(1U)
13874 
13875 #define S_PVT_REG_TERMP_B    4
13876 #define M_PVT_REG_TERMP_B    0xfU
13877 #define V_PVT_REG_TERMP_B(x) ((x) << S_PVT_REG_TERMP_B)
13878 #define G_PVT_REG_TERMP_B(x) (((x) >> S_PVT_REG_TERMP_B) & M_PVT_REG_TERMP_B)
13879 
13880 #define S_PVT_REG_TERMP_A    0
13881 #define M_PVT_REG_TERMP_A    0xfU
13882 #define V_PVT_REG_TERMP_A(x) ((x) << S_PVT_REG_TERMP_A)
13883 #define G_PVT_REG_TERMP_A(x) (((x) >> S_PVT_REG_TERMP_A) & M_PVT_REG_TERMP_A)
13884 
13885 #define A_DBG_GPIO_PE_EN 0x6118
13886 
13887 #define S_GPIO19_PE_EN    19
13888 #define V_GPIO19_PE_EN(x) ((x) << S_GPIO19_PE_EN)
13889 #define F_GPIO19_PE_EN    V_GPIO19_PE_EN(1U)
13890 
13891 #define S_GPIO18_PE_EN    18
13892 #define V_GPIO18_PE_EN(x) ((x) << S_GPIO18_PE_EN)
13893 #define F_GPIO18_PE_EN    V_GPIO18_PE_EN(1U)
13894 
13895 #define S_GPIO17_PE_EN    17
13896 #define V_GPIO17_PE_EN(x) ((x) << S_GPIO17_PE_EN)
13897 #define F_GPIO17_PE_EN    V_GPIO17_PE_EN(1U)
13898 
13899 #define S_GPIO16_PE_EN    16
13900 #define V_GPIO16_PE_EN(x) ((x) << S_GPIO16_PE_EN)
13901 #define F_GPIO16_PE_EN    V_GPIO16_PE_EN(1U)
13902 
13903 #define S_GPIO15_PE_EN    15
13904 #define V_GPIO15_PE_EN(x) ((x) << S_GPIO15_PE_EN)
13905 #define F_GPIO15_PE_EN    V_GPIO15_PE_EN(1U)
13906 
13907 #define S_GPIO14_PE_EN    14
13908 #define V_GPIO14_PE_EN(x) ((x) << S_GPIO14_PE_EN)
13909 #define F_GPIO14_PE_EN    V_GPIO14_PE_EN(1U)
13910 
13911 #define S_GPIO13_PE_EN    13
13912 #define V_GPIO13_PE_EN(x) ((x) << S_GPIO13_PE_EN)
13913 #define F_GPIO13_PE_EN    V_GPIO13_PE_EN(1U)
13914 
13915 #define S_GPIO12_PE_EN    12
13916 #define V_GPIO12_PE_EN(x) ((x) << S_GPIO12_PE_EN)
13917 #define F_GPIO12_PE_EN    V_GPIO12_PE_EN(1U)
13918 
13919 #define S_GPIO11_PE_EN    11
13920 #define V_GPIO11_PE_EN(x) ((x) << S_GPIO11_PE_EN)
13921 #define F_GPIO11_PE_EN    V_GPIO11_PE_EN(1U)
13922 
13923 #define S_GPIO10_PE_EN    10
13924 #define V_GPIO10_PE_EN(x) ((x) << S_GPIO10_PE_EN)
13925 #define F_GPIO10_PE_EN    V_GPIO10_PE_EN(1U)
13926 
13927 #define S_GPIO9_PE_EN    9
13928 #define V_GPIO9_PE_EN(x) ((x) << S_GPIO9_PE_EN)
13929 #define F_GPIO9_PE_EN    V_GPIO9_PE_EN(1U)
13930 
13931 #define S_GPIO8_PE_EN    8
13932 #define V_GPIO8_PE_EN(x) ((x) << S_GPIO8_PE_EN)
13933 #define F_GPIO8_PE_EN    V_GPIO8_PE_EN(1U)
13934 
13935 #define S_GPIO7_PE_EN    7
13936 #define V_GPIO7_PE_EN(x) ((x) << S_GPIO7_PE_EN)
13937 #define F_GPIO7_PE_EN    V_GPIO7_PE_EN(1U)
13938 
13939 #define S_GPIO6_PE_EN    6
13940 #define V_GPIO6_PE_EN(x) ((x) << S_GPIO6_PE_EN)
13941 #define F_GPIO6_PE_EN    V_GPIO6_PE_EN(1U)
13942 
13943 #define S_GPIO5_PE_EN    5
13944 #define V_GPIO5_PE_EN(x) ((x) << S_GPIO5_PE_EN)
13945 #define F_GPIO5_PE_EN    V_GPIO5_PE_EN(1U)
13946 
13947 #define S_GPIO4_PE_EN    4
13948 #define V_GPIO4_PE_EN(x) ((x) << S_GPIO4_PE_EN)
13949 #define F_GPIO4_PE_EN    V_GPIO4_PE_EN(1U)
13950 
13951 #define S_GPIO3_PE_EN    3
13952 #define V_GPIO3_PE_EN(x) ((x) << S_GPIO3_PE_EN)
13953 #define F_GPIO3_PE_EN    V_GPIO3_PE_EN(1U)
13954 
13955 #define S_GPIO2_PE_EN    2
13956 #define V_GPIO2_PE_EN(x) ((x) << S_GPIO2_PE_EN)
13957 #define F_GPIO2_PE_EN    V_GPIO2_PE_EN(1U)
13958 
13959 #define S_GPIO1_PE_EN    1
13960 #define V_GPIO1_PE_EN(x) ((x) << S_GPIO1_PE_EN)
13961 #define F_GPIO1_PE_EN    V_GPIO1_PE_EN(1U)
13962 
13963 #define S_GPIO0_PE_EN    0
13964 #define V_GPIO0_PE_EN(x) ((x) << S_GPIO0_PE_EN)
13965 #define F_GPIO0_PE_EN    V_GPIO0_PE_EN(1U)
13966 
13967 #define A_DBG_PVT_REG_THRESHOLD 0x611c
13968 
13969 #define S_PVT_CALIBRATION_DONE    8
13970 #define V_PVT_CALIBRATION_DONE(x) ((x) << S_PVT_CALIBRATION_DONE)
13971 #define F_PVT_CALIBRATION_DONE    V_PVT_CALIBRATION_DONE(1U)
13972 
13973 #define S_THRESHOLD_TERMP_MAX_SYNC    7
13974 #define V_THRESHOLD_TERMP_MAX_SYNC(x) ((x) << S_THRESHOLD_TERMP_MAX_SYNC)
13975 #define F_THRESHOLD_TERMP_MAX_SYNC    V_THRESHOLD_TERMP_MAX_SYNC(1U)
13976 
13977 #define S_THRESHOLD_TERMP_MIN_SYNC    6
13978 #define V_THRESHOLD_TERMP_MIN_SYNC(x) ((x) << S_THRESHOLD_TERMP_MIN_SYNC)
13979 #define F_THRESHOLD_TERMP_MIN_SYNC    V_THRESHOLD_TERMP_MIN_SYNC(1U)
13980 
13981 #define S_THRESHOLD_TERMN_MAX_SYNC    5
13982 #define V_THRESHOLD_TERMN_MAX_SYNC(x) ((x) << S_THRESHOLD_TERMN_MAX_SYNC)
13983 #define F_THRESHOLD_TERMN_MAX_SYNC    V_THRESHOLD_TERMN_MAX_SYNC(1U)
13984 
13985 #define S_THRESHOLD_TERMN_MIN_SYNC    4
13986 #define V_THRESHOLD_TERMN_MIN_SYNC(x) ((x) << S_THRESHOLD_TERMN_MIN_SYNC)
13987 #define F_THRESHOLD_TERMN_MIN_SYNC    V_THRESHOLD_TERMN_MIN_SYNC(1U)
13988 
13989 #define S_THRESHOLD_DRVP_MAX_SYNC    3
13990 #define V_THRESHOLD_DRVP_MAX_SYNC(x) ((x) << S_THRESHOLD_DRVP_MAX_SYNC)
13991 #define F_THRESHOLD_DRVP_MAX_SYNC    V_THRESHOLD_DRVP_MAX_SYNC(1U)
13992 
13993 #define S_THRESHOLD_DRVP_MIN_SYNC    2
13994 #define V_THRESHOLD_DRVP_MIN_SYNC(x) ((x) << S_THRESHOLD_DRVP_MIN_SYNC)
13995 #define F_THRESHOLD_DRVP_MIN_SYNC    V_THRESHOLD_DRVP_MIN_SYNC(1U)
13996 
13997 #define S_THRESHOLD_DRVN_MAX_SYNC    1
13998 #define V_THRESHOLD_DRVN_MAX_SYNC(x) ((x) << S_THRESHOLD_DRVN_MAX_SYNC)
13999 #define F_THRESHOLD_DRVN_MAX_SYNC    V_THRESHOLD_DRVN_MAX_SYNC(1U)
14000 
14001 #define S_THRESHOLD_DRVN_MIN_SYNC    0
14002 #define V_THRESHOLD_DRVN_MIN_SYNC(x) ((x) << S_THRESHOLD_DRVN_MIN_SYNC)
14003 #define F_THRESHOLD_DRVN_MIN_SYNC    V_THRESHOLD_DRVN_MIN_SYNC(1U)
14004 
14005 #define A_DBG_GPIO_PS_EN 0x611c
14006 
14007 #define S_GPIO19_PS_EN    19
14008 #define V_GPIO19_PS_EN(x) ((x) << S_GPIO19_PS_EN)
14009 #define F_GPIO19_PS_EN    V_GPIO19_PS_EN(1U)
14010 
14011 #define S_GPIO18_PS_EN    18
14012 #define V_GPIO18_PS_EN(x) ((x) << S_GPIO18_PS_EN)
14013 #define F_GPIO18_PS_EN    V_GPIO18_PS_EN(1U)
14014 
14015 #define S_GPIO17_PS_EN    17
14016 #define V_GPIO17_PS_EN(x) ((x) << S_GPIO17_PS_EN)
14017 #define F_GPIO17_PS_EN    V_GPIO17_PS_EN(1U)
14018 
14019 #define S_GPIO16_PS_EN    16
14020 #define V_GPIO16_PS_EN(x) ((x) << S_GPIO16_PS_EN)
14021 #define F_GPIO16_PS_EN    V_GPIO16_PS_EN(1U)
14022 
14023 #define S_GPIO15_PS_EN    15
14024 #define V_GPIO15_PS_EN(x) ((x) << S_GPIO15_PS_EN)
14025 #define F_GPIO15_PS_EN    V_GPIO15_PS_EN(1U)
14026 
14027 #define S_GPIO14_PS_EN    14
14028 #define V_GPIO14_PS_EN(x) ((x) << S_GPIO14_PS_EN)
14029 #define F_GPIO14_PS_EN    V_GPIO14_PS_EN(1U)
14030 
14031 #define S_GPIO13_PS_EN    13
14032 #define V_GPIO13_PS_EN(x) ((x) << S_GPIO13_PS_EN)
14033 #define F_GPIO13_PS_EN    V_GPIO13_PS_EN(1U)
14034 
14035 #define S_GPIO12_PS_EN    12
14036 #define V_GPIO12_PS_EN(x) ((x) << S_GPIO12_PS_EN)
14037 #define F_GPIO12_PS_EN    V_GPIO12_PS_EN(1U)
14038 
14039 #define S_GPIO11_PS_EN    11
14040 #define V_GPIO11_PS_EN(x) ((x) << S_GPIO11_PS_EN)
14041 #define F_GPIO11_PS_EN    V_GPIO11_PS_EN(1U)
14042 
14043 #define S_GPIO10_PS_EN    10
14044 #define V_GPIO10_PS_EN(x) ((x) << S_GPIO10_PS_EN)
14045 #define F_GPIO10_PS_EN    V_GPIO10_PS_EN(1U)
14046 
14047 #define S_GPIO9_PS_EN    9
14048 #define V_GPIO9_PS_EN(x) ((x) << S_GPIO9_PS_EN)
14049 #define F_GPIO9_PS_EN    V_GPIO9_PS_EN(1U)
14050 
14051 #define S_GPIO8_PS_EN    8
14052 #define V_GPIO8_PS_EN(x) ((x) << S_GPIO8_PS_EN)
14053 #define F_GPIO8_PS_EN    V_GPIO8_PS_EN(1U)
14054 
14055 #define S_GPIO7_PS_EN    7
14056 #define V_GPIO7_PS_EN(x) ((x) << S_GPIO7_PS_EN)
14057 #define F_GPIO7_PS_EN    V_GPIO7_PS_EN(1U)
14058 
14059 #define S_GPIO6_PS_EN    6
14060 #define V_GPIO6_PS_EN(x) ((x) << S_GPIO6_PS_EN)
14061 #define F_GPIO6_PS_EN    V_GPIO6_PS_EN(1U)
14062 
14063 #define S_GPIO5_PS_EN    5
14064 #define V_GPIO5_PS_EN(x) ((x) << S_GPIO5_PS_EN)
14065 #define F_GPIO5_PS_EN    V_GPIO5_PS_EN(1U)
14066 
14067 #define S_GPIO4_PS_EN    4
14068 #define V_GPIO4_PS_EN(x) ((x) << S_GPIO4_PS_EN)
14069 #define F_GPIO4_PS_EN    V_GPIO4_PS_EN(1U)
14070 
14071 #define S_GPIO3_PS_EN    3
14072 #define V_GPIO3_PS_EN(x) ((x) << S_GPIO3_PS_EN)
14073 #define F_GPIO3_PS_EN    V_GPIO3_PS_EN(1U)
14074 
14075 #define S_GPIO2_PS_EN    2
14076 #define V_GPIO2_PS_EN(x) ((x) << S_GPIO2_PS_EN)
14077 #define F_GPIO2_PS_EN    V_GPIO2_PS_EN(1U)
14078 
14079 #define S_GPIO1_PS_EN    1
14080 #define V_GPIO1_PS_EN(x) ((x) << S_GPIO1_PS_EN)
14081 #define F_GPIO1_PS_EN    V_GPIO1_PS_EN(1U)
14082 
14083 #define S_GPIO0_PS_EN    0
14084 #define V_GPIO0_PS_EN(x) ((x) << S_GPIO0_PS_EN)
14085 #define F_GPIO0_PS_EN    V_GPIO0_PS_EN(1U)
14086 
14087 #define A_DBG_PVT_REG_IN_TERMP 0x6120
14088 
14089 #define S_REG_IN_TERMP_B    4
14090 #define M_REG_IN_TERMP_B    0xfU
14091 #define V_REG_IN_TERMP_B(x) ((x) << S_REG_IN_TERMP_B)
14092 #define G_REG_IN_TERMP_B(x) (((x) >> S_REG_IN_TERMP_B) & M_REG_IN_TERMP_B)
14093 
14094 #define S_REG_IN_TERMP_A    0
14095 #define M_REG_IN_TERMP_A    0xfU
14096 #define V_REG_IN_TERMP_A(x) ((x) << S_REG_IN_TERMP_A)
14097 #define G_REG_IN_TERMP_A(x) (((x) >> S_REG_IN_TERMP_A) & M_REG_IN_TERMP_A)
14098 
14099 #define A_DBG_EFUSE_BYTE16_19 0x6120
14100 #define A_DBG_PVT_REG_IN_TERMN 0x6124
14101 
14102 #define S_REG_IN_TERMN_B    4
14103 #define M_REG_IN_TERMN_B    0xfU
14104 #define V_REG_IN_TERMN_B(x) ((x) << S_REG_IN_TERMN_B)
14105 #define G_REG_IN_TERMN_B(x) (((x) >> S_REG_IN_TERMN_B) & M_REG_IN_TERMN_B)
14106 
14107 #define S_REG_IN_TERMN_A    0
14108 #define M_REG_IN_TERMN_A    0xfU
14109 #define V_REG_IN_TERMN_A(x) ((x) << S_REG_IN_TERMN_A)
14110 #define G_REG_IN_TERMN_A(x) (((x) >> S_REG_IN_TERMN_A) & M_REG_IN_TERMN_A)
14111 
14112 #define A_DBG_EFUSE_BYTE20_23 0x6124
14113 #define A_DBG_PVT_REG_IN_DRVP 0x6128
14114 
14115 #define S_REG_IN_DRVP_B    4
14116 #define M_REG_IN_DRVP_B    0xfU
14117 #define V_REG_IN_DRVP_B(x) ((x) << S_REG_IN_DRVP_B)
14118 #define G_REG_IN_DRVP_B(x) (((x) >> S_REG_IN_DRVP_B) & M_REG_IN_DRVP_B)
14119 
14120 #define S_REG_IN_DRVP_A    0
14121 #define M_REG_IN_DRVP_A    0xfU
14122 #define V_REG_IN_DRVP_A(x) ((x) << S_REG_IN_DRVP_A)
14123 #define G_REG_IN_DRVP_A(x) (((x) >> S_REG_IN_DRVP_A) & M_REG_IN_DRVP_A)
14124 
14125 #define A_DBG_EFUSE_BYTE24_27 0x6128
14126 #define A_DBG_PVT_REG_IN_DRVN 0x612c
14127 
14128 #define S_REG_IN_DRVN_B    4
14129 #define M_REG_IN_DRVN_B    0xfU
14130 #define V_REG_IN_DRVN_B(x) ((x) << S_REG_IN_DRVN_B)
14131 #define G_REG_IN_DRVN_B(x) (((x) >> S_REG_IN_DRVN_B) & M_REG_IN_DRVN_B)
14132 
14133 #define S_REG_IN_DRVN_A    0
14134 #define M_REG_IN_DRVN_A    0xfU
14135 #define V_REG_IN_DRVN_A(x) ((x) << S_REG_IN_DRVN_A)
14136 #define G_REG_IN_DRVN_A(x) (((x) >> S_REG_IN_DRVN_A) & M_REG_IN_DRVN_A)
14137 
14138 #define A_DBG_EFUSE_BYTE28_31 0x612c
14139 #define A_DBG_PVT_REG_OUT_TERMP 0x6130
14140 
14141 #define S_REG_OUT_TERMP_B    4
14142 #define M_REG_OUT_TERMP_B    0xfU
14143 #define V_REG_OUT_TERMP_B(x) ((x) << S_REG_OUT_TERMP_B)
14144 #define G_REG_OUT_TERMP_B(x) (((x) >> S_REG_OUT_TERMP_B) & M_REG_OUT_TERMP_B)
14145 
14146 #define S_REG_OUT_TERMP_A    0
14147 #define M_REG_OUT_TERMP_A    0xfU
14148 #define V_REG_OUT_TERMP_A(x) ((x) << S_REG_OUT_TERMP_A)
14149 #define G_REG_OUT_TERMP_A(x) (((x) >> S_REG_OUT_TERMP_A) & M_REG_OUT_TERMP_A)
14150 
14151 #define A_DBG_EFUSE_BYTE32_35 0x6130
14152 #define A_DBG_PVT_REG_OUT_TERMN 0x6134
14153 
14154 #define S_REG_OUT_TERMN_B    4
14155 #define M_REG_OUT_TERMN_B    0xfU
14156 #define V_REG_OUT_TERMN_B(x) ((x) << S_REG_OUT_TERMN_B)
14157 #define G_REG_OUT_TERMN_B(x) (((x) >> S_REG_OUT_TERMN_B) & M_REG_OUT_TERMN_B)
14158 
14159 #define S_REG_OUT_TERMN_A    0
14160 #define M_REG_OUT_TERMN_A    0xfU
14161 #define V_REG_OUT_TERMN_A(x) ((x) << S_REG_OUT_TERMN_A)
14162 #define G_REG_OUT_TERMN_A(x) (((x) >> S_REG_OUT_TERMN_A) & M_REG_OUT_TERMN_A)
14163 
14164 #define A_DBG_EFUSE_BYTE36_39 0x6134
14165 #define A_DBG_PVT_REG_OUT_DRVP 0x6138
14166 
14167 #define S_REG_OUT_DRVP_B    4
14168 #define M_REG_OUT_DRVP_B    0xfU
14169 #define V_REG_OUT_DRVP_B(x) ((x) << S_REG_OUT_DRVP_B)
14170 #define G_REG_OUT_DRVP_B(x) (((x) >> S_REG_OUT_DRVP_B) & M_REG_OUT_DRVP_B)
14171 
14172 #define S_REG_OUT_DRVP_A    0
14173 #define M_REG_OUT_DRVP_A    0xfU
14174 #define V_REG_OUT_DRVP_A(x) ((x) << S_REG_OUT_DRVP_A)
14175 #define G_REG_OUT_DRVP_A(x) (((x) >> S_REG_OUT_DRVP_A) & M_REG_OUT_DRVP_A)
14176 
14177 #define A_DBG_EFUSE_BYTE40_43 0x6138
14178 #define A_DBG_PVT_REG_OUT_DRVN 0x613c
14179 
14180 #define S_REG_OUT_DRVN_B    4
14181 #define M_REG_OUT_DRVN_B    0xfU
14182 #define V_REG_OUT_DRVN_B(x) ((x) << S_REG_OUT_DRVN_B)
14183 #define G_REG_OUT_DRVN_B(x) (((x) >> S_REG_OUT_DRVN_B) & M_REG_OUT_DRVN_B)
14184 
14185 #define S_REG_OUT_DRVN_A    0
14186 #define M_REG_OUT_DRVN_A    0xfU
14187 #define V_REG_OUT_DRVN_A(x) ((x) << S_REG_OUT_DRVN_A)
14188 #define G_REG_OUT_DRVN_A(x) (((x) >> S_REG_OUT_DRVN_A) & M_REG_OUT_DRVN_A)
14189 
14190 #define A_DBG_EFUSE_BYTE44_47 0x613c
14191 #define A_DBG_PVT_REG_HISTORY_TERMP 0x6140
14192 
14193 #define S_TERMP_B_HISTORY    4
14194 #define M_TERMP_B_HISTORY    0xfU
14195 #define V_TERMP_B_HISTORY(x) ((x) << S_TERMP_B_HISTORY)
14196 #define G_TERMP_B_HISTORY(x) (((x) >> S_TERMP_B_HISTORY) & M_TERMP_B_HISTORY)
14197 
14198 #define S_TERMP_A_HISTORY    0
14199 #define M_TERMP_A_HISTORY    0xfU
14200 #define V_TERMP_A_HISTORY(x) ((x) << S_TERMP_A_HISTORY)
14201 #define G_TERMP_A_HISTORY(x) (((x) >> S_TERMP_A_HISTORY) & M_TERMP_A_HISTORY)
14202 
14203 #define A_DBG_EFUSE_BYTE48_51 0x6140
14204 #define A_DBG_PVT_REG_HISTORY_TERMN 0x6144
14205 
14206 #define S_TERMN_B_HISTORY    4
14207 #define M_TERMN_B_HISTORY    0xfU
14208 #define V_TERMN_B_HISTORY(x) ((x) << S_TERMN_B_HISTORY)
14209 #define G_TERMN_B_HISTORY(x) (((x) >> S_TERMN_B_HISTORY) & M_TERMN_B_HISTORY)
14210 
14211 #define S_TERMN_A_HISTORY    0
14212 #define M_TERMN_A_HISTORY    0xfU
14213 #define V_TERMN_A_HISTORY(x) ((x) << S_TERMN_A_HISTORY)
14214 #define G_TERMN_A_HISTORY(x) (((x) >> S_TERMN_A_HISTORY) & M_TERMN_A_HISTORY)
14215 
14216 #define A_DBG_EFUSE_BYTE52_55 0x6144
14217 #define A_DBG_PVT_REG_HISTORY_DRVP 0x6148
14218 
14219 #define S_DRVP_B_HISTORY    4
14220 #define M_DRVP_B_HISTORY    0xfU
14221 #define V_DRVP_B_HISTORY(x) ((x) << S_DRVP_B_HISTORY)
14222 #define G_DRVP_B_HISTORY(x) (((x) >> S_DRVP_B_HISTORY) & M_DRVP_B_HISTORY)
14223 
14224 #define S_DRVP_A_HISTORY    0
14225 #define M_DRVP_A_HISTORY    0xfU
14226 #define V_DRVP_A_HISTORY(x) ((x) << S_DRVP_A_HISTORY)
14227 #define G_DRVP_A_HISTORY(x) (((x) >> S_DRVP_A_HISTORY) & M_DRVP_A_HISTORY)
14228 
14229 #define A_DBG_EFUSE_BYTE56_59 0x6148
14230 #define A_DBG_PVT_REG_HISTORY_DRVN 0x614c
14231 
14232 #define S_DRVN_B_HISTORY    4
14233 #define M_DRVN_B_HISTORY    0xfU
14234 #define V_DRVN_B_HISTORY(x) ((x) << S_DRVN_B_HISTORY)
14235 #define G_DRVN_B_HISTORY(x) (((x) >> S_DRVN_B_HISTORY) & M_DRVN_B_HISTORY)
14236 
14237 #define S_DRVN_A_HISTORY    0
14238 #define M_DRVN_A_HISTORY    0xfU
14239 #define V_DRVN_A_HISTORY(x) ((x) << S_DRVN_A_HISTORY)
14240 #define G_DRVN_A_HISTORY(x) (((x) >> S_DRVN_A_HISTORY) & M_DRVN_A_HISTORY)
14241 
14242 #define A_DBG_EFUSE_BYTE60_63 0x614c
14243 #define A_DBG_PVT_REG_SAMPLE_WAIT_CLKS 0x6150
14244 
14245 #define S_SAMPLE_WAIT_CLKS    0
14246 #define M_SAMPLE_WAIT_CLKS    0x1fU
14247 #define V_SAMPLE_WAIT_CLKS(x) ((x) << S_SAMPLE_WAIT_CLKS)
14248 #define G_SAMPLE_WAIT_CLKS(x) (((x) >> S_SAMPLE_WAIT_CLKS) & M_SAMPLE_WAIT_CLKS)
14249 
14250 #define A_DBG_STATIC_U_PLL_CONF6 0x6150
14251 
14252 #define S_STATIC_U_PLL_VREGTUNE    0
14253 #define M_STATIC_U_PLL_VREGTUNE    0x7ffffU
14254 #define V_STATIC_U_PLL_VREGTUNE(x) ((x) << S_STATIC_U_PLL_VREGTUNE)
14255 #define G_STATIC_U_PLL_VREGTUNE(x) (((x) >> S_STATIC_U_PLL_VREGTUNE) & M_STATIC_U_PLL_VREGTUNE)
14256 
14257 #define A_DBG_STATIC_C_PLL_CONF6 0x6154
14258 
14259 #define S_STATIC_C_PLL_VREGTUNE    0
14260 #define M_STATIC_C_PLL_VREGTUNE    0x7ffffU
14261 #define V_STATIC_C_PLL_VREGTUNE(x) ((x) << S_STATIC_C_PLL_VREGTUNE)
14262 #define G_STATIC_C_PLL_VREGTUNE(x) (((x) >> S_STATIC_C_PLL_VREGTUNE) & M_STATIC_C_PLL_VREGTUNE)
14263 
14264 #define A_DBG_CUST_EFUSE_PROGRAM 0x6158
14265 
14266 #define S_EFUSE_PROG_PERIOD    16
14267 #define M_EFUSE_PROG_PERIOD    0xffffU
14268 #define V_EFUSE_PROG_PERIOD(x) ((x) << S_EFUSE_PROG_PERIOD)
14269 #define G_EFUSE_PROG_PERIOD(x) (((x) >> S_EFUSE_PROG_PERIOD) & M_EFUSE_PROG_PERIOD)
14270 
14271 #define S_EFUSE_OPER_TYP    14
14272 #define M_EFUSE_OPER_TYP    0x3U
14273 #define V_EFUSE_OPER_TYP(x) ((x) << S_EFUSE_OPER_TYP)
14274 #define G_EFUSE_OPER_TYP(x) (((x) >> S_EFUSE_OPER_TYP) & M_EFUSE_OPER_TYP)
14275 
14276 #define S_EFUSE_ADDR    8
14277 #define M_EFUSE_ADDR    0x3fU
14278 #define V_EFUSE_ADDR(x) ((x) << S_EFUSE_ADDR)
14279 #define G_EFUSE_ADDR(x) (((x) >> S_EFUSE_ADDR) & M_EFUSE_ADDR)
14280 
14281 #define S_EFUSE_DIN    0
14282 #define M_EFUSE_DIN    0xffU
14283 #define V_EFUSE_DIN(x) ((x) << S_EFUSE_DIN)
14284 #define G_EFUSE_DIN(x) (((x) >> S_EFUSE_DIN) & M_EFUSE_DIN)
14285 
14286 #define A_DBG_CUST_EFUSE_OUT 0x615c
14287 
14288 #define S_EFUSE_OPER_DONE    8
14289 #define V_EFUSE_OPER_DONE(x) ((x) << S_EFUSE_OPER_DONE)
14290 #define F_EFUSE_OPER_DONE    V_EFUSE_OPER_DONE(1U)
14291 
14292 #define S_EFUSE_DOUT    0
14293 #define M_EFUSE_DOUT    0xffU
14294 #define V_EFUSE_DOUT(x) ((x) << S_EFUSE_DOUT)
14295 #define G_EFUSE_DOUT(x) (((x) >> S_EFUSE_DOUT) & M_EFUSE_DOUT)
14296 
14297 #define A_DBG_CUST_EFUSE_BYTE0_3 0x6160
14298 #define A_DBG_CUST_EFUSE_BYTE4_7 0x6164
14299 #define A_DBG_CUST_EFUSE_BYTE8_11 0x6168
14300 #define A_DBG_CUST_EFUSE_BYTE12_15 0x616c
14301 #define A_DBG_CUST_EFUSE_BYTE16_19 0x6170
14302 #define A_DBG_CUST_EFUSE_BYTE20_23 0x6174
14303 #define A_DBG_CUST_EFUSE_BYTE24_27 0x6178
14304 #define A_DBG_CUST_EFUSE_BYTE28_31 0x617c
14305 #define A_DBG_CUST_EFUSE_BYTE32_35 0x6180
14306 #define A_DBG_CUST_EFUSE_BYTE36_39 0x6184
14307 #define A_DBG_CUST_EFUSE_BYTE40_43 0x6188
14308 #define A_DBG_CUST_EFUSE_BYTE44_47 0x618c
14309 #define A_DBG_CUST_EFUSE_BYTE48_51 0x6190
14310 #define A_DBG_CUST_EFUSE_BYTE52_55 0x6194
14311 #define A_DBG_CUST_EFUSE_BYTE56_59 0x6198
14312 #define A_DBG_CUST_EFUSE_BYTE60_63 0x619c
14313 
14314 /* registers for module MC */
14315 #define MC_BASE_ADDR 0x6200
14316 
14317 #define A_MC_PCTL_SCFG 0x6200
14318 
14319 #define S_RKINF_EN    5
14320 #define V_RKINF_EN(x) ((x) << S_RKINF_EN)
14321 #define F_RKINF_EN    V_RKINF_EN(1U)
14322 
14323 #define S_DUAL_PCTL_EN    4
14324 #define V_DUAL_PCTL_EN(x) ((x) << S_DUAL_PCTL_EN)
14325 #define F_DUAL_PCTL_EN    V_DUAL_PCTL_EN(1U)
14326 
14327 #define S_SLAVE_MODE    3
14328 #define V_SLAVE_MODE(x) ((x) << S_SLAVE_MODE)
14329 #define F_SLAVE_MODE    V_SLAVE_MODE(1U)
14330 
14331 #define S_LOOPBACK_EN    1
14332 #define V_LOOPBACK_EN(x) ((x) << S_LOOPBACK_EN)
14333 #define F_LOOPBACK_EN    V_LOOPBACK_EN(1U)
14334 
14335 #define S_HW_LOW_POWER_EN    0
14336 #define V_HW_LOW_POWER_EN(x) ((x) << S_HW_LOW_POWER_EN)
14337 #define F_HW_LOW_POWER_EN    V_HW_LOW_POWER_EN(1U)
14338 
14339 #define A_MC_PCTL_SCTL 0x6204
14340 
14341 #define S_STATE_CMD    0
14342 #define M_STATE_CMD    0x7U
14343 #define V_STATE_CMD(x) ((x) << S_STATE_CMD)
14344 #define G_STATE_CMD(x) (((x) >> S_STATE_CMD) & M_STATE_CMD)
14345 
14346 #define A_MC_PCTL_STAT 0x6208
14347 
14348 #define S_CTL_STAT    0
14349 #define M_CTL_STAT    0x7U
14350 #define V_CTL_STAT(x) ((x) << S_CTL_STAT)
14351 #define G_CTL_STAT(x) (((x) >> S_CTL_STAT) & M_CTL_STAT)
14352 
14353 #define A_MC_PCTL_MCMD 0x6240
14354 
14355 #define S_START_CMD    31
14356 #define V_START_CMD(x) ((x) << S_START_CMD)
14357 #define F_START_CMD    V_START_CMD(1U)
14358 
14359 #define S_CMD_ADD_DEL    24
14360 #define M_CMD_ADD_DEL    0xfU
14361 #define V_CMD_ADD_DEL(x) ((x) << S_CMD_ADD_DEL)
14362 #define G_CMD_ADD_DEL(x) (((x) >> S_CMD_ADD_DEL) & M_CMD_ADD_DEL)
14363 
14364 #define S_RANK_SEL    20
14365 #define M_RANK_SEL    0xfU
14366 #define V_RANK_SEL(x) ((x) << S_RANK_SEL)
14367 #define G_RANK_SEL(x) (((x) >> S_RANK_SEL) & M_RANK_SEL)
14368 
14369 #define S_BANK_ADDR    17
14370 #define M_BANK_ADDR    0x7U
14371 #define V_BANK_ADDR(x) ((x) << S_BANK_ADDR)
14372 #define G_BANK_ADDR(x) (((x) >> S_BANK_ADDR) & M_BANK_ADDR)
14373 
14374 #define S_CMD_ADDR    4
14375 #define M_CMD_ADDR    0x1fffU
14376 #define V_CMD_ADDR(x) ((x) << S_CMD_ADDR)
14377 #define G_CMD_ADDR(x) (((x) >> S_CMD_ADDR) & M_CMD_ADDR)
14378 
14379 #define S_CMD_OPCODE    0
14380 #define M_CMD_OPCODE    0x7U
14381 #define V_CMD_OPCODE(x) ((x) << S_CMD_OPCODE)
14382 #define G_CMD_OPCODE(x) (((x) >> S_CMD_OPCODE) & M_CMD_OPCODE)
14383 
14384 #define A_MC_PCTL_POWCTL 0x6244
14385 
14386 #define S_POWER_UP_START    0
14387 #define V_POWER_UP_START(x) ((x) << S_POWER_UP_START)
14388 #define F_POWER_UP_START    V_POWER_UP_START(1U)
14389 
14390 #define A_MC_PCTL_POWSTAT 0x6248
14391 
14392 #define S_PHY_CALIBDONE    1
14393 #define V_PHY_CALIBDONE(x) ((x) << S_PHY_CALIBDONE)
14394 #define F_PHY_CALIBDONE    V_PHY_CALIBDONE(1U)
14395 
14396 #define S_POWER_UP_DONE    0
14397 #define V_POWER_UP_DONE(x) ((x) << S_POWER_UP_DONE)
14398 #define F_POWER_UP_DONE    V_POWER_UP_DONE(1U)
14399 
14400 #define A_MC_PCTL_MCFG 0x6280
14401 
14402 #define S_TFAW_CFG    18
14403 #define M_TFAW_CFG    0x3U
14404 #define V_TFAW_CFG(x) ((x) << S_TFAW_CFG)
14405 #define G_TFAW_CFG(x) (((x) >> S_TFAW_CFG) & M_TFAW_CFG)
14406 
14407 #define S_PD_EXIT_MODE    17
14408 #define V_PD_EXIT_MODE(x) ((x) << S_PD_EXIT_MODE)
14409 #define F_PD_EXIT_MODE    V_PD_EXIT_MODE(1U)
14410 
14411 #define S_PD_TYPE    16
14412 #define V_PD_TYPE(x) ((x) << S_PD_TYPE)
14413 #define F_PD_TYPE    V_PD_TYPE(1U)
14414 
14415 #define S_PD_IDLE    8
14416 #define M_PD_IDLE    0xffU
14417 #define V_PD_IDLE(x) ((x) << S_PD_IDLE)
14418 #define G_PD_IDLE(x) (((x) >> S_PD_IDLE) & M_PD_IDLE)
14419 
14420 #define S_PAGE_POLICY    6
14421 #define M_PAGE_POLICY    0x3U
14422 #define V_PAGE_POLICY(x) ((x) << S_PAGE_POLICY)
14423 #define G_PAGE_POLICY(x) (((x) >> S_PAGE_POLICY) & M_PAGE_POLICY)
14424 
14425 #define S_DDR3_EN    5
14426 #define V_DDR3_EN(x) ((x) << S_DDR3_EN)
14427 #define F_DDR3_EN    V_DDR3_EN(1U)
14428 
14429 #define S_TWO_T_EN    3
14430 #define V_TWO_T_EN(x) ((x) << S_TWO_T_EN)
14431 #define F_TWO_T_EN    V_TWO_T_EN(1U)
14432 
14433 #define S_BL8INT_EN    2
14434 #define V_BL8INT_EN(x) ((x) << S_BL8INT_EN)
14435 #define F_BL8INT_EN    V_BL8INT_EN(1U)
14436 
14437 #define S_MEM_BL    0
14438 #define V_MEM_BL(x) ((x) << S_MEM_BL)
14439 #define F_MEM_BL    V_MEM_BL(1U)
14440 
14441 #define A_MC_PCTL_PPCFG 0x6284
14442 
14443 #define S_RPMEM_DIS    1
14444 #define M_RPMEM_DIS    0xffU
14445 #define V_RPMEM_DIS(x) ((x) << S_RPMEM_DIS)
14446 #define G_RPMEM_DIS(x) (((x) >> S_RPMEM_DIS) & M_RPMEM_DIS)
14447 
14448 #define S_PPMEM_EN    0
14449 #define V_PPMEM_EN(x) ((x) << S_PPMEM_EN)
14450 #define F_PPMEM_EN    V_PPMEM_EN(1U)
14451 
14452 #define A_MC_PCTL_MSTAT 0x6288
14453 
14454 #define S_POWER_DOWN    0
14455 #define V_POWER_DOWN(x) ((x) << S_POWER_DOWN)
14456 #define F_POWER_DOWN    V_POWER_DOWN(1U)
14457 
14458 #define A_MC_PCTL_ODTCFG 0x628c
14459 
14460 #define S_RANK3_ODT_DEFAULT    28
14461 #define V_RANK3_ODT_DEFAULT(x) ((x) << S_RANK3_ODT_DEFAULT)
14462 #define F_RANK3_ODT_DEFAULT    V_RANK3_ODT_DEFAULT(1U)
14463 
14464 #define S_RANK3_ODT_WRITE_SEL    27
14465 #define V_RANK3_ODT_WRITE_SEL(x) ((x) << S_RANK3_ODT_WRITE_SEL)
14466 #define F_RANK3_ODT_WRITE_SEL    V_RANK3_ODT_WRITE_SEL(1U)
14467 
14468 #define S_RANK3_ODT_WRITE_NSE    26
14469 #define V_RANK3_ODT_WRITE_NSE(x) ((x) << S_RANK3_ODT_WRITE_NSE)
14470 #define F_RANK3_ODT_WRITE_NSE    V_RANK3_ODT_WRITE_NSE(1U)
14471 
14472 #define S_RANK3_ODT_READ_SEL    25
14473 #define V_RANK3_ODT_READ_SEL(x) ((x) << S_RANK3_ODT_READ_SEL)
14474 #define F_RANK3_ODT_READ_SEL    V_RANK3_ODT_READ_SEL(1U)
14475 
14476 #define S_RANK3_ODT_READ_NSEL    24
14477 #define V_RANK3_ODT_READ_NSEL(x) ((x) << S_RANK3_ODT_READ_NSEL)
14478 #define F_RANK3_ODT_READ_NSEL    V_RANK3_ODT_READ_NSEL(1U)
14479 
14480 #define S_RANK2_ODT_DEFAULT    20
14481 #define V_RANK2_ODT_DEFAULT(x) ((x) << S_RANK2_ODT_DEFAULT)
14482 #define F_RANK2_ODT_DEFAULT    V_RANK2_ODT_DEFAULT(1U)
14483 
14484 #define S_RANK2_ODT_WRITE_SEL    19
14485 #define V_RANK2_ODT_WRITE_SEL(x) ((x) << S_RANK2_ODT_WRITE_SEL)
14486 #define F_RANK2_ODT_WRITE_SEL    V_RANK2_ODT_WRITE_SEL(1U)
14487 
14488 #define S_RANK2_ODT_WRITE_NSEL    18
14489 #define V_RANK2_ODT_WRITE_NSEL(x) ((x) << S_RANK2_ODT_WRITE_NSEL)
14490 #define F_RANK2_ODT_WRITE_NSEL    V_RANK2_ODT_WRITE_NSEL(1U)
14491 
14492 #define S_RANK2_ODT_READ_SEL    17
14493 #define V_RANK2_ODT_READ_SEL(x) ((x) << S_RANK2_ODT_READ_SEL)
14494 #define F_RANK2_ODT_READ_SEL    V_RANK2_ODT_READ_SEL(1U)
14495 
14496 #define S_RANK2_ODT_READ_NSEL    16
14497 #define V_RANK2_ODT_READ_NSEL(x) ((x) << S_RANK2_ODT_READ_NSEL)
14498 #define F_RANK2_ODT_READ_NSEL    V_RANK2_ODT_READ_NSEL(1U)
14499 
14500 #define S_RANK1_ODT_DEFAULT    12
14501 #define V_RANK1_ODT_DEFAULT(x) ((x) << S_RANK1_ODT_DEFAULT)
14502 #define F_RANK1_ODT_DEFAULT    V_RANK1_ODT_DEFAULT(1U)
14503 
14504 #define S_RANK1_ODT_WRITE_SEL    11
14505 #define V_RANK1_ODT_WRITE_SEL(x) ((x) << S_RANK1_ODT_WRITE_SEL)
14506 #define F_RANK1_ODT_WRITE_SEL    V_RANK1_ODT_WRITE_SEL(1U)
14507 
14508 #define S_RANK1_ODT_WRITE_NSEL    10
14509 #define V_RANK1_ODT_WRITE_NSEL(x) ((x) << S_RANK1_ODT_WRITE_NSEL)
14510 #define F_RANK1_ODT_WRITE_NSEL    V_RANK1_ODT_WRITE_NSEL(1U)
14511 
14512 #define S_RANK1_ODT_READ_SEL    9
14513 #define V_RANK1_ODT_READ_SEL(x) ((x) << S_RANK1_ODT_READ_SEL)
14514 #define F_RANK1_ODT_READ_SEL    V_RANK1_ODT_READ_SEL(1U)
14515 
14516 #define S_RANK1_ODT_READ_NSEL    8
14517 #define V_RANK1_ODT_READ_NSEL(x) ((x) << S_RANK1_ODT_READ_NSEL)
14518 #define F_RANK1_ODT_READ_NSEL    V_RANK1_ODT_READ_NSEL(1U)
14519 
14520 #define S_RANK0_ODT_DEFAULT    4
14521 #define V_RANK0_ODT_DEFAULT(x) ((x) << S_RANK0_ODT_DEFAULT)
14522 #define F_RANK0_ODT_DEFAULT    V_RANK0_ODT_DEFAULT(1U)
14523 
14524 #define S_RANK0_ODT_WRITE_SEL    3
14525 #define V_RANK0_ODT_WRITE_SEL(x) ((x) << S_RANK0_ODT_WRITE_SEL)
14526 #define F_RANK0_ODT_WRITE_SEL    V_RANK0_ODT_WRITE_SEL(1U)
14527 
14528 #define S_RANK0_ODT_WRITE_NSEL    2
14529 #define V_RANK0_ODT_WRITE_NSEL(x) ((x) << S_RANK0_ODT_WRITE_NSEL)
14530 #define F_RANK0_ODT_WRITE_NSEL    V_RANK0_ODT_WRITE_NSEL(1U)
14531 
14532 #define S_RANK0_ODT_READ_SEL    1
14533 #define V_RANK0_ODT_READ_SEL(x) ((x) << S_RANK0_ODT_READ_SEL)
14534 #define F_RANK0_ODT_READ_SEL    V_RANK0_ODT_READ_SEL(1U)
14535 
14536 #define S_RANK0_ODT_READ_NSEL    0
14537 #define V_RANK0_ODT_READ_NSEL(x) ((x) << S_RANK0_ODT_READ_NSEL)
14538 #define F_RANK0_ODT_READ_NSEL    V_RANK0_ODT_READ_NSEL(1U)
14539 
14540 #define A_MC_PCTL_DQSECFG 0x6290
14541 
14542 #define S_DV_ALAT    20
14543 #define M_DV_ALAT    0xfU
14544 #define V_DV_ALAT(x) ((x) << S_DV_ALAT)
14545 #define G_DV_ALAT(x) (((x) >> S_DV_ALAT) & M_DV_ALAT)
14546 
14547 #define S_DV_ALEN    16
14548 #define M_DV_ALEN    0x3U
14549 #define V_DV_ALEN(x) ((x) << S_DV_ALEN)
14550 #define G_DV_ALEN(x) (((x) >> S_DV_ALEN) & M_DV_ALEN)
14551 
14552 #define S_DSE_ALAT    12
14553 #define M_DSE_ALAT    0xfU
14554 #define V_DSE_ALAT(x) ((x) << S_DSE_ALAT)
14555 #define G_DSE_ALAT(x) (((x) >> S_DSE_ALAT) & M_DSE_ALAT)
14556 
14557 #define S_DSE_ALEN    8
14558 #define M_DSE_ALEN    0x3U
14559 #define V_DSE_ALEN(x) ((x) << S_DSE_ALEN)
14560 #define G_DSE_ALEN(x) (((x) >> S_DSE_ALEN) & M_DSE_ALEN)
14561 
14562 #define S_QSE_ALAT    4
14563 #define M_QSE_ALAT    0xfU
14564 #define V_QSE_ALAT(x) ((x) << S_QSE_ALAT)
14565 #define G_QSE_ALAT(x) (((x) >> S_QSE_ALAT) & M_QSE_ALAT)
14566 
14567 #define S_QSE_ALEN    0
14568 #define M_QSE_ALEN    0x3U
14569 #define V_QSE_ALEN(x) ((x) << S_QSE_ALEN)
14570 #define G_QSE_ALEN(x) (((x) >> S_QSE_ALEN) & M_QSE_ALEN)
14571 
14572 #define A_MC_PCTL_DTUPDES 0x6294
14573 
14574 #define S_DTU_RD_MISSING    13
14575 #define V_DTU_RD_MISSING(x) ((x) << S_DTU_RD_MISSING)
14576 #define F_DTU_RD_MISSING    V_DTU_RD_MISSING(1U)
14577 
14578 #define S_DTU_EAFFL    9
14579 #define M_DTU_EAFFL    0xfU
14580 #define V_DTU_EAFFL(x) ((x) << S_DTU_EAFFL)
14581 #define G_DTU_EAFFL(x) (((x) >> S_DTU_EAFFL) & M_DTU_EAFFL)
14582 
14583 #define S_DTU_RANDOM_ERROR    8
14584 #define V_DTU_RANDOM_ERROR(x) ((x) << S_DTU_RANDOM_ERROR)
14585 #define F_DTU_RANDOM_ERROR    V_DTU_RANDOM_ERROR(1U)
14586 
14587 #define S_DTU_ERROR_B7    7
14588 #define V_DTU_ERROR_B7(x) ((x) << S_DTU_ERROR_B7)
14589 #define F_DTU_ERROR_B7    V_DTU_ERROR_B7(1U)
14590 
14591 #define S_DTU_ERR_B6    6
14592 #define V_DTU_ERR_B6(x) ((x) << S_DTU_ERR_B6)
14593 #define F_DTU_ERR_B6    V_DTU_ERR_B6(1U)
14594 
14595 #define S_DTU_ERR_B5    5
14596 #define V_DTU_ERR_B5(x) ((x) << S_DTU_ERR_B5)
14597 #define F_DTU_ERR_B5    V_DTU_ERR_B5(1U)
14598 
14599 #define S_DTU_ERR_B4    4
14600 #define V_DTU_ERR_B4(x) ((x) << S_DTU_ERR_B4)
14601 #define F_DTU_ERR_B4    V_DTU_ERR_B4(1U)
14602 
14603 #define S_DTU_ERR_B3    3
14604 #define V_DTU_ERR_B3(x) ((x) << S_DTU_ERR_B3)
14605 #define F_DTU_ERR_B3    V_DTU_ERR_B3(1U)
14606 
14607 #define S_DTU_ERR_B2    2
14608 #define V_DTU_ERR_B2(x) ((x) << S_DTU_ERR_B2)
14609 #define F_DTU_ERR_B2    V_DTU_ERR_B2(1U)
14610 
14611 #define S_DTU_ERR_B1    1
14612 #define V_DTU_ERR_B1(x) ((x) << S_DTU_ERR_B1)
14613 #define F_DTU_ERR_B1    V_DTU_ERR_B1(1U)
14614 
14615 #define S_DTU_ERR_B0    0
14616 #define V_DTU_ERR_B0(x) ((x) << S_DTU_ERR_B0)
14617 #define F_DTU_ERR_B0    V_DTU_ERR_B0(1U)
14618 
14619 #define A_MC_PCTL_DTUNA 0x6298
14620 #define A_MC_PCTL_DTUNE 0x629c
14621 #define A_MC_PCTL_DTUPRDO 0x62a0
14622 
14623 #define S_DTU_ALLBITS_1    16
14624 #define M_DTU_ALLBITS_1    0xffffU
14625 #define V_DTU_ALLBITS_1(x) ((x) << S_DTU_ALLBITS_1)
14626 #define G_DTU_ALLBITS_1(x) (((x) >> S_DTU_ALLBITS_1) & M_DTU_ALLBITS_1)
14627 
14628 #define S_DTU_ALLBITS_0    0
14629 #define M_DTU_ALLBITS_0    0xffffU
14630 #define V_DTU_ALLBITS_0(x) ((x) << S_DTU_ALLBITS_0)
14631 #define G_DTU_ALLBITS_0(x) (((x) >> S_DTU_ALLBITS_0) & M_DTU_ALLBITS_0)
14632 
14633 #define A_MC_PCTL_DTUPRD1 0x62a4
14634 
14635 #define S_DTU_ALLBITS_3    16
14636 #define M_DTU_ALLBITS_3    0xffffU
14637 #define V_DTU_ALLBITS_3(x) ((x) << S_DTU_ALLBITS_3)
14638 #define G_DTU_ALLBITS_3(x) (((x) >> S_DTU_ALLBITS_3) & M_DTU_ALLBITS_3)
14639 
14640 #define S_DTU_ALLBITS_2    0
14641 #define M_DTU_ALLBITS_2    0xffffU
14642 #define V_DTU_ALLBITS_2(x) ((x) << S_DTU_ALLBITS_2)
14643 #define G_DTU_ALLBITS_2(x) (((x) >> S_DTU_ALLBITS_2) & M_DTU_ALLBITS_2)
14644 
14645 #define A_MC_PCTL_DTUPRD2 0x62a8
14646 
14647 #define S_DTU_ALLBITS_5    16
14648 #define M_DTU_ALLBITS_5    0xffffU
14649 #define V_DTU_ALLBITS_5(x) ((x) << S_DTU_ALLBITS_5)
14650 #define G_DTU_ALLBITS_5(x) (((x) >> S_DTU_ALLBITS_5) & M_DTU_ALLBITS_5)
14651 
14652 #define S_DTU_ALLBITS_4    0
14653 #define M_DTU_ALLBITS_4    0xffffU
14654 #define V_DTU_ALLBITS_4(x) ((x) << S_DTU_ALLBITS_4)
14655 #define G_DTU_ALLBITS_4(x) (((x) >> S_DTU_ALLBITS_4) & M_DTU_ALLBITS_4)
14656 
14657 #define A_MC_PCTL_DTUPRD3 0x62ac
14658 
14659 #define S_DTU_ALLBITS_7    16
14660 #define M_DTU_ALLBITS_7    0xffffU
14661 #define V_DTU_ALLBITS_7(x) ((x) << S_DTU_ALLBITS_7)
14662 #define G_DTU_ALLBITS_7(x) (((x) >> S_DTU_ALLBITS_7) & M_DTU_ALLBITS_7)
14663 
14664 #define S_DTU_ALLBITS_6    0
14665 #define M_DTU_ALLBITS_6    0xffffU
14666 #define V_DTU_ALLBITS_6(x) ((x) << S_DTU_ALLBITS_6)
14667 #define G_DTU_ALLBITS_6(x) (((x) >> S_DTU_ALLBITS_6) & M_DTU_ALLBITS_6)
14668 
14669 #define A_MC_PCTL_DTUAWDT 0x62b0
14670 
14671 #define S_NUMBER_RANKS    9
14672 #define M_NUMBER_RANKS    0x3U
14673 #define V_NUMBER_RANKS(x) ((x) << S_NUMBER_RANKS)
14674 #define G_NUMBER_RANKS(x) (((x) >> S_NUMBER_RANKS) & M_NUMBER_RANKS)
14675 
14676 #define S_ROW_ADDR_WIDTH    6
14677 #define M_ROW_ADDR_WIDTH    0x3U
14678 #define V_ROW_ADDR_WIDTH(x) ((x) << S_ROW_ADDR_WIDTH)
14679 #define G_ROW_ADDR_WIDTH(x) (((x) >> S_ROW_ADDR_WIDTH) & M_ROW_ADDR_WIDTH)
14680 
14681 #define S_BANK_ADDR_WIDTH    3
14682 #define M_BANK_ADDR_WIDTH    0x3U
14683 #define V_BANK_ADDR_WIDTH(x) ((x) << S_BANK_ADDR_WIDTH)
14684 #define G_BANK_ADDR_WIDTH(x) (((x) >> S_BANK_ADDR_WIDTH) & M_BANK_ADDR_WIDTH)
14685 
14686 #define S_COLUMN_ADDR_WIDTH    0
14687 #define M_COLUMN_ADDR_WIDTH    0x3U
14688 #define V_COLUMN_ADDR_WIDTH(x) ((x) << S_COLUMN_ADDR_WIDTH)
14689 #define G_COLUMN_ADDR_WIDTH(x) (((x) >> S_COLUMN_ADDR_WIDTH) & M_COLUMN_ADDR_WIDTH)
14690 
14691 #define A_MC_PCTL_TOGCNT1U 0x62c0
14692 
14693 #define S_TOGGLE_COUNTER_1U    0
14694 #define M_TOGGLE_COUNTER_1U    0x3ffU
14695 #define V_TOGGLE_COUNTER_1U(x) ((x) << S_TOGGLE_COUNTER_1U)
14696 #define G_TOGGLE_COUNTER_1U(x) (((x) >> S_TOGGLE_COUNTER_1U) & M_TOGGLE_COUNTER_1U)
14697 
14698 #define A_MC_PCTL_TINIT 0x62c4
14699 
14700 #define S_T_INIT    0
14701 #define M_T_INIT    0x1ffU
14702 #define V_T_INIT(x) ((x) << S_T_INIT)
14703 #define G_T_INIT(x) (((x) >> S_T_INIT) & M_T_INIT)
14704 
14705 #define A_MC_PCTL_TRSTH 0x62c8
14706 
14707 #define S_T_RSTH    0
14708 #define M_T_RSTH    0x3ffU
14709 #define V_T_RSTH(x) ((x) << S_T_RSTH)
14710 #define G_T_RSTH(x) (((x) >> S_T_RSTH) & M_T_RSTH)
14711 
14712 #define A_MC_PCTL_TOGCNT100N 0x62cc
14713 
14714 #define S_TOGGLE_COUNTER_100N    0
14715 #define M_TOGGLE_COUNTER_100N    0x7fU
14716 #define V_TOGGLE_COUNTER_100N(x) ((x) << S_TOGGLE_COUNTER_100N)
14717 #define G_TOGGLE_COUNTER_100N(x) (((x) >> S_TOGGLE_COUNTER_100N) & M_TOGGLE_COUNTER_100N)
14718 
14719 #define A_MC_PCTL_TREFI 0x62d0
14720 
14721 #define S_T_REFI    0
14722 #define M_T_REFI    0xffU
14723 #define V_T_REFI(x) ((x) << S_T_REFI)
14724 #define G_T_REFI(x) (((x) >> S_T_REFI) & M_T_REFI)
14725 
14726 #define A_MC_PCTL_TMRD 0x62d4
14727 
14728 #define S_T_MRD    0
14729 #define M_T_MRD    0x7U
14730 #define V_T_MRD(x) ((x) << S_T_MRD)
14731 #define G_T_MRD(x) (((x) >> S_T_MRD) & M_T_MRD)
14732 
14733 #define A_MC_PCTL_TRFC 0x62d8
14734 
14735 #define S_T_RFC    0
14736 #define M_T_RFC    0xffU
14737 #define V_T_RFC(x) ((x) << S_T_RFC)
14738 #define G_T_RFC(x) (((x) >> S_T_RFC) & M_T_RFC)
14739 
14740 #define A_MC_PCTL_TRP 0x62dc
14741 
14742 #define S_T_RP    0
14743 #define M_T_RP    0xfU
14744 #define V_T_RP(x) ((x) << S_T_RP)
14745 #define G_T_RP(x) (((x) >> S_T_RP) & M_T_RP)
14746 
14747 #define A_MC_PCTL_TRTW 0x62e0
14748 
14749 #define S_T_RTW    0
14750 #define M_T_RTW    0x7U
14751 #define V_T_RTW(x) ((x) << S_T_RTW)
14752 #define G_T_RTW(x) (((x) >> S_T_RTW) & M_T_RTW)
14753 
14754 #define A_MC_PCTL_TAL 0x62e4
14755 
14756 #define S_T_AL    0
14757 #define M_T_AL    0xfU
14758 #define V_T_AL(x) ((x) << S_T_AL)
14759 #define G_T_AL(x) (((x) >> S_T_AL) & M_T_AL)
14760 
14761 #define A_MC_PCTL_TCL 0x62e8
14762 
14763 #define S_T_CL    0
14764 #define M_T_CL    0xfU
14765 #define V_T_CL(x) ((x) << S_T_CL)
14766 #define G_T_CL(x) (((x) >> S_T_CL) & M_T_CL)
14767 
14768 #define A_MC_PCTL_TCWL 0x62ec
14769 
14770 #define S_T_CWL    0
14771 #define M_T_CWL    0xfU
14772 #define V_T_CWL(x) ((x) << S_T_CWL)
14773 #define G_T_CWL(x) (((x) >> S_T_CWL) & M_T_CWL)
14774 
14775 #define A_MC_PCTL_TRAS 0x62f0
14776 
14777 #define S_T_RAS    0
14778 #define M_T_RAS    0x3fU
14779 #define V_T_RAS(x) ((x) << S_T_RAS)
14780 #define G_T_RAS(x) (((x) >> S_T_RAS) & M_T_RAS)
14781 
14782 #define A_MC_PCTL_TRC 0x62f4
14783 
14784 #define S_T_RC    0
14785 #define M_T_RC    0x3fU
14786 #define V_T_RC(x) ((x) << S_T_RC)
14787 #define G_T_RC(x) (((x) >> S_T_RC) & M_T_RC)
14788 
14789 #define A_MC_PCTL_TRCD 0x62f8
14790 
14791 #define S_T_RCD    0
14792 #define M_T_RCD    0xfU
14793 #define V_T_RCD(x) ((x) << S_T_RCD)
14794 #define G_T_RCD(x) (((x) >> S_T_RCD) & M_T_RCD)
14795 
14796 #define A_MC_PCTL_TRRD 0x62fc
14797 
14798 #define S_T_RRD    0
14799 #define M_T_RRD    0xfU
14800 #define V_T_RRD(x) ((x) << S_T_RRD)
14801 #define G_T_RRD(x) (((x) >> S_T_RRD) & M_T_RRD)
14802 
14803 #define A_MC_PCTL_TRTP 0x6300
14804 
14805 #define S_T_RTP    0
14806 #define M_T_RTP    0x7U
14807 #define V_T_RTP(x) ((x) << S_T_RTP)
14808 #define G_T_RTP(x) (((x) >> S_T_RTP) & M_T_RTP)
14809 
14810 #define A_MC_PCTL_TWR 0x6304
14811 
14812 #define S_T_WR    0
14813 #define M_T_WR    0x7U
14814 #define V_T_WR(x) ((x) << S_T_WR)
14815 #define G_T_WR(x) (((x) >> S_T_WR) & M_T_WR)
14816 
14817 #define A_MC_PCTL_TWTR 0x6308
14818 
14819 #define S_T_WTR    0
14820 #define M_T_WTR    0x7U
14821 #define V_T_WTR(x) ((x) << S_T_WTR)
14822 #define G_T_WTR(x) (((x) >> S_T_WTR) & M_T_WTR)
14823 
14824 #define A_MC_PCTL_TEXSR 0x630c
14825 
14826 #define S_T_EXSR    0
14827 #define M_T_EXSR    0x3ffU
14828 #define V_T_EXSR(x) ((x) << S_T_EXSR)
14829 #define G_T_EXSR(x) (((x) >> S_T_EXSR) & M_T_EXSR)
14830 
14831 #define A_MC_PCTL_TXP 0x6310
14832 
14833 #define S_T_XP    0
14834 #define M_T_XP    0x7U
14835 #define V_T_XP(x) ((x) << S_T_XP)
14836 #define G_T_XP(x) (((x) >> S_T_XP) & M_T_XP)
14837 
14838 #define A_MC_PCTL_TXPDLL 0x6314
14839 
14840 #define S_T_XPDLL    0
14841 #define M_T_XPDLL    0x3fU
14842 #define V_T_XPDLL(x) ((x) << S_T_XPDLL)
14843 #define G_T_XPDLL(x) (((x) >> S_T_XPDLL) & M_T_XPDLL)
14844 
14845 #define A_MC_PCTL_TZQCS 0x6318
14846 
14847 #define S_T_ZQCS    0
14848 #define M_T_ZQCS    0x7fU
14849 #define V_T_ZQCS(x) ((x) << S_T_ZQCS)
14850 #define G_T_ZQCS(x) (((x) >> S_T_ZQCS) & M_T_ZQCS)
14851 
14852 #define A_MC_PCTL_TZQCSI 0x631c
14853 
14854 #define S_T_ZQCSI    0
14855 #define M_T_ZQCSI    0xfffU
14856 #define V_T_ZQCSI(x) ((x) << S_T_ZQCSI)
14857 #define G_T_ZQCSI(x) (((x) >> S_T_ZQCSI) & M_T_ZQCSI)
14858 
14859 #define A_MC_PCTL_TDQS 0x6320
14860 
14861 #define S_T_DQS    0
14862 #define M_T_DQS    0x7U
14863 #define V_T_DQS(x) ((x) << S_T_DQS)
14864 #define G_T_DQS(x) (((x) >> S_T_DQS) & M_T_DQS)
14865 
14866 #define A_MC_PCTL_TCKSRE 0x6324
14867 
14868 #define S_T_CKSRE    0
14869 #define M_T_CKSRE    0xfU
14870 #define V_T_CKSRE(x) ((x) << S_T_CKSRE)
14871 #define G_T_CKSRE(x) (((x) >> S_T_CKSRE) & M_T_CKSRE)
14872 
14873 #define A_MC_PCTL_TCKSRX 0x6328
14874 
14875 #define S_T_CKSRX    0
14876 #define M_T_CKSRX    0xfU
14877 #define V_T_CKSRX(x) ((x) << S_T_CKSRX)
14878 #define G_T_CKSRX(x) (((x) >> S_T_CKSRX) & M_T_CKSRX)
14879 
14880 #define A_MC_PCTL_TCKE 0x632c
14881 
14882 #define S_T_CKE    0
14883 #define M_T_CKE    0x7U
14884 #define V_T_CKE(x) ((x) << S_T_CKE)
14885 #define G_T_CKE(x) (((x) >> S_T_CKE) & M_T_CKE)
14886 
14887 #define A_MC_PCTL_TMOD 0x6330
14888 
14889 #define S_T_MOD    0
14890 #define M_T_MOD    0xfU
14891 #define V_T_MOD(x) ((x) << S_T_MOD)
14892 #define G_T_MOD(x) (((x) >> S_T_MOD) & M_T_MOD)
14893 
14894 #define A_MC_PCTL_TRSTL 0x6334
14895 
14896 #define S_RSTHOLD    0
14897 #define M_RSTHOLD    0x7fU
14898 #define V_RSTHOLD(x) ((x) << S_RSTHOLD)
14899 #define G_RSTHOLD(x) (((x) >> S_RSTHOLD) & M_RSTHOLD)
14900 
14901 #define A_MC_PCTL_TZQCL 0x6338
14902 
14903 #define S_T_ZQCL    0
14904 #define M_T_ZQCL    0x3ffU
14905 #define V_T_ZQCL(x) ((x) << S_T_ZQCL)
14906 #define G_T_ZQCL(x) (((x) >> S_T_ZQCL) & M_T_ZQCL)
14907 
14908 #define A_MC_PCTL_DWLCFG0 0x6370
14909 
14910 #define S_T_ADWL_VEC    0
14911 #define M_T_ADWL_VEC    0x1ffU
14912 #define V_T_ADWL_VEC(x) ((x) << S_T_ADWL_VEC)
14913 #define G_T_ADWL_VEC(x) (((x) >> S_T_ADWL_VEC) & M_T_ADWL_VEC)
14914 
14915 #define A_MC_PCTL_DWLCFG1 0x6374
14916 #define A_MC_PCTL_DWLCFG2 0x6378
14917 #define A_MC_PCTL_DWLCFG3 0x637c
14918 #define A_MC_PCTL_ECCCFG 0x6380
14919 
14920 #define S_INLINE_SYN_EN    4
14921 #define V_INLINE_SYN_EN(x) ((x) << S_INLINE_SYN_EN)
14922 #define F_INLINE_SYN_EN    V_INLINE_SYN_EN(1U)
14923 
14924 #define S_ECC_EN    3
14925 #define V_ECC_EN(x) ((x) << S_ECC_EN)
14926 #define F_ECC_EN    V_ECC_EN(1U)
14927 
14928 #define S_ECC_INTR_EN    2
14929 #define V_ECC_INTR_EN(x) ((x) << S_ECC_INTR_EN)
14930 #define F_ECC_INTR_EN    V_ECC_INTR_EN(1U)
14931 
14932 #define A_MC_PCTL_ECCTST 0x6384
14933 
14934 #define S_ECC_TEST_MASK    0
14935 #define M_ECC_TEST_MASK    0xffU
14936 #define V_ECC_TEST_MASK(x) ((x) << S_ECC_TEST_MASK)
14937 #define G_ECC_TEST_MASK(x) (((x) >> S_ECC_TEST_MASK) & M_ECC_TEST_MASK)
14938 
14939 #define A_MC_PCTL_ECCCLR 0x6388
14940 
14941 #define S_CLR_ECC_LOG    1
14942 #define V_CLR_ECC_LOG(x) ((x) << S_CLR_ECC_LOG)
14943 #define F_CLR_ECC_LOG    V_CLR_ECC_LOG(1U)
14944 
14945 #define S_CLR_ECC_INTR    0
14946 #define V_CLR_ECC_INTR(x) ((x) << S_CLR_ECC_INTR)
14947 #define F_CLR_ECC_INTR    V_CLR_ECC_INTR(1U)
14948 
14949 #define A_MC_PCTL_ECCLOG 0x638c
14950 #define A_MC_PCTL_DTUWACTL 0x6400
14951 
14952 #define S_DTU_WR_RANK    30
14953 #define M_DTU_WR_RANK    0x3U
14954 #define V_DTU_WR_RANK(x) ((x) << S_DTU_WR_RANK)
14955 #define G_DTU_WR_RANK(x) (((x) >> S_DTU_WR_RANK) & M_DTU_WR_RANK)
14956 
14957 #define S_DTU_WR_ROW    13
14958 #define M_DTU_WR_ROW    0x1ffffU
14959 #define V_DTU_WR_ROW(x) ((x) << S_DTU_WR_ROW)
14960 #define G_DTU_WR_ROW(x) (((x) >> S_DTU_WR_ROW) & M_DTU_WR_ROW)
14961 
14962 #define S_DTU_WR_BANK    10
14963 #define M_DTU_WR_BANK    0x7U
14964 #define V_DTU_WR_BANK(x) ((x) << S_DTU_WR_BANK)
14965 #define G_DTU_WR_BANK(x) (((x) >> S_DTU_WR_BANK) & M_DTU_WR_BANK)
14966 
14967 #define S_DTU_WR_COL    0
14968 #define M_DTU_WR_COL    0x3ffU
14969 #define V_DTU_WR_COL(x) ((x) << S_DTU_WR_COL)
14970 #define G_DTU_WR_COL(x) (((x) >> S_DTU_WR_COL) & M_DTU_WR_COL)
14971 
14972 #define A_MC_PCTL_DTURACTL 0x6404
14973 
14974 #define S_DTU_RD_RANK    30
14975 #define M_DTU_RD_RANK    0x3U
14976 #define V_DTU_RD_RANK(x) ((x) << S_DTU_RD_RANK)
14977 #define G_DTU_RD_RANK(x) (((x) >> S_DTU_RD_RANK) & M_DTU_RD_RANK)
14978 
14979 #define S_DTU_RD_ROW    13
14980 #define M_DTU_RD_ROW    0x1ffffU
14981 #define V_DTU_RD_ROW(x) ((x) << S_DTU_RD_ROW)
14982 #define G_DTU_RD_ROW(x) (((x) >> S_DTU_RD_ROW) & M_DTU_RD_ROW)
14983 
14984 #define S_DTU_RD_BANK    10
14985 #define M_DTU_RD_BANK    0x7U
14986 #define V_DTU_RD_BANK(x) ((x) << S_DTU_RD_BANK)
14987 #define G_DTU_RD_BANK(x) (((x) >> S_DTU_RD_BANK) & M_DTU_RD_BANK)
14988 
14989 #define S_DTU_RD_COL    0
14990 #define M_DTU_RD_COL    0x3ffU
14991 #define V_DTU_RD_COL(x) ((x) << S_DTU_RD_COL)
14992 #define G_DTU_RD_COL(x) (((x) >> S_DTU_RD_COL) & M_DTU_RD_COL)
14993 
14994 #define A_MC_PCTL_DTUCFG 0x6408
14995 
14996 #define S_DTU_ROW_INCREMENTS    16
14997 #define M_DTU_ROW_INCREMENTS    0x7fU
14998 #define V_DTU_ROW_INCREMENTS(x) ((x) << S_DTU_ROW_INCREMENTS)
14999 #define G_DTU_ROW_INCREMENTS(x) (((x) >> S_DTU_ROW_INCREMENTS) & M_DTU_ROW_INCREMENTS)
15000 
15001 #define S_DTU_WR_MULTI_RD    15
15002 #define V_DTU_WR_MULTI_RD(x) ((x) << S_DTU_WR_MULTI_RD)
15003 #define F_DTU_WR_MULTI_RD    V_DTU_WR_MULTI_RD(1U)
15004 
15005 #define S_DTU_DATA_MASK_EN    14
15006 #define V_DTU_DATA_MASK_EN(x) ((x) << S_DTU_DATA_MASK_EN)
15007 #define F_DTU_DATA_MASK_EN    V_DTU_DATA_MASK_EN(1U)
15008 
15009 #define S_DTU_TARGET_LANE    10
15010 #define M_DTU_TARGET_LANE    0xfU
15011 #define V_DTU_TARGET_LANE(x) ((x) << S_DTU_TARGET_LANE)
15012 #define G_DTU_TARGET_LANE(x) (((x) >> S_DTU_TARGET_LANE) & M_DTU_TARGET_LANE)
15013 
15014 #define S_DTU_GENERATE_RANDOM    9
15015 #define V_DTU_GENERATE_RANDOM(x) ((x) << S_DTU_GENERATE_RANDOM)
15016 #define F_DTU_GENERATE_RANDOM    V_DTU_GENERATE_RANDOM(1U)
15017 
15018 #define S_DTU_INCR_BANKS    8
15019 #define V_DTU_INCR_BANKS(x) ((x) << S_DTU_INCR_BANKS)
15020 #define F_DTU_INCR_BANKS    V_DTU_INCR_BANKS(1U)
15021 
15022 #define S_DTU_INCR_COLS    7
15023 #define V_DTU_INCR_COLS(x) ((x) << S_DTU_INCR_COLS)
15024 #define F_DTU_INCR_COLS    V_DTU_INCR_COLS(1U)
15025 
15026 #define S_DTU_NALEN    1
15027 #define M_DTU_NALEN    0x3fU
15028 #define V_DTU_NALEN(x) ((x) << S_DTU_NALEN)
15029 #define G_DTU_NALEN(x) (((x) >> S_DTU_NALEN) & M_DTU_NALEN)
15030 
15031 #define S_DTU_ENABLE    0
15032 #define V_DTU_ENABLE(x) ((x) << S_DTU_ENABLE)
15033 #define F_DTU_ENABLE    V_DTU_ENABLE(1U)
15034 
15035 #define A_MC_PCTL_DTUECTL 0x640c
15036 
15037 #define S_WR_MULTI_RD_RST    2
15038 #define V_WR_MULTI_RD_RST(x) ((x) << S_WR_MULTI_RD_RST)
15039 #define F_WR_MULTI_RD_RST    V_WR_MULTI_RD_RST(1U)
15040 
15041 #define S_RUN_ERROR_REPORTS    1
15042 #define V_RUN_ERROR_REPORTS(x) ((x) << S_RUN_ERROR_REPORTS)
15043 #define F_RUN_ERROR_REPORTS    V_RUN_ERROR_REPORTS(1U)
15044 
15045 #define S_RUN_DTU    0
15046 #define V_RUN_DTU(x) ((x) << S_RUN_DTU)
15047 #define F_RUN_DTU    V_RUN_DTU(1U)
15048 
15049 #define A_MC_PCTL_DTUWD0 0x6410
15050 
15051 #define S_DTU_WR_BYTE3    24
15052 #define M_DTU_WR_BYTE3    0xffU
15053 #define V_DTU_WR_BYTE3(x) ((x) << S_DTU_WR_BYTE3)
15054 #define G_DTU_WR_BYTE3(x) (((x) >> S_DTU_WR_BYTE3) & M_DTU_WR_BYTE3)
15055 
15056 #define S_DTU_WR_BYTE2    16
15057 #define M_DTU_WR_BYTE2    0xffU
15058 #define V_DTU_WR_BYTE2(x) ((x) << S_DTU_WR_BYTE2)
15059 #define G_DTU_WR_BYTE2(x) (((x) >> S_DTU_WR_BYTE2) & M_DTU_WR_BYTE2)
15060 
15061 #define S_DTU_WR_BYTE1    8
15062 #define M_DTU_WR_BYTE1    0xffU
15063 #define V_DTU_WR_BYTE1(x) ((x) << S_DTU_WR_BYTE1)
15064 #define G_DTU_WR_BYTE1(x) (((x) >> S_DTU_WR_BYTE1) & M_DTU_WR_BYTE1)
15065 
15066 #define S_DTU_WR_BYTE0    0
15067 #define M_DTU_WR_BYTE0    0xffU
15068 #define V_DTU_WR_BYTE0(x) ((x) << S_DTU_WR_BYTE0)
15069 #define G_DTU_WR_BYTE0(x) (((x) >> S_DTU_WR_BYTE0) & M_DTU_WR_BYTE0)
15070 
15071 #define A_MC_PCTL_DTUWD1 0x6414
15072 
15073 #define S_DTU_WR_BYTE7    24
15074 #define M_DTU_WR_BYTE7    0xffU
15075 #define V_DTU_WR_BYTE7(x) ((x) << S_DTU_WR_BYTE7)
15076 #define G_DTU_WR_BYTE7(x) (((x) >> S_DTU_WR_BYTE7) & M_DTU_WR_BYTE7)
15077 
15078 #define S_DTU_WR_BYTE6    16
15079 #define M_DTU_WR_BYTE6    0xffU
15080 #define V_DTU_WR_BYTE6(x) ((x) << S_DTU_WR_BYTE6)
15081 #define G_DTU_WR_BYTE6(x) (((x) >> S_DTU_WR_BYTE6) & M_DTU_WR_BYTE6)
15082 
15083 #define S_DTU_WR_BYTE5    8
15084 #define M_DTU_WR_BYTE5    0xffU
15085 #define V_DTU_WR_BYTE5(x) ((x) << S_DTU_WR_BYTE5)
15086 #define G_DTU_WR_BYTE5(x) (((x) >> S_DTU_WR_BYTE5) & M_DTU_WR_BYTE5)
15087 
15088 #define S_DTU_WR_BYTE4    0
15089 #define M_DTU_WR_BYTE4    0xffU
15090 #define V_DTU_WR_BYTE4(x) ((x) << S_DTU_WR_BYTE4)
15091 #define G_DTU_WR_BYTE4(x) (((x) >> S_DTU_WR_BYTE4) & M_DTU_WR_BYTE4)
15092 
15093 #define A_MC_PCTL_DTUWD2 0x6418
15094 
15095 #define S_DTU_WR_BYTE11    24
15096 #define M_DTU_WR_BYTE11    0xffU
15097 #define V_DTU_WR_BYTE11(x) ((x) << S_DTU_WR_BYTE11)
15098 #define G_DTU_WR_BYTE11(x) (((x) >> S_DTU_WR_BYTE11) & M_DTU_WR_BYTE11)
15099 
15100 #define S_DTU_WR_BYTE10    16
15101 #define M_DTU_WR_BYTE10    0xffU
15102 #define V_DTU_WR_BYTE10(x) ((x) << S_DTU_WR_BYTE10)
15103 #define G_DTU_WR_BYTE10(x) (((x) >> S_DTU_WR_BYTE10) & M_DTU_WR_BYTE10)
15104 
15105 #define S_DTU_WR_BYTE9    8
15106 #define M_DTU_WR_BYTE9    0xffU
15107 #define V_DTU_WR_BYTE9(x) ((x) << S_DTU_WR_BYTE9)
15108 #define G_DTU_WR_BYTE9(x) (((x) >> S_DTU_WR_BYTE9) & M_DTU_WR_BYTE9)
15109 
15110 #define S_DTU_WR_BYTE8    0
15111 #define M_DTU_WR_BYTE8    0xffU
15112 #define V_DTU_WR_BYTE8(x) ((x) << S_DTU_WR_BYTE8)
15113 #define G_DTU_WR_BYTE8(x) (((x) >> S_DTU_WR_BYTE8) & M_DTU_WR_BYTE8)
15114 
15115 #define A_MC_PCTL_DTUWD3 0x641c
15116 
15117 #define S_DTU_WR_BYTE15    24
15118 #define M_DTU_WR_BYTE15    0xffU
15119 #define V_DTU_WR_BYTE15(x) ((x) << S_DTU_WR_BYTE15)
15120 #define G_DTU_WR_BYTE15(x) (((x) >> S_DTU_WR_BYTE15) & M_DTU_WR_BYTE15)
15121 
15122 #define S_DTU_WR_BYTE14    16
15123 #define M_DTU_WR_BYTE14    0xffU
15124 #define V_DTU_WR_BYTE14(x) ((x) << S_DTU_WR_BYTE14)
15125 #define G_DTU_WR_BYTE14(x) (((x) >> S_DTU_WR_BYTE14) & M_DTU_WR_BYTE14)
15126 
15127 #define S_DTU_WR_BYTE13    8
15128 #define M_DTU_WR_BYTE13    0xffU
15129 #define V_DTU_WR_BYTE13(x) ((x) << S_DTU_WR_BYTE13)
15130 #define G_DTU_WR_BYTE13(x) (((x) >> S_DTU_WR_BYTE13) & M_DTU_WR_BYTE13)
15131 
15132 #define S_DTU_WR_BYTE12    0
15133 #define M_DTU_WR_BYTE12    0xffU
15134 #define V_DTU_WR_BYTE12(x) ((x) << S_DTU_WR_BYTE12)
15135 #define G_DTU_WR_BYTE12(x) (((x) >> S_DTU_WR_BYTE12) & M_DTU_WR_BYTE12)
15136 
15137 #define A_MC_PCTL_DTUWDM 0x6420
15138 
15139 #define S_DM_WR_BYTE0    0
15140 #define M_DM_WR_BYTE0    0xffffU
15141 #define V_DM_WR_BYTE0(x) ((x) << S_DM_WR_BYTE0)
15142 #define G_DM_WR_BYTE0(x) (((x) >> S_DM_WR_BYTE0) & M_DM_WR_BYTE0)
15143 
15144 #define A_MC_PCTL_DTURD0 0x6424
15145 
15146 #define S_DTU_RD_BYTE3    24
15147 #define M_DTU_RD_BYTE3    0xffU
15148 #define V_DTU_RD_BYTE3(x) ((x) << S_DTU_RD_BYTE3)
15149 #define G_DTU_RD_BYTE3(x) (((x) >> S_DTU_RD_BYTE3) & M_DTU_RD_BYTE3)
15150 
15151 #define S_DTU_RD_BYTE2    16
15152 #define M_DTU_RD_BYTE2    0xffU
15153 #define V_DTU_RD_BYTE2(x) ((x) << S_DTU_RD_BYTE2)
15154 #define G_DTU_RD_BYTE2(x) (((x) >> S_DTU_RD_BYTE2) & M_DTU_RD_BYTE2)
15155 
15156 #define S_DTU_RD_BYTE1    8
15157 #define M_DTU_RD_BYTE1    0xffU
15158 #define V_DTU_RD_BYTE1(x) ((x) << S_DTU_RD_BYTE1)
15159 #define G_DTU_RD_BYTE1(x) (((x) >> S_DTU_RD_BYTE1) & M_DTU_RD_BYTE1)
15160 
15161 #define S_DTU_RD_BYTE0    0
15162 #define M_DTU_RD_BYTE0    0xffU
15163 #define V_DTU_RD_BYTE0(x) ((x) << S_DTU_RD_BYTE0)
15164 #define G_DTU_RD_BYTE0(x) (((x) >> S_DTU_RD_BYTE0) & M_DTU_RD_BYTE0)
15165 
15166 #define A_MC_PCTL_DTURD1 0x6428
15167 
15168 #define S_DTU_RD_BYTE7    24
15169 #define M_DTU_RD_BYTE7    0xffU
15170 #define V_DTU_RD_BYTE7(x) ((x) << S_DTU_RD_BYTE7)
15171 #define G_DTU_RD_BYTE7(x) (((x) >> S_DTU_RD_BYTE7) & M_DTU_RD_BYTE7)
15172 
15173 #define S_DTU_RD_BYTE6    16
15174 #define M_DTU_RD_BYTE6    0xffU
15175 #define V_DTU_RD_BYTE6(x) ((x) << S_DTU_RD_BYTE6)
15176 #define G_DTU_RD_BYTE6(x) (((x) >> S_DTU_RD_BYTE6) & M_DTU_RD_BYTE6)
15177 
15178 #define S_DTU_RD_BYTE5    8
15179 #define M_DTU_RD_BYTE5    0xffU
15180 #define V_DTU_RD_BYTE5(x) ((x) << S_DTU_RD_BYTE5)
15181 #define G_DTU_RD_BYTE5(x) (((x) >> S_DTU_RD_BYTE5) & M_DTU_RD_BYTE5)
15182 
15183 #define S_DTU_RD_BYTE4    0
15184 #define M_DTU_RD_BYTE4    0xffU
15185 #define V_DTU_RD_BYTE4(x) ((x) << S_DTU_RD_BYTE4)
15186 #define G_DTU_RD_BYTE4(x) (((x) >> S_DTU_RD_BYTE4) & M_DTU_RD_BYTE4)
15187 
15188 #define A_MC_PCTL_DTURD2 0x642c
15189 
15190 #define S_DTU_RD_BYTE11    24
15191 #define M_DTU_RD_BYTE11    0xffU
15192 #define V_DTU_RD_BYTE11(x) ((x) << S_DTU_RD_BYTE11)
15193 #define G_DTU_RD_BYTE11(x) (((x) >> S_DTU_RD_BYTE11) & M_DTU_RD_BYTE11)
15194 
15195 #define S_DTU_RD_BYTE10    16
15196 #define M_DTU_RD_BYTE10    0xffU
15197 #define V_DTU_RD_BYTE10(x) ((x) << S_DTU_RD_BYTE10)
15198 #define G_DTU_RD_BYTE10(x) (((x) >> S_DTU_RD_BYTE10) & M_DTU_RD_BYTE10)
15199 
15200 #define S_DTU_RD_BYTE9    8
15201 #define M_DTU_RD_BYTE9    0xffU
15202 #define V_DTU_RD_BYTE9(x) ((x) << S_DTU_RD_BYTE9)
15203 #define G_DTU_RD_BYTE9(x) (((x) >> S_DTU_RD_BYTE9) & M_DTU_RD_BYTE9)
15204 
15205 #define S_DTU_RD_BYTE8    0
15206 #define M_DTU_RD_BYTE8    0xffU
15207 #define V_DTU_RD_BYTE8(x) ((x) << S_DTU_RD_BYTE8)
15208 #define G_DTU_RD_BYTE8(x) (((x) >> S_DTU_RD_BYTE8) & M_DTU_RD_BYTE8)
15209 
15210 #define A_MC_PCTL_DTURD3 0x6430
15211 
15212 #define S_DTU_RD_BYTE15    24
15213 #define M_DTU_RD_BYTE15    0xffU
15214 #define V_DTU_RD_BYTE15(x) ((x) << S_DTU_RD_BYTE15)
15215 #define G_DTU_RD_BYTE15(x) (((x) >> S_DTU_RD_BYTE15) & M_DTU_RD_BYTE15)
15216 
15217 #define S_DTU_RD_BYTE14    16
15218 #define M_DTU_RD_BYTE14    0xffU
15219 #define V_DTU_RD_BYTE14(x) ((x) << S_DTU_RD_BYTE14)
15220 #define G_DTU_RD_BYTE14(x) (((x) >> S_DTU_RD_BYTE14) & M_DTU_RD_BYTE14)
15221 
15222 #define S_DTU_RD_BYTE13    8
15223 #define M_DTU_RD_BYTE13    0xffU
15224 #define V_DTU_RD_BYTE13(x) ((x) << S_DTU_RD_BYTE13)
15225 #define G_DTU_RD_BYTE13(x) (((x) >> S_DTU_RD_BYTE13) & M_DTU_RD_BYTE13)
15226 
15227 #define S_DTU_RD_BYTE12    0
15228 #define M_DTU_RD_BYTE12    0xffU
15229 #define V_DTU_RD_BYTE12(x) ((x) << S_DTU_RD_BYTE12)
15230 #define G_DTU_RD_BYTE12(x) (((x) >> S_DTU_RD_BYTE12) & M_DTU_RD_BYTE12)
15231 
15232 #define A_MC_DTULFSRWD 0x6434
15233 #define A_MC_PCTL_DTULFSRRD 0x6438
15234 #define A_MC_PCTL_DTUEAF 0x643c
15235 
15236 #define S_EA_RANK    30
15237 #define M_EA_RANK    0x3U
15238 #define V_EA_RANK(x) ((x) << S_EA_RANK)
15239 #define G_EA_RANK(x) (((x) >> S_EA_RANK) & M_EA_RANK)
15240 
15241 #define S_EA_ROW    13
15242 #define M_EA_ROW    0x1ffffU
15243 #define V_EA_ROW(x) ((x) << S_EA_ROW)
15244 #define G_EA_ROW(x) (((x) >> S_EA_ROW) & M_EA_ROW)
15245 
15246 #define S_EA_BANK    10
15247 #define M_EA_BANK    0x7U
15248 #define V_EA_BANK(x) ((x) << S_EA_BANK)
15249 #define G_EA_BANK(x) (((x) >> S_EA_BANK) & M_EA_BANK)
15250 
15251 #define S_EA_COLUMN    0
15252 #define M_EA_COLUMN    0x3ffU
15253 #define V_EA_COLUMN(x) ((x) << S_EA_COLUMN)
15254 #define G_EA_COLUMN(x) (((x) >> S_EA_COLUMN) & M_EA_COLUMN)
15255 
15256 #define A_MC_PCTL_PHYPVTCFG 0x6500
15257 
15258 #define S_PVT_UPD_REQ_EN    15
15259 #define V_PVT_UPD_REQ_EN(x) ((x) << S_PVT_UPD_REQ_EN)
15260 #define F_PVT_UPD_REQ_EN    V_PVT_UPD_REQ_EN(1U)
15261 
15262 #define S_PVT_UPD_TRIG_POL    14
15263 #define V_PVT_UPD_TRIG_POL(x) ((x) << S_PVT_UPD_TRIG_POL)
15264 #define F_PVT_UPD_TRIG_POL    V_PVT_UPD_TRIG_POL(1U)
15265 
15266 #define S_PVT_UPD_TRIG_TYPE    12
15267 #define V_PVT_UPD_TRIG_TYPE(x) ((x) << S_PVT_UPD_TRIG_TYPE)
15268 #define F_PVT_UPD_TRIG_TYPE    V_PVT_UPD_TRIG_TYPE(1U)
15269 
15270 #define S_PVT_UPD_DONE_POL    10
15271 #define V_PVT_UPD_DONE_POL(x) ((x) << S_PVT_UPD_DONE_POL)
15272 #define F_PVT_UPD_DONE_POL    V_PVT_UPD_DONE_POL(1U)
15273 
15274 #define S_PVT_UPD_DONE_TYPE    8
15275 #define M_PVT_UPD_DONE_TYPE    0x3U
15276 #define V_PVT_UPD_DONE_TYPE(x) ((x) << S_PVT_UPD_DONE_TYPE)
15277 #define G_PVT_UPD_DONE_TYPE(x) (((x) >> S_PVT_UPD_DONE_TYPE) & M_PVT_UPD_DONE_TYPE)
15278 
15279 #define S_PHY_UPD_REQ_EN    7
15280 #define V_PHY_UPD_REQ_EN(x) ((x) << S_PHY_UPD_REQ_EN)
15281 #define F_PHY_UPD_REQ_EN    V_PHY_UPD_REQ_EN(1U)
15282 
15283 #define S_PHY_UPD_TRIG_POL    6
15284 #define V_PHY_UPD_TRIG_POL(x) ((x) << S_PHY_UPD_TRIG_POL)
15285 #define F_PHY_UPD_TRIG_POL    V_PHY_UPD_TRIG_POL(1U)
15286 
15287 #define S_PHY_UPD_TRIG_TYPE    4
15288 #define V_PHY_UPD_TRIG_TYPE(x) ((x) << S_PHY_UPD_TRIG_TYPE)
15289 #define F_PHY_UPD_TRIG_TYPE    V_PHY_UPD_TRIG_TYPE(1U)
15290 
15291 #define S_PHY_UPD_DONE_POL    2
15292 #define V_PHY_UPD_DONE_POL(x) ((x) << S_PHY_UPD_DONE_POL)
15293 #define F_PHY_UPD_DONE_POL    V_PHY_UPD_DONE_POL(1U)
15294 
15295 #define S_PHY_UPD_DONE_TYPE    0
15296 #define M_PHY_UPD_DONE_TYPE    0x3U
15297 #define V_PHY_UPD_DONE_TYPE(x) ((x) << S_PHY_UPD_DONE_TYPE)
15298 #define G_PHY_UPD_DONE_TYPE(x) (((x) >> S_PHY_UPD_DONE_TYPE) & M_PHY_UPD_DONE_TYPE)
15299 
15300 #define A_MC_PCTL_PHYPVTSTAT 0x6504
15301 
15302 #define S_I_PVT_UPD_TRIG    5
15303 #define V_I_PVT_UPD_TRIG(x) ((x) << S_I_PVT_UPD_TRIG)
15304 #define F_I_PVT_UPD_TRIG    V_I_PVT_UPD_TRIG(1U)
15305 
15306 #define S_I_PVT_UPD_DONE    4
15307 #define V_I_PVT_UPD_DONE(x) ((x) << S_I_PVT_UPD_DONE)
15308 #define F_I_PVT_UPD_DONE    V_I_PVT_UPD_DONE(1U)
15309 
15310 #define S_I_PHY_UPD_TRIG    1
15311 #define V_I_PHY_UPD_TRIG(x) ((x) << S_I_PHY_UPD_TRIG)
15312 #define F_I_PHY_UPD_TRIG    V_I_PHY_UPD_TRIG(1U)
15313 
15314 #define S_I_PHY_UPD_DONE    0
15315 #define V_I_PHY_UPD_DONE(x) ((x) << S_I_PHY_UPD_DONE)
15316 #define F_I_PHY_UPD_DONE    V_I_PHY_UPD_DONE(1U)
15317 
15318 #define A_MC_PCTL_PHYTUPDON 0x6508
15319 
15320 #define S_PHY_T_UPDON    0
15321 #define M_PHY_T_UPDON    0xffU
15322 #define V_PHY_T_UPDON(x) ((x) << S_PHY_T_UPDON)
15323 #define G_PHY_T_UPDON(x) (((x) >> S_PHY_T_UPDON) & M_PHY_T_UPDON)
15324 
15325 #define A_MC_PCTL_PHYTUPDDLY 0x650c
15326 
15327 #define S_PHY_T_UPDDLY    0
15328 #define M_PHY_T_UPDDLY    0xfU
15329 #define V_PHY_T_UPDDLY(x) ((x) << S_PHY_T_UPDDLY)
15330 #define G_PHY_T_UPDDLY(x) (((x) >> S_PHY_T_UPDDLY) & M_PHY_T_UPDDLY)
15331 
15332 #define A_MC_PCTL_PVTTUPON 0x6510
15333 
15334 #define S_PVT_T_UPDON    0
15335 #define M_PVT_T_UPDON    0xffU
15336 #define V_PVT_T_UPDON(x) ((x) << S_PVT_T_UPDON)
15337 #define G_PVT_T_UPDON(x) (((x) >> S_PVT_T_UPDON) & M_PVT_T_UPDON)
15338 
15339 #define A_MC_PCTL_PVTTUPDDLY 0x6514
15340 
15341 #define S_PVT_T_UPDDLY    0
15342 #define M_PVT_T_UPDDLY    0xfU
15343 #define V_PVT_T_UPDDLY(x) ((x) << S_PVT_T_UPDDLY)
15344 #define G_PVT_T_UPDDLY(x) (((x) >> S_PVT_T_UPDDLY) & M_PVT_T_UPDDLY)
15345 
15346 #define A_MC_PCTL_PHYPVTUPDI 0x6518
15347 
15348 #define S_PHYPVT_T_UPDI    0
15349 #define M_PHYPVT_T_UPDI    0xffU
15350 #define V_PHYPVT_T_UPDI(x) ((x) << S_PHYPVT_T_UPDI)
15351 #define G_PHYPVT_T_UPDI(x) (((x) >> S_PHYPVT_T_UPDI) & M_PHYPVT_T_UPDI)
15352 
15353 #define A_MC_PCTL_PHYIOCRV1 0x651c
15354 
15355 #define S_BYTE_OE_CTL    16
15356 #define M_BYTE_OE_CTL    0x3U
15357 #define V_BYTE_OE_CTL(x) ((x) << S_BYTE_OE_CTL)
15358 #define G_BYTE_OE_CTL(x) (((x) >> S_BYTE_OE_CTL) & M_BYTE_OE_CTL)
15359 
15360 #define S_DYN_SOC_ODT_ALAT    12
15361 #define M_DYN_SOC_ODT_ALAT    0xfU
15362 #define V_DYN_SOC_ODT_ALAT(x) ((x) << S_DYN_SOC_ODT_ALAT)
15363 #define G_DYN_SOC_ODT_ALAT(x) (((x) >> S_DYN_SOC_ODT_ALAT) & M_DYN_SOC_ODT_ALAT)
15364 
15365 #define S_DYN_SOC_ODT_ATEN    8
15366 #define M_DYN_SOC_ODT_ATEN    0x3U
15367 #define V_DYN_SOC_ODT_ATEN(x) ((x) << S_DYN_SOC_ODT_ATEN)
15368 #define G_DYN_SOC_ODT_ATEN(x) (((x) >> S_DYN_SOC_ODT_ATEN) & M_DYN_SOC_ODT_ATEN)
15369 
15370 #define S_DYN_SOC_ODT    2
15371 #define V_DYN_SOC_ODT(x) ((x) << S_DYN_SOC_ODT)
15372 #define F_DYN_SOC_ODT    V_DYN_SOC_ODT(1U)
15373 
15374 #define S_SOC_ODT_EN    0
15375 #define V_SOC_ODT_EN(x) ((x) << S_SOC_ODT_EN)
15376 #define F_SOC_ODT_EN    V_SOC_ODT_EN(1U)
15377 
15378 #define A_MC_PCTL_PHYTUPDWAIT 0x6520
15379 
15380 #define S_PHY_T_UPDWAIT    0
15381 #define M_PHY_T_UPDWAIT    0x3fU
15382 #define V_PHY_T_UPDWAIT(x) ((x) << S_PHY_T_UPDWAIT)
15383 #define G_PHY_T_UPDWAIT(x) (((x) >> S_PHY_T_UPDWAIT) & M_PHY_T_UPDWAIT)
15384 
15385 #define A_MC_PCTL_PVTTUPDWAIT 0x6524
15386 
15387 #define S_PVT_T_UPDWAIT    0
15388 #define M_PVT_T_UPDWAIT    0x3fU
15389 #define V_PVT_T_UPDWAIT(x) ((x) << S_PVT_T_UPDWAIT)
15390 #define G_PVT_T_UPDWAIT(x) (((x) >> S_PVT_T_UPDWAIT) & M_PVT_T_UPDWAIT)
15391 
15392 #define A_MC_DDR3PHYAC_GCR 0x6a00
15393 
15394 #define S_WLRANK    8
15395 #define M_WLRANK    0x3U
15396 #define V_WLRANK(x) ((x) << S_WLRANK)
15397 #define G_WLRANK(x) (((x) >> S_WLRANK) & M_WLRANK)
15398 
15399 #define S_FDEPTH    6
15400 #define M_FDEPTH    0x3U
15401 #define V_FDEPTH(x) ((x) << S_FDEPTH)
15402 #define G_FDEPTH(x) (((x) >> S_FDEPTH) & M_FDEPTH)
15403 
15404 #define S_LPFDEPTH    4
15405 #define M_LPFDEPTH    0x3U
15406 #define V_LPFDEPTH(x) ((x) << S_LPFDEPTH)
15407 #define G_LPFDEPTH(x) (((x) >> S_LPFDEPTH) & M_LPFDEPTH)
15408 
15409 #define S_LPFEN    3
15410 #define V_LPFEN(x) ((x) << S_LPFEN)
15411 #define F_LPFEN    V_LPFEN(1U)
15412 
15413 #define S_WL    2
15414 #define V_WL(x) ((x) << S_WL)
15415 #define F_WL    V_WL(1U)
15416 
15417 #define S_CAL    1
15418 #define V_CAL(x) ((x) << S_CAL)
15419 #define F_CAL    V_CAL(1U)
15420 
15421 #define S_MDLEN    0
15422 #define V_MDLEN(x) ((x) << S_MDLEN)
15423 #define F_MDLEN    V_MDLEN(1U)
15424 
15425 #define A_MC_DDR3PHYAC_RCR0 0x6a04
15426 
15427 #define S_OCPONR    8
15428 #define V_OCPONR(x) ((x) << S_OCPONR)
15429 #define F_OCPONR    V_OCPONR(1U)
15430 
15431 #define S_OCPOND    7
15432 #define V_OCPOND(x) ((x) << S_OCPOND)
15433 #define F_OCPOND    V_OCPOND(1U)
15434 
15435 #define S_OCOEN    6
15436 #define V_OCOEN(x) ((x) << S_OCOEN)
15437 #define F_OCOEN    V_OCOEN(1U)
15438 
15439 #define S_CKEPONR    5
15440 #define V_CKEPONR(x) ((x) << S_CKEPONR)
15441 #define F_CKEPONR    V_CKEPONR(1U)
15442 
15443 #define S_CKEPOND    4
15444 #define V_CKEPOND(x) ((x) << S_CKEPOND)
15445 #define F_CKEPOND    V_CKEPOND(1U)
15446 
15447 #define S_CKEOEN    3
15448 #define V_CKEOEN(x) ((x) << S_CKEOEN)
15449 #define F_CKEOEN    V_CKEOEN(1U)
15450 
15451 #define S_CKPONR    2
15452 #define V_CKPONR(x) ((x) << S_CKPONR)
15453 #define F_CKPONR    V_CKPONR(1U)
15454 
15455 #define S_CKPOND    1
15456 #define V_CKPOND(x) ((x) << S_CKPOND)
15457 #define F_CKPOND    V_CKPOND(1U)
15458 
15459 #define S_CKOEN    0
15460 #define V_CKOEN(x) ((x) << S_CKOEN)
15461 #define F_CKOEN    V_CKOEN(1U)
15462 
15463 #define A_MC_DDR3PHYAC_ACCR 0x6a14
15464 
15465 #define S_ACPONR    8
15466 #define V_ACPONR(x) ((x) << S_ACPONR)
15467 #define F_ACPONR    V_ACPONR(1U)
15468 
15469 #define S_ACPOND    7
15470 #define V_ACPOND(x) ((x) << S_ACPOND)
15471 #define F_ACPOND    V_ACPOND(1U)
15472 
15473 #define S_ACOEN    6
15474 #define V_ACOEN(x) ((x) << S_ACOEN)
15475 #define F_ACOEN    V_ACOEN(1U)
15476 
15477 #define S_CK5PONR    5
15478 #define V_CK5PONR(x) ((x) << S_CK5PONR)
15479 #define F_CK5PONR    V_CK5PONR(1U)
15480 
15481 #define S_CK5POND    4
15482 #define V_CK5POND(x) ((x) << S_CK5POND)
15483 #define F_CK5POND    V_CK5POND(1U)
15484 
15485 #define S_CK5OEN    3
15486 #define V_CK5OEN(x) ((x) << S_CK5OEN)
15487 #define F_CK5OEN    V_CK5OEN(1U)
15488 
15489 #define S_CK4PONR    2
15490 #define V_CK4PONR(x) ((x) << S_CK4PONR)
15491 #define F_CK4PONR    V_CK4PONR(1U)
15492 
15493 #define S_CK4POND    1
15494 #define V_CK4POND(x) ((x) << S_CK4POND)
15495 #define F_CK4POND    V_CK4POND(1U)
15496 
15497 #define S_CK4OEN    0
15498 #define V_CK4OEN(x) ((x) << S_CK4OEN)
15499 #define F_CK4OEN    V_CK4OEN(1U)
15500 
15501 #define A_MC_DDR3PHYAC_GSR 0x6a18
15502 
15503 #define S_WLERR    4
15504 #define V_WLERR(x) ((x) << S_WLERR)
15505 #define F_WLERR    V_WLERR(1U)
15506 
15507 #define S_INIT    3
15508 #define V_INIT(x) ((x) << S_INIT)
15509 #define F_INIT    V_INIT(1U)
15510 
15511 #define S_ACCAL    0
15512 #define V_ACCAL(x) ((x) << S_ACCAL)
15513 #define F_ACCAL    V_ACCAL(1U)
15514 
15515 #define A_MC_DDR3PHYAC_ECSR 0x6a1c
15516 
15517 #define S_WLDEC    1
15518 #define V_WLDEC(x) ((x) << S_WLDEC)
15519 #define F_WLDEC    V_WLDEC(1U)
15520 
15521 #define S_WLINC    0
15522 #define V_WLINC(x) ((x) << S_WLINC)
15523 #define F_WLINC    V_WLINC(1U)
15524 
15525 #define A_MC_DDR3PHYAC_OCSR 0x6a20
15526 #define A_MC_DDR3PHYAC_MDIPR 0x6a24
15527 
15528 #define S_PRD    0
15529 #define M_PRD    0x3ffU
15530 #define V_PRD(x) ((x) << S_PRD)
15531 #define G_PRD(x) (((x) >> S_PRD) & M_PRD)
15532 
15533 #define A_MC_DDR3PHYAC_MDTPR 0x6a28
15534 #define A_MC_DDR3PHYAC_MDPPR0 0x6a2c
15535 #define A_MC_DDR3PHYAC_MDPPR1 0x6a30
15536 #define A_MC_DDR3PHYAC_PMBDR0 0x6a34
15537 
15538 #define S_DFLTDLY    0
15539 #define M_DFLTDLY    0x7fU
15540 #define V_DFLTDLY(x) ((x) << S_DFLTDLY)
15541 #define G_DFLTDLY(x) (((x) >> S_DFLTDLY) & M_DFLTDLY)
15542 
15543 #define A_MC_DDR3PHYAC_PMBDR1 0x6a38
15544 #define A_MC_DDR3PHYAC_ACR 0x6a60
15545 
15546 #define S_TSEL    9
15547 #define V_TSEL(x) ((x) << S_TSEL)
15548 #define F_TSEL    V_TSEL(1U)
15549 
15550 #define S_ISEL    7
15551 #define M_ISEL    0x3U
15552 #define V_ISEL(x) ((x) << S_ISEL)
15553 #define G_ISEL(x) (((x) >> S_ISEL) & M_ISEL)
15554 
15555 #define S_CALBYP    2
15556 #define V_CALBYP(x) ((x) << S_CALBYP)
15557 #define F_CALBYP    V_CALBYP(1U)
15558 
15559 #define S_SDRSELINV    1
15560 #define V_SDRSELINV(x) ((x) << S_SDRSELINV)
15561 #define F_SDRSELINV    V_SDRSELINV(1U)
15562 
15563 #define S_CKINV    0
15564 #define V_CKINV(x) ((x) << S_CKINV)
15565 #define F_CKINV    V_CKINV(1U)
15566 
15567 #define A_MC_DDR3PHYAC_PSCR 0x6a64
15568 
15569 #define S_PSCALE    0
15570 #define M_PSCALE    0x3ffU
15571 #define V_PSCALE(x) ((x) << S_PSCALE)
15572 #define G_PSCALE(x) (((x) >> S_PSCALE) & M_PSCALE)
15573 
15574 #define A_MC_DDR3PHYAC_PRCR 0x6a68
15575 
15576 #define S_PHYINIT    9
15577 #define V_PHYINIT(x) ((x) << S_PHYINIT)
15578 #define F_PHYINIT    V_PHYINIT(1U)
15579 
15580 #define S_PHYHRST    7
15581 #define V_PHYHRST(x) ((x) << S_PHYHRST)
15582 #define F_PHYHRST    V_PHYHRST(1U)
15583 
15584 #define S_RSTCLKS    3
15585 #define M_RSTCLKS    0xfU
15586 #define V_RSTCLKS(x) ((x) << S_RSTCLKS)
15587 #define G_RSTCLKS(x) (((x) >> S_RSTCLKS) & M_RSTCLKS)
15588 
15589 #define S_PLLPD    2
15590 #define V_PLLPD(x) ((x) << S_PLLPD)
15591 #define F_PLLPD    V_PLLPD(1U)
15592 
15593 #define S_PLLRST    1
15594 #define V_PLLRST(x) ((x) << S_PLLRST)
15595 #define F_PLLRST    V_PLLRST(1U)
15596 
15597 #define S_PHYRST    0
15598 #define V_PHYRST(x) ((x) << S_PHYRST)
15599 #define F_PHYRST    V_PHYRST(1U)
15600 
15601 #define A_MC_DDR3PHYAC_PLLCR0 0x6a6c
15602 
15603 #define S_RSTCXKS    4
15604 #define M_RSTCXKS    0x1fU
15605 #define V_RSTCXKS(x) ((x) << S_RSTCXKS)
15606 #define G_RSTCXKS(x) (((x) >> S_RSTCXKS) & M_RSTCXKS)
15607 
15608 #define S_ICPSEL    3
15609 #define V_ICPSEL(x) ((x) << S_ICPSEL)
15610 #define F_ICPSEL    V_ICPSEL(1U)
15611 
15612 #define S_TESTA    0
15613 #define M_TESTA    0x7U
15614 #define V_TESTA(x) ((x) << S_TESTA)
15615 #define G_TESTA(x) (((x) >> S_TESTA) & M_TESTA)
15616 
15617 #define A_MC_DDR3PHYAC_PLLCR1 0x6a70
15618 
15619 #define S_BYPASS    9
15620 #define V_BYPASS(x) ((x) << S_BYPASS)
15621 #define F_BYPASS    V_BYPASS(1U)
15622 
15623 #define S_BDIV    3
15624 #define M_BDIV    0x3U
15625 #define V_BDIV(x) ((x) << S_BDIV)
15626 #define G_BDIV(x) (((x) >> S_BDIV) & M_BDIV)
15627 
15628 #define S_TESTD    0
15629 #define M_TESTD    0x7U
15630 #define V_TESTD(x) ((x) << S_TESTD)
15631 #define G_TESTD(x) (((x) >> S_TESTD) & M_TESTD)
15632 
15633 #define A_MC_DDR3PHYAC_CLKENR 0x6a78
15634 
15635 #define S_CKCLKEN    3
15636 #define M_CKCLKEN    0x3fU
15637 #define V_CKCLKEN(x) ((x) << S_CKCLKEN)
15638 #define G_CKCLKEN(x) (((x) >> S_CKCLKEN) & M_CKCLKEN)
15639 
15640 #define S_HDRCLKEN    2
15641 #define V_HDRCLKEN(x) ((x) << S_HDRCLKEN)
15642 #define F_HDRCLKEN    V_HDRCLKEN(1U)
15643 
15644 #define S_SDRCLKEN    1
15645 #define V_SDRCLKEN(x) ((x) << S_SDRCLKEN)
15646 #define F_SDRCLKEN    V_SDRCLKEN(1U)
15647 
15648 #define S_DDRCLKEN    0
15649 #define V_DDRCLKEN(x) ((x) << S_DDRCLKEN)
15650 #define F_DDRCLKEN    V_DDRCLKEN(1U)
15651 
15652 #define A_MC_DDR3PHYDATX8_GCR 0x6b00
15653 
15654 #define S_PONR    6
15655 #define V_PONR(x) ((x) << S_PONR)
15656 #define F_PONR    V_PONR(1U)
15657 
15658 #define S_POND    5
15659 #define V_POND(x) ((x) << S_POND)
15660 #define F_POND    V_POND(1U)
15661 
15662 #define S_RDBDVT    4
15663 #define V_RDBDVT(x) ((x) << S_RDBDVT)
15664 #define F_RDBDVT    V_RDBDVT(1U)
15665 
15666 #define S_WDBDVT    3
15667 #define V_WDBDVT(x) ((x) << S_WDBDVT)
15668 #define F_WDBDVT    V_WDBDVT(1U)
15669 
15670 #define S_RDSDVT    2
15671 #define V_RDSDVT(x) ((x) << S_RDSDVT)
15672 #define F_RDSDVT    V_RDSDVT(1U)
15673 
15674 #define S_WDSDVT    1
15675 #define V_WDSDVT(x) ((x) << S_WDSDVT)
15676 #define F_WDSDVT    V_WDSDVT(1U)
15677 
15678 #define S_WLSDVT    0
15679 #define V_WLSDVT(x) ((x) << S_WLSDVT)
15680 #define F_WLSDVT    V_WLSDVT(1U)
15681 
15682 #define A_MC_DDR3PHYDATX8_WDSDR 0x6b04
15683 
15684 #define S_WDSDR_DLY    0
15685 #define M_WDSDR_DLY    0x3ffU
15686 #define V_WDSDR_DLY(x) ((x) << S_WDSDR_DLY)
15687 #define G_WDSDR_DLY(x) (((x) >> S_WDSDR_DLY) & M_WDSDR_DLY)
15688 
15689 #define A_MC_DDR3PHYDATX8_WLDPR 0x6b08
15690 #define A_MC_DDR3PHYDATX8_WLDR 0x6b0c
15691 
15692 #define S_WL_DLY    0
15693 #define M_WL_DLY    0x3ffU
15694 #define V_WL_DLY(x) ((x) << S_WL_DLY)
15695 #define G_WL_DLY(x) (((x) >> S_WL_DLY) & M_WL_DLY)
15696 
15697 #define A_MC_DDR3PHYDATX8_WDBDR0 0x6b1c
15698 
15699 #define S_DLY    0
15700 #define M_DLY    0x7fU
15701 #define V_DLY(x) ((x) << S_DLY)
15702 #define G_DLY(x) (((x) >> S_DLY) & M_DLY)
15703 
15704 #define A_MC_DDR3PHYDATX8_WDBDR1 0x6b20
15705 #define A_MC_DDR3PHYDATX8_WDBDR2 0x6b24
15706 #define A_MC_DDR3PHYDATX8_WDBDR3 0x6b28
15707 #define A_MC_DDR3PHYDATX8_WDBDR4 0x6b2c
15708 #define A_MC_DDR3PHYDATX8_WDBDR5 0x6b30
15709 #define A_MC_DDR3PHYDATX8_WDBDR6 0x6b34
15710 #define A_MC_DDR3PHYDATX8_WDBDR7 0x6b38
15711 #define A_MC_DDR3PHYDATX8_WDBDR8 0x6b3c
15712 #define A_MC_DDR3PHYDATX8_WDBDMR 0x6b40
15713 
15714 #define S_MAXDLY    0
15715 #define M_MAXDLY    0x7fU
15716 #define V_MAXDLY(x) ((x) << S_MAXDLY)
15717 #define G_MAXDLY(x) (((x) >> S_MAXDLY) & M_MAXDLY)
15718 
15719 #define A_MC_DDR3PHYDATX8_RDSDR 0x6b44
15720 
15721 #define S_RDSDR_DLY    0
15722 #define M_RDSDR_DLY    0x3ffU
15723 #define V_RDSDR_DLY(x) ((x) << S_RDSDR_DLY)
15724 #define G_RDSDR_DLY(x) (((x) >> S_RDSDR_DLY) & M_RDSDR_DLY)
15725 
15726 #define A_MC_DDR3PHYDATX8_RDBDR0 0x6b48
15727 #define A_MC_DDR3PHYDATX8_RDBDR1 0x6b4c
15728 #define A_MC_DDR3PHYDATX8_RDBDR2 0x6b50
15729 #define A_MC_DDR3PHYDATX8_RDBDR3 0x6b54
15730 #define A_MC_DDR3PHYDATX8_RDBDR4 0x6b58
15731 #define A_MC_DDR3PHYDATX8_RDBDR5 0x6b5c
15732 #define A_MC_DDR3PHYDATX8_RDBDR6 0x6b60
15733 #define A_MC_DDR3PHYDATX8_RDBDR7 0x6b64
15734 #define A_MC_DDR3PHYDATX8_RDBDMR 0x6b68
15735 #define A_MC_DDR3PHYDATX8_PMBDR0 0x6b6c
15736 #define A_MC_DDR3PHYDATX8_PMBDR1 0x6b70
15737 #define A_MC_DDR3PHYDATX8_PMBDR2 0x6b74
15738 #define A_MC_DDR3PHYDATX8_PMBDR3 0x6b78
15739 #define A_MC_DDR3PHYDATX8_WDBDPR 0x6b7c
15740 
15741 #define S_DP_DLY    0
15742 #define M_DP_DLY    0x1ffU
15743 #define V_DP_DLY(x) ((x) << S_DP_DLY)
15744 #define G_DP_DLY(x) (((x) >> S_DP_DLY) & M_DP_DLY)
15745 
15746 #define A_MC_DDR3PHYDATX8_RDBDPR 0x6b80
15747 #define A_MC_DDR3PHYDATX8_GSR 0x6b84
15748 
15749 #define S_WLDONE    3
15750 #define V_WLDONE(x) ((x) << S_WLDONE)
15751 #define F_WLDONE    V_WLDONE(1U)
15752 
15753 #define S_WLCAL    2
15754 #define V_WLCAL(x) ((x) << S_WLCAL)
15755 #define F_WLCAL    V_WLCAL(1U)
15756 
15757 #define S_READ    1
15758 #define V_READ(x) ((x) << S_READ)
15759 #define F_READ    V_READ(1U)
15760 
15761 #define S_RDQSCAL    0
15762 #define V_RDQSCAL(x) ((x) << S_RDQSCAL)
15763 #define F_RDQSCAL    V_RDQSCAL(1U)
15764 
15765 #define A_MC_DDR3PHYDATX8_ACR 0x6bf0
15766 
15767 #define S_PHYHSRST    9
15768 #define V_PHYHSRST(x) ((x) << S_PHYHSRST)
15769 #define F_PHYHSRST    V_PHYHSRST(1U)
15770 
15771 #define S_WLSTEP    8
15772 #define V_WLSTEP(x) ((x) << S_WLSTEP)
15773 #define F_WLSTEP    V_WLSTEP(1U)
15774 
15775 #define S_SDR_SEL_INV    2
15776 #define V_SDR_SEL_INV(x) ((x) << S_SDR_SEL_INV)
15777 #define F_SDR_SEL_INV    V_SDR_SEL_INV(1U)
15778 
15779 #define S_DDRSELINV    1
15780 #define V_DDRSELINV(x) ((x) << S_DDRSELINV)
15781 #define F_DDRSELINV    V_DDRSELINV(1U)
15782 
15783 #define S_DSINV    0
15784 #define V_DSINV(x) ((x) << S_DSINV)
15785 #define F_DSINV    V_DSINV(1U)
15786 
15787 #define A_MC_DDR3PHYDATX8_RSR 0x6bf4
15788 
15789 #define S_WLRANKSEL    9
15790 #define V_WLRANKSEL(x) ((x) << S_WLRANKSEL)
15791 #define F_WLRANKSEL    V_WLRANKSEL(1U)
15792 
15793 #define S_RANK    0
15794 #define M_RANK    0x3U
15795 #define V_RANK(x) ((x) << S_RANK)
15796 #define G_RANK(x) (((x) >> S_RANK) & M_RANK)
15797 
15798 #define A_MC_DDR3PHYDATX8_CLKENR 0x6bf8
15799 
15800 #define S_DTOSEL    8
15801 #define M_DTOSEL    0x3U
15802 #define V_DTOSEL(x) ((x) << S_DTOSEL)
15803 #define G_DTOSEL(x) (((x) >> S_DTOSEL) & M_DTOSEL)
15804 
15805 #define A_MC_PVT_REG_CALIBRATE_CTL 0x7400
15806 #define A_MC_PVT_REG_UPDATE_CTL 0x7404
15807 #define A_MC_PVT_REG_LAST_MEASUREMENT 0x7408
15808 #define A_MC_PVT_REG_DRVN 0x740c
15809 #define A_MC_PVT_REG_DRVP 0x7410
15810 #define A_MC_PVT_REG_TERMN 0x7414
15811 #define A_MC_PVT_REG_TERMP 0x7418
15812 #define A_MC_PVT_REG_THRESHOLD 0x741c
15813 #define A_MC_PVT_REG_IN_TERMP 0x7420
15814 #define A_MC_PVT_REG_IN_TERMN 0x7424
15815 #define A_MC_PVT_REG_IN_DRVP 0x7428
15816 #define A_MC_PVT_REG_IN_DRVN 0x742c
15817 #define A_MC_PVT_REG_OUT_TERMP 0x7430
15818 #define A_MC_PVT_REG_OUT_TERMN 0x7434
15819 #define A_MC_PVT_REG_OUT_DRVP 0x7438
15820 #define A_MC_PVT_REG_OUT_DRVN 0x743c
15821 #define A_MC_PVT_REG_HISTORY_TERMP 0x7440
15822 #define A_MC_PVT_REG_HISTORY_TERMN 0x7444
15823 #define A_MC_PVT_REG_HISTORY_DRVP 0x7448
15824 #define A_MC_PVT_REG_HISTORY_DRVN 0x744c
15825 #define A_MC_PVT_REG_SAMPLE_WAIT_CLKS 0x7450
15826 #define A_MC_DDRPHY_RST_CTRL 0x7500
15827 
15828 #define S_DDRIO_ENABLE    1
15829 #define V_DDRIO_ENABLE(x) ((x) << S_DDRIO_ENABLE)
15830 #define F_DDRIO_ENABLE    V_DDRIO_ENABLE(1U)
15831 
15832 #define S_PHY_RST_N    0
15833 #define V_PHY_RST_N(x) ((x) << S_PHY_RST_N)
15834 #define F_PHY_RST_N    V_PHY_RST_N(1U)
15835 
15836 #define A_MC_PERFORMANCE_CTRL 0x7504
15837 
15838 #define S_STALL_CHK_BIT    2
15839 #define V_STALL_CHK_BIT(x) ((x) << S_STALL_CHK_BIT)
15840 #define F_STALL_CHK_BIT    V_STALL_CHK_BIT(1U)
15841 
15842 #define S_DDR3_BRC_MODE    1
15843 #define V_DDR3_BRC_MODE(x) ((x) << S_DDR3_BRC_MODE)
15844 #define F_DDR3_BRC_MODE    V_DDR3_BRC_MODE(1U)
15845 
15846 #define S_RMW_PERF_CTRL    0
15847 #define V_RMW_PERF_CTRL(x) ((x) << S_RMW_PERF_CTRL)
15848 #define F_RMW_PERF_CTRL    V_RMW_PERF_CTRL(1U)
15849 
15850 #define A_MC_ECC_CTRL 0x7508
15851 
15852 #define S_ECC_BYPASS_BIST    1
15853 #define V_ECC_BYPASS_BIST(x) ((x) << S_ECC_BYPASS_BIST)
15854 #define F_ECC_BYPASS_BIST    V_ECC_BYPASS_BIST(1U)
15855 
15856 #define S_ECC_DISABLE    0
15857 #define V_ECC_DISABLE(x) ((x) << S_ECC_DISABLE)
15858 #define F_ECC_DISABLE    V_ECC_DISABLE(1U)
15859 
15860 #define A_MC_PAR_ENABLE 0x750c
15861 
15862 #define S_ECC_UE_PAR_ENABLE    3
15863 #define V_ECC_UE_PAR_ENABLE(x) ((x) << S_ECC_UE_PAR_ENABLE)
15864 #define F_ECC_UE_PAR_ENABLE    V_ECC_UE_PAR_ENABLE(1U)
15865 
15866 #define S_ECC_CE_PAR_ENABLE    2
15867 #define V_ECC_CE_PAR_ENABLE(x) ((x) << S_ECC_CE_PAR_ENABLE)
15868 #define F_ECC_CE_PAR_ENABLE    V_ECC_CE_PAR_ENABLE(1U)
15869 
15870 #define S_PERR_REG_INT_ENABLE    1
15871 #define V_PERR_REG_INT_ENABLE(x) ((x) << S_PERR_REG_INT_ENABLE)
15872 #define F_PERR_REG_INT_ENABLE    V_PERR_REG_INT_ENABLE(1U)
15873 
15874 #define S_PERR_BLK_INT_ENABLE    0
15875 #define V_PERR_BLK_INT_ENABLE(x) ((x) << S_PERR_BLK_INT_ENABLE)
15876 #define F_PERR_BLK_INT_ENABLE    V_PERR_BLK_INT_ENABLE(1U)
15877 
15878 #define A_MC_PAR_CAUSE 0x7510
15879 
15880 #define S_ECC_UE_PAR_CAUSE    3
15881 #define V_ECC_UE_PAR_CAUSE(x) ((x) << S_ECC_UE_PAR_CAUSE)
15882 #define F_ECC_UE_PAR_CAUSE    V_ECC_UE_PAR_CAUSE(1U)
15883 
15884 #define S_ECC_CE_PAR_CAUSE    2
15885 #define V_ECC_CE_PAR_CAUSE(x) ((x) << S_ECC_CE_PAR_CAUSE)
15886 #define F_ECC_CE_PAR_CAUSE    V_ECC_CE_PAR_CAUSE(1U)
15887 
15888 #define S_FIFOR_PAR_CAUSE    1
15889 #define V_FIFOR_PAR_CAUSE(x) ((x) << S_FIFOR_PAR_CAUSE)
15890 #define F_FIFOR_PAR_CAUSE    V_FIFOR_PAR_CAUSE(1U)
15891 
15892 #define S_RDATA_FIFOR_PAR_CAUSE    0
15893 #define V_RDATA_FIFOR_PAR_CAUSE(x) ((x) << S_RDATA_FIFOR_PAR_CAUSE)
15894 #define F_RDATA_FIFOR_PAR_CAUSE    V_RDATA_FIFOR_PAR_CAUSE(1U)
15895 
15896 #define A_MC_INT_ENABLE 0x7514
15897 
15898 #define S_ECC_UE_INT_ENABLE    2
15899 #define V_ECC_UE_INT_ENABLE(x) ((x) << S_ECC_UE_INT_ENABLE)
15900 #define F_ECC_UE_INT_ENABLE    V_ECC_UE_INT_ENABLE(1U)
15901 
15902 #define S_ECC_CE_INT_ENABLE    1
15903 #define V_ECC_CE_INT_ENABLE(x) ((x) << S_ECC_CE_INT_ENABLE)
15904 #define F_ECC_CE_INT_ENABLE    V_ECC_CE_INT_ENABLE(1U)
15905 
15906 #define S_PERR_INT_ENABLE    0
15907 #define V_PERR_INT_ENABLE(x) ((x) << S_PERR_INT_ENABLE)
15908 #define F_PERR_INT_ENABLE    V_PERR_INT_ENABLE(1U)
15909 
15910 #define A_MC_INT_CAUSE 0x7518
15911 
15912 #define S_ECC_UE_INT_CAUSE    2
15913 #define V_ECC_UE_INT_CAUSE(x) ((x) << S_ECC_UE_INT_CAUSE)
15914 #define F_ECC_UE_INT_CAUSE    V_ECC_UE_INT_CAUSE(1U)
15915 
15916 #define S_ECC_CE_INT_CAUSE    1
15917 #define V_ECC_CE_INT_CAUSE(x) ((x) << S_ECC_CE_INT_CAUSE)
15918 #define F_ECC_CE_INT_CAUSE    V_ECC_CE_INT_CAUSE(1U)
15919 
15920 #define S_PERR_INT_CAUSE    0
15921 #define V_PERR_INT_CAUSE(x) ((x) << S_PERR_INT_CAUSE)
15922 #define F_PERR_INT_CAUSE    V_PERR_INT_CAUSE(1U)
15923 
15924 #define A_MC_ECC_STATUS 0x751c
15925 
15926 #define S_ECC_CECNT    16
15927 #define M_ECC_CECNT    0xffffU
15928 #define V_ECC_CECNT(x) ((x) << S_ECC_CECNT)
15929 #define G_ECC_CECNT(x) (((x) >> S_ECC_CECNT) & M_ECC_CECNT)
15930 
15931 #define S_ECC_UECNT    0
15932 #define M_ECC_UECNT    0xffffU
15933 #define V_ECC_UECNT(x) ((x) << S_ECC_UECNT)
15934 #define G_ECC_UECNT(x) (((x) >> S_ECC_UECNT) & M_ECC_UECNT)
15935 
15936 #define A_MC_PHY_CTRL 0x7520
15937 
15938 #define S_CTLPHYRR    0
15939 #define V_CTLPHYRR(x) ((x) << S_CTLPHYRR)
15940 #define F_CTLPHYRR    V_CTLPHYRR(1U)
15941 
15942 #define A_MC_STATIC_CFG_STATUS 0x7524
15943 
15944 #define S_STATIC_MODE    9
15945 #define V_STATIC_MODE(x) ((x) << S_STATIC_MODE)
15946 #define F_STATIC_MODE    V_STATIC_MODE(1U)
15947 
15948 #define S_STATIC_DEN    6
15949 #define M_STATIC_DEN    0x7U
15950 #define V_STATIC_DEN(x) ((x) << S_STATIC_DEN)
15951 #define G_STATIC_DEN(x) (((x) >> S_STATIC_DEN) & M_STATIC_DEN)
15952 
15953 #define S_STATIC_ORG    5
15954 #define V_STATIC_ORG(x) ((x) << S_STATIC_ORG)
15955 #define F_STATIC_ORG    V_STATIC_ORG(1U)
15956 
15957 #define S_STATIC_RKS    4
15958 #define V_STATIC_RKS(x) ((x) << S_STATIC_RKS)
15959 #define F_STATIC_RKS    V_STATIC_RKS(1U)
15960 
15961 #define S_STATIC_WIDTH    1
15962 #define M_STATIC_WIDTH    0x7U
15963 #define V_STATIC_WIDTH(x) ((x) << S_STATIC_WIDTH)
15964 #define G_STATIC_WIDTH(x) (((x) >> S_STATIC_WIDTH) & M_STATIC_WIDTH)
15965 
15966 #define S_STATIC_SLOW    0
15967 #define V_STATIC_SLOW(x) ((x) << S_STATIC_SLOW)
15968 #define F_STATIC_SLOW    V_STATIC_SLOW(1U)
15969 
15970 #define A_MC_CORE_PCTL_STAT 0x7528
15971 
15972 #define S_PCTL_ACCESS_STAT    0
15973 #define M_PCTL_ACCESS_STAT    0x7U
15974 #define V_PCTL_ACCESS_STAT(x) ((x) << S_PCTL_ACCESS_STAT)
15975 #define G_PCTL_ACCESS_STAT(x) (((x) >> S_PCTL_ACCESS_STAT) & M_PCTL_ACCESS_STAT)
15976 
15977 #define A_MC_DEBUG_CNT 0x752c
15978 
15979 #define S_WDATA_OCNT    8
15980 #define M_WDATA_OCNT    0x1fU
15981 #define V_WDATA_OCNT(x) ((x) << S_WDATA_OCNT)
15982 #define G_WDATA_OCNT(x) (((x) >> S_WDATA_OCNT) & M_WDATA_OCNT)
15983 
15984 #define S_RDATA_OCNT    0
15985 #define M_RDATA_OCNT    0x1fU
15986 #define V_RDATA_OCNT(x) ((x) << S_RDATA_OCNT)
15987 #define G_RDATA_OCNT(x) (((x) >> S_RDATA_OCNT) & M_RDATA_OCNT)
15988 
15989 #define A_MC_BONUS 0x7530
15990 #define A_MC_BIST_CMD 0x7600
15991 
15992 #define S_START_BIST    31
15993 #define V_START_BIST(x) ((x) << S_START_BIST)
15994 #define F_START_BIST    V_START_BIST(1U)
15995 
15996 #define S_BIST_CMD_GAP    8
15997 #define M_BIST_CMD_GAP    0xffU
15998 #define V_BIST_CMD_GAP(x) ((x) << S_BIST_CMD_GAP)
15999 #define G_BIST_CMD_GAP(x) (((x) >> S_BIST_CMD_GAP) & M_BIST_CMD_GAP)
16000 
16001 #define S_BIST_OPCODE    0
16002 #define M_BIST_OPCODE    0x3U
16003 #define V_BIST_OPCODE(x) ((x) << S_BIST_OPCODE)
16004 #define G_BIST_OPCODE(x) (((x) >> S_BIST_OPCODE) & M_BIST_OPCODE)
16005 
16006 #define A_MC_BIST_CMD_ADDR 0x7604
16007 #define A_MC_BIST_CMD_LEN 0x7608
16008 #define A_MC_BIST_DATA_PATTERN 0x760c
16009 
16010 #define S_BIST_DATA_TYPE    0
16011 #define M_BIST_DATA_TYPE    0xfU
16012 #define V_BIST_DATA_TYPE(x) ((x) << S_BIST_DATA_TYPE)
16013 #define G_BIST_DATA_TYPE(x) (((x) >> S_BIST_DATA_TYPE) & M_BIST_DATA_TYPE)
16014 
16015 #define A_MC_BIST_USER_WDATA0 0x7614
16016 #define A_MC_BIST_USER_WDATA1 0x7618
16017 #define A_MC_BIST_USER_WDATA2 0x761c
16018 
16019 #define S_USER_DATA2    0
16020 #define M_USER_DATA2    0xffU
16021 #define V_USER_DATA2(x) ((x) << S_USER_DATA2)
16022 #define G_USER_DATA2(x) (((x) >> S_USER_DATA2) & M_USER_DATA2)
16023 
16024 #define A_MC_BIST_NUM_ERR 0x7680
16025 #define A_MC_BIST_ERR_FIRST_ADDR 0x7684
16026 #define A_MC_BIST_STATUS_RDATA 0x7688
16027 
16028 /* registers for module MA */
16029 #define MA_BASE_ADDR 0x7700
16030 
16031 #define A_MA_CLIENT0_RD_LATENCY_THRESHOLD 0x7700
16032 
16033 #define S_THRESHOLD1    17
16034 #define M_THRESHOLD1    0x7fffU
16035 #define V_THRESHOLD1(x) ((x) << S_THRESHOLD1)
16036 #define G_THRESHOLD1(x) (((x) >> S_THRESHOLD1) & M_THRESHOLD1)
16037 
16038 #define S_THRESHOLD1_EN    16
16039 #define V_THRESHOLD1_EN(x) ((x) << S_THRESHOLD1_EN)
16040 #define F_THRESHOLD1_EN    V_THRESHOLD1_EN(1U)
16041 
16042 #define S_THRESHOLD0    1
16043 #define M_THRESHOLD0    0x7fffU
16044 #define V_THRESHOLD0(x) ((x) << S_THRESHOLD0)
16045 #define G_THRESHOLD0(x) (((x) >> S_THRESHOLD0) & M_THRESHOLD0)
16046 
16047 #define S_THRESHOLD0_EN    0
16048 #define V_THRESHOLD0_EN(x) ((x) << S_THRESHOLD0_EN)
16049 #define F_THRESHOLD0_EN    V_THRESHOLD0_EN(1U)
16050 
16051 #define A_MA_CLIENT0_WR_LATENCY_THRESHOLD 0x7704
16052 #define A_MA_CLIENT1_RD_LATENCY_THRESHOLD 0x7708
16053 #define A_MA_CLIENT1_WR_LATENCY_THRESHOLD 0x770c
16054 #define A_MA_CLIENT2_RD_LATENCY_THRESHOLD 0x7710
16055 #define A_MA_CLIENT2_WR_LATENCY_THRESHOLD 0x7714
16056 #define A_MA_CLIENT3_RD_LATENCY_THRESHOLD 0x7718
16057 #define A_MA_CLIENT3_WR_LATENCY_THRESHOLD 0x771c
16058 #define A_MA_CLIENT4_RD_LATENCY_THRESHOLD 0x7720
16059 #define A_MA_CLIENT4_WR_LATENCY_THRESHOLD 0x7724
16060 #define A_MA_CLIENT5_RD_LATENCY_THRESHOLD 0x7728
16061 #define A_MA_CLIENT5_WR_LATENCY_THRESHOLD 0x772c
16062 #define A_MA_CLIENT6_RD_LATENCY_THRESHOLD 0x7730
16063 #define A_MA_CLIENT6_WR_LATENCY_THRESHOLD 0x7734
16064 #define A_MA_CLIENT7_RD_LATENCY_THRESHOLD 0x7738
16065 #define A_MA_CLIENT7_WR_LATENCY_THRESHOLD 0x773c
16066 #define A_MA_CLIENT8_RD_LATENCY_THRESHOLD 0x7740
16067 #define A_MA_CLIENT8_WR_LATENCY_THRESHOLD 0x7744
16068 #define A_MA_CLIENT9_RD_LATENCY_THRESHOLD 0x7748
16069 #define A_MA_CLIENT9_WR_LATENCY_THRESHOLD 0x774c
16070 #define A_MA_CLIENT10_RD_LATENCY_THRESHOLD 0x7750
16071 #define A_MA_CLIENT10_WR_LATENCY_THRESHOLD 0x7754
16072 #define A_MA_CLIENT11_RD_LATENCY_THRESHOLD 0x7758
16073 #define A_MA_CLIENT11_WR_LATENCY_THRESHOLD 0x775c
16074 #define A_MA_CLIENT12_RD_LATENCY_THRESHOLD 0x7760
16075 #define A_MA_CLIENT12_WR_LATENCY_THRESHOLD 0x7764
16076 #define A_MA_SGE_TH0_DEBUG_CNT 0x7768
16077 
16078 #define S_DBG_READ_DATA_CNT    24
16079 #define M_DBG_READ_DATA_CNT    0xffU
16080 #define V_DBG_READ_DATA_CNT(x) ((x) << S_DBG_READ_DATA_CNT)
16081 #define G_DBG_READ_DATA_CNT(x) (((x) >> S_DBG_READ_DATA_CNT) & M_DBG_READ_DATA_CNT)
16082 
16083 #define S_DBG_READ_REQ_CNT    16
16084 #define M_DBG_READ_REQ_CNT    0xffU
16085 #define V_DBG_READ_REQ_CNT(x) ((x) << S_DBG_READ_REQ_CNT)
16086 #define G_DBG_READ_REQ_CNT(x) (((x) >> S_DBG_READ_REQ_CNT) & M_DBG_READ_REQ_CNT)
16087 
16088 #define S_DBG_WRITE_DATA_CNT    8
16089 #define M_DBG_WRITE_DATA_CNT    0xffU
16090 #define V_DBG_WRITE_DATA_CNT(x) ((x) << S_DBG_WRITE_DATA_CNT)
16091 #define G_DBG_WRITE_DATA_CNT(x) (((x) >> S_DBG_WRITE_DATA_CNT) & M_DBG_WRITE_DATA_CNT)
16092 
16093 #define S_DBG_WRITE_REQ_CNT    0
16094 #define M_DBG_WRITE_REQ_CNT    0xffU
16095 #define V_DBG_WRITE_REQ_CNT(x) ((x) << S_DBG_WRITE_REQ_CNT)
16096 #define G_DBG_WRITE_REQ_CNT(x) (((x) >> S_DBG_WRITE_REQ_CNT) & M_DBG_WRITE_REQ_CNT)
16097 
16098 #define A_MA_SGE_TH1_DEBUG_CNT 0x776c
16099 #define A_MA_ULPTX_DEBUG_CNT 0x7770
16100 #define A_MA_ULPRX_DEBUG_CNT 0x7774
16101 #define A_MA_ULPTXRX_DEBUG_CNT 0x7778
16102 #define A_MA_TP_TH0_DEBUG_CNT 0x777c
16103 #define A_MA_TP_TH1_DEBUG_CNT 0x7780
16104 #define A_MA_LE_DEBUG_CNT 0x7784
16105 #define A_MA_CIM_DEBUG_CNT 0x7788
16106 #define A_MA_PCIE_DEBUG_CNT 0x778c
16107 #define A_MA_PMTX_DEBUG_CNT 0x7790
16108 #define A_MA_PMRX_DEBUG_CNT 0x7794
16109 #define A_MA_HMA_DEBUG_CNT 0x7798
16110 #define A_MA_EDRAM0_BAR 0x77c0
16111 
16112 #define S_EDRAM0_BASE    16
16113 #define M_EDRAM0_BASE    0xfffU
16114 #define V_EDRAM0_BASE(x) ((x) << S_EDRAM0_BASE)
16115 #define G_EDRAM0_BASE(x) (((x) >> S_EDRAM0_BASE) & M_EDRAM0_BASE)
16116 
16117 #define S_EDRAM0_SIZE    0
16118 #define M_EDRAM0_SIZE    0xfffU
16119 #define V_EDRAM0_SIZE(x) ((x) << S_EDRAM0_SIZE)
16120 #define G_EDRAM0_SIZE(x) (((x) >> S_EDRAM0_SIZE) & M_EDRAM0_SIZE)
16121 
16122 #define A_MA_EDRAM1_BAR 0x77c4
16123 
16124 #define S_EDRAM1_BASE    16
16125 #define M_EDRAM1_BASE    0xfffU
16126 #define V_EDRAM1_BASE(x) ((x) << S_EDRAM1_BASE)
16127 #define G_EDRAM1_BASE(x) (((x) >> S_EDRAM1_BASE) & M_EDRAM1_BASE)
16128 
16129 #define S_EDRAM1_SIZE    0
16130 #define M_EDRAM1_SIZE    0xfffU
16131 #define V_EDRAM1_SIZE(x) ((x) << S_EDRAM1_SIZE)
16132 #define G_EDRAM1_SIZE(x) (((x) >> S_EDRAM1_SIZE) & M_EDRAM1_SIZE)
16133 
16134 #define A_MA_EXT_MEMORY_BAR 0x77c8
16135 
16136 #define S_EXT_MEM_BASE    16
16137 #define M_EXT_MEM_BASE    0xfffU
16138 #define V_EXT_MEM_BASE(x) ((x) << S_EXT_MEM_BASE)
16139 #define G_EXT_MEM_BASE(x) (((x) >> S_EXT_MEM_BASE) & M_EXT_MEM_BASE)
16140 
16141 #define S_EXT_MEM_SIZE    0
16142 #define M_EXT_MEM_SIZE    0xfffU
16143 #define V_EXT_MEM_SIZE(x) ((x) << S_EXT_MEM_SIZE)
16144 #define G_EXT_MEM_SIZE(x) (((x) >> S_EXT_MEM_SIZE) & M_EXT_MEM_SIZE)
16145 
16146 #define A_MA_EXT_MEMORY0_BAR 0x77c8
16147 
16148 #define S_EXT_MEM0_BASE    16
16149 #define M_EXT_MEM0_BASE    0xfffU
16150 #define V_EXT_MEM0_BASE(x) ((x) << S_EXT_MEM0_BASE)
16151 #define G_EXT_MEM0_BASE(x) (((x) >> S_EXT_MEM0_BASE) & M_EXT_MEM0_BASE)
16152 
16153 #define S_EXT_MEM0_SIZE    0
16154 #define M_EXT_MEM0_SIZE    0xfffU
16155 #define V_EXT_MEM0_SIZE(x) ((x) << S_EXT_MEM0_SIZE)
16156 #define G_EXT_MEM0_SIZE(x) (((x) >> S_EXT_MEM0_SIZE) & M_EXT_MEM0_SIZE)
16157 
16158 #define A_MA_HOST_MEMORY_BAR 0x77cc
16159 
16160 #define S_HMA_BASE    16
16161 #define M_HMA_BASE    0xfffU
16162 #define V_HMA_BASE(x) ((x) << S_HMA_BASE)
16163 #define G_HMA_BASE(x) (((x) >> S_HMA_BASE) & M_HMA_BASE)
16164 
16165 #define S_HMA_SIZE    0
16166 #define M_HMA_SIZE    0xfffU
16167 #define V_HMA_SIZE(x) ((x) << S_HMA_SIZE)
16168 #define G_HMA_SIZE(x) (((x) >> S_HMA_SIZE) & M_HMA_SIZE)
16169 
16170 #define A_MA_EXT_MEM_PAGE_SIZE 0x77d0
16171 
16172 #define S_BRC_MODE    2
16173 #define V_BRC_MODE(x) ((x) << S_BRC_MODE)
16174 #define F_BRC_MODE    V_BRC_MODE(1U)
16175 
16176 #define S_EXT_MEM_PAGE_SIZE    0
16177 #define M_EXT_MEM_PAGE_SIZE    0x3U
16178 #define V_EXT_MEM_PAGE_SIZE(x) ((x) << S_EXT_MEM_PAGE_SIZE)
16179 #define G_EXT_MEM_PAGE_SIZE(x) (((x) >> S_EXT_MEM_PAGE_SIZE) & M_EXT_MEM_PAGE_SIZE)
16180 
16181 #define S_BRC_MODE1    6
16182 #define V_BRC_MODE1(x) ((x) << S_BRC_MODE1)
16183 #define F_BRC_MODE1    V_BRC_MODE1(1U)
16184 
16185 #define S_EXT_MEM_PAGE_SIZE1    4
16186 #define M_EXT_MEM_PAGE_SIZE1    0x3U
16187 #define V_EXT_MEM_PAGE_SIZE1(x) ((x) << S_EXT_MEM_PAGE_SIZE1)
16188 #define G_EXT_MEM_PAGE_SIZE1(x) (((x) >> S_EXT_MEM_PAGE_SIZE1) & M_EXT_MEM_PAGE_SIZE1)
16189 
16190 #define S_BRBC_MODE    4
16191 #define V_BRBC_MODE(x) ((x) << S_BRBC_MODE)
16192 #define F_BRBC_MODE    V_BRBC_MODE(1U)
16193 
16194 #define S_T6_BRC_MODE    3
16195 #define V_T6_BRC_MODE(x) ((x) << S_T6_BRC_MODE)
16196 #define F_T6_BRC_MODE    V_T6_BRC_MODE(1U)
16197 
16198 #define S_T6_EXT_MEM_PAGE_SIZE    0
16199 #define M_T6_EXT_MEM_PAGE_SIZE    0x7U
16200 #define V_T6_EXT_MEM_PAGE_SIZE(x) ((x) << S_T6_EXT_MEM_PAGE_SIZE)
16201 #define G_T6_EXT_MEM_PAGE_SIZE(x) (((x) >> S_T6_EXT_MEM_PAGE_SIZE) & M_T6_EXT_MEM_PAGE_SIZE)
16202 
16203 #define A_MA_ARB_CTRL 0x77d4
16204 
16205 #define S_DIS_PAGE_HINT    1
16206 #define V_DIS_PAGE_HINT(x) ((x) << S_DIS_PAGE_HINT)
16207 #define F_DIS_PAGE_HINT    V_DIS_PAGE_HINT(1U)
16208 
16209 #define S_DIS_ADV_ARB    0
16210 #define V_DIS_ADV_ARB(x) ((x) << S_DIS_ADV_ARB)
16211 #define F_DIS_ADV_ARB    V_DIS_ADV_ARB(1U)
16212 
16213 #define S_DIS_BANK_FAIR    2
16214 #define V_DIS_BANK_FAIR(x) ((x) << S_DIS_BANK_FAIR)
16215 #define F_DIS_BANK_FAIR    V_DIS_BANK_FAIR(1U)
16216 
16217 #define S_HMA_WRT_EN    26
16218 #define V_HMA_WRT_EN(x) ((x) << S_HMA_WRT_EN)
16219 #define F_HMA_WRT_EN    V_HMA_WRT_EN(1U)
16220 
16221 #define S_HMA_NUM_PG_128B_FDBK    21
16222 #define M_HMA_NUM_PG_128B_FDBK    0x1fU
16223 #define V_HMA_NUM_PG_128B_FDBK(x) ((x) << S_HMA_NUM_PG_128B_FDBK)
16224 #define G_HMA_NUM_PG_128B_FDBK(x) (((x) >> S_HMA_NUM_PG_128B_FDBK) & M_HMA_NUM_PG_128B_FDBK)
16225 
16226 #define S_HMA_DIS_128B_PG_CNT_FDBK    20
16227 #define V_HMA_DIS_128B_PG_CNT_FDBK(x) ((x) << S_HMA_DIS_128B_PG_CNT_FDBK)
16228 #define F_HMA_DIS_128B_PG_CNT_FDBK    V_HMA_DIS_128B_PG_CNT_FDBK(1U)
16229 
16230 #define S_HMA_DIS_BG_ARB    19
16231 #define V_HMA_DIS_BG_ARB(x) ((x) << S_HMA_DIS_BG_ARB)
16232 #define F_HMA_DIS_BG_ARB    V_HMA_DIS_BG_ARB(1U)
16233 
16234 #define S_HMA_DIS_BANK_FAIR    18
16235 #define V_HMA_DIS_BANK_FAIR(x) ((x) << S_HMA_DIS_BANK_FAIR)
16236 #define F_HMA_DIS_BANK_FAIR    V_HMA_DIS_BANK_FAIR(1U)
16237 
16238 #define S_HMA_DIS_PAGE_HINT    17
16239 #define V_HMA_DIS_PAGE_HINT(x) ((x) << S_HMA_DIS_PAGE_HINT)
16240 #define F_HMA_DIS_PAGE_HINT    V_HMA_DIS_PAGE_HINT(1U)
16241 
16242 #define S_HMA_DIS_ADV_ARB    16
16243 #define V_HMA_DIS_ADV_ARB(x) ((x) << S_HMA_DIS_ADV_ARB)
16244 #define F_HMA_DIS_ADV_ARB    V_HMA_DIS_ADV_ARB(1U)
16245 
16246 #define S_NUM_PG_128B_FDBK    5
16247 #define M_NUM_PG_128B_FDBK    0x1fU
16248 #define V_NUM_PG_128B_FDBK(x) ((x) << S_NUM_PG_128B_FDBK)
16249 #define G_NUM_PG_128B_FDBK(x) (((x) >> S_NUM_PG_128B_FDBK) & M_NUM_PG_128B_FDBK)
16250 
16251 #define S_DIS_128B_PG_CNT_FDBK    4
16252 #define V_DIS_128B_PG_CNT_FDBK(x) ((x) << S_DIS_128B_PG_CNT_FDBK)
16253 #define F_DIS_128B_PG_CNT_FDBK    V_DIS_128B_PG_CNT_FDBK(1U)
16254 
16255 #define S_DIS_BG_ARB    3
16256 #define V_DIS_BG_ARB(x) ((x) << S_DIS_BG_ARB)
16257 #define F_DIS_BG_ARB    V_DIS_BG_ARB(1U)
16258 
16259 #define A_MA_TARGET_MEM_ENABLE 0x77d8
16260 
16261 #define S_HMA_ENABLE    3
16262 #define V_HMA_ENABLE(x) ((x) << S_HMA_ENABLE)
16263 #define F_HMA_ENABLE    V_HMA_ENABLE(1U)
16264 
16265 #define S_EXT_MEM_ENABLE    2
16266 #define V_EXT_MEM_ENABLE(x) ((x) << S_EXT_MEM_ENABLE)
16267 #define F_EXT_MEM_ENABLE    V_EXT_MEM_ENABLE(1U)
16268 
16269 #define S_EDRAM1_ENABLE    1
16270 #define V_EDRAM1_ENABLE(x) ((x) << S_EDRAM1_ENABLE)
16271 #define F_EDRAM1_ENABLE    V_EDRAM1_ENABLE(1U)
16272 
16273 #define S_EDRAM0_ENABLE    0
16274 #define V_EDRAM0_ENABLE(x) ((x) << S_EDRAM0_ENABLE)
16275 #define F_EDRAM0_ENABLE    V_EDRAM0_ENABLE(1U)
16276 
16277 #define S_HMA_MUX    5
16278 #define V_HMA_MUX(x) ((x) << S_HMA_MUX)
16279 #define F_HMA_MUX    V_HMA_MUX(1U)
16280 
16281 #define S_EXT_MEM1_ENABLE    4
16282 #define V_EXT_MEM1_ENABLE(x) ((x) << S_EXT_MEM1_ENABLE)
16283 #define F_EXT_MEM1_ENABLE    V_EXT_MEM1_ENABLE(1U)
16284 
16285 #define S_EXT_MEM0_ENABLE    2
16286 #define V_EXT_MEM0_ENABLE(x) ((x) << S_EXT_MEM0_ENABLE)
16287 #define F_EXT_MEM0_ENABLE    V_EXT_MEM0_ENABLE(1U)
16288 
16289 #define S_MC_SPLIT    6
16290 #define V_MC_SPLIT(x) ((x) << S_MC_SPLIT)
16291 #define F_MC_SPLIT    V_MC_SPLIT(1U)
16292 
16293 #define A_MA_INT_ENABLE 0x77dc
16294 
16295 #define S_MEM_PERR_INT_ENABLE    1
16296 #define V_MEM_PERR_INT_ENABLE(x) ((x) << S_MEM_PERR_INT_ENABLE)
16297 #define F_MEM_PERR_INT_ENABLE    V_MEM_PERR_INT_ENABLE(1U)
16298 
16299 #define S_MEM_WRAP_INT_ENABLE    0
16300 #define V_MEM_WRAP_INT_ENABLE(x) ((x) << S_MEM_WRAP_INT_ENABLE)
16301 #define F_MEM_WRAP_INT_ENABLE    V_MEM_WRAP_INT_ENABLE(1U)
16302 
16303 #define S_MEM_TO_INT_ENABLE    2
16304 #define V_MEM_TO_INT_ENABLE(x) ((x) << S_MEM_TO_INT_ENABLE)
16305 #define F_MEM_TO_INT_ENABLE    V_MEM_TO_INT_ENABLE(1U)
16306 
16307 #define A_MA_INT_CAUSE 0x77e0
16308 
16309 #define S_MEM_PERR_INT_CAUSE    1
16310 #define V_MEM_PERR_INT_CAUSE(x) ((x) << S_MEM_PERR_INT_CAUSE)
16311 #define F_MEM_PERR_INT_CAUSE    V_MEM_PERR_INT_CAUSE(1U)
16312 
16313 #define S_MEM_WRAP_INT_CAUSE    0
16314 #define V_MEM_WRAP_INT_CAUSE(x) ((x) << S_MEM_WRAP_INT_CAUSE)
16315 #define F_MEM_WRAP_INT_CAUSE    V_MEM_WRAP_INT_CAUSE(1U)
16316 
16317 #define S_MEM_TO_INT_CAUSE    2
16318 #define V_MEM_TO_INT_CAUSE(x) ((x) << S_MEM_TO_INT_CAUSE)
16319 #define F_MEM_TO_INT_CAUSE    V_MEM_TO_INT_CAUSE(1U)
16320 
16321 #define A_MA_INT_WRAP_STATUS 0x77e4
16322 
16323 #define S_MEM_WRAP_ADDRESS    4
16324 #define M_MEM_WRAP_ADDRESS    0xfffffffU
16325 #define V_MEM_WRAP_ADDRESS(x) ((x) << S_MEM_WRAP_ADDRESS)
16326 #define G_MEM_WRAP_ADDRESS(x) (((x) >> S_MEM_WRAP_ADDRESS) & M_MEM_WRAP_ADDRESS)
16327 
16328 #define S_MEM_WRAP_CLIENT_NUM    0
16329 #define M_MEM_WRAP_CLIENT_NUM    0xfU
16330 #define V_MEM_WRAP_CLIENT_NUM(x) ((x) << S_MEM_WRAP_CLIENT_NUM)
16331 #define G_MEM_WRAP_CLIENT_NUM(x) (((x) >> S_MEM_WRAP_CLIENT_NUM) & M_MEM_WRAP_CLIENT_NUM)
16332 
16333 #define A_MA_TP_THREAD1_MAPPER 0x77e8
16334 
16335 #define S_TP_THREAD1_EN    0
16336 #define M_TP_THREAD1_EN    0xffU
16337 #define V_TP_THREAD1_EN(x) ((x) << S_TP_THREAD1_EN)
16338 #define G_TP_THREAD1_EN(x) (((x) >> S_TP_THREAD1_EN) & M_TP_THREAD1_EN)
16339 
16340 #define A_MA_SGE_THREAD1_MAPPER 0x77ec
16341 
16342 #define S_SGE_THREAD1_EN    0
16343 #define M_SGE_THREAD1_EN    0xffU
16344 #define V_SGE_THREAD1_EN(x) ((x) << S_SGE_THREAD1_EN)
16345 #define G_SGE_THREAD1_EN(x) (((x) >> S_SGE_THREAD1_EN) & M_SGE_THREAD1_EN)
16346 
16347 #define A_MA_PARITY_ERROR_ENABLE 0x77f0
16348 
16349 #define S_TP_DMARBT_PAR_ERROR_EN    31
16350 #define V_TP_DMARBT_PAR_ERROR_EN(x) ((x) << S_TP_DMARBT_PAR_ERROR_EN)
16351 #define F_TP_DMARBT_PAR_ERROR_EN    V_TP_DMARBT_PAR_ERROR_EN(1U)
16352 
16353 #define S_LOGIC_FIFO_PAR_ERROR_EN    30
16354 #define V_LOGIC_FIFO_PAR_ERROR_EN(x) ((x) << S_LOGIC_FIFO_PAR_ERROR_EN)
16355 #define F_LOGIC_FIFO_PAR_ERROR_EN    V_LOGIC_FIFO_PAR_ERROR_EN(1U)
16356 
16357 #define S_ARB3_PAR_WRQUEUE_ERROR_EN    29
16358 #define V_ARB3_PAR_WRQUEUE_ERROR_EN(x) ((x) << S_ARB3_PAR_WRQUEUE_ERROR_EN)
16359 #define F_ARB3_PAR_WRQUEUE_ERROR_EN    V_ARB3_PAR_WRQUEUE_ERROR_EN(1U)
16360 
16361 #define S_ARB2_PAR_WRQUEUE_ERROR_EN    28
16362 #define V_ARB2_PAR_WRQUEUE_ERROR_EN(x) ((x) << S_ARB2_PAR_WRQUEUE_ERROR_EN)
16363 #define F_ARB2_PAR_WRQUEUE_ERROR_EN    V_ARB2_PAR_WRQUEUE_ERROR_EN(1U)
16364 
16365 #define S_ARB1_PAR_WRQUEUE_ERROR_EN    27
16366 #define V_ARB1_PAR_WRQUEUE_ERROR_EN(x) ((x) << S_ARB1_PAR_WRQUEUE_ERROR_EN)
16367 #define F_ARB1_PAR_WRQUEUE_ERROR_EN    V_ARB1_PAR_WRQUEUE_ERROR_EN(1U)
16368 
16369 #define S_ARB0_PAR_WRQUEUE_ERROR_EN    26
16370 #define V_ARB0_PAR_WRQUEUE_ERROR_EN(x) ((x) << S_ARB0_PAR_WRQUEUE_ERROR_EN)
16371 #define F_ARB0_PAR_WRQUEUE_ERROR_EN    V_ARB0_PAR_WRQUEUE_ERROR_EN(1U)
16372 
16373 #define S_ARB3_PAR_RDQUEUE_ERROR_EN    25
16374 #define V_ARB3_PAR_RDQUEUE_ERROR_EN(x) ((x) << S_ARB3_PAR_RDQUEUE_ERROR_EN)
16375 #define F_ARB3_PAR_RDQUEUE_ERROR_EN    V_ARB3_PAR_RDQUEUE_ERROR_EN(1U)
16376 
16377 #define S_ARB2_PAR_RDQUEUE_ERROR_EN    24
16378 #define V_ARB2_PAR_RDQUEUE_ERROR_EN(x) ((x) << S_ARB2_PAR_RDQUEUE_ERROR_EN)
16379 #define F_ARB2_PAR_RDQUEUE_ERROR_EN    V_ARB2_PAR_RDQUEUE_ERROR_EN(1U)
16380 
16381 #define S_ARB1_PAR_RDQUEUE_ERROR_EN    23
16382 #define V_ARB1_PAR_RDQUEUE_ERROR_EN(x) ((x) << S_ARB1_PAR_RDQUEUE_ERROR_EN)
16383 #define F_ARB1_PAR_RDQUEUE_ERROR_EN    V_ARB1_PAR_RDQUEUE_ERROR_EN(1U)
16384 
16385 #define S_ARB0_PAR_RDQUEUE_ERROR_EN    22
16386 #define V_ARB0_PAR_RDQUEUE_ERROR_EN(x) ((x) << S_ARB0_PAR_RDQUEUE_ERROR_EN)
16387 #define F_ARB0_PAR_RDQUEUE_ERROR_EN    V_ARB0_PAR_RDQUEUE_ERROR_EN(1U)
16388 
16389 #define S_CL10_PAR_WRQUEUE_ERROR_EN    21
16390 #define V_CL10_PAR_WRQUEUE_ERROR_EN(x) ((x) << S_CL10_PAR_WRQUEUE_ERROR_EN)
16391 #define F_CL10_PAR_WRQUEUE_ERROR_EN    V_CL10_PAR_WRQUEUE_ERROR_EN(1U)
16392 
16393 #define S_CL9_PAR_WRQUEUE_ERROR_EN    20
16394 #define V_CL9_PAR_WRQUEUE_ERROR_EN(x) ((x) << S_CL9_PAR_WRQUEUE_ERROR_EN)
16395 #define F_CL9_PAR_WRQUEUE_ERROR_EN    V_CL9_PAR_WRQUEUE_ERROR_EN(1U)
16396 
16397 #define S_CL8_PAR_WRQUEUE_ERROR_EN    19
16398 #define V_CL8_PAR_WRQUEUE_ERROR_EN(x) ((x) << S_CL8_PAR_WRQUEUE_ERROR_EN)
16399 #define F_CL8_PAR_WRQUEUE_ERROR_EN    V_CL8_PAR_WRQUEUE_ERROR_EN(1U)
16400 
16401 #define S_CL7_PAR_WRQUEUE_ERROR_EN    18
16402 #define V_CL7_PAR_WRQUEUE_ERROR_EN(x) ((x) << S_CL7_PAR_WRQUEUE_ERROR_EN)
16403 #define F_CL7_PAR_WRQUEUE_ERROR_EN    V_CL7_PAR_WRQUEUE_ERROR_EN(1U)
16404 
16405 #define S_CL6_PAR_WRQUEUE_ERROR_EN    17
16406 #define V_CL6_PAR_WRQUEUE_ERROR_EN(x) ((x) << S_CL6_PAR_WRQUEUE_ERROR_EN)
16407 #define F_CL6_PAR_WRQUEUE_ERROR_EN    V_CL6_PAR_WRQUEUE_ERROR_EN(1U)
16408 
16409 #define S_CL5_PAR_WRQUEUE_ERROR_EN    16
16410 #define V_CL5_PAR_WRQUEUE_ERROR_EN(x) ((x) << S_CL5_PAR_WRQUEUE_ERROR_EN)
16411 #define F_CL5_PAR_WRQUEUE_ERROR_EN    V_CL5_PAR_WRQUEUE_ERROR_EN(1U)
16412 
16413 #define S_CL4_PAR_WRQUEUE_ERROR_EN    15
16414 #define V_CL4_PAR_WRQUEUE_ERROR_EN(x) ((x) << S_CL4_PAR_WRQUEUE_ERROR_EN)
16415 #define F_CL4_PAR_WRQUEUE_ERROR_EN    V_CL4_PAR_WRQUEUE_ERROR_EN(1U)
16416 
16417 #define S_CL3_PAR_WRQUEUE_ERROR_EN    14
16418 #define V_CL3_PAR_WRQUEUE_ERROR_EN(x) ((x) << S_CL3_PAR_WRQUEUE_ERROR_EN)
16419 #define F_CL3_PAR_WRQUEUE_ERROR_EN    V_CL3_PAR_WRQUEUE_ERROR_EN(1U)
16420 
16421 #define S_CL2_PAR_WRQUEUE_ERROR_EN    13
16422 #define V_CL2_PAR_WRQUEUE_ERROR_EN(x) ((x) << S_CL2_PAR_WRQUEUE_ERROR_EN)
16423 #define F_CL2_PAR_WRQUEUE_ERROR_EN    V_CL2_PAR_WRQUEUE_ERROR_EN(1U)
16424 
16425 #define S_CL1_PAR_WRQUEUE_ERROR_EN    12
16426 #define V_CL1_PAR_WRQUEUE_ERROR_EN(x) ((x) << S_CL1_PAR_WRQUEUE_ERROR_EN)
16427 #define F_CL1_PAR_WRQUEUE_ERROR_EN    V_CL1_PAR_WRQUEUE_ERROR_EN(1U)
16428 
16429 #define S_CL0_PAR_WRQUEUE_ERROR_EN    11
16430 #define V_CL0_PAR_WRQUEUE_ERROR_EN(x) ((x) << S_CL0_PAR_WRQUEUE_ERROR_EN)
16431 #define F_CL0_PAR_WRQUEUE_ERROR_EN    V_CL0_PAR_WRQUEUE_ERROR_EN(1U)
16432 
16433 #define S_CL10_PAR_RDQUEUE_ERROR_EN    10
16434 #define V_CL10_PAR_RDQUEUE_ERROR_EN(x) ((x) << S_CL10_PAR_RDQUEUE_ERROR_EN)
16435 #define F_CL10_PAR_RDQUEUE_ERROR_EN    V_CL10_PAR_RDQUEUE_ERROR_EN(1U)
16436 
16437 #define S_CL9_PAR_RDQUEUE_ERROR_EN    9
16438 #define V_CL9_PAR_RDQUEUE_ERROR_EN(x) ((x) << S_CL9_PAR_RDQUEUE_ERROR_EN)
16439 #define F_CL9_PAR_RDQUEUE_ERROR_EN    V_CL9_PAR_RDQUEUE_ERROR_EN(1U)
16440 
16441 #define S_CL8_PAR_RDQUEUE_ERROR_EN    8
16442 #define V_CL8_PAR_RDQUEUE_ERROR_EN(x) ((x) << S_CL8_PAR_RDQUEUE_ERROR_EN)
16443 #define F_CL8_PAR_RDQUEUE_ERROR_EN    V_CL8_PAR_RDQUEUE_ERROR_EN(1U)
16444 
16445 #define S_CL7_PAR_RDQUEUE_ERROR_EN    7
16446 #define V_CL7_PAR_RDQUEUE_ERROR_EN(x) ((x) << S_CL7_PAR_RDQUEUE_ERROR_EN)
16447 #define F_CL7_PAR_RDQUEUE_ERROR_EN    V_CL7_PAR_RDQUEUE_ERROR_EN(1U)
16448 
16449 #define S_CL6_PAR_RDQUEUE_ERROR_EN    6
16450 #define V_CL6_PAR_RDQUEUE_ERROR_EN(x) ((x) << S_CL6_PAR_RDQUEUE_ERROR_EN)
16451 #define F_CL6_PAR_RDQUEUE_ERROR_EN    V_CL6_PAR_RDQUEUE_ERROR_EN(1U)
16452 
16453 #define S_CL5_PAR_RDQUEUE_ERROR_EN    5
16454 #define V_CL5_PAR_RDQUEUE_ERROR_EN(x) ((x) << S_CL5_PAR_RDQUEUE_ERROR_EN)
16455 #define F_CL5_PAR_RDQUEUE_ERROR_EN    V_CL5_PAR_RDQUEUE_ERROR_EN(1U)
16456 
16457 #define S_CL4_PAR_RDQUEUE_ERROR_EN    4
16458 #define V_CL4_PAR_RDQUEUE_ERROR_EN(x) ((x) << S_CL4_PAR_RDQUEUE_ERROR_EN)
16459 #define F_CL4_PAR_RDQUEUE_ERROR_EN    V_CL4_PAR_RDQUEUE_ERROR_EN(1U)
16460 
16461 #define S_CL3_PAR_RDQUEUE_ERROR_EN    3
16462 #define V_CL3_PAR_RDQUEUE_ERROR_EN(x) ((x) << S_CL3_PAR_RDQUEUE_ERROR_EN)
16463 #define F_CL3_PAR_RDQUEUE_ERROR_EN    V_CL3_PAR_RDQUEUE_ERROR_EN(1U)
16464 
16465 #define S_CL2_PAR_RDQUEUE_ERROR_EN    2
16466 #define V_CL2_PAR_RDQUEUE_ERROR_EN(x) ((x) << S_CL2_PAR_RDQUEUE_ERROR_EN)
16467 #define F_CL2_PAR_RDQUEUE_ERROR_EN    V_CL2_PAR_RDQUEUE_ERROR_EN(1U)
16468 
16469 #define S_CL1_PAR_RDQUEUE_ERROR_EN    1
16470 #define V_CL1_PAR_RDQUEUE_ERROR_EN(x) ((x) << S_CL1_PAR_RDQUEUE_ERROR_EN)
16471 #define F_CL1_PAR_RDQUEUE_ERROR_EN    V_CL1_PAR_RDQUEUE_ERROR_EN(1U)
16472 
16473 #define S_CL0_PAR_RDQUEUE_ERROR_EN    0
16474 #define V_CL0_PAR_RDQUEUE_ERROR_EN(x) ((x) << S_CL0_PAR_RDQUEUE_ERROR_EN)
16475 #define F_CL0_PAR_RDQUEUE_ERROR_EN    V_CL0_PAR_RDQUEUE_ERROR_EN(1U)
16476 
16477 #define A_MA_PARITY_ERROR_ENABLE1 0x77f0
16478 #define A_MA_PARITY_ERROR_STATUS 0x77f4
16479 
16480 #define S_TP_DMARBT_PAR_ERROR    31
16481 #define V_TP_DMARBT_PAR_ERROR(x) ((x) << S_TP_DMARBT_PAR_ERROR)
16482 #define F_TP_DMARBT_PAR_ERROR    V_TP_DMARBT_PAR_ERROR(1U)
16483 
16484 #define S_LOGIC_FIFO_PAR_ERROR    30
16485 #define V_LOGIC_FIFO_PAR_ERROR(x) ((x) << S_LOGIC_FIFO_PAR_ERROR)
16486 #define F_LOGIC_FIFO_PAR_ERROR    V_LOGIC_FIFO_PAR_ERROR(1U)
16487 
16488 #define S_ARB3_PAR_WRQUEUE_ERROR    29
16489 #define V_ARB3_PAR_WRQUEUE_ERROR(x) ((x) << S_ARB3_PAR_WRQUEUE_ERROR)
16490 #define F_ARB3_PAR_WRQUEUE_ERROR    V_ARB3_PAR_WRQUEUE_ERROR(1U)
16491 
16492 #define S_ARB2_PAR_WRQUEUE_ERROR    28
16493 #define V_ARB2_PAR_WRQUEUE_ERROR(x) ((x) << S_ARB2_PAR_WRQUEUE_ERROR)
16494 #define F_ARB2_PAR_WRQUEUE_ERROR    V_ARB2_PAR_WRQUEUE_ERROR(1U)
16495 
16496 #define S_ARB1_PAR_WRQUEUE_ERROR    27
16497 #define V_ARB1_PAR_WRQUEUE_ERROR(x) ((x) << S_ARB1_PAR_WRQUEUE_ERROR)
16498 #define F_ARB1_PAR_WRQUEUE_ERROR    V_ARB1_PAR_WRQUEUE_ERROR(1U)
16499 
16500 #define S_ARB0_PAR_WRQUEUE_ERROR    26
16501 #define V_ARB0_PAR_WRQUEUE_ERROR(x) ((x) << S_ARB0_PAR_WRQUEUE_ERROR)
16502 #define F_ARB0_PAR_WRQUEUE_ERROR    V_ARB0_PAR_WRQUEUE_ERROR(1U)
16503 
16504 #define S_ARB3_PAR_RDQUEUE_ERROR    25
16505 #define V_ARB3_PAR_RDQUEUE_ERROR(x) ((x) << S_ARB3_PAR_RDQUEUE_ERROR)
16506 #define F_ARB3_PAR_RDQUEUE_ERROR    V_ARB3_PAR_RDQUEUE_ERROR(1U)
16507 
16508 #define S_ARB2_PAR_RDQUEUE_ERROR    24
16509 #define V_ARB2_PAR_RDQUEUE_ERROR(x) ((x) << S_ARB2_PAR_RDQUEUE_ERROR)
16510 #define F_ARB2_PAR_RDQUEUE_ERROR    V_ARB2_PAR_RDQUEUE_ERROR(1U)
16511 
16512 #define S_ARB1_PAR_RDQUEUE_ERROR    23
16513 #define V_ARB1_PAR_RDQUEUE_ERROR(x) ((x) << S_ARB1_PAR_RDQUEUE_ERROR)
16514 #define F_ARB1_PAR_RDQUEUE_ERROR    V_ARB1_PAR_RDQUEUE_ERROR(1U)
16515 
16516 #define S_ARB0_PAR_RDQUEUE_ERROR    22
16517 #define V_ARB0_PAR_RDQUEUE_ERROR(x) ((x) << S_ARB0_PAR_RDQUEUE_ERROR)
16518 #define F_ARB0_PAR_RDQUEUE_ERROR    V_ARB0_PAR_RDQUEUE_ERROR(1U)
16519 
16520 #define S_CL10_PAR_WRQUEUE_ERROR    21
16521 #define V_CL10_PAR_WRQUEUE_ERROR(x) ((x) << S_CL10_PAR_WRQUEUE_ERROR)
16522 #define F_CL10_PAR_WRQUEUE_ERROR    V_CL10_PAR_WRQUEUE_ERROR(1U)
16523 
16524 #define S_CL9_PAR_WRQUEUE_ERROR    20
16525 #define V_CL9_PAR_WRQUEUE_ERROR(x) ((x) << S_CL9_PAR_WRQUEUE_ERROR)
16526 #define F_CL9_PAR_WRQUEUE_ERROR    V_CL9_PAR_WRQUEUE_ERROR(1U)
16527 
16528 #define S_CL8_PAR_WRQUEUE_ERROR    19
16529 #define V_CL8_PAR_WRQUEUE_ERROR(x) ((x) << S_CL8_PAR_WRQUEUE_ERROR)
16530 #define F_CL8_PAR_WRQUEUE_ERROR    V_CL8_PAR_WRQUEUE_ERROR(1U)
16531 
16532 #define S_CL7_PAR_WRQUEUE_ERROR    18
16533 #define V_CL7_PAR_WRQUEUE_ERROR(x) ((x) << S_CL7_PAR_WRQUEUE_ERROR)
16534 #define F_CL7_PAR_WRQUEUE_ERROR    V_CL7_PAR_WRQUEUE_ERROR(1U)
16535 
16536 #define S_CL6_PAR_WRQUEUE_ERROR    17
16537 #define V_CL6_PAR_WRQUEUE_ERROR(x) ((x) << S_CL6_PAR_WRQUEUE_ERROR)
16538 #define F_CL6_PAR_WRQUEUE_ERROR    V_CL6_PAR_WRQUEUE_ERROR(1U)
16539 
16540 #define S_CL5_PAR_WRQUEUE_ERROR    16
16541 #define V_CL5_PAR_WRQUEUE_ERROR(x) ((x) << S_CL5_PAR_WRQUEUE_ERROR)
16542 #define F_CL5_PAR_WRQUEUE_ERROR    V_CL5_PAR_WRQUEUE_ERROR(1U)
16543 
16544 #define S_CL4_PAR_WRQUEUE_ERROR    15
16545 #define V_CL4_PAR_WRQUEUE_ERROR(x) ((x) << S_CL4_PAR_WRQUEUE_ERROR)
16546 #define F_CL4_PAR_WRQUEUE_ERROR    V_CL4_PAR_WRQUEUE_ERROR(1U)
16547 
16548 #define S_CL3_PAR_WRQUEUE_ERROR    14
16549 #define V_CL3_PAR_WRQUEUE_ERROR(x) ((x) << S_CL3_PAR_WRQUEUE_ERROR)
16550 #define F_CL3_PAR_WRQUEUE_ERROR    V_CL3_PAR_WRQUEUE_ERROR(1U)
16551 
16552 #define S_CL2_PAR_WRQUEUE_ERROR    13
16553 #define V_CL2_PAR_WRQUEUE_ERROR(x) ((x) << S_CL2_PAR_WRQUEUE_ERROR)
16554 #define F_CL2_PAR_WRQUEUE_ERROR    V_CL2_PAR_WRQUEUE_ERROR(1U)
16555 
16556 #define S_CL1_PAR_WRQUEUE_ERROR    12
16557 #define V_CL1_PAR_WRQUEUE_ERROR(x) ((x) << S_CL1_PAR_WRQUEUE_ERROR)
16558 #define F_CL1_PAR_WRQUEUE_ERROR    V_CL1_PAR_WRQUEUE_ERROR(1U)
16559 
16560 #define S_CL0_PAR_WRQUEUE_ERROR    11
16561 #define V_CL0_PAR_WRQUEUE_ERROR(x) ((x) << S_CL0_PAR_WRQUEUE_ERROR)
16562 #define F_CL0_PAR_WRQUEUE_ERROR    V_CL0_PAR_WRQUEUE_ERROR(1U)
16563 
16564 #define S_CL10_PAR_RDQUEUE_ERROR    10
16565 #define V_CL10_PAR_RDQUEUE_ERROR(x) ((x) << S_CL10_PAR_RDQUEUE_ERROR)
16566 #define F_CL10_PAR_RDQUEUE_ERROR    V_CL10_PAR_RDQUEUE_ERROR(1U)
16567 
16568 #define S_CL9_PAR_RDQUEUE_ERROR    9
16569 #define V_CL9_PAR_RDQUEUE_ERROR(x) ((x) << S_CL9_PAR_RDQUEUE_ERROR)
16570 #define F_CL9_PAR_RDQUEUE_ERROR    V_CL9_PAR_RDQUEUE_ERROR(1U)
16571 
16572 #define S_CL8_PAR_RDQUEUE_ERROR    8
16573 #define V_CL8_PAR_RDQUEUE_ERROR(x) ((x) << S_CL8_PAR_RDQUEUE_ERROR)
16574 #define F_CL8_PAR_RDQUEUE_ERROR    V_CL8_PAR_RDQUEUE_ERROR(1U)
16575 
16576 #define S_CL7_PAR_RDQUEUE_ERROR    7
16577 #define V_CL7_PAR_RDQUEUE_ERROR(x) ((x) << S_CL7_PAR_RDQUEUE_ERROR)
16578 #define F_CL7_PAR_RDQUEUE_ERROR    V_CL7_PAR_RDQUEUE_ERROR(1U)
16579 
16580 #define S_CL6_PAR_RDQUEUE_ERROR    6
16581 #define V_CL6_PAR_RDQUEUE_ERROR(x) ((x) << S_CL6_PAR_RDQUEUE_ERROR)
16582 #define F_CL6_PAR_RDQUEUE_ERROR    V_CL6_PAR_RDQUEUE_ERROR(1U)
16583 
16584 #define S_CL5_PAR_RDQUEUE_ERROR    5
16585 #define V_CL5_PAR_RDQUEUE_ERROR(x) ((x) << S_CL5_PAR_RDQUEUE_ERROR)
16586 #define F_CL5_PAR_RDQUEUE_ERROR    V_CL5_PAR_RDQUEUE_ERROR(1U)
16587 
16588 #define S_CL4_PAR_RDQUEUE_ERROR    4
16589 #define V_CL4_PAR_RDQUEUE_ERROR(x) ((x) << S_CL4_PAR_RDQUEUE_ERROR)
16590 #define F_CL4_PAR_RDQUEUE_ERROR    V_CL4_PAR_RDQUEUE_ERROR(1U)
16591 
16592 #define S_CL3_PAR_RDQUEUE_ERROR    3
16593 #define V_CL3_PAR_RDQUEUE_ERROR(x) ((x) << S_CL3_PAR_RDQUEUE_ERROR)
16594 #define F_CL3_PAR_RDQUEUE_ERROR    V_CL3_PAR_RDQUEUE_ERROR(1U)
16595 
16596 #define S_CL2_PAR_RDQUEUE_ERROR    2
16597 #define V_CL2_PAR_RDQUEUE_ERROR(x) ((x) << S_CL2_PAR_RDQUEUE_ERROR)
16598 #define F_CL2_PAR_RDQUEUE_ERROR    V_CL2_PAR_RDQUEUE_ERROR(1U)
16599 
16600 #define S_CL1_PAR_RDQUEUE_ERROR    1
16601 #define V_CL1_PAR_RDQUEUE_ERROR(x) ((x) << S_CL1_PAR_RDQUEUE_ERROR)
16602 #define F_CL1_PAR_RDQUEUE_ERROR    V_CL1_PAR_RDQUEUE_ERROR(1U)
16603 
16604 #define S_CL0_PAR_RDQUEUE_ERROR    0
16605 #define V_CL0_PAR_RDQUEUE_ERROR(x) ((x) << S_CL0_PAR_RDQUEUE_ERROR)
16606 #define F_CL0_PAR_RDQUEUE_ERROR    V_CL0_PAR_RDQUEUE_ERROR(1U)
16607 
16608 #define A_MA_PARITY_ERROR_STATUS1 0x77f4
16609 #define A_MA_SGE_PCIE_COHERANCY_CTRL 0x77f8
16610 
16611 #define S_BONUS_REG    6
16612 #define M_BONUS_REG    0x3ffffffU
16613 #define V_BONUS_REG(x) ((x) << S_BONUS_REG)
16614 #define G_BONUS_REG(x) (((x) >> S_BONUS_REG) & M_BONUS_REG)
16615 
16616 #define S_COHERANCY_CMD_TYPE    4
16617 #define M_COHERANCY_CMD_TYPE    0x3U
16618 #define V_COHERANCY_CMD_TYPE(x) ((x) << S_COHERANCY_CMD_TYPE)
16619 #define G_COHERANCY_CMD_TYPE(x) (((x) >> S_COHERANCY_CMD_TYPE) & M_COHERANCY_CMD_TYPE)
16620 
16621 #define S_COHERANCY_THREAD_NUM    1
16622 #define M_COHERANCY_THREAD_NUM    0x7U
16623 #define V_COHERANCY_THREAD_NUM(x) ((x) << S_COHERANCY_THREAD_NUM)
16624 #define G_COHERANCY_THREAD_NUM(x) (((x) >> S_COHERANCY_THREAD_NUM) & M_COHERANCY_THREAD_NUM)
16625 
16626 #define S_COHERANCY_ENABLE    0
16627 #define V_COHERANCY_ENABLE(x) ((x) << S_COHERANCY_ENABLE)
16628 #define F_COHERANCY_ENABLE    V_COHERANCY_ENABLE(1U)
16629 
16630 #define A_MA_ERROR_ENABLE 0x77fc
16631 
16632 #define S_UE_ENABLE    0
16633 #define V_UE_ENABLE(x) ((x) << S_UE_ENABLE)
16634 #define F_UE_ENABLE    V_UE_ENABLE(1U)
16635 
16636 #define S_FUTURE_EXPANSION    1
16637 #define M_FUTURE_EXPANSION    0x7fffffffU
16638 #define V_FUTURE_EXPANSION(x) ((x) << S_FUTURE_EXPANSION)
16639 #define G_FUTURE_EXPANSION(x) (((x) >> S_FUTURE_EXPANSION) & M_FUTURE_EXPANSION)
16640 
16641 #define S_FUTURE_EXPANSION_EE    1
16642 #define M_FUTURE_EXPANSION_EE    0x7fffffffU
16643 #define V_FUTURE_EXPANSION_EE(x) ((x) << S_FUTURE_EXPANSION_EE)
16644 #define G_FUTURE_EXPANSION_EE(x) (((x) >> S_FUTURE_EXPANSION_EE) & M_FUTURE_EXPANSION_EE)
16645 
16646 #define A_MA_PARITY_ERROR_ENABLE2 0x7800
16647 
16648 #define S_ARB4_PAR_WRQUEUE_ERROR_EN    1
16649 #define V_ARB4_PAR_WRQUEUE_ERROR_EN(x) ((x) << S_ARB4_PAR_WRQUEUE_ERROR_EN)
16650 #define F_ARB4_PAR_WRQUEUE_ERROR_EN    V_ARB4_PAR_WRQUEUE_ERROR_EN(1U)
16651 
16652 #define S_ARB4_PAR_RDQUEUE_ERROR_EN    0
16653 #define V_ARB4_PAR_RDQUEUE_ERROR_EN(x) ((x) << S_ARB4_PAR_RDQUEUE_ERROR_EN)
16654 #define F_ARB4_PAR_RDQUEUE_ERROR_EN    V_ARB4_PAR_RDQUEUE_ERROR_EN(1U)
16655 
16656 #define A_MA_PARITY_ERROR_STATUS2 0x7804
16657 
16658 #define S_ARB4_PAR_WRQUEUE_ERROR    1
16659 #define V_ARB4_PAR_WRQUEUE_ERROR(x) ((x) << S_ARB4_PAR_WRQUEUE_ERROR)
16660 #define F_ARB4_PAR_WRQUEUE_ERROR    V_ARB4_PAR_WRQUEUE_ERROR(1U)
16661 
16662 #define S_ARB4_PAR_RDQUEUE_ERROR    0
16663 #define V_ARB4_PAR_RDQUEUE_ERROR(x) ((x) << S_ARB4_PAR_RDQUEUE_ERROR)
16664 #define F_ARB4_PAR_RDQUEUE_ERROR    V_ARB4_PAR_RDQUEUE_ERROR(1U)
16665 
16666 #define A_MA_EXT_MEMORY1_BAR 0x7808
16667 
16668 #define S_EXT_MEM1_BASE    16
16669 #define M_EXT_MEM1_BASE    0xfffU
16670 #define V_EXT_MEM1_BASE(x) ((x) << S_EXT_MEM1_BASE)
16671 #define G_EXT_MEM1_BASE(x) (((x) >> S_EXT_MEM1_BASE) & M_EXT_MEM1_BASE)
16672 
16673 #define S_EXT_MEM1_SIZE    0
16674 #define M_EXT_MEM1_SIZE    0xfffU
16675 #define V_EXT_MEM1_SIZE(x) ((x) << S_EXT_MEM1_SIZE)
16676 #define G_EXT_MEM1_SIZE(x) (((x) >> S_EXT_MEM1_SIZE) & M_EXT_MEM1_SIZE)
16677 
16678 #define A_MA_PMTX_THROTTLE 0x780c
16679 
16680 #define S_FL_ENABLE    31
16681 #define V_FL_ENABLE(x) ((x) << S_FL_ENABLE)
16682 #define F_FL_ENABLE    V_FL_ENABLE(1U)
16683 
16684 #define S_FL_LIMIT    0
16685 #define M_FL_LIMIT    0xffU
16686 #define V_FL_LIMIT(x) ((x) << S_FL_LIMIT)
16687 #define G_FL_LIMIT(x) (((x) >> S_FL_LIMIT) & M_FL_LIMIT)
16688 
16689 #define A_MA_PMRX_THROTTLE 0x7810
16690 #define A_MA_SGE_TH0_WRDATA_CNT 0x7814
16691 #define A_MA_SGE_TH1_WRDATA_CNT 0x7818
16692 #define A_MA_ULPTX_WRDATA_CNT 0x781c
16693 #define A_MA_ULPRX_WRDATA_CNT 0x7820
16694 #define A_MA_ULPTXRX_WRDATA_CNT 0x7824
16695 #define A_MA_TP_TH0_WRDATA_CNT 0x7828
16696 #define A_MA_TP_TH1_WRDATA_CNT 0x782c
16697 #define A_MA_LE_WRDATA_CNT 0x7830
16698 #define A_MA_CIM_WRDATA_CNT 0x7834
16699 #define A_MA_PCIE_WRDATA_CNT 0x7838
16700 #define A_MA_PMTX_WRDATA_CNT 0x783c
16701 #define A_MA_PMRX_WRDATA_CNT 0x7840
16702 #define A_MA_HMA_WRDATA_CNT 0x7844
16703 #define A_MA_SGE_TH0_RDDATA_CNT 0x7848
16704 #define A_MA_SGE_TH1_RDDATA_CNT 0x784c
16705 #define A_MA_ULPTX_RDDATA_CNT 0x7850
16706 #define A_MA_ULPRX_RDDATA_CNT 0x7854
16707 #define A_MA_ULPTXRX_RDDATA_CNT 0x7858
16708 #define A_MA_TP_TH0_RDDATA_CNT 0x785c
16709 #define A_MA_TP_TH1_RDDATA_CNT 0x7860
16710 #define A_MA_LE_RDDATA_CNT 0x7864
16711 #define A_MA_CIM_RDDATA_CNT 0x7868
16712 #define A_MA_PCIE_RDDATA_CNT 0x786c
16713 #define A_MA_PMTX_RDDATA_CNT 0x7870
16714 #define A_MA_PMRX_RDDATA_CNT 0x7874
16715 #define A_MA_HMA_RDDATA_CNT 0x7878
16716 #define A_MA_EDRAM0_WRDATA_CNT1 0x787c
16717 #define A_MA_EXIT_ADDR_FAULT 0x787c
16718 
16719 #define S_EXIT_ADDR_FAULT    0
16720 #define V_EXIT_ADDR_FAULT(x) ((x) << S_EXIT_ADDR_FAULT)
16721 #define F_EXIT_ADDR_FAULT    V_EXIT_ADDR_FAULT(1U)
16722 
16723 #define A_MA_EDRAM0_WRDATA_CNT0 0x7880
16724 #define A_MA_DDR_DEVICE_CFG 0x7880
16725 
16726 #define S_MEM_WIDTH    1
16727 #define M_MEM_WIDTH    0x7U
16728 #define V_MEM_WIDTH(x) ((x) << S_MEM_WIDTH)
16729 #define G_MEM_WIDTH(x) (((x) >> S_MEM_WIDTH) & M_MEM_WIDTH)
16730 
16731 #define S_DDR_MODE    0
16732 #define V_DDR_MODE(x) ((x) << S_DDR_MODE)
16733 #define F_DDR_MODE    V_DDR_MODE(1U)
16734 
16735 #define A_MA_EDRAM1_WRDATA_CNT1 0x7884
16736 #define A_MA_EDRAM1_WRDATA_CNT0 0x7888
16737 #define A_MA_EXT_MEMORY0_WRDATA_CNT1 0x788c
16738 #define A_MA_EXT_MEMORY0_WRDATA_CNT0 0x7890
16739 #define A_MA_HOST_MEMORY_WRDATA_CNT1 0x7894
16740 #define A_MA_HOST_MEMORY_WRDATA_CNT0 0x7898
16741 #define A_MA_EXT_MEMORY1_WRDATA_CNT1 0x789c
16742 #define A_MA_EXT_MEMORY1_WRDATA_CNT0 0x78a0
16743 #define A_MA_EDRAM0_RDDATA_CNT1 0x78a4
16744 #define A_MA_EDRAM0_RDDATA_CNT0 0x78a8
16745 #define A_MA_EDRAM1_RDDATA_CNT1 0x78ac
16746 #define A_MA_EDRAM1_RDDATA_CNT0 0x78b0
16747 #define A_MA_EXT_MEMORY0_RDDATA_CNT1 0x78b4
16748 #define A_MA_EXT_MEMORY0_RDDATA_CNT0 0x78b8
16749 #define A_MA_HOST_MEMORY_RDDATA_CNT1 0x78bc
16750 #define A_MA_HOST_MEMORY_RDDATA_CNT0 0x78c0
16751 #define A_MA_EXT_MEMORY1_RDDATA_CNT1 0x78c4
16752 #define A_MA_EXT_MEMORY1_RDDATA_CNT0 0x78c8
16753 #define A_MA_TIMEOUT_CFG 0x78cc
16754 
16755 #define S_CLR    31
16756 #define V_CLR(x) ((x) << S_CLR)
16757 #define F_CLR    V_CLR(1U)
16758 
16759 #define S_CNT_LOCK    30
16760 #define V_CNT_LOCK(x) ((x) << S_CNT_LOCK)
16761 #define F_CNT_LOCK    V_CNT_LOCK(1U)
16762 
16763 #define S_WRN    24
16764 #define V_WRN(x) ((x) << S_WRN)
16765 #define F_WRN    V_WRN(1U)
16766 
16767 #define S_DIR    23
16768 #define V_DIR(x) ((x) << S_DIR)
16769 #define F_DIR    V_DIR(1U)
16770 
16771 #define S_TO_BUS    22
16772 #define V_TO_BUS(x) ((x) << S_TO_BUS)
16773 #define F_TO_BUS    V_TO_BUS(1U)
16774 
16775 #define S_CLIENT    16
16776 #define M_CLIENT    0xfU
16777 #define V_CLIENT(x) ((x) << S_CLIENT)
16778 #define G_CLIENT(x) (((x) >> S_CLIENT) & M_CLIENT)
16779 
16780 #define S_DELAY    0
16781 #define M_DELAY    0xffffU
16782 #define V_DELAY(x) ((x) << S_DELAY)
16783 #define G_DELAY(x) (((x) >> S_DELAY) & M_DELAY)
16784 
16785 #define A_MA_TIMEOUT_CNT 0x78d0
16786 
16787 #define S_CNT_VAL    0
16788 #define M_CNT_VAL    0xffffU
16789 #define V_CNT_VAL(x) ((x) << S_CNT_VAL)
16790 #define G_CNT_VAL(x) (((x) >> S_CNT_VAL) & M_CNT_VAL)
16791 
16792 #define A_MA_WRITE_TIMEOUT_ERROR_ENABLE 0x78d4
16793 
16794 #define S_FUTURE_CEXPANSION    29
16795 #define M_FUTURE_CEXPANSION    0x7U
16796 #define V_FUTURE_CEXPANSION(x) ((x) << S_FUTURE_CEXPANSION)
16797 #define G_FUTURE_CEXPANSION(x) (((x) >> S_FUTURE_CEXPANSION) & M_FUTURE_CEXPANSION)
16798 
16799 #define S_CL12_WR_CMD_TO_EN    28
16800 #define V_CL12_WR_CMD_TO_EN(x) ((x) << S_CL12_WR_CMD_TO_EN)
16801 #define F_CL12_WR_CMD_TO_EN    V_CL12_WR_CMD_TO_EN(1U)
16802 
16803 #define S_CL11_WR_CMD_TO_EN    27
16804 #define V_CL11_WR_CMD_TO_EN(x) ((x) << S_CL11_WR_CMD_TO_EN)
16805 #define F_CL11_WR_CMD_TO_EN    V_CL11_WR_CMD_TO_EN(1U)
16806 
16807 #define S_CL10_WR_CMD_TO_EN    26
16808 #define V_CL10_WR_CMD_TO_EN(x) ((x) << S_CL10_WR_CMD_TO_EN)
16809 #define F_CL10_WR_CMD_TO_EN    V_CL10_WR_CMD_TO_EN(1U)
16810 
16811 #define S_CL9_WR_CMD_TO_EN    25
16812 #define V_CL9_WR_CMD_TO_EN(x) ((x) << S_CL9_WR_CMD_TO_EN)
16813 #define F_CL9_WR_CMD_TO_EN    V_CL9_WR_CMD_TO_EN(1U)
16814 
16815 #define S_CL8_WR_CMD_TO_EN    24
16816 #define V_CL8_WR_CMD_TO_EN(x) ((x) << S_CL8_WR_CMD_TO_EN)
16817 #define F_CL8_WR_CMD_TO_EN    V_CL8_WR_CMD_TO_EN(1U)
16818 
16819 #define S_CL7_WR_CMD_TO_EN    23
16820 #define V_CL7_WR_CMD_TO_EN(x) ((x) << S_CL7_WR_CMD_TO_EN)
16821 #define F_CL7_WR_CMD_TO_EN    V_CL7_WR_CMD_TO_EN(1U)
16822 
16823 #define S_CL6_WR_CMD_TO_EN    22
16824 #define V_CL6_WR_CMD_TO_EN(x) ((x) << S_CL6_WR_CMD_TO_EN)
16825 #define F_CL6_WR_CMD_TO_EN    V_CL6_WR_CMD_TO_EN(1U)
16826 
16827 #define S_CL5_WR_CMD_TO_EN    21
16828 #define V_CL5_WR_CMD_TO_EN(x) ((x) << S_CL5_WR_CMD_TO_EN)
16829 #define F_CL5_WR_CMD_TO_EN    V_CL5_WR_CMD_TO_EN(1U)
16830 
16831 #define S_CL4_WR_CMD_TO_EN    20
16832 #define V_CL4_WR_CMD_TO_EN(x) ((x) << S_CL4_WR_CMD_TO_EN)
16833 #define F_CL4_WR_CMD_TO_EN    V_CL4_WR_CMD_TO_EN(1U)
16834 
16835 #define S_CL3_WR_CMD_TO_EN    19
16836 #define V_CL3_WR_CMD_TO_EN(x) ((x) << S_CL3_WR_CMD_TO_EN)
16837 #define F_CL3_WR_CMD_TO_EN    V_CL3_WR_CMD_TO_EN(1U)
16838 
16839 #define S_CL2_WR_CMD_TO_EN    18
16840 #define V_CL2_WR_CMD_TO_EN(x) ((x) << S_CL2_WR_CMD_TO_EN)
16841 #define F_CL2_WR_CMD_TO_EN    V_CL2_WR_CMD_TO_EN(1U)
16842 
16843 #define S_CL1_WR_CMD_TO_EN    17
16844 #define V_CL1_WR_CMD_TO_EN(x) ((x) << S_CL1_WR_CMD_TO_EN)
16845 #define F_CL1_WR_CMD_TO_EN    V_CL1_WR_CMD_TO_EN(1U)
16846 
16847 #define S_CL0_WR_CMD_TO_EN    16
16848 #define V_CL0_WR_CMD_TO_EN(x) ((x) << S_CL0_WR_CMD_TO_EN)
16849 #define F_CL0_WR_CMD_TO_EN    V_CL0_WR_CMD_TO_EN(1U)
16850 
16851 #define S_FUTURE_DEXPANSION    13
16852 #define M_FUTURE_DEXPANSION    0x7U
16853 #define V_FUTURE_DEXPANSION(x) ((x) << S_FUTURE_DEXPANSION)
16854 #define G_FUTURE_DEXPANSION(x) (((x) >> S_FUTURE_DEXPANSION) & M_FUTURE_DEXPANSION)
16855 
16856 #define S_CL12_WR_DATA_TO_EN    12
16857 #define V_CL12_WR_DATA_TO_EN(x) ((x) << S_CL12_WR_DATA_TO_EN)
16858 #define F_CL12_WR_DATA_TO_EN    V_CL12_WR_DATA_TO_EN(1U)
16859 
16860 #define S_CL11_WR_DATA_TO_EN    11
16861 #define V_CL11_WR_DATA_TO_EN(x) ((x) << S_CL11_WR_DATA_TO_EN)
16862 #define F_CL11_WR_DATA_TO_EN    V_CL11_WR_DATA_TO_EN(1U)
16863 
16864 #define S_CL10_WR_DATA_TO_EN    10
16865 #define V_CL10_WR_DATA_TO_EN(x) ((x) << S_CL10_WR_DATA_TO_EN)
16866 #define F_CL10_WR_DATA_TO_EN    V_CL10_WR_DATA_TO_EN(1U)
16867 
16868 #define S_CL9_WR_DATA_TO_EN    9
16869 #define V_CL9_WR_DATA_TO_EN(x) ((x) << S_CL9_WR_DATA_TO_EN)
16870 #define F_CL9_WR_DATA_TO_EN    V_CL9_WR_DATA_TO_EN(1U)
16871 
16872 #define S_CL8_WR_DATA_TO_EN    8
16873 #define V_CL8_WR_DATA_TO_EN(x) ((x) << S_CL8_WR_DATA_TO_EN)
16874 #define F_CL8_WR_DATA_TO_EN    V_CL8_WR_DATA_TO_EN(1U)
16875 
16876 #define S_CL7_WR_DATA_TO_EN    7
16877 #define V_CL7_WR_DATA_TO_EN(x) ((x) << S_CL7_WR_DATA_TO_EN)
16878 #define F_CL7_WR_DATA_TO_EN    V_CL7_WR_DATA_TO_EN(1U)
16879 
16880 #define S_CL6_WR_DATA_TO_EN    6
16881 #define V_CL6_WR_DATA_TO_EN(x) ((x) << S_CL6_WR_DATA_TO_EN)
16882 #define F_CL6_WR_DATA_TO_EN    V_CL6_WR_DATA_TO_EN(1U)
16883 
16884 #define S_CL5_WR_DATA_TO_EN    5
16885 #define V_CL5_WR_DATA_TO_EN(x) ((x) << S_CL5_WR_DATA_TO_EN)
16886 #define F_CL5_WR_DATA_TO_EN    V_CL5_WR_DATA_TO_EN(1U)
16887 
16888 #define S_CL4_WR_DATA_TO_EN    4
16889 #define V_CL4_WR_DATA_TO_EN(x) ((x) << S_CL4_WR_DATA_TO_EN)
16890 #define F_CL4_WR_DATA_TO_EN    V_CL4_WR_DATA_TO_EN(1U)
16891 
16892 #define S_CL3_WR_DATA_TO_EN    3
16893 #define V_CL3_WR_DATA_TO_EN(x) ((x) << S_CL3_WR_DATA_TO_EN)
16894 #define F_CL3_WR_DATA_TO_EN    V_CL3_WR_DATA_TO_EN(1U)
16895 
16896 #define S_CL2_WR_DATA_TO_EN    2
16897 #define V_CL2_WR_DATA_TO_EN(x) ((x) << S_CL2_WR_DATA_TO_EN)
16898 #define F_CL2_WR_DATA_TO_EN    V_CL2_WR_DATA_TO_EN(1U)
16899 
16900 #define S_CL1_WR_DATA_TO_EN    1
16901 #define V_CL1_WR_DATA_TO_EN(x) ((x) << S_CL1_WR_DATA_TO_EN)
16902 #define F_CL1_WR_DATA_TO_EN    V_CL1_WR_DATA_TO_EN(1U)
16903 
16904 #define S_CL0_WR_DATA_TO_EN    0
16905 #define V_CL0_WR_DATA_TO_EN(x) ((x) << S_CL0_WR_DATA_TO_EN)
16906 #define F_CL0_WR_DATA_TO_EN    V_CL0_WR_DATA_TO_EN(1U)
16907 
16908 #define S_FUTURE_CEXPANSION_WTE    29
16909 #define M_FUTURE_CEXPANSION_WTE    0x7U
16910 #define V_FUTURE_CEXPANSION_WTE(x) ((x) << S_FUTURE_CEXPANSION_WTE)
16911 #define G_FUTURE_CEXPANSION_WTE(x) (((x) >> S_FUTURE_CEXPANSION_WTE) & M_FUTURE_CEXPANSION_WTE)
16912 
16913 #define S_FUTURE_DEXPANSION_WTE    13
16914 #define M_FUTURE_DEXPANSION_WTE    0x7U
16915 #define V_FUTURE_DEXPANSION_WTE(x) ((x) << S_FUTURE_DEXPANSION_WTE)
16916 #define G_FUTURE_DEXPANSION_WTE(x) (((x) >> S_FUTURE_DEXPANSION_WTE) & M_FUTURE_DEXPANSION_WTE)
16917 
16918 #define A_MA_WRITE_TIMEOUT_ERROR_STATUS 0x78d8
16919 
16920 #define S_CL12_WR_CMD_TO_ERROR    28
16921 #define V_CL12_WR_CMD_TO_ERROR(x) ((x) << S_CL12_WR_CMD_TO_ERROR)
16922 #define F_CL12_WR_CMD_TO_ERROR    V_CL12_WR_CMD_TO_ERROR(1U)
16923 
16924 #define S_CL11_WR_CMD_TO_ERROR    27
16925 #define V_CL11_WR_CMD_TO_ERROR(x) ((x) << S_CL11_WR_CMD_TO_ERROR)
16926 #define F_CL11_WR_CMD_TO_ERROR    V_CL11_WR_CMD_TO_ERROR(1U)
16927 
16928 #define S_CL10_WR_CMD_TO_ERROR    26
16929 #define V_CL10_WR_CMD_TO_ERROR(x) ((x) << S_CL10_WR_CMD_TO_ERROR)
16930 #define F_CL10_WR_CMD_TO_ERROR    V_CL10_WR_CMD_TO_ERROR(1U)
16931 
16932 #define S_CL9_WR_CMD_TO_ERROR    25
16933 #define V_CL9_WR_CMD_TO_ERROR(x) ((x) << S_CL9_WR_CMD_TO_ERROR)
16934 #define F_CL9_WR_CMD_TO_ERROR    V_CL9_WR_CMD_TO_ERROR(1U)
16935 
16936 #define S_CL8_WR_CMD_TO_ERROR    24
16937 #define V_CL8_WR_CMD_TO_ERROR(x) ((x) << S_CL8_WR_CMD_TO_ERROR)
16938 #define F_CL8_WR_CMD_TO_ERROR    V_CL8_WR_CMD_TO_ERROR(1U)
16939 
16940 #define S_CL7_WR_CMD_TO_ERROR    23
16941 #define V_CL7_WR_CMD_TO_ERROR(x) ((x) << S_CL7_WR_CMD_TO_ERROR)
16942 #define F_CL7_WR_CMD_TO_ERROR    V_CL7_WR_CMD_TO_ERROR(1U)
16943 
16944 #define S_CL6_WR_CMD_TO_ERROR    22
16945 #define V_CL6_WR_CMD_TO_ERROR(x) ((x) << S_CL6_WR_CMD_TO_ERROR)
16946 #define F_CL6_WR_CMD_TO_ERROR    V_CL6_WR_CMD_TO_ERROR(1U)
16947 
16948 #define S_CL5_WR_CMD_TO_ERROR    21
16949 #define V_CL5_WR_CMD_TO_ERROR(x) ((x) << S_CL5_WR_CMD_TO_ERROR)
16950 #define F_CL5_WR_CMD_TO_ERROR    V_CL5_WR_CMD_TO_ERROR(1U)
16951 
16952 #define S_CL4_WR_CMD_TO_ERROR    20
16953 #define V_CL4_WR_CMD_TO_ERROR(x) ((x) << S_CL4_WR_CMD_TO_ERROR)
16954 #define F_CL4_WR_CMD_TO_ERROR    V_CL4_WR_CMD_TO_ERROR(1U)
16955 
16956 #define S_CL3_WR_CMD_TO_ERROR    19
16957 #define V_CL3_WR_CMD_TO_ERROR(x) ((x) << S_CL3_WR_CMD_TO_ERROR)
16958 #define F_CL3_WR_CMD_TO_ERROR    V_CL3_WR_CMD_TO_ERROR(1U)
16959 
16960 #define S_CL2_WR_CMD_TO_ERROR    18
16961 #define V_CL2_WR_CMD_TO_ERROR(x) ((x) << S_CL2_WR_CMD_TO_ERROR)
16962 #define F_CL2_WR_CMD_TO_ERROR    V_CL2_WR_CMD_TO_ERROR(1U)
16963 
16964 #define S_CL1_WR_CMD_TO_ERROR    17
16965 #define V_CL1_WR_CMD_TO_ERROR(x) ((x) << S_CL1_WR_CMD_TO_ERROR)
16966 #define F_CL1_WR_CMD_TO_ERROR    V_CL1_WR_CMD_TO_ERROR(1U)
16967 
16968 #define S_CL0_WR_CMD_TO_ERROR    16
16969 #define V_CL0_WR_CMD_TO_ERROR(x) ((x) << S_CL0_WR_CMD_TO_ERROR)
16970 #define F_CL0_WR_CMD_TO_ERROR    V_CL0_WR_CMD_TO_ERROR(1U)
16971 
16972 #define S_CL12_WR_DATA_TO_ERROR    12
16973 #define V_CL12_WR_DATA_TO_ERROR(x) ((x) << S_CL12_WR_DATA_TO_ERROR)
16974 #define F_CL12_WR_DATA_TO_ERROR    V_CL12_WR_DATA_TO_ERROR(1U)
16975 
16976 #define S_CL11_WR_DATA_TO_ERROR    11
16977 #define V_CL11_WR_DATA_TO_ERROR(x) ((x) << S_CL11_WR_DATA_TO_ERROR)
16978 #define F_CL11_WR_DATA_TO_ERROR    V_CL11_WR_DATA_TO_ERROR(1U)
16979 
16980 #define S_CL10_WR_DATA_TO_ERROR    10
16981 #define V_CL10_WR_DATA_TO_ERROR(x) ((x) << S_CL10_WR_DATA_TO_ERROR)
16982 #define F_CL10_WR_DATA_TO_ERROR    V_CL10_WR_DATA_TO_ERROR(1U)
16983 
16984 #define S_CL9_WR_DATA_TO_ERROR    9
16985 #define V_CL9_WR_DATA_TO_ERROR(x) ((x) << S_CL9_WR_DATA_TO_ERROR)
16986 #define F_CL9_WR_DATA_TO_ERROR    V_CL9_WR_DATA_TO_ERROR(1U)
16987 
16988 #define S_CL8_WR_DATA_TO_ERROR    8
16989 #define V_CL8_WR_DATA_TO_ERROR(x) ((x) << S_CL8_WR_DATA_TO_ERROR)
16990 #define F_CL8_WR_DATA_TO_ERROR    V_CL8_WR_DATA_TO_ERROR(1U)
16991 
16992 #define S_CL7_WR_DATA_TO_ERROR    7
16993 #define V_CL7_WR_DATA_TO_ERROR(x) ((x) << S_CL7_WR_DATA_TO_ERROR)
16994 #define F_CL7_WR_DATA_TO_ERROR    V_CL7_WR_DATA_TO_ERROR(1U)
16995 
16996 #define S_CL6_WR_DATA_TO_ERROR    6
16997 #define V_CL6_WR_DATA_TO_ERROR(x) ((x) << S_CL6_WR_DATA_TO_ERROR)
16998 #define F_CL6_WR_DATA_TO_ERROR    V_CL6_WR_DATA_TO_ERROR(1U)
16999 
17000 #define S_CL5_WR_DATA_TO_ERROR    5
17001 #define V_CL5_WR_DATA_TO_ERROR(x) ((x) << S_CL5_WR_DATA_TO_ERROR)
17002 #define F_CL5_WR_DATA_TO_ERROR    V_CL5_WR_DATA_TO_ERROR(1U)
17003 
17004 #define S_CL4_WR_DATA_TO_ERROR    4
17005 #define V_CL4_WR_DATA_TO_ERROR(x) ((x) << S_CL4_WR_DATA_TO_ERROR)
17006 #define F_CL4_WR_DATA_TO_ERROR    V_CL4_WR_DATA_TO_ERROR(1U)
17007 
17008 #define S_CL3_WR_DATA_TO_ERROR    3
17009 #define V_CL3_WR_DATA_TO_ERROR(x) ((x) << S_CL3_WR_DATA_TO_ERROR)
17010 #define F_CL3_WR_DATA_TO_ERROR    V_CL3_WR_DATA_TO_ERROR(1U)
17011 
17012 #define S_CL2_WR_DATA_TO_ERROR    2
17013 #define V_CL2_WR_DATA_TO_ERROR(x) ((x) << S_CL2_WR_DATA_TO_ERROR)
17014 #define F_CL2_WR_DATA_TO_ERROR    V_CL2_WR_DATA_TO_ERROR(1U)
17015 
17016 #define S_CL1_WR_DATA_TO_ERROR    1
17017 #define V_CL1_WR_DATA_TO_ERROR(x) ((x) << S_CL1_WR_DATA_TO_ERROR)
17018 #define F_CL1_WR_DATA_TO_ERROR    V_CL1_WR_DATA_TO_ERROR(1U)
17019 
17020 #define S_CL0_WR_DATA_TO_ERROR    0
17021 #define V_CL0_WR_DATA_TO_ERROR(x) ((x) << S_CL0_WR_DATA_TO_ERROR)
17022 #define F_CL0_WR_DATA_TO_ERROR    V_CL0_WR_DATA_TO_ERROR(1U)
17023 
17024 #define S_FUTURE_CEXPANSION_WTS    29
17025 #define M_FUTURE_CEXPANSION_WTS    0x7U
17026 #define V_FUTURE_CEXPANSION_WTS(x) ((x) << S_FUTURE_CEXPANSION_WTS)
17027 #define G_FUTURE_CEXPANSION_WTS(x) (((x) >> S_FUTURE_CEXPANSION_WTS) & M_FUTURE_CEXPANSION_WTS)
17028 
17029 #define S_FUTURE_DEXPANSION_WTS    13
17030 #define M_FUTURE_DEXPANSION_WTS    0x7U
17031 #define V_FUTURE_DEXPANSION_WTS(x) ((x) << S_FUTURE_DEXPANSION_WTS)
17032 #define G_FUTURE_DEXPANSION_WTS(x) (((x) >> S_FUTURE_DEXPANSION_WTS) & M_FUTURE_DEXPANSION_WTS)
17033 
17034 #define A_MA_READ_TIMEOUT_ERROR_ENABLE 0x78dc
17035 
17036 #define S_CL12_RD_CMD_TO_EN    28
17037 #define V_CL12_RD_CMD_TO_EN(x) ((x) << S_CL12_RD_CMD_TO_EN)
17038 #define F_CL12_RD_CMD_TO_EN    V_CL12_RD_CMD_TO_EN(1U)
17039 
17040 #define S_CL11_RD_CMD_TO_EN    27
17041 #define V_CL11_RD_CMD_TO_EN(x) ((x) << S_CL11_RD_CMD_TO_EN)
17042 #define F_CL11_RD_CMD_TO_EN    V_CL11_RD_CMD_TO_EN(1U)
17043 
17044 #define S_CL10_RD_CMD_TO_EN    26
17045 #define V_CL10_RD_CMD_TO_EN(x) ((x) << S_CL10_RD_CMD_TO_EN)
17046 #define F_CL10_RD_CMD_TO_EN    V_CL10_RD_CMD_TO_EN(1U)
17047 
17048 #define S_CL9_RD_CMD_TO_EN    25
17049 #define V_CL9_RD_CMD_TO_EN(x) ((x) << S_CL9_RD_CMD_TO_EN)
17050 #define F_CL9_RD_CMD_TO_EN    V_CL9_RD_CMD_TO_EN(1U)
17051 
17052 #define S_CL8_RD_CMD_TO_EN    24
17053 #define V_CL8_RD_CMD_TO_EN(x) ((x) << S_CL8_RD_CMD_TO_EN)
17054 #define F_CL8_RD_CMD_TO_EN    V_CL8_RD_CMD_TO_EN(1U)
17055 
17056 #define S_CL7_RD_CMD_TO_EN    23
17057 #define V_CL7_RD_CMD_TO_EN(x) ((x) << S_CL7_RD_CMD_TO_EN)
17058 #define F_CL7_RD_CMD_TO_EN    V_CL7_RD_CMD_TO_EN(1U)
17059 
17060 #define S_CL6_RD_CMD_TO_EN    22
17061 #define V_CL6_RD_CMD_TO_EN(x) ((x) << S_CL6_RD_CMD_TO_EN)
17062 #define F_CL6_RD_CMD_TO_EN    V_CL6_RD_CMD_TO_EN(1U)
17063 
17064 #define S_CL5_RD_CMD_TO_EN    21
17065 #define V_CL5_RD_CMD_TO_EN(x) ((x) << S_CL5_RD_CMD_TO_EN)
17066 #define F_CL5_RD_CMD_TO_EN    V_CL5_RD_CMD_TO_EN(1U)
17067 
17068 #define S_CL4_RD_CMD_TO_EN    20
17069 #define V_CL4_RD_CMD_TO_EN(x) ((x) << S_CL4_RD_CMD_TO_EN)
17070 #define F_CL4_RD_CMD_TO_EN    V_CL4_RD_CMD_TO_EN(1U)
17071 
17072 #define S_CL3_RD_CMD_TO_EN    19
17073 #define V_CL3_RD_CMD_TO_EN(x) ((x) << S_CL3_RD_CMD_TO_EN)
17074 #define F_CL3_RD_CMD_TO_EN    V_CL3_RD_CMD_TO_EN(1U)
17075 
17076 #define S_CL2_RD_CMD_TO_EN    18
17077 #define V_CL2_RD_CMD_TO_EN(x) ((x) << S_CL2_RD_CMD_TO_EN)
17078 #define F_CL2_RD_CMD_TO_EN    V_CL2_RD_CMD_TO_EN(1U)
17079 
17080 #define S_CL1_RD_CMD_TO_EN    17
17081 #define V_CL1_RD_CMD_TO_EN(x) ((x) << S_CL1_RD_CMD_TO_EN)
17082 #define F_CL1_RD_CMD_TO_EN    V_CL1_RD_CMD_TO_EN(1U)
17083 
17084 #define S_CL0_RD_CMD_TO_EN    16
17085 #define V_CL0_RD_CMD_TO_EN(x) ((x) << S_CL0_RD_CMD_TO_EN)
17086 #define F_CL0_RD_CMD_TO_EN    V_CL0_RD_CMD_TO_EN(1U)
17087 
17088 #define S_CL12_RD_DATA_TO_EN    12
17089 #define V_CL12_RD_DATA_TO_EN(x) ((x) << S_CL12_RD_DATA_TO_EN)
17090 #define F_CL12_RD_DATA_TO_EN    V_CL12_RD_DATA_TO_EN(1U)
17091 
17092 #define S_CL11_RD_DATA_TO_EN    11
17093 #define V_CL11_RD_DATA_TO_EN(x) ((x) << S_CL11_RD_DATA_TO_EN)
17094 #define F_CL11_RD_DATA_TO_EN    V_CL11_RD_DATA_TO_EN(1U)
17095 
17096 #define S_CL10_RD_DATA_TO_EN    10
17097 #define V_CL10_RD_DATA_TO_EN(x) ((x) << S_CL10_RD_DATA_TO_EN)
17098 #define F_CL10_RD_DATA_TO_EN    V_CL10_RD_DATA_TO_EN(1U)
17099 
17100 #define S_CL9_RD_DATA_TO_EN    9
17101 #define V_CL9_RD_DATA_TO_EN(x) ((x) << S_CL9_RD_DATA_TO_EN)
17102 #define F_CL9_RD_DATA_TO_EN    V_CL9_RD_DATA_TO_EN(1U)
17103 
17104 #define S_CL8_RD_DATA_TO_EN    8
17105 #define V_CL8_RD_DATA_TO_EN(x) ((x) << S_CL8_RD_DATA_TO_EN)
17106 #define F_CL8_RD_DATA_TO_EN    V_CL8_RD_DATA_TO_EN(1U)
17107 
17108 #define S_CL7_RD_DATA_TO_EN    7
17109 #define V_CL7_RD_DATA_TO_EN(x) ((x) << S_CL7_RD_DATA_TO_EN)
17110 #define F_CL7_RD_DATA_TO_EN    V_CL7_RD_DATA_TO_EN(1U)
17111 
17112 #define S_CL6_RD_DATA_TO_EN    6
17113 #define V_CL6_RD_DATA_TO_EN(x) ((x) << S_CL6_RD_DATA_TO_EN)
17114 #define F_CL6_RD_DATA_TO_EN    V_CL6_RD_DATA_TO_EN(1U)
17115 
17116 #define S_CL5_RD_DATA_TO_EN    5
17117 #define V_CL5_RD_DATA_TO_EN(x) ((x) << S_CL5_RD_DATA_TO_EN)
17118 #define F_CL5_RD_DATA_TO_EN    V_CL5_RD_DATA_TO_EN(1U)
17119 
17120 #define S_CL4_RD_DATA_TO_EN    4
17121 #define V_CL4_RD_DATA_TO_EN(x) ((x) << S_CL4_RD_DATA_TO_EN)
17122 #define F_CL4_RD_DATA_TO_EN    V_CL4_RD_DATA_TO_EN(1U)
17123 
17124 #define S_CL3_RD_DATA_TO_EN    3
17125 #define V_CL3_RD_DATA_TO_EN(x) ((x) << S_CL3_RD_DATA_TO_EN)
17126 #define F_CL3_RD_DATA_TO_EN    V_CL3_RD_DATA_TO_EN(1U)
17127 
17128 #define S_CL2_RD_DATA_TO_EN    2
17129 #define V_CL2_RD_DATA_TO_EN(x) ((x) << S_CL2_RD_DATA_TO_EN)
17130 #define F_CL2_RD_DATA_TO_EN    V_CL2_RD_DATA_TO_EN(1U)
17131 
17132 #define S_CL1_RD_DATA_TO_EN    1
17133 #define V_CL1_RD_DATA_TO_EN(x) ((x) << S_CL1_RD_DATA_TO_EN)
17134 #define F_CL1_RD_DATA_TO_EN    V_CL1_RD_DATA_TO_EN(1U)
17135 
17136 #define S_CL0_RD_DATA_TO_EN    0
17137 #define V_CL0_RD_DATA_TO_EN(x) ((x) << S_CL0_RD_DATA_TO_EN)
17138 #define F_CL0_RD_DATA_TO_EN    V_CL0_RD_DATA_TO_EN(1U)
17139 
17140 #define S_FUTURE_CEXPANSION_RTE    29
17141 #define M_FUTURE_CEXPANSION_RTE    0x7U
17142 #define V_FUTURE_CEXPANSION_RTE(x) ((x) << S_FUTURE_CEXPANSION_RTE)
17143 #define G_FUTURE_CEXPANSION_RTE(x) (((x) >> S_FUTURE_CEXPANSION_RTE) & M_FUTURE_CEXPANSION_RTE)
17144 
17145 #define S_FUTURE_DEXPANSION_RTE    13
17146 #define M_FUTURE_DEXPANSION_RTE    0x7U
17147 #define V_FUTURE_DEXPANSION_RTE(x) ((x) << S_FUTURE_DEXPANSION_RTE)
17148 #define G_FUTURE_DEXPANSION_RTE(x) (((x) >> S_FUTURE_DEXPANSION_RTE) & M_FUTURE_DEXPANSION_RTE)
17149 
17150 #define A_MA_READ_TIMEOUT_ERROR_STATUS 0x78e0
17151 
17152 #define S_CL12_RD_CMD_TO_ERROR    28
17153 #define V_CL12_RD_CMD_TO_ERROR(x) ((x) << S_CL12_RD_CMD_TO_ERROR)
17154 #define F_CL12_RD_CMD_TO_ERROR    V_CL12_RD_CMD_TO_ERROR(1U)
17155 
17156 #define S_CL11_RD_CMD_TO_ERROR    27
17157 #define V_CL11_RD_CMD_TO_ERROR(x) ((x) << S_CL11_RD_CMD_TO_ERROR)
17158 #define F_CL11_RD_CMD_TO_ERROR    V_CL11_RD_CMD_TO_ERROR(1U)
17159 
17160 #define S_CL10_RD_CMD_TO_ERROR    26
17161 #define V_CL10_RD_CMD_TO_ERROR(x) ((x) << S_CL10_RD_CMD_TO_ERROR)
17162 #define F_CL10_RD_CMD_TO_ERROR    V_CL10_RD_CMD_TO_ERROR(1U)
17163 
17164 #define S_CL9_RD_CMD_TO_ERROR    25
17165 #define V_CL9_RD_CMD_TO_ERROR(x) ((x) << S_CL9_RD_CMD_TO_ERROR)
17166 #define F_CL9_RD_CMD_TO_ERROR    V_CL9_RD_CMD_TO_ERROR(1U)
17167 
17168 #define S_CL8_RD_CMD_TO_ERROR    24
17169 #define V_CL8_RD_CMD_TO_ERROR(x) ((x) << S_CL8_RD_CMD_TO_ERROR)
17170 #define F_CL8_RD_CMD_TO_ERROR    V_CL8_RD_CMD_TO_ERROR(1U)
17171 
17172 #define S_CL7_RD_CMD_TO_ERROR    23
17173 #define V_CL7_RD_CMD_TO_ERROR(x) ((x) << S_CL7_RD_CMD_TO_ERROR)
17174 #define F_CL7_RD_CMD_TO_ERROR    V_CL7_RD_CMD_TO_ERROR(1U)
17175 
17176 #define S_CL6_RD_CMD_TO_ERROR    22
17177 #define V_CL6_RD_CMD_TO_ERROR(x) ((x) << S_CL6_RD_CMD_TO_ERROR)
17178 #define F_CL6_RD_CMD_TO_ERROR    V_CL6_RD_CMD_TO_ERROR(1U)
17179 
17180 #define S_CL5_RD_CMD_TO_ERROR    21
17181 #define V_CL5_RD_CMD_TO_ERROR(x) ((x) << S_CL5_RD_CMD_TO_ERROR)
17182 #define F_CL5_RD_CMD_TO_ERROR    V_CL5_RD_CMD_TO_ERROR(1U)
17183 
17184 #define S_CL4_RD_CMD_TO_ERROR    20
17185 #define V_CL4_RD_CMD_TO_ERROR(x) ((x) << S_CL4_RD_CMD_TO_ERROR)
17186 #define F_CL4_RD_CMD_TO_ERROR    V_CL4_RD_CMD_TO_ERROR(1U)
17187 
17188 #define S_CL3_RD_CMD_TO_ERROR    19
17189 #define V_CL3_RD_CMD_TO_ERROR(x) ((x) << S_CL3_RD_CMD_TO_ERROR)
17190 #define F_CL3_RD_CMD_TO_ERROR    V_CL3_RD_CMD_TO_ERROR(1U)
17191 
17192 #define S_CL2_RD_CMD_TO_ERROR    18
17193 #define V_CL2_RD_CMD_TO_ERROR(x) ((x) << S_CL2_RD_CMD_TO_ERROR)
17194 #define F_CL2_RD_CMD_TO_ERROR    V_CL2_RD_CMD_TO_ERROR(1U)
17195 
17196 #define S_CL1_RD_CMD_TO_ERROR    17
17197 #define V_CL1_RD_CMD_TO_ERROR(x) ((x) << S_CL1_RD_CMD_TO_ERROR)
17198 #define F_CL1_RD_CMD_TO_ERROR    V_CL1_RD_CMD_TO_ERROR(1U)
17199 
17200 #define S_CL0_RD_CMD_TO_ERROR    16
17201 #define V_CL0_RD_CMD_TO_ERROR(x) ((x) << S_CL0_RD_CMD_TO_ERROR)
17202 #define F_CL0_RD_CMD_TO_ERROR    V_CL0_RD_CMD_TO_ERROR(1U)
17203 
17204 #define S_CL12_RD_DATA_TO_ERROR    12
17205 #define V_CL12_RD_DATA_TO_ERROR(x) ((x) << S_CL12_RD_DATA_TO_ERROR)
17206 #define F_CL12_RD_DATA_TO_ERROR    V_CL12_RD_DATA_TO_ERROR(1U)
17207 
17208 #define S_CL11_RD_DATA_TO_ERROR    11
17209 #define V_CL11_RD_DATA_TO_ERROR(x) ((x) << S_CL11_RD_DATA_TO_ERROR)
17210 #define F_CL11_RD_DATA_TO_ERROR    V_CL11_RD_DATA_TO_ERROR(1U)
17211 
17212 #define S_CL10_RD_DATA_TO_ERROR    10
17213 #define V_CL10_RD_DATA_TO_ERROR(x) ((x) << S_CL10_RD_DATA_TO_ERROR)
17214 #define F_CL10_RD_DATA_TO_ERROR    V_CL10_RD_DATA_TO_ERROR(1U)
17215 
17216 #define S_CL9_RD_DATA_TO_ERROR    9
17217 #define V_CL9_RD_DATA_TO_ERROR(x) ((x) << S_CL9_RD_DATA_TO_ERROR)
17218 #define F_CL9_RD_DATA_TO_ERROR    V_CL9_RD_DATA_TO_ERROR(1U)
17219 
17220 #define S_CL8_RD_DATA_TO_ERROR    8
17221 #define V_CL8_RD_DATA_TO_ERROR(x) ((x) << S_CL8_RD_DATA_TO_ERROR)
17222 #define F_CL8_RD_DATA_TO_ERROR    V_CL8_RD_DATA_TO_ERROR(1U)
17223 
17224 #define S_CL7_RD_DATA_TO_ERROR    7
17225 #define V_CL7_RD_DATA_TO_ERROR(x) ((x) << S_CL7_RD_DATA_TO_ERROR)
17226 #define F_CL7_RD_DATA_TO_ERROR    V_CL7_RD_DATA_TO_ERROR(1U)
17227 
17228 #define S_CL6_RD_DATA_TO_ERROR    6
17229 #define V_CL6_RD_DATA_TO_ERROR(x) ((x) << S_CL6_RD_DATA_TO_ERROR)
17230 #define F_CL6_RD_DATA_TO_ERROR    V_CL6_RD_DATA_TO_ERROR(1U)
17231 
17232 #define S_CL5_RD_DATA_TO_ERROR    5
17233 #define V_CL5_RD_DATA_TO_ERROR(x) ((x) << S_CL5_RD_DATA_TO_ERROR)
17234 #define F_CL5_RD_DATA_TO_ERROR    V_CL5_RD_DATA_TO_ERROR(1U)
17235 
17236 #define S_CL4_RD_DATA_TO_ERROR    4
17237 #define V_CL4_RD_DATA_TO_ERROR(x) ((x) << S_CL4_RD_DATA_TO_ERROR)
17238 #define F_CL4_RD_DATA_TO_ERROR    V_CL4_RD_DATA_TO_ERROR(1U)
17239 
17240 #define S_CL3_RD_DATA_TO_ERROR    3
17241 #define V_CL3_RD_DATA_TO_ERROR(x) ((x) << S_CL3_RD_DATA_TO_ERROR)
17242 #define F_CL3_RD_DATA_TO_ERROR    V_CL3_RD_DATA_TO_ERROR(1U)
17243 
17244 #define S_CL2_RD_DATA_TO_ERROR    2
17245 #define V_CL2_RD_DATA_TO_ERROR(x) ((x) << S_CL2_RD_DATA_TO_ERROR)
17246 #define F_CL2_RD_DATA_TO_ERROR    V_CL2_RD_DATA_TO_ERROR(1U)
17247 
17248 #define S_CL1_RD_DATA_TO_ERROR    1
17249 #define V_CL1_RD_DATA_TO_ERROR(x) ((x) << S_CL1_RD_DATA_TO_ERROR)
17250 #define F_CL1_RD_DATA_TO_ERROR    V_CL1_RD_DATA_TO_ERROR(1U)
17251 
17252 #define S_CL0_RD_DATA_TO_ERROR    0
17253 #define V_CL0_RD_DATA_TO_ERROR(x) ((x) << S_CL0_RD_DATA_TO_ERROR)
17254 #define F_CL0_RD_DATA_TO_ERROR    V_CL0_RD_DATA_TO_ERROR(1U)
17255 
17256 #define S_FUTURE_CEXPANSION_RTS    29
17257 #define M_FUTURE_CEXPANSION_RTS    0x7U
17258 #define V_FUTURE_CEXPANSION_RTS(x) ((x) << S_FUTURE_CEXPANSION_RTS)
17259 #define G_FUTURE_CEXPANSION_RTS(x) (((x) >> S_FUTURE_CEXPANSION_RTS) & M_FUTURE_CEXPANSION_RTS)
17260 
17261 #define S_FUTURE_DEXPANSION_RTS    13
17262 #define M_FUTURE_DEXPANSION_RTS    0x7U
17263 #define V_FUTURE_DEXPANSION_RTS(x) ((x) << S_FUTURE_DEXPANSION_RTS)
17264 #define G_FUTURE_DEXPANSION_RTS(x) (((x) >> S_FUTURE_DEXPANSION_RTS) & M_FUTURE_DEXPANSION_RTS)
17265 
17266 #define A_MA_BKP_CNT_SEL 0x78e4
17267 
17268 #define S_BKP_CNT_TYPE    30
17269 #define M_BKP_CNT_TYPE    0x3U
17270 #define V_BKP_CNT_TYPE(x) ((x) << S_BKP_CNT_TYPE)
17271 #define G_BKP_CNT_TYPE(x) (((x) >> S_BKP_CNT_TYPE) & M_BKP_CNT_TYPE)
17272 
17273 #define S_BKP_CLIENT    24
17274 #define M_BKP_CLIENT    0xfU
17275 #define V_BKP_CLIENT(x) ((x) << S_BKP_CLIENT)
17276 #define G_BKP_CLIENT(x) (((x) >> S_BKP_CLIENT) & M_BKP_CLIENT)
17277 
17278 #define A_MA_BKP_CNT 0x78e8
17279 #define A_MA_WRT_ARB 0x78ec
17280 
17281 #define S_WRT_EN    31
17282 #define V_WRT_EN(x) ((x) << S_WRT_EN)
17283 #define F_WRT_EN    V_WRT_EN(1U)
17284 
17285 #define S_WR_TIM    16
17286 #define M_WR_TIM    0xffU
17287 #define V_WR_TIM(x) ((x) << S_WR_TIM)
17288 #define G_WR_TIM(x) (((x) >> S_WR_TIM) & M_WR_TIM)
17289 
17290 #define S_RD_WIN    8
17291 #define M_RD_WIN    0xffU
17292 #define V_RD_WIN(x) ((x) << S_RD_WIN)
17293 #define G_RD_WIN(x) (((x) >> S_RD_WIN) & M_RD_WIN)
17294 
17295 #define S_WR_WIN    0
17296 #define M_WR_WIN    0xffU
17297 #define V_WR_WIN(x) ((x) << S_WR_WIN)
17298 #define G_WR_WIN(x) (((x) >> S_WR_WIN) & M_WR_WIN)
17299 
17300 #define A_MA_IF_PARITY_ERROR_ENABLE 0x78f0
17301 
17302 #define S_T5_FUTURE_DEXPANSION    13
17303 #define M_T5_FUTURE_DEXPANSION    0x7ffffU
17304 #define V_T5_FUTURE_DEXPANSION(x) ((x) << S_T5_FUTURE_DEXPANSION)
17305 #define G_T5_FUTURE_DEXPANSION(x) (((x) >> S_T5_FUTURE_DEXPANSION) & M_T5_FUTURE_DEXPANSION)
17306 
17307 #define S_CL12_IF_PAR_EN    12
17308 #define V_CL12_IF_PAR_EN(x) ((x) << S_CL12_IF_PAR_EN)
17309 #define F_CL12_IF_PAR_EN    V_CL12_IF_PAR_EN(1U)
17310 
17311 #define S_CL11_IF_PAR_EN    11
17312 #define V_CL11_IF_PAR_EN(x) ((x) << S_CL11_IF_PAR_EN)
17313 #define F_CL11_IF_PAR_EN    V_CL11_IF_PAR_EN(1U)
17314 
17315 #define S_CL10_IF_PAR_EN    10
17316 #define V_CL10_IF_PAR_EN(x) ((x) << S_CL10_IF_PAR_EN)
17317 #define F_CL10_IF_PAR_EN    V_CL10_IF_PAR_EN(1U)
17318 
17319 #define S_CL9_IF_PAR_EN    9
17320 #define V_CL9_IF_PAR_EN(x) ((x) << S_CL9_IF_PAR_EN)
17321 #define F_CL9_IF_PAR_EN    V_CL9_IF_PAR_EN(1U)
17322 
17323 #define S_CL8_IF_PAR_EN    8
17324 #define V_CL8_IF_PAR_EN(x) ((x) << S_CL8_IF_PAR_EN)
17325 #define F_CL8_IF_PAR_EN    V_CL8_IF_PAR_EN(1U)
17326 
17327 #define S_CL7_IF_PAR_EN    7
17328 #define V_CL7_IF_PAR_EN(x) ((x) << S_CL7_IF_PAR_EN)
17329 #define F_CL7_IF_PAR_EN    V_CL7_IF_PAR_EN(1U)
17330 
17331 #define S_CL6_IF_PAR_EN    6
17332 #define V_CL6_IF_PAR_EN(x) ((x) << S_CL6_IF_PAR_EN)
17333 #define F_CL6_IF_PAR_EN    V_CL6_IF_PAR_EN(1U)
17334 
17335 #define S_CL5_IF_PAR_EN    5
17336 #define V_CL5_IF_PAR_EN(x) ((x) << S_CL5_IF_PAR_EN)
17337 #define F_CL5_IF_PAR_EN    V_CL5_IF_PAR_EN(1U)
17338 
17339 #define S_CL4_IF_PAR_EN    4
17340 #define V_CL4_IF_PAR_EN(x) ((x) << S_CL4_IF_PAR_EN)
17341 #define F_CL4_IF_PAR_EN    V_CL4_IF_PAR_EN(1U)
17342 
17343 #define S_CL3_IF_PAR_EN    3
17344 #define V_CL3_IF_PAR_EN(x) ((x) << S_CL3_IF_PAR_EN)
17345 #define F_CL3_IF_PAR_EN    V_CL3_IF_PAR_EN(1U)
17346 
17347 #define S_CL2_IF_PAR_EN    2
17348 #define V_CL2_IF_PAR_EN(x) ((x) << S_CL2_IF_PAR_EN)
17349 #define F_CL2_IF_PAR_EN    V_CL2_IF_PAR_EN(1U)
17350 
17351 #define S_CL1_IF_PAR_EN    1
17352 #define V_CL1_IF_PAR_EN(x) ((x) << S_CL1_IF_PAR_EN)
17353 #define F_CL1_IF_PAR_EN    V_CL1_IF_PAR_EN(1U)
17354 
17355 #define S_CL0_IF_PAR_EN    0
17356 #define V_CL0_IF_PAR_EN(x) ((x) << S_CL0_IF_PAR_EN)
17357 #define F_CL0_IF_PAR_EN    V_CL0_IF_PAR_EN(1U)
17358 
17359 #define S_FUTURE_DEXPANSION_IPE    13
17360 #define M_FUTURE_DEXPANSION_IPE    0x7ffffU
17361 #define V_FUTURE_DEXPANSION_IPE(x) ((x) << S_FUTURE_DEXPANSION_IPE)
17362 #define G_FUTURE_DEXPANSION_IPE(x) (((x) >> S_FUTURE_DEXPANSION_IPE) & M_FUTURE_DEXPANSION_IPE)
17363 
17364 #define A_MA_IF_PARITY_ERROR_STATUS 0x78f4
17365 
17366 #define S_T5_FUTURE_DEXPANSION    13
17367 #define M_T5_FUTURE_DEXPANSION    0x7ffffU
17368 #define V_T5_FUTURE_DEXPANSION(x) ((x) << S_T5_FUTURE_DEXPANSION)
17369 #define G_T5_FUTURE_DEXPANSION(x) (((x) >> S_T5_FUTURE_DEXPANSION) & M_T5_FUTURE_DEXPANSION)
17370 
17371 #define S_CL12_IF_PAR_ERROR    12
17372 #define V_CL12_IF_PAR_ERROR(x) ((x) << S_CL12_IF_PAR_ERROR)
17373 #define F_CL12_IF_PAR_ERROR    V_CL12_IF_PAR_ERROR(1U)
17374 
17375 #define S_CL11_IF_PAR_ERROR    11
17376 #define V_CL11_IF_PAR_ERROR(x) ((x) << S_CL11_IF_PAR_ERROR)
17377 #define F_CL11_IF_PAR_ERROR    V_CL11_IF_PAR_ERROR(1U)
17378 
17379 #define S_CL10_IF_PAR_ERROR    10
17380 #define V_CL10_IF_PAR_ERROR(x) ((x) << S_CL10_IF_PAR_ERROR)
17381 #define F_CL10_IF_PAR_ERROR    V_CL10_IF_PAR_ERROR(1U)
17382 
17383 #define S_CL9_IF_PAR_ERROR    9
17384 #define V_CL9_IF_PAR_ERROR(x) ((x) << S_CL9_IF_PAR_ERROR)
17385 #define F_CL9_IF_PAR_ERROR    V_CL9_IF_PAR_ERROR(1U)
17386 
17387 #define S_CL8_IF_PAR_ERROR    8
17388 #define V_CL8_IF_PAR_ERROR(x) ((x) << S_CL8_IF_PAR_ERROR)
17389 #define F_CL8_IF_PAR_ERROR    V_CL8_IF_PAR_ERROR(1U)
17390 
17391 #define S_CL7_IF_PAR_ERROR    7
17392 #define V_CL7_IF_PAR_ERROR(x) ((x) << S_CL7_IF_PAR_ERROR)
17393 #define F_CL7_IF_PAR_ERROR    V_CL7_IF_PAR_ERROR(1U)
17394 
17395 #define S_CL6_IF_PAR_ERROR    6
17396 #define V_CL6_IF_PAR_ERROR(x) ((x) << S_CL6_IF_PAR_ERROR)
17397 #define F_CL6_IF_PAR_ERROR    V_CL6_IF_PAR_ERROR(1U)
17398 
17399 #define S_CL5_IF_PAR_ERROR    5
17400 #define V_CL5_IF_PAR_ERROR(x) ((x) << S_CL5_IF_PAR_ERROR)
17401 #define F_CL5_IF_PAR_ERROR    V_CL5_IF_PAR_ERROR(1U)
17402 
17403 #define S_CL4_IF_PAR_ERROR    4
17404 #define V_CL4_IF_PAR_ERROR(x) ((x) << S_CL4_IF_PAR_ERROR)
17405 #define F_CL4_IF_PAR_ERROR    V_CL4_IF_PAR_ERROR(1U)
17406 
17407 #define S_CL3_IF_PAR_ERROR    3
17408 #define V_CL3_IF_PAR_ERROR(x) ((x) << S_CL3_IF_PAR_ERROR)
17409 #define F_CL3_IF_PAR_ERROR    V_CL3_IF_PAR_ERROR(1U)
17410 
17411 #define S_CL2_IF_PAR_ERROR    2
17412 #define V_CL2_IF_PAR_ERROR(x) ((x) << S_CL2_IF_PAR_ERROR)
17413 #define F_CL2_IF_PAR_ERROR    V_CL2_IF_PAR_ERROR(1U)
17414 
17415 #define S_CL1_IF_PAR_ERROR    1
17416 #define V_CL1_IF_PAR_ERROR(x) ((x) << S_CL1_IF_PAR_ERROR)
17417 #define F_CL1_IF_PAR_ERROR    V_CL1_IF_PAR_ERROR(1U)
17418 
17419 #define S_CL0_IF_PAR_ERROR    0
17420 #define V_CL0_IF_PAR_ERROR(x) ((x) << S_CL0_IF_PAR_ERROR)
17421 #define F_CL0_IF_PAR_ERROR    V_CL0_IF_PAR_ERROR(1U)
17422 
17423 #define S_FUTURE_DEXPANSION_IPS    13
17424 #define M_FUTURE_DEXPANSION_IPS    0x7ffffU
17425 #define V_FUTURE_DEXPANSION_IPS(x) ((x) << S_FUTURE_DEXPANSION_IPS)
17426 #define G_FUTURE_DEXPANSION_IPS(x) (((x) >> S_FUTURE_DEXPANSION_IPS) & M_FUTURE_DEXPANSION_IPS)
17427 
17428 #define A_MA_LOCAL_DEBUG_CFG 0x78f8
17429 
17430 #define S_DEBUG_OR    15
17431 #define V_DEBUG_OR(x) ((x) << S_DEBUG_OR)
17432 #define F_DEBUG_OR    V_DEBUG_OR(1U)
17433 
17434 #define S_DEBUG_HI    14
17435 #define V_DEBUG_HI(x) ((x) << S_DEBUG_HI)
17436 #define F_DEBUG_HI    V_DEBUG_HI(1U)
17437 
17438 #define S_DEBUG_RPT    13
17439 #define V_DEBUG_RPT(x) ((x) << S_DEBUG_RPT)
17440 #define F_DEBUG_RPT    V_DEBUG_RPT(1U)
17441 
17442 #define S_DEBUGPAGE    10
17443 #define M_DEBUGPAGE    0x7U
17444 #define V_DEBUGPAGE(x) ((x) << S_DEBUGPAGE)
17445 #define G_DEBUGPAGE(x) (((x) >> S_DEBUGPAGE) & M_DEBUGPAGE)
17446 
17447 #define A_MA_LOCAL_DEBUG_RPT 0x78fc
17448 #define A_MA_SGE_THREAD_0_CLIENT_INTERFACE_EXTERNAL 0xa000
17449 
17450 #define S_CMDVLD0    31
17451 #define V_CMDVLD0(x) ((x) << S_CMDVLD0)
17452 #define F_CMDVLD0    V_CMDVLD0(1U)
17453 
17454 #define S_CMDRDY0    30
17455 #define V_CMDRDY0(x) ((x) << S_CMDRDY0)
17456 #define F_CMDRDY0    V_CMDRDY0(1U)
17457 
17458 #define S_CMDTYPE0    29
17459 #define V_CMDTYPE0(x) ((x) << S_CMDTYPE0)
17460 #define F_CMDTYPE0    V_CMDTYPE0(1U)
17461 
17462 #define S_CMDLEN0    21
17463 #define M_CMDLEN0    0xffU
17464 #define V_CMDLEN0(x) ((x) << S_CMDLEN0)
17465 #define G_CMDLEN0(x) (((x) >> S_CMDLEN0) & M_CMDLEN0)
17466 
17467 #define S_CMDADDR0    8
17468 #define M_CMDADDR0    0x1fffU
17469 #define V_CMDADDR0(x) ((x) << S_CMDADDR0)
17470 #define G_CMDADDR0(x) (((x) >> S_CMDADDR0) & M_CMDADDR0)
17471 
17472 #define S_WRDATAVLD0    7
17473 #define V_WRDATAVLD0(x) ((x) << S_WRDATAVLD0)
17474 #define F_WRDATAVLD0    V_WRDATAVLD0(1U)
17475 
17476 #define S_WRDATARDY0    6
17477 #define V_WRDATARDY0(x) ((x) << S_WRDATARDY0)
17478 #define F_WRDATARDY0    V_WRDATARDY0(1U)
17479 
17480 #define S_RDDATARDY0    5
17481 #define V_RDDATARDY0(x) ((x) << S_RDDATARDY0)
17482 #define F_RDDATARDY0    V_RDDATARDY0(1U)
17483 
17484 #define S_RDDATAVLD0    4
17485 #define V_RDDATAVLD0(x) ((x) << S_RDDATAVLD0)
17486 #define F_RDDATAVLD0    V_RDDATAVLD0(1U)
17487 
17488 #define S_RDDATA0    0
17489 #define M_RDDATA0    0xfU
17490 #define V_RDDATA0(x) ((x) << S_RDDATA0)
17491 #define G_RDDATA0(x) (((x) >> S_RDDATA0) & M_RDDATA0)
17492 
17493 #define A_MA_SGE_THREAD_1_CLIENT_INTERFACE_EXTERNAL 0xa001
17494 
17495 #define S_CMDVLD1    31
17496 #define V_CMDVLD1(x) ((x) << S_CMDVLD1)
17497 #define F_CMDVLD1    V_CMDVLD1(1U)
17498 
17499 #define S_CMDRDY1    30
17500 #define V_CMDRDY1(x) ((x) << S_CMDRDY1)
17501 #define F_CMDRDY1    V_CMDRDY1(1U)
17502 
17503 #define S_CMDTYPE1    29
17504 #define V_CMDTYPE1(x) ((x) << S_CMDTYPE1)
17505 #define F_CMDTYPE1    V_CMDTYPE1(1U)
17506 
17507 #define S_CMDLEN1    21
17508 #define M_CMDLEN1    0xffU
17509 #define V_CMDLEN1(x) ((x) << S_CMDLEN1)
17510 #define G_CMDLEN1(x) (((x) >> S_CMDLEN1) & M_CMDLEN1)
17511 
17512 #define S_CMDADDR1    8
17513 #define M_CMDADDR1    0x1fffU
17514 #define V_CMDADDR1(x) ((x) << S_CMDADDR1)
17515 #define G_CMDADDR1(x) (((x) >> S_CMDADDR1) & M_CMDADDR1)
17516 
17517 #define S_WRDATAVLD1    7
17518 #define V_WRDATAVLD1(x) ((x) << S_WRDATAVLD1)
17519 #define F_WRDATAVLD1    V_WRDATAVLD1(1U)
17520 
17521 #define S_WRDATARDY1    6
17522 #define V_WRDATARDY1(x) ((x) << S_WRDATARDY1)
17523 #define F_WRDATARDY1    V_WRDATARDY1(1U)
17524 
17525 #define S_RDDATARDY1    5
17526 #define V_RDDATARDY1(x) ((x) << S_RDDATARDY1)
17527 #define F_RDDATARDY1    V_RDDATARDY1(1U)
17528 
17529 #define S_RDDATAVLD1    4
17530 #define V_RDDATAVLD1(x) ((x) << S_RDDATAVLD1)
17531 #define F_RDDATAVLD1    V_RDDATAVLD1(1U)
17532 
17533 #define S_RDDATA1    0
17534 #define M_RDDATA1    0xfU
17535 #define V_RDDATA1(x) ((x) << S_RDDATA1)
17536 #define G_RDDATA1(x) (((x) >> S_RDDATA1) & M_RDDATA1)
17537 
17538 #define A_MA_ULP_TX_CLIENT_INTERFACE_EXTERNAL 0xa002
17539 
17540 #define S_CMDVLD2    31
17541 #define V_CMDVLD2(x) ((x) << S_CMDVLD2)
17542 #define F_CMDVLD2    V_CMDVLD2(1U)
17543 
17544 #define S_CMDRDY2    30
17545 #define V_CMDRDY2(x) ((x) << S_CMDRDY2)
17546 #define F_CMDRDY2    V_CMDRDY2(1U)
17547 
17548 #define S_CMDTYPE2    29
17549 #define V_CMDTYPE2(x) ((x) << S_CMDTYPE2)
17550 #define F_CMDTYPE2    V_CMDTYPE2(1U)
17551 
17552 #define S_CMDLEN2    21
17553 #define M_CMDLEN2    0xffU
17554 #define V_CMDLEN2(x) ((x) << S_CMDLEN2)
17555 #define G_CMDLEN2(x) (((x) >> S_CMDLEN2) & M_CMDLEN2)
17556 
17557 #define S_CMDADDR2    8
17558 #define M_CMDADDR2    0x1fffU
17559 #define V_CMDADDR2(x) ((x) << S_CMDADDR2)
17560 #define G_CMDADDR2(x) (((x) >> S_CMDADDR2) & M_CMDADDR2)
17561 
17562 #define S_WRDATAVLD2    7
17563 #define V_WRDATAVLD2(x) ((x) << S_WRDATAVLD2)
17564 #define F_WRDATAVLD2    V_WRDATAVLD2(1U)
17565 
17566 #define S_WRDATARDY2    6
17567 #define V_WRDATARDY2(x) ((x) << S_WRDATARDY2)
17568 #define F_WRDATARDY2    V_WRDATARDY2(1U)
17569 
17570 #define S_RDDATARDY2    5
17571 #define V_RDDATARDY2(x) ((x) << S_RDDATARDY2)
17572 #define F_RDDATARDY2    V_RDDATARDY2(1U)
17573 
17574 #define S_RDDATAVLD2    4
17575 #define V_RDDATAVLD2(x) ((x) << S_RDDATAVLD2)
17576 #define F_RDDATAVLD2    V_RDDATAVLD2(1U)
17577 
17578 #define S_RDDATA2    0
17579 #define M_RDDATA2    0xfU
17580 #define V_RDDATA2(x) ((x) << S_RDDATA2)
17581 #define G_RDDATA2(x) (((x) >> S_RDDATA2) & M_RDDATA2)
17582 
17583 #define A_MA_ULP_RX_CLIENT_INTERFACE_EXTERNAL 0xa003
17584 
17585 #define S_CMDVLD3    31
17586 #define V_CMDVLD3(x) ((x) << S_CMDVLD3)
17587 #define F_CMDVLD3    V_CMDVLD3(1U)
17588 
17589 #define S_CMDRDY3    30
17590 #define V_CMDRDY3(x) ((x) << S_CMDRDY3)
17591 #define F_CMDRDY3    V_CMDRDY3(1U)
17592 
17593 #define S_CMDTYPE3    29
17594 #define V_CMDTYPE3(x) ((x) << S_CMDTYPE3)
17595 #define F_CMDTYPE3    V_CMDTYPE3(1U)
17596 
17597 #define S_CMDLEN3    21
17598 #define M_CMDLEN3    0xffU
17599 #define V_CMDLEN3(x) ((x) << S_CMDLEN3)
17600 #define G_CMDLEN3(x) (((x) >> S_CMDLEN3) & M_CMDLEN3)
17601 
17602 #define S_CMDADDR3    8
17603 #define M_CMDADDR3    0x1fffU
17604 #define V_CMDADDR3(x) ((x) << S_CMDADDR3)
17605 #define G_CMDADDR3(x) (((x) >> S_CMDADDR3) & M_CMDADDR3)
17606 
17607 #define S_WRDATAVLD3    7
17608 #define V_WRDATAVLD3(x) ((x) << S_WRDATAVLD3)
17609 #define F_WRDATAVLD3    V_WRDATAVLD3(1U)
17610 
17611 #define S_WRDATARDY3    6
17612 #define V_WRDATARDY3(x) ((x) << S_WRDATARDY3)
17613 #define F_WRDATARDY3    V_WRDATARDY3(1U)
17614 
17615 #define S_RDDATARDY3    5
17616 #define V_RDDATARDY3(x) ((x) << S_RDDATARDY3)
17617 #define F_RDDATARDY3    V_RDDATARDY3(1U)
17618 
17619 #define S_RDDATAVLD3    4
17620 #define V_RDDATAVLD3(x) ((x) << S_RDDATAVLD3)
17621 #define F_RDDATAVLD3    V_RDDATAVLD3(1U)
17622 
17623 #define S_RDDATA3    0
17624 #define M_RDDATA3    0xfU
17625 #define V_RDDATA3(x) ((x) << S_RDDATA3)
17626 #define G_RDDATA3(x) (((x) >> S_RDDATA3) & M_RDDATA3)
17627 
17628 #define A_MA_ULP_TX_RX_CLIENT_INTERFACE_EXTERNAL 0xa004
17629 
17630 #define S_CMDVLD4    31
17631 #define V_CMDVLD4(x) ((x) << S_CMDVLD4)
17632 #define F_CMDVLD4    V_CMDVLD4(1U)
17633 
17634 #define S_CMDRDY4    30
17635 #define V_CMDRDY4(x) ((x) << S_CMDRDY4)
17636 #define F_CMDRDY4    V_CMDRDY4(1U)
17637 
17638 #define S_CMDTYPE4    29
17639 #define V_CMDTYPE4(x) ((x) << S_CMDTYPE4)
17640 #define F_CMDTYPE4    V_CMDTYPE4(1U)
17641 
17642 #define S_CMDLEN4    21
17643 #define M_CMDLEN4    0xffU
17644 #define V_CMDLEN4(x) ((x) << S_CMDLEN4)
17645 #define G_CMDLEN4(x) (((x) >> S_CMDLEN4) & M_CMDLEN4)
17646 
17647 #define S_CMDADDR4    8
17648 #define M_CMDADDR4    0x1fffU
17649 #define V_CMDADDR4(x) ((x) << S_CMDADDR4)
17650 #define G_CMDADDR4(x) (((x) >> S_CMDADDR4) & M_CMDADDR4)
17651 
17652 #define S_WRDATAVLD4    7
17653 #define V_WRDATAVLD4(x) ((x) << S_WRDATAVLD4)
17654 #define F_WRDATAVLD4    V_WRDATAVLD4(1U)
17655 
17656 #define S_WRDATARDY4    6
17657 #define V_WRDATARDY4(x) ((x) << S_WRDATARDY4)
17658 #define F_WRDATARDY4    V_WRDATARDY4(1U)
17659 
17660 #define S_RDDATARDY4    5
17661 #define V_RDDATARDY4(x) ((x) << S_RDDATARDY4)
17662 #define F_RDDATARDY4    V_RDDATARDY4(1U)
17663 
17664 #define S_RDDATAVLD4    4
17665 #define V_RDDATAVLD4(x) ((x) << S_RDDATAVLD4)
17666 #define F_RDDATAVLD4    V_RDDATAVLD4(1U)
17667 
17668 #define S_RDDATA4    0
17669 #define M_RDDATA4    0xfU
17670 #define V_RDDATA4(x) ((x) << S_RDDATA4)
17671 #define G_RDDATA4(x) (((x) >> S_RDDATA4) & M_RDDATA4)
17672 
17673 #define A_MA_TP_THREAD_0_CLIENT_INTERFACE_EXTERNAL 0xa005
17674 
17675 #define S_CMDVLD5    31
17676 #define V_CMDVLD5(x) ((x) << S_CMDVLD5)
17677 #define F_CMDVLD5    V_CMDVLD5(1U)
17678 
17679 #define S_CMDRDY5    30
17680 #define V_CMDRDY5(x) ((x) << S_CMDRDY5)
17681 #define F_CMDRDY5    V_CMDRDY5(1U)
17682 
17683 #define S_CMDTYPE5    29
17684 #define V_CMDTYPE5(x) ((x) << S_CMDTYPE5)
17685 #define F_CMDTYPE5    V_CMDTYPE5(1U)
17686 
17687 #define S_CMDLEN5    21
17688 #define M_CMDLEN5    0xffU
17689 #define V_CMDLEN5(x) ((x) << S_CMDLEN5)
17690 #define G_CMDLEN5(x) (((x) >> S_CMDLEN5) & M_CMDLEN5)
17691 
17692 #define S_CMDADDR5    8
17693 #define M_CMDADDR5    0x1fffU
17694 #define V_CMDADDR5(x) ((x) << S_CMDADDR5)
17695 #define G_CMDADDR5(x) (((x) >> S_CMDADDR5) & M_CMDADDR5)
17696 
17697 #define S_WRDATAVLD5    7
17698 #define V_WRDATAVLD5(x) ((x) << S_WRDATAVLD5)
17699 #define F_WRDATAVLD5    V_WRDATAVLD5(1U)
17700 
17701 #define S_WRDATARDY5    6
17702 #define V_WRDATARDY5(x) ((x) << S_WRDATARDY5)
17703 #define F_WRDATARDY5    V_WRDATARDY5(1U)
17704 
17705 #define S_RDDATARDY5    5
17706 #define V_RDDATARDY5(x) ((x) << S_RDDATARDY5)
17707 #define F_RDDATARDY5    V_RDDATARDY5(1U)
17708 
17709 #define S_RDDATAVLD5    4
17710 #define V_RDDATAVLD5(x) ((x) << S_RDDATAVLD5)
17711 #define F_RDDATAVLD5    V_RDDATAVLD5(1U)
17712 
17713 #define S_RDDATA5    0
17714 #define M_RDDATA5    0xfU
17715 #define V_RDDATA5(x) ((x) << S_RDDATA5)
17716 #define G_RDDATA5(x) (((x) >> S_RDDATA5) & M_RDDATA5)
17717 
17718 #define A_MA_TP_THREAD_1_CLIENT_INTERFACE_EXTERNAL 0xa006
17719 
17720 #define S_CMDVLD6    31
17721 #define V_CMDVLD6(x) ((x) << S_CMDVLD6)
17722 #define F_CMDVLD6    V_CMDVLD6(1U)
17723 
17724 #define S_CMDRDY6    30
17725 #define V_CMDRDY6(x) ((x) << S_CMDRDY6)
17726 #define F_CMDRDY6    V_CMDRDY6(1U)
17727 
17728 #define S_CMDTYPE6    29
17729 #define V_CMDTYPE6(x) ((x) << S_CMDTYPE6)
17730 #define F_CMDTYPE6    V_CMDTYPE6(1U)
17731 
17732 #define S_CMDLEN6    21
17733 #define M_CMDLEN6    0xffU
17734 #define V_CMDLEN6(x) ((x) << S_CMDLEN6)
17735 #define G_CMDLEN6(x) (((x) >> S_CMDLEN6) & M_CMDLEN6)
17736 
17737 #define S_CMDADDR6    8
17738 #define M_CMDADDR6    0x1fffU
17739 #define V_CMDADDR6(x) ((x) << S_CMDADDR6)
17740 #define G_CMDADDR6(x) (((x) >> S_CMDADDR6) & M_CMDADDR6)
17741 
17742 #define S_WRDATAVLD6    7
17743 #define V_WRDATAVLD6(x) ((x) << S_WRDATAVLD6)
17744 #define F_WRDATAVLD6    V_WRDATAVLD6(1U)
17745 
17746 #define S_WRDATARDY6    6
17747 #define V_WRDATARDY6(x) ((x) << S_WRDATARDY6)
17748 #define F_WRDATARDY6    V_WRDATARDY6(1U)
17749 
17750 #define S_RDDATARDY6    5
17751 #define V_RDDATARDY6(x) ((x) << S_RDDATARDY6)
17752 #define F_RDDATARDY6    V_RDDATARDY6(1U)
17753 
17754 #define S_RDDATAVLD6    4
17755 #define V_RDDATAVLD6(x) ((x) << S_RDDATAVLD6)
17756 #define F_RDDATAVLD6    V_RDDATAVLD6(1U)
17757 
17758 #define S_RDDATA6    0
17759 #define M_RDDATA6    0xfU
17760 #define V_RDDATA6(x) ((x) << S_RDDATA6)
17761 #define G_RDDATA6(x) (((x) >> S_RDDATA6) & M_RDDATA6)
17762 
17763 #define A_MA_LE_CLIENT_INTERFACE_EXTERNAL 0xa007
17764 
17765 #define S_CMDVLD7    31
17766 #define V_CMDVLD7(x) ((x) << S_CMDVLD7)
17767 #define F_CMDVLD7    V_CMDVLD7(1U)
17768 
17769 #define S_CMDRDY7    30
17770 #define V_CMDRDY7(x) ((x) << S_CMDRDY7)
17771 #define F_CMDRDY7    V_CMDRDY7(1U)
17772 
17773 #define S_CMDTYPE7    29
17774 #define V_CMDTYPE7(x) ((x) << S_CMDTYPE7)
17775 #define F_CMDTYPE7    V_CMDTYPE7(1U)
17776 
17777 #define S_CMDLEN7    21
17778 #define M_CMDLEN7    0xffU
17779 #define V_CMDLEN7(x) ((x) << S_CMDLEN7)
17780 #define G_CMDLEN7(x) (((x) >> S_CMDLEN7) & M_CMDLEN7)
17781 
17782 #define S_CMDADDR7    8
17783 #define M_CMDADDR7    0x1fffU
17784 #define V_CMDADDR7(x) ((x) << S_CMDADDR7)
17785 #define G_CMDADDR7(x) (((x) >> S_CMDADDR7) & M_CMDADDR7)
17786 
17787 #define S_WRDATAVLD7    7
17788 #define V_WRDATAVLD7(x) ((x) << S_WRDATAVLD7)
17789 #define F_WRDATAVLD7    V_WRDATAVLD7(1U)
17790 
17791 #define S_WRDATARDY7    6
17792 #define V_WRDATARDY7(x) ((x) << S_WRDATARDY7)
17793 #define F_WRDATARDY7    V_WRDATARDY7(1U)
17794 
17795 #define S_RDDATARDY7    5
17796 #define V_RDDATARDY7(x) ((x) << S_RDDATARDY7)
17797 #define F_RDDATARDY7    V_RDDATARDY7(1U)
17798 
17799 #define S_RDDATAVLD7    4
17800 #define V_RDDATAVLD7(x) ((x) << S_RDDATAVLD7)
17801 #define F_RDDATAVLD7    V_RDDATAVLD7(1U)
17802 
17803 #define S_RDDATA7    0
17804 #define M_RDDATA7    0xfU
17805 #define V_RDDATA7(x) ((x) << S_RDDATA7)
17806 #define G_RDDATA7(x) (((x) >> S_RDDATA7) & M_RDDATA7)
17807 
17808 #define A_MA_CIM_CLIENT_INTERFACE_EXTERNAL 0xa008
17809 
17810 #define S_CMDVLD8    31
17811 #define V_CMDVLD8(x) ((x) << S_CMDVLD8)
17812 #define F_CMDVLD8    V_CMDVLD8(1U)
17813 
17814 #define S_CMDRDY8    30
17815 #define V_CMDRDY8(x) ((x) << S_CMDRDY8)
17816 #define F_CMDRDY8    V_CMDRDY8(1U)
17817 
17818 #define S_CMDTYPE8    29
17819 #define V_CMDTYPE8(x) ((x) << S_CMDTYPE8)
17820 #define F_CMDTYPE8    V_CMDTYPE8(1U)
17821 
17822 #define S_CMDLEN8    21
17823 #define M_CMDLEN8    0xffU
17824 #define V_CMDLEN8(x) ((x) << S_CMDLEN8)
17825 #define G_CMDLEN8(x) (((x) >> S_CMDLEN8) & M_CMDLEN8)
17826 
17827 #define S_CMDADDR8    8
17828 #define M_CMDADDR8    0x1fffU
17829 #define V_CMDADDR8(x) ((x) << S_CMDADDR8)
17830 #define G_CMDADDR8(x) (((x) >> S_CMDADDR8) & M_CMDADDR8)
17831 
17832 #define S_WRDATAVLD8    7
17833 #define V_WRDATAVLD8(x) ((x) << S_WRDATAVLD8)
17834 #define F_WRDATAVLD8    V_WRDATAVLD8(1U)
17835 
17836 #define S_WRDATARDY8    6
17837 #define V_WRDATARDY8(x) ((x) << S_WRDATARDY8)
17838 #define F_WRDATARDY8    V_WRDATARDY8(1U)
17839 
17840 #define S_RDDATARDY8    5
17841 #define V_RDDATARDY8(x) ((x) << S_RDDATARDY8)
17842 #define F_RDDATARDY8    V_RDDATARDY8(1U)
17843 
17844 #define S_RDDATAVLD8    4
17845 #define V_RDDATAVLD8(x) ((x) << S_RDDATAVLD8)
17846 #define F_RDDATAVLD8    V_RDDATAVLD8(1U)
17847 
17848 #define S_RDDATA8    0
17849 #define M_RDDATA8    0xfU
17850 #define V_RDDATA8(x) ((x) << S_RDDATA8)
17851 #define G_RDDATA8(x) (((x) >> S_RDDATA8) & M_RDDATA8)
17852 
17853 #define A_MA_PCIE_CLIENT_INTERFACE_EXTERNAL 0xa009
17854 
17855 #define S_CMDVLD9    31
17856 #define V_CMDVLD9(x) ((x) << S_CMDVLD9)
17857 #define F_CMDVLD9    V_CMDVLD9(1U)
17858 
17859 #define S_CMDRDY9    30
17860 #define V_CMDRDY9(x) ((x) << S_CMDRDY9)
17861 #define F_CMDRDY9    V_CMDRDY9(1U)
17862 
17863 #define S_CMDTYPE9    29
17864 #define V_CMDTYPE9(x) ((x) << S_CMDTYPE9)
17865 #define F_CMDTYPE9    V_CMDTYPE9(1U)
17866 
17867 #define S_CMDLEN9    21
17868 #define M_CMDLEN9    0xffU
17869 #define V_CMDLEN9(x) ((x) << S_CMDLEN9)
17870 #define G_CMDLEN9(x) (((x) >> S_CMDLEN9) & M_CMDLEN9)
17871 
17872 #define S_CMDADDR9    8
17873 #define M_CMDADDR9    0x1fffU
17874 #define V_CMDADDR9(x) ((x) << S_CMDADDR9)
17875 #define G_CMDADDR9(x) (((x) >> S_CMDADDR9) & M_CMDADDR9)
17876 
17877 #define S_WRDATAVLD9    7
17878 #define V_WRDATAVLD9(x) ((x) << S_WRDATAVLD9)
17879 #define F_WRDATAVLD9    V_WRDATAVLD9(1U)
17880 
17881 #define S_WRDATARDY9    6
17882 #define V_WRDATARDY9(x) ((x) << S_WRDATARDY9)
17883 #define F_WRDATARDY9    V_WRDATARDY9(1U)
17884 
17885 #define S_RDDATARDY9    5
17886 #define V_RDDATARDY9(x) ((x) << S_RDDATARDY9)
17887 #define F_RDDATARDY9    V_RDDATARDY9(1U)
17888 
17889 #define S_RDDATAVLD9    4
17890 #define V_RDDATAVLD9(x) ((x) << S_RDDATAVLD9)
17891 #define F_RDDATAVLD9    V_RDDATAVLD9(1U)
17892 
17893 #define S_RDDATA9    0
17894 #define M_RDDATA9    0xfU
17895 #define V_RDDATA9(x) ((x) << S_RDDATA9)
17896 #define G_RDDATA9(x) (((x) >> S_RDDATA9) & M_RDDATA9)
17897 
17898 #define A_MA_PM_TX_CLIENT_INTERFACE_EXTERNAL 0xa00a
17899 
17900 #define S_CMDVLD10    31
17901 #define V_CMDVLD10(x) ((x) << S_CMDVLD10)
17902 #define F_CMDVLD10    V_CMDVLD10(1U)
17903 
17904 #define S_CMDRDY10    30
17905 #define V_CMDRDY10(x) ((x) << S_CMDRDY10)
17906 #define F_CMDRDY10    V_CMDRDY10(1U)
17907 
17908 #define S_CMDTYPE10    29
17909 #define V_CMDTYPE10(x) ((x) << S_CMDTYPE10)
17910 #define F_CMDTYPE10    V_CMDTYPE10(1U)
17911 
17912 #define S_CMDLEN10    21
17913 #define M_CMDLEN10    0xffU
17914 #define V_CMDLEN10(x) ((x) << S_CMDLEN10)
17915 #define G_CMDLEN10(x) (((x) >> S_CMDLEN10) & M_CMDLEN10)
17916 
17917 #define S_CMDADDR10    8
17918 #define M_CMDADDR10    0x1fffU
17919 #define V_CMDADDR10(x) ((x) << S_CMDADDR10)
17920 #define G_CMDADDR10(x) (((x) >> S_CMDADDR10) & M_CMDADDR10)
17921 
17922 #define S_WRDATAVLD10    7
17923 #define V_WRDATAVLD10(x) ((x) << S_WRDATAVLD10)
17924 #define F_WRDATAVLD10    V_WRDATAVLD10(1U)
17925 
17926 #define S_WRDATARDY10    6
17927 #define V_WRDATARDY10(x) ((x) << S_WRDATARDY10)
17928 #define F_WRDATARDY10    V_WRDATARDY10(1U)
17929 
17930 #define S_RDDATARDY10    5
17931 #define V_RDDATARDY10(x) ((x) << S_RDDATARDY10)
17932 #define F_RDDATARDY10    V_RDDATARDY10(1U)
17933 
17934 #define S_RDDATAVLD10    4
17935 #define V_RDDATAVLD10(x) ((x) << S_RDDATAVLD10)
17936 #define F_RDDATAVLD10    V_RDDATAVLD10(1U)
17937 
17938 #define S_RDDATA10    0
17939 #define M_RDDATA10    0xfU
17940 #define V_RDDATA10(x) ((x) << S_RDDATA10)
17941 #define G_RDDATA10(x) (((x) >> S_RDDATA10) & M_RDDATA10)
17942 
17943 #define A_MA_PM_RX_CLIENT_INTERFACE_EXTERNAL 0xa00b
17944 
17945 #define S_CMDVLD11    31
17946 #define V_CMDVLD11(x) ((x) << S_CMDVLD11)
17947 #define F_CMDVLD11    V_CMDVLD11(1U)
17948 
17949 #define S_CMDRDY11    30
17950 #define V_CMDRDY11(x) ((x) << S_CMDRDY11)
17951 #define F_CMDRDY11    V_CMDRDY11(1U)
17952 
17953 #define S_CMDTYPE11    29
17954 #define V_CMDTYPE11(x) ((x) << S_CMDTYPE11)
17955 #define F_CMDTYPE11    V_CMDTYPE11(1U)
17956 
17957 #define S_CMDLEN11    21
17958 #define M_CMDLEN11    0xffU
17959 #define V_CMDLEN11(x) ((x) << S_CMDLEN11)
17960 #define G_CMDLEN11(x) (((x) >> S_CMDLEN11) & M_CMDLEN11)
17961 
17962 #define S_CMDADDR11    8
17963 #define M_CMDADDR11    0x1fffU
17964 #define V_CMDADDR11(x) ((x) << S_CMDADDR11)
17965 #define G_CMDADDR11(x) (((x) >> S_CMDADDR11) & M_CMDADDR11)
17966 
17967 #define S_WRDATAVLD11    7
17968 #define V_WRDATAVLD11(x) ((x) << S_WRDATAVLD11)
17969 #define F_WRDATAVLD11    V_WRDATAVLD11(1U)
17970 
17971 #define S_WRDATARDY11    6
17972 #define V_WRDATARDY11(x) ((x) << S_WRDATARDY11)
17973 #define F_WRDATARDY11    V_WRDATARDY11(1U)
17974 
17975 #define S_RDDATARDY11    5
17976 #define V_RDDATARDY11(x) ((x) << S_RDDATARDY11)
17977 #define F_RDDATARDY11    V_RDDATARDY11(1U)
17978 
17979 #define S_RDDATAVLD11    4
17980 #define V_RDDATAVLD11(x) ((x) << S_RDDATAVLD11)
17981 #define F_RDDATAVLD11    V_RDDATAVLD11(1U)
17982 
17983 #define S_RDDATA11    0
17984 #define M_RDDATA11    0xfU
17985 #define V_RDDATA11(x) ((x) << S_RDDATA11)
17986 #define G_RDDATA11(x) (((x) >> S_RDDATA11) & M_RDDATA11)
17987 
17988 #define A_MA_HMA_CLIENT_INTERFACE_EXTERNAL 0xa00c
17989 
17990 #define S_CMDVLD12    31
17991 #define V_CMDVLD12(x) ((x) << S_CMDVLD12)
17992 #define F_CMDVLD12    V_CMDVLD12(1U)
17993 
17994 #define S_CMDRDY12    30
17995 #define V_CMDRDY12(x) ((x) << S_CMDRDY12)
17996 #define F_CMDRDY12    V_CMDRDY12(1U)
17997 
17998 #define S_CMDTYPE12    29
17999 #define V_CMDTYPE12(x) ((x) << S_CMDTYPE12)
18000 #define F_CMDTYPE12    V_CMDTYPE12(1U)
18001 
18002 #define S_CMDLEN12    21
18003 #define M_CMDLEN12    0xffU
18004 #define V_CMDLEN12(x) ((x) << S_CMDLEN12)
18005 #define G_CMDLEN12(x) (((x) >> S_CMDLEN12) & M_CMDLEN12)
18006 
18007 #define S_CMDADDR12    8
18008 #define M_CMDADDR12    0x1fffU
18009 #define V_CMDADDR12(x) ((x) << S_CMDADDR12)
18010 #define G_CMDADDR12(x) (((x) >> S_CMDADDR12) & M_CMDADDR12)
18011 
18012 #define S_WRDATAVLD12    7
18013 #define V_WRDATAVLD12(x) ((x) << S_WRDATAVLD12)
18014 #define F_WRDATAVLD12    V_WRDATAVLD12(1U)
18015 
18016 #define S_WRDATARDY12    6
18017 #define V_WRDATARDY12(x) ((x) << S_WRDATARDY12)
18018 #define F_WRDATARDY12    V_WRDATARDY12(1U)
18019 
18020 #define S_RDDATARDY12    5
18021 #define V_RDDATARDY12(x) ((x) << S_RDDATARDY12)
18022 #define F_RDDATARDY12    V_RDDATARDY12(1U)
18023 
18024 #define S_RDDATAVLD12    4
18025 #define V_RDDATAVLD12(x) ((x) << S_RDDATAVLD12)
18026 #define F_RDDATAVLD12    V_RDDATAVLD12(1U)
18027 
18028 #define S_RDDATA12    0
18029 #define M_RDDATA12    0xfU
18030 #define V_RDDATA12(x) ((x) << S_RDDATA12)
18031 #define G_RDDATA12(x) (((x) >> S_RDDATA12) & M_RDDATA12)
18032 
18033 #define A_MA_TARGET_0_ARBITER_INTERFACE_EXTERNAL_REG0 0xa00d
18034 
18035 #define S_CI0_ARB0_REQ    31
18036 #define V_CI0_ARB0_REQ(x) ((x) << S_CI0_ARB0_REQ)
18037 #define F_CI0_ARB0_REQ    V_CI0_ARB0_REQ(1U)
18038 
18039 #define S_ARB0_CI0_GNT    30
18040 #define V_ARB0_CI0_GNT(x) ((x) << S_ARB0_CI0_GNT)
18041 #define F_ARB0_CI0_GNT    V_ARB0_CI0_GNT(1U)
18042 
18043 #define S_CI0_DM0_WDATA_VLD    29
18044 #define V_CI0_DM0_WDATA_VLD(x) ((x) << S_CI0_DM0_WDATA_VLD)
18045 #define F_CI0_DM0_WDATA_VLD    V_CI0_DM0_WDATA_VLD(1U)
18046 
18047 #define S_DM0_CI0_RDATA_VLD    28
18048 #define V_DM0_CI0_RDATA_VLD(x) ((x) << S_DM0_CI0_RDATA_VLD)
18049 #define F_DM0_CI0_RDATA_VLD    V_DM0_CI0_RDATA_VLD(1U)
18050 
18051 #define S_CI1_ARB0_REQ    27
18052 #define V_CI1_ARB0_REQ(x) ((x) << S_CI1_ARB0_REQ)
18053 #define F_CI1_ARB0_REQ    V_CI1_ARB0_REQ(1U)
18054 
18055 #define S_ARB0_CI1_GNT    26
18056 #define V_ARB0_CI1_GNT(x) ((x) << S_ARB0_CI1_GNT)
18057 #define F_ARB0_CI1_GNT    V_ARB0_CI1_GNT(1U)
18058 
18059 #define S_CI1_DM0_WDATA_VLD    25
18060 #define V_CI1_DM0_WDATA_VLD(x) ((x) << S_CI1_DM0_WDATA_VLD)
18061 #define F_CI1_DM0_WDATA_VLD    V_CI1_DM0_WDATA_VLD(1U)
18062 
18063 #define S_DM0_CI1_RDATA_VLD    24
18064 #define V_DM0_CI1_RDATA_VLD(x) ((x) << S_DM0_CI1_RDATA_VLD)
18065 #define F_DM0_CI1_RDATA_VLD    V_DM0_CI1_RDATA_VLD(1U)
18066 
18067 #define S_CI2_ARB0_REQ    23
18068 #define V_CI2_ARB0_REQ(x) ((x) << S_CI2_ARB0_REQ)
18069 #define F_CI2_ARB0_REQ    V_CI2_ARB0_REQ(1U)
18070 
18071 #define S_ARB0_CI2_GNT    22
18072 #define V_ARB0_CI2_GNT(x) ((x) << S_ARB0_CI2_GNT)
18073 #define F_ARB0_CI2_GNT    V_ARB0_CI2_GNT(1U)
18074 
18075 #define S_CI2_DM0_WDATA_VLD    21
18076 #define V_CI2_DM0_WDATA_VLD(x) ((x) << S_CI2_DM0_WDATA_VLD)
18077 #define F_CI2_DM0_WDATA_VLD    V_CI2_DM0_WDATA_VLD(1U)
18078 
18079 #define S_DM0_CI2_RDATA_VLD    20
18080 #define V_DM0_CI2_RDATA_VLD(x) ((x) << S_DM0_CI2_RDATA_VLD)
18081 #define F_DM0_CI2_RDATA_VLD    V_DM0_CI2_RDATA_VLD(1U)
18082 
18083 #define S_CI3_ARB0_REQ    19
18084 #define V_CI3_ARB0_REQ(x) ((x) << S_CI3_ARB0_REQ)
18085 #define F_CI3_ARB0_REQ    V_CI3_ARB0_REQ(1U)
18086 
18087 #define S_ARB0_CI3_GNT    18
18088 #define V_ARB0_CI3_GNT(x) ((x) << S_ARB0_CI3_GNT)
18089 #define F_ARB0_CI3_GNT    V_ARB0_CI3_GNT(1U)
18090 
18091 #define S_CI3_DM0_WDATA_VLD    17
18092 #define V_CI3_DM0_WDATA_VLD(x) ((x) << S_CI3_DM0_WDATA_VLD)
18093 #define F_CI3_DM0_WDATA_VLD    V_CI3_DM0_WDATA_VLD(1U)
18094 
18095 #define S_DM0_CI3_RDATA_VLD    16
18096 #define V_DM0_CI3_RDATA_VLD(x) ((x) << S_DM0_CI3_RDATA_VLD)
18097 #define F_DM0_CI3_RDATA_VLD    V_DM0_CI3_RDATA_VLD(1U)
18098 
18099 #define S_CI4_ARB0_REQ    15
18100 #define V_CI4_ARB0_REQ(x) ((x) << S_CI4_ARB0_REQ)
18101 #define F_CI4_ARB0_REQ    V_CI4_ARB0_REQ(1U)
18102 
18103 #define S_ARB0_CI4_GNT    14
18104 #define V_ARB0_CI4_GNT(x) ((x) << S_ARB0_CI4_GNT)
18105 #define F_ARB0_CI4_GNT    V_ARB0_CI4_GNT(1U)
18106 
18107 #define S_CI4_DM0_WDATA_VLD    13
18108 #define V_CI4_DM0_WDATA_VLD(x) ((x) << S_CI4_DM0_WDATA_VLD)
18109 #define F_CI4_DM0_WDATA_VLD    V_CI4_DM0_WDATA_VLD(1U)
18110 
18111 #define S_DM0_CI4_RDATA_VLD    12
18112 #define V_DM0_CI4_RDATA_VLD(x) ((x) << S_DM0_CI4_RDATA_VLD)
18113 #define F_DM0_CI4_RDATA_VLD    V_DM0_CI4_RDATA_VLD(1U)
18114 
18115 #define S_CI5_ARB0_REQ    11
18116 #define V_CI5_ARB0_REQ(x) ((x) << S_CI5_ARB0_REQ)
18117 #define F_CI5_ARB0_REQ    V_CI5_ARB0_REQ(1U)
18118 
18119 #define S_ARB0_CI5_GNT    10
18120 #define V_ARB0_CI5_GNT(x) ((x) << S_ARB0_CI5_GNT)
18121 #define F_ARB0_CI5_GNT    V_ARB0_CI5_GNT(1U)
18122 
18123 #define S_CI5_DM0_WDATA_VLD    9
18124 #define V_CI5_DM0_WDATA_VLD(x) ((x) << S_CI5_DM0_WDATA_VLD)
18125 #define F_CI5_DM0_WDATA_VLD    V_CI5_DM0_WDATA_VLD(1U)
18126 
18127 #define S_DM0_CI5_RDATA_VLD    8
18128 #define V_DM0_CI5_RDATA_VLD(x) ((x) << S_DM0_CI5_RDATA_VLD)
18129 #define F_DM0_CI5_RDATA_VLD    V_DM0_CI5_RDATA_VLD(1U)
18130 
18131 #define S_CI6_ARB0_REQ    7
18132 #define V_CI6_ARB0_REQ(x) ((x) << S_CI6_ARB0_REQ)
18133 #define F_CI6_ARB0_REQ    V_CI6_ARB0_REQ(1U)
18134 
18135 #define S_ARB0_CI6_GNT    6
18136 #define V_ARB0_CI6_GNT(x) ((x) << S_ARB0_CI6_GNT)
18137 #define F_ARB0_CI6_GNT    V_ARB0_CI6_GNT(1U)
18138 
18139 #define S_CI6_DM0_WDATA_VLD    5
18140 #define V_CI6_DM0_WDATA_VLD(x) ((x) << S_CI6_DM0_WDATA_VLD)
18141 #define F_CI6_DM0_WDATA_VLD    V_CI6_DM0_WDATA_VLD(1U)
18142 
18143 #define S_DM0_CI6_RDATA_VLD    4
18144 #define V_DM0_CI6_RDATA_VLD(x) ((x) << S_DM0_CI6_RDATA_VLD)
18145 #define F_DM0_CI6_RDATA_VLD    V_DM0_CI6_RDATA_VLD(1U)
18146 
18147 #define S_CI7_ARB0_REQ    3
18148 #define V_CI7_ARB0_REQ(x) ((x) << S_CI7_ARB0_REQ)
18149 #define F_CI7_ARB0_REQ    V_CI7_ARB0_REQ(1U)
18150 
18151 #define S_ARB0_CI7_GNT    2
18152 #define V_ARB0_CI7_GNT(x) ((x) << S_ARB0_CI7_GNT)
18153 #define F_ARB0_CI7_GNT    V_ARB0_CI7_GNT(1U)
18154 
18155 #define S_CI7_DM0_WDATA_VLD    1
18156 #define V_CI7_DM0_WDATA_VLD(x) ((x) << S_CI7_DM0_WDATA_VLD)
18157 #define F_CI7_DM0_WDATA_VLD    V_CI7_DM0_WDATA_VLD(1U)
18158 
18159 #define S_DM0_CI7_RDATA_VLD    0
18160 #define V_DM0_CI7_RDATA_VLD(x) ((x) << S_DM0_CI7_RDATA_VLD)
18161 #define F_DM0_CI7_RDATA_VLD    V_DM0_CI7_RDATA_VLD(1U)
18162 
18163 #define A_MA_TARGET_1_ARBITER_INTERFACE_EXTERNAL_REG0 0xa00e
18164 
18165 #define S_CI0_ARB1_REQ    31
18166 #define V_CI0_ARB1_REQ(x) ((x) << S_CI0_ARB1_REQ)
18167 #define F_CI0_ARB1_REQ    V_CI0_ARB1_REQ(1U)
18168 
18169 #define S_ARB1_CI0_GNT    30
18170 #define V_ARB1_CI0_GNT(x) ((x) << S_ARB1_CI0_GNT)
18171 #define F_ARB1_CI0_GNT    V_ARB1_CI0_GNT(1U)
18172 
18173 #define S_CI0_DM1_WDATA_VLD    29
18174 #define V_CI0_DM1_WDATA_VLD(x) ((x) << S_CI0_DM1_WDATA_VLD)
18175 #define F_CI0_DM1_WDATA_VLD    V_CI0_DM1_WDATA_VLD(1U)
18176 
18177 #define S_DM1_CI0_RDATA_VLD    28
18178 #define V_DM1_CI0_RDATA_VLD(x) ((x) << S_DM1_CI0_RDATA_VLD)
18179 #define F_DM1_CI0_RDATA_VLD    V_DM1_CI0_RDATA_VLD(1U)
18180 
18181 #define S_CI1_ARB1_REQ    27
18182 #define V_CI1_ARB1_REQ(x) ((x) << S_CI1_ARB1_REQ)
18183 #define F_CI1_ARB1_REQ    V_CI1_ARB1_REQ(1U)
18184 
18185 #define S_ARB1_CI1_GNT    26
18186 #define V_ARB1_CI1_GNT(x) ((x) << S_ARB1_CI1_GNT)
18187 #define F_ARB1_CI1_GNT    V_ARB1_CI1_GNT(1U)
18188 
18189 #define S_CI1_DM1_WDATA_VLD    25
18190 #define V_CI1_DM1_WDATA_VLD(x) ((x) << S_CI1_DM1_WDATA_VLD)
18191 #define F_CI1_DM1_WDATA_VLD    V_CI1_DM1_WDATA_VLD(1U)
18192 
18193 #define S_DM1_CI1_RDATA_VLD    24
18194 #define V_DM1_CI1_RDATA_VLD(x) ((x) << S_DM1_CI1_RDATA_VLD)
18195 #define F_DM1_CI1_RDATA_VLD    V_DM1_CI1_RDATA_VLD(1U)
18196 
18197 #define S_CI2_ARB1_REQ    23
18198 #define V_CI2_ARB1_REQ(x) ((x) << S_CI2_ARB1_REQ)
18199 #define F_CI2_ARB1_REQ    V_CI2_ARB1_REQ(1U)
18200 
18201 #define S_ARB1_CI2_GNT    22
18202 #define V_ARB1_CI2_GNT(x) ((x) << S_ARB1_CI2_GNT)
18203 #define F_ARB1_CI2_GNT    V_ARB1_CI2_GNT(1U)
18204 
18205 #define S_CI2_DM1_WDATA_VLD    21
18206 #define V_CI2_DM1_WDATA_VLD(x) ((x) << S_CI2_DM1_WDATA_VLD)
18207 #define F_CI2_DM1_WDATA_VLD    V_CI2_DM1_WDATA_VLD(1U)
18208 
18209 #define S_DM1_CI2_RDATA_VLD    20
18210 #define V_DM1_CI2_RDATA_VLD(x) ((x) << S_DM1_CI2_RDATA_VLD)
18211 #define F_DM1_CI2_RDATA_VLD    V_DM1_CI2_RDATA_VLD(1U)
18212 
18213 #define S_CI3_ARB1_REQ    19
18214 #define V_CI3_ARB1_REQ(x) ((x) << S_CI3_ARB1_REQ)
18215 #define F_CI3_ARB1_REQ    V_CI3_ARB1_REQ(1U)
18216 
18217 #define S_ARB1_CI3_GNT    18
18218 #define V_ARB1_CI3_GNT(x) ((x) << S_ARB1_CI3_GNT)
18219 #define F_ARB1_CI3_GNT    V_ARB1_CI3_GNT(1U)
18220 
18221 #define S_CI3_DM1_WDATA_VLD    17
18222 #define V_CI3_DM1_WDATA_VLD(x) ((x) << S_CI3_DM1_WDATA_VLD)
18223 #define F_CI3_DM1_WDATA_VLD    V_CI3_DM1_WDATA_VLD(1U)
18224 
18225 #define S_DM1_CI3_RDATA_VLD    16
18226 #define V_DM1_CI3_RDATA_VLD(x) ((x) << S_DM1_CI3_RDATA_VLD)
18227 #define F_DM1_CI3_RDATA_VLD    V_DM1_CI3_RDATA_VLD(1U)
18228 
18229 #define S_CI4_ARB1_REQ    15
18230 #define V_CI4_ARB1_REQ(x) ((x) << S_CI4_ARB1_REQ)
18231 #define F_CI4_ARB1_REQ    V_CI4_ARB1_REQ(1U)
18232 
18233 #define S_ARB1_CI4_GNT    14
18234 #define V_ARB1_CI4_GNT(x) ((x) << S_ARB1_CI4_GNT)
18235 #define F_ARB1_CI4_GNT    V_ARB1_CI4_GNT(1U)
18236 
18237 #define S_CI4_DM1_WDATA_VLD    13
18238 #define V_CI4_DM1_WDATA_VLD(x) ((x) << S_CI4_DM1_WDATA_VLD)
18239 #define F_CI4_DM1_WDATA_VLD    V_CI4_DM1_WDATA_VLD(1U)
18240 
18241 #define S_DM1_CI4_RDATA_VLD    12
18242 #define V_DM1_CI4_RDATA_VLD(x) ((x) << S_DM1_CI4_RDATA_VLD)
18243 #define F_DM1_CI4_RDATA_VLD    V_DM1_CI4_RDATA_VLD(1U)
18244 
18245 #define S_CI5_ARB1_REQ    11
18246 #define V_CI5_ARB1_REQ(x) ((x) << S_CI5_ARB1_REQ)
18247 #define F_CI5_ARB1_REQ    V_CI5_ARB1_REQ(1U)
18248 
18249 #define S_ARB1_CI5_GNT    10
18250 #define V_ARB1_CI5_GNT(x) ((x) << S_ARB1_CI5_GNT)
18251 #define F_ARB1_CI5_GNT    V_ARB1_CI5_GNT(1U)
18252 
18253 #define S_CI5_DM1_WDATA_VLD    9
18254 #define V_CI5_DM1_WDATA_VLD(x) ((x) << S_CI5_DM1_WDATA_VLD)
18255 #define F_CI5_DM1_WDATA_VLD    V_CI5_DM1_WDATA_VLD(1U)
18256 
18257 #define S_DM1_CI5_RDATA_VLD    8
18258 #define V_DM1_CI5_RDATA_VLD(x) ((x) << S_DM1_CI5_RDATA_VLD)
18259 #define F_DM1_CI5_RDATA_VLD    V_DM1_CI5_RDATA_VLD(1U)
18260 
18261 #define S_CI6_ARB1_REQ    7
18262 #define V_CI6_ARB1_REQ(x) ((x) << S_CI6_ARB1_REQ)
18263 #define F_CI6_ARB1_REQ    V_CI6_ARB1_REQ(1U)
18264 
18265 #define S_ARB1_CI6_GNT    6
18266 #define V_ARB1_CI6_GNT(x) ((x) << S_ARB1_CI6_GNT)
18267 #define F_ARB1_CI6_GNT    V_ARB1_CI6_GNT(1U)
18268 
18269 #define S_CI6_DM1_WDATA_VLD    5
18270 #define V_CI6_DM1_WDATA_VLD(x) ((x) << S_CI6_DM1_WDATA_VLD)
18271 #define F_CI6_DM1_WDATA_VLD    V_CI6_DM1_WDATA_VLD(1U)
18272 
18273 #define S_DM1_CI6_RDATA_VLD    4
18274 #define V_DM1_CI6_RDATA_VLD(x) ((x) << S_DM1_CI6_RDATA_VLD)
18275 #define F_DM1_CI6_RDATA_VLD    V_DM1_CI6_RDATA_VLD(1U)
18276 
18277 #define S_CI7_ARB1_REQ    3
18278 #define V_CI7_ARB1_REQ(x) ((x) << S_CI7_ARB1_REQ)
18279 #define F_CI7_ARB1_REQ    V_CI7_ARB1_REQ(1U)
18280 
18281 #define S_ARB1_CI7_GNT    2
18282 #define V_ARB1_CI7_GNT(x) ((x) << S_ARB1_CI7_GNT)
18283 #define F_ARB1_CI7_GNT    V_ARB1_CI7_GNT(1U)
18284 
18285 #define S_CI7_DM1_WDATA_VLD    1
18286 #define V_CI7_DM1_WDATA_VLD(x) ((x) << S_CI7_DM1_WDATA_VLD)
18287 #define F_CI7_DM1_WDATA_VLD    V_CI7_DM1_WDATA_VLD(1U)
18288 
18289 #define S_DM1_CI7_RDATA_VLD    0
18290 #define V_DM1_CI7_RDATA_VLD(x) ((x) << S_DM1_CI7_RDATA_VLD)
18291 #define F_DM1_CI7_RDATA_VLD    V_DM1_CI7_RDATA_VLD(1U)
18292 
18293 #define A_MA_TARGET_2_ARBITER_INTERFACE_EXTERNAL_REG0 0xa00f
18294 
18295 #define S_CI0_ARB2_REQ    31
18296 #define V_CI0_ARB2_REQ(x) ((x) << S_CI0_ARB2_REQ)
18297 #define F_CI0_ARB2_REQ    V_CI0_ARB2_REQ(1U)
18298 
18299 #define S_ARB2_CI0_GNT    30
18300 #define V_ARB2_CI0_GNT(x) ((x) << S_ARB2_CI0_GNT)
18301 #define F_ARB2_CI0_GNT    V_ARB2_CI0_GNT(1U)
18302 
18303 #define S_CI0_DM2_WDATA_VLD    29
18304 #define V_CI0_DM2_WDATA_VLD(x) ((x) << S_CI0_DM2_WDATA_VLD)
18305 #define F_CI0_DM2_WDATA_VLD    V_CI0_DM2_WDATA_VLD(1U)
18306 
18307 #define S_DM2_CI0_RDATA_VLD    28
18308 #define V_DM2_CI0_RDATA_VLD(x) ((x) << S_DM2_CI0_RDATA_VLD)
18309 #define F_DM2_CI0_RDATA_VLD    V_DM2_CI0_RDATA_VLD(1U)
18310 
18311 #define S_CI1_ARB2_REQ    27
18312 #define V_CI1_ARB2_REQ(x) ((x) << S_CI1_ARB2_REQ)
18313 #define F_CI1_ARB2_REQ    V_CI1_ARB2_REQ(1U)
18314 
18315 #define S_ARB2_CI1_GNT    26
18316 #define V_ARB2_CI1_GNT(x) ((x) << S_ARB2_CI1_GNT)
18317 #define F_ARB2_CI1_GNT    V_ARB2_CI1_GNT(1U)
18318 
18319 #define S_CI1_DM2_WDATA_VLD    25
18320 #define V_CI1_DM2_WDATA_VLD(x) ((x) << S_CI1_DM2_WDATA_VLD)
18321 #define F_CI1_DM2_WDATA_VLD    V_CI1_DM2_WDATA_VLD(1U)
18322 
18323 #define S_DM2_CI1_RDATA_VLD    24
18324 #define V_DM2_CI1_RDATA_VLD(x) ((x) << S_DM2_CI1_RDATA_VLD)
18325 #define F_DM2_CI1_RDATA_VLD    V_DM2_CI1_RDATA_VLD(1U)
18326 
18327 #define S_CI2_ARB2_REQ    23
18328 #define V_CI2_ARB2_REQ(x) ((x) << S_CI2_ARB2_REQ)
18329 #define F_CI2_ARB2_REQ    V_CI2_ARB2_REQ(1U)
18330 
18331 #define S_ARB2_CI2_GNT    22
18332 #define V_ARB2_CI2_GNT(x) ((x) << S_ARB2_CI2_GNT)
18333 #define F_ARB2_CI2_GNT    V_ARB2_CI2_GNT(1U)
18334 
18335 #define S_CI2_DM2_WDATA_VLD    21
18336 #define V_CI2_DM2_WDATA_VLD(x) ((x) << S_CI2_DM2_WDATA_VLD)
18337 #define F_CI2_DM2_WDATA_VLD    V_CI2_DM2_WDATA_VLD(1U)
18338 
18339 #define S_DM2_CI2_RDATA_VLD    20
18340 #define V_DM2_CI2_RDATA_VLD(x) ((x) << S_DM2_CI2_RDATA_VLD)
18341 #define F_DM2_CI2_RDATA_VLD    V_DM2_CI2_RDATA_VLD(1U)
18342 
18343 #define S_CI3_ARB2_REQ    19
18344 #define V_CI3_ARB2_REQ(x) ((x) << S_CI3_ARB2_REQ)
18345 #define F_CI3_ARB2_REQ    V_CI3_ARB2_REQ(1U)
18346 
18347 #define S_ARB2_CI3_GNT    18
18348 #define V_ARB2_CI3_GNT(x) ((x) << S_ARB2_CI3_GNT)
18349 #define F_ARB2_CI3_GNT    V_ARB2_CI3_GNT(1U)
18350 
18351 #define S_CI3_DM2_WDATA_VLD    17
18352 #define V_CI3_DM2_WDATA_VLD(x) ((x) << S_CI3_DM2_WDATA_VLD)
18353 #define F_CI3_DM2_WDATA_VLD    V_CI3_DM2_WDATA_VLD(1U)
18354 
18355 #define S_DM2_CI3_RDATA_VLD    16
18356 #define V_DM2_CI3_RDATA_VLD(x) ((x) << S_DM2_CI3_RDATA_VLD)
18357 #define F_DM2_CI3_RDATA_VLD    V_DM2_CI3_RDATA_VLD(1U)
18358 
18359 #define S_CI4_ARB2_REQ    15
18360 #define V_CI4_ARB2_REQ(x) ((x) << S_CI4_ARB2_REQ)
18361 #define F_CI4_ARB2_REQ    V_CI4_ARB2_REQ(1U)
18362 
18363 #define S_ARB2_CI4_GNT    14
18364 #define V_ARB2_CI4_GNT(x) ((x) << S_ARB2_CI4_GNT)
18365 #define F_ARB2_CI4_GNT    V_ARB2_CI4_GNT(1U)
18366 
18367 #define S_CI4_DM2_WDATA_VLD    13
18368 #define V_CI4_DM2_WDATA_VLD(x) ((x) << S_CI4_DM2_WDATA_VLD)
18369 #define F_CI4_DM2_WDATA_VLD    V_CI4_DM2_WDATA_VLD(1U)
18370 
18371 #define S_DM2_CI4_RDATA_VLD    12
18372 #define V_DM2_CI4_RDATA_VLD(x) ((x) << S_DM2_CI4_RDATA_VLD)
18373 #define F_DM2_CI4_RDATA_VLD    V_DM2_CI4_RDATA_VLD(1U)
18374 
18375 #define S_CI5_ARB2_REQ    11
18376 #define V_CI5_ARB2_REQ(x) ((x) << S_CI5_ARB2_REQ)
18377 #define F_CI5_ARB2_REQ    V_CI5_ARB2_REQ(1U)
18378 
18379 #define S_ARB2_CI5_GNT    10
18380 #define V_ARB2_CI5_GNT(x) ((x) << S_ARB2_CI5_GNT)
18381 #define F_ARB2_CI5_GNT    V_ARB2_CI5_GNT(1U)
18382 
18383 #define S_CI5_DM2_WDATA_VLD    9
18384 #define V_CI5_DM2_WDATA_VLD(x) ((x) << S_CI5_DM2_WDATA_VLD)
18385 #define F_CI5_DM2_WDATA_VLD    V_CI5_DM2_WDATA_VLD(1U)
18386 
18387 #define S_DM2_CI5_RDATA_VLD    8
18388 #define V_DM2_CI5_RDATA_VLD(x) ((x) << S_DM2_CI5_RDATA_VLD)
18389 #define F_DM2_CI5_RDATA_VLD    V_DM2_CI5_RDATA_VLD(1U)
18390 
18391 #define S_CI6_ARB2_REQ    7
18392 #define V_CI6_ARB2_REQ(x) ((x) << S_CI6_ARB2_REQ)
18393 #define F_CI6_ARB2_REQ    V_CI6_ARB2_REQ(1U)
18394 
18395 #define S_ARB2_CI6_GNT    6
18396 #define V_ARB2_CI6_GNT(x) ((x) << S_ARB2_CI6_GNT)
18397 #define F_ARB2_CI6_GNT    V_ARB2_CI6_GNT(1U)
18398 
18399 #define S_CI6_DM2_WDATA_VLD    5
18400 #define V_CI6_DM2_WDATA_VLD(x) ((x) << S_CI6_DM2_WDATA_VLD)
18401 #define F_CI6_DM2_WDATA_VLD    V_CI6_DM2_WDATA_VLD(1U)
18402 
18403 #define S_DM2_CI6_RDATA_VLD    4
18404 #define V_DM2_CI6_RDATA_VLD(x) ((x) << S_DM2_CI6_RDATA_VLD)
18405 #define F_DM2_CI6_RDATA_VLD    V_DM2_CI6_RDATA_VLD(1U)
18406 
18407 #define S_CI7_ARB2_REQ    3
18408 #define V_CI7_ARB2_REQ(x) ((x) << S_CI7_ARB2_REQ)
18409 #define F_CI7_ARB2_REQ    V_CI7_ARB2_REQ(1U)
18410 
18411 #define S_ARB2_CI7_GNT    2
18412 #define V_ARB2_CI7_GNT(x) ((x) << S_ARB2_CI7_GNT)
18413 #define F_ARB2_CI7_GNT    V_ARB2_CI7_GNT(1U)
18414 
18415 #define S_CI7_DM2_WDATA_VLD    1
18416 #define V_CI7_DM2_WDATA_VLD(x) ((x) << S_CI7_DM2_WDATA_VLD)
18417 #define F_CI7_DM2_WDATA_VLD    V_CI7_DM2_WDATA_VLD(1U)
18418 
18419 #define S_DM2_CI7_RDATA_VLD    0
18420 #define V_DM2_CI7_RDATA_VLD(x) ((x) << S_DM2_CI7_RDATA_VLD)
18421 #define F_DM2_CI7_RDATA_VLD    V_DM2_CI7_RDATA_VLD(1U)
18422 
18423 #define A_MA_TARGET_3_ARBITER_INTERFACE_EXTERNAL_REG0 0xa010
18424 
18425 #define S_CI0_ARB3_REQ    31
18426 #define V_CI0_ARB3_REQ(x) ((x) << S_CI0_ARB3_REQ)
18427 #define F_CI0_ARB3_REQ    V_CI0_ARB3_REQ(1U)
18428 
18429 #define S_ARB3_CI0_GNT    30
18430 #define V_ARB3_CI0_GNT(x) ((x) << S_ARB3_CI0_GNT)
18431 #define F_ARB3_CI0_GNT    V_ARB3_CI0_GNT(1U)
18432 
18433 #define S_CI0_DM3_WDATA_VLD    29
18434 #define V_CI0_DM3_WDATA_VLD(x) ((x) << S_CI0_DM3_WDATA_VLD)
18435 #define F_CI0_DM3_WDATA_VLD    V_CI0_DM3_WDATA_VLD(1U)
18436 
18437 #define S_DM3_CI0_RDATA_VLD    28
18438 #define V_DM3_CI0_RDATA_VLD(x) ((x) << S_DM3_CI0_RDATA_VLD)
18439 #define F_DM3_CI0_RDATA_VLD    V_DM3_CI0_RDATA_VLD(1U)
18440 
18441 #define S_CI1_ARB3_REQ    27
18442 #define V_CI1_ARB3_REQ(x) ((x) << S_CI1_ARB3_REQ)
18443 #define F_CI1_ARB3_REQ    V_CI1_ARB3_REQ(1U)
18444 
18445 #define S_ARB3_CI1_GNT    26
18446 #define V_ARB3_CI1_GNT(x) ((x) << S_ARB3_CI1_GNT)
18447 #define F_ARB3_CI1_GNT    V_ARB3_CI1_GNT(1U)
18448 
18449 #define S_CI1_DM3_WDATA_VLD    25
18450 #define V_CI1_DM3_WDATA_VLD(x) ((x) << S_CI1_DM3_WDATA_VLD)
18451 #define F_CI1_DM3_WDATA_VLD    V_CI1_DM3_WDATA_VLD(1U)
18452 
18453 #define S_DM3_CI1_RDATA_VLD    24
18454 #define V_DM3_CI1_RDATA_VLD(x) ((x) << S_DM3_CI1_RDATA_VLD)
18455 #define F_DM3_CI1_RDATA_VLD    V_DM3_CI1_RDATA_VLD(1U)
18456 
18457 #define S_CI2_ARB3_REQ    23
18458 #define V_CI2_ARB3_REQ(x) ((x) << S_CI2_ARB3_REQ)
18459 #define F_CI2_ARB3_REQ    V_CI2_ARB3_REQ(1U)
18460 
18461 #define S_ARB3_CI2_GNT    22
18462 #define V_ARB3_CI2_GNT(x) ((x) << S_ARB3_CI2_GNT)
18463 #define F_ARB3_CI2_GNT    V_ARB3_CI2_GNT(1U)
18464 
18465 #define S_CI2_DM3_WDATA_VLD    21
18466 #define V_CI2_DM3_WDATA_VLD(x) ((x) << S_CI2_DM3_WDATA_VLD)
18467 #define F_CI2_DM3_WDATA_VLD    V_CI2_DM3_WDATA_VLD(1U)
18468 
18469 #define S_DM3_CI2_RDATA_VLD    20
18470 #define V_DM3_CI2_RDATA_VLD(x) ((x) << S_DM3_CI2_RDATA_VLD)
18471 #define F_DM3_CI2_RDATA_VLD    V_DM3_CI2_RDATA_VLD(1U)
18472 
18473 #define S_CI3_ARB3_REQ    19
18474 #define V_CI3_ARB3_REQ(x) ((x) << S_CI3_ARB3_REQ)
18475 #define F_CI3_ARB3_REQ    V_CI3_ARB3_REQ(1U)
18476 
18477 #define S_ARB3_CI3_GNT    18
18478 #define V_ARB3_CI3_GNT(x) ((x) << S_ARB3_CI3_GNT)
18479 #define F_ARB3_CI3_GNT    V_ARB3_CI3_GNT(1U)
18480 
18481 #define S_CI3_DM3_WDATA_VLD    17
18482 #define V_CI3_DM3_WDATA_VLD(x) ((x) << S_CI3_DM3_WDATA_VLD)
18483 #define F_CI3_DM3_WDATA_VLD    V_CI3_DM3_WDATA_VLD(1U)
18484 
18485 #define S_DM3_CI3_RDATA_VLD    16
18486 #define V_DM3_CI3_RDATA_VLD(x) ((x) << S_DM3_CI3_RDATA_VLD)
18487 #define F_DM3_CI3_RDATA_VLD    V_DM3_CI3_RDATA_VLD(1U)
18488 
18489 #define S_CI4_ARB3_REQ    15
18490 #define V_CI4_ARB3_REQ(x) ((x) << S_CI4_ARB3_REQ)
18491 #define F_CI4_ARB3_REQ    V_CI4_ARB3_REQ(1U)
18492 
18493 #define S_ARB3_CI4_GNT    14
18494 #define V_ARB3_CI4_GNT(x) ((x) << S_ARB3_CI4_GNT)
18495 #define F_ARB3_CI4_GNT    V_ARB3_CI4_GNT(1U)
18496 
18497 #define S_CI4_DM3_WDATA_VLD    13
18498 #define V_CI4_DM3_WDATA_VLD(x) ((x) << S_CI4_DM3_WDATA_VLD)
18499 #define F_CI4_DM3_WDATA_VLD    V_CI4_DM3_WDATA_VLD(1U)
18500 
18501 #define S_DM3_CI4_RDATA_VLD    12
18502 #define V_DM3_CI4_RDATA_VLD(x) ((x) << S_DM3_CI4_RDATA_VLD)
18503 #define F_DM3_CI4_RDATA_VLD    V_DM3_CI4_RDATA_VLD(1U)
18504 
18505 #define S_CI5_ARB3_REQ    11
18506 #define V_CI5_ARB3_REQ(x) ((x) << S_CI5_ARB3_REQ)
18507 #define F_CI5_ARB3_REQ    V_CI5_ARB3_REQ(1U)
18508 
18509 #define S_ARB3_CI5_GNT    10
18510 #define V_ARB3_CI5_GNT(x) ((x) << S_ARB3_CI5_GNT)
18511 #define F_ARB3_CI5_GNT    V_ARB3_CI5_GNT(1U)
18512 
18513 #define S_CI5_DM3_WDATA_VLD    9
18514 #define V_CI5_DM3_WDATA_VLD(x) ((x) << S_CI5_DM3_WDATA_VLD)
18515 #define F_CI5_DM3_WDATA_VLD    V_CI5_DM3_WDATA_VLD(1U)
18516 
18517 #define S_DM3_CI5_RDATA_VLD    8
18518 #define V_DM3_CI5_RDATA_VLD(x) ((x) << S_DM3_CI5_RDATA_VLD)
18519 #define F_DM3_CI5_RDATA_VLD    V_DM3_CI5_RDATA_VLD(1U)
18520 
18521 #define S_CI6_ARB3_REQ    7
18522 #define V_CI6_ARB3_REQ(x) ((x) << S_CI6_ARB3_REQ)
18523 #define F_CI6_ARB3_REQ    V_CI6_ARB3_REQ(1U)
18524 
18525 #define S_ARB3_CI6_GNT    6
18526 #define V_ARB3_CI6_GNT(x) ((x) << S_ARB3_CI6_GNT)
18527 #define F_ARB3_CI6_GNT    V_ARB3_CI6_GNT(1U)
18528 
18529 #define S_CI6_DM3_WDATA_VLD    5
18530 #define V_CI6_DM3_WDATA_VLD(x) ((x) << S_CI6_DM3_WDATA_VLD)
18531 #define F_CI6_DM3_WDATA_VLD    V_CI6_DM3_WDATA_VLD(1U)
18532 
18533 #define S_DM3_CI6_RDATA_VLD    4
18534 #define V_DM3_CI6_RDATA_VLD(x) ((x) << S_DM3_CI6_RDATA_VLD)
18535 #define F_DM3_CI6_RDATA_VLD    V_DM3_CI6_RDATA_VLD(1U)
18536 
18537 #define S_CI7_ARB3_REQ    3
18538 #define V_CI7_ARB3_REQ(x) ((x) << S_CI7_ARB3_REQ)
18539 #define F_CI7_ARB3_REQ    V_CI7_ARB3_REQ(1U)
18540 
18541 #define S_ARB3_CI7_GNT    2
18542 #define V_ARB3_CI7_GNT(x) ((x) << S_ARB3_CI7_GNT)
18543 #define F_ARB3_CI7_GNT    V_ARB3_CI7_GNT(1U)
18544 
18545 #define S_CI7_DM3_WDATA_VLD    1
18546 #define V_CI7_DM3_WDATA_VLD(x) ((x) << S_CI7_DM3_WDATA_VLD)
18547 #define F_CI7_DM3_WDATA_VLD    V_CI7_DM3_WDATA_VLD(1U)
18548 
18549 #define S_DM3_CI7_RDATA_VLD    0
18550 #define V_DM3_CI7_RDATA_VLD(x) ((x) << S_DM3_CI7_RDATA_VLD)
18551 #define F_DM3_CI7_RDATA_VLD    V_DM3_CI7_RDATA_VLD(1U)
18552 
18553 #define A_MA_MA_DEBUG_SIGNATURE_LTL_END 0xa011
18554 #define A_MA_MA_DEBUG_SIGNATURE_BIG_END_INVERSE 0xa012
18555 #define A_MA_TARGET_0_ARBITER_INTERFACE_EXTERNAL_REG1 0xa013
18556 
18557 #define S_CI8_ARB0_REQ    31
18558 #define V_CI8_ARB0_REQ(x) ((x) << S_CI8_ARB0_REQ)
18559 #define F_CI8_ARB0_REQ    V_CI8_ARB0_REQ(1U)
18560 
18561 #define S_ARB0_CI8_GNT    30
18562 #define V_ARB0_CI8_GNT(x) ((x) << S_ARB0_CI8_GNT)
18563 #define F_ARB0_CI8_GNT    V_ARB0_CI8_GNT(1U)
18564 
18565 #define S_CI8_DM0_WDATA_VLD    29
18566 #define V_CI8_DM0_WDATA_VLD(x) ((x) << S_CI8_DM0_WDATA_VLD)
18567 #define F_CI8_DM0_WDATA_VLD    V_CI8_DM0_WDATA_VLD(1U)
18568 
18569 #define S_DM0_CI8_RDATA_VLD    28
18570 #define V_DM0_CI8_RDATA_VLD(x) ((x) << S_DM0_CI8_RDATA_VLD)
18571 #define F_DM0_CI8_RDATA_VLD    V_DM0_CI8_RDATA_VLD(1U)
18572 
18573 #define S_CI9_ARB0_REQ    27
18574 #define V_CI9_ARB0_REQ(x) ((x) << S_CI9_ARB0_REQ)
18575 #define F_CI9_ARB0_REQ    V_CI9_ARB0_REQ(1U)
18576 
18577 #define S_ARB0_CI9_GNT    26
18578 #define V_ARB0_CI9_GNT(x) ((x) << S_ARB0_CI9_GNT)
18579 #define F_ARB0_CI9_GNT    V_ARB0_CI9_GNT(1U)
18580 
18581 #define S_CI9_DM0_WDATA_VLD    25
18582 #define V_CI9_DM0_WDATA_VLD(x) ((x) << S_CI9_DM0_WDATA_VLD)
18583 #define F_CI9_DM0_WDATA_VLD    V_CI9_DM0_WDATA_VLD(1U)
18584 
18585 #define S_DM0_CI9_RDATA_VLD    24
18586 #define V_DM0_CI9_RDATA_VLD(x) ((x) << S_DM0_CI9_RDATA_VLD)
18587 #define F_DM0_CI9_RDATA_VLD    V_DM0_CI9_RDATA_VLD(1U)
18588 
18589 #define S_CI10_ARB0_REQ    23
18590 #define V_CI10_ARB0_REQ(x) ((x) << S_CI10_ARB0_REQ)
18591 #define F_CI10_ARB0_REQ    V_CI10_ARB0_REQ(1U)
18592 
18593 #define S_ARB0_CI10_GNT    22
18594 #define V_ARB0_CI10_GNT(x) ((x) << S_ARB0_CI10_GNT)
18595 #define F_ARB0_CI10_GNT    V_ARB0_CI10_GNT(1U)
18596 
18597 #define S_CI10_DM0_WDATA_VLD    21
18598 #define V_CI10_DM0_WDATA_VLD(x) ((x) << S_CI10_DM0_WDATA_VLD)
18599 #define F_CI10_DM0_WDATA_VLD    V_CI10_DM0_WDATA_VLD(1U)
18600 
18601 #define S_DM0_CI10_RDATA_VLD    20
18602 #define V_DM0_CI10_RDATA_VLD(x) ((x) << S_DM0_CI10_RDATA_VLD)
18603 #define F_DM0_CI10_RDATA_VLD    V_DM0_CI10_RDATA_VLD(1U)
18604 
18605 #define S_CI11_ARB0_REQ    19
18606 #define V_CI11_ARB0_REQ(x) ((x) << S_CI11_ARB0_REQ)
18607 #define F_CI11_ARB0_REQ    V_CI11_ARB0_REQ(1U)
18608 
18609 #define S_ARB0_CI11_GNT    18
18610 #define V_ARB0_CI11_GNT(x) ((x) << S_ARB0_CI11_GNT)
18611 #define F_ARB0_CI11_GNT    V_ARB0_CI11_GNT(1U)
18612 
18613 #define S_CI11_DM0_WDATA_VLD    17
18614 #define V_CI11_DM0_WDATA_VLD(x) ((x) << S_CI11_DM0_WDATA_VLD)
18615 #define F_CI11_DM0_WDATA_VLD    V_CI11_DM0_WDATA_VLD(1U)
18616 
18617 #define S_DM0_CI11_RDATA_VLD    16
18618 #define V_DM0_CI11_RDATA_VLD(x) ((x) << S_DM0_CI11_RDATA_VLD)
18619 #define F_DM0_CI11_RDATA_VLD    V_DM0_CI11_RDATA_VLD(1U)
18620 
18621 #define S_CI12_ARB0_REQ    15
18622 #define V_CI12_ARB0_REQ(x) ((x) << S_CI12_ARB0_REQ)
18623 #define F_CI12_ARB0_REQ    V_CI12_ARB0_REQ(1U)
18624 
18625 #define S_ARB0_CI12_GNT    14
18626 #define V_ARB0_CI12_GNT(x) ((x) << S_ARB0_CI12_GNT)
18627 #define F_ARB0_CI12_GNT    V_ARB0_CI12_GNT(1U)
18628 
18629 #define S_CI12_DM0_WDATA_VLD    13
18630 #define V_CI12_DM0_WDATA_VLD(x) ((x) << S_CI12_DM0_WDATA_VLD)
18631 #define F_CI12_DM0_WDATA_VLD    V_CI12_DM0_WDATA_VLD(1U)
18632 
18633 #define S_DM0_CI12_RDATA_VLD    12
18634 #define V_DM0_CI12_RDATA_VLD(x) ((x) << S_DM0_CI12_RDATA_VLD)
18635 #define F_DM0_CI12_RDATA_VLD    V_DM0_CI12_RDATA_VLD(1U)
18636 
18637 #define A_MA_TARGET_1_ARBITER_INTERFACE_EXTERNAL_REG1 0xa014
18638 
18639 #define S_CI8_ARB1_REQ    31
18640 #define V_CI8_ARB1_REQ(x) ((x) << S_CI8_ARB1_REQ)
18641 #define F_CI8_ARB1_REQ    V_CI8_ARB1_REQ(1U)
18642 
18643 #define S_ARB1_CI8_GNT    30
18644 #define V_ARB1_CI8_GNT(x) ((x) << S_ARB1_CI8_GNT)
18645 #define F_ARB1_CI8_GNT    V_ARB1_CI8_GNT(1U)
18646 
18647 #define S_CI8_DM1_WDATA_VLD    29
18648 #define V_CI8_DM1_WDATA_VLD(x) ((x) << S_CI8_DM1_WDATA_VLD)
18649 #define F_CI8_DM1_WDATA_VLD    V_CI8_DM1_WDATA_VLD(1U)
18650 
18651 #define S_DM1_CI8_RDATA_VLD    28
18652 #define V_DM1_CI8_RDATA_VLD(x) ((x) << S_DM1_CI8_RDATA_VLD)
18653 #define F_DM1_CI8_RDATA_VLD    V_DM1_CI8_RDATA_VLD(1U)
18654 
18655 #define S_CI9_ARB1_REQ    27
18656 #define V_CI9_ARB1_REQ(x) ((x) << S_CI9_ARB1_REQ)
18657 #define F_CI9_ARB1_REQ    V_CI9_ARB1_REQ(1U)
18658 
18659 #define S_ARB1_CI9_GNT    26
18660 #define V_ARB1_CI9_GNT(x) ((x) << S_ARB1_CI9_GNT)
18661 #define F_ARB1_CI9_GNT    V_ARB1_CI9_GNT(1U)
18662 
18663 #define S_CI9_DM1_WDATA_VLD    25
18664 #define V_CI9_DM1_WDATA_VLD(x) ((x) << S_CI9_DM1_WDATA_VLD)
18665 #define F_CI9_DM1_WDATA_VLD    V_CI9_DM1_WDATA_VLD(1U)
18666 
18667 #define S_DM1_CI9_RDATA_VLD    24
18668 #define V_DM1_CI9_RDATA_VLD(x) ((x) << S_DM1_CI9_RDATA_VLD)
18669 #define F_DM1_CI9_RDATA_VLD    V_DM1_CI9_RDATA_VLD(1U)
18670 
18671 #define S_CI10_ARB1_REQ    23
18672 #define V_CI10_ARB1_REQ(x) ((x) << S_CI10_ARB1_REQ)
18673 #define F_CI10_ARB1_REQ    V_CI10_ARB1_REQ(1U)
18674 
18675 #define S_ARB1_CI10_GNT    22
18676 #define V_ARB1_CI10_GNT(x) ((x) << S_ARB1_CI10_GNT)
18677 #define F_ARB1_CI10_GNT    V_ARB1_CI10_GNT(1U)
18678 
18679 #define S_CI10_DM1_WDATA_VLD    21
18680 #define V_CI10_DM1_WDATA_VLD(x) ((x) << S_CI10_DM1_WDATA_VLD)
18681 #define F_CI10_DM1_WDATA_VLD    V_CI10_DM1_WDATA_VLD(1U)
18682 
18683 #define S_DM1_CI10_RDATA_VLD    20
18684 #define V_DM1_CI10_RDATA_VLD(x) ((x) << S_DM1_CI10_RDATA_VLD)
18685 #define F_DM1_CI10_RDATA_VLD    V_DM1_CI10_RDATA_VLD(1U)
18686 
18687 #define S_CI11_ARB1_REQ    19
18688 #define V_CI11_ARB1_REQ(x) ((x) << S_CI11_ARB1_REQ)
18689 #define F_CI11_ARB1_REQ    V_CI11_ARB1_REQ(1U)
18690 
18691 #define S_ARB1_CI11_GNT    18
18692 #define V_ARB1_CI11_GNT(x) ((x) << S_ARB1_CI11_GNT)
18693 #define F_ARB1_CI11_GNT    V_ARB1_CI11_GNT(1U)
18694 
18695 #define S_CI11_DM1_WDATA_VLD    17
18696 #define V_CI11_DM1_WDATA_VLD(x) ((x) << S_CI11_DM1_WDATA_VLD)
18697 #define F_CI11_DM1_WDATA_VLD    V_CI11_DM1_WDATA_VLD(1U)
18698 
18699 #define S_DM1_CI11_RDATA_VLD    16
18700 #define V_DM1_CI11_RDATA_VLD(x) ((x) << S_DM1_CI11_RDATA_VLD)
18701 #define F_DM1_CI11_RDATA_VLD    V_DM1_CI11_RDATA_VLD(1U)
18702 
18703 #define S_CI12_ARB1_REQ    15
18704 #define V_CI12_ARB1_REQ(x) ((x) << S_CI12_ARB1_REQ)
18705 #define F_CI12_ARB1_REQ    V_CI12_ARB1_REQ(1U)
18706 
18707 #define S_ARB1_CI12_GNT    14
18708 #define V_ARB1_CI12_GNT(x) ((x) << S_ARB1_CI12_GNT)
18709 #define F_ARB1_CI12_GNT    V_ARB1_CI12_GNT(1U)
18710 
18711 #define S_CI12_DM1_WDATA_VLD    13
18712 #define V_CI12_DM1_WDATA_VLD(x) ((x) << S_CI12_DM1_WDATA_VLD)
18713 #define F_CI12_DM1_WDATA_VLD    V_CI12_DM1_WDATA_VLD(1U)
18714 
18715 #define S_DM1_CI12_RDATA_VLD    12
18716 #define V_DM1_CI12_RDATA_VLD(x) ((x) << S_DM1_CI12_RDATA_VLD)
18717 #define F_DM1_CI12_RDATA_VLD    V_DM1_CI12_RDATA_VLD(1U)
18718 
18719 #define A_MA_TARGET_2_ARBITER_INTERFACE_EXTERNAL_REG1 0xa015
18720 
18721 #define S_CI8_ARB2_REQ    31
18722 #define V_CI8_ARB2_REQ(x) ((x) << S_CI8_ARB2_REQ)
18723 #define F_CI8_ARB2_REQ    V_CI8_ARB2_REQ(1U)
18724 
18725 #define S_ARB2_CI8_GNT    30
18726 #define V_ARB2_CI8_GNT(x) ((x) << S_ARB2_CI8_GNT)
18727 #define F_ARB2_CI8_GNT    V_ARB2_CI8_GNT(1U)
18728 
18729 #define S_CI8_DM2_WDATA_VLD    29
18730 #define V_CI8_DM2_WDATA_VLD(x) ((x) << S_CI8_DM2_WDATA_VLD)
18731 #define F_CI8_DM2_WDATA_VLD    V_CI8_DM2_WDATA_VLD(1U)
18732 
18733 #define S_DM2_CI8_RDATA_VLD    28
18734 #define V_DM2_CI8_RDATA_VLD(x) ((x) << S_DM2_CI8_RDATA_VLD)
18735 #define F_DM2_CI8_RDATA_VLD    V_DM2_CI8_RDATA_VLD(1U)
18736 
18737 #define S_CI9_ARB2_REQ    27
18738 #define V_CI9_ARB2_REQ(x) ((x) << S_CI9_ARB2_REQ)
18739 #define F_CI9_ARB2_REQ    V_CI9_ARB2_REQ(1U)
18740 
18741 #define S_ARB2_CI9_GNT    26
18742 #define V_ARB2_CI9_GNT(x) ((x) << S_ARB2_CI9_GNT)
18743 #define F_ARB2_CI9_GNT    V_ARB2_CI9_GNT(1U)
18744 
18745 #define S_CI9_DM2_WDATA_VLD    25
18746 #define V_CI9_DM2_WDATA_VLD(x) ((x) << S_CI9_DM2_WDATA_VLD)
18747 #define F_CI9_DM2_WDATA_VLD    V_CI9_DM2_WDATA_VLD(1U)
18748 
18749 #define S_DM2_CI9_RDATA_VLD    24
18750 #define V_DM2_CI9_RDATA_VLD(x) ((x) << S_DM2_CI9_RDATA_VLD)
18751 #define F_DM2_CI9_RDATA_VLD    V_DM2_CI9_RDATA_VLD(1U)
18752 
18753 #define S_CI10_ARB2_REQ    23
18754 #define V_CI10_ARB2_REQ(x) ((x) << S_CI10_ARB2_REQ)
18755 #define F_CI10_ARB2_REQ    V_CI10_ARB2_REQ(1U)
18756 
18757 #define S_ARB2_CI10_GNT    22
18758 #define V_ARB2_CI10_GNT(x) ((x) << S_ARB2_CI10_GNT)
18759 #define F_ARB2_CI10_GNT    V_ARB2_CI10_GNT(1U)
18760 
18761 #define S_CI10_DM2_WDATA_VLD    21
18762 #define V_CI10_DM2_WDATA_VLD(x) ((x) << S_CI10_DM2_WDATA_VLD)
18763 #define F_CI10_DM2_WDATA_VLD    V_CI10_DM2_WDATA_VLD(1U)
18764 
18765 #define S_DM2_CI10_RDATA_VLD    20
18766 #define V_DM2_CI10_RDATA_VLD(x) ((x) << S_DM2_CI10_RDATA_VLD)
18767 #define F_DM2_CI10_RDATA_VLD    V_DM2_CI10_RDATA_VLD(1U)
18768 
18769 #define S_CI11_ARB2_REQ    19
18770 #define V_CI11_ARB2_REQ(x) ((x) << S_CI11_ARB2_REQ)
18771 #define F_CI11_ARB2_REQ    V_CI11_ARB2_REQ(1U)
18772 
18773 #define S_ARB2_CI11_GNT    18
18774 #define V_ARB2_CI11_GNT(x) ((x) << S_ARB2_CI11_GNT)
18775 #define F_ARB2_CI11_GNT    V_ARB2_CI11_GNT(1U)
18776 
18777 #define S_CI11_DM2_WDATA_VLD    17
18778 #define V_CI11_DM2_WDATA_VLD(x) ((x) << S_CI11_DM2_WDATA_VLD)
18779 #define F_CI11_DM2_WDATA_VLD    V_CI11_DM2_WDATA_VLD(1U)
18780 
18781 #define S_DM2_CI11_RDATA_VLD    16
18782 #define V_DM2_CI11_RDATA_VLD(x) ((x) << S_DM2_CI11_RDATA_VLD)
18783 #define F_DM2_CI11_RDATA_VLD    V_DM2_CI11_RDATA_VLD(1U)
18784 
18785 #define S_CI12_ARB2_REQ    15
18786 #define V_CI12_ARB2_REQ(x) ((x) << S_CI12_ARB2_REQ)
18787 #define F_CI12_ARB2_REQ    V_CI12_ARB2_REQ(1U)
18788 
18789 #define S_ARB2_CI12_GNT    14
18790 #define V_ARB2_CI12_GNT(x) ((x) << S_ARB2_CI12_GNT)
18791 #define F_ARB2_CI12_GNT    V_ARB2_CI12_GNT(1U)
18792 
18793 #define S_CI12_DM2_WDATA_VLD    13
18794 #define V_CI12_DM2_WDATA_VLD(x) ((x) << S_CI12_DM2_WDATA_VLD)
18795 #define F_CI12_DM2_WDATA_VLD    V_CI12_DM2_WDATA_VLD(1U)
18796 
18797 #define S_DM2_CI12_RDATA_VLD    12
18798 #define V_DM2_CI12_RDATA_VLD(x) ((x) << S_DM2_CI12_RDATA_VLD)
18799 #define F_DM2_CI12_RDATA_VLD    V_DM2_CI12_RDATA_VLD(1U)
18800 
18801 #define A_MA_TARGET_3_ARBITER_INTERFACE_EXTERNAL_REG1 0xa016
18802 
18803 #define S_CI8_ARB3_REQ    31
18804 #define V_CI8_ARB3_REQ(x) ((x) << S_CI8_ARB3_REQ)
18805 #define F_CI8_ARB3_REQ    V_CI8_ARB3_REQ(1U)
18806 
18807 #define S_ARB3_CI8_GNT    30
18808 #define V_ARB3_CI8_GNT(x) ((x) << S_ARB3_CI8_GNT)
18809 #define F_ARB3_CI8_GNT    V_ARB3_CI8_GNT(1U)
18810 
18811 #define S_CI8_DM3_WDATA_VLD    29
18812 #define V_CI8_DM3_WDATA_VLD(x) ((x) << S_CI8_DM3_WDATA_VLD)
18813 #define F_CI8_DM3_WDATA_VLD    V_CI8_DM3_WDATA_VLD(1U)
18814 
18815 #define S_DM3_CI8_RDATA_VLD    28
18816 #define V_DM3_CI8_RDATA_VLD(x) ((x) << S_DM3_CI8_RDATA_VLD)
18817 #define F_DM3_CI8_RDATA_VLD    V_DM3_CI8_RDATA_VLD(1U)
18818 
18819 #define S_CI9_ARB3_REQ    27
18820 #define V_CI9_ARB3_REQ(x) ((x) << S_CI9_ARB3_REQ)
18821 #define F_CI9_ARB3_REQ    V_CI9_ARB3_REQ(1U)
18822 
18823 #define S_ARB3_CI9_GNT    26
18824 #define V_ARB3_CI9_GNT(x) ((x) << S_ARB3_CI9_GNT)
18825 #define F_ARB3_CI9_GNT    V_ARB3_CI9_GNT(1U)
18826 
18827 #define S_CI9_DM3_WDATA_VLD    25
18828 #define V_CI9_DM3_WDATA_VLD(x) ((x) << S_CI9_DM3_WDATA_VLD)
18829 #define F_CI9_DM3_WDATA_VLD    V_CI9_DM3_WDATA_VLD(1U)
18830 
18831 #define S_DM3_CI9_RDATA_VLD    24
18832 #define V_DM3_CI9_RDATA_VLD(x) ((x) << S_DM3_CI9_RDATA_VLD)
18833 #define F_DM3_CI9_RDATA_VLD    V_DM3_CI9_RDATA_VLD(1U)
18834 
18835 #define S_CI10_ARB3_REQ    23
18836 #define V_CI10_ARB3_REQ(x) ((x) << S_CI10_ARB3_REQ)
18837 #define F_CI10_ARB3_REQ    V_CI10_ARB3_REQ(1U)
18838 
18839 #define S_ARB3_CI10_GNT    22
18840 #define V_ARB3_CI10_GNT(x) ((x) << S_ARB3_CI10_GNT)
18841 #define F_ARB3_CI10_GNT    V_ARB3_CI10_GNT(1U)
18842 
18843 #define S_CI10_DM3_WDATA_VLD    21
18844 #define V_CI10_DM3_WDATA_VLD(x) ((x) << S_CI10_DM3_WDATA_VLD)
18845 #define F_CI10_DM3_WDATA_VLD    V_CI10_DM3_WDATA_VLD(1U)
18846 
18847 #define S_DM3_CI10_RDATA_VLD    20
18848 #define V_DM3_CI10_RDATA_VLD(x) ((x) << S_DM3_CI10_RDATA_VLD)
18849 #define F_DM3_CI10_RDATA_VLD    V_DM3_CI10_RDATA_VLD(1U)
18850 
18851 #define S_CI11_ARB3_REQ    19
18852 #define V_CI11_ARB3_REQ(x) ((x) << S_CI11_ARB3_REQ)
18853 #define F_CI11_ARB3_REQ    V_CI11_ARB3_REQ(1U)
18854 
18855 #define S_ARB3_CI11_GNT    18
18856 #define V_ARB3_CI11_GNT(x) ((x) << S_ARB3_CI11_GNT)
18857 #define F_ARB3_CI11_GNT    V_ARB3_CI11_GNT(1U)
18858 
18859 #define S_CI11_DM3_WDATA_VLD    17
18860 #define V_CI11_DM3_WDATA_VLD(x) ((x) << S_CI11_DM3_WDATA_VLD)
18861 #define F_CI11_DM3_WDATA_VLD    V_CI11_DM3_WDATA_VLD(1U)
18862 
18863 #define S_DM3_CI11_RDATA_VLD    16
18864 #define V_DM3_CI11_RDATA_VLD(x) ((x) << S_DM3_CI11_RDATA_VLD)
18865 #define F_DM3_CI11_RDATA_VLD    V_DM3_CI11_RDATA_VLD(1U)
18866 
18867 #define S_CI12_ARB3_REQ    15
18868 #define V_CI12_ARB3_REQ(x) ((x) << S_CI12_ARB3_REQ)
18869 #define F_CI12_ARB3_REQ    V_CI12_ARB3_REQ(1U)
18870 
18871 #define S_ARB3_CI12_GNT    14
18872 #define V_ARB3_CI12_GNT(x) ((x) << S_ARB3_CI12_GNT)
18873 #define F_ARB3_CI12_GNT    V_ARB3_CI12_GNT(1U)
18874 
18875 #define S_CI12_DM3_WDATA_VLD    13
18876 #define V_CI12_DM3_WDATA_VLD(x) ((x) << S_CI12_DM3_WDATA_VLD)
18877 #define F_CI12_DM3_WDATA_VLD    V_CI12_DM3_WDATA_VLD(1U)
18878 
18879 #define S_DM3_CI12_RDATA_VLD    12
18880 #define V_DM3_CI12_RDATA_VLD(x) ((x) << S_DM3_CI12_RDATA_VLD)
18881 #define F_DM3_CI12_RDATA_VLD    V_DM3_CI12_RDATA_VLD(1U)
18882 
18883 #define A_MA_SGE_THREAD_0_CLIENT_INTERFACE_INTERNAL_REG0 0xa400
18884 
18885 #define S_CMD_IN_FIFO_CNT0    30
18886 #define M_CMD_IN_FIFO_CNT0    0x3U
18887 #define V_CMD_IN_FIFO_CNT0(x) ((x) << S_CMD_IN_FIFO_CNT0)
18888 #define G_CMD_IN_FIFO_CNT0(x) (((x) >> S_CMD_IN_FIFO_CNT0) & M_CMD_IN_FIFO_CNT0)
18889 
18890 #define S_CMD_SPLIT_FIFO_CNT0    28
18891 #define M_CMD_SPLIT_FIFO_CNT0    0x3U
18892 #define V_CMD_SPLIT_FIFO_CNT0(x) ((x) << S_CMD_SPLIT_FIFO_CNT0)
18893 #define G_CMD_SPLIT_FIFO_CNT0(x) (((x) >> S_CMD_SPLIT_FIFO_CNT0) & M_CMD_SPLIT_FIFO_CNT0)
18894 
18895 #define S_CMD_THROTTLE_FIFO_CNT0    22
18896 #define M_CMD_THROTTLE_FIFO_CNT0    0x3fU
18897 #define V_CMD_THROTTLE_FIFO_CNT0(x) ((x) << S_CMD_THROTTLE_FIFO_CNT0)
18898 #define G_CMD_THROTTLE_FIFO_CNT0(x) (((x) >> S_CMD_THROTTLE_FIFO_CNT0) & M_CMD_THROTTLE_FIFO_CNT0)
18899 
18900 #define S_RD_CHNL_FIFO_CNT0    15
18901 #define M_RD_CHNL_FIFO_CNT0    0x7fU
18902 #define V_RD_CHNL_FIFO_CNT0(x) ((x) << S_RD_CHNL_FIFO_CNT0)
18903 #define G_RD_CHNL_FIFO_CNT0(x) (((x) >> S_RD_CHNL_FIFO_CNT0) & M_RD_CHNL_FIFO_CNT0)
18904 
18905 #define S_RD_DATA_EXT_FIFO_CNT0    13
18906 #define M_RD_DATA_EXT_FIFO_CNT0    0x3U
18907 #define V_RD_DATA_EXT_FIFO_CNT0(x) ((x) << S_RD_DATA_EXT_FIFO_CNT0)
18908 #define G_RD_DATA_EXT_FIFO_CNT0(x) (((x) >> S_RD_DATA_EXT_FIFO_CNT0) & M_RD_DATA_EXT_FIFO_CNT0)
18909 
18910 #define S_RD_DATA_512B_FIFO_CNT0    5
18911 #define M_RD_DATA_512B_FIFO_CNT0    0xffU
18912 #define V_RD_DATA_512B_FIFO_CNT0(x) ((x) << S_RD_DATA_512B_FIFO_CNT0)
18913 #define G_RD_DATA_512B_FIFO_CNT0(x) (((x) >> S_RD_DATA_512B_FIFO_CNT0) & M_RD_DATA_512B_FIFO_CNT0)
18914 
18915 #define S_RD_REQ_TAG_FIFO_CNT0    1
18916 #define M_RD_REQ_TAG_FIFO_CNT0    0xfU
18917 #define V_RD_REQ_TAG_FIFO_CNT0(x) ((x) << S_RD_REQ_TAG_FIFO_CNT0)
18918 #define G_RD_REQ_TAG_FIFO_CNT0(x) (((x) >> S_RD_REQ_TAG_FIFO_CNT0) & M_RD_REQ_TAG_FIFO_CNT0)
18919 
18920 #define A_MA_SGE_THREAD_1_CLIENT_INTERFACE_INTERNAL_REG0 0xa401
18921 
18922 #define S_CMD_IN_FIFO_CNT1    30
18923 #define M_CMD_IN_FIFO_CNT1    0x3U
18924 #define V_CMD_IN_FIFO_CNT1(x) ((x) << S_CMD_IN_FIFO_CNT1)
18925 #define G_CMD_IN_FIFO_CNT1(x) (((x) >> S_CMD_IN_FIFO_CNT1) & M_CMD_IN_FIFO_CNT1)
18926 
18927 #define S_CMD_SPLIT_FIFO_CNT1    28
18928 #define M_CMD_SPLIT_FIFO_CNT1    0x3U
18929 #define V_CMD_SPLIT_FIFO_CNT1(x) ((x) << S_CMD_SPLIT_FIFO_CNT1)
18930 #define G_CMD_SPLIT_FIFO_CNT1(x) (((x) >> S_CMD_SPLIT_FIFO_CNT1) & M_CMD_SPLIT_FIFO_CNT1)
18931 
18932 #define S_CMD_THROTTLE_FIFO_CNT1    22
18933 #define M_CMD_THROTTLE_FIFO_CNT1    0x3fU
18934 #define V_CMD_THROTTLE_FIFO_CNT1(x) ((x) << S_CMD_THROTTLE_FIFO_CNT1)
18935 #define G_CMD_THROTTLE_FIFO_CNT1(x) (((x) >> S_CMD_THROTTLE_FIFO_CNT1) & M_CMD_THROTTLE_FIFO_CNT1)
18936 
18937 #define S_RD_CHNL_FIFO_CNT1    15
18938 #define M_RD_CHNL_FIFO_CNT1    0x7fU
18939 #define V_RD_CHNL_FIFO_CNT1(x) ((x) << S_RD_CHNL_FIFO_CNT1)
18940 #define G_RD_CHNL_FIFO_CNT1(x) (((x) >> S_RD_CHNL_FIFO_CNT1) & M_RD_CHNL_FIFO_CNT1)
18941 
18942 #define S_RD_DATA_EXT_FIFO_CNT1    13
18943 #define M_RD_DATA_EXT_FIFO_CNT1    0x3U
18944 #define V_RD_DATA_EXT_FIFO_CNT1(x) ((x) << S_RD_DATA_EXT_FIFO_CNT1)
18945 #define G_RD_DATA_EXT_FIFO_CNT1(x) (((x) >> S_RD_DATA_EXT_FIFO_CNT1) & M_RD_DATA_EXT_FIFO_CNT1)
18946 
18947 #define S_RD_DATA_512B_FIFO_CNT1    5
18948 #define M_RD_DATA_512B_FIFO_CNT1    0xffU
18949 #define V_RD_DATA_512B_FIFO_CNT1(x) ((x) << S_RD_DATA_512B_FIFO_CNT1)
18950 #define G_RD_DATA_512B_FIFO_CNT1(x) (((x) >> S_RD_DATA_512B_FIFO_CNT1) & M_RD_DATA_512B_FIFO_CNT1)
18951 
18952 #define S_RD_REQ_TAG_FIFO_CNT1    1
18953 #define M_RD_REQ_TAG_FIFO_CNT1    0xfU
18954 #define V_RD_REQ_TAG_FIFO_CNT1(x) ((x) << S_RD_REQ_TAG_FIFO_CNT1)
18955 #define G_RD_REQ_TAG_FIFO_CNT1(x) (((x) >> S_RD_REQ_TAG_FIFO_CNT1) & M_RD_REQ_TAG_FIFO_CNT1)
18956 
18957 #define A_MA_ULP_TX_CLIENT_INTERFACE_INTERNAL_REG0 0xa402
18958 
18959 #define S_CMD_IN_FIFO_CNT2    30
18960 #define M_CMD_IN_FIFO_CNT2    0x3U
18961 #define V_CMD_IN_FIFO_CNT2(x) ((x) << S_CMD_IN_FIFO_CNT2)
18962 #define G_CMD_IN_FIFO_CNT2(x) (((x) >> S_CMD_IN_FIFO_CNT2) & M_CMD_IN_FIFO_CNT2)
18963 
18964 #define S_CMD_SPLIT_FIFO_CNT2    28
18965 #define M_CMD_SPLIT_FIFO_CNT2    0x3U
18966 #define V_CMD_SPLIT_FIFO_CNT2(x) ((x) << S_CMD_SPLIT_FIFO_CNT2)
18967 #define G_CMD_SPLIT_FIFO_CNT2(x) (((x) >> S_CMD_SPLIT_FIFO_CNT2) & M_CMD_SPLIT_FIFO_CNT2)
18968 
18969 #define S_CMD_THROTTLE_FIFO_CNT2    22
18970 #define M_CMD_THROTTLE_FIFO_CNT2    0x3fU
18971 #define V_CMD_THROTTLE_FIFO_CNT2(x) ((x) << S_CMD_THROTTLE_FIFO_CNT2)
18972 #define G_CMD_THROTTLE_FIFO_CNT2(x) (((x) >> S_CMD_THROTTLE_FIFO_CNT2) & M_CMD_THROTTLE_FIFO_CNT2)
18973 
18974 #define S_RD_CHNL_FIFO_CNT2    15
18975 #define M_RD_CHNL_FIFO_CNT2    0x7fU
18976 #define V_RD_CHNL_FIFO_CNT2(x) ((x) << S_RD_CHNL_FIFO_CNT2)
18977 #define G_RD_CHNL_FIFO_CNT2(x) (((x) >> S_RD_CHNL_FIFO_CNT2) & M_RD_CHNL_FIFO_CNT2)
18978 
18979 #define S_RD_DATA_EXT_FIFO_CNT2    13
18980 #define M_RD_DATA_EXT_FIFO_CNT2    0x3U
18981 #define V_RD_DATA_EXT_FIFO_CNT2(x) ((x) << S_RD_DATA_EXT_FIFO_CNT2)
18982 #define G_RD_DATA_EXT_FIFO_CNT2(x) (((x) >> S_RD_DATA_EXT_FIFO_CNT2) & M_RD_DATA_EXT_FIFO_CNT2)
18983 
18984 #define S_RD_DATA_512B_FIFO_CNT2    5
18985 #define M_RD_DATA_512B_FIFO_CNT2    0xffU
18986 #define V_RD_DATA_512B_FIFO_CNT2(x) ((x) << S_RD_DATA_512B_FIFO_CNT2)
18987 #define G_RD_DATA_512B_FIFO_CNT2(x) (((x) >> S_RD_DATA_512B_FIFO_CNT2) & M_RD_DATA_512B_FIFO_CNT2)
18988 
18989 #define S_RD_REQ_TAG_FIFO_CNT2    1
18990 #define M_RD_REQ_TAG_FIFO_CNT2    0xfU
18991 #define V_RD_REQ_TAG_FIFO_CNT2(x) ((x) << S_RD_REQ_TAG_FIFO_CNT2)
18992 #define G_RD_REQ_TAG_FIFO_CNT2(x) (((x) >> S_RD_REQ_TAG_FIFO_CNT2) & M_RD_REQ_TAG_FIFO_CNT2)
18993 
18994 #define A_MA_ULP_RX_CLIENT_INTERFACE_INTERNAL_REG0 0xa403
18995 
18996 #define S_CMD_IN_FIFO_CNT3    30
18997 #define M_CMD_IN_FIFO_CNT3    0x3U
18998 #define V_CMD_IN_FIFO_CNT3(x) ((x) << S_CMD_IN_FIFO_CNT3)
18999 #define G_CMD_IN_FIFO_CNT3(x) (((x) >> S_CMD_IN_FIFO_CNT3) & M_CMD_IN_FIFO_CNT3)
19000 
19001 #define S_CMD_SPLIT_FIFO_CNT3    28
19002 #define M_CMD_SPLIT_FIFO_CNT3    0x3U
19003 #define V_CMD_SPLIT_FIFO_CNT3(x) ((x) << S_CMD_SPLIT_FIFO_CNT3)
19004 #define G_CMD_SPLIT_FIFO_CNT3(x) (((x) >> S_CMD_SPLIT_FIFO_CNT3) & M_CMD_SPLIT_FIFO_CNT3)
19005 
19006 #define S_CMD_THROTTLE_FIFO_CNT3    22
19007 #define M_CMD_THROTTLE_FIFO_CNT3    0x3fU
19008 #define V_CMD_THROTTLE_FIFO_CNT3(x) ((x) << S_CMD_THROTTLE_FIFO_CNT3)
19009 #define G_CMD_THROTTLE_FIFO_CNT3(x) (((x) >> S_CMD_THROTTLE_FIFO_CNT3) & M_CMD_THROTTLE_FIFO_CNT3)
19010 
19011 #define S_RD_CHNL_FIFO_CNT3    15
19012 #define M_RD_CHNL_FIFO_CNT3    0x7fU
19013 #define V_RD_CHNL_FIFO_CNT3(x) ((x) << S_RD_CHNL_FIFO_CNT3)
19014 #define G_RD_CHNL_FIFO_CNT3(x) (((x) >> S_RD_CHNL_FIFO_CNT3) & M_RD_CHNL_FIFO_CNT3)
19015 
19016 #define S_RD_DATA_EXT_FIFO_CNT3    13
19017 #define M_RD_DATA_EXT_FIFO_CNT3    0x3U
19018 #define V_RD_DATA_EXT_FIFO_CNT3(x) ((x) << S_RD_DATA_EXT_FIFO_CNT3)
19019 #define G_RD_DATA_EXT_FIFO_CNT3(x) (((x) >> S_RD_DATA_EXT_FIFO_CNT3) & M_RD_DATA_EXT_FIFO_CNT3)
19020 
19021 #define S_RD_DATA_512B_FIFO_CNT3    5
19022 #define M_RD_DATA_512B_FIFO_CNT3    0xffU
19023 #define V_RD_DATA_512B_FIFO_CNT3(x) ((x) << S_RD_DATA_512B_FIFO_CNT3)
19024 #define G_RD_DATA_512B_FIFO_CNT3(x) (((x) >> S_RD_DATA_512B_FIFO_CNT3) & M_RD_DATA_512B_FIFO_CNT3)
19025 
19026 #define S_RD_REQ_TAG_FIFO_CNT3    1
19027 #define M_RD_REQ_TAG_FIFO_CNT3    0xfU
19028 #define V_RD_REQ_TAG_FIFO_CNT3(x) ((x) << S_RD_REQ_TAG_FIFO_CNT3)
19029 #define G_RD_REQ_TAG_FIFO_CNT3(x) (((x) >> S_RD_REQ_TAG_FIFO_CNT3) & M_RD_REQ_TAG_FIFO_CNT3)
19030 
19031 #define A_MA_ULP_TX_RX_CLIENT_INTERFACE_INTERNAL_REG0 0xa404
19032 
19033 #define S_CMD_IN_FIFO_CNT4    30
19034 #define M_CMD_IN_FIFO_CNT4    0x3U
19035 #define V_CMD_IN_FIFO_CNT4(x) ((x) << S_CMD_IN_FIFO_CNT4)
19036 #define G_CMD_IN_FIFO_CNT4(x) (((x) >> S_CMD_IN_FIFO_CNT4) & M_CMD_IN_FIFO_CNT4)
19037 
19038 #define S_CMD_SPLIT_FIFO_CNT4    28
19039 #define M_CMD_SPLIT_FIFO_CNT4    0x3U
19040 #define V_CMD_SPLIT_FIFO_CNT4(x) ((x) << S_CMD_SPLIT_FIFO_CNT4)
19041 #define G_CMD_SPLIT_FIFO_CNT4(x) (((x) >> S_CMD_SPLIT_FIFO_CNT4) & M_CMD_SPLIT_FIFO_CNT4)
19042 
19043 #define S_CMD_THROTTLE_FIFO_CNT4    22
19044 #define M_CMD_THROTTLE_FIFO_CNT4    0x3fU
19045 #define V_CMD_THROTTLE_FIFO_CNT4(x) ((x) << S_CMD_THROTTLE_FIFO_CNT4)
19046 #define G_CMD_THROTTLE_FIFO_CNT4(x) (((x) >> S_CMD_THROTTLE_FIFO_CNT4) & M_CMD_THROTTLE_FIFO_CNT4)
19047 
19048 #define S_RD_CHNL_FIFO_CNT4    15
19049 #define M_RD_CHNL_FIFO_CNT4    0x7fU
19050 #define V_RD_CHNL_FIFO_CNT4(x) ((x) << S_RD_CHNL_FIFO_CNT4)
19051 #define G_RD_CHNL_FIFO_CNT4(x) (((x) >> S_RD_CHNL_FIFO_CNT4) & M_RD_CHNL_FIFO_CNT4)
19052 
19053 #define S_RD_DATA_EXT_FIFO_CNT4    13
19054 #define M_RD_DATA_EXT_FIFO_CNT4    0x3U
19055 #define V_RD_DATA_EXT_FIFO_CNT4(x) ((x) << S_RD_DATA_EXT_FIFO_CNT4)
19056 #define G_RD_DATA_EXT_FIFO_CNT4(x) (((x) >> S_RD_DATA_EXT_FIFO_CNT4) & M_RD_DATA_EXT_FIFO_CNT4)
19057 
19058 #define S_RD_DATA_512B_FIFO_CNT4    5
19059 #define M_RD_DATA_512B_FIFO_CNT4    0xffU
19060 #define V_RD_DATA_512B_FIFO_CNT4(x) ((x) << S_RD_DATA_512B_FIFO_CNT4)
19061 #define G_RD_DATA_512B_FIFO_CNT4(x) (((x) >> S_RD_DATA_512B_FIFO_CNT4) & M_RD_DATA_512B_FIFO_CNT4)
19062 
19063 #define S_RD_REQ_TAG_FIFO_CNT4    1
19064 #define M_RD_REQ_TAG_FIFO_CNT4    0xfU
19065 #define V_RD_REQ_TAG_FIFO_CNT4(x) ((x) << S_RD_REQ_TAG_FIFO_CNT4)
19066 #define G_RD_REQ_TAG_FIFO_CNT4(x) (((x) >> S_RD_REQ_TAG_FIFO_CNT4) & M_RD_REQ_TAG_FIFO_CNT4)
19067 
19068 #define A_MA_TP_THREAD_0_CLIENT_INTERFACE_INTERNAL_REG0 0xa405
19069 
19070 #define S_CMD_IN_FIFO_CNT5    30
19071 #define M_CMD_IN_FIFO_CNT5    0x3U
19072 #define V_CMD_IN_FIFO_CNT5(x) ((x) << S_CMD_IN_FIFO_CNT5)
19073 #define G_CMD_IN_FIFO_CNT5(x) (((x) >> S_CMD_IN_FIFO_CNT5) & M_CMD_IN_FIFO_CNT5)
19074 
19075 #define S_CMD_SPLIT_FIFO_CNT5    28
19076 #define M_CMD_SPLIT_FIFO_CNT5    0x3U
19077 #define V_CMD_SPLIT_FIFO_CNT5(x) ((x) << S_CMD_SPLIT_FIFO_CNT5)
19078 #define G_CMD_SPLIT_FIFO_CNT5(x) (((x) >> S_CMD_SPLIT_FIFO_CNT5) & M_CMD_SPLIT_FIFO_CNT5)
19079 
19080 #define S_CMD_THROTTLE_FIFO_CNT5    22
19081 #define M_CMD_THROTTLE_FIFO_CNT5    0x3fU
19082 #define V_CMD_THROTTLE_FIFO_CNT5(x) ((x) << S_CMD_THROTTLE_FIFO_CNT5)
19083 #define G_CMD_THROTTLE_FIFO_CNT5(x) (((x) >> S_CMD_THROTTLE_FIFO_CNT5) & M_CMD_THROTTLE_FIFO_CNT5)
19084 
19085 #define S_RD_CHNL_FIFO_CNT5    15
19086 #define M_RD_CHNL_FIFO_CNT5    0x7fU
19087 #define V_RD_CHNL_FIFO_CNT5(x) ((x) << S_RD_CHNL_FIFO_CNT5)
19088 #define G_RD_CHNL_FIFO_CNT5(x) (((x) >> S_RD_CHNL_FIFO_CNT5) & M_RD_CHNL_FIFO_CNT5)
19089 
19090 #define S_RD_DATA_EXT_FIFO_CNT5    13
19091 #define M_RD_DATA_EXT_FIFO_CNT5    0x3U
19092 #define V_RD_DATA_EXT_FIFO_CNT5(x) ((x) << S_RD_DATA_EXT_FIFO_CNT5)
19093 #define G_RD_DATA_EXT_FIFO_CNT5(x) (((x) >> S_RD_DATA_EXT_FIFO_CNT5) & M_RD_DATA_EXT_FIFO_CNT5)
19094 
19095 #define S_RD_DATA_512B_FIFO_CNT5    5
19096 #define M_RD_DATA_512B_FIFO_CNT5    0xffU
19097 #define V_RD_DATA_512B_FIFO_CNT5(x) ((x) << S_RD_DATA_512B_FIFO_CNT5)
19098 #define G_RD_DATA_512B_FIFO_CNT5(x) (((x) >> S_RD_DATA_512B_FIFO_CNT5) & M_RD_DATA_512B_FIFO_CNT5)
19099 
19100 #define S_RD_REQ_TAG_FIFO_CNT5    1
19101 #define M_RD_REQ_TAG_FIFO_CNT5    0xfU
19102 #define V_RD_REQ_TAG_FIFO_CNT5(x) ((x) << S_RD_REQ_TAG_FIFO_CNT5)
19103 #define G_RD_REQ_TAG_FIFO_CNT5(x) (((x) >> S_RD_REQ_TAG_FIFO_CNT5) & M_RD_REQ_TAG_FIFO_CNT5)
19104 
19105 #define A_MA_TP_THREAD_1_CLIENT_INTERFACE_INTERNAL_REG0 0xa406
19106 
19107 #define S_CMD_IN_FIFO_CNT6    30
19108 #define M_CMD_IN_FIFO_CNT6    0x3U
19109 #define V_CMD_IN_FIFO_CNT6(x) ((x) << S_CMD_IN_FIFO_CNT6)
19110 #define G_CMD_IN_FIFO_CNT6(x) (((x) >> S_CMD_IN_FIFO_CNT6) & M_CMD_IN_FIFO_CNT6)
19111 
19112 #define S_CMD_SPLIT_FIFO_CNT6    28
19113 #define M_CMD_SPLIT_FIFO_CNT6    0x3U
19114 #define V_CMD_SPLIT_FIFO_CNT6(x) ((x) << S_CMD_SPLIT_FIFO_CNT6)
19115 #define G_CMD_SPLIT_FIFO_CNT6(x) (((x) >> S_CMD_SPLIT_FIFO_CNT6) & M_CMD_SPLIT_FIFO_CNT6)
19116 
19117 #define S_CMD_THROTTLE_FIFO_CNT6    22
19118 #define M_CMD_THROTTLE_FIFO_CNT6    0x3fU
19119 #define V_CMD_THROTTLE_FIFO_CNT6(x) ((x) << S_CMD_THROTTLE_FIFO_CNT6)
19120 #define G_CMD_THROTTLE_FIFO_CNT6(x) (((x) >> S_CMD_THROTTLE_FIFO_CNT6) & M_CMD_THROTTLE_FIFO_CNT6)
19121 
19122 #define S_RD_CHNL_FIFO_CNT6    15
19123 #define M_RD_CHNL_FIFO_CNT6    0x7fU
19124 #define V_RD_CHNL_FIFO_CNT6(x) ((x) << S_RD_CHNL_FIFO_CNT6)
19125 #define G_RD_CHNL_FIFO_CNT6(x) (((x) >> S_RD_CHNL_FIFO_CNT6) & M_RD_CHNL_FIFO_CNT6)
19126 
19127 #define S_RD_DATA_EXT_FIFO_CNT6    13
19128 #define M_RD_DATA_EXT_FIFO_CNT6    0x3U
19129 #define V_RD_DATA_EXT_FIFO_CNT6(x) ((x) << S_RD_DATA_EXT_FIFO_CNT6)
19130 #define G_RD_DATA_EXT_FIFO_CNT6(x) (((x) >> S_RD_DATA_EXT_FIFO_CNT6) & M_RD_DATA_EXT_FIFO_CNT6)
19131 
19132 #define S_RD_DATA_512B_FIFO_CNT6    5
19133 #define M_RD_DATA_512B_FIFO_CNT6    0xffU
19134 #define V_RD_DATA_512B_FIFO_CNT6(x) ((x) << S_RD_DATA_512B_FIFO_CNT6)
19135 #define G_RD_DATA_512B_FIFO_CNT6(x) (((x) >> S_RD_DATA_512B_FIFO_CNT6) & M_RD_DATA_512B_FIFO_CNT6)
19136 
19137 #define S_RD_REQ_TAG_FIFO_CNT6    1
19138 #define M_RD_REQ_TAG_FIFO_CNT6    0xfU
19139 #define V_RD_REQ_TAG_FIFO_CNT6(x) ((x) << S_RD_REQ_TAG_FIFO_CNT6)
19140 #define G_RD_REQ_TAG_FIFO_CNT6(x) (((x) >> S_RD_REQ_TAG_FIFO_CNT6) & M_RD_REQ_TAG_FIFO_CNT6)
19141 
19142 #define A_MA_LE_CLIENT_INTERFACE_INTERNAL_REG0 0xa407
19143 
19144 #define S_CMD_IN_FIFO_CNT7    30
19145 #define M_CMD_IN_FIFO_CNT7    0x3U
19146 #define V_CMD_IN_FIFO_CNT7(x) ((x) << S_CMD_IN_FIFO_CNT7)
19147 #define G_CMD_IN_FIFO_CNT7(x) (((x) >> S_CMD_IN_FIFO_CNT7) & M_CMD_IN_FIFO_CNT7)
19148 
19149 #define S_CMD_SPLIT_FIFO_CNT7    28
19150 #define M_CMD_SPLIT_FIFO_CNT7    0x3U
19151 #define V_CMD_SPLIT_FIFO_CNT7(x) ((x) << S_CMD_SPLIT_FIFO_CNT7)
19152 #define G_CMD_SPLIT_FIFO_CNT7(x) (((x) >> S_CMD_SPLIT_FIFO_CNT7) & M_CMD_SPLIT_FIFO_CNT7)
19153 
19154 #define S_CMD_THROTTLE_FIFO_CNT7    22
19155 #define M_CMD_THROTTLE_FIFO_CNT7    0x3fU
19156 #define V_CMD_THROTTLE_FIFO_CNT7(x) ((x) << S_CMD_THROTTLE_FIFO_CNT7)
19157 #define G_CMD_THROTTLE_FIFO_CNT7(x) (((x) >> S_CMD_THROTTLE_FIFO_CNT7) & M_CMD_THROTTLE_FIFO_CNT7)
19158 
19159 #define S_RD_CHNL_FIFO_CNT7    15
19160 #define M_RD_CHNL_FIFO_CNT7    0x7fU
19161 #define V_RD_CHNL_FIFO_CNT7(x) ((x) << S_RD_CHNL_FIFO_CNT7)
19162 #define G_RD_CHNL_FIFO_CNT7(x) (((x) >> S_RD_CHNL_FIFO_CNT7) & M_RD_CHNL_FIFO_CNT7)
19163 
19164 #define S_RD_DATA_EXT_FIFO_CNT7    13
19165 #define M_RD_DATA_EXT_FIFO_CNT7    0x3U
19166 #define V_RD_DATA_EXT_FIFO_CNT7(x) ((x) << S_RD_DATA_EXT_FIFO_CNT7)
19167 #define G_RD_DATA_EXT_FIFO_CNT7(x) (((x) >> S_RD_DATA_EXT_FIFO_CNT7) & M_RD_DATA_EXT_FIFO_CNT7)
19168 
19169 #define S_RD_DATA_512B_FIFO_CNT7    5
19170 #define M_RD_DATA_512B_FIFO_CNT7    0xffU
19171 #define V_RD_DATA_512B_FIFO_CNT7(x) ((x) << S_RD_DATA_512B_FIFO_CNT7)
19172 #define G_RD_DATA_512B_FIFO_CNT7(x) (((x) >> S_RD_DATA_512B_FIFO_CNT7) & M_RD_DATA_512B_FIFO_CNT7)
19173 
19174 #define S_RD_REQ_TAG_FIFO_CNT7    1
19175 #define M_RD_REQ_TAG_FIFO_CNT7    0xfU
19176 #define V_RD_REQ_TAG_FIFO_CNT7(x) ((x) << S_RD_REQ_TAG_FIFO_CNT7)
19177 #define G_RD_REQ_TAG_FIFO_CNT7(x) (((x) >> S_RD_REQ_TAG_FIFO_CNT7) & M_RD_REQ_TAG_FIFO_CNT7)
19178 
19179 #define A_MA_CIM_CLIENT_INTERFACE_INTERNAL_REG0 0xa408
19180 
19181 #define S_CMD_IN_FIFO_CNT8    30
19182 #define M_CMD_IN_FIFO_CNT8    0x3U
19183 #define V_CMD_IN_FIFO_CNT8(x) ((x) << S_CMD_IN_FIFO_CNT8)
19184 #define G_CMD_IN_FIFO_CNT8(x) (((x) >> S_CMD_IN_FIFO_CNT8) & M_CMD_IN_FIFO_CNT8)
19185 
19186 #define S_CMD_SPLIT_FIFO_CNT8    28
19187 #define M_CMD_SPLIT_FIFO_CNT8    0x3U
19188 #define V_CMD_SPLIT_FIFO_CNT8(x) ((x) << S_CMD_SPLIT_FIFO_CNT8)
19189 #define G_CMD_SPLIT_FIFO_CNT8(x) (((x) >> S_CMD_SPLIT_FIFO_CNT8) & M_CMD_SPLIT_FIFO_CNT8)
19190 
19191 #define S_CMD_THROTTLE_FIFO_CNT8    22
19192 #define M_CMD_THROTTLE_FIFO_CNT8    0x3fU
19193 #define V_CMD_THROTTLE_FIFO_CNT8(x) ((x) << S_CMD_THROTTLE_FIFO_CNT8)
19194 #define G_CMD_THROTTLE_FIFO_CNT8(x) (((x) >> S_CMD_THROTTLE_FIFO_CNT8) & M_CMD_THROTTLE_FIFO_CNT8)
19195 
19196 #define S_RD_CHNL_FIFO_CNT8    15
19197 #define M_RD_CHNL_FIFO_CNT8    0x7fU
19198 #define V_RD_CHNL_FIFO_CNT8(x) ((x) << S_RD_CHNL_FIFO_CNT8)
19199 #define G_RD_CHNL_FIFO_CNT8(x) (((x) >> S_RD_CHNL_FIFO_CNT8) & M_RD_CHNL_FIFO_CNT8)
19200 
19201 #define S_RD_DATA_EXT_FIFO_CNT8    13
19202 #define M_RD_DATA_EXT_FIFO_CNT8    0x3U
19203 #define V_RD_DATA_EXT_FIFO_CNT8(x) ((x) << S_RD_DATA_EXT_FIFO_CNT8)
19204 #define G_RD_DATA_EXT_FIFO_CNT8(x) (((x) >> S_RD_DATA_EXT_FIFO_CNT8) & M_RD_DATA_EXT_FIFO_CNT8)
19205 
19206 #define S_RD_DATA_512B_FIFO_CNT8    5
19207 #define M_RD_DATA_512B_FIFO_CNT8    0xffU
19208 #define V_RD_DATA_512B_FIFO_CNT8(x) ((x) << S_RD_DATA_512B_FIFO_CNT8)
19209 #define G_RD_DATA_512B_FIFO_CNT8(x) (((x) >> S_RD_DATA_512B_FIFO_CNT8) & M_RD_DATA_512B_FIFO_CNT8)
19210 
19211 #define S_RD_REQ_TAG_FIFO_CNT8    1
19212 #define M_RD_REQ_TAG_FIFO_CNT8    0xfU
19213 #define V_RD_REQ_TAG_FIFO_CNT8(x) ((x) << S_RD_REQ_TAG_FIFO_CNT8)
19214 #define G_RD_REQ_TAG_FIFO_CNT8(x) (((x) >> S_RD_REQ_TAG_FIFO_CNT8) & M_RD_REQ_TAG_FIFO_CNT8)
19215 
19216 #define A_MA_PCIE_CLIENT_INTERFACE_INTERNAL_REG0 0xa409
19217 
19218 #define S_CMD_IN_FIFO_CNT9    30
19219 #define M_CMD_IN_FIFO_CNT9    0x3U
19220 #define V_CMD_IN_FIFO_CNT9(x) ((x) << S_CMD_IN_FIFO_CNT9)
19221 #define G_CMD_IN_FIFO_CNT9(x) (((x) >> S_CMD_IN_FIFO_CNT9) & M_CMD_IN_FIFO_CNT9)
19222 
19223 #define S_CMD_SPLIT_FIFO_CNT9    28
19224 #define M_CMD_SPLIT_FIFO_CNT9    0x3U
19225 #define V_CMD_SPLIT_FIFO_CNT9(x) ((x) << S_CMD_SPLIT_FIFO_CNT9)
19226 #define G_CMD_SPLIT_FIFO_CNT9(x) (((x) >> S_CMD_SPLIT_FIFO_CNT9) & M_CMD_SPLIT_FIFO_CNT9)
19227 
19228 #define S_CMD_THROTTLE_FIFO_CNT9    22
19229 #define M_CMD_THROTTLE_FIFO_CNT9    0x3fU
19230 #define V_CMD_THROTTLE_FIFO_CNT9(x) ((x) << S_CMD_THROTTLE_FIFO_CNT9)
19231 #define G_CMD_THROTTLE_FIFO_CNT9(x) (((x) >> S_CMD_THROTTLE_FIFO_CNT9) & M_CMD_THROTTLE_FIFO_CNT9)
19232 
19233 #define S_RD_CHNL_FIFO_CNT9    15
19234 #define M_RD_CHNL_FIFO_CNT9    0x7fU
19235 #define V_RD_CHNL_FIFO_CNT9(x) ((x) << S_RD_CHNL_FIFO_CNT9)
19236 #define G_RD_CHNL_FIFO_CNT9(x) (((x) >> S_RD_CHNL_FIFO_CNT9) & M_RD_CHNL_FIFO_CNT9)
19237 
19238 #define S_RD_DATA_EXT_FIFO_CNT9    13
19239 #define M_RD_DATA_EXT_FIFO_CNT9    0x3U
19240 #define V_RD_DATA_EXT_FIFO_CNT9(x) ((x) << S_RD_DATA_EXT_FIFO_CNT9)
19241 #define G_RD_DATA_EXT_FIFO_CNT9(x) (((x) >> S_RD_DATA_EXT_FIFO_CNT9) & M_RD_DATA_EXT_FIFO_CNT9)
19242 
19243 #define S_RD_DATA_512B_FIFO_CNT9    5
19244 #define M_RD_DATA_512B_FIFO_CNT9    0xffU
19245 #define V_RD_DATA_512B_FIFO_CNT9(x) ((x) << S_RD_DATA_512B_FIFO_CNT9)
19246 #define G_RD_DATA_512B_FIFO_CNT9(x) (((x) >> S_RD_DATA_512B_FIFO_CNT9) & M_RD_DATA_512B_FIFO_CNT9)
19247 
19248 #define S_RD_REQ_TAG_FIFO_CNT9    1
19249 #define M_RD_REQ_TAG_FIFO_CNT9    0xfU
19250 #define V_RD_REQ_TAG_FIFO_CNT9(x) ((x) << S_RD_REQ_TAG_FIFO_CNT9)
19251 #define G_RD_REQ_TAG_FIFO_CNT9(x) (((x) >> S_RD_REQ_TAG_FIFO_CNT9) & M_RD_REQ_TAG_FIFO_CNT9)
19252 
19253 #define A_MA_PM_TX_CLIENT_INTERFACE_INTERNAL_REG0 0xa40a
19254 
19255 #define S_CMD_IN_FIFO_CNT10    30
19256 #define M_CMD_IN_FIFO_CNT10    0x3U
19257 #define V_CMD_IN_FIFO_CNT10(x) ((x) << S_CMD_IN_FIFO_CNT10)
19258 #define G_CMD_IN_FIFO_CNT10(x) (((x) >> S_CMD_IN_FIFO_CNT10) & M_CMD_IN_FIFO_CNT10)
19259 
19260 #define S_CMD_SPLIT_FIFO_CNT10    28
19261 #define M_CMD_SPLIT_FIFO_CNT10    0x3U
19262 #define V_CMD_SPLIT_FIFO_CNT10(x) ((x) << S_CMD_SPLIT_FIFO_CNT10)
19263 #define G_CMD_SPLIT_FIFO_CNT10(x) (((x) >> S_CMD_SPLIT_FIFO_CNT10) & M_CMD_SPLIT_FIFO_CNT10)
19264 
19265 #define S_CMD_THROTTLE_FIFO_CNT10    22
19266 #define M_CMD_THROTTLE_FIFO_CNT10    0x3fU
19267 #define V_CMD_THROTTLE_FIFO_CNT10(x) ((x) << S_CMD_THROTTLE_FIFO_CNT10)
19268 #define G_CMD_THROTTLE_FIFO_CNT10(x) (((x) >> S_CMD_THROTTLE_FIFO_CNT10) & M_CMD_THROTTLE_FIFO_CNT10)
19269 
19270 #define S_RD_CHNL_FIFO_CNT10    15
19271 #define M_RD_CHNL_FIFO_CNT10    0x7fU
19272 #define V_RD_CHNL_FIFO_CNT10(x) ((x) << S_RD_CHNL_FIFO_CNT10)
19273 #define G_RD_CHNL_FIFO_CNT10(x) (((x) >> S_RD_CHNL_FIFO_CNT10) & M_RD_CHNL_FIFO_CNT10)
19274 
19275 #define S_RD_DATA_EXT_FIFO_CNT10    13
19276 #define M_RD_DATA_EXT_FIFO_CNT10    0x3U
19277 #define V_RD_DATA_EXT_FIFO_CNT10(x) ((x) << S_RD_DATA_EXT_FIFO_CNT10)
19278 #define G_RD_DATA_EXT_FIFO_CNT10(x) (((x) >> S_RD_DATA_EXT_FIFO_CNT10) & M_RD_DATA_EXT_FIFO_CNT10)
19279 
19280 #define S_RD_DATA_512B_FIFO_CNT10    5
19281 #define M_RD_DATA_512B_FIFO_CNT10    0xffU
19282 #define V_RD_DATA_512B_FIFO_CNT10(x) ((x) << S_RD_DATA_512B_FIFO_CNT10)
19283 #define G_RD_DATA_512B_FIFO_CNT10(x) (((x) >> S_RD_DATA_512B_FIFO_CNT10) & M_RD_DATA_512B_FIFO_CNT10)
19284 
19285 #define S_RD_REQ_TAG_FIFO_CNT10    1
19286 #define M_RD_REQ_TAG_FIFO_CNT10    0xfU
19287 #define V_RD_REQ_TAG_FIFO_CNT10(x) ((x) << S_RD_REQ_TAG_FIFO_CNT10)
19288 #define G_RD_REQ_TAG_FIFO_CNT10(x) (((x) >> S_RD_REQ_TAG_FIFO_CNT10) & M_RD_REQ_TAG_FIFO_CNT10)
19289 
19290 #define A_MA_PM_RX_CLIENT_INTERFACE_INTERNAL_REG0 0xa40b
19291 
19292 #define S_CMD_IN_FIFO_CNT11    30
19293 #define M_CMD_IN_FIFO_CNT11    0x3U
19294 #define V_CMD_IN_FIFO_CNT11(x) ((x) << S_CMD_IN_FIFO_CNT11)
19295 #define G_CMD_IN_FIFO_CNT11(x) (((x) >> S_CMD_IN_FIFO_CNT11) & M_CMD_IN_FIFO_CNT11)
19296 
19297 #define S_CMD_SPLIT_FIFO_CNT11    28
19298 #define M_CMD_SPLIT_FIFO_CNT11    0x3U
19299 #define V_CMD_SPLIT_FIFO_CNT11(x) ((x) << S_CMD_SPLIT_FIFO_CNT11)
19300 #define G_CMD_SPLIT_FIFO_CNT11(x) (((x) >> S_CMD_SPLIT_FIFO_CNT11) & M_CMD_SPLIT_FIFO_CNT11)
19301 
19302 #define S_CMD_THROTTLE_FIFO_CNT11    22
19303 #define M_CMD_THROTTLE_FIFO_CNT11    0x3fU
19304 #define V_CMD_THROTTLE_FIFO_CNT11(x) ((x) << S_CMD_THROTTLE_FIFO_CNT11)
19305 #define G_CMD_THROTTLE_FIFO_CNT11(x) (((x) >> S_CMD_THROTTLE_FIFO_CNT11) & M_CMD_THROTTLE_FIFO_CNT11)
19306 
19307 #define S_RD_CHNL_FIFO_CNT11    15
19308 #define M_RD_CHNL_FIFO_CNT11    0x7fU
19309 #define V_RD_CHNL_FIFO_CNT11(x) ((x) << S_RD_CHNL_FIFO_CNT11)
19310 #define G_RD_CHNL_FIFO_CNT11(x) (((x) >> S_RD_CHNL_FIFO_CNT11) & M_RD_CHNL_FIFO_CNT11)
19311 
19312 #define S_RD_DATA_EXT_FIFO_CNT11    13
19313 #define M_RD_DATA_EXT_FIFO_CNT11    0x3U
19314 #define V_RD_DATA_EXT_FIFO_CNT11(x) ((x) << S_RD_DATA_EXT_FIFO_CNT11)
19315 #define G_RD_DATA_EXT_FIFO_CNT11(x) (((x) >> S_RD_DATA_EXT_FIFO_CNT11) & M_RD_DATA_EXT_FIFO_CNT11)
19316 
19317 #define S_RD_DATA_512B_FIFO_CNT11    5
19318 #define M_RD_DATA_512B_FIFO_CNT11    0xffU
19319 #define V_RD_DATA_512B_FIFO_CNT11(x) ((x) << S_RD_DATA_512B_FIFO_CNT11)
19320 #define G_RD_DATA_512B_FIFO_CNT11(x) (((x) >> S_RD_DATA_512B_FIFO_CNT11) & M_RD_DATA_512B_FIFO_CNT11)
19321 
19322 #define S_RD_REQ_TAG_FIFO_CNT11    1
19323 #define M_RD_REQ_TAG_FIFO_CNT11    0xfU
19324 #define V_RD_REQ_TAG_FIFO_CNT11(x) ((x) << S_RD_REQ_TAG_FIFO_CNT11)
19325 #define G_RD_REQ_TAG_FIFO_CNT11(x) (((x) >> S_RD_REQ_TAG_FIFO_CNT11) & M_RD_REQ_TAG_FIFO_CNT11)
19326 
19327 #define A_MA_HMA_CLIENT_INTERFACE_INTERNAL_REG0 0xa40c
19328 
19329 #define S_CMD_IN_FIFO_CNT12    30
19330 #define M_CMD_IN_FIFO_CNT12    0x3U
19331 #define V_CMD_IN_FIFO_CNT12(x) ((x) << S_CMD_IN_FIFO_CNT12)
19332 #define G_CMD_IN_FIFO_CNT12(x) (((x) >> S_CMD_IN_FIFO_CNT12) & M_CMD_IN_FIFO_CNT12)
19333 
19334 #define S_CMD_SPLIT_FIFO_CNT12    28
19335 #define M_CMD_SPLIT_FIFO_CNT12    0x3U
19336 #define V_CMD_SPLIT_FIFO_CNT12(x) ((x) << S_CMD_SPLIT_FIFO_CNT12)
19337 #define G_CMD_SPLIT_FIFO_CNT12(x) (((x) >> S_CMD_SPLIT_FIFO_CNT12) & M_CMD_SPLIT_FIFO_CNT12)
19338 
19339 #define S_CMD_THROTTLE_FIFO_CNT12    22
19340 #define M_CMD_THROTTLE_FIFO_CNT12    0x3fU
19341 #define V_CMD_THROTTLE_FIFO_CNT12(x) ((x) << S_CMD_THROTTLE_FIFO_CNT12)
19342 #define G_CMD_THROTTLE_FIFO_CNT12(x) (((x) >> S_CMD_THROTTLE_FIFO_CNT12) & M_CMD_THROTTLE_FIFO_CNT12)
19343 
19344 #define S_RD_CHNL_FIFO_CNT12    15
19345 #define M_RD_CHNL_FIFO_CNT12    0x7fU
19346 #define V_RD_CHNL_FIFO_CNT12(x) ((x) << S_RD_CHNL_FIFO_CNT12)
19347 #define G_RD_CHNL_FIFO_CNT12(x) (((x) >> S_RD_CHNL_FIFO_CNT12) & M_RD_CHNL_FIFO_CNT12)
19348 
19349 #define S_RD_DATA_EXT_FIFO_CNT12    13
19350 #define M_RD_DATA_EXT_FIFO_CNT12    0x3U
19351 #define V_RD_DATA_EXT_FIFO_CNT12(x) ((x) << S_RD_DATA_EXT_FIFO_CNT12)
19352 #define G_RD_DATA_EXT_FIFO_CNT12(x) (((x) >> S_RD_DATA_EXT_FIFO_CNT12) & M_RD_DATA_EXT_FIFO_CNT12)
19353 
19354 #define S_RD_DATA_512B_FIFO_CNT12    5
19355 #define M_RD_DATA_512B_FIFO_CNT12    0xffU
19356 #define V_RD_DATA_512B_FIFO_CNT12(x) ((x) << S_RD_DATA_512B_FIFO_CNT12)
19357 #define G_RD_DATA_512B_FIFO_CNT12(x) (((x) >> S_RD_DATA_512B_FIFO_CNT12) & M_RD_DATA_512B_FIFO_CNT12)
19358 
19359 #define S_RD_REQ_TAG_FIFO_CNT12    1
19360 #define M_RD_REQ_TAG_FIFO_CNT12    0xfU
19361 #define V_RD_REQ_TAG_FIFO_CNT12(x) ((x) << S_RD_REQ_TAG_FIFO_CNT12)
19362 #define G_RD_REQ_TAG_FIFO_CNT12(x) (((x) >> S_RD_REQ_TAG_FIFO_CNT12) & M_RD_REQ_TAG_FIFO_CNT12)
19363 
19364 #define A_MA_TARGET_0_ARBITER_INTERFACE_INTERNAL_REG0 0xa40d
19365 
19366 #define S_WR_DATA_FSM0    23
19367 #define V_WR_DATA_FSM0(x) ((x) << S_WR_DATA_FSM0)
19368 #define F_WR_DATA_FSM0    V_WR_DATA_FSM0(1U)
19369 
19370 #define S_RD_DATA_FSM0    22
19371 #define V_RD_DATA_FSM0(x) ((x) << S_RD_DATA_FSM0)
19372 #define F_RD_DATA_FSM0    V_RD_DATA_FSM0(1U)
19373 
19374 #define S_TGT_CMD_FIFO_CNT0    19
19375 #define M_TGT_CMD_FIFO_CNT0    0x7U
19376 #define V_TGT_CMD_FIFO_CNT0(x) ((x) << S_TGT_CMD_FIFO_CNT0)
19377 #define G_TGT_CMD_FIFO_CNT0(x) (((x) >> S_TGT_CMD_FIFO_CNT0) & M_TGT_CMD_FIFO_CNT0)
19378 
19379 #define S_CLNT_NUM_FIFO_CNT0    16
19380 #define M_CLNT_NUM_FIFO_CNT0    0x7U
19381 #define V_CLNT_NUM_FIFO_CNT0(x) ((x) << S_CLNT_NUM_FIFO_CNT0)
19382 #define G_CLNT_NUM_FIFO_CNT0(x) (((x) >> S_CLNT_NUM_FIFO_CNT0) & M_CLNT_NUM_FIFO_CNT0)
19383 
19384 #define S_WR_CMD_TAG_FIFO_CNT_TGT0    8
19385 #define M_WR_CMD_TAG_FIFO_CNT_TGT0    0xffU
19386 #define V_WR_CMD_TAG_FIFO_CNT_TGT0(x) ((x) << S_WR_CMD_TAG_FIFO_CNT_TGT0)
19387 #define G_WR_CMD_TAG_FIFO_CNT_TGT0(x) (((x) >> S_WR_CMD_TAG_FIFO_CNT_TGT0) & M_WR_CMD_TAG_FIFO_CNT_TGT0)
19388 
19389 #define S_WR_DATA_512B_FIFO_CNT_TGT0    0
19390 #define M_WR_DATA_512B_FIFO_CNT_TGT0    0xffU
19391 #define V_WR_DATA_512B_FIFO_CNT_TGT0(x) ((x) << S_WR_DATA_512B_FIFO_CNT_TGT0)
19392 #define G_WR_DATA_512B_FIFO_CNT_TGT0(x) (((x) >> S_WR_DATA_512B_FIFO_CNT_TGT0) & M_WR_DATA_512B_FIFO_CNT_TGT0)
19393 
19394 #define A_MA_TARGET_1_ARBITER_INTERFACE_INTERNAL_REG0 0xa40e
19395 
19396 #define S_WR_DATA_FSM1    23
19397 #define V_WR_DATA_FSM1(x) ((x) << S_WR_DATA_FSM1)
19398 #define F_WR_DATA_FSM1    V_WR_DATA_FSM1(1U)
19399 
19400 #define S_RD_DATA_FSM1    22
19401 #define V_RD_DATA_FSM1(x) ((x) << S_RD_DATA_FSM1)
19402 #define F_RD_DATA_FSM1    V_RD_DATA_FSM1(1U)
19403 
19404 #define S_TGT_CMD_FIFO_CNT1    19
19405 #define M_TGT_CMD_FIFO_CNT1    0x7U
19406 #define V_TGT_CMD_FIFO_CNT1(x) ((x) << S_TGT_CMD_FIFO_CNT1)
19407 #define G_TGT_CMD_FIFO_CNT1(x) (((x) >> S_TGT_CMD_FIFO_CNT1) & M_TGT_CMD_FIFO_CNT1)
19408 
19409 #define S_CLNT_NUM_FIFO_CNT1    16
19410 #define M_CLNT_NUM_FIFO_CNT1    0x7U
19411 #define V_CLNT_NUM_FIFO_CNT1(x) ((x) << S_CLNT_NUM_FIFO_CNT1)
19412 #define G_CLNT_NUM_FIFO_CNT1(x) (((x) >> S_CLNT_NUM_FIFO_CNT1) & M_CLNT_NUM_FIFO_CNT1)
19413 
19414 #define S_WR_CMD_TAG_FIFO_CNT_TGT1    8
19415 #define M_WR_CMD_TAG_FIFO_CNT_TGT1    0xffU
19416 #define V_WR_CMD_TAG_FIFO_CNT_TGT1(x) ((x) << S_WR_CMD_TAG_FIFO_CNT_TGT1)
19417 #define G_WR_CMD_TAG_FIFO_CNT_TGT1(x) (((x) >> S_WR_CMD_TAG_FIFO_CNT_TGT1) & M_WR_CMD_TAG_FIFO_CNT_TGT1)
19418 
19419 #define S_WR_DATA_512B_FIFO_CNT_TGT1    0
19420 #define M_WR_DATA_512B_FIFO_CNT_TGT1    0xffU
19421 #define V_WR_DATA_512B_FIFO_CNT_TGT1(x) ((x) << S_WR_DATA_512B_FIFO_CNT_TGT1)
19422 #define G_WR_DATA_512B_FIFO_CNT_TGT1(x) (((x) >> S_WR_DATA_512B_FIFO_CNT_TGT1) & M_WR_DATA_512B_FIFO_CNT_TGT1)
19423 
19424 #define A_MA_TARGET_2_ARBITER_INTERFACE_INTERNAL_REG0 0xa40f
19425 
19426 #define S_WR_DATA_FSM2    23
19427 #define V_WR_DATA_FSM2(x) ((x) << S_WR_DATA_FSM2)
19428 #define F_WR_DATA_FSM2    V_WR_DATA_FSM2(1U)
19429 
19430 #define S_RD_DATA_FSM2    22
19431 #define V_RD_DATA_FSM2(x) ((x) << S_RD_DATA_FSM2)
19432 #define F_RD_DATA_FSM2    V_RD_DATA_FSM2(1U)
19433 
19434 #define S_TGT_CMD_FIFO_CNT2    19
19435 #define M_TGT_CMD_FIFO_CNT2    0x7U
19436 #define V_TGT_CMD_FIFO_CNT2(x) ((x) << S_TGT_CMD_FIFO_CNT2)
19437 #define G_TGT_CMD_FIFO_CNT2(x) (((x) >> S_TGT_CMD_FIFO_CNT2) & M_TGT_CMD_FIFO_CNT2)
19438 
19439 #define S_CLNT_NUM_FIFO_CNT2    16
19440 #define M_CLNT_NUM_FIFO_CNT2    0x7U
19441 #define V_CLNT_NUM_FIFO_CNT2(x) ((x) << S_CLNT_NUM_FIFO_CNT2)
19442 #define G_CLNT_NUM_FIFO_CNT2(x) (((x) >> S_CLNT_NUM_FIFO_CNT2) & M_CLNT_NUM_FIFO_CNT2)
19443 
19444 #define S_WR_CMD_TAG_FIFO_CNT_TGT2    8
19445 #define M_WR_CMD_TAG_FIFO_CNT_TGT2    0xffU
19446 #define V_WR_CMD_TAG_FIFO_CNT_TGT2(x) ((x) << S_WR_CMD_TAG_FIFO_CNT_TGT2)
19447 #define G_WR_CMD_TAG_FIFO_CNT_TGT2(x) (((x) >> S_WR_CMD_TAG_FIFO_CNT_TGT2) & M_WR_CMD_TAG_FIFO_CNT_TGT2)
19448 
19449 #define S_WR_DATA_512B_FIFO_CNT_TGT2    0
19450 #define M_WR_DATA_512B_FIFO_CNT_TGT2    0xffU
19451 #define V_WR_DATA_512B_FIFO_CNT_TGT2(x) ((x) << S_WR_DATA_512B_FIFO_CNT_TGT2)
19452 #define G_WR_DATA_512B_FIFO_CNT_TGT2(x) (((x) >> S_WR_DATA_512B_FIFO_CNT_TGT2) & M_WR_DATA_512B_FIFO_CNT_TGT2)
19453 
19454 #define A_MA_TARGET_3_ARBITER_INTERFACE_INTERNAL_REG0 0xa410
19455 
19456 #define S_WR_DATA_FSM3    23
19457 #define V_WR_DATA_FSM3(x) ((x) << S_WR_DATA_FSM3)
19458 #define F_WR_DATA_FSM3    V_WR_DATA_FSM3(1U)
19459 
19460 #define S_RD_DATA_FSM3    22
19461 #define V_RD_DATA_FSM3(x) ((x) << S_RD_DATA_FSM3)
19462 #define F_RD_DATA_FSM3    V_RD_DATA_FSM3(1U)
19463 
19464 #define S_TGT_CMD_FIFO_CNT3    19
19465 #define M_TGT_CMD_FIFO_CNT3    0x7U
19466 #define V_TGT_CMD_FIFO_CNT3(x) ((x) << S_TGT_CMD_FIFO_CNT3)
19467 #define G_TGT_CMD_FIFO_CNT3(x) (((x) >> S_TGT_CMD_FIFO_CNT3) & M_TGT_CMD_FIFO_CNT3)
19468 
19469 #define S_CLNT_NUM_FIFO_CNT3    16
19470 #define M_CLNT_NUM_FIFO_CNT3    0x7U
19471 #define V_CLNT_NUM_FIFO_CNT3(x) ((x) << S_CLNT_NUM_FIFO_CNT3)
19472 #define G_CLNT_NUM_FIFO_CNT3(x) (((x) >> S_CLNT_NUM_FIFO_CNT3) & M_CLNT_NUM_FIFO_CNT3)
19473 
19474 #define S_WR_CMD_TAG_FIFO_CNT_TGT3    8
19475 #define M_WR_CMD_TAG_FIFO_CNT_TGT3    0xffU
19476 #define V_WR_CMD_TAG_FIFO_CNT_TGT3(x) ((x) << S_WR_CMD_TAG_FIFO_CNT_TGT3)
19477 #define G_WR_CMD_TAG_FIFO_CNT_TGT3(x) (((x) >> S_WR_CMD_TAG_FIFO_CNT_TGT3) & M_WR_CMD_TAG_FIFO_CNT_TGT3)
19478 
19479 #define S_WR_DATA_512B_FIFO_CNT_TGT    0
19480 #define M_WR_DATA_512B_FIFO_CNT_TGT    0xffU
19481 #define V_WR_DATA_512B_FIFO_CNT_TGT(x) ((x) << S_WR_DATA_512B_FIFO_CNT_TGT)
19482 #define G_WR_DATA_512B_FIFO_CNT_TGT(x) (((x) >> S_WR_DATA_512B_FIFO_CNT_TGT) & M_WR_DATA_512B_FIFO_CNT_TGT)
19483 
19484 #define A_MA_SGE_THREAD_0_CLNT_EXP_RD_CYC_CNT_LO 0xa412
19485 #define A_MA_SGE_THREAD_1_CLNT_EXP_RD_CYC_CNT_LO 0xa413
19486 #define A_MA_ULP_TX_CLNT_EXP_RD_CYC_CNT_LO 0xa414
19487 #define A_MA_ULP_RX_CLNT_EXP_RD_CYC_CNT_LO 0xa415
19488 #define A_MA_ULP_TX_RX_CLNT_EXP_RD_CYC_CNT_LO 0xa416
19489 #define A_MA_TP_THREAD_0_CLNT_EXP_RD_CYC_CNT_LO 0xa417
19490 #define A_MA_TP_THREAD_1_CLNT_EXP_RD_CYC_CNT_LO 0xa418
19491 #define A_MA_LE_CLNT_EXP_RD_CYC_CNT_LO 0xa419
19492 #define A_MA_CIM_CLNT_EXP_RD_CYC_CNT_LO 0xa41a
19493 #define A_MA_PCIE_CLNT_EXP_RD_CYC_CNT_LO 0xa41b
19494 #define A_MA_PM_TX_CLNT_EXP_RD_CYC_CNT_LO 0xa41c
19495 #define A_MA_PM_RX_CLNT_EXP_RD_CYC_CNT_LO 0xa41d
19496 #define A_MA_HMA_CLNT_EXP_RD_CYC_CNT_LO 0xa41e
19497 #define A_T6_MA_EDRAM0_WRDATA_CNT1 0xa800
19498 #define A_T6_MA_EDRAM0_WRDATA_CNT0 0xa801
19499 #define A_T6_MA_EDRAM1_WRDATA_CNT1 0xa802
19500 #define A_T6_MA_EDRAM1_WRDATA_CNT0 0xa803
19501 #define A_T6_MA_EXT_MEMORY0_WRDATA_CNT1 0xa804
19502 #define A_T6_MA_EXT_MEMORY0_WRDATA_CNT0 0xa805
19503 #define A_T6_MA_HOST_MEMORY_WRDATA_CNT1 0xa806
19504 #define A_T6_MA_HOST_MEMORY_WRDATA_CNT0 0xa807
19505 #define A_T6_MA_EXT_MEMORY1_WRDATA_CNT1 0xa808
19506 #define A_T6_MA_EXT_MEMORY1_WRDATA_CNT0 0xa809
19507 #define A_T6_MA_EDRAM0_RDDATA_CNT1 0xa80a
19508 #define A_T6_MA_EDRAM0_RDDATA_CNT0 0xa80b
19509 #define A_T6_MA_EDRAM1_RDDATA_CNT1 0xa80c
19510 #define A_T6_MA_EDRAM1_RDDATA_CNT0 0xa80d
19511 #define A_T6_MA_EXT_MEMORY0_RDDATA_CNT1 0xa80e
19512 #define A_T6_MA_EXT_MEMORY0_RDDATA_CNT0 0xa80f
19513 #define A_T6_MA_HOST_MEMORY_RDDATA_CNT1 0xa810
19514 #define A_T6_MA_HOST_MEMORY_RDDATA_CNT0 0xa811
19515 #define A_T6_MA_EXT_MEMORY1_RDDATA_CNT1 0xa812
19516 #define A_T6_MA_EXT_MEMORY1_RDDATA_CNT0 0xa813
19517 #define A_MA_SGE_THREAD_0_CLNT_ACT_WR_CYC_CNT_HI 0xac00
19518 #define A_MA_SGE_THREAD_0_CLNT_ACT_WR_CYC_CNT_LO 0xac01
19519 #define A_MA_SGE_THREAD_1_CLNT_ACT_WR_CYC_CNT_HI 0xac02
19520 #define A_MA_SGE_THREAD_1_CLNT_ACT_WR_CYC_CNT_LO 0xac03
19521 #define A_MA_ULP_TX_CLNT_ACT_WR_CYC_CNT_HI 0xac04
19522 #define A_MA_ULP_TX_CLNT_ACT_WR_CYC_CNT_LO 0xac05
19523 #define A_MA_ULP_RX_CLNT_ACT_WR_CYC_CNT_HI 0xac06
19524 #define A_MA_ULP_RX_CLNT_ACT_WR_CYC_CNT_LO 0xac07
19525 #define A_MA_ULP_TX_RX_CLNT_ACT_WR_CYC_CNT_HI 0xac08
19526 #define A_MA_ULP_TX_RX_CLNT_ACT_WR_CYC_CNT_LO 0xac09
19527 #define A_MA_TP_THREAD_0_CLNT_ACT_WR_CYC_CNT_HI 0xac0a
19528 #define A_MA_TP_THREAD_0_CLNT_ACT_WR_CYC_CNT_LO 0xac0b
19529 #define A_MA_TP_THREAD_1_CLNT_ACT_WR_CYC_CNT_HI 0xac0c
19530 #define A_MA_TP_THREAD_1_CLNT_ACT_WR_CYC_CNT_LO 0xac0d
19531 #define A_MA_LE_CLNT_ACT_WR_CYC_CNT_HI 0xac0e
19532 #define A_MA_LE_CLNT_ACT_WR_CYC_CNT_LO 0xac0f
19533 #define A_MA_CIM_CLNT_ACT_WR_CYC_CNT_HI 0xac10
19534 #define A_MA_CIM_CLNT_ACT_WR_CYC_CNT_LO 0xac11
19535 #define A_MA_PCIE_CLNT_ACT_WR_CYC_CNT_HI 0xac12
19536 #define A_MA_PCIE_CLNT_ACT_WR_CYC_CNT_LO 0xac13
19537 #define A_MA_PM_TX_CLNT_ACT_WR_CYC_CNT_HI 0xac14
19538 #define A_MA_PM_TX_CLNT_ACT_WR_CYC_CNT_LO 0xac15
19539 #define A_MA_PM_RX_CLNT_ACT_WR_CYC_CNT_HI 0xac16
19540 #define A_MA_PM_RX_CLNT_ACT_WR_CYC_CNT_LO 0xac17
19541 #define A_MA_HMA_CLNT_ACT_WR_CYC_CNT_HI 0xac18
19542 #define A_MA_HMA_CLNT_ACT_WR_CYC_CNT_LO 0xac19
19543 #define A_MA_SGE_THREAD_0_CLNT_WR_REQ_CNT 0xb000
19544 #define A_MA_SGE_THREAD_1_CLNT_WR_REQ_CNT 0xb001
19545 #define A_MA_ULP_TX_CLNT_WR_REQ_CNT 0xb002
19546 #define A_MA_ULP_RX_CLNT_WR_REQ_CNT 0xb003
19547 #define A_MA_ULP_TX_RX_CLNT_WR_REQ_CNT 0xb004
19548 #define A_MA_TP_THREAD_0_CLNT_WR_REQ_CNT 0xb005
19549 #define A_MA_TP_THREAD_1_CLNT_WR_REQ_CNT 0xb006
19550 #define A_MA_LE_CLNT_WR_REQ_CNT 0xb007
19551 #define A_MA_CIM_CLNT_WR_REQ_CNT 0xb008
19552 #define A_MA_PCIE_CLNT_WR_REQ_CNT 0xb009
19553 #define A_MA_PM_TX_CLNT_WR_REQ_CNT 0xb00a
19554 #define A_MA_PM_RX_CLNT_WR_REQ_CNT 0xb00b
19555 #define A_MA_HMA_CLNT_WR_REQ_CNT 0xb00c
19556 #define A_MA_SGE_THREAD_0_CLNT_RD_REQ_CNT 0xb00d
19557 #define A_MA_SGE_THREAD_1_CLNT_RD_REQ_CNT 0xb00e
19558 #define A_MA_ULP_TX_CLNT_RD_REQ_CNT 0xb00f
19559 #define A_MA_ULP_RX_CLNT_RD_REQ_CNT 0xb010
19560 #define A_MA_ULP_TX_RX_CLNT_RD_REQ_CNT 0xb011
19561 #define A_MA_TP_THREAD_0_CLNT_RD_REQ_CNT 0xb012
19562 #define A_MA_TP_THREAD_1_CLNT_RD_REQ_CNT 0xb013
19563 #define A_MA_LE_CLNT_RD_REQ_CNT 0xb014
19564 #define A_MA_CIM_CLNT_RD_REQ_CNT 0xb015
19565 #define A_MA_PCIE_CLNT_RD_REQ_CNT 0xb016
19566 #define A_MA_PM_TX_CLNT_RD_REQ_CNT 0xb017
19567 #define A_MA_PM_RX_CLNT_RD_REQ_CNT 0xb018
19568 #define A_MA_HMA_CLNT_RD_REQ_CNT 0xb019
19569 #define A_MA_SGE_THREAD_0_CLNT_EXP_RD_CYC_CNT_HI 0xb400
19570 #define A_MA_SGE_THREAD_1_CLNT_EXP_RD_CYC_CNT_HI 0xb401
19571 #define A_MA_ULP_TX_CLNT_EXP_RD_CYC_CNT_HI 0xb402
19572 #define A_MA_ULP_RX_CLNT_EXP_RD_CYC_CNT_HI 0xb403
19573 #define A_MA_ULP_TX_RX_CLNT_EXP_RD_CYC_CNT_HI 0xb404
19574 #define A_MA_TP_THREAD_0_CLNT_EXP_RD_CYC_CNT_HI 0xb405
19575 #define A_MA_TP_THREAD_1_CLNT_EXP_RD_CYC_CNT_HI 0xb406
19576 #define A_MA_LE_CLNT_EXP_RD_CYC_CNT_HI 0xb407
19577 #define A_MA_CIM_CLNT_EXP_RD_CYC_CNT_HI 0xb408
19578 #define A_MA_PCIE_CLNT_EXP_RD_CYC_CNT_HI 0xb409
19579 #define A_MA_PM_TX_CLNT_EXP_RD_CYC_CNT_HI 0xb40a
19580 #define A_MA_PM_RX_CLNT_EXP_RD_CYC_CNT_HI 0xb40b
19581 #define A_MA_HMA_CLNT_EXP_RD_CYC_CNT_HI 0xb40c
19582 #define A_MA_SGE_THREAD_0_CLNT_EXP_WR_CYC_CNT_HI 0xb40d
19583 #define A_MA_SGE_THREAD_1_CLNT_EXP_WR_CYC_CNT_HI 0xb40e
19584 #define A_MA_ULP_TX_CLNT_EXP_WR_CYC_CNT_HI 0xb40f
19585 #define A_MA_ULP_RX_CLNT_EXP_WR_CYC_CNT_HI 0xb410
19586 #define A_MA_ULP_TX_RX_CLNT_EXP_WR_CYC_CNT_HI 0xb411
19587 #define A_MA_TP_THREAD_0_CLNT_EXP_WR_CYC_CNT_HI 0xb412
19588 #define A_MA_TP_THREAD_1_CLNT_EXP_WR_CYC_CNT_HI 0xb413
19589 #define A_MA_LE_CLNT_EXP_WR_CYC_CNT_HI 0xb414
19590 #define A_MA_CIM_CLNT_EXP_WR_CYC_CNT_HI 0xb415
19591 #define A_MA_PCIE_CLNT_EXP_WR_CYC_CNT_HI 0xb416
19592 #define A_MA_PM_TX_CLNT_EXP_WR_CYC_CNT_HI 0xb417
19593 #define A_MA_PM_RX_CLNT_EXP_WR_CYC_CNT_HI 0xb418
19594 #define A_MA_HMA_CLNT_EXP_WR_CYC_CNT_HI 0xb419
19595 #define A_MA_SGE_THREAD_0_CLIENT_INTERFACE_INTERNAL_REG1 0xe400
19596 
19597 #define S_WR_DATA_EXT_FIFO_CNT0    30
19598 #define M_WR_DATA_EXT_FIFO_CNT0    0x3U
19599 #define V_WR_DATA_EXT_FIFO_CNT0(x) ((x) << S_WR_DATA_EXT_FIFO_CNT0)
19600 #define G_WR_DATA_EXT_FIFO_CNT0(x) (((x) >> S_WR_DATA_EXT_FIFO_CNT0) & M_WR_DATA_EXT_FIFO_CNT0)
19601 
19602 #define S_WR_CMD_TAG_FIFO_CNT0    26
19603 #define M_WR_CMD_TAG_FIFO_CNT0    0xfU
19604 #define V_WR_CMD_TAG_FIFO_CNT0(x) ((x) << S_WR_CMD_TAG_FIFO_CNT0)
19605 #define G_WR_CMD_TAG_FIFO_CNT0(x) (((x) >> S_WR_CMD_TAG_FIFO_CNT0) & M_WR_CMD_TAG_FIFO_CNT0)
19606 
19607 #define S_WR_DATA_512B_FIFO_CNT0    18
19608 #define M_WR_DATA_512B_FIFO_CNT0    0xffU
19609 #define V_WR_DATA_512B_FIFO_CNT0(x) ((x) << S_WR_DATA_512B_FIFO_CNT0)
19610 #define G_WR_DATA_512B_FIFO_CNT0(x) (((x) >> S_WR_DATA_512B_FIFO_CNT0) & M_WR_DATA_512B_FIFO_CNT0)
19611 
19612 #define S_RD_DATA_ALIGN_FSM0    17
19613 #define V_RD_DATA_ALIGN_FSM0(x) ((x) << S_RD_DATA_ALIGN_FSM0)
19614 #define F_RD_DATA_ALIGN_FSM0    V_RD_DATA_ALIGN_FSM0(1U)
19615 
19616 #define S_RD_DATA_FETCH_FSM0    16
19617 #define V_RD_DATA_FETCH_FSM0(x) ((x) << S_RD_DATA_FETCH_FSM0)
19618 #define F_RD_DATA_FETCH_FSM0    V_RD_DATA_FETCH_FSM0(1U)
19619 
19620 #define S_COHERENCY_TX_FSM0    15
19621 #define V_COHERENCY_TX_FSM0(x) ((x) << S_COHERENCY_TX_FSM0)
19622 #define F_COHERENCY_TX_FSM0    V_COHERENCY_TX_FSM0(1U)
19623 
19624 #define S_COHERENCY_RX_FSM0    14
19625 #define V_COHERENCY_RX_FSM0(x) ((x) << S_COHERENCY_RX_FSM0)
19626 #define F_COHERENCY_RX_FSM0    V_COHERENCY_RX_FSM0(1U)
19627 
19628 #define S_ARB_REQ_FSM0    13
19629 #define V_ARB_REQ_FSM0(x) ((x) << S_ARB_REQ_FSM0)
19630 #define F_ARB_REQ_FSM0    V_ARB_REQ_FSM0(1U)
19631 
19632 #define S_CMD_SPLIT_FSM0    10
19633 #define M_CMD_SPLIT_FSM0    0x7U
19634 #define V_CMD_SPLIT_FSM0(x) ((x) << S_CMD_SPLIT_FSM0)
19635 #define G_CMD_SPLIT_FSM0(x) (((x) >> S_CMD_SPLIT_FSM0) & M_CMD_SPLIT_FSM0)
19636 
19637 #define A_MA_SGE_THREAD_1_CLIENT_INTERFACE_INTERNAL_REG1 0xe420
19638 
19639 #define S_WR_DATA_EXT_FIFO_CNT1    30
19640 #define M_WR_DATA_EXT_FIFO_CNT1    0x3U
19641 #define V_WR_DATA_EXT_FIFO_CNT1(x) ((x) << S_WR_DATA_EXT_FIFO_CNT1)
19642 #define G_WR_DATA_EXT_FIFO_CNT1(x) (((x) >> S_WR_DATA_EXT_FIFO_CNT1) & M_WR_DATA_EXT_FIFO_CNT1)
19643 
19644 #define S_WR_CMD_TAG_FIFO_CNT1    26
19645 #define M_WR_CMD_TAG_FIFO_CNT1    0xfU
19646 #define V_WR_CMD_TAG_FIFO_CNT1(x) ((x) << S_WR_CMD_TAG_FIFO_CNT1)
19647 #define G_WR_CMD_TAG_FIFO_CNT1(x) (((x) >> S_WR_CMD_TAG_FIFO_CNT1) & M_WR_CMD_TAG_FIFO_CNT1)
19648 
19649 #define S_WR_DATA_512B_FIFO_CNT1    18
19650 #define M_WR_DATA_512B_FIFO_CNT1    0xffU
19651 #define V_WR_DATA_512B_FIFO_CNT1(x) ((x) << S_WR_DATA_512B_FIFO_CNT1)
19652 #define G_WR_DATA_512B_FIFO_CNT1(x) (((x) >> S_WR_DATA_512B_FIFO_CNT1) & M_WR_DATA_512B_FIFO_CNT1)
19653 
19654 #define S_RD_DATA_ALIGN_FSM1    17
19655 #define V_RD_DATA_ALIGN_FSM1(x) ((x) << S_RD_DATA_ALIGN_FSM1)
19656 #define F_RD_DATA_ALIGN_FSM1    V_RD_DATA_ALIGN_FSM1(1U)
19657 
19658 #define S_RD_DATA_FETCH_FSM1    16
19659 #define V_RD_DATA_FETCH_FSM1(x) ((x) << S_RD_DATA_FETCH_FSM1)
19660 #define F_RD_DATA_FETCH_FSM1    V_RD_DATA_FETCH_FSM1(1U)
19661 
19662 #define S_COHERENCY_TX_FSM1    15
19663 #define V_COHERENCY_TX_FSM1(x) ((x) << S_COHERENCY_TX_FSM1)
19664 #define F_COHERENCY_TX_FSM1    V_COHERENCY_TX_FSM1(1U)
19665 
19666 #define S_COHERENCY_RX_FSM1    14
19667 #define V_COHERENCY_RX_FSM1(x) ((x) << S_COHERENCY_RX_FSM1)
19668 #define F_COHERENCY_RX_FSM1    V_COHERENCY_RX_FSM1(1U)
19669 
19670 #define S_ARB_REQ_FSM1    13
19671 #define V_ARB_REQ_FSM1(x) ((x) << S_ARB_REQ_FSM1)
19672 #define F_ARB_REQ_FSM1    V_ARB_REQ_FSM1(1U)
19673 
19674 #define S_CMD_SPLIT_FSM1    10
19675 #define M_CMD_SPLIT_FSM1    0x7U
19676 #define V_CMD_SPLIT_FSM1(x) ((x) << S_CMD_SPLIT_FSM1)
19677 #define G_CMD_SPLIT_FSM1(x) (((x) >> S_CMD_SPLIT_FSM1) & M_CMD_SPLIT_FSM1)
19678 
19679 #define A_MA_ULP_TX_CLIENT_INTERFACE_INTERNAL_REG1 0xe440
19680 
19681 #define S_WR_DATA_EXT_FIFO_CNT2    30
19682 #define M_WR_DATA_EXT_FIFO_CNT2    0x3U
19683 #define V_WR_DATA_EXT_FIFO_CNT2(x) ((x) << S_WR_DATA_EXT_FIFO_CNT2)
19684 #define G_WR_DATA_EXT_FIFO_CNT2(x) (((x) >> S_WR_DATA_EXT_FIFO_CNT2) & M_WR_DATA_EXT_FIFO_CNT2)
19685 
19686 #define S_WR_CMD_TAG_FIFO_CNT2    26
19687 #define M_WR_CMD_TAG_FIFO_CNT2    0xfU
19688 #define V_WR_CMD_TAG_FIFO_CNT2(x) ((x) << S_WR_CMD_TAG_FIFO_CNT2)
19689 #define G_WR_CMD_TAG_FIFO_CNT2(x) (((x) >> S_WR_CMD_TAG_FIFO_CNT2) & M_WR_CMD_TAG_FIFO_CNT2)
19690 
19691 #define S_WR_DATA_512B_FIFO_CNT2    18
19692 #define M_WR_DATA_512B_FIFO_CNT2    0xffU
19693 #define V_WR_DATA_512B_FIFO_CNT2(x) ((x) << S_WR_DATA_512B_FIFO_CNT2)
19694 #define G_WR_DATA_512B_FIFO_CNT2(x) (((x) >> S_WR_DATA_512B_FIFO_CNT2) & M_WR_DATA_512B_FIFO_CNT2)
19695 
19696 #define S_RD_DATA_ALIGN_FSM2    17
19697 #define V_RD_DATA_ALIGN_FSM2(x) ((x) << S_RD_DATA_ALIGN_FSM2)
19698 #define F_RD_DATA_ALIGN_FSM2    V_RD_DATA_ALIGN_FSM2(1U)
19699 
19700 #define S_RD_DATA_FETCH_FSM2    16
19701 #define V_RD_DATA_FETCH_FSM2(x) ((x) << S_RD_DATA_FETCH_FSM2)
19702 #define F_RD_DATA_FETCH_FSM2    V_RD_DATA_FETCH_FSM2(1U)
19703 
19704 #define S_COHERENCY_TX_FSM2    15
19705 #define V_COHERENCY_TX_FSM2(x) ((x) << S_COHERENCY_TX_FSM2)
19706 #define F_COHERENCY_TX_FSM2    V_COHERENCY_TX_FSM2(1U)
19707 
19708 #define S_COHERENCY_RX_FSM2    14
19709 #define V_COHERENCY_RX_FSM2(x) ((x) << S_COHERENCY_RX_FSM2)
19710 #define F_COHERENCY_RX_FSM2    V_COHERENCY_RX_FSM2(1U)
19711 
19712 #define S_ARB_REQ_FSM2    13
19713 #define V_ARB_REQ_FSM2(x) ((x) << S_ARB_REQ_FSM2)
19714 #define F_ARB_REQ_FSM2    V_ARB_REQ_FSM2(1U)
19715 
19716 #define S_CMD_SPLIT_FSM2    10
19717 #define M_CMD_SPLIT_FSM2    0x7U
19718 #define V_CMD_SPLIT_FSM2(x) ((x) << S_CMD_SPLIT_FSM2)
19719 #define G_CMD_SPLIT_FSM2(x) (((x) >> S_CMD_SPLIT_FSM2) & M_CMD_SPLIT_FSM2)
19720 
19721 #define A_MA_ULP_RX_CLIENT_INTERFACE_INTERNAL_REG1 0xe460
19722 
19723 #define S_WR_DATA_EXT_FIFO_CNT3    30
19724 #define M_WR_DATA_EXT_FIFO_CNT3    0x3U
19725 #define V_WR_DATA_EXT_FIFO_CNT3(x) ((x) << S_WR_DATA_EXT_FIFO_CNT3)
19726 #define G_WR_DATA_EXT_FIFO_CNT3(x) (((x) >> S_WR_DATA_EXT_FIFO_CNT3) & M_WR_DATA_EXT_FIFO_CNT3)
19727 
19728 #define S_WR_CMD_TAG_FIFO_CNT3    26
19729 #define M_WR_CMD_TAG_FIFO_CNT3    0xfU
19730 #define V_WR_CMD_TAG_FIFO_CNT3(x) ((x) << S_WR_CMD_TAG_FIFO_CNT3)
19731 #define G_WR_CMD_TAG_FIFO_CNT3(x) (((x) >> S_WR_CMD_TAG_FIFO_CNT3) & M_WR_CMD_TAG_FIFO_CNT3)
19732 
19733 #define S_WR_DATA_512B_FIFO_CNT3    18
19734 #define M_WR_DATA_512B_FIFO_CNT3    0xffU
19735 #define V_WR_DATA_512B_FIFO_CNT3(x) ((x) << S_WR_DATA_512B_FIFO_CNT3)
19736 #define G_WR_DATA_512B_FIFO_CNT3(x) (((x) >> S_WR_DATA_512B_FIFO_CNT3) & M_WR_DATA_512B_FIFO_CNT3)
19737 
19738 #define S_RD_DATA_ALIGN_FSM3    17
19739 #define V_RD_DATA_ALIGN_FSM3(x) ((x) << S_RD_DATA_ALIGN_FSM3)
19740 #define F_RD_DATA_ALIGN_FSM3    V_RD_DATA_ALIGN_FSM3(1U)
19741 
19742 #define S_RD_DATA_FETCH_FSM3    16
19743 #define V_RD_DATA_FETCH_FSM3(x) ((x) << S_RD_DATA_FETCH_FSM3)
19744 #define F_RD_DATA_FETCH_FSM3    V_RD_DATA_FETCH_FSM3(1U)
19745 
19746 #define S_COHERENCY_TX_FSM3    15
19747 #define V_COHERENCY_TX_FSM3(x) ((x) << S_COHERENCY_TX_FSM3)
19748 #define F_COHERENCY_TX_FSM3    V_COHERENCY_TX_FSM3(1U)
19749 
19750 #define S_COHERENCY_RX_FSM3    14
19751 #define V_COHERENCY_RX_FSM3(x) ((x) << S_COHERENCY_RX_FSM3)
19752 #define F_COHERENCY_RX_FSM3    V_COHERENCY_RX_FSM3(1U)
19753 
19754 #define S_ARB_REQ_FSM3    13
19755 #define V_ARB_REQ_FSM3(x) ((x) << S_ARB_REQ_FSM3)
19756 #define F_ARB_REQ_FSM3    V_ARB_REQ_FSM3(1U)
19757 
19758 #define S_CMD_SPLIT_FSM3    10
19759 #define M_CMD_SPLIT_FSM3    0x7U
19760 #define V_CMD_SPLIT_FSM3(x) ((x) << S_CMD_SPLIT_FSM3)
19761 #define G_CMD_SPLIT_FSM3(x) (((x) >> S_CMD_SPLIT_FSM3) & M_CMD_SPLIT_FSM3)
19762 
19763 #define A_MA_ULP_TX_RX_CLIENT_INTERFACE_INTERNAL_REG1 0xe480
19764 
19765 #define S_WR_DATA_EXT_FIFO_CNT4    30
19766 #define M_WR_DATA_EXT_FIFO_CNT4    0x3U
19767 #define V_WR_DATA_EXT_FIFO_CNT4(x) ((x) << S_WR_DATA_EXT_FIFO_CNT4)
19768 #define G_WR_DATA_EXT_FIFO_CNT4(x) (((x) >> S_WR_DATA_EXT_FIFO_CNT4) & M_WR_DATA_EXT_FIFO_CNT4)
19769 
19770 #define S_WR_CMD_TAG_FIFO_CNT4    26
19771 #define M_WR_CMD_TAG_FIFO_CNT4    0xfU
19772 #define V_WR_CMD_TAG_FIFO_CNT4(x) ((x) << S_WR_CMD_TAG_FIFO_CNT4)
19773 #define G_WR_CMD_TAG_FIFO_CNT4(x) (((x) >> S_WR_CMD_TAG_FIFO_CNT4) & M_WR_CMD_TAG_FIFO_CNT4)
19774 
19775 #define S_WR_DATA_512B_FIFO_CNT4    18
19776 #define M_WR_DATA_512B_FIFO_CNT4    0xffU
19777 #define V_WR_DATA_512B_FIFO_CNT4(x) ((x) << S_WR_DATA_512B_FIFO_CNT4)
19778 #define G_WR_DATA_512B_FIFO_CNT4(x) (((x) >> S_WR_DATA_512B_FIFO_CNT4) & M_WR_DATA_512B_FIFO_CNT4)
19779 
19780 #define S_RD_DATA_ALIGN_FSM4    17
19781 #define V_RD_DATA_ALIGN_FSM4(x) ((x) << S_RD_DATA_ALIGN_FSM4)
19782 #define F_RD_DATA_ALIGN_FSM4    V_RD_DATA_ALIGN_FSM4(1U)
19783 
19784 #define S_RD_DATA_FETCH_FSM4    16
19785 #define V_RD_DATA_FETCH_FSM4(x) ((x) << S_RD_DATA_FETCH_FSM4)
19786 #define F_RD_DATA_FETCH_FSM4    V_RD_DATA_FETCH_FSM4(1U)
19787 
19788 #define S_COHERENCY_TX_FSM4    15
19789 #define V_COHERENCY_TX_FSM4(x) ((x) << S_COHERENCY_TX_FSM4)
19790 #define F_COHERENCY_TX_FSM4    V_COHERENCY_TX_FSM4(1U)
19791 
19792 #define S_COHERENCY_RX_FSM4    14
19793 #define V_COHERENCY_RX_FSM4(x) ((x) << S_COHERENCY_RX_FSM4)
19794 #define F_COHERENCY_RX_FSM4    V_COHERENCY_RX_FSM4(1U)
19795 
19796 #define S_ARB_REQ_FSM4    13
19797 #define V_ARB_REQ_FSM4(x) ((x) << S_ARB_REQ_FSM4)
19798 #define F_ARB_REQ_FSM4    V_ARB_REQ_FSM4(1U)
19799 
19800 #define S_CMD_SPLIT_FSM4    10
19801 #define M_CMD_SPLIT_FSM4    0x7U
19802 #define V_CMD_SPLIT_FSM4(x) ((x) << S_CMD_SPLIT_FSM4)
19803 #define G_CMD_SPLIT_FSM4(x) (((x) >> S_CMD_SPLIT_FSM4) & M_CMD_SPLIT_FSM4)
19804 
19805 #define A_MA_TP_THREAD_0_CLIENT_INTERFACE_INTERNAL_REG1 0xe4a0
19806 
19807 #define S_WR_DATA_EXT_FIFO_CNT5    30
19808 #define M_WR_DATA_EXT_FIFO_CNT5    0x3U
19809 #define V_WR_DATA_EXT_FIFO_CNT5(x) ((x) << S_WR_DATA_EXT_FIFO_CNT5)
19810 #define G_WR_DATA_EXT_FIFO_CNT5(x) (((x) >> S_WR_DATA_EXT_FIFO_CNT5) & M_WR_DATA_EXT_FIFO_CNT5)
19811 
19812 #define S_WR_CMD_TAG_FIFO_CNT5    26
19813 #define M_WR_CMD_TAG_FIFO_CNT5    0xfU
19814 #define V_WR_CMD_TAG_FIFO_CNT5(x) ((x) << S_WR_CMD_TAG_FIFO_CNT5)
19815 #define G_WR_CMD_TAG_FIFO_CNT5(x) (((x) >> S_WR_CMD_TAG_FIFO_CNT5) & M_WR_CMD_TAG_FIFO_CNT5)
19816 
19817 #define S_WR_DATA_512B_FIFO_CNT5    18
19818 #define M_WR_DATA_512B_FIFO_CNT5    0xffU
19819 #define V_WR_DATA_512B_FIFO_CNT5(x) ((x) << S_WR_DATA_512B_FIFO_CNT5)
19820 #define G_WR_DATA_512B_FIFO_CNT5(x) (((x) >> S_WR_DATA_512B_FIFO_CNT5) & M_WR_DATA_512B_FIFO_CNT5)
19821 
19822 #define S_RD_DATA_ALIGN_FSM5    17
19823 #define V_RD_DATA_ALIGN_FSM5(x) ((x) << S_RD_DATA_ALIGN_FSM5)
19824 #define F_RD_DATA_ALIGN_FSM5    V_RD_DATA_ALIGN_FSM5(1U)
19825 
19826 #define S_RD_DATA_FETCH_FSM5    16
19827 #define V_RD_DATA_FETCH_FSM5(x) ((x) << S_RD_DATA_FETCH_FSM5)
19828 #define F_RD_DATA_FETCH_FSM5    V_RD_DATA_FETCH_FSM5(1U)
19829 
19830 #define S_COHERENCY_TX_FSM5    15
19831 #define V_COHERENCY_TX_FSM5(x) ((x) << S_COHERENCY_TX_FSM5)
19832 #define F_COHERENCY_TX_FSM5    V_COHERENCY_TX_FSM5(1U)
19833 
19834 #define S_COHERENCY_RX_FSM5    14
19835 #define V_COHERENCY_RX_FSM5(x) ((x) << S_COHERENCY_RX_FSM5)
19836 #define F_COHERENCY_RX_FSM5    V_COHERENCY_RX_FSM5(1U)
19837 
19838 #define S_ARB_REQ_FSM5    13
19839 #define V_ARB_REQ_FSM5(x) ((x) << S_ARB_REQ_FSM5)
19840 #define F_ARB_REQ_FSM5    V_ARB_REQ_FSM5(1U)
19841 
19842 #define S_CMD_SPLIT_FSM5    10
19843 #define M_CMD_SPLIT_FSM5    0x7U
19844 #define V_CMD_SPLIT_FSM5(x) ((x) << S_CMD_SPLIT_FSM5)
19845 #define G_CMD_SPLIT_FSM5(x) (((x) >> S_CMD_SPLIT_FSM5) & M_CMD_SPLIT_FSM5)
19846 
19847 #define A_MA_TP_THREAD_1_CLIENT_INTERFACE_INTERNAL_REG1 0xe4c0
19848 
19849 #define S_WR_DATA_EXT_FIFO_CNT6    30
19850 #define M_WR_DATA_EXT_FIFO_CNT6    0x3U
19851 #define V_WR_DATA_EXT_FIFO_CNT6(x) ((x) << S_WR_DATA_EXT_FIFO_CNT6)
19852 #define G_WR_DATA_EXT_FIFO_CNT6(x) (((x) >> S_WR_DATA_EXT_FIFO_CNT6) & M_WR_DATA_EXT_FIFO_CNT6)
19853 
19854 #define S_WR_CMD_TAG_FIFO_CNT6    26
19855 #define M_WR_CMD_TAG_FIFO_CNT6    0xfU
19856 #define V_WR_CMD_TAG_FIFO_CNT6(x) ((x) << S_WR_CMD_TAG_FIFO_CNT6)
19857 #define G_WR_CMD_TAG_FIFO_CNT6(x) (((x) >> S_WR_CMD_TAG_FIFO_CNT6) & M_WR_CMD_TAG_FIFO_CNT6)
19858 
19859 #define S_WR_DATA_512B_FIFO_CNT6    18
19860 #define M_WR_DATA_512B_FIFO_CNT6    0xffU
19861 #define V_WR_DATA_512B_FIFO_CNT6(x) ((x) << S_WR_DATA_512B_FIFO_CNT6)
19862 #define G_WR_DATA_512B_FIFO_CNT6(x) (((x) >> S_WR_DATA_512B_FIFO_CNT6) & M_WR_DATA_512B_FIFO_CNT6)
19863 
19864 #define S_RD_DATA_ALIGN_FSM6    17
19865 #define V_RD_DATA_ALIGN_FSM6(x) ((x) << S_RD_DATA_ALIGN_FSM6)
19866 #define F_RD_DATA_ALIGN_FSM6    V_RD_DATA_ALIGN_FSM6(1U)
19867 
19868 #define S_RD_DATA_FETCH_FSM6    16
19869 #define V_RD_DATA_FETCH_FSM6(x) ((x) << S_RD_DATA_FETCH_FSM6)
19870 #define F_RD_DATA_FETCH_FSM6    V_RD_DATA_FETCH_FSM6(1U)
19871 
19872 #define S_COHERENCY_TX_FSM6    15
19873 #define V_COHERENCY_TX_FSM6(x) ((x) << S_COHERENCY_TX_FSM6)
19874 #define F_COHERENCY_TX_FSM6    V_COHERENCY_TX_FSM6(1U)
19875 
19876 #define S_COHERENCY_RX_FSM6    14
19877 #define V_COHERENCY_RX_FSM6(x) ((x) << S_COHERENCY_RX_FSM6)
19878 #define F_COHERENCY_RX_FSM6    V_COHERENCY_RX_FSM6(1U)
19879 
19880 #define S_ARB_REQ_FSM6    13
19881 #define V_ARB_REQ_FSM6(x) ((x) << S_ARB_REQ_FSM6)
19882 #define F_ARB_REQ_FSM6    V_ARB_REQ_FSM6(1U)
19883 
19884 #define S_CMD_SPLIT_FSM6    10
19885 #define M_CMD_SPLIT_FSM6    0x7U
19886 #define V_CMD_SPLIT_FSM6(x) ((x) << S_CMD_SPLIT_FSM6)
19887 #define G_CMD_SPLIT_FSM6(x) (((x) >> S_CMD_SPLIT_FSM6) & M_CMD_SPLIT_FSM6)
19888 
19889 #define A_MA_LE_CLIENT_INTERFACE_INTERNAL_REG1 0xe4e0
19890 
19891 #define S_WR_DATA_EXT_FIFO_CNT7    30
19892 #define M_WR_DATA_EXT_FIFO_CNT7    0x3U
19893 #define V_WR_DATA_EXT_FIFO_CNT7(x) ((x) << S_WR_DATA_EXT_FIFO_CNT7)
19894 #define G_WR_DATA_EXT_FIFO_CNT7(x) (((x) >> S_WR_DATA_EXT_FIFO_CNT7) & M_WR_DATA_EXT_FIFO_CNT7)
19895 
19896 #define S_WR_CMD_TAG_FIFO_CNT7    26
19897 #define M_WR_CMD_TAG_FIFO_CNT7    0xfU
19898 #define V_WR_CMD_TAG_FIFO_CNT7(x) ((x) << S_WR_CMD_TAG_FIFO_CNT7)
19899 #define G_WR_CMD_TAG_FIFO_CNT7(x) (((x) >> S_WR_CMD_TAG_FIFO_CNT7) & M_WR_CMD_TAG_FIFO_CNT7)
19900 
19901 #define S_WR_DATA_512B_FIFO_CNT7    18
19902 #define M_WR_DATA_512B_FIFO_CNT7    0xffU
19903 #define V_WR_DATA_512B_FIFO_CNT7(x) ((x) << S_WR_DATA_512B_FIFO_CNT7)
19904 #define G_WR_DATA_512B_FIFO_CNT7(x) (((x) >> S_WR_DATA_512B_FIFO_CNT7) & M_WR_DATA_512B_FIFO_CNT7)
19905 
19906 #define S_RD_DATA_ALIGN_FSM7    17
19907 #define V_RD_DATA_ALIGN_FSM7(x) ((x) << S_RD_DATA_ALIGN_FSM7)
19908 #define F_RD_DATA_ALIGN_FSM7    V_RD_DATA_ALIGN_FSM7(1U)
19909 
19910 #define S_RD_DATA_FETCH_FSM7    16
19911 #define V_RD_DATA_FETCH_FSM7(x) ((x) << S_RD_DATA_FETCH_FSM7)
19912 #define F_RD_DATA_FETCH_FSM7    V_RD_DATA_FETCH_FSM7(1U)
19913 
19914 #define S_COHERENCY_TX_FSM7    15
19915 #define V_COHERENCY_TX_FSM7(x) ((x) << S_COHERENCY_TX_FSM7)
19916 #define F_COHERENCY_TX_FSM7    V_COHERENCY_TX_FSM7(1U)
19917 
19918 #define S_COHERENCY_RX_FSM7    14
19919 #define V_COHERENCY_RX_FSM7(x) ((x) << S_COHERENCY_RX_FSM7)
19920 #define F_COHERENCY_RX_FSM7    V_COHERENCY_RX_FSM7(1U)
19921 
19922 #define S_ARB_REQ_FSM7    13
19923 #define V_ARB_REQ_FSM7(x) ((x) << S_ARB_REQ_FSM7)
19924 #define F_ARB_REQ_FSM7    V_ARB_REQ_FSM7(1U)
19925 
19926 #define S_CMD_SPLIT_FSM7    10
19927 #define M_CMD_SPLIT_FSM7    0x7U
19928 #define V_CMD_SPLIT_FSM7(x) ((x) << S_CMD_SPLIT_FSM7)
19929 #define G_CMD_SPLIT_FSM7(x) (((x) >> S_CMD_SPLIT_FSM7) & M_CMD_SPLIT_FSM7)
19930 
19931 #define A_MA_CIM_CLIENT_INTERFACE_INTERNAL_REG1 0xe500
19932 
19933 #define S_WR_DATA_EXT_FIFO_CNT8    30
19934 #define M_WR_DATA_EXT_FIFO_CNT8    0x3U
19935 #define V_WR_DATA_EXT_FIFO_CNT8(x) ((x) << S_WR_DATA_EXT_FIFO_CNT8)
19936 #define G_WR_DATA_EXT_FIFO_CNT8(x) (((x) >> S_WR_DATA_EXT_FIFO_CNT8) & M_WR_DATA_EXT_FIFO_CNT8)
19937 
19938 #define S_WR_CMD_TAG_FIFO_CNT8    26
19939 #define M_WR_CMD_TAG_FIFO_CNT8    0xfU
19940 #define V_WR_CMD_TAG_FIFO_CNT8(x) ((x) << S_WR_CMD_TAG_FIFO_CNT8)
19941 #define G_WR_CMD_TAG_FIFO_CNT8(x) (((x) >> S_WR_CMD_TAG_FIFO_CNT8) & M_WR_CMD_TAG_FIFO_CNT8)
19942 
19943 #define S_WR_DATA_512B_FIFO_CNT8    18
19944 #define M_WR_DATA_512B_FIFO_CNT8    0xffU
19945 #define V_WR_DATA_512B_FIFO_CNT8(x) ((x) << S_WR_DATA_512B_FIFO_CNT8)
19946 #define G_WR_DATA_512B_FIFO_CNT8(x) (((x) >> S_WR_DATA_512B_FIFO_CNT8) & M_WR_DATA_512B_FIFO_CNT8)
19947 
19948 #define S_RD_DATA_ALIGN_FSM8    17
19949 #define V_RD_DATA_ALIGN_FSM8(x) ((x) << S_RD_DATA_ALIGN_FSM8)
19950 #define F_RD_DATA_ALIGN_FSM8    V_RD_DATA_ALIGN_FSM8(1U)
19951 
19952 #define S_RD_DATA_FETCH_FSM8    16
19953 #define V_RD_DATA_FETCH_FSM8(x) ((x) << S_RD_DATA_FETCH_FSM8)
19954 #define F_RD_DATA_FETCH_FSM8    V_RD_DATA_FETCH_FSM8(1U)
19955 
19956 #define S_COHERENCY_TX_FSM8    15
19957 #define V_COHERENCY_TX_FSM8(x) ((x) << S_COHERENCY_TX_FSM8)
19958 #define F_COHERENCY_TX_FSM8    V_COHERENCY_TX_FSM8(1U)
19959 
19960 #define S_COHERENCY_RX_FSM8    14
19961 #define V_COHERENCY_RX_FSM8(x) ((x) << S_COHERENCY_RX_FSM8)
19962 #define F_COHERENCY_RX_FSM8    V_COHERENCY_RX_FSM8(1U)
19963 
19964 #define S_ARB_REQ_FSM8    13
19965 #define V_ARB_REQ_FSM8(x) ((x) << S_ARB_REQ_FSM8)
19966 #define F_ARB_REQ_FSM8    V_ARB_REQ_FSM8(1U)
19967 
19968 #define S_CMD_SPLIT_FSM8    10
19969 #define M_CMD_SPLIT_FSM8    0x7U
19970 #define V_CMD_SPLIT_FSM8(x) ((x) << S_CMD_SPLIT_FSM8)
19971 #define G_CMD_SPLIT_FSM8(x) (((x) >> S_CMD_SPLIT_FSM8) & M_CMD_SPLIT_FSM8)
19972 
19973 #define A_MA_PCIE_CLIENT_INTERFACE_INTERNAL_REG1 0xe520
19974 
19975 #define S_WR_DATA_EXT_FIFO_CNT9    30
19976 #define M_WR_DATA_EXT_FIFO_CNT9    0x3U
19977 #define V_WR_DATA_EXT_FIFO_CNT9(x) ((x) << S_WR_DATA_EXT_FIFO_CNT9)
19978 #define G_WR_DATA_EXT_FIFO_CNT9(x) (((x) >> S_WR_DATA_EXT_FIFO_CNT9) & M_WR_DATA_EXT_FIFO_CNT9)
19979 
19980 #define S_WR_CMD_TAG_FIFO_CNT9    26
19981 #define M_WR_CMD_TAG_FIFO_CNT9    0xfU
19982 #define V_WR_CMD_TAG_FIFO_CNT9(x) ((x) << S_WR_CMD_TAG_FIFO_CNT9)
19983 #define G_WR_CMD_TAG_FIFO_CNT9(x) (((x) >> S_WR_CMD_TAG_FIFO_CNT9) & M_WR_CMD_TAG_FIFO_CNT9)
19984 
19985 #define S_WR_DATA_512B_FIFO_CNT9    18
19986 #define M_WR_DATA_512B_FIFO_CNT9    0xffU
19987 #define V_WR_DATA_512B_FIFO_CNT9(x) ((x) << S_WR_DATA_512B_FIFO_CNT9)
19988 #define G_WR_DATA_512B_FIFO_CNT9(x) (((x) >> S_WR_DATA_512B_FIFO_CNT9) & M_WR_DATA_512B_FIFO_CNT9)
19989 
19990 #define S_RD_DATA_ALIGN_FSM9    17
19991 #define V_RD_DATA_ALIGN_FSM9(x) ((x) << S_RD_DATA_ALIGN_FSM9)
19992 #define F_RD_DATA_ALIGN_FSM9    V_RD_DATA_ALIGN_FSM9(1U)
19993 
19994 #define S_RD_DATA_FETCH_FSM9    16
19995 #define V_RD_DATA_FETCH_FSM9(x) ((x) << S_RD_DATA_FETCH_FSM9)
19996 #define F_RD_DATA_FETCH_FSM9    V_RD_DATA_FETCH_FSM9(1U)
19997 
19998 #define S_COHERENCY_TX_FSM9    15
19999 #define V_COHERENCY_TX_FSM9(x) ((x) << S_COHERENCY_TX_FSM9)
20000 #define F_COHERENCY_TX_FSM9    V_COHERENCY_TX_FSM9(1U)
20001 
20002 #define S_COHERENCY_RX_FSM9    14
20003 #define V_COHERENCY_RX_FSM9(x) ((x) << S_COHERENCY_RX_FSM9)
20004 #define F_COHERENCY_RX_FSM9    V_COHERENCY_RX_FSM9(1U)
20005 
20006 #define S_ARB_REQ_FSM9    13
20007 #define V_ARB_REQ_FSM9(x) ((x) << S_ARB_REQ_FSM9)
20008 #define F_ARB_REQ_FSM9    V_ARB_REQ_FSM9(1U)
20009 
20010 #define S_CMD_SPLIT_FSM9    10
20011 #define M_CMD_SPLIT_FSM9    0x7U
20012 #define V_CMD_SPLIT_FSM9(x) ((x) << S_CMD_SPLIT_FSM9)
20013 #define G_CMD_SPLIT_FSM9(x) (((x) >> S_CMD_SPLIT_FSM9) & M_CMD_SPLIT_FSM9)
20014 
20015 #define A_MA_PM_TX_CLIENT_INTERFACE_INTERNAL_REG1 0xe540
20016 
20017 #define S_WR_DATA_EXT_FIFO_CNT10    30
20018 #define M_WR_DATA_EXT_FIFO_CNT10    0x3U
20019 #define V_WR_DATA_EXT_FIFO_CNT10(x) ((x) << S_WR_DATA_EXT_FIFO_CNT10)
20020 #define G_WR_DATA_EXT_FIFO_CNT10(x) (((x) >> S_WR_DATA_EXT_FIFO_CNT10) & M_WR_DATA_EXT_FIFO_CNT10)
20021 
20022 #define S_WR_CMD_TAG_FIFO_CNT10    26
20023 #define M_WR_CMD_TAG_FIFO_CNT10    0xfU
20024 #define V_WR_CMD_TAG_FIFO_CNT10(x) ((x) << S_WR_CMD_TAG_FIFO_CNT10)
20025 #define G_WR_CMD_TAG_FIFO_CNT10(x) (((x) >> S_WR_CMD_TAG_FIFO_CNT10) & M_WR_CMD_TAG_FIFO_CNT10)
20026 
20027 #define S_WR_DATA_512B_FIFO_CNT10    18
20028 #define M_WR_DATA_512B_FIFO_CNT10    0xffU
20029 #define V_WR_DATA_512B_FIFO_CNT10(x) ((x) << S_WR_DATA_512B_FIFO_CNT10)
20030 #define G_WR_DATA_512B_FIFO_CNT10(x) (((x) >> S_WR_DATA_512B_FIFO_CNT10) & M_WR_DATA_512B_FIFO_CNT10)
20031 
20032 #define S_RD_DATA_ALIGN_FSM10    17
20033 #define V_RD_DATA_ALIGN_FSM10(x) ((x) << S_RD_DATA_ALIGN_FSM10)
20034 #define F_RD_DATA_ALIGN_FSM10    V_RD_DATA_ALIGN_FSM10(1U)
20035 
20036 #define S_RD_DATA_FETCH_FSM10    16
20037 #define V_RD_DATA_FETCH_FSM10(x) ((x) << S_RD_DATA_FETCH_FSM10)
20038 #define F_RD_DATA_FETCH_FSM10    V_RD_DATA_FETCH_FSM10(1U)
20039 
20040 #define S_COHERENCY_TX_FSM10    15
20041 #define V_COHERENCY_TX_FSM10(x) ((x) << S_COHERENCY_TX_FSM10)
20042 #define F_COHERENCY_TX_FSM10    V_COHERENCY_TX_FSM10(1U)
20043 
20044 #define S_COHERENCY_RX_FSM10    14
20045 #define V_COHERENCY_RX_FSM10(x) ((x) << S_COHERENCY_RX_FSM10)
20046 #define F_COHERENCY_RX_FSM10    V_COHERENCY_RX_FSM10(1U)
20047 
20048 #define S_ARB_REQ_FSM10    13
20049 #define V_ARB_REQ_FSM10(x) ((x) << S_ARB_REQ_FSM10)
20050 #define F_ARB_REQ_FSM10    V_ARB_REQ_FSM10(1U)
20051 
20052 #define S_CMD_SPLIT_FSM10    10
20053 #define M_CMD_SPLIT_FSM10    0x7U
20054 #define V_CMD_SPLIT_FSM10(x) ((x) << S_CMD_SPLIT_FSM10)
20055 #define G_CMD_SPLIT_FSM10(x) (((x) >> S_CMD_SPLIT_FSM10) & M_CMD_SPLIT_FSM10)
20056 
20057 #define A_MA_PM_RX_CLIENT_INTERFACE_INTERNAL_REG1 0xe560
20058 
20059 #define S_WR_DATA_EXT_FIFO_CNT11    30
20060 #define M_WR_DATA_EXT_FIFO_CNT11    0x3U
20061 #define V_WR_DATA_EXT_FIFO_CNT11(x) ((x) << S_WR_DATA_EXT_FIFO_CNT11)
20062 #define G_WR_DATA_EXT_FIFO_CNT11(x) (((x) >> S_WR_DATA_EXT_FIFO_CNT11) & M_WR_DATA_EXT_FIFO_CNT11)
20063 
20064 #define S_WR_CMD_TAG_FIFO_CNT11    26
20065 #define M_WR_CMD_TAG_FIFO_CNT11    0xfU
20066 #define V_WR_CMD_TAG_FIFO_CNT11(x) ((x) << S_WR_CMD_TAG_FIFO_CNT11)
20067 #define G_WR_CMD_TAG_FIFO_CNT11(x) (((x) >> S_WR_CMD_TAG_FIFO_CNT11) & M_WR_CMD_TAG_FIFO_CNT11)
20068 
20069 #define S_WR_DATA_512B_FIFO_CNT11    18
20070 #define M_WR_DATA_512B_FIFO_CNT11    0xffU
20071 #define V_WR_DATA_512B_FIFO_CNT11(x) ((x) << S_WR_DATA_512B_FIFO_CNT11)
20072 #define G_WR_DATA_512B_FIFO_CNT11(x) (((x) >> S_WR_DATA_512B_FIFO_CNT11) & M_WR_DATA_512B_FIFO_CNT11)
20073 
20074 #define S_RD_DATA_ALIGN_FSM11    17
20075 #define V_RD_DATA_ALIGN_FSM11(x) ((x) << S_RD_DATA_ALIGN_FSM11)
20076 #define F_RD_DATA_ALIGN_FSM11    V_RD_DATA_ALIGN_FSM11(1U)
20077 
20078 #define S_RD_DATA_FETCH_FSM11    16
20079 #define V_RD_DATA_FETCH_FSM11(x) ((x) << S_RD_DATA_FETCH_FSM11)
20080 #define F_RD_DATA_FETCH_FSM11    V_RD_DATA_FETCH_FSM11(1U)
20081 
20082 #define S_COHERENCY_TX_FSM11    15
20083 #define V_COHERENCY_TX_FSM11(x) ((x) << S_COHERENCY_TX_FSM11)
20084 #define F_COHERENCY_TX_FSM11    V_COHERENCY_TX_FSM11(1U)
20085 
20086 #define S_COHERENCY_RX_FSM11    14
20087 #define V_COHERENCY_RX_FSM11(x) ((x) << S_COHERENCY_RX_FSM11)
20088 #define F_COHERENCY_RX_FSM11    V_COHERENCY_RX_FSM11(1U)
20089 
20090 #define S_ARB_REQ_FSM11    13
20091 #define V_ARB_REQ_FSM11(x) ((x) << S_ARB_REQ_FSM11)
20092 #define F_ARB_REQ_FSM11    V_ARB_REQ_FSM11(1U)
20093 
20094 #define S_CMD_SPLIT_FSM11    10
20095 #define M_CMD_SPLIT_FSM11    0x7U
20096 #define V_CMD_SPLIT_FSM11(x) ((x) << S_CMD_SPLIT_FSM11)
20097 #define G_CMD_SPLIT_FSM11(x) (((x) >> S_CMD_SPLIT_FSM11) & M_CMD_SPLIT_FSM11)
20098 
20099 #define A_MA_HMA_CLIENT_INTERFACE_INTERNAL_REG1 0xe580
20100 
20101 #define S_WR_DATA_EXT_FIFO_CNT12    30
20102 #define M_WR_DATA_EXT_FIFO_CNT12    0x3U
20103 #define V_WR_DATA_EXT_FIFO_CNT12(x) ((x) << S_WR_DATA_EXT_FIFO_CNT12)
20104 #define G_WR_DATA_EXT_FIFO_CNT12(x) (((x) >> S_WR_DATA_EXT_FIFO_CNT12) & M_WR_DATA_EXT_FIFO_CNT12)
20105 
20106 #define S_WR_CMD_TAG_FIFO_CNT12    26
20107 #define M_WR_CMD_TAG_FIFO_CNT12    0xfU
20108 #define V_WR_CMD_TAG_FIFO_CNT12(x) ((x) << S_WR_CMD_TAG_FIFO_CNT12)
20109 #define G_WR_CMD_TAG_FIFO_CNT12(x) (((x) >> S_WR_CMD_TAG_FIFO_CNT12) & M_WR_CMD_TAG_FIFO_CNT12)
20110 
20111 #define S_WR_DATA_512B_FIFO_CNT12    18
20112 #define M_WR_DATA_512B_FIFO_CNT12    0xffU
20113 #define V_WR_DATA_512B_FIFO_CNT12(x) ((x) << S_WR_DATA_512B_FIFO_CNT12)
20114 #define G_WR_DATA_512B_FIFO_CNT12(x) (((x) >> S_WR_DATA_512B_FIFO_CNT12) & M_WR_DATA_512B_FIFO_CNT12)
20115 
20116 #define S_RD_DATA_ALIGN_FSM12    17
20117 #define V_RD_DATA_ALIGN_FSM12(x) ((x) << S_RD_DATA_ALIGN_FSM12)
20118 #define F_RD_DATA_ALIGN_FSM12    V_RD_DATA_ALIGN_FSM12(1U)
20119 
20120 #define S_RD_DATA_FETCH_FSM12    16
20121 #define V_RD_DATA_FETCH_FSM12(x) ((x) << S_RD_DATA_FETCH_FSM12)
20122 #define F_RD_DATA_FETCH_FSM12    V_RD_DATA_FETCH_FSM12(1U)
20123 
20124 #define S_COHERENCY_TX_FSM12    15
20125 #define V_COHERENCY_TX_FSM12(x) ((x) << S_COHERENCY_TX_FSM12)
20126 #define F_COHERENCY_TX_FSM12    V_COHERENCY_TX_FSM12(1U)
20127 
20128 #define S_COHERENCY_RX_FSM12    14
20129 #define V_COHERENCY_RX_FSM12(x) ((x) << S_COHERENCY_RX_FSM12)
20130 #define F_COHERENCY_RX_FSM12    V_COHERENCY_RX_FSM12(1U)
20131 
20132 #define S_ARB_REQ_FSM12    13
20133 #define V_ARB_REQ_FSM12(x) ((x) << S_ARB_REQ_FSM12)
20134 #define F_ARB_REQ_FSM12    V_ARB_REQ_FSM12(1U)
20135 
20136 #define S_CMD_SPLIT_FSM12    10
20137 #define M_CMD_SPLIT_FSM12    0x7U
20138 #define V_CMD_SPLIT_FSM12(x) ((x) << S_CMD_SPLIT_FSM12)
20139 #define G_CMD_SPLIT_FSM12(x) (((x) >> S_CMD_SPLIT_FSM12) & M_CMD_SPLIT_FSM12)
20140 
20141 #define A_MA_TARGET_0_ARBITER_INTERFACE_INTERNAL_REG1 0xe5a0
20142 
20143 #define S_RD_CMD_TAG_FIFO_CNT0    8
20144 #define M_RD_CMD_TAG_FIFO_CNT0    0xffU
20145 #define V_RD_CMD_TAG_FIFO_CNT0(x) ((x) << S_RD_CMD_TAG_FIFO_CNT0)
20146 #define G_RD_CMD_TAG_FIFO_CNT0(x) (((x) >> S_RD_CMD_TAG_FIFO_CNT0) & M_RD_CMD_TAG_FIFO_CNT0)
20147 
20148 #define S_RD_DATA_FIFO_CNT0    0
20149 #define M_RD_DATA_FIFO_CNT0    0xffU
20150 #define V_RD_DATA_FIFO_CNT0(x) ((x) << S_RD_DATA_FIFO_CNT0)
20151 #define G_RD_DATA_FIFO_CNT0(x) (((x) >> S_RD_DATA_FIFO_CNT0) & M_RD_DATA_FIFO_CNT0)
20152 
20153 #define A_MA_TARGET_1_ARBITER_INTERFACE_INTERNAL_REG1 0xe5c0
20154 
20155 #define S_RD_CMD_TAG_FIFO_CNT1    8
20156 #define M_RD_CMD_TAG_FIFO_CNT1    0xffU
20157 #define V_RD_CMD_TAG_FIFO_CNT1(x) ((x) << S_RD_CMD_TAG_FIFO_CNT1)
20158 #define G_RD_CMD_TAG_FIFO_CNT1(x) (((x) >> S_RD_CMD_TAG_FIFO_CNT1) & M_RD_CMD_TAG_FIFO_CNT1)
20159 
20160 #define S_RD_DATA_FIFO_CNT1    0
20161 #define M_RD_DATA_FIFO_CNT1    0xffU
20162 #define V_RD_DATA_FIFO_CNT1(x) ((x) << S_RD_DATA_FIFO_CNT1)
20163 #define G_RD_DATA_FIFO_CNT1(x) (((x) >> S_RD_DATA_FIFO_CNT1) & M_RD_DATA_FIFO_CNT1)
20164 
20165 #define A_MA_TARGET_2_ARBITER_INTERFACE_INTERNAL_REG1 0xe5e0
20166 
20167 #define S_RD_CMD_TAG_FIFO_CNT2    8
20168 #define M_RD_CMD_TAG_FIFO_CNT2    0xffU
20169 #define V_RD_CMD_TAG_FIFO_CNT2(x) ((x) << S_RD_CMD_TAG_FIFO_CNT2)
20170 #define G_RD_CMD_TAG_FIFO_CNT2(x) (((x) >> S_RD_CMD_TAG_FIFO_CNT2) & M_RD_CMD_TAG_FIFO_CNT2)
20171 
20172 #define S_RD_DATA_FIFO_CNT2    0
20173 #define M_RD_DATA_FIFO_CNT2    0xffU
20174 #define V_RD_DATA_FIFO_CNT2(x) ((x) << S_RD_DATA_FIFO_CNT2)
20175 #define G_RD_DATA_FIFO_CNT2(x) (((x) >> S_RD_DATA_FIFO_CNT2) & M_RD_DATA_FIFO_CNT2)
20176 
20177 #define A_MA_TARGET_3_ARBITER_INTERFACE_INTERNAL_REG1 0xe600
20178 
20179 #define S_RD_CMD_TAG_FIFO_CNT3    8
20180 #define M_RD_CMD_TAG_FIFO_CNT3    0xffU
20181 #define V_RD_CMD_TAG_FIFO_CNT3(x) ((x) << S_RD_CMD_TAG_FIFO_CNT3)
20182 #define G_RD_CMD_TAG_FIFO_CNT3(x) (((x) >> S_RD_CMD_TAG_FIFO_CNT3) & M_RD_CMD_TAG_FIFO_CNT3)
20183 
20184 #define S_RD_DATA_FIFO_CNT3    0
20185 #define M_RD_DATA_FIFO_CNT3    0xffU
20186 #define V_RD_DATA_FIFO_CNT3(x) ((x) << S_RD_DATA_FIFO_CNT3)
20187 #define G_RD_DATA_FIFO_CNT3(x) (((x) >> S_RD_DATA_FIFO_CNT3) & M_RD_DATA_FIFO_CNT3)
20188 
20189 #define A_MA_SGE_THREAD_0_CLNT_EXP_WR_CYC_CNT_LO 0xe640
20190 #define A_MA_SGE_THREAD_1_CLNT_EXP_WR_CYC_CNT_LO 0xe660
20191 #define A_MA_ULP_TX_CLNT_EXP_WR_CYC_CNT_LO 0xe680
20192 #define A_MA_ULP_RX_CLNT_EXP_WR_CYC_CNT_LO 0xe6a0
20193 #define A_MA_ULP_TX_RX_CLNT_EXP_WR_CYC_CNT_LO 0xe6c0
20194 #define A_MA_TP_THREAD_0_CLNT_EXP_WR_CYC_CNT_LO 0xe6e0
20195 #define A_MA_TP_THREAD_1_CLNT_EXP_WR_CYC_CNT_LO 0xe700
20196 #define A_MA_LE_CLNT_EXP_WR_CYC_CNT_LO 0xe720
20197 #define A_MA_CIM_CLNT_EXP_WR_CYC_CNT_LO 0xe740
20198 #define A_MA_PCIE_CLNT_EXP_WR_CYC_CNT_LO 0xe760
20199 #define A_MA_PM_TX_CLNT_EXP_WR_CYC_CNT_LO 0xe780
20200 #define A_MA_PM_RX_CLNT_EXP_WR_CYC_CNT_LO 0xe7a0
20201 #define A_MA_HMA_CLNT_EXP_WR_CYC_CNT_LO 0xe7c0
20202 #define A_MA_EDRAM0_WR_REQ_CNT_HI 0xe800
20203 #define A_MA_EDRAM0_WR_REQ_CNT_LO 0xe820
20204 #define A_MA_EDRAM1_WR_REQ_CNT_HI 0xe840
20205 #define A_MA_EDRAM1_WR_REQ_CNT_LO 0xe860
20206 #define A_MA_EXT_MEMORY0_WR_REQ_CNT_HI 0xe880
20207 #define A_MA_EXT_MEMORY0_WR_REQ_CNT_LO 0xe8a0
20208 #define A_MA_EXT_MEMORY1_WR_REQ_CNT_HI 0xe8c0
20209 #define A_MA_EXT_MEMORY1_WR_REQ_CNT_LO 0xe8e0
20210 #define A_MA_EDRAM0_RD_REQ_CNT_HI 0xe900
20211 #define A_MA_EDRAM0_RD_REQ_CNT_LO 0xe920
20212 #define A_MA_EDRAM1_RD_REQ_CNT_HI 0xe940
20213 #define A_MA_EDRAM1_RD_REQ_CNT_LO 0xe960
20214 #define A_MA_EXT_MEMORY0_RD_REQ_CNT_HI 0xe980
20215 #define A_MA_EXT_MEMORY0_RD_REQ_CNT_LO 0xe9a0
20216 #define A_MA_EXT_MEMORY1_RD_REQ_CNT_HI 0xe9c0
20217 #define A_MA_EXT_MEMORY1_RD_REQ_CNT_LO 0xe9e0
20218 #define A_MA_SGE_THREAD_0_CLNT_ACT_RD_CYC_CNT_HI 0xec00
20219 #define A_MA_SGE_THREAD_0_CLNT_ACT_RD_CYC_CNT_LO 0xec20
20220 #define A_MA_SGE_THREAD_1_CLNT_ACT_RD_CYC_CNT_HI 0xec40
20221 #define A_MA_SGE_THREAD_1_CLNT_ACT_RD_CYC_CNT_LO 0xec60
20222 #define A_MA_ULP_TX_CLNT_ACT_RD_CYC_CNT_HI 0xec80
20223 #define A_MA_ULP_TX_CLNT_ACT_RD_CYC_CNT_LO 0xeca0
20224 #define A_MA_ULP_RX_CLNT_ACT_RD_CYC_CNT_HI 0xecc0
20225 #define A_MA_ULP_RX_CLNT_ACT_RD_CYC_CNT_LO 0xece0
20226 #define A_MA_ULP_TX_RX_CLNT_ACT_RD_CYC_CNT_HI 0xed00
20227 #define A_MA_ULP_TX_RX_CLNT_ACT_RD_CYC_CNT_LO 0xed20
20228 #define A_MA_TP_THREAD_0_CLNT_ACT_RD_CYC_CNT_HI 0xed40
20229 #define A_MA_TP_THREAD_0_CLNT_ACT_RD_CYC_CNT_LO 0xed60
20230 #define A_MA_TP_THREAD_1_CLNT_ACT_RD_CYC_CNT_HI 0xed80
20231 #define A_MA_TP_THREAD_1_CLNT_ACT_RD_CYC_CNT_LO 0xeda0
20232 #define A_MA_LE_CLNT_ACT_RD_CYC_CNT_HI 0xedc0
20233 #define A_MA_LE_CLNT_ACT_RD_CYC_CNT_LO 0xede0
20234 #define A_MA_CIM_CLNT_ACT_RD_CYC_CNT_HI 0xee00
20235 #define A_MA_CIM_CLNT_ACT_RD_CYC_CNT_LO 0xee20
20236 #define A_MA_PCIE_CLNT_ACT_RD_CYC_CNT_HI 0xee40
20237 #define A_MA_PCIE_CLNT_ACT_RD_CYC_CNT_LO 0xee60
20238 #define A_MA_PM_TX_CLNT_ACT_RD_CYC_CNT_HI 0xee80
20239 #define A_MA_PM_TX_CLNT_ACT_RD_CYC_CNT_LO 0xeea0
20240 #define A_MA_PM_RX_CLNT_ACT_RD_CYC_CNT_HI 0xeec0
20241 #define A_MA_PM_RX_CLNT_ACT_RD_CYC_CNT_LO 0xeee0
20242 #define A_MA_HMA_CLNT_ACT_RD_CYC_CNT_HI 0xef00
20243 #define A_MA_HMA_CLNT_ACT_RD_CYC_CNT_LO 0xef20
20244 #define A_MA_PM_TX_RD_THROTTLE_STATUS 0xf000
20245 
20246 #define S_PTMAXTRANS    16
20247 #define V_PTMAXTRANS(x) ((x) << S_PTMAXTRANS)
20248 #define F_PTMAXTRANS    V_PTMAXTRANS(1U)
20249 
20250 #define S_PTFLITCNT    0
20251 #define M_PTFLITCNT    0xffU
20252 #define V_PTFLITCNT(x) ((x) << S_PTFLITCNT)
20253 #define G_PTFLITCNT(x) (((x) >> S_PTFLITCNT) & M_PTFLITCNT)
20254 
20255 #define A_MA_PM_RX_RD_THROTTLE_STATUS 0xf020
20256 
20257 #define S_PRMAXTRANS    16
20258 #define V_PRMAXTRANS(x) ((x) << S_PRMAXTRANS)
20259 #define F_PRMAXTRANS    V_PRMAXTRANS(1U)
20260 
20261 #define S_PRFLITCNT    0
20262 #define M_PRFLITCNT    0xffU
20263 #define V_PRFLITCNT(x) ((x) << S_PRFLITCNT)
20264 #define G_PRFLITCNT(x) (((x) >> S_PRFLITCNT) & M_PRFLITCNT)
20265 
20266 /* registers for module EDC_0 */
20267 #define EDC_0_BASE_ADDR 0x7900
20268 
20269 #define A_EDC_REF 0x7900
20270 
20271 #define S_EDC_INST_NUM    18
20272 #define V_EDC_INST_NUM(x) ((x) << S_EDC_INST_NUM)
20273 #define F_EDC_INST_NUM    V_EDC_INST_NUM(1U)
20274 
20275 #define S_ENABLE_PERF    17
20276 #define V_ENABLE_PERF(x) ((x) << S_ENABLE_PERF)
20277 #define F_ENABLE_PERF    V_ENABLE_PERF(1U)
20278 
20279 #define S_ECC_BYPASS    16
20280 #define V_ECC_BYPASS(x) ((x) << S_ECC_BYPASS)
20281 #define F_ECC_BYPASS    V_ECC_BYPASS(1U)
20282 
20283 #define S_REFFREQ    0
20284 #define M_REFFREQ    0xffffU
20285 #define V_REFFREQ(x) ((x) << S_REFFREQ)
20286 #define G_REFFREQ(x) (((x) >> S_REFFREQ) & M_REFFREQ)
20287 
20288 #define A_EDC_BIST_CMD 0x7904
20289 #define A_EDC_BIST_CMD_ADDR 0x7908
20290 #define A_EDC_BIST_CMD_LEN 0x790c
20291 #define A_EDC_BIST_DATA_PATTERN 0x7910
20292 #define A_EDC_BIST_USER_WDATA0 0x7914
20293 #define A_EDC_BIST_USER_WDATA1 0x7918
20294 #define A_EDC_BIST_USER_WDATA2 0x791c
20295 #define A_EDC_BIST_NUM_ERR 0x7920
20296 #define A_EDC_BIST_ERR_FIRST_ADDR 0x7924
20297 #define A_EDC_BIST_STATUS_RDATA 0x7928
20298 #define A_EDC_PAR_ENABLE 0x7970
20299 
20300 #define S_ECC_UE    2
20301 #define V_ECC_UE(x) ((x) << S_ECC_UE)
20302 #define F_ECC_UE    V_ECC_UE(1U)
20303 
20304 #define S_ECC_CE    1
20305 #define V_ECC_CE(x) ((x) << S_ECC_CE)
20306 #define F_ECC_CE    V_ECC_CE(1U)
20307 
20308 #define A_EDC_INT_ENABLE 0x7974
20309 #define A_EDC_INT_CAUSE 0x7978
20310 
20311 #define S_ECC_UE_PAR    5
20312 #define V_ECC_UE_PAR(x) ((x) << S_ECC_UE_PAR)
20313 #define F_ECC_UE_PAR    V_ECC_UE_PAR(1U)
20314 
20315 #define S_ECC_CE_PAR    4
20316 #define V_ECC_CE_PAR(x) ((x) << S_ECC_CE_PAR)
20317 #define F_ECC_CE_PAR    V_ECC_CE_PAR(1U)
20318 
20319 #define S_PERR_PAR_CAUSE    3
20320 #define V_PERR_PAR_CAUSE(x) ((x) << S_PERR_PAR_CAUSE)
20321 #define F_PERR_PAR_CAUSE    V_PERR_PAR_CAUSE(1U)
20322 
20323 #define A_EDC_ECC_STATUS 0x797c
20324 
20325 /* registers for module EDC_1 */
20326 #define EDC_1_BASE_ADDR 0x7980
20327 
20328 /* registers for module HMA */
20329 #define HMA_BASE_ADDR 0x7a00
20330 
20331 /* registers for module CIM */
20332 #define CIM_BASE_ADDR 0x7b00
20333 
20334 #define A_CIM_VF_EXT_MAILBOX_CTRL 0x0
20335 
20336 #define S_VFMBGENERIC    4
20337 #define M_VFMBGENERIC    0xfU
20338 #define V_VFMBGENERIC(x) ((x) << S_VFMBGENERIC)
20339 #define G_VFMBGENERIC(x) (((x) >> S_VFMBGENERIC) & M_VFMBGENERIC)
20340 
20341 #define A_CIM_VF_EXT_MAILBOX_STATUS 0x4
20342 
20343 #define S_MBVFREADY    0
20344 #define V_MBVFREADY(x) ((x) << S_MBVFREADY)
20345 #define F_MBVFREADY    V_MBVFREADY(1U)
20346 
20347 #define A_CIM_PF_MAILBOX_DATA 0x240
20348 #define A_CIM_PF_MAILBOX_CTRL 0x280
20349 
20350 #define S_MBGENERIC    4
20351 #define M_MBGENERIC    0xfffffffU
20352 #define V_MBGENERIC(x) ((x) << S_MBGENERIC)
20353 #define G_MBGENERIC(x) (((x) >> S_MBGENERIC) & M_MBGENERIC)
20354 
20355 #define S_MBMSGVALID    3
20356 #define V_MBMSGVALID(x) ((x) << S_MBMSGVALID)
20357 #define F_MBMSGVALID    V_MBMSGVALID(1U)
20358 
20359 #define S_MBINTREQ    2
20360 #define V_MBINTREQ(x) ((x) << S_MBINTREQ)
20361 #define F_MBINTREQ    V_MBINTREQ(1U)
20362 
20363 #define S_MBOWNER    0
20364 #define M_MBOWNER    0x3U
20365 #define V_MBOWNER(x) ((x) << S_MBOWNER)
20366 #define G_MBOWNER(x) (((x) >> S_MBOWNER) & M_MBOWNER)
20367 
20368 #define A_CIM_PF_MAILBOX_ACC_STATUS 0x284
20369 
20370 #define S_MBWRBUSY    31
20371 #define V_MBWRBUSY(x) ((x) << S_MBWRBUSY)
20372 #define F_MBWRBUSY    V_MBWRBUSY(1U)
20373 
20374 #define A_CIM_PF_HOST_INT_ENABLE 0x288
20375 
20376 #define S_MBMSGRDYINTEN    19
20377 #define V_MBMSGRDYINTEN(x) ((x) << S_MBMSGRDYINTEN)
20378 #define F_MBMSGRDYINTEN    V_MBMSGRDYINTEN(1U)
20379 
20380 #define A_CIM_PF_HOST_INT_CAUSE 0x28c
20381 
20382 #define S_MBMSGRDYINT    19
20383 #define V_MBMSGRDYINT(x) ((x) << S_MBMSGRDYINT)
20384 #define F_MBMSGRDYINT    V_MBMSGRDYINT(1U)
20385 
20386 #define A_CIM_PF_MAILBOX_CTRL_SHADOW_COPY 0x290
20387 #define A_CIM_BOOT_CFG 0x7b00
20388 
20389 #define S_BOOTADDR    8
20390 #define M_BOOTADDR    0xffffffU
20391 #define V_BOOTADDR(x) ((x) << S_BOOTADDR)
20392 #define G_BOOTADDR(x) (((x) >> S_BOOTADDR) & M_BOOTADDR)
20393 
20394 #define S_UPGEN    2
20395 #define M_UPGEN    0x3fU
20396 #define V_UPGEN(x) ((x) << S_UPGEN)
20397 #define G_UPGEN(x) (((x) >> S_UPGEN) & M_UPGEN)
20398 
20399 #define S_BOOTSDRAM    1
20400 #define V_BOOTSDRAM(x) ((x) << S_BOOTSDRAM)
20401 #define F_BOOTSDRAM    V_BOOTSDRAM(1U)
20402 
20403 #define S_UPCRST    0
20404 #define V_UPCRST(x) ((x) << S_UPCRST)
20405 #define F_UPCRST    V_UPCRST(1U)
20406 
20407 #define A_CIM_FLASH_BASE_ADDR 0x7b04
20408 
20409 #define S_FLASHBASEADDR    6
20410 #define M_FLASHBASEADDR    0x3ffffU
20411 #define V_FLASHBASEADDR(x) ((x) << S_FLASHBASEADDR)
20412 #define G_FLASHBASEADDR(x) (((x) >> S_FLASHBASEADDR) & M_FLASHBASEADDR)
20413 
20414 #define A_CIM_FLASH_ADDR_SIZE 0x7b08
20415 
20416 #define S_FLASHADDRSIZE    4
20417 #define M_FLASHADDRSIZE    0xfffffU
20418 #define V_FLASHADDRSIZE(x) ((x) << S_FLASHADDRSIZE)
20419 #define G_FLASHADDRSIZE(x) (((x) >> S_FLASHADDRSIZE) & M_FLASHADDRSIZE)
20420 
20421 #define A_CIM_EEPROM_BASE_ADDR 0x7b0c
20422 
20423 #define S_EEPROMBASEADDR    6
20424 #define M_EEPROMBASEADDR    0x3ffffU
20425 #define V_EEPROMBASEADDR(x) ((x) << S_EEPROMBASEADDR)
20426 #define G_EEPROMBASEADDR(x) (((x) >> S_EEPROMBASEADDR) & M_EEPROMBASEADDR)
20427 
20428 #define A_CIM_EEPROM_ADDR_SIZE 0x7b10
20429 
20430 #define S_EEPROMADDRSIZE    4
20431 #define M_EEPROMADDRSIZE    0xfffffU
20432 #define V_EEPROMADDRSIZE(x) ((x) << S_EEPROMADDRSIZE)
20433 #define G_EEPROMADDRSIZE(x) (((x) >> S_EEPROMADDRSIZE) & M_EEPROMADDRSIZE)
20434 
20435 #define A_CIM_SDRAM_BASE_ADDR 0x7b14
20436 
20437 #define S_SDRAMBASEADDR    6
20438 #define M_SDRAMBASEADDR    0x3ffffffU
20439 #define V_SDRAMBASEADDR(x) ((x) << S_SDRAMBASEADDR)
20440 #define G_SDRAMBASEADDR(x) (((x) >> S_SDRAMBASEADDR) & M_SDRAMBASEADDR)
20441 
20442 #define A_CIM_SDRAM_ADDR_SIZE 0x7b18
20443 
20444 #define S_SDRAMADDRSIZE    4
20445 #define M_SDRAMADDRSIZE    0xfffffffU
20446 #define V_SDRAMADDRSIZE(x) ((x) << S_SDRAMADDRSIZE)
20447 #define G_SDRAMADDRSIZE(x) (((x) >> S_SDRAMADDRSIZE) & M_SDRAMADDRSIZE)
20448 
20449 #define A_CIM_EXTMEM2_BASE_ADDR 0x7b1c
20450 
20451 #define S_EXTMEM2BASEADDR    6
20452 #define M_EXTMEM2BASEADDR    0x3ffffffU
20453 #define V_EXTMEM2BASEADDR(x) ((x) << S_EXTMEM2BASEADDR)
20454 #define G_EXTMEM2BASEADDR(x) (((x) >> S_EXTMEM2BASEADDR) & M_EXTMEM2BASEADDR)
20455 
20456 #define A_CIM_EXTMEM2_ADDR_SIZE 0x7b20
20457 
20458 #define S_EXTMEM2ADDRSIZE    4
20459 #define M_EXTMEM2ADDRSIZE    0xfffffffU
20460 #define V_EXTMEM2ADDRSIZE(x) ((x) << S_EXTMEM2ADDRSIZE)
20461 #define G_EXTMEM2ADDRSIZE(x) (((x) >> S_EXTMEM2ADDRSIZE) & M_EXTMEM2ADDRSIZE)
20462 
20463 #define A_CIM_UP_SPARE_INT 0x7b24
20464 
20465 #define S_TDEBUGINT    4
20466 #define V_TDEBUGINT(x) ((x) << S_TDEBUGINT)
20467 #define F_TDEBUGINT    V_TDEBUGINT(1U)
20468 
20469 #define S_BOOTVECSEL    3
20470 #define V_BOOTVECSEL(x) ((x) << S_BOOTVECSEL)
20471 #define F_BOOTVECSEL    V_BOOTVECSEL(1U)
20472 
20473 #define S_UPSPAREINT    0
20474 #define M_UPSPAREINT    0x7U
20475 #define V_UPSPAREINT(x) ((x) << S_UPSPAREINT)
20476 #define G_UPSPAREINT(x) (((x) >> S_UPSPAREINT) & M_UPSPAREINT)
20477 
20478 #define A_CIM_HOST_INT_ENABLE 0x7b28
20479 
20480 #define S_TIEQOUTPARERRINTEN    20
20481 #define V_TIEQOUTPARERRINTEN(x) ((x) << S_TIEQOUTPARERRINTEN)
20482 #define F_TIEQOUTPARERRINTEN    V_TIEQOUTPARERRINTEN(1U)
20483 
20484 #define S_TIEQINPARERRINTEN    19
20485 #define V_TIEQINPARERRINTEN(x) ((x) << S_TIEQINPARERRINTEN)
20486 #define F_TIEQINPARERRINTEN    V_TIEQINPARERRINTEN(1U)
20487 
20488 #define S_MBHOSTPARERR    18
20489 #define V_MBHOSTPARERR(x) ((x) << S_MBHOSTPARERR)
20490 #define F_MBHOSTPARERR    V_MBHOSTPARERR(1U)
20491 
20492 #define S_MBUPPARERR    17
20493 #define V_MBUPPARERR(x) ((x) << S_MBUPPARERR)
20494 #define F_MBUPPARERR    V_MBUPPARERR(1U)
20495 
20496 #define S_IBQTP0PARERR    16
20497 #define V_IBQTP0PARERR(x) ((x) << S_IBQTP0PARERR)
20498 #define F_IBQTP0PARERR    V_IBQTP0PARERR(1U)
20499 
20500 #define S_IBQTP1PARERR    15
20501 #define V_IBQTP1PARERR(x) ((x) << S_IBQTP1PARERR)
20502 #define F_IBQTP1PARERR    V_IBQTP1PARERR(1U)
20503 
20504 #define S_IBQULPPARERR    14
20505 #define V_IBQULPPARERR(x) ((x) << S_IBQULPPARERR)
20506 #define F_IBQULPPARERR    V_IBQULPPARERR(1U)
20507 
20508 #define S_IBQSGELOPARERR    13
20509 #define V_IBQSGELOPARERR(x) ((x) << S_IBQSGELOPARERR)
20510 #define F_IBQSGELOPARERR    V_IBQSGELOPARERR(1U)
20511 
20512 #define S_IBQSGEHIPARERR    12
20513 #define V_IBQSGEHIPARERR(x) ((x) << S_IBQSGEHIPARERR)
20514 #define F_IBQSGEHIPARERR    V_IBQSGEHIPARERR(1U)
20515 
20516 #define S_IBQNCSIPARERR    11
20517 #define V_IBQNCSIPARERR(x) ((x) << S_IBQNCSIPARERR)
20518 #define F_IBQNCSIPARERR    V_IBQNCSIPARERR(1U)
20519 
20520 #define S_OBQULP0PARERR    10
20521 #define V_OBQULP0PARERR(x) ((x) << S_OBQULP0PARERR)
20522 #define F_OBQULP0PARERR    V_OBQULP0PARERR(1U)
20523 
20524 #define S_OBQULP1PARERR    9
20525 #define V_OBQULP1PARERR(x) ((x) << S_OBQULP1PARERR)
20526 #define F_OBQULP1PARERR    V_OBQULP1PARERR(1U)
20527 
20528 #define S_OBQULP2PARERR    8
20529 #define V_OBQULP2PARERR(x) ((x) << S_OBQULP2PARERR)
20530 #define F_OBQULP2PARERR    V_OBQULP2PARERR(1U)
20531 
20532 #define S_OBQULP3PARERR    7
20533 #define V_OBQULP3PARERR(x) ((x) << S_OBQULP3PARERR)
20534 #define F_OBQULP3PARERR    V_OBQULP3PARERR(1U)
20535 
20536 #define S_OBQSGEPARERR    6
20537 #define V_OBQSGEPARERR(x) ((x) << S_OBQSGEPARERR)
20538 #define F_OBQSGEPARERR    V_OBQSGEPARERR(1U)
20539 
20540 #define S_OBQNCSIPARERR    5
20541 #define V_OBQNCSIPARERR(x) ((x) << S_OBQNCSIPARERR)
20542 #define F_OBQNCSIPARERR    V_OBQNCSIPARERR(1U)
20543 
20544 #define S_TIMER1INTEN    3
20545 #define V_TIMER1INTEN(x) ((x) << S_TIMER1INTEN)
20546 #define F_TIMER1INTEN    V_TIMER1INTEN(1U)
20547 
20548 #define S_TIMER0INTEN    2
20549 #define V_TIMER0INTEN(x) ((x) << S_TIMER0INTEN)
20550 #define F_TIMER0INTEN    V_TIMER0INTEN(1U)
20551 
20552 #define S_PREFDROPINTEN    1
20553 #define V_PREFDROPINTEN(x) ((x) << S_PREFDROPINTEN)
20554 #define F_PREFDROPINTEN    V_PREFDROPINTEN(1U)
20555 
20556 #define S_MA_CIM_INTFPERR    28
20557 #define V_MA_CIM_INTFPERR(x) ((x) << S_MA_CIM_INTFPERR)
20558 #define F_MA_CIM_INTFPERR    V_MA_CIM_INTFPERR(1U)
20559 
20560 #define S_PLCIM_MSTRSPDATAPARERR    27
20561 #define V_PLCIM_MSTRSPDATAPARERR(x) ((x) << S_PLCIM_MSTRSPDATAPARERR)
20562 #define F_PLCIM_MSTRSPDATAPARERR    V_PLCIM_MSTRSPDATAPARERR(1U)
20563 
20564 #define S_NCSI2CIMINTFPARERR    26
20565 #define V_NCSI2CIMINTFPARERR(x) ((x) << S_NCSI2CIMINTFPARERR)
20566 #define F_NCSI2CIMINTFPARERR    V_NCSI2CIMINTFPARERR(1U)
20567 
20568 #define S_SGE2CIMINTFPARERR    25
20569 #define V_SGE2CIMINTFPARERR(x) ((x) << S_SGE2CIMINTFPARERR)
20570 #define F_SGE2CIMINTFPARERR    V_SGE2CIMINTFPARERR(1U)
20571 
20572 #define S_ULP2CIMINTFPARERR    24
20573 #define V_ULP2CIMINTFPARERR(x) ((x) << S_ULP2CIMINTFPARERR)
20574 #define F_ULP2CIMINTFPARERR    V_ULP2CIMINTFPARERR(1U)
20575 
20576 #define S_TP2CIMINTFPARERR    23
20577 #define V_TP2CIMINTFPARERR(x) ((x) << S_TP2CIMINTFPARERR)
20578 #define F_TP2CIMINTFPARERR    V_TP2CIMINTFPARERR(1U)
20579 
20580 #define S_OBQSGERX1PARERR    22
20581 #define V_OBQSGERX1PARERR(x) ((x) << S_OBQSGERX1PARERR)
20582 #define F_OBQSGERX1PARERR    V_OBQSGERX1PARERR(1U)
20583 
20584 #define S_OBQSGERX0PARERR    21
20585 #define V_OBQSGERX0PARERR(x) ((x) << S_OBQSGERX0PARERR)
20586 #define F_OBQSGERX0PARERR    V_OBQSGERX0PARERR(1U)
20587 
20588 #define S_PCIE2CIMINTFPARERR    29
20589 #define V_PCIE2CIMINTFPARERR(x) ((x) << S_PCIE2CIMINTFPARERR)
20590 #define F_PCIE2CIMINTFPARERR    V_PCIE2CIMINTFPARERR(1U)
20591 
20592 #define S_IBQPCIEPARERR    12
20593 #define V_IBQPCIEPARERR(x) ((x) << S_IBQPCIEPARERR)
20594 #define F_IBQPCIEPARERR    V_IBQPCIEPARERR(1U)
20595 
20596 #define A_CIM_HOST_INT_CAUSE 0x7b2c
20597 
20598 #define S_TIEQOUTPARERRINT    20
20599 #define V_TIEQOUTPARERRINT(x) ((x) << S_TIEQOUTPARERRINT)
20600 #define F_TIEQOUTPARERRINT    V_TIEQOUTPARERRINT(1U)
20601 
20602 #define S_TIEQINPARERRINT    19
20603 #define V_TIEQINPARERRINT(x) ((x) << S_TIEQINPARERRINT)
20604 #define F_TIEQINPARERRINT    V_TIEQINPARERRINT(1U)
20605 
20606 #define S_TIMER1INT    3
20607 #define V_TIMER1INT(x) ((x) << S_TIMER1INT)
20608 #define F_TIMER1INT    V_TIMER1INT(1U)
20609 
20610 #define S_TIMER0INT    2
20611 #define V_TIMER0INT(x) ((x) << S_TIMER0INT)
20612 #define F_TIMER0INT    V_TIMER0INT(1U)
20613 
20614 #define S_PREFDROPINT    1
20615 #define V_PREFDROPINT(x) ((x) << S_PREFDROPINT)
20616 #define F_PREFDROPINT    V_PREFDROPINT(1U)
20617 
20618 #define S_UPACCNONZERO    0
20619 #define V_UPACCNONZERO(x) ((x) << S_UPACCNONZERO)
20620 #define F_UPACCNONZERO    V_UPACCNONZERO(1U)
20621 
20622 #define A_CIM_HOST_UPACC_INT_ENABLE 0x7b30
20623 
20624 #define S_EEPROMWRINTEN    30
20625 #define V_EEPROMWRINTEN(x) ((x) << S_EEPROMWRINTEN)
20626 #define F_EEPROMWRINTEN    V_EEPROMWRINTEN(1U)
20627 
20628 #define S_TIMEOUTMAINTEN    29
20629 #define V_TIMEOUTMAINTEN(x) ((x) << S_TIMEOUTMAINTEN)
20630 #define F_TIMEOUTMAINTEN    V_TIMEOUTMAINTEN(1U)
20631 
20632 #define S_TIMEOUTINTEN    28
20633 #define V_TIMEOUTINTEN(x) ((x) << S_TIMEOUTINTEN)
20634 #define F_TIMEOUTINTEN    V_TIMEOUTINTEN(1U)
20635 
20636 #define S_RSPOVRLOOKUPINTEN    27
20637 #define V_RSPOVRLOOKUPINTEN(x) ((x) << S_RSPOVRLOOKUPINTEN)
20638 #define F_RSPOVRLOOKUPINTEN    V_RSPOVRLOOKUPINTEN(1U)
20639 
20640 #define S_REQOVRLOOKUPINTEN    26
20641 #define V_REQOVRLOOKUPINTEN(x) ((x) << S_REQOVRLOOKUPINTEN)
20642 #define F_REQOVRLOOKUPINTEN    V_REQOVRLOOKUPINTEN(1U)
20643 
20644 #define S_BLKWRPLINTEN    25
20645 #define V_BLKWRPLINTEN(x) ((x) << S_BLKWRPLINTEN)
20646 #define F_BLKWRPLINTEN    V_BLKWRPLINTEN(1U)
20647 
20648 #define S_BLKRDPLINTEN    24
20649 #define V_BLKRDPLINTEN(x) ((x) << S_BLKRDPLINTEN)
20650 #define F_BLKRDPLINTEN    V_BLKRDPLINTEN(1U)
20651 
20652 #define S_SGLWRPLINTEN    23
20653 #define V_SGLWRPLINTEN(x) ((x) << S_SGLWRPLINTEN)
20654 #define F_SGLWRPLINTEN    V_SGLWRPLINTEN(1U)
20655 
20656 #define S_SGLRDPLINTEN    22
20657 #define V_SGLRDPLINTEN(x) ((x) << S_SGLRDPLINTEN)
20658 #define F_SGLRDPLINTEN    V_SGLRDPLINTEN(1U)
20659 
20660 #define S_BLKWRCTLINTEN    21
20661 #define V_BLKWRCTLINTEN(x) ((x) << S_BLKWRCTLINTEN)
20662 #define F_BLKWRCTLINTEN    V_BLKWRCTLINTEN(1U)
20663 
20664 #define S_BLKRDCTLINTEN    20
20665 #define V_BLKRDCTLINTEN(x) ((x) << S_BLKRDCTLINTEN)
20666 #define F_BLKRDCTLINTEN    V_BLKRDCTLINTEN(1U)
20667 
20668 #define S_SGLWRCTLINTEN    19
20669 #define V_SGLWRCTLINTEN(x) ((x) << S_SGLWRCTLINTEN)
20670 #define F_SGLWRCTLINTEN    V_SGLWRCTLINTEN(1U)
20671 
20672 #define S_SGLRDCTLINTEN    18
20673 #define V_SGLRDCTLINTEN(x) ((x) << S_SGLRDCTLINTEN)
20674 #define F_SGLRDCTLINTEN    V_SGLRDCTLINTEN(1U)
20675 
20676 #define S_BLKWREEPROMINTEN    17
20677 #define V_BLKWREEPROMINTEN(x) ((x) << S_BLKWREEPROMINTEN)
20678 #define F_BLKWREEPROMINTEN    V_BLKWREEPROMINTEN(1U)
20679 
20680 #define S_BLKRDEEPROMINTEN    16
20681 #define V_BLKRDEEPROMINTEN(x) ((x) << S_BLKRDEEPROMINTEN)
20682 #define F_BLKRDEEPROMINTEN    V_BLKRDEEPROMINTEN(1U)
20683 
20684 #define S_SGLWREEPROMINTEN    15
20685 #define V_SGLWREEPROMINTEN(x) ((x) << S_SGLWREEPROMINTEN)
20686 #define F_SGLWREEPROMINTEN    V_SGLWREEPROMINTEN(1U)
20687 
20688 #define S_SGLRDEEPROMINTEN    14
20689 #define V_SGLRDEEPROMINTEN(x) ((x) << S_SGLRDEEPROMINTEN)
20690 #define F_SGLRDEEPROMINTEN    V_SGLRDEEPROMINTEN(1U)
20691 
20692 #define S_BLKWRFLASHINTEN    13
20693 #define V_BLKWRFLASHINTEN(x) ((x) << S_BLKWRFLASHINTEN)
20694 #define F_BLKWRFLASHINTEN    V_BLKWRFLASHINTEN(1U)
20695 
20696 #define S_BLKRDFLASHINTEN    12
20697 #define V_BLKRDFLASHINTEN(x) ((x) << S_BLKRDFLASHINTEN)
20698 #define F_BLKRDFLASHINTEN    V_BLKRDFLASHINTEN(1U)
20699 
20700 #define S_SGLWRFLASHINTEN    11
20701 #define V_SGLWRFLASHINTEN(x) ((x) << S_SGLWRFLASHINTEN)
20702 #define F_SGLWRFLASHINTEN    V_SGLWRFLASHINTEN(1U)
20703 
20704 #define S_SGLRDFLASHINTEN    10
20705 #define V_SGLRDFLASHINTEN(x) ((x) << S_SGLRDFLASHINTEN)
20706 #define F_SGLRDFLASHINTEN    V_SGLRDFLASHINTEN(1U)
20707 
20708 #define S_BLKWRBOOTINTEN    9
20709 #define V_BLKWRBOOTINTEN(x) ((x) << S_BLKWRBOOTINTEN)
20710 #define F_BLKWRBOOTINTEN    V_BLKWRBOOTINTEN(1U)
20711 
20712 #define S_BLKRDBOOTINTEN    8
20713 #define V_BLKRDBOOTINTEN(x) ((x) << S_BLKRDBOOTINTEN)
20714 #define F_BLKRDBOOTINTEN    V_BLKRDBOOTINTEN(1U)
20715 
20716 #define S_SGLWRBOOTINTEN    7
20717 #define V_SGLWRBOOTINTEN(x) ((x) << S_SGLWRBOOTINTEN)
20718 #define F_SGLWRBOOTINTEN    V_SGLWRBOOTINTEN(1U)
20719 
20720 #define S_SGLRDBOOTINTEN    6
20721 #define V_SGLRDBOOTINTEN(x) ((x) << S_SGLRDBOOTINTEN)
20722 #define F_SGLRDBOOTINTEN    V_SGLRDBOOTINTEN(1U)
20723 
20724 #define S_ILLWRBEINTEN    5
20725 #define V_ILLWRBEINTEN(x) ((x) << S_ILLWRBEINTEN)
20726 #define F_ILLWRBEINTEN    V_ILLWRBEINTEN(1U)
20727 
20728 #define S_ILLRDBEINTEN    4
20729 #define V_ILLRDBEINTEN(x) ((x) << S_ILLRDBEINTEN)
20730 #define F_ILLRDBEINTEN    V_ILLRDBEINTEN(1U)
20731 
20732 #define S_ILLRDINTEN    3
20733 #define V_ILLRDINTEN(x) ((x) << S_ILLRDINTEN)
20734 #define F_ILLRDINTEN    V_ILLRDINTEN(1U)
20735 
20736 #define S_ILLWRINTEN    2
20737 #define V_ILLWRINTEN(x) ((x) << S_ILLWRINTEN)
20738 #define F_ILLWRINTEN    V_ILLWRINTEN(1U)
20739 
20740 #define S_ILLTRANSINTEN    1
20741 #define V_ILLTRANSINTEN(x) ((x) << S_ILLTRANSINTEN)
20742 #define F_ILLTRANSINTEN    V_ILLTRANSINTEN(1U)
20743 
20744 #define S_RSVDSPACEINTEN    0
20745 #define V_RSVDSPACEINTEN(x) ((x) << S_RSVDSPACEINTEN)
20746 #define F_RSVDSPACEINTEN    V_RSVDSPACEINTEN(1U)
20747 
20748 #define A_CIM_HOST_UPACC_INT_CAUSE 0x7b34
20749 
20750 #define S_EEPROMWRINT    30
20751 #define V_EEPROMWRINT(x) ((x) << S_EEPROMWRINT)
20752 #define F_EEPROMWRINT    V_EEPROMWRINT(1U)
20753 
20754 #define S_TIMEOUTMAINT    29
20755 #define V_TIMEOUTMAINT(x) ((x) << S_TIMEOUTMAINT)
20756 #define F_TIMEOUTMAINT    V_TIMEOUTMAINT(1U)
20757 
20758 #define S_TIMEOUTINT    28
20759 #define V_TIMEOUTINT(x) ((x) << S_TIMEOUTINT)
20760 #define F_TIMEOUTINT    V_TIMEOUTINT(1U)
20761 
20762 #define S_RSPOVRLOOKUPINT    27
20763 #define V_RSPOVRLOOKUPINT(x) ((x) << S_RSPOVRLOOKUPINT)
20764 #define F_RSPOVRLOOKUPINT    V_RSPOVRLOOKUPINT(1U)
20765 
20766 #define S_REQOVRLOOKUPINT    26
20767 #define V_REQOVRLOOKUPINT(x) ((x) << S_REQOVRLOOKUPINT)
20768 #define F_REQOVRLOOKUPINT    V_REQOVRLOOKUPINT(1U)
20769 
20770 #define S_BLKWRPLINT    25
20771 #define V_BLKWRPLINT(x) ((x) << S_BLKWRPLINT)
20772 #define F_BLKWRPLINT    V_BLKWRPLINT(1U)
20773 
20774 #define S_BLKRDPLINT    24
20775 #define V_BLKRDPLINT(x) ((x) << S_BLKRDPLINT)
20776 #define F_BLKRDPLINT    V_BLKRDPLINT(1U)
20777 
20778 #define S_SGLWRPLINT    23
20779 #define V_SGLWRPLINT(x) ((x) << S_SGLWRPLINT)
20780 #define F_SGLWRPLINT    V_SGLWRPLINT(1U)
20781 
20782 #define S_SGLRDPLINT    22
20783 #define V_SGLRDPLINT(x) ((x) << S_SGLRDPLINT)
20784 #define F_SGLRDPLINT    V_SGLRDPLINT(1U)
20785 
20786 #define S_BLKWRCTLINT    21
20787 #define V_BLKWRCTLINT(x) ((x) << S_BLKWRCTLINT)
20788 #define F_BLKWRCTLINT    V_BLKWRCTLINT(1U)
20789 
20790 #define S_BLKRDCTLINT    20
20791 #define V_BLKRDCTLINT(x) ((x) << S_BLKRDCTLINT)
20792 #define F_BLKRDCTLINT    V_BLKRDCTLINT(1U)
20793 
20794 #define S_SGLWRCTLINT    19
20795 #define V_SGLWRCTLINT(x) ((x) << S_SGLWRCTLINT)
20796 #define F_SGLWRCTLINT    V_SGLWRCTLINT(1U)
20797 
20798 #define S_SGLRDCTLINT    18
20799 #define V_SGLRDCTLINT(x) ((x) << S_SGLRDCTLINT)
20800 #define F_SGLRDCTLINT    V_SGLRDCTLINT(1U)
20801 
20802 #define S_BLKWREEPROMINT    17
20803 #define V_BLKWREEPROMINT(x) ((x) << S_BLKWREEPROMINT)
20804 #define F_BLKWREEPROMINT    V_BLKWREEPROMINT(1U)
20805 
20806 #define S_BLKRDEEPROMINT    16
20807 #define V_BLKRDEEPROMINT(x) ((x) << S_BLKRDEEPROMINT)
20808 #define F_BLKRDEEPROMINT    V_BLKRDEEPROMINT(1U)
20809 
20810 #define S_SGLWREEPROMINT    15
20811 #define V_SGLWREEPROMINT(x) ((x) << S_SGLWREEPROMINT)
20812 #define F_SGLWREEPROMINT    V_SGLWREEPROMINT(1U)
20813 
20814 #define S_SGLRDEEPROMINT    14
20815 #define V_SGLRDEEPROMINT(x) ((x) << S_SGLRDEEPROMINT)
20816 #define F_SGLRDEEPROMINT    V_SGLRDEEPROMINT(1U)
20817 
20818 #define S_BLKWRFLASHINT    13
20819 #define V_BLKWRFLASHINT(x) ((x) << S_BLKWRFLASHINT)
20820 #define F_BLKWRFLASHINT    V_BLKWRFLASHINT(1U)
20821 
20822 #define S_BLKRDFLASHINT    12
20823 #define V_BLKRDFLASHINT(x) ((x) << S_BLKRDFLASHINT)
20824 #define F_BLKRDFLASHINT    V_BLKRDFLASHINT(1U)
20825 
20826 #define S_SGLWRFLASHINT    11
20827 #define V_SGLWRFLASHINT(x) ((x) << S_SGLWRFLASHINT)
20828 #define F_SGLWRFLASHINT    V_SGLWRFLASHINT(1U)
20829 
20830 #define S_SGLRDFLASHINT    10
20831 #define V_SGLRDFLASHINT(x) ((x) << S_SGLRDFLASHINT)
20832 #define F_SGLRDFLASHINT    V_SGLRDFLASHINT(1U)
20833 
20834 #define S_BLKWRBOOTINT    9
20835 #define V_BLKWRBOOTINT(x) ((x) << S_BLKWRBOOTINT)
20836 #define F_BLKWRBOOTINT    V_BLKWRBOOTINT(1U)
20837 
20838 #define S_BLKRDBOOTINT    8
20839 #define V_BLKRDBOOTINT(x) ((x) << S_BLKRDBOOTINT)
20840 #define F_BLKRDBOOTINT    V_BLKRDBOOTINT(1U)
20841 
20842 #define S_SGLWRBOOTINT    7
20843 #define V_SGLWRBOOTINT(x) ((x) << S_SGLWRBOOTINT)
20844 #define F_SGLWRBOOTINT    V_SGLWRBOOTINT(1U)
20845 
20846 #define S_SGLRDBOOTINT    6
20847 #define V_SGLRDBOOTINT(x) ((x) << S_SGLRDBOOTINT)
20848 #define F_SGLRDBOOTINT    V_SGLRDBOOTINT(1U)
20849 
20850 #define S_ILLWRBEINT    5
20851 #define V_ILLWRBEINT(x) ((x) << S_ILLWRBEINT)
20852 #define F_ILLWRBEINT    V_ILLWRBEINT(1U)
20853 
20854 #define S_ILLRDBEINT    4
20855 #define V_ILLRDBEINT(x) ((x) << S_ILLRDBEINT)
20856 #define F_ILLRDBEINT    V_ILLRDBEINT(1U)
20857 
20858 #define S_ILLRDINT    3
20859 #define V_ILLRDINT(x) ((x) << S_ILLRDINT)
20860 #define F_ILLRDINT    V_ILLRDINT(1U)
20861 
20862 #define S_ILLWRINT    2
20863 #define V_ILLWRINT(x) ((x) << S_ILLWRINT)
20864 #define F_ILLWRINT    V_ILLWRINT(1U)
20865 
20866 #define S_ILLTRANSINT    1
20867 #define V_ILLTRANSINT(x) ((x) << S_ILLTRANSINT)
20868 #define F_ILLTRANSINT    V_ILLTRANSINT(1U)
20869 
20870 #define S_RSVDSPACEINT    0
20871 #define V_RSVDSPACEINT(x) ((x) << S_RSVDSPACEINT)
20872 #define F_RSVDSPACEINT    V_RSVDSPACEINT(1U)
20873 
20874 #define A_CIM_UP_INT_ENABLE 0x7b38
20875 
20876 #define S_MSTPLINTEN    4
20877 #define V_MSTPLINTEN(x) ((x) << S_MSTPLINTEN)
20878 #define F_MSTPLINTEN    V_MSTPLINTEN(1U)
20879 
20880 #define A_CIM_UP_INT_CAUSE 0x7b3c
20881 
20882 #define S_MSTPLINT    4
20883 #define V_MSTPLINT(x) ((x) << S_MSTPLINT)
20884 #define F_MSTPLINT    V_MSTPLINT(1U)
20885 
20886 #define A_CIM_UP_ACC_INT_ENABLE 0x7b40
20887 #define A_CIM_UP_ACC_INT_CAUSE 0x7b44
20888 #define A_CIM_QUEUE_CONFIG_REF 0x7b48
20889 
20890 #define S_OBQSELECT    4
20891 #define V_OBQSELECT(x) ((x) << S_OBQSELECT)
20892 #define F_OBQSELECT    V_OBQSELECT(1U)
20893 
20894 #define S_IBQSELECT    3
20895 #define V_IBQSELECT(x) ((x) << S_IBQSELECT)
20896 #define F_IBQSELECT    V_IBQSELECT(1U)
20897 
20898 #define S_QUENUMSELECT    0
20899 #define M_QUENUMSELECT    0x7U
20900 #define V_QUENUMSELECT(x) ((x) << S_QUENUMSELECT)
20901 #define G_QUENUMSELECT(x) (((x) >> S_QUENUMSELECT) & M_QUENUMSELECT)
20902 
20903 #define A_CIM_QUEUE_CONFIG_CTRL 0x7b4c
20904 
20905 #define S_CIMQSIZE    24
20906 #define M_CIMQSIZE    0x3fU
20907 #define V_CIMQSIZE(x) ((x) << S_CIMQSIZE)
20908 #define G_CIMQSIZE(x) (((x) >> S_CIMQSIZE) & M_CIMQSIZE)
20909 
20910 #define S_CIMQBASE    16
20911 #define M_CIMQBASE    0x3fU
20912 #define V_CIMQBASE(x) ((x) << S_CIMQBASE)
20913 #define G_CIMQBASE(x) (((x) >> S_CIMQBASE) & M_CIMQBASE)
20914 
20915 #define S_CIMQDBG8BEN    9
20916 #define V_CIMQDBG8BEN(x) ((x) << S_CIMQDBG8BEN)
20917 #define F_CIMQDBG8BEN    V_CIMQDBG8BEN(1U)
20918 
20919 #define S_QUEFULLTHRSH    0
20920 #define M_QUEFULLTHRSH    0x1ffU
20921 #define V_QUEFULLTHRSH(x) ((x) << S_QUEFULLTHRSH)
20922 #define G_QUEFULLTHRSH(x) (((x) >> S_QUEFULLTHRSH) & M_QUEFULLTHRSH)
20923 
20924 #define S_CIMQ1KEN    30
20925 #define V_CIMQ1KEN(x) ((x) << S_CIMQ1KEN)
20926 #define F_CIMQ1KEN    V_CIMQ1KEN(1U)
20927 
20928 #define A_CIM_HOST_ACC_CTRL 0x7b50
20929 
20930 #define S_HOSTBUSY    17
20931 #define V_HOSTBUSY(x) ((x) << S_HOSTBUSY)
20932 #define F_HOSTBUSY    V_HOSTBUSY(1U)
20933 
20934 #define S_HOSTWRITE    16
20935 #define V_HOSTWRITE(x) ((x) << S_HOSTWRITE)
20936 #define F_HOSTWRITE    V_HOSTWRITE(1U)
20937 
20938 #define S_HOSTADDR    0
20939 #define M_HOSTADDR    0xffffU
20940 #define V_HOSTADDR(x) ((x) << S_HOSTADDR)
20941 #define G_HOSTADDR(x) (((x) >> S_HOSTADDR) & M_HOSTADDR)
20942 
20943 #define A_CIM_HOST_ACC_DATA 0x7b54
20944 #define A_CIM_CDEBUGDATA 0x7b58
20945 
20946 #define S_CDEBUGDATAH    16
20947 #define M_CDEBUGDATAH    0xffffU
20948 #define V_CDEBUGDATAH(x) ((x) << S_CDEBUGDATAH)
20949 #define G_CDEBUGDATAH(x) (((x) >> S_CDEBUGDATAH) & M_CDEBUGDATAH)
20950 
20951 #define S_CDEBUGDATAL    0
20952 #define M_CDEBUGDATAL    0xffffU
20953 #define V_CDEBUGDATAL(x) ((x) << S_CDEBUGDATAL)
20954 #define G_CDEBUGDATAL(x) (((x) >> S_CDEBUGDATAL) & M_CDEBUGDATAL)
20955 
20956 #define A_CIM_IBQ_DBG_CFG 0x7b60
20957 
20958 #define S_IBQDBGADDR    16
20959 #define M_IBQDBGADDR    0xfffU
20960 #define V_IBQDBGADDR(x) ((x) << S_IBQDBGADDR)
20961 #define G_IBQDBGADDR(x) (((x) >> S_IBQDBGADDR) & M_IBQDBGADDR)
20962 
20963 #define S_IBQDBGWR    2
20964 #define V_IBQDBGWR(x) ((x) << S_IBQDBGWR)
20965 #define F_IBQDBGWR    V_IBQDBGWR(1U)
20966 
20967 #define S_IBQDBGBUSY    1
20968 #define V_IBQDBGBUSY(x) ((x) << S_IBQDBGBUSY)
20969 #define F_IBQDBGBUSY    V_IBQDBGBUSY(1U)
20970 
20971 #define S_IBQDBGEN    0
20972 #define V_IBQDBGEN(x) ((x) << S_IBQDBGEN)
20973 #define F_IBQDBGEN    V_IBQDBGEN(1U)
20974 
20975 #define A_CIM_OBQ_DBG_CFG 0x7b64
20976 
20977 #define S_OBQDBGADDR    16
20978 #define M_OBQDBGADDR    0xfffU
20979 #define V_OBQDBGADDR(x) ((x) << S_OBQDBGADDR)
20980 #define G_OBQDBGADDR(x) (((x) >> S_OBQDBGADDR) & M_OBQDBGADDR)
20981 
20982 #define S_OBQDBGWR    2
20983 #define V_OBQDBGWR(x) ((x) << S_OBQDBGWR)
20984 #define F_OBQDBGWR    V_OBQDBGWR(1U)
20985 
20986 #define S_OBQDBGBUSY    1
20987 #define V_OBQDBGBUSY(x) ((x) << S_OBQDBGBUSY)
20988 #define F_OBQDBGBUSY    V_OBQDBGBUSY(1U)
20989 
20990 #define S_OBQDBGEN    0
20991 #define V_OBQDBGEN(x) ((x) << S_OBQDBGEN)
20992 #define F_OBQDBGEN    V_OBQDBGEN(1U)
20993 
20994 #define A_CIM_IBQ_DBG_DATA 0x7b68
20995 #define A_CIM_OBQ_DBG_DATA 0x7b6c
20996 #define A_CIM_DEBUGCFG 0x7b70
20997 
20998 #define S_POLADBGRDPTR    23
20999 #define M_POLADBGRDPTR    0x1ffU
21000 #define V_POLADBGRDPTR(x) ((x) << S_POLADBGRDPTR)
21001 #define G_POLADBGRDPTR(x) (((x) >> S_POLADBGRDPTR) & M_POLADBGRDPTR)
21002 
21003 #define S_PILADBGRDPTR    14
21004 #define M_PILADBGRDPTR    0x1ffU
21005 #define V_PILADBGRDPTR(x) ((x) << S_PILADBGRDPTR)
21006 #define G_PILADBGRDPTR(x) (((x) >> S_PILADBGRDPTR) & M_PILADBGRDPTR)
21007 
21008 #define S_LAMASKTRIG    13
21009 #define V_LAMASKTRIG(x) ((x) << S_LAMASKTRIG)
21010 #define F_LAMASKTRIG    V_LAMASKTRIG(1U)
21011 
21012 #define S_LADBGEN    12
21013 #define V_LADBGEN(x) ((x) << S_LADBGEN)
21014 #define F_LADBGEN    V_LADBGEN(1U)
21015 
21016 #define S_LAFILLONCE    11
21017 #define V_LAFILLONCE(x) ((x) << S_LAFILLONCE)
21018 #define F_LAFILLONCE    V_LAFILLONCE(1U)
21019 
21020 #define S_LAMASKSTOP    10
21021 #define V_LAMASKSTOP(x) ((x) << S_LAMASKSTOP)
21022 #define F_LAMASKSTOP    V_LAMASKSTOP(1U)
21023 
21024 #define S_DEBUGSELH    5
21025 #define M_DEBUGSELH    0x1fU
21026 #define V_DEBUGSELH(x) ((x) << S_DEBUGSELH)
21027 #define G_DEBUGSELH(x) (((x) >> S_DEBUGSELH) & M_DEBUGSELH)
21028 
21029 #define S_DEBUGSELL    0
21030 #define M_DEBUGSELL    0x1fU
21031 #define V_DEBUGSELL(x) ((x) << S_DEBUGSELL)
21032 #define G_DEBUGSELL(x) (((x) >> S_DEBUGSELL) & M_DEBUGSELL)
21033 
21034 #define A_CIM_DEBUGSTS 0x7b74
21035 
21036 #define S_LARESET    31
21037 #define V_LARESET(x) ((x) << S_LARESET)
21038 #define F_LARESET    V_LARESET(1U)
21039 
21040 #define S_POLADBGWRPTR    16
21041 #define M_POLADBGWRPTR    0x1ffU
21042 #define V_POLADBGWRPTR(x) ((x) << S_POLADBGWRPTR)
21043 #define G_POLADBGWRPTR(x) (((x) >> S_POLADBGWRPTR) & M_POLADBGWRPTR)
21044 
21045 #define S_PILADBGWRPTR    0
21046 #define M_PILADBGWRPTR    0x1ffU
21047 #define V_PILADBGWRPTR(x) ((x) << S_PILADBGWRPTR)
21048 #define G_PILADBGWRPTR(x) (((x) >> S_PILADBGWRPTR) & M_PILADBGWRPTR)
21049 
21050 #define A_CIM_PO_LA_DEBUGDATA 0x7b78
21051 #define A_CIM_PI_LA_DEBUGDATA 0x7b7c
21052 #define A_CIM_PO_LA_MADEBUGDATA 0x7b80
21053 #define A_CIM_PI_LA_MADEBUGDATA 0x7b84
21054 #define A_CIM_PO_LA_PIFSMDEBUGDATA 0x7b8c
21055 #define A_CIM_MEM_ZONE0_VA 0x7b90
21056 
21057 #define S_MEM_ZONE_VA    4
21058 #define M_MEM_ZONE_VA    0xfffffffU
21059 #define V_MEM_ZONE_VA(x) ((x) << S_MEM_ZONE_VA)
21060 #define G_MEM_ZONE_VA(x) (((x) >> S_MEM_ZONE_VA) & M_MEM_ZONE_VA)
21061 
21062 #define A_CIM_MEM_ZONE0_BA 0x7b94
21063 
21064 #define S_MEM_ZONE_BA    6
21065 #define M_MEM_ZONE_BA    0x3ffffffU
21066 #define V_MEM_ZONE_BA(x) ((x) << S_MEM_ZONE_BA)
21067 #define G_MEM_ZONE_BA(x) (((x) >> S_MEM_ZONE_BA) & M_MEM_ZONE_BA)
21068 
21069 #define S_PBT_ENABLE    5
21070 #define V_PBT_ENABLE(x) ((x) << S_PBT_ENABLE)
21071 #define F_PBT_ENABLE    V_PBT_ENABLE(1U)
21072 
21073 #define S_ZONE_DST    0
21074 #define M_ZONE_DST    0x3U
21075 #define V_ZONE_DST(x) ((x) << S_ZONE_DST)
21076 #define G_ZONE_DST(x) (((x) >> S_ZONE_DST) & M_ZONE_DST)
21077 
21078 #define A_CIM_MEM_ZONE0_LEN 0x7b98
21079 
21080 #define S_MEM_ZONE_LEN    4
21081 #define M_MEM_ZONE_LEN    0xfffffffU
21082 #define V_MEM_ZONE_LEN(x) ((x) << S_MEM_ZONE_LEN)
21083 #define G_MEM_ZONE_LEN(x) (((x) >> S_MEM_ZONE_LEN) & M_MEM_ZONE_LEN)
21084 
21085 #define A_CIM_MEM_ZONE1_VA 0x7b9c
21086 #define A_CIM_MEM_ZONE1_BA 0x7ba0
21087 #define A_CIM_MEM_ZONE1_LEN 0x7ba4
21088 #define A_CIM_MEM_ZONE2_VA 0x7ba8
21089 #define A_CIM_MEM_ZONE2_BA 0x7bac
21090 #define A_CIM_MEM_ZONE2_LEN 0x7bb0
21091 #define A_CIM_MEM_ZONE3_VA 0x7bb4
21092 #define A_CIM_MEM_ZONE3_BA 0x7bb8
21093 #define A_CIM_MEM_ZONE3_LEN 0x7bbc
21094 #define A_CIM_MEM_ZONE4_VA 0x7bc0
21095 #define A_CIM_MEM_ZONE4_BA 0x7bc4
21096 #define A_CIM_MEM_ZONE4_LEN 0x7bc8
21097 #define A_CIM_MEM_ZONE5_VA 0x7bcc
21098 #define A_CIM_MEM_ZONE5_BA 0x7bd0
21099 #define A_CIM_MEM_ZONE5_LEN 0x7bd4
21100 #define A_CIM_MEM_ZONE6_VA 0x7bd8
21101 #define A_CIM_MEM_ZONE6_BA 0x7bdc
21102 #define A_CIM_MEM_ZONE6_LEN 0x7be0
21103 #define A_CIM_MEM_ZONE7_VA 0x7be4
21104 #define A_CIM_MEM_ZONE7_BA 0x7be8
21105 #define A_CIM_MEM_ZONE7_LEN 0x7bec
21106 #define A_CIM_BOOT_LEN 0x7bf0
21107 
21108 #define S_BOOTLEN    4
21109 #define M_BOOTLEN    0xfffffffU
21110 #define V_BOOTLEN(x) ((x) << S_BOOTLEN)
21111 #define G_BOOTLEN(x) (((x) >> S_BOOTLEN) & M_BOOTLEN)
21112 
21113 #define A_CIM_GLB_TIMER_CTL 0x7bf4
21114 
21115 #define S_TIMER1EN    4
21116 #define V_TIMER1EN(x) ((x) << S_TIMER1EN)
21117 #define F_TIMER1EN    V_TIMER1EN(1U)
21118 
21119 #define S_TIMER0EN    3
21120 #define V_TIMER0EN(x) ((x) << S_TIMER0EN)
21121 #define F_TIMER0EN    V_TIMER0EN(1U)
21122 
21123 #define S_TIMEREN    1
21124 #define V_TIMEREN(x) ((x) << S_TIMEREN)
21125 #define F_TIMEREN    V_TIMEREN(1U)
21126 
21127 #define A_CIM_GLB_TIMER 0x7bf8
21128 #define A_CIM_GLB_TIMER_TICK 0x7bfc
21129 
21130 #define S_GLBLTTICK    0
21131 #define M_GLBLTTICK    0xffffU
21132 #define V_GLBLTTICK(x) ((x) << S_GLBLTTICK)
21133 #define G_GLBLTTICK(x) (((x) >> S_GLBLTTICK) & M_GLBLTTICK)
21134 
21135 #define A_CIM_TIMER0 0x7c00
21136 #define A_CIM_TIMER1 0x7c04
21137 #define A_CIM_DEBUG_ADDR_TIMEOUT 0x7c08
21138 
21139 #define S_DADDRTIMEOUT    2
21140 #define M_DADDRTIMEOUT    0x3fffffffU
21141 #define V_DADDRTIMEOUT(x) ((x) << S_DADDRTIMEOUT)
21142 #define G_DADDRTIMEOUT(x) (((x) >> S_DADDRTIMEOUT) & M_DADDRTIMEOUT)
21143 
21144 #define S_DADDRTIMEOUTTYPE    0
21145 #define M_DADDRTIMEOUTTYPE    0x3U
21146 #define V_DADDRTIMEOUTTYPE(x) ((x) << S_DADDRTIMEOUTTYPE)
21147 #define G_DADDRTIMEOUTTYPE(x) (((x) >> S_DADDRTIMEOUTTYPE) & M_DADDRTIMEOUTTYPE)
21148 
21149 #define A_CIM_DEBUG_ADDR_ILLEGAL 0x7c0c
21150 
21151 #define S_DADDRILLEGAL    2
21152 #define M_DADDRILLEGAL    0x3fffffffU
21153 #define V_DADDRILLEGAL(x) ((x) << S_DADDRILLEGAL)
21154 #define G_DADDRILLEGAL(x) (((x) >> S_DADDRILLEGAL) & M_DADDRILLEGAL)
21155 
21156 #define S_DADDRILLEGALTYPE    0
21157 #define M_DADDRILLEGALTYPE    0x3U
21158 #define V_DADDRILLEGALTYPE(x) ((x) << S_DADDRILLEGALTYPE)
21159 #define G_DADDRILLEGALTYPE(x) (((x) >> S_DADDRILLEGALTYPE) & M_DADDRILLEGALTYPE)
21160 
21161 #define A_CIM_DEBUG_PIF_CAUSE_MASK 0x7c10
21162 
21163 #define S_DPIFHOSTMASK    0
21164 #define M_DPIFHOSTMASK    0x1fffffU
21165 #define V_DPIFHOSTMASK(x) ((x) << S_DPIFHOSTMASK)
21166 #define G_DPIFHOSTMASK(x) (((x) >> S_DPIFHOSTMASK) & M_DPIFHOSTMASK)
21167 
21168 #define S_T5_DPIFHOSTMASK    0
21169 #define M_T5_DPIFHOSTMASK    0x1fffffffU
21170 #define V_T5_DPIFHOSTMASK(x) ((x) << S_T5_DPIFHOSTMASK)
21171 #define G_T5_DPIFHOSTMASK(x) (((x) >> S_T5_DPIFHOSTMASK) & M_T5_DPIFHOSTMASK)
21172 
21173 #define S_T6_T5_DPIFHOSTMASK    0
21174 #define M_T6_T5_DPIFHOSTMASK    0x3fffffffU
21175 #define V_T6_T5_DPIFHOSTMASK(x) ((x) << S_T6_T5_DPIFHOSTMASK)
21176 #define G_T6_T5_DPIFHOSTMASK(x) (((x) >> S_T6_T5_DPIFHOSTMASK) & M_T6_T5_DPIFHOSTMASK)
21177 
21178 #define A_CIM_DEBUG_PIF_UPACC_CAUSE_MASK 0x7c14
21179 
21180 #define S_DPIFHUPAMASK    0
21181 #define M_DPIFHUPAMASK    0x7fffffffU
21182 #define V_DPIFHUPAMASK(x) ((x) << S_DPIFHUPAMASK)
21183 #define G_DPIFHUPAMASK(x) (((x) >> S_DPIFHUPAMASK) & M_DPIFHUPAMASK)
21184 
21185 #define A_CIM_DEBUG_UP_CAUSE_MASK 0x7c18
21186 
21187 #define S_DUPMASK    0
21188 #define M_DUPMASK    0x1fffffU
21189 #define V_DUPMASK(x) ((x) << S_DUPMASK)
21190 #define G_DUPMASK(x) (((x) >> S_DUPMASK) & M_DUPMASK)
21191 
21192 #define S_T5_DUPMASK    0
21193 #define M_T5_DUPMASK    0x1fffffffU
21194 #define V_T5_DUPMASK(x) ((x) << S_T5_DUPMASK)
21195 #define G_T5_DUPMASK(x) (((x) >> S_T5_DUPMASK) & M_T5_DUPMASK)
21196 
21197 #define S_T6_T5_DUPMASK    0
21198 #define M_T6_T5_DUPMASK    0x3fffffffU
21199 #define V_T6_T5_DUPMASK(x) ((x) << S_T6_T5_DUPMASK)
21200 #define G_T6_T5_DUPMASK(x) (((x) >> S_T6_T5_DUPMASK) & M_T6_T5_DUPMASK)
21201 
21202 #define A_CIM_DEBUG_UP_UPACC_CAUSE_MASK 0x7c1c
21203 
21204 #define S_DUPUACCMASK    0
21205 #define M_DUPUACCMASK    0x7fffffffU
21206 #define V_DUPUACCMASK(x) ((x) << S_DUPUACCMASK)
21207 #define G_DUPUACCMASK(x) (((x) >> S_DUPUACCMASK) & M_DUPUACCMASK)
21208 
21209 #define A_CIM_PERR_INJECT 0x7c20
21210 #define A_CIM_PERR_ENABLE 0x7c24
21211 
21212 #define S_PERREN    0
21213 #define M_PERREN    0x1fffffU
21214 #define V_PERREN(x) ((x) << S_PERREN)
21215 #define G_PERREN(x) (((x) >> S_PERREN) & M_PERREN)
21216 
21217 #define S_T5_PERREN    0
21218 #define M_T5_PERREN    0x1fffffffU
21219 #define V_T5_PERREN(x) ((x) << S_T5_PERREN)
21220 #define G_T5_PERREN(x) (((x) >> S_T5_PERREN) & M_T5_PERREN)
21221 
21222 #define S_T6_T5_PERREN    0
21223 #define M_T6_T5_PERREN    0x3fffffffU
21224 #define V_T6_T5_PERREN(x) ((x) << S_T6_T5_PERREN)
21225 #define G_T6_T5_PERREN(x) (((x) >> S_T6_T5_PERREN) & M_T6_T5_PERREN)
21226 
21227 #define A_CIM_EEPROM_BUSY_BIT 0x7c28
21228 
21229 #define S_EEPROMBUSY    0
21230 #define V_EEPROMBUSY(x) ((x) << S_EEPROMBUSY)
21231 #define F_EEPROMBUSY    V_EEPROMBUSY(1U)
21232 
21233 #define A_CIM_MA_TIMER_EN 0x7c2c
21234 
21235 #define S_MA_TIMER_ENABLE    0
21236 #define V_MA_TIMER_ENABLE(x) ((x) << S_MA_TIMER_ENABLE)
21237 #define F_MA_TIMER_ENABLE    V_MA_TIMER_ENABLE(1U)
21238 
21239 #define S_SLOW_TIMER_ENABLE    1
21240 #define V_SLOW_TIMER_ENABLE(x) ((x) << S_SLOW_TIMER_ENABLE)
21241 #define F_SLOW_TIMER_ENABLE    V_SLOW_TIMER_ENABLE(1U)
21242 
21243 #define A_CIM_UP_PO_SINGLE_OUTSTANDING 0x7c30
21244 
21245 #define S_UP_PO_SINGLE_OUTSTANDING    0
21246 #define V_UP_PO_SINGLE_OUTSTANDING(x) ((x) << S_UP_PO_SINGLE_OUTSTANDING)
21247 #define F_UP_PO_SINGLE_OUTSTANDING    V_UP_PO_SINGLE_OUTSTANDING(1U)
21248 
21249 #define A_CIM_CIM_DEBUG_SPARE 0x7c34
21250 #define A_CIM_UP_OPERATION_FREQ 0x7c38
21251 #define A_CIM_CIM_IBQ_ERR_CODE 0x7c3c
21252 
21253 #define S_CIM_ULP_TX_PKT_ERR_CODE    16
21254 #define M_CIM_ULP_TX_PKT_ERR_CODE    0xffU
21255 #define V_CIM_ULP_TX_PKT_ERR_CODE(x) ((x) << S_CIM_ULP_TX_PKT_ERR_CODE)
21256 #define G_CIM_ULP_TX_PKT_ERR_CODE(x) (((x) >> S_CIM_ULP_TX_PKT_ERR_CODE) & M_CIM_ULP_TX_PKT_ERR_CODE)
21257 
21258 #define S_CIM_SGE1_PKT_ERR_CODE    8
21259 #define M_CIM_SGE1_PKT_ERR_CODE    0xffU
21260 #define V_CIM_SGE1_PKT_ERR_CODE(x) ((x) << S_CIM_SGE1_PKT_ERR_CODE)
21261 #define G_CIM_SGE1_PKT_ERR_CODE(x) (((x) >> S_CIM_SGE1_PKT_ERR_CODE) & M_CIM_SGE1_PKT_ERR_CODE)
21262 
21263 #define S_CIM_SGE0_PKT_ERR_CODE    0
21264 #define M_CIM_SGE0_PKT_ERR_CODE    0xffU
21265 #define V_CIM_SGE0_PKT_ERR_CODE(x) ((x) << S_CIM_SGE0_PKT_ERR_CODE)
21266 #define G_CIM_SGE0_PKT_ERR_CODE(x) (((x) >> S_CIM_SGE0_PKT_ERR_CODE) & M_CIM_SGE0_PKT_ERR_CODE)
21267 
21268 #define S_CIM_PCIE_PKT_ERR_CODE    8
21269 #define M_CIM_PCIE_PKT_ERR_CODE    0xffU
21270 #define V_CIM_PCIE_PKT_ERR_CODE(x) ((x) << S_CIM_PCIE_PKT_ERR_CODE)
21271 #define G_CIM_PCIE_PKT_ERR_CODE(x) (((x) >> S_CIM_PCIE_PKT_ERR_CODE) & M_CIM_PCIE_PKT_ERR_CODE)
21272 
21273 #define A_CIM_IBQ_DBG_WAIT_COUNTER 0x7c40
21274 #define A_CIM_PIO_UP_MST_CFG_SEL 0x7c44
21275 
21276 #define S_PIO_UP_MST_CFG_SEL    0
21277 #define V_PIO_UP_MST_CFG_SEL(x) ((x) << S_PIO_UP_MST_CFG_SEL)
21278 #define F_PIO_UP_MST_CFG_SEL    V_PIO_UP_MST_CFG_SEL(1U)
21279 
21280 #define A_CIM_CGEN 0x7c48
21281 
21282 #define S_TSCH_CGEN    0
21283 #define V_TSCH_CGEN(x) ((x) << S_TSCH_CGEN)
21284 #define F_TSCH_CGEN    V_TSCH_CGEN(1U)
21285 
21286 #define A_CIM_QUEUE_FEATURE_DISABLE 0x7c4c
21287 
21288 #define S_OBQ_THROUTTLE_ON_EOP    4
21289 #define V_OBQ_THROUTTLE_ON_EOP(x) ((x) << S_OBQ_THROUTTLE_ON_EOP)
21290 #define F_OBQ_THROUTTLE_ON_EOP    V_OBQ_THROUTTLE_ON_EOP(1U)
21291 
21292 #define S_OBQ_READ_CTL_PERF_MODE_DISABLE    3
21293 #define V_OBQ_READ_CTL_PERF_MODE_DISABLE(x) ((x) << S_OBQ_READ_CTL_PERF_MODE_DISABLE)
21294 #define F_OBQ_READ_CTL_PERF_MODE_DISABLE    V_OBQ_READ_CTL_PERF_MODE_DISABLE(1U)
21295 
21296 #define S_OBQ_WAIT_FOR_EOP_FLUSH_DISABLE    2
21297 #define V_OBQ_WAIT_FOR_EOP_FLUSH_DISABLE(x) ((x) << S_OBQ_WAIT_FOR_EOP_FLUSH_DISABLE)
21298 #define F_OBQ_WAIT_FOR_EOP_FLUSH_DISABLE    V_OBQ_WAIT_FOR_EOP_FLUSH_DISABLE(1U)
21299 
21300 #define S_IBQ_RRA_DSBL    1
21301 #define V_IBQ_RRA_DSBL(x) ((x) << S_IBQ_RRA_DSBL)
21302 #define F_IBQ_RRA_DSBL    V_IBQ_RRA_DSBL(1U)
21303 
21304 #define S_IBQ_SKID_FIFO_EOP_FLSH_DSBL    0
21305 #define V_IBQ_SKID_FIFO_EOP_FLSH_DSBL(x) ((x) << S_IBQ_SKID_FIFO_EOP_FLSH_DSBL)
21306 #define F_IBQ_SKID_FIFO_EOP_FLSH_DSBL    V_IBQ_SKID_FIFO_EOP_FLSH_DSBL(1U)
21307 
21308 #define S_PCIE_OBQ_IF_DISABLE    5
21309 #define V_PCIE_OBQ_IF_DISABLE(x) ((x) << S_PCIE_OBQ_IF_DISABLE)
21310 #define F_PCIE_OBQ_IF_DISABLE    V_PCIE_OBQ_IF_DISABLE(1U)
21311 
21312 #define A_CIM_CGEN_GLOBAL 0x7c50
21313 
21314 #define S_CGEN_GLOBAL    0
21315 #define V_CGEN_GLOBAL(x) ((x) << S_CGEN_GLOBAL)
21316 #define F_CGEN_GLOBAL    V_CGEN_GLOBAL(1U)
21317 
21318 #define A_CIM_DPSLP_EN 0x7c54
21319 
21320 #define S_PIFDBGLA_DPSLP_EN    0
21321 #define V_PIFDBGLA_DPSLP_EN(x) ((x) << S_PIFDBGLA_DPSLP_EN)
21322 #define F_PIFDBGLA_DPSLP_EN    V_PIFDBGLA_DPSLP_EN(1U)
21323 
21324 /* registers for module TP */
21325 #define TP_BASE_ADDR 0x7d00
21326 
21327 #define A_TP_IN_CONFIG 0x7d00
21328 
21329 #define S_TCPOPTPARSERDISCH3    27
21330 #define V_TCPOPTPARSERDISCH3(x) ((x) << S_TCPOPTPARSERDISCH3)
21331 #define F_TCPOPTPARSERDISCH3    V_TCPOPTPARSERDISCH3(1U)
21332 
21333 #define S_TCPOPTPARSERDISCH2    26
21334 #define V_TCPOPTPARSERDISCH2(x) ((x) << S_TCPOPTPARSERDISCH2)
21335 #define F_TCPOPTPARSERDISCH2    V_TCPOPTPARSERDISCH2(1U)
21336 
21337 #define S_TCPOPTPARSERDISCH1    25
21338 #define V_TCPOPTPARSERDISCH1(x) ((x) << S_TCPOPTPARSERDISCH1)
21339 #define F_TCPOPTPARSERDISCH1    V_TCPOPTPARSERDISCH1(1U)
21340 
21341 #define S_TCPOPTPARSERDISCH0    24
21342 #define V_TCPOPTPARSERDISCH0(x) ((x) << S_TCPOPTPARSERDISCH0)
21343 #define F_TCPOPTPARSERDISCH0    V_TCPOPTPARSERDISCH0(1U)
21344 
21345 #define S_CRCPASSPRT3    23
21346 #define V_CRCPASSPRT3(x) ((x) << S_CRCPASSPRT3)
21347 #define F_CRCPASSPRT3    V_CRCPASSPRT3(1U)
21348 
21349 #define S_CRCPASSPRT2    22
21350 #define V_CRCPASSPRT2(x) ((x) << S_CRCPASSPRT2)
21351 #define F_CRCPASSPRT2    V_CRCPASSPRT2(1U)
21352 
21353 #define S_CRCPASSPRT1    21
21354 #define V_CRCPASSPRT1(x) ((x) << S_CRCPASSPRT1)
21355 #define F_CRCPASSPRT1    V_CRCPASSPRT1(1U)
21356 
21357 #define S_CRCPASSPRT0    20
21358 #define V_CRCPASSPRT0(x) ((x) << S_CRCPASSPRT0)
21359 #define F_CRCPASSPRT0    V_CRCPASSPRT0(1U)
21360 
21361 #define S_VEPAMODE    19
21362 #define V_VEPAMODE(x) ((x) << S_VEPAMODE)
21363 #define F_VEPAMODE    V_VEPAMODE(1U)
21364 
21365 #define S_FIPUPEN    18
21366 #define V_FIPUPEN(x) ((x) << S_FIPUPEN)
21367 #define F_FIPUPEN    V_FIPUPEN(1U)
21368 
21369 #define S_FCOEUPEN    17
21370 #define V_FCOEUPEN(x) ((x) << S_FCOEUPEN)
21371 #define F_FCOEUPEN    V_FCOEUPEN(1U)
21372 
21373 #define S_FCOEENABLE    16
21374 #define V_FCOEENABLE(x) ((x) << S_FCOEENABLE)
21375 #define F_FCOEENABLE    V_FCOEENABLE(1U)
21376 
21377 #define S_IPV6ENABLE    15
21378 #define V_IPV6ENABLE(x) ((x) << S_IPV6ENABLE)
21379 #define F_IPV6ENABLE    V_IPV6ENABLE(1U)
21380 
21381 #define S_NICMODE    14
21382 #define V_NICMODE(x) ((x) << S_NICMODE)
21383 #define F_NICMODE    V_NICMODE(1U)
21384 
21385 #define S_ECHECKSUMCHECKTCP    13
21386 #define V_ECHECKSUMCHECKTCP(x) ((x) << S_ECHECKSUMCHECKTCP)
21387 #define F_ECHECKSUMCHECKTCP    V_ECHECKSUMCHECKTCP(1U)
21388 
21389 #define S_ECHECKSUMCHECKIP    12
21390 #define V_ECHECKSUMCHECKIP(x) ((x) << S_ECHECKSUMCHECKIP)
21391 #define F_ECHECKSUMCHECKIP    V_ECHECKSUMCHECKIP(1U)
21392 
21393 #define S_EREPORTUDPHDRLEN    11
21394 #define V_EREPORTUDPHDRLEN(x) ((x) << S_EREPORTUDPHDRLEN)
21395 #define F_EREPORTUDPHDRLEN    V_EREPORTUDPHDRLEN(1U)
21396 
21397 #define S_IN_ECPL    10
21398 #define V_IN_ECPL(x) ((x) << S_IN_ECPL)
21399 #define F_IN_ECPL    V_IN_ECPL(1U)
21400 
21401 #define S_VNTAGENABLE    9
21402 #define V_VNTAGENABLE(x) ((x) << S_VNTAGENABLE)
21403 #define F_VNTAGENABLE    V_VNTAGENABLE(1U)
21404 
21405 #define S_IN_EETH    8
21406 #define V_IN_EETH(x) ((x) << S_IN_EETH)
21407 #define F_IN_EETH    V_IN_EETH(1U)
21408 
21409 #define S_CCHECKSUMCHECKTCP    6
21410 #define V_CCHECKSUMCHECKTCP(x) ((x) << S_CCHECKSUMCHECKTCP)
21411 #define F_CCHECKSUMCHECKTCP    V_CCHECKSUMCHECKTCP(1U)
21412 
21413 #define S_CCHECKSUMCHECKIP    5
21414 #define V_CCHECKSUMCHECKIP(x) ((x) << S_CCHECKSUMCHECKIP)
21415 #define F_CCHECKSUMCHECKIP    V_CCHECKSUMCHECKIP(1U)
21416 
21417 #define S_CTAG    4
21418 #define V_CTAG(x) ((x) << S_CTAG)
21419 #define F_CTAG    V_CTAG(1U)
21420 
21421 #define S_IN_CCPL    3
21422 #define V_IN_CCPL(x) ((x) << S_IN_CCPL)
21423 #define F_IN_CCPL    V_IN_CCPL(1U)
21424 
21425 #define S_IN_CETH    1
21426 #define V_IN_CETH(x) ((x) << S_IN_CETH)
21427 #define F_IN_CETH    V_IN_CETH(1U)
21428 
21429 #define S_CTUNNEL    0
21430 #define V_CTUNNEL(x) ((x) << S_CTUNNEL)
21431 #define F_CTUNNEL    V_CTUNNEL(1U)
21432 
21433 #define S_VLANEXTENPORT3    31
21434 #define V_VLANEXTENPORT3(x) ((x) << S_VLANEXTENPORT3)
21435 #define F_VLANEXTENPORT3    V_VLANEXTENPORT3(1U)
21436 
21437 #define S_VLANEXTENPORT2    30
21438 #define V_VLANEXTENPORT2(x) ((x) << S_VLANEXTENPORT2)
21439 #define F_VLANEXTENPORT2    V_VLANEXTENPORT2(1U)
21440 
21441 #define S_VLANEXTENPORT1    29
21442 #define V_VLANEXTENPORT1(x) ((x) << S_VLANEXTENPORT1)
21443 #define F_VLANEXTENPORT1    V_VLANEXTENPORT1(1U)
21444 
21445 #define S_VLANEXTENPORT0    28
21446 #define V_VLANEXTENPORT0(x) ((x) << S_VLANEXTENPORT0)
21447 #define F_VLANEXTENPORT0    V_VLANEXTENPORT0(1U)
21448 
21449 #define S_VNTAGDEFAULTVAL    13
21450 #define V_VNTAGDEFAULTVAL(x) ((x) << S_VNTAGDEFAULTVAL)
21451 #define F_VNTAGDEFAULTVAL    V_VNTAGDEFAULTVAL(1U)
21452 
21453 #define S_ECHECKUDPLEN    12
21454 #define V_ECHECKUDPLEN(x) ((x) << S_ECHECKUDPLEN)
21455 #define F_ECHECKUDPLEN    V_ECHECKUDPLEN(1U)
21456 
21457 #define S_FCOEFPMA    10
21458 #define V_FCOEFPMA(x) ((x) << S_FCOEFPMA)
21459 #define F_FCOEFPMA    V_FCOEFPMA(1U)
21460 
21461 #define S_VNTAGETHENABLE    8
21462 #define V_VNTAGETHENABLE(x) ((x) << S_VNTAGETHENABLE)
21463 #define F_VNTAGETHENABLE    V_VNTAGETHENABLE(1U)
21464 
21465 #define S_IP_CCSM    7
21466 #define V_IP_CCSM(x) ((x) << S_IP_CCSM)
21467 #define F_IP_CCSM    V_IP_CCSM(1U)
21468 
21469 #define S_CCHECKSUMCHECKUDP    6
21470 #define V_CCHECKSUMCHECKUDP(x) ((x) << S_CCHECKSUMCHECKUDP)
21471 #define F_CCHECKSUMCHECKUDP    V_CCHECKSUMCHECKUDP(1U)
21472 
21473 #define S_TCP_CCSM    5
21474 #define V_TCP_CCSM(x) ((x) << S_TCP_CCSM)
21475 #define F_TCP_CCSM    V_TCP_CCSM(1U)
21476 
21477 #define S_CDEMUX    3
21478 #define V_CDEMUX(x) ((x) << S_CDEMUX)
21479 #define F_CDEMUX    V_CDEMUX(1U)
21480 
21481 #define S_ETHUPEN    2
21482 #define V_ETHUPEN(x) ((x) << S_ETHUPEN)
21483 #define F_ETHUPEN    V_ETHUPEN(1U)
21484 
21485 #define S_CXOFFOVERRIDE    3
21486 #define V_CXOFFOVERRIDE(x) ((x) << S_CXOFFOVERRIDE)
21487 #define F_CXOFFOVERRIDE    V_CXOFFOVERRIDE(1U)
21488 
21489 #define S_EGREDROPEN    1
21490 #define V_EGREDROPEN(x) ((x) << S_EGREDROPEN)
21491 #define F_EGREDROPEN    V_EGREDROPEN(1U)
21492 
21493 #define S_CFASTDEMUXEN    0
21494 #define V_CFASTDEMUXEN(x) ((x) << S_CFASTDEMUXEN)
21495 #define F_CFASTDEMUXEN    V_CFASTDEMUXEN(1U)
21496 
21497 #define A_TP_OUT_CONFIG 0x7d04
21498 
21499 #define S_PORTQFCEN    28
21500 #define M_PORTQFCEN    0xfU
21501 #define V_PORTQFCEN(x) ((x) << S_PORTQFCEN)
21502 #define G_PORTQFCEN(x) (((x) >> S_PORTQFCEN) & M_PORTQFCEN)
21503 
21504 #define S_EPKTDISTCHN3    23
21505 #define V_EPKTDISTCHN3(x) ((x) << S_EPKTDISTCHN3)
21506 #define F_EPKTDISTCHN3    V_EPKTDISTCHN3(1U)
21507 
21508 #define S_EPKTDISTCHN2    22
21509 #define V_EPKTDISTCHN2(x) ((x) << S_EPKTDISTCHN2)
21510 #define F_EPKTDISTCHN2    V_EPKTDISTCHN2(1U)
21511 
21512 #define S_EPKTDISTCHN1    21
21513 #define V_EPKTDISTCHN1(x) ((x) << S_EPKTDISTCHN1)
21514 #define F_EPKTDISTCHN1    V_EPKTDISTCHN1(1U)
21515 
21516 #define S_EPKTDISTCHN0    20
21517 #define V_EPKTDISTCHN0(x) ((x) << S_EPKTDISTCHN0)
21518 #define F_EPKTDISTCHN0    V_EPKTDISTCHN0(1U)
21519 
21520 #define S_TTLMODE    19
21521 #define V_TTLMODE(x) ((x) << S_TTLMODE)
21522 #define F_TTLMODE    V_TTLMODE(1U)
21523 
21524 #define S_EQFCDMAC    18
21525 #define V_EQFCDMAC(x) ((x) << S_EQFCDMAC)
21526 #define F_EQFCDMAC    V_EQFCDMAC(1U)
21527 
21528 #define S_ELPBKINCMPSSTAT    17
21529 #define V_ELPBKINCMPSSTAT(x) ((x) << S_ELPBKINCMPSSTAT)
21530 #define F_ELPBKINCMPSSTAT    V_ELPBKINCMPSSTAT(1U)
21531 
21532 #define S_IPIDSPLITMODE    16
21533 #define V_IPIDSPLITMODE(x) ((x) << S_IPIDSPLITMODE)
21534 #define F_IPIDSPLITMODE    V_IPIDSPLITMODE(1U)
21535 
21536 #define S_VLANEXTENABLEPORT3    15
21537 #define V_VLANEXTENABLEPORT3(x) ((x) << S_VLANEXTENABLEPORT3)
21538 #define F_VLANEXTENABLEPORT3    V_VLANEXTENABLEPORT3(1U)
21539 
21540 #define S_VLANEXTENABLEPORT2    14
21541 #define V_VLANEXTENABLEPORT2(x) ((x) << S_VLANEXTENABLEPORT2)
21542 #define F_VLANEXTENABLEPORT2    V_VLANEXTENABLEPORT2(1U)
21543 
21544 #define S_VLANEXTENABLEPORT1    13
21545 #define V_VLANEXTENABLEPORT1(x) ((x) << S_VLANEXTENABLEPORT1)
21546 #define F_VLANEXTENABLEPORT1    V_VLANEXTENABLEPORT1(1U)
21547 
21548 #define S_VLANEXTENABLEPORT0    12
21549 #define V_VLANEXTENABLEPORT0(x) ((x) << S_VLANEXTENABLEPORT0)
21550 #define F_VLANEXTENABLEPORT0    V_VLANEXTENABLEPORT0(1U)
21551 
21552 #define S_ECHECKSUMINSERTTCP    11
21553 #define V_ECHECKSUMINSERTTCP(x) ((x) << S_ECHECKSUMINSERTTCP)
21554 #define F_ECHECKSUMINSERTTCP    V_ECHECKSUMINSERTTCP(1U)
21555 
21556 #define S_ECHECKSUMINSERTIP    10
21557 #define V_ECHECKSUMINSERTIP(x) ((x) << S_ECHECKSUMINSERTIP)
21558 #define F_ECHECKSUMINSERTIP    V_ECHECKSUMINSERTIP(1U)
21559 
21560 #define S_ECPL    8
21561 #define V_ECPL(x) ((x) << S_ECPL)
21562 #define F_ECPL    V_ECPL(1U)
21563 
21564 #define S_EPRIORITY    7
21565 #define V_EPRIORITY(x) ((x) << S_EPRIORITY)
21566 #define F_EPRIORITY    V_EPRIORITY(1U)
21567 
21568 #define S_EETHERNET    6
21569 #define V_EETHERNET(x) ((x) << S_EETHERNET)
21570 #define F_EETHERNET    V_EETHERNET(1U)
21571 
21572 #define S_CCHECKSUMINSERTTCP    5
21573 #define V_CCHECKSUMINSERTTCP(x) ((x) << S_CCHECKSUMINSERTTCP)
21574 #define F_CCHECKSUMINSERTTCP    V_CCHECKSUMINSERTTCP(1U)
21575 
21576 #define S_CCHECKSUMINSERTIP    4
21577 #define V_CCHECKSUMINSERTIP(x) ((x) << S_CCHECKSUMINSERTIP)
21578 #define F_CCHECKSUMINSERTIP    V_CCHECKSUMINSERTIP(1U)
21579 
21580 #define S_CCPL    2
21581 #define V_CCPL(x) ((x) << S_CCPL)
21582 #define F_CCPL    V_CCPL(1U)
21583 
21584 #define S_CETHERNET    0
21585 #define V_CETHERNET(x) ((x) << S_CETHERNET)
21586 #define F_CETHERNET    V_CETHERNET(1U)
21587 
21588 #define S_EVNTAGEN    9
21589 #define V_EVNTAGEN(x) ((x) << S_EVNTAGEN)
21590 #define F_EVNTAGEN    V_EVNTAGEN(1U)
21591 
21592 #define S_CCPLACKMODE    13
21593 #define V_CCPLACKMODE(x) ((x) << S_CCPLACKMODE)
21594 #define F_CCPLACKMODE    V_CCPLACKMODE(1U)
21595 
21596 #define S_RMWHINTENABLE    12
21597 #define V_RMWHINTENABLE(x) ((x) << S_RMWHINTENABLE)
21598 #define F_RMWHINTENABLE    V_RMWHINTENABLE(1U)
21599 
21600 #define S_EV6FLWEN    8
21601 #define V_EV6FLWEN(x) ((x) << S_EV6FLWEN)
21602 #define F_EV6FLWEN    V_EV6FLWEN(1U)
21603 
21604 #define S_EVLANPRIO    6
21605 #define V_EVLANPRIO(x) ((x) << S_EVLANPRIO)
21606 #define F_EVLANPRIO    V_EVLANPRIO(1U)
21607 
21608 #define S_CRXPKTENC    3
21609 #define V_CRXPKTENC(x) ((x) << S_CRXPKTENC)
21610 #define F_CRXPKTENC    V_CRXPKTENC(1U)
21611 
21612 #define S_CRXPKTXT    1
21613 #define V_CRXPKTXT(x) ((x) << S_CRXPKTXT)
21614 #define F_CRXPKTXT    V_CRXPKTXT(1U)
21615 
21616 #define A_TP_GLOBAL_CONFIG 0x7d08
21617 
21618 #define S_SYNCOOKIEPARAMS    26
21619 #define M_SYNCOOKIEPARAMS    0x3fU
21620 #define V_SYNCOOKIEPARAMS(x) ((x) << S_SYNCOOKIEPARAMS)
21621 #define G_SYNCOOKIEPARAMS(x) (((x) >> S_SYNCOOKIEPARAMS) & M_SYNCOOKIEPARAMS)
21622 
21623 #define S_RXFLOWCONTROLDISABLE    25
21624 #define V_RXFLOWCONTROLDISABLE(x) ((x) << S_RXFLOWCONTROLDISABLE)
21625 #define F_RXFLOWCONTROLDISABLE    V_RXFLOWCONTROLDISABLE(1U)
21626 
21627 #define S_TXPACINGENABLE    24
21628 #define V_TXPACINGENABLE(x) ((x) << S_TXPACINGENABLE)
21629 #define F_TXPACINGENABLE    V_TXPACINGENABLE(1U)
21630 
21631 #define S_ATTACKFILTERENABLE    23
21632 #define V_ATTACKFILTERENABLE(x) ((x) << S_ATTACKFILTERENABLE)
21633 #define F_ATTACKFILTERENABLE    V_ATTACKFILTERENABLE(1U)
21634 
21635 #define S_SYNCOOKIENOOPTIONS    22
21636 #define V_SYNCOOKIENOOPTIONS(x) ((x) << S_SYNCOOKIENOOPTIONS)
21637 #define F_SYNCOOKIENOOPTIONS    V_SYNCOOKIENOOPTIONS(1U)
21638 
21639 #define S_PROTECTEDMODE    21
21640 #define V_PROTECTEDMODE(x) ((x) << S_PROTECTEDMODE)
21641 #define F_PROTECTEDMODE    V_PROTECTEDMODE(1U)
21642 
21643 #define S_PINGDROP    20
21644 #define V_PINGDROP(x) ((x) << S_PINGDROP)
21645 #define F_PINGDROP    V_PINGDROP(1U)
21646 
21647 #define S_FRAGMENTDROP    19
21648 #define V_FRAGMENTDROP(x) ((x) << S_FRAGMENTDROP)
21649 #define F_FRAGMENTDROP    V_FRAGMENTDROP(1U)
21650 
21651 #define S_FIVETUPLELOOKUP    17
21652 #define M_FIVETUPLELOOKUP    0x3U
21653 #define V_FIVETUPLELOOKUP(x) ((x) << S_FIVETUPLELOOKUP)
21654 #define G_FIVETUPLELOOKUP(x) (((x) >> S_FIVETUPLELOOKUP) & M_FIVETUPLELOOKUP)
21655 
21656 #define S_OFDMPSSTATS    16
21657 #define V_OFDMPSSTATS(x) ((x) << S_OFDMPSSTATS)
21658 #define F_OFDMPSSTATS    V_OFDMPSSTATS(1U)
21659 
21660 #define S_DONTFRAGMENT    15
21661 #define V_DONTFRAGMENT(x) ((x) << S_DONTFRAGMENT)
21662 #define F_DONTFRAGMENT    V_DONTFRAGMENT(1U)
21663 
21664 #define S_IPIDENTSPLIT    14
21665 #define V_IPIDENTSPLIT(x) ((x) << S_IPIDENTSPLIT)
21666 #define F_IPIDENTSPLIT    V_IPIDENTSPLIT(1U)
21667 
21668 #define S_IPCHECKSUMOFFLOAD    13
21669 #define V_IPCHECKSUMOFFLOAD(x) ((x) << S_IPCHECKSUMOFFLOAD)
21670 #define F_IPCHECKSUMOFFLOAD    V_IPCHECKSUMOFFLOAD(1U)
21671 
21672 #define S_UDPCHECKSUMOFFLOAD    12
21673 #define V_UDPCHECKSUMOFFLOAD(x) ((x) << S_UDPCHECKSUMOFFLOAD)
21674 #define F_UDPCHECKSUMOFFLOAD    V_UDPCHECKSUMOFFLOAD(1U)
21675 
21676 #define S_TCPCHECKSUMOFFLOAD    11
21677 #define V_TCPCHECKSUMOFFLOAD(x) ((x) << S_TCPCHECKSUMOFFLOAD)
21678 #define F_TCPCHECKSUMOFFLOAD    V_TCPCHECKSUMOFFLOAD(1U)
21679 
21680 #define S_RSSLOOPBACKENABLE    10
21681 #define V_RSSLOOPBACKENABLE(x) ((x) << S_RSSLOOPBACKENABLE)
21682 #define F_RSSLOOPBACKENABLE    V_RSSLOOPBACKENABLE(1U)
21683 
21684 #define S_TCAMSERVERUSE    8
21685 #define M_TCAMSERVERUSE    0x3U
21686 #define V_TCAMSERVERUSE(x) ((x) << S_TCAMSERVERUSE)
21687 #define G_TCAMSERVERUSE(x) (((x) >> S_TCAMSERVERUSE) & M_TCAMSERVERUSE)
21688 
21689 #define S_IPTTL    0
21690 #define M_IPTTL    0xffU
21691 #define V_IPTTL(x) ((x) << S_IPTTL)
21692 #define G_IPTTL(x) (((x) >> S_IPTTL) & M_IPTTL)
21693 
21694 #define S_RSSSYNSTEERENABLE    12
21695 #define V_RSSSYNSTEERENABLE(x) ((x) << S_RSSSYNSTEERENABLE)
21696 #define F_RSSSYNSTEERENABLE    V_RSSSYNSTEERENABLE(1U)
21697 
21698 #define S_ISSFROMCPLENABLE    11
21699 #define V_ISSFROMCPLENABLE(x) ((x) << S_ISSFROMCPLENABLE)
21700 #define F_ISSFROMCPLENABLE    V_ISSFROMCPLENABLE(1U)
21701 
21702 #define S_ACTIVEFILTERCOUNTS    22
21703 #define V_ACTIVEFILTERCOUNTS(x) ((x) << S_ACTIVEFILTERCOUNTS)
21704 #define F_ACTIVEFILTERCOUNTS    V_ACTIVEFILTERCOUNTS(1U)
21705 
21706 #define A_TP_DB_CONFIG 0x7d0c
21707 
21708 #define S_DBMAXOPCNT    24
21709 #define M_DBMAXOPCNT    0xffU
21710 #define V_DBMAXOPCNT(x) ((x) << S_DBMAXOPCNT)
21711 #define G_DBMAXOPCNT(x) (((x) >> S_DBMAXOPCNT) & M_DBMAXOPCNT)
21712 
21713 #define S_CXMAXOPCNTDISABLE    23
21714 #define V_CXMAXOPCNTDISABLE(x) ((x) << S_CXMAXOPCNTDISABLE)
21715 #define F_CXMAXOPCNTDISABLE    V_CXMAXOPCNTDISABLE(1U)
21716 
21717 #define S_CXMAXOPCNT    16
21718 #define M_CXMAXOPCNT    0x7fU
21719 #define V_CXMAXOPCNT(x) ((x) << S_CXMAXOPCNT)
21720 #define G_CXMAXOPCNT(x) (((x) >> S_CXMAXOPCNT) & M_CXMAXOPCNT)
21721 
21722 #define S_TXMAXOPCNTDISABLE    15
21723 #define V_TXMAXOPCNTDISABLE(x) ((x) << S_TXMAXOPCNTDISABLE)
21724 #define F_TXMAXOPCNTDISABLE    V_TXMAXOPCNTDISABLE(1U)
21725 
21726 #define S_TXMAXOPCNT    8
21727 #define M_TXMAXOPCNT    0x7fU
21728 #define V_TXMAXOPCNT(x) ((x) << S_TXMAXOPCNT)
21729 #define G_TXMAXOPCNT(x) (((x) >> S_TXMAXOPCNT) & M_TXMAXOPCNT)
21730 
21731 #define S_RXMAXOPCNTDISABLE    7
21732 #define V_RXMAXOPCNTDISABLE(x) ((x) << S_RXMAXOPCNTDISABLE)
21733 #define F_RXMAXOPCNTDISABLE    V_RXMAXOPCNTDISABLE(1U)
21734 
21735 #define S_RXMAXOPCNT    0
21736 #define M_RXMAXOPCNT    0x7fU
21737 #define V_RXMAXOPCNT(x) ((x) << S_RXMAXOPCNT)
21738 #define G_RXMAXOPCNT(x) (((x) >> S_RXMAXOPCNT) & M_RXMAXOPCNT)
21739 
21740 #define A_TP_CMM_TCB_BASE 0x7d10
21741 #define A_TP_CMM_MM_BASE 0x7d14
21742 #define A_TP_CMM_TIMER_BASE 0x7d18
21743 #define A_TP_CMM_MM_FLST_SIZE 0x7d1c
21744 
21745 #define S_RXPOOLSIZE    16
21746 #define M_RXPOOLSIZE    0xffffU
21747 #define V_RXPOOLSIZE(x) ((x) << S_RXPOOLSIZE)
21748 #define G_RXPOOLSIZE(x) (((x) >> S_RXPOOLSIZE) & M_RXPOOLSIZE)
21749 
21750 #define S_TXPOOLSIZE    0
21751 #define M_TXPOOLSIZE    0xffffU
21752 #define V_TXPOOLSIZE(x) ((x) << S_TXPOOLSIZE)
21753 #define G_TXPOOLSIZE(x) (((x) >> S_TXPOOLSIZE) & M_TXPOOLSIZE)
21754 
21755 #define A_TP_PMM_TX_BASE 0x7d20
21756 #define A_TP_PMM_DEFRAG_BASE 0x7d24
21757 #define A_TP_PMM_RX_BASE 0x7d28
21758 #define A_TP_PMM_RX_PAGE_SIZE 0x7d2c
21759 #define A_TP_PMM_RX_MAX_PAGE 0x7d30
21760 
21761 #define S_PMRXNUMCHN    31
21762 #define V_PMRXNUMCHN(x) ((x) << S_PMRXNUMCHN)
21763 #define F_PMRXNUMCHN    V_PMRXNUMCHN(1U)
21764 
21765 #define S_PMRXMAXPAGE    0
21766 #define M_PMRXMAXPAGE    0x1fffffU
21767 #define V_PMRXMAXPAGE(x) ((x) << S_PMRXMAXPAGE)
21768 #define G_PMRXMAXPAGE(x) (((x) >> S_PMRXMAXPAGE) & M_PMRXMAXPAGE)
21769 
21770 #define A_TP_PMM_TX_PAGE_SIZE 0x7d34
21771 #define A_TP_PMM_TX_MAX_PAGE 0x7d38
21772 
21773 #define S_PMTXNUMCHN    30
21774 #define M_PMTXNUMCHN    0x3U
21775 #define V_PMTXNUMCHN(x) ((x) << S_PMTXNUMCHN)
21776 #define G_PMTXNUMCHN(x) (((x) >> S_PMTXNUMCHN) & M_PMTXNUMCHN)
21777 
21778 #define S_PMTXMAXPAGE    0
21779 #define M_PMTXMAXPAGE    0x1fffffU
21780 #define V_PMTXMAXPAGE(x) ((x) << S_PMTXMAXPAGE)
21781 #define G_PMTXMAXPAGE(x) (((x) >> S_PMTXMAXPAGE) & M_PMTXMAXPAGE)
21782 
21783 #define A_TP_TCP_OPTIONS 0x7d40
21784 
21785 #define S_MTUDEFAULT    16
21786 #define M_MTUDEFAULT    0xffffU
21787 #define V_MTUDEFAULT(x) ((x) << S_MTUDEFAULT)
21788 #define G_MTUDEFAULT(x) (((x) >> S_MTUDEFAULT) & M_MTUDEFAULT)
21789 
21790 #define S_MTUENABLE    10
21791 #define V_MTUENABLE(x) ((x) << S_MTUENABLE)
21792 #define F_MTUENABLE    V_MTUENABLE(1U)
21793 
21794 #define S_SACKTX    9
21795 #define V_SACKTX(x) ((x) << S_SACKTX)
21796 #define F_SACKTX    V_SACKTX(1U)
21797 
21798 #define S_SACKRX    8
21799 #define V_SACKRX(x) ((x) << S_SACKRX)
21800 #define F_SACKRX    V_SACKRX(1U)
21801 
21802 #define S_SACKMODE    4
21803 #define M_SACKMODE    0x3U
21804 #define V_SACKMODE(x) ((x) << S_SACKMODE)
21805 #define G_SACKMODE(x) (((x) >> S_SACKMODE) & M_SACKMODE)
21806 
21807 #define S_WINDOWSCALEMODE    2
21808 #define M_WINDOWSCALEMODE    0x3U
21809 #define V_WINDOWSCALEMODE(x) ((x) << S_WINDOWSCALEMODE)
21810 #define G_WINDOWSCALEMODE(x) (((x) >> S_WINDOWSCALEMODE) & M_WINDOWSCALEMODE)
21811 
21812 #define S_TIMESTAMPSMODE    0
21813 #define M_TIMESTAMPSMODE    0x3U
21814 #define V_TIMESTAMPSMODE(x) ((x) << S_TIMESTAMPSMODE)
21815 #define G_TIMESTAMPSMODE(x) (((x) >> S_TIMESTAMPSMODE) & M_TIMESTAMPSMODE)
21816 
21817 #define A_TP_DACK_CONFIG 0x7d44
21818 
21819 #define S_AUTOSTATE3    30
21820 #define M_AUTOSTATE3    0x3U
21821 #define V_AUTOSTATE3(x) ((x) << S_AUTOSTATE3)
21822 #define G_AUTOSTATE3(x) (((x) >> S_AUTOSTATE3) & M_AUTOSTATE3)
21823 
21824 #define S_AUTOSTATE2    28
21825 #define M_AUTOSTATE2    0x3U
21826 #define V_AUTOSTATE2(x) ((x) << S_AUTOSTATE2)
21827 #define G_AUTOSTATE2(x) (((x) >> S_AUTOSTATE2) & M_AUTOSTATE2)
21828 
21829 #define S_AUTOSTATE1    26
21830 #define M_AUTOSTATE1    0x3U
21831 #define V_AUTOSTATE1(x) ((x) << S_AUTOSTATE1)
21832 #define G_AUTOSTATE1(x) (((x) >> S_AUTOSTATE1) & M_AUTOSTATE1)
21833 
21834 #define S_BYTETHRESHOLD    8
21835 #define M_BYTETHRESHOLD    0x3ffffU
21836 #define V_BYTETHRESHOLD(x) ((x) << S_BYTETHRESHOLD)
21837 #define G_BYTETHRESHOLD(x) (((x) >> S_BYTETHRESHOLD) & M_BYTETHRESHOLD)
21838 
21839 #define S_MSSTHRESHOLD    4
21840 #define M_MSSTHRESHOLD    0x7U
21841 #define V_MSSTHRESHOLD(x) ((x) << S_MSSTHRESHOLD)
21842 #define G_MSSTHRESHOLD(x) (((x) >> S_MSSTHRESHOLD) & M_MSSTHRESHOLD)
21843 
21844 #define S_AUTOCAREFUL    2
21845 #define V_AUTOCAREFUL(x) ((x) << S_AUTOCAREFUL)
21846 #define F_AUTOCAREFUL    V_AUTOCAREFUL(1U)
21847 
21848 #define S_AUTOENABLE    1
21849 #define V_AUTOENABLE(x) ((x) << S_AUTOENABLE)
21850 #define F_AUTOENABLE    V_AUTOENABLE(1U)
21851 
21852 #define S_MODE    0
21853 #define V_MODE(x) ((x) << S_MODE)
21854 #define F_MODE    V_MODE(1U)
21855 
21856 #define A_TP_PC_CONFIG 0x7d48
21857 
21858 #define S_CMCACHEDISABLE    31
21859 #define V_CMCACHEDISABLE(x) ((x) << S_CMCACHEDISABLE)
21860 #define F_CMCACHEDISABLE    V_CMCACHEDISABLE(1U)
21861 
21862 #define S_ENABLEOCSPIFULL    30
21863 #define V_ENABLEOCSPIFULL(x) ((x) << S_ENABLEOCSPIFULL)
21864 #define F_ENABLEOCSPIFULL    V_ENABLEOCSPIFULL(1U)
21865 
21866 #define S_ENABLEFLMERRORDDP    29
21867 #define V_ENABLEFLMERRORDDP(x) ((x) << S_ENABLEFLMERRORDDP)
21868 #define F_ENABLEFLMERRORDDP    V_ENABLEFLMERRORDDP(1U)
21869 
21870 #define S_LOCKTID    28
21871 #define V_LOCKTID(x) ((x) << S_LOCKTID)
21872 #define F_LOCKTID    V_LOCKTID(1U)
21873 
21874 #define S_DISABLEINVPEND    27
21875 #define V_DISABLEINVPEND(x) ((x) << S_DISABLEINVPEND)
21876 #define F_DISABLEINVPEND    V_DISABLEINVPEND(1U)
21877 
21878 #define S_ENABLEFILTERCOUNT    26
21879 #define V_ENABLEFILTERCOUNT(x) ((x) << S_ENABLEFILTERCOUNT)
21880 #define F_ENABLEFILTERCOUNT    V_ENABLEFILTERCOUNT(1U)
21881 
21882 #define S_RDDPCONGEN    25
21883 #define V_RDDPCONGEN(x) ((x) << S_RDDPCONGEN)
21884 #define F_RDDPCONGEN    V_RDDPCONGEN(1U)
21885 
21886 #define S_ENABLEONFLYPDU    24
21887 #define V_ENABLEONFLYPDU(x) ((x) << S_ENABLEONFLYPDU)
21888 #define F_ENABLEONFLYPDU    V_ENABLEONFLYPDU(1U)
21889 
21890 #define S_ENABLEMINRCVWND    23
21891 #define V_ENABLEMINRCVWND(x) ((x) << S_ENABLEMINRCVWND)
21892 #define F_ENABLEMINRCVWND    V_ENABLEMINRCVWND(1U)
21893 
21894 #define S_ENABLEMAXRCVWND    22
21895 #define V_ENABLEMAXRCVWND(x) ((x) << S_ENABLEMAXRCVWND)
21896 #define F_ENABLEMAXRCVWND    V_ENABLEMAXRCVWND(1U)
21897 
21898 #define S_TXDATAACKRATEENABLE    21
21899 #define V_TXDATAACKRATEENABLE(x) ((x) << S_TXDATAACKRATEENABLE)
21900 #define F_TXDATAACKRATEENABLE    V_TXDATAACKRATEENABLE(1U)
21901 
21902 #define S_TXDEFERENABLE    20
21903 #define V_TXDEFERENABLE(x) ((x) << S_TXDEFERENABLE)
21904 #define F_TXDEFERENABLE    V_TXDEFERENABLE(1U)
21905 
21906 #define S_RXCONGESTIONMODE    19
21907 #define V_RXCONGESTIONMODE(x) ((x) << S_RXCONGESTIONMODE)
21908 #define F_RXCONGESTIONMODE    V_RXCONGESTIONMODE(1U)
21909 
21910 #define S_HEARBEATONCEDACK    18
21911 #define V_HEARBEATONCEDACK(x) ((x) << S_HEARBEATONCEDACK)
21912 #define F_HEARBEATONCEDACK    V_HEARBEATONCEDACK(1U)
21913 
21914 #define S_HEARBEATONCEHEAP    17
21915 #define V_HEARBEATONCEHEAP(x) ((x) << S_HEARBEATONCEHEAP)
21916 #define F_HEARBEATONCEHEAP    V_HEARBEATONCEHEAP(1U)
21917 
21918 #define S_HEARBEATDACK    16
21919 #define V_HEARBEATDACK(x) ((x) << S_HEARBEATDACK)
21920 #define F_HEARBEATDACK    V_HEARBEATDACK(1U)
21921 
21922 #define S_TXCONGESTIONMODE    15
21923 #define V_TXCONGESTIONMODE(x) ((x) << S_TXCONGESTIONMODE)
21924 #define F_TXCONGESTIONMODE    V_TXCONGESTIONMODE(1U)
21925 
21926 #define S_ACCEPTLATESTRCVADV    14
21927 #define V_ACCEPTLATESTRCVADV(x) ((x) << S_ACCEPTLATESTRCVADV)
21928 #define F_ACCEPTLATESTRCVADV    V_ACCEPTLATESTRCVADV(1U)
21929 
21930 #define S_DISABLESYNDATA    13
21931 #define V_DISABLESYNDATA(x) ((x) << S_DISABLESYNDATA)
21932 #define F_DISABLESYNDATA    V_DISABLESYNDATA(1U)
21933 
21934 #define S_DISABLEWINDOWPSH    12
21935 #define V_DISABLEWINDOWPSH(x) ((x) << S_DISABLEWINDOWPSH)
21936 #define F_DISABLEWINDOWPSH    V_DISABLEWINDOWPSH(1U)
21937 
21938 #define S_DISABLEFINOLDDATA    11
21939 #define V_DISABLEFINOLDDATA(x) ((x) << S_DISABLEFINOLDDATA)
21940 #define F_DISABLEFINOLDDATA    V_DISABLEFINOLDDATA(1U)
21941 
21942 #define S_ENABLEFLMERROR    10
21943 #define V_ENABLEFLMERROR(x) ((x) << S_ENABLEFLMERROR)
21944 #define F_ENABLEFLMERROR    V_ENABLEFLMERROR(1U)
21945 
21946 #define S_ENABLEOPTMTU    9
21947 #define V_ENABLEOPTMTU(x) ((x) << S_ENABLEOPTMTU)
21948 #define F_ENABLEOPTMTU    V_ENABLEOPTMTU(1U)
21949 
21950 #define S_FILTERPEERFIN    8
21951 #define V_FILTERPEERFIN(x) ((x) << S_FILTERPEERFIN)
21952 #define F_FILTERPEERFIN    V_FILTERPEERFIN(1U)
21953 
21954 #define S_ENABLEFEEDBACKSEND    7
21955 #define V_ENABLEFEEDBACKSEND(x) ((x) << S_ENABLEFEEDBACKSEND)
21956 #define F_ENABLEFEEDBACKSEND    V_ENABLEFEEDBACKSEND(1U)
21957 
21958 #define S_ENABLERDMAERROR    6
21959 #define V_ENABLERDMAERROR(x) ((x) << S_ENABLERDMAERROR)
21960 #define F_ENABLERDMAERROR    V_ENABLERDMAERROR(1U)
21961 
21962 #define S_ENABLEDDPFLOWCONTROL    5
21963 #define V_ENABLEDDPFLOWCONTROL(x) ((x) << S_ENABLEDDPFLOWCONTROL)
21964 #define F_ENABLEDDPFLOWCONTROL    V_ENABLEDDPFLOWCONTROL(1U)
21965 
21966 #define S_DISABLEHELDFIN    4
21967 #define V_DISABLEHELDFIN(x) ((x) << S_DISABLEHELDFIN)
21968 #define F_DISABLEHELDFIN    V_DISABLEHELDFIN(1U)
21969 
21970 #define S_ENABLEOFDOVLAN    3
21971 #define V_ENABLEOFDOVLAN(x) ((x) << S_ENABLEOFDOVLAN)
21972 #define F_ENABLEOFDOVLAN    V_ENABLEOFDOVLAN(1U)
21973 
21974 #define S_DISABLETIMEWAIT    2
21975 #define V_DISABLETIMEWAIT(x) ((x) << S_DISABLETIMEWAIT)
21976 #define F_DISABLETIMEWAIT    V_DISABLETIMEWAIT(1U)
21977 
21978 #define S_ENABLEVLANCHECK    1
21979 #define V_ENABLEVLANCHECK(x) ((x) << S_ENABLEVLANCHECK)
21980 #define F_ENABLEVLANCHECK    V_ENABLEVLANCHECK(1U)
21981 
21982 #define S_TXDATAACKPAGEENABLE    0
21983 #define V_TXDATAACKPAGEENABLE(x) ((x) << S_TXDATAACKPAGEENABLE)
21984 #define F_TXDATAACKPAGEENABLE    V_TXDATAACKPAGEENABLE(1U)
21985 
21986 #define S_ENABLEFILTERNAT    5
21987 #define V_ENABLEFILTERNAT(x) ((x) << S_ENABLEFILTERNAT)
21988 #define F_ENABLEFILTERNAT    V_ENABLEFILTERNAT(1U)
21989 
21990 #define S_ENABLEFINCHECK    31
21991 #define V_ENABLEFINCHECK(x) ((x) << S_ENABLEFINCHECK)
21992 #define F_ENABLEFINCHECK    V_ENABLEFINCHECK(1U)
21993 
21994 #define S_ENABLEMIBVFPLD    21
21995 #define V_ENABLEMIBVFPLD(x) ((x) << S_ENABLEMIBVFPLD)
21996 #define F_ENABLEMIBVFPLD    V_ENABLEMIBVFPLD(1U)
21997 
21998 #define S_DISABLESEPPSHFLAG    4
21999 #define V_DISABLESEPPSHFLAG(x) ((x) << S_DISABLESEPPSHFLAG)
22000 #define F_DISABLESEPPSHFLAG    V_DISABLESEPPSHFLAG(1U)
22001 
22002 #define A_TP_PC_CONFIG2 0x7d4c
22003 
22004 #define S_ENABLEMTUVFMODE    31
22005 #define V_ENABLEMTUVFMODE(x) ((x) << S_ENABLEMTUVFMODE)
22006 #define F_ENABLEMTUVFMODE    V_ENABLEMTUVFMODE(1U)
22007 
22008 #define S_ENABLEMIBVFMODE    30
22009 #define V_ENABLEMIBVFMODE(x) ((x) << S_ENABLEMIBVFMODE)
22010 #define F_ENABLEMIBVFMODE    V_ENABLEMIBVFMODE(1U)
22011 
22012 #define S_DISABLELBKCHECK    29
22013 #define V_DISABLELBKCHECK(x) ((x) << S_DISABLELBKCHECK)
22014 #define F_DISABLELBKCHECK    V_DISABLELBKCHECK(1U)
22015 
22016 #define S_ENABLEURGDDPOFF    28
22017 #define V_ENABLEURGDDPOFF(x) ((x) << S_ENABLEURGDDPOFF)
22018 #define F_ENABLEURGDDPOFF    V_ENABLEURGDDPOFF(1U)
22019 
22020 #define S_ENABLEFILTERLPBK    27
22021 #define V_ENABLEFILTERLPBK(x) ((x) << S_ENABLEFILTERLPBK)
22022 #define F_ENABLEFILTERLPBK    V_ENABLEFILTERLPBK(1U)
22023 
22024 #define S_DISABLETBLMMGR    26
22025 #define V_DISABLETBLMMGR(x) ((x) << S_DISABLETBLMMGR)
22026 #define F_DISABLETBLMMGR    V_DISABLETBLMMGR(1U)
22027 
22028 #define S_CNGRECSNDNXT    25
22029 #define V_CNGRECSNDNXT(x) ((x) << S_CNGRECSNDNXT)
22030 #define F_CNGRECSNDNXT    V_CNGRECSNDNXT(1U)
22031 
22032 #define S_ENABLELBKCHN    24
22033 #define V_ENABLELBKCHN(x) ((x) << S_ENABLELBKCHN)
22034 #define F_ENABLELBKCHN    V_ENABLELBKCHN(1U)
22035 
22036 #define S_ENABLELROECN    23
22037 #define V_ENABLELROECN(x) ((x) << S_ENABLELROECN)
22038 #define F_ENABLELROECN    V_ENABLELROECN(1U)
22039 
22040 #define S_ENABLEPCMDCHECK    22
22041 #define V_ENABLEPCMDCHECK(x) ((x) << S_ENABLEPCMDCHECK)
22042 #define F_ENABLEPCMDCHECK    V_ENABLEPCMDCHECK(1U)
22043 
22044 #define S_ENABLEELBKAFULL    21
22045 #define V_ENABLEELBKAFULL(x) ((x) << S_ENABLEELBKAFULL)
22046 #define F_ENABLEELBKAFULL    V_ENABLEELBKAFULL(1U)
22047 
22048 #define S_ENABLECLBKAFULL    20
22049 #define V_ENABLECLBKAFULL(x) ((x) << S_ENABLECLBKAFULL)
22050 #define F_ENABLECLBKAFULL    V_ENABLECLBKAFULL(1U)
22051 
22052 #define S_ENABLEOESPIFULL    19
22053 #define V_ENABLEOESPIFULL(x) ((x) << S_ENABLEOESPIFULL)
22054 #define F_ENABLEOESPIFULL    V_ENABLEOESPIFULL(1U)
22055 
22056 #define S_DISABLEHITCHECK    18
22057 #define V_DISABLEHITCHECK(x) ((x) << S_DISABLEHITCHECK)
22058 #define F_DISABLEHITCHECK    V_DISABLEHITCHECK(1U)
22059 
22060 #define S_ENABLERSSERRCHECK    17
22061 #define V_ENABLERSSERRCHECK(x) ((x) << S_ENABLERSSERRCHECK)
22062 #define F_ENABLERSSERRCHECK    V_ENABLERSSERRCHECK(1U)
22063 
22064 #define S_DISABLENEWPSHFLAG    16
22065 #define V_DISABLENEWPSHFLAG(x) ((x) << S_DISABLENEWPSHFLAG)
22066 #define F_DISABLENEWPSHFLAG    V_DISABLENEWPSHFLAG(1U)
22067 
22068 #define S_ENABLERDDPRCVADVCLR    15
22069 #define V_ENABLERDDPRCVADVCLR(x) ((x) << S_ENABLERDDPRCVADVCLR)
22070 #define F_ENABLERDDPRCVADVCLR    V_ENABLERDDPRCVADVCLR(1U)
22071 
22072 #define S_ENABLETXDATAARPMISS    14
22073 #define V_ENABLETXDATAARPMISS(x) ((x) << S_ENABLETXDATAARPMISS)
22074 #define F_ENABLETXDATAARPMISS    V_ENABLETXDATAARPMISS(1U)
22075 
22076 #define S_ENABLEARPMISS    13
22077 #define V_ENABLEARPMISS(x) ((x) << S_ENABLEARPMISS)
22078 #define F_ENABLEARPMISS    V_ENABLEARPMISS(1U)
22079 
22080 #define S_ENABLERSTPAWS    12
22081 #define V_ENABLERSTPAWS(x) ((x) << S_ENABLERSTPAWS)
22082 #define F_ENABLERSTPAWS    V_ENABLERSTPAWS(1U)
22083 
22084 #define S_ENABLEIPV6RSS    11
22085 #define V_ENABLEIPV6RSS(x) ((x) << S_ENABLEIPV6RSS)
22086 #define F_ENABLEIPV6RSS    V_ENABLEIPV6RSS(1U)
22087 
22088 #define S_ENABLENONOFDHYBRSS    10
22089 #define V_ENABLENONOFDHYBRSS(x) ((x) << S_ENABLENONOFDHYBRSS)
22090 #define F_ENABLENONOFDHYBRSS    V_ENABLENONOFDHYBRSS(1U)
22091 
22092 #define S_ENABLEUDP4TUPRSS    9
22093 #define V_ENABLEUDP4TUPRSS(x) ((x) << S_ENABLEUDP4TUPRSS)
22094 #define F_ENABLEUDP4TUPRSS    V_ENABLEUDP4TUPRSS(1U)
22095 
22096 #define S_ENABLERXPKTTMSTPRSS    8
22097 #define V_ENABLERXPKTTMSTPRSS(x) ((x) << S_ENABLERXPKTTMSTPRSS)
22098 #define F_ENABLERXPKTTMSTPRSS    V_ENABLERXPKTTMSTPRSS(1U)
22099 
22100 #define S_ENABLEEPCMDAFULL    7
22101 #define V_ENABLEEPCMDAFULL(x) ((x) << S_ENABLEEPCMDAFULL)
22102 #define F_ENABLEEPCMDAFULL    V_ENABLEEPCMDAFULL(1U)
22103 
22104 #define S_ENABLECPCMDAFULL    6
22105 #define V_ENABLECPCMDAFULL(x) ((x) << S_ENABLECPCMDAFULL)
22106 #define F_ENABLECPCMDAFULL    V_ENABLECPCMDAFULL(1U)
22107 
22108 #define S_ENABLEEHDRAFULL    5
22109 #define V_ENABLEEHDRAFULL(x) ((x) << S_ENABLEEHDRAFULL)
22110 #define F_ENABLEEHDRAFULL    V_ENABLEEHDRAFULL(1U)
22111 
22112 #define S_ENABLECHDRAFULL    4
22113 #define V_ENABLECHDRAFULL(x) ((x) << S_ENABLECHDRAFULL)
22114 #define F_ENABLECHDRAFULL    V_ENABLECHDRAFULL(1U)
22115 
22116 #define S_ENABLEEMACAFULL    3
22117 #define V_ENABLEEMACAFULL(x) ((x) << S_ENABLEEMACAFULL)
22118 #define F_ENABLEEMACAFULL    V_ENABLEEMACAFULL(1U)
22119 
22120 #define S_ENABLENONOFDTIDRSS    2
22121 #define V_ENABLENONOFDTIDRSS(x) ((x) << S_ENABLENONOFDTIDRSS)
22122 #define F_ENABLENONOFDTIDRSS    V_ENABLENONOFDTIDRSS(1U)
22123 
22124 #define S_ENABLENONOFDTCBRSS    1
22125 #define V_ENABLENONOFDTCBRSS(x) ((x) << S_ENABLENONOFDTCBRSS)
22126 #define F_ENABLENONOFDTCBRSS    V_ENABLENONOFDTCBRSS(1U)
22127 
22128 #define S_ENABLETNLOFDCLOSED    0
22129 #define V_ENABLETNLOFDCLOSED(x) ((x) << S_ENABLETNLOFDCLOSED)
22130 #define F_ENABLETNLOFDCLOSED    V_ENABLETNLOFDCLOSED(1U)
22131 
22132 #define S_ENABLEFINDDPOFF    14
22133 #define V_ENABLEFINDDPOFF(x) ((x) << S_ENABLEFINDDPOFF)
22134 #define F_ENABLEFINDDPOFF    V_ENABLEFINDDPOFF(1U)
22135 
22136 #define A_TP_TCP_BACKOFF_REG0 0x7d50
22137 
22138 #define S_TIMERBACKOFFINDEX3    24
22139 #define M_TIMERBACKOFFINDEX3    0xffU
22140 #define V_TIMERBACKOFFINDEX3(x) ((x) << S_TIMERBACKOFFINDEX3)
22141 #define G_TIMERBACKOFFINDEX3(x) (((x) >> S_TIMERBACKOFFINDEX3) & M_TIMERBACKOFFINDEX3)
22142 
22143 #define S_TIMERBACKOFFINDEX2    16
22144 #define M_TIMERBACKOFFINDEX2    0xffU
22145 #define V_TIMERBACKOFFINDEX2(x) ((x) << S_TIMERBACKOFFINDEX2)
22146 #define G_TIMERBACKOFFINDEX2(x) (((x) >> S_TIMERBACKOFFINDEX2) & M_TIMERBACKOFFINDEX2)
22147 
22148 #define S_TIMERBACKOFFINDEX1    8
22149 #define M_TIMERBACKOFFINDEX1    0xffU
22150 #define V_TIMERBACKOFFINDEX1(x) ((x) << S_TIMERBACKOFFINDEX1)
22151 #define G_TIMERBACKOFFINDEX1(x) (((x) >> S_TIMERBACKOFFINDEX1) & M_TIMERBACKOFFINDEX1)
22152 
22153 #define S_TIMERBACKOFFINDEX0    0
22154 #define M_TIMERBACKOFFINDEX0    0xffU
22155 #define V_TIMERBACKOFFINDEX0(x) ((x) << S_TIMERBACKOFFINDEX0)
22156 #define G_TIMERBACKOFFINDEX0(x) (((x) >> S_TIMERBACKOFFINDEX0) & M_TIMERBACKOFFINDEX0)
22157 
22158 #define A_TP_TCP_BACKOFF_REG1 0x7d54
22159 
22160 #define S_TIMERBACKOFFINDEX7    24
22161 #define M_TIMERBACKOFFINDEX7    0xffU
22162 #define V_TIMERBACKOFFINDEX7(x) ((x) << S_TIMERBACKOFFINDEX7)
22163 #define G_TIMERBACKOFFINDEX7(x) (((x) >> S_TIMERBACKOFFINDEX7) & M_TIMERBACKOFFINDEX7)
22164 
22165 #define S_TIMERBACKOFFINDEX6    16
22166 #define M_TIMERBACKOFFINDEX6    0xffU
22167 #define V_TIMERBACKOFFINDEX6(x) ((x) << S_TIMERBACKOFFINDEX6)
22168 #define G_TIMERBACKOFFINDEX6(x) (((x) >> S_TIMERBACKOFFINDEX6) & M_TIMERBACKOFFINDEX6)
22169 
22170 #define S_TIMERBACKOFFINDEX5    8
22171 #define M_TIMERBACKOFFINDEX5    0xffU
22172 #define V_TIMERBACKOFFINDEX5(x) ((x) << S_TIMERBACKOFFINDEX5)
22173 #define G_TIMERBACKOFFINDEX5(x) (((x) >> S_TIMERBACKOFFINDEX5) & M_TIMERBACKOFFINDEX5)
22174 
22175 #define S_TIMERBACKOFFINDEX4    0
22176 #define M_TIMERBACKOFFINDEX4    0xffU
22177 #define V_TIMERBACKOFFINDEX4(x) ((x) << S_TIMERBACKOFFINDEX4)
22178 #define G_TIMERBACKOFFINDEX4(x) (((x) >> S_TIMERBACKOFFINDEX4) & M_TIMERBACKOFFINDEX4)
22179 
22180 #define A_TP_TCP_BACKOFF_REG2 0x7d58
22181 
22182 #define S_TIMERBACKOFFINDEX11    24
22183 #define M_TIMERBACKOFFINDEX11    0xffU
22184 #define V_TIMERBACKOFFINDEX11(x) ((x) << S_TIMERBACKOFFINDEX11)
22185 #define G_TIMERBACKOFFINDEX11(x) (((x) >> S_TIMERBACKOFFINDEX11) & M_TIMERBACKOFFINDEX11)
22186 
22187 #define S_TIMERBACKOFFINDEX10    16
22188 #define M_TIMERBACKOFFINDEX10    0xffU
22189 #define V_TIMERBACKOFFINDEX10(x) ((x) << S_TIMERBACKOFFINDEX10)
22190 #define G_TIMERBACKOFFINDEX10(x) (((x) >> S_TIMERBACKOFFINDEX10) & M_TIMERBACKOFFINDEX10)
22191 
22192 #define S_TIMERBACKOFFINDEX9    8
22193 #define M_TIMERBACKOFFINDEX9    0xffU
22194 #define V_TIMERBACKOFFINDEX9(x) ((x) << S_TIMERBACKOFFINDEX9)
22195 #define G_TIMERBACKOFFINDEX9(x) (((x) >> S_TIMERBACKOFFINDEX9) & M_TIMERBACKOFFINDEX9)
22196 
22197 #define S_TIMERBACKOFFINDEX8    0
22198 #define M_TIMERBACKOFFINDEX8    0xffU
22199 #define V_TIMERBACKOFFINDEX8(x) ((x) << S_TIMERBACKOFFINDEX8)
22200 #define G_TIMERBACKOFFINDEX8(x) (((x) >> S_TIMERBACKOFFINDEX8) & M_TIMERBACKOFFINDEX8)
22201 
22202 #define A_TP_TCP_BACKOFF_REG3 0x7d5c
22203 
22204 #define S_TIMERBACKOFFINDEX15    24
22205 #define M_TIMERBACKOFFINDEX15    0xffU
22206 #define V_TIMERBACKOFFINDEX15(x) ((x) << S_TIMERBACKOFFINDEX15)
22207 #define G_TIMERBACKOFFINDEX15(x) (((x) >> S_TIMERBACKOFFINDEX15) & M_TIMERBACKOFFINDEX15)
22208 
22209 #define S_TIMERBACKOFFINDEX14    16
22210 #define M_TIMERBACKOFFINDEX14    0xffU
22211 #define V_TIMERBACKOFFINDEX14(x) ((x) << S_TIMERBACKOFFINDEX14)
22212 #define G_TIMERBACKOFFINDEX14(x) (((x) >> S_TIMERBACKOFFINDEX14) & M_TIMERBACKOFFINDEX14)
22213 
22214 #define S_TIMERBACKOFFINDEX13    8
22215 #define M_TIMERBACKOFFINDEX13    0xffU
22216 #define V_TIMERBACKOFFINDEX13(x) ((x) << S_TIMERBACKOFFINDEX13)
22217 #define G_TIMERBACKOFFINDEX13(x) (((x) >> S_TIMERBACKOFFINDEX13) & M_TIMERBACKOFFINDEX13)
22218 
22219 #define S_TIMERBACKOFFINDEX12    0
22220 #define M_TIMERBACKOFFINDEX12    0xffU
22221 #define V_TIMERBACKOFFINDEX12(x) ((x) << S_TIMERBACKOFFINDEX12)
22222 #define G_TIMERBACKOFFINDEX12(x) (((x) >> S_TIMERBACKOFFINDEX12) & M_TIMERBACKOFFINDEX12)
22223 
22224 #define A_TP_PARA_REG0 0x7d60
22225 
22226 #define S_INITCWNDIDLE    27
22227 #define V_INITCWNDIDLE(x) ((x) << S_INITCWNDIDLE)
22228 #define F_INITCWNDIDLE    V_INITCWNDIDLE(1U)
22229 
22230 #define S_INITCWND    24
22231 #define M_INITCWND    0x7U
22232 #define V_INITCWND(x) ((x) << S_INITCWND)
22233 #define G_INITCWND(x) (((x) >> S_INITCWND) & M_INITCWND)
22234 
22235 #define S_DUPACKTHRESH    20
22236 #define M_DUPACKTHRESH    0xfU
22237 #define V_DUPACKTHRESH(x) ((x) << S_DUPACKTHRESH)
22238 #define G_DUPACKTHRESH(x) (((x) >> S_DUPACKTHRESH) & M_DUPACKTHRESH)
22239 
22240 #define S_CPLERRENABLE    12
22241 #define V_CPLERRENABLE(x) ((x) << S_CPLERRENABLE)
22242 #define F_CPLERRENABLE    V_CPLERRENABLE(1U)
22243 
22244 #define S_FASTTNLCNT    11
22245 #define V_FASTTNLCNT(x) ((x) << S_FASTTNLCNT)
22246 #define F_FASTTNLCNT    V_FASTTNLCNT(1U)
22247 
22248 #define S_FASTTBLCNT    10
22249 #define V_FASTTBLCNT(x) ((x) << S_FASTTBLCNT)
22250 #define F_FASTTBLCNT    V_FASTTBLCNT(1U)
22251 
22252 #define S_TPTCAMKEY    9
22253 #define V_TPTCAMKEY(x) ((x) << S_TPTCAMKEY)
22254 #define F_TPTCAMKEY    V_TPTCAMKEY(1U)
22255 
22256 #define S_SWSMODE    8
22257 #define V_SWSMODE(x) ((x) << S_SWSMODE)
22258 #define F_SWSMODE    V_SWSMODE(1U)
22259 
22260 #define S_TSMPMODE    6
22261 #define M_TSMPMODE    0x3U
22262 #define V_TSMPMODE(x) ((x) << S_TSMPMODE)
22263 #define G_TSMPMODE(x) (((x) >> S_TSMPMODE) & M_TSMPMODE)
22264 
22265 #define S_BYTECOUNTLIMIT    4
22266 #define M_BYTECOUNTLIMIT    0x3U
22267 #define V_BYTECOUNTLIMIT(x) ((x) << S_BYTECOUNTLIMIT)
22268 #define G_BYTECOUNTLIMIT(x) (((x) >> S_BYTECOUNTLIMIT) & M_BYTECOUNTLIMIT)
22269 
22270 #define S_SWSSHOVE    3
22271 #define V_SWSSHOVE(x) ((x) << S_SWSSHOVE)
22272 #define F_SWSSHOVE    V_SWSSHOVE(1U)
22273 
22274 #define S_TBLTIMER    2
22275 #define V_TBLTIMER(x) ((x) << S_TBLTIMER)
22276 #define F_TBLTIMER    V_TBLTIMER(1U)
22277 
22278 #define S_RXTPACE    1
22279 #define V_RXTPACE(x) ((x) << S_RXTPACE)
22280 #define F_RXTPACE    V_RXTPACE(1U)
22281 
22282 #define S_SWSTIMER    0
22283 #define V_SWSTIMER(x) ((x) << S_SWSTIMER)
22284 #define F_SWSTIMER    V_SWSTIMER(1U)
22285 
22286 #define S_LIMTXTHRESH    28
22287 #define M_LIMTXTHRESH    0xfU
22288 #define V_LIMTXTHRESH(x) ((x) << S_LIMTXTHRESH)
22289 #define G_LIMTXTHRESH(x) (((x) >> S_LIMTXTHRESH) & M_LIMTXTHRESH)
22290 
22291 #define S_CHNERRENABLE    14
22292 #define V_CHNERRENABLE(x) ((x) << S_CHNERRENABLE)
22293 #define F_CHNERRENABLE    V_CHNERRENABLE(1U)
22294 
22295 #define S_SETTIMEENABLE    13
22296 #define V_SETTIMEENABLE(x) ((x) << S_SETTIMEENABLE)
22297 #define F_SETTIMEENABLE    V_SETTIMEENABLE(1U)
22298 
22299 #define S_ECNCNGFIFO    19
22300 #define V_ECNCNGFIFO(x) ((x) << S_ECNCNGFIFO)
22301 #define F_ECNCNGFIFO    V_ECNCNGFIFO(1U)
22302 
22303 #define S_ECNSYNACK    18
22304 #define V_ECNSYNACK(x) ((x) << S_ECNSYNACK)
22305 #define F_ECNSYNACK    V_ECNSYNACK(1U)
22306 
22307 #define S_ECNTHRESH    16
22308 #define M_ECNTHRESH    0x3U
22309 #define V_ECNTHRESH(x) ((x) << S_ECNTHRESH)
22310 #define G_ECNTHRESH(x) (((x) >> S_ECNTHRESH) & M_ECNTHRESH)
22311 
22312 #define S_ECNMODE    15
22313 #define V_ECNMODE(x) ((x) << S_ECNMODE)
22314 #define F_ECNMODE    V_ECNMODE(1U)
22315 
22316 #define S_ECNMODECWR    14
22317 #define V_ECNMODECWR(x) ((x) << S_ECNMODECWR)
22318 #define F_ECNMODECWR    V_ECNMODECWR(1U)
22319 
22320 #define S_FORCESHOVE    10
22321 #define V_FORCESHOVE(x) ((x) << S_FORCESHOVE)
22322 #define F_FORCESHOVE    V_FORCESHOVE(1U)
22323 
22324 #define A_TP_PARA_REG1 0x7d64
22325 
22326 #define S_INITRWND    16
22327 #define M_INITRWND    0xffffU
22328 #define V_INITRWND(x) ((x) << S_INITRWND)
22329 #define G_INITRWND(x) (((x) >> S_INITRWND) & M_INITRWND)
22330 
22331 #define S_INITIALSSTHRESH    0
22332 #define M_INITIALSSTHRESH    0xffffU
22333 #define V_INITIALSSTHRESH(x) ((x) << S_INITIALSSTHRESH)
22334 #define G_INITIALSSTHRESH(x) (((x) >> S_INITIALSSTHRESH) & M_INITIALSSTHRESH)
22335 
22336 #define A_TP_PARA_REG2 0x7d68
22337 
22338 #define S_MAXRXDATA    16
22339 #define M_MAXRXDATA    0xffffU
22340 #define V_MAXRXDATA(x) ((x) << S_MAXRXDATA)
22341 #define G_MAXRXDATA(x) (((x) >> S_MAXRXDATA) & M_MAXRXDATA)
22342 
22343 #define S_RXCOALESCESIZE    0
22344 #define M_RXCOALESCESIZE    0xffffU
22345 #define V_RXCOALESCESIZE(x) ((x) << S_RXCOALESCESIZE)
22346 #define G_RXCOALESCESIZE(x) (((x) >> S_RXCOALESCESIZE) & M_RXCOALESCESIZE)
22347 
22348 #define A_TP_PARA_REG3 0x7d6c
22349 
22350 #define S_ENABLETNLCNGLPBK    31
22351 #define V_ENABLETNLCNGLPBK(x) ((x) << S_ENABLETNLCNGLPBK)
22352 #define F_ENABLETNLCNGLPBK    V_ENABLETNLCNGLPBK(1U)
22353 
22354 #define S_ENABLETNLCNGFIFO    30
22355 #define V_ENABLETNLCNGFIFO(x) ((x) << S_ENABLETNLCNGFIFO)
22356 #define F_ENABLETNLCNGFIFO    V_ENABLETNLCNGFIFO(1U)
22357 
22358 #define S_ENABLETNLCNGHDR    29
22359 #define V_ENABLETNLCNGHDR(x) ((x) << S_ENABLETNLCNGHDR)
22360 #define F_ENABLETNLCNGHDR    V_ENABLETNLCNGHDR(1U)
22361 
22362 #define S_ENABLETNLCNGSGE    28
22363 #define V_ENABLETNLCNGSGE(x) ((x) << S_ENABLETNLCNGSGE)
22364 #define F_ENABLETNLCNGSGE    V_ENABLETNLCNGSGE(1U)
22365 
22366 #define S_RXMACCHECK    27
22367 #define V_RXMACCHECK(x) ((x) << S_RXMACCHECK)
22368 #define F_RXMACCHECK    V_RXMACCHECK(1U)
22369 
22370 #define S_RXSYNFILTER    26
22371 #define V_RXSYNFILTER(x) ((x) << S_RXSYNFILTER)
22372 #define F_RXSYNFILTER    V_RXSYNFILTER(1U)
22373 
22374 #define S_CNGCTRLECN    25
22375 #define V_CNGCTRLECN(x) ((x) << S_CNGCTRLECN)
22376 #define F_CNGCTRLECN    V_CNGCTRLECN(1U)
22377 
22378 #define S_RXDDPOFFINIT    24
22379 #define V_RXDDPOFFINIT(x) ((x) << S_RXDDPOFFINIT)
22380 #define F_RXDDPOFFINIT    V_RXDDPOFFINIT(1U)
22381 
22382 #define S_TUNNELCNGDROP3    23
22383 #define V_TUNNELCNGDROP3(x) ((x) << S_TUNNELCNGDROP3)
22384 #define F_TUNNELCNGDROP3    V_TUNNELCNGDROP3(1U)
22385 
22386 #define S_TUNNELCNGDROP2    22
22387 #define V_TUNNELCNGDROP2(x) ((x) << S_TUNNELCNGDROP2)
22388 #define F_TUNNELCNGDROP2    V_TUNNELCNGDROP2(1U)
22389 
22390 #define S_TUNNELCNGDROP1    21
22391 #define V_TUNNELCNGDROP1(x) ((x) << S_TUNNELCNGDROP1)
22392 #define F_TUNNELCNGDROP1    V_TUNNELCNGDROP1(1U)
22393 
22394 #define S_TUNNELCNGDROP0    20
22395 #define V_TUNNELCNGDROP0(x) ((x) << S_TUNNELCNGDROP0)
22396 #define F_TUNNELCNGDROP0    V_TUNNELCNGDROP0(1U)
22397 
22398 #define S_TXDATAACKIDX    16
22399 #define M_TXDATAACKIDX    0xfU
22400 #define V_TXDATAACKIDX(x) ((x) << S_TXDATAACKIDX)
22401 #define G_TXDATAACKIDX(x) (((x) >> S_TXDATAACKIDX) & M_TXDATAACKIDX)
22402 
22403 #define S_RXFRAGENABLE    12
22404 #define M_RXFRAGENABLE    0x7U
22405 #define V_RXFRAGENABLE(x) ((x) << S_RXFRAGENABLE)
22406 #define G_RXFRAGENABLE(x) (((x) >> S_RXFRAGENABLE) & M_RXFRAGENABLE)
22407 
22408 #define S_TXPACEFIXEDSTRICT    11
22409 #define V_TXPACEFIXEDSTRICT(x) ((x) << S_TXPACEFIXEDSTRICT)
22410 #define F_TXPACEFIXEDSTRICT    V_TXPACEFIXEDSTRICT(1U)
22411 
22412 #define S_TXPACEAUTOSTRICT    10
22413 #define V_TXPACEAUTOSTRICT(x) ((x) << S_TXPACEAUTOSTRICT)
22414 #define F_TXPACEAUTOSTRICT    V_TXPACEAUTOSTRICT(1U)
22415 
22416 #define S_TXPACEFIXED    9
22417 #define V_TXPACEFIXED(x) ((x) << S_TXPACEFIXED)
22418 #define F_TXPACEFIXED    V_TXPACEFIXED(1U)
22419 
22420 #define S_TXPACEAUTO    8
22421 #define V_TXPACEAUTO(x) ((x) << S_TXPACEAUTO)
22422 #define F_TXPACEAUTO    V_TXPACEAUTO(1U)
22423 
22424 #define S_RXCHNTUNNEL    7
22425 #define V_RXCHNTUNNEL(x) ((x) << S_RXCHNTUNNEL)
22426 #define F_RXCHNTUNNEL    V_RXCHNTUNNEL(1U)
22427 
22428 #define S_RXURGTUNNEL    6
22429 #define V_RXURGTUNNEL(x) ((x) << S_RXURGTUNNEL)
22430 #define F_RXURGTUNNEL    V_RXURGTUNNEL(1U)
22431 
22432 #define S_RXURGMODE    5
22433 #define V_RXURGMODE(x) ((x) << S_RXURGMODE)
22434 #define F_RXURGMODE    V_RXURGMODE(1U)
22435 
22436 #define S_TXURGMODE    4
22437 #define V_TXURGMODE(x) ((x) << S_TXURGMODE)
22438 #define F_TXURGMODE    V_TXURGMODE(1U)
22439 
22440 #define S_CNGCTRLMODE    2
22441 #define M_CNGCTRLMODE    0x3U
22442 #define V_CNGCTRLMODE(x) ((x) << S_CNGCTRLMODE)
22443 #define G_CNGCTRLMODE(x) (((x) >> S_CNGCTRLMODE) & M_CNGCTRLMODE)
22444 
22445 #define S_RXCOALESCEENABLE    1
22446 #define V_RXCOALESCEENABLE(x) ((x) << S_RXCOALESCEENABLE)
22447 #define F_RXCOALESCEENABLE    V_RXCOALESCEENABLE(1U)
22448 
22449 #define S_RXCOALESCEPSHEN    0
22450 #define V_RXCOALESCEPSHEN(x) ((x) << S_RXCOALESCEPSHEN)
22451 #define F_RXCOALESCEPSHEN    V_RXCOALESCEPSHEN(1U)
22452 
22453 #define A_TP_PARA_REG4 0x7d70
22454 
22455 #define S_HIGHSPEEDCFG    24
22456 #define M_HIGHSPEEDCFG    0xffU
22457 #define V_HIGHSPEEDCFG(x) ((x) << S_HIGHSPEEDCFG)
22458 #define G_HIGHSPEEDCFG(x) (((x) >> S_HIGHSPEEDCFG) & M_HIGHSPEEDCFG)
22459 
22460 #define S_NEWRENOCFG    16
22461 #define M_NEWRENOCFG    0xffU
22462 #define V_NEWRENOCFG(x) ((x) << S_NEWRENOCFG)
22463 #define G_NEWRENOCFG(x) (((x) >> S_NEWRENOCFG) & M_NEWRENOCFG)
22464 
22465 #define S_TAHOECFG    8
22466 #define M_TAHOECFG    0xffU
22467 #define V_TAHOECFG(x) ((x) << S_TAHOECFG)
22468 #define G_TAHOECFG(x) (((x) >> S_TAHOECFG) & M_TAHOECFG)
22469 
22470 #define S_RENOCFG    0
22471 #define M_RENOCFG    0xffU
22472 #define V_RENOCFG(x) ((x) << S_RENOCFG)
22473 #define G_RENOCFG(x) (((x) >> S_RENOCFG) & M_RENOCFG)
22474 
22475 #define S_IDLECWNDHIGHSPEED    28
22476 #define V_IDLECWNDHIGHSPEED(x) ((x) << S_IDLECWNDHIGHSPEED)
22477 #define F_IDLECWNDHIGHSPEED    V_IDLECWNDHIGHSPEED(1U)
22478 
22479 #define S_RXMTCWNDHIGHSPEED    27
22480 #define V_RXMTCWNDHIGHSPEED(x) ((x) << S_RXMTCWNDHIGHSPEED)
22481 #define F_RXMTCWNDHIGHSPEED    V_RXMTCWNDHIGHSPEED(1U)
22482 
22483 #define S_OVERDRIVEHIGHSPEED    25
22484 #define M_OVERDRIVEHIGHSPEED    0x3U
22485 #define V_OVERDRIVEHIGHSPEED(x) ((x) << S_OVERDRIVEHIGHSPEED)
22486 #define G_OVERDRIVEHIGHSPEED(x) (((x) >> S_OVERDRIVEHIGHSPEED) & M_OVERDRIVEHIGHSPEED)
22487 
22488 #define S_BYTECOUNTHIGHSPEED    24
22489 #define V_BYTECOUNTHIGHSPEED(x) ((x) << S_BYTECOUNTHIGHSPEED)
22490 #define F_BYTECOUNTHIGHSPEED    V_BYTECOUNTHIGHSPEED(1U)
22491 
22492 #define S_IDLECWNDNEWRENO    20
22493 #define V_IDLECWNDNEWRENO(x) ((x) << S_IDLECWNDNEWRENO)
22494 #define F_IDLECWNDNEWRENO    V_IDLECWNDNEWRENO(1U)
22495 
22496 #define S_RXMTCWNDNEWRENO    19
22497 #define V_RXMTCWNDNEWRENO(x) ((x) << S_RXMTCWNDNEWRENO)
22498 #define F_RXMTCWNDNEWRENO    V_RXMTCWNDNEWRENO(1U)
22499 
22500 #define S_OVERDRIVENEWRENO    17
22501 #define M_OVERDRIVENEWRENO    0x3U
22502 #define V_OVERDRIVENEWRENO(x) ((x) << S_OVERDRIVENEWRENO)
22503 #define G_OVERDRIVENEWRENO(x) (((x) >> S_OVERDRIVENEWRENO) & M_OVERDRIVENEWRENO)
22504 
22505 #define S_BYTECOUNTNEWRENO    16
22506 #define V_BYTECOUNTNEWRENO(x) ((x) << S_BYTECOUNTNEWRENO)
22507 #define F_BYTECOUNTNEWRENO    V_BYTECOUNTNEWRENO(1U)
22508 
22509 #define S_IDLECWNDTAHOE    12
22510 #define V_IDLECWNDTAHOE(x) ((x) << S_IDLECWNDTAHOE)
22511 #define F_IDLECWNDTAHOE    V_IDLECWNDTAHOE(1U)
22512 
22513 #define S_RXMTCWNDTAHOE    11
22514 #define V_RXMTCWNDTAHOE(x) ((x) << S_RXMTCWNDTAHOE)
22515 #define F_RXMTCWNDTAHOE    V_RXMTCWNDTAHOE(1U)
22516 
22517 #define S_OVERDRIVETAHOE    9
22518 #define M_OVERDRIVETAHOE    0x3U
22519 #define V_OVERDRIVETAHOE(x) ((x) << S_OVERDRIVETAHOE)
22520 #define G_OVERDRIVETAHOE(x) (((x) >> S_OVERDRIVETAHOE) & M_OVERDRIVETAHOE)
22521 
22522 #define S_BYTECOUNTTAHOE    8
22523 #define V_BYTECOUNTTAHOE(x) ((x) << S_BYTECOUNTTAHOE)
22524 #define F_BYTECOUNTTAHOE    V_BYTECOUNTTAHOE(1U)
22525 
22526 #define S_IDLECWNDRENO    4
22527 #define V_IDLECWNDRENO(x) ((x) << S_IDLECWNDRENO)
22528 #define F_IDLECWNDRENO    V_IDLECWNDRENO(1U)
22529 
22530 #define S_RXMTCWNDRENO    3
22531 #define V_RXMTCWNDRENO(x) ((x) << S_RXMTCWNDRENO)
22532 #define F_RXMTCWNDRENO    V_RXMTCWNDRENO(1U)
22533 
22534 #define S_OVERDRIVERENO    1
22535 #define M_OVERDRIVERENO    0x3U
22536 #define V_OVERDRIVERENO(x) ((x) << S_OVERDRIVERENO)
22537 #define G_OVERDRIVERENO(x) (((x) >> S_OVERDRIVERENO) & M_OVERDRIVERENO)
22538 
22539 #define S_BYTECOUNTRENO    0
22540 #define V_BYTECOUNTRENO(x) ((x) << S_BYTECOUNTRENO)
22541 #define F_BYTECOUNTRENO    V_BYTECOUNTRENO(1U)
22542 
22543 #define A_TP_PARA_REG5 0x7d74
22544 
22545 #define S_INDICATESIZE    16
22546 #define M_INDICATESIZE    0xffffU
22547 #define V_INDICATESIZE(x) ((x) << S_INDICATESIZE)
22548 #define G_INDICATESIZE(x) (((x) >> S_INDICATESIZE) & M_INDICATESIZE)
22549 
22550 #define S_MAXPROXYSIZE    12
22551 #define M_MAXPROXYSIZE    0xfU
22552 #define V_MAXPROXYSIZE(x) ((x) << S_MAXPROXYSIZE)
22553 #define G_MAXPROXYSIZE(x) (((x) >> S_MAXPROXYSIZE) & M_MAXPROXYSIZE)
22554 
22555 #define S_ENABLEREADPDU    11
22556 #define V_ENABLEREADPDU(x) ((x) << S_ENABLEREADPDU)
22557 #define F_ENABLEREADPDU    V_ENABLEREADPDU(1U)
22558 
22559 #define S_RXREADAHEAD    10
22560 #define V_RXREADAHEAD(x) ((x) << S_RXREADAHEAD)
22561 #define F_RXREADAHEAD    V_RXREADAHEAD(1U)
22562 
22563 #define S_EMPTYRQENABLE    9
22564 #define V_EMPTYRQENABLE(x) ((x) << S_EMPTYRQENABLE)
22565 #define F_EMPTYRQENABLE    V_EMPTYRQENABLE(1U)
22566 
22567 #define S_SCHDENABLE    8
22568 #define V_SCHDENABLE(x) ((x) << S_SCHDENABLE)
22569 #define F_SCHDENABLE    V_SCHDENABLE(1U)
22570 
22571 #define S_REARMDDPOFFSET    4
22572 #define V_REARMDDPOFFSET(x) ((x) << S_REARMDDPOFFSET)
22573 #define F_REARMDDPOFFSET    V_REARMDDPOFFSET(1U)
22574 
22575 #define S_RESETDDPOFFSET    3
22576 #define V_RESETDDPOFFSET(x) ((x) << S_RESETDDPOFFSET)
22577 #define F_RESETDDPOFFSET    V_RESETDDPOFFSET(1U)
22578 
22579 #define S_ONFLYDDPENABLE    2
22580 #define V_ONFLYDDPENABLE(x) ((x) << S_ONFLYDDPENABLE)
22581 #define F_ONFLYDDPENABLE    V_ONFLYDDPENABLE(1U)
22582 
22583 #define S_DACKTIMERSPIN    1
22584 #define V_DACKTIMERSPIN(x) ((x) << S_DACKTIMERSPIN)
22585 #define F_DACKTIMERSPIN    V_DACKTIMERSPIN(1U)
22586 
22587 #define S_PUSHTIMERENABLE    0
22588 #define V_PUSHTIMERENABLE(x) ((x) << S_PUSHTIMERENABLE)
22589 #define F_PUSHTIMERENABLE    V_PUSHTIMERENABLE(1U)
22590 
22591 #define S_ENABLEXOFFPDU    7
22592 #define V_ENABLEXOFFPDU(x) ((x) << S_ENABLEXOFFPDU)
22593 #define F_ENABLEXOFFPDU    V_ENABLEXOFFPDU(1U)
22594 
22595 #define S_ENABLENEWFAR    6
22596 #define V_ENABLENEWFAR(x) ((x) << S_ENABLENEWFAR)
22597 #define F_ENABLENEWFAR    V_ENABLENEWFAR(1U)
22598 
22599 #define S_ENABLEFRAGCHECK    5
22600 #define V_ENABLEFRAGCHECK(x) ((x) << S_ENABLEFRAGCHECK)
22601 #define F_ENABLEFRAGCHECK    V_ENABLEFRAGCHECK(1U)
22602 
22603 #define S_ENABLEFCOECHECK    6
22604 #define V_ENABLEFCOECHECK(x) ((x) << S_ENABLEFCOECHECK)
22605 #define F_ENABLEFCOECHECK    V_ENABLEFCOECHECK(1U)
22606 
22607 #define S_ENABLERDMAFIX    1
22608 #define V_ENABLERDMAFIX(x) ((x) << S_ENABLERDMAFIX)
22609 #define F_ENABLERDMAFIX    V_ENABLERDMAFIX(1U)
22610 
22611 #define A_TP_PARA_REG6 0x7d78
22612 
22613 #define S_TXPDUSIZEADJ    24
22614 #define M_TXPDUSIZEADJ    0xffU
22615 #define V_TXPDUSIZEADJ(x) ((x) << S_TXPDUSIZEADJ)
22616 #define G_TXPDUSIZEADJ(x) (((x) >> S_TXPDUSIZEADJ) & M_TXPDUSIZEADJ)
22617 
22618 #define S_ENABLECBYP    21
22619 #define V_ENABLECBYP(x) ((x) << S_ENABLECBYP)
22620 #define F_ENABLECBYP    V_ENABLECBYP(1U)
22621 
22622 #define S_LIMITEDTRANSMIT    20
22623 #define M_LIMITEDTRANSMIT    0xfU
22624 #define V_LIMITEDTRANSMIT(x) ((x) << S_LIMITEDTRANSMIT)
22625 #define G_LIMITEDTRANSMIT(x) (((x) >> S_LIMITEDTRANSMIT) & M_LIMITEDTRANSMIT)
22626 
22627 #define S_ENABLECSAV    19
22628 #define V_ENABLECSAV(x) ((x) << S_ENABLECSAV)
22629 #define F_ENABLECSAV    V_ENABLECSAV(1U)
22630 
22631 #define S_ENABLEDEFERPDU    18
22632 #define V_ENABLEDEFERPDU(x) ((x) << S_ENABLEDEFERPDU)
22633 #define F_ENABLEDEFERPDU    V_ENABLEDEFERPDU(1U)
22634 
22635 #define S_ENABLEFLUSH    17
22636 #define V_ENABLEFLUSH(x) ((x) << S_ENABLEFLUSH)
22637 #define F_ENABLEFLUSH    V_ENABLEFLUSH(1U)
22638 
22639 #define S_ENABLEBYTEPERSIST    16
22640 #define V_ENABLEBYTEPERSIST(x) ((x) << S_ENABLEBYTEPERSIST)
22641 #define F_ENABLEBYTEPERSIST    V_ENABLEBYTEPERSIST(1U)
22642 
22643 #define S_DISABLETMOCNG    15
22644 #define V_DISABLETMOCNG(x) ((x) << S_DISABLETMOCNG)
22645 #define F_DISABLETMOCNG    V_DISABLETMOCNG(1U)
22646 
22647 #define S_TXREADAHEAD    14
22648 #define V_TXREADAHEAD(x) ((x) << S_TXREADAHEAD)
22649 #define F_TXREADAHEAD    V_TXREADAHEAD(1U)
22650 
22651 #define S_ALLOWEXEPTION    13
22652 #define V_ALLOWEXEPTION(x) ((x) << S_ALLOWEXEPTION)
22653 #define F_ALLOWEXEPTION    V_ALLOWEXEPTION(1U)
22654 
22655 #define S_ENABLEDEFERACK    12
22656 #define V_ENABLEDEFERACK(x) ((x) << S_ENABLEDEFERACK)
22657 #define F_ENABLEDEFERACK    V_ENABLEDEFERACK(1U)
22658 
22659 #define S_ENABLEESND    11
22660 #define V_ENABLEESND(x) ((x) << S_ENABLEESND)
22661 #define F_ENABLEESND    V_ENABLEESND(1U)
22662 
22663 #define S_ENABLECSND    10
22664 #define V_ENABLECSND(x) ((x) << S_ENABLECSND)
22665 #define F_ENABLECSND    V_ENABLECSND(1U)
22666 
22667 #define S_ENABLEPDUE    9
22668 #define V_ENABLEPDUE(x) ((x) << S_ENABLEPDUE)
22669 #define F_ENABLEPDUE    V_ENABLEPDUE(1U)
22670 
22671 #define S_ENABLEPDUC    8
22672 #define V_ENABLEPDUC(x) ((x) << S_ENABLEPDUC)
22673 #define F_ENABLEPDUC    V_ENABLEPDUC(1U)
22674 
22675 #define S_ENABLEBUFI    7
22676 #define V_ENABLEBUFI(x) ((x) << S_ENABLEBUFI)
22677 #define F_ENABLEBUFI    V_ENABLEBUFI(1U)
22678 
22679 #define S_ENABLEBUFE    6
22680 #define V_ENABLEBUFE(x) ((x) << S_ENABLEBUFE)
22681 #define F_ENABLEBUFE    V_ENABLEBUFE(1U)
22682 
22683 #define S_ENABLEDEFER    5
22684 #define V_ENABLEDEFER(x) ((x) << S_ENABLEDEFER)
22685 #define F_ENABLEDEFER    V_ENABLEDEFER(1U)
22686 
22687 #define S_ENABLECLEARRXMTOOS    4
22688 #define V_ENABLECLEARRXMTOOS(x) ((x) << S_ENABLECLEARRXMTOOS)
22689 #define F_ENABLECLEARRXMTOOS    V_ENABLECLEARRXMTOOS(1U)
22690 
22691 #define S_DISABLEPDUCNG    3
22692 #define V_DISABLEPDUCNG(x) ((x) << S_DISABLEPDUCNG)
22693 #define F_DISABLEPDUCNG    V_DISABLEPDUCNG(1U)
22694 
22695 #define S_DISABLEPDUTIMEOUT    2
22696 #define V_DISABLEPDUTIMEOUT(x) ((x) << S_DISABLEPDUTIMEOUT)
22697 #define F_DISABLEPDUTIMEOUT    V_DISABLEPDUTIMEOUT(1U)
22698 
22699 #define S_DISABLEPDURXMT    1
22700 #define V_DISABLEPDURXMT(x) ((x) << S_DISABLEPDURXMT)
22701 #define F_DISABLEPDURXMT    V_DISABLEPDURXMT(1U)
22702 
22703 #define S_DISABLEPDUXMT    0
22704 #define V_DISABLEPDUXMT(x) ((x) << S_DISABLEPDUXMT)
22705 #define F_DISABLEPDUXMT    V_DISABLEPDUXMT(1U)
22706 
22707 #define S_DISABLEPDUACK    20
22708 #define V_DISABLEPDUACK(x) ((x) << S_DISABLEPDUACK)
22709 #define F_DISABLEPDUACK    V_DISABLEPDUACK(1U)
22710 
22711 #define S_TXTCAMKEY    22
22712 #define V_TXTCAMKEY(x) ((x) << S_TXTCAMKEY)
22713 #define F_TXTCAMKEY    V_TXTCAMKEY(1U)
22714 
22715 #define S_ENABLECBYP    21
22716 #define V_ENABLECBYP(x) ((x) << S_ENABLECBYP)
22717 #define F_ENABLECBYP    V_ENABLECBYP(1U)
22718 
22719 #define A_TP_PARA_REG7 0x7d7c
22720 
22721 #define S_PMMAXXFERLEN1    16
22722 #define M_PMMAXXFERLEN1    0xffffU
22723 #define V_PMMAXXFERLEN1(x) ((x) << S_PMMAXXFERLEN1)
22724 #define G_PMMAXXFERLEN1(x) (((x) >> S_PMMAXXFERLEN1) & M_PMMAXXFERLEN1)
22725 
22726 #define S_PMMAXXFERLEN0    0
22727 #define M_PMMAXXFERLEN0    0xffffU
22728 #define V_PMMAXXFERLEN0(x) ((x) << S_PMMAXXFERLEN0)
22729 #define G_PMMAXXFERLEN0(x) (((x) >> S_PMMAXXFERLEN0) & M_PMMAXXFERLEN0)
22730 
22731 #define A_TP_ENG_CONFIG 0x7d80
22732 
22733 #define S_TABLELATENCYDONE    28
22734 #define M_TABLELATENCYDONE    0xfU
22735 #define V_TABLELATENCYDONE(x) ((x) << S_TABLELATENCYDONE)
22736 #define G_TABLELATENCYDONE(x) (((x) >> S_TABLELATENCYDONE) & M_TABLELATENCYDONE)
22737 
22738 #define S_TABLELATENCYSTART    24
22739 #define M_TABLELATENCYSTART    0xfU
22740 #define V_TABLELATENCYSTART(x) ((x) << S_TABLELATENCYSTART)
22741 #define G_TABLELATENCYSTART(x) (((x) >> S_TABLELATENCYSTART) & M_TABLELATENCYSTART)
22742 
22743 #define S_ENGINELATENCYDELTA    16
22744 #define M_ENGINELATENCYDELTA    0xfU
22745 #define V_ENGINELATENCYDELTA(x) ((x) << S_ENGINELATENCYDELTA)
22746 #define G_ENGINELATENCYDELTA(x) (((x) >> S_ENGINELATENCYDELTA) & M_ENGINELATENCYDELTA)
22747 
22748 #define S_ENGINELATENCYMMGR    12
22749 #define M_ENGINELATENCYMMGR    0xfU
22750 #define V_ENGINELATENCYMMGR(x) ((x) << S_ENGINELATENCYMMGR)
22751 #define G_ENGINELATENCYMMGR(x) (((x) >> S_ENGINELATENCYMMGR) & M_ENGINELATENCYMMGR)
22752 
22753 #define S_ENGINELATENCYWIREIP6    8
22754 #define M_ENGINELATENCYWIREIP6    0xfU
22755 #define V_ENGINELATENCYWIREIP6(x) ((x) << S_ENGINELATENCYWIREIP6)
22756 #define G_ENGINELATENCYWIREIP6(x) (((x) >> S_ENGINELATENCYWIREIP6) & M_ENGINELATENCYWIREIP6)
22757 
22758 #define S_ENGINELATENCYWIRE    4
22759 #define M_ENGINELATENCYWIRE    0xfU
22760 #define V_ENGINELATENCYWIRE(x) ((x) << S_ENGINELATENCYWIRE)
22761 #define G_ENGINELATENCYWIRE(x) (((x) >> S_ENGINELATENCYWIRE) & M_ENGINELATENCYWIRE)
22762 
22763 #define S_ENGINELATENCYBASE    0
22764 #define M_ENGINELATENCYBASE    0xfU
22765 #define V_ENGINELATENCYBASE(x) ((x) << S_ENGINELATENCYBASE)
22766 #define G_ENGINELATENCYBASE(x) (((x) >> S_ENGINELATENCYBASE) & M_ENGINELATENCYBASE)
22767 
22768 #define A_TP_PARA_REG8 0x7d84
22769 
22770 #define S_ECNACKECT    2
22771 #define V_ECNACKECT(x) ((x) << S_ECNACKECT)
22772 #define F_ECNACKECT    V_ECNACKECT(1U)
22773 
22774 #define S_ECNFINECT    1
22775 #define V_ECNFINECT(x) ((x) << S_ECNFINECT)
22776 #define F_ECNFINECT    V_ECNFINECT(1U)
22777 
22778 #define S_ECNSYNECT    0
22779 #define V_ECNSYNECT(x) ((x) << S_ECNSYNECT)
22780 #define F_ECNSYNECT    V_ECNSYNECT(1U)
22781 
22782 #define A_TP_ERR_CONFIG 0x7d8c
22783 
22784 #define S_TNLERRORPING    30
22785 #define V_TNLERRORPING(x) ((x) << S_TNLERRORPING)
22786 #define F_TNLERRORPING    V_TNLERRORPING(1U)
22787 
22788 #define S_TNLERRORCSUM    29
22789 #define V_TNLERRORCSUM(x) ((x) << S_TNLERRORCSUM)
22790 #define F_TNLERRORCSUM    V_TNLERRORCSUM(1U)
22791 
22792 #define S_TNLERRORCSUMIP    28
22793 #define V_TNLERRORCSUMIP(x) ((x) << S_TNLERRORCSUMIP)
22794 #define F_TNLERRORCSUMIP    V_TNLERRORCSUMIP(1U)
22795 
22796 #define S_TNLERRORTCPOPT    25
22797 #define V_TNLERRORTCPOPT(x) ((x) << S_TNLERRORTCPOPT)
22798 #define F_TNLERRORTCPOPT    V_TNLERRORTCPOPT(1U)
22799 
22800 #define S_TNLERRORPKTLEN    24
22801 #define V_TNLERRORPKTLEN(x) ((x) << S_TNLERRORPKTLEN)
22802 #define F_TNLERRORPKTLEN    V_TNLERRORPKTLEN(1U)
22803 
22804 #define S_TNLERRORTCPHDRLEN    23
22805 #define V_TNLERRORTCPHDRLEN(x) ((x) << S_TNLERRORTCPHDRLEN)
22806 #define F_TNLERRORTCPHDRLEN    V_TNLERRORTCPHDRLEN(1U)
22807 
22808 #define S_TNLERRORIPHDRLEN    22
22809 #define V_TNLERRORIPHDRLEN(x) ((x) << S_TNLERRORIPHDRLEN)
22810 #define F_TNLERRORIPHDRLEN    V_TNLERRORIPHDRLEN(1U)
22811 
22812 #define S_TNLERRORETHHDRLEN    21
22813 #define V_TNLERRORETHHDRLEN(x) ((x) << S_TNLERRORETHHDRLEN)
22814 #define F_TNLERRORETHHDRLEN    V_TNLERRORETHHDRLEN(1U)
22815 
22816 #define S_TNLERRORATTACK    20
22817 #define V_TNLERRORATTACK(x) ((x) << S_TNLERRORATTACK)
22818 #define F_TNLERRORATTACK    V_TNLERRORATTACK(1U)
22819 
22820 #define S_TNLERRORFRAG    19
22821 #define V_TNLERRORFRAG(x) ((x) << S_TNLERRORFRAG)
22822 #define F_TNLERRORFRAG    V_TNLERRORFRAG(1U)
22823 
22824 #define S_TNLERRORIPVER    18
22825 #define V_TNLERRORIPVER(x) ((x) << S_TNLERRORIPVER)
22826 #define F_TNLERRORIPVER    V_TNLERRORIPVER(1U)
22827 
22828 #define S_TNLERRORMAC    17
22829 #define V_TNLERRORMAC(x) ((x) << S_TNLERRORMAC)
22830 #define F_TNLERRORMAC    V_TNLERRORMAC(1U)
22831 
22832 #define S_TNLERRORANY    16
22833 #define V_TNLERRORANY(x) ((x) << S_TNLERRORANY)
22834 #define F_TNLERRORANY    V_TNLERRORANY(1U)
22835 
22836 #define S_DROPERRORPING    14
22837 #define V_DROPERRORPING(x) ((x) << S_DROPERRORPING)
22838 #define F_DROPERRORPING    V_DROPERRORPING(1U)
22839 
22840 #define S_DROPERRORCSUM    13
22841 #define V_DROPERRORCSUM(x) ((x) << S_DROPERRORCSUM)
22842 #define F_DROPERRORCSUM    V_DROPERRORCSUM(1U)
22843 
22844 #define S_DROPERRORCSUMIP    12
22845 #define V_DROPERRORCSUMIP(x) ((x) << S_DROPERRORCSUMIP)
22846 #define F_DROPERRORCSUMIP    V_DROPERRORCSUMIP(1U)
22847 
22848 #define S_DROPERRORTCPOPT    9
22849 #define V_DROPERRORTCPOPT(x) ((x) << S_DROPERRORTCPOPT)
22850 #define F_DROPERRORTCPOPT    V_DROPERRORTCPOPT(1U)
22851 
22852 #define S_DROPERRORPKTLEN    8
22853 #define V_DROPERRORPKTLEN(x) ((x) << S_DROPERRORPKTLEN)
22854 #define F_DROPERRORPKTLEN    V_DROPERRORPKTLEN(1U)
22855 
22856 #define S_DROPERRORTCPHDRLEN    7
22857 #define V_DROPERRORTCPHDRLEN(x) ((x) << S_DROPERRORTCPHDRLEN)
22858 #define F_DROPERRORTCPHDRLEN    V_DROPERRORTCPHDRLEN(1U)
22859 
22860 #define S_DROPERRORIPHDRLEN    6
22861 #define V_DROPERRORIPHDRLEN(x) ((x) << S_DROPERRORIPHDRLEN)
22862 #define F_DROPERRORIPHDRLEN    V_DROPERRORIPHDRLEN(1U)
22863 
22864 #define S_DROPERRORETHHDRLEN    5
22865 #define V_DROPERRORETHHDRLEN(x) ((x) << S_DROPERRORETHHDRLEN)
22866 #define F_DROPERRORETHHDRLEN    V_DROPERRORETHHDRLEN(1U)
22867 
22868 #define S_DROPERRORATTACK    4
22869 #define V_DROPERRORATTACK(x) ((x) << S_DROPERRORATTACK)
22870 #define F_DROPERRORATTACK    V_DROPERRORATTACK(1U)
22871 
22872 #define S_DROPERRORFRAG    3
22873 #define V_DROPERRORFRAG(x) ((x) << S_DROPERRORFRAG)
22874 #define F_DROPERRORFRAG    V_DROPERRORFRAG(1U)
22875 
22876 #define S_DROPERRORIPVER    2
22877 #define V_DROPERRORIPVER(x) ((x) << S_DROPERRORIPVER)
22878 #define F_DROPERRORIPVER    V_DROPERRORIPVER(1U)
22879 
22880 #define S_DROPERRORMAC    1
22881 #define V_DROPERRORMAC(x) ((x) << S_DROPERRORMAC)
22882 #define F_DROPERRORMAC    V_DROPERRORMAC(1U)
22883 
22884 #define S_DROPERRORANY    0
22885 #define V_DROPERRORANY(x) ((x) << S_DROPERRORANY)
22886 #define F_DROPERRORANY    V_DROPERRORANY(1U)
22887 
22888 #define S_TNLERRORFPMA    31
22889 #define V_TNLERRORFPMA(x) ((x) << S_TNLERRORFPMA)
22890 #define F_TNLERRORFPMA    V_TNLERRORFPMA(1U)
22891 
22892 #define S_DROPERRORFPMA    15
22893 #define V_DROPERRORFPMA(x) ((x) << S_DROPERRORFPMA)
22894 #define F_DROPERRORFPMA    V_DROPERRORFPMA(1U)
22895 
22896 #define S_TNLERROROPAQUE    27
22897 #define V_TNLERROROPAQUE(x) ((x) << S_TNLERROROPAQUE)
22898 #define F_TNLERROROPAQUE    V_TNLERROROPAQUE(1U)
22899 
22900 #define S_TNLERRORIP6OPT    26
22901 #define V_TNLERRORIP6OPT(x) ((x) << S_TNLERRORIP6OPT)
22902 #define F_TNLERRORIP6OPT    V_TNLERRORIP6OPT(1U)
22903 
22904 #define S_DROPERROROPAQUE    11
22905 #define V_DROPERROROPAQUE(x) ((x) << S_DROPERROROPAQUE)
22906 #define F_DROPERROROPAQUE    V_DROPERROROPAQUE(1U)
22907 
22908 #define S_DROPERRORIP6OPT    10
22909 #define V_DROPERRORIP6OPT(x) ((x) << S_DROPERRORIP6OPT)
22910 #define F_DROPERRORIP6OPT    V_DROPERRORIP6OPT(1U)
22911 
22912 #define A_TP_TIMER_RESOLUTION 0x7d90
22913 
22914 #define S_TIMERRESOLUTION    16
22915 #define M_TIMERRESOLUTION    0xffU
22916 #define V_TIMERRESOLUTION(x) ((x) << S_TIMERRESOLUTION)
22917 #define G_TIMERRESOLUTION(x) (((x) >> S_TIMERRESOLUTION) & M_TIMERRESOLUTION)
22918 
22919 #define S_TIMESTAMPRESOLUTION    8
22920 #define M_TIMESTAMPRESOLUTION    0xffU
22921 #define V_TIMESTAMPRESOLUTION(x) ((x) << S_TIMESTAMPRESOLUTION)
22922 #define G_TIMESTAMPRESOLUTION(x) (((x) >> S_TIMESTAMPRESOLUTION) & M_TIMESTAMPRESOLUTION)
22923 
22924 #define S_DELAYEDACKRESOLUTION    0
22925 #define M_DELAYEDACKRESOLUTION    0xffU
22926 #define V_DELAYEDACKRESOLUTION(x) ((x) << S_DELAYEDACKRESOLUTION)
22927 #define G_DELAYEDACKRESOLUTION(x) (((x) >> S_DELAYEDACKRESOLUTION) & M_DELAYEDACKRESOLUTION)
22928 
22929 #define A_TP_MSL 0x7d94
22930 
22931 #define S_MSL    0
22932 #define M_MSL    0x3fffffffU
22933 #define V_MSL(x) ((x) << S_MSL)
22934 #define G_MSL(x) (((x) >> S_MSL) & M_MSL)
22935 
22936 #define A_TP_RXT_MIN 0x7d98
22937 
22938 #define S_RXTMIN    0
22939 #define M_RXTMIN    0x3fffffffU
22940 #define V_RXTMIN(x) ((x) << S_RXTMIN)
22941 #define G_RXTMIN(x) (((x) >> S_RXTMIN) & M_RXTMIN)
22942 
22943 #define A_TP_RXT_MAX 0x7d9c
22944 
22945 #define S_RXTMAX    0
22946 #define M_RXTMAX    0x3fffffffU
22947 #define V_RXTMAX(x) ((x) << S_RXTMAX)
22948 #define G_RXTMAX(x) (((x) >> S_RXTMAX) & M_RXTMAX)
22949 
22950 #define A_TP_PERS_MIN 0x7da0
22951 
22952 #define S_PERSMIN    0
22953 #define M_PERSMIN    0x3fffffffU
22954 #define V_PERSMIN(x) ((x) << S_PERSMIN)
22955 #define G_PERSMIN(x) (((x) >> S_PERSMIN) & M_PERSMIN)
22956 
22957 #define A_TP_PERS_MAX 0x7da4
22958 
22959 #define S_PERSMAX    0
22960 #define M_PERSMAX    0x3fffffffU
22961 #define V_PERSMAX(x) ((x) << S_PERSMAX)
22962 #define G_PERSMAX(x) (((x) >> S_PERSMAX) & M_PERSMAX)
22963 
22964 #define A_TP_KEEP_IDLE 0x7da8
22965 
22966 #define S_KEEPALIVEIDLE    0
22967 #define M_KEEPALIVEIDLE    0x3fffffffU
22968 #define V_KEEPALIVEIDLE(x) ((x) << S_KEEPALIVEIDLE)
22969 #define G_KEEPALIVEIDLE(x) (((x) >> S_KEEPALIVEIDLE) & M_KEEPALIVEIDLE)
22970 
22971 #define A_TP_KEEP_INTVL 0x7dac
22972 
22973 #define S_KEEPALIVEINTVL    0
22974 #define M_KEEPALIVEINTVL    0x3fffffffU
22975 #define V_KEEPALIVEINTVL(x) ((x) << S_KEEPALIVEINTVL)
22976 #define G_KEEPALIVEINTVL(x) (((x) >> S_KEEPALIVEINTVL) & M_KEEPALIVEINTVL)
22977 
22978 #define A_TP_INIT_SRTT 0x7db0
22979 
22980 #define S_MAXRTT    16
22981 #define M_MAXRTT    0xffffU
22982 #define V_MAXRTT(x) ((x) << S_MAXRTT)
22983 #define G_MAXRTT(x) (((x) >> S_MAXRTT) & M_MAXRTT)
22984 
22985 #define S_INITSRTT    0
22986 #define M_INITSRTT    0xffffU
22987 #define V_INITSRTT(x) ((x) << S_INITSRTT)
22988 #define G_INITSRTT(x) (((x) >> S_INITSRTT) & M_INITSRTT)
22989 
22990 #define A_TP_DACK_TIMER 0x7db4
22991 
22992 #define S_DACKTIME    0
22993 #define M_DACKTIME    0xfffU
22994 #define V_DACKTIME(x) ((x) << S_DACKTIME)
22995 #define G_DACKTIME(x) (((x) >> S_DACKTIME) & M_DACKTIME)
22996 
22997 #define A_TP_FINWAIT2_TIMER 0x7db8
22998 
22999 #define S_FINWAIT2TIME    0
23000 #define M_FINWAIT2TIME    0x3fffffffU
23001 #define V_FINWAIT2TIME(x) ((x) << S_FINWAIT2TIME)
23002 #define G_FINWAIT2TIME(x) (((x) >> S_FINWAIT2TIME) & M_FINWAIT2TIME)
23003 
23004 #define A_TP_FAST_FINWAIT2_TIMER 0x7dbc
23005 
23006 #define S_FASTFINWAIT2TIME    0
23007 #define M_FASTFINWAIT2TIME    0x3fffffffU
23008 #define V_FASTFINWAIT2TIME(x) ((x) << S_FASTFINWAIT2TIME)
23009 #define G_FASTFINWAIT2TIME(x) (((x) >> S_FASTFINWAIT2TIME) & M_FASTFINWAIT2TIME)
23010 
23011 #define A_TP_SHIFT_CNT 0x7dc0
23012 
23013 #define S_SYNSHIFTMAX    24
23014 #define M_SYNSHIFTMAX    0xffU
23015 #define V_SYNSHIFTMAX(x) ((x) << S_SYNSHIFTMAX)
23016 #define G_SYNSHIFTMAX(x) (((x) >> S_SYNSHIFTMAX) & M_SYNSHIFTMAX)
23017 
23018 #define S_RXTSHIFTMAXR1    20
23019 #define M_RXTSHIFTMAXR1    0xfU
23020 #define V_RXTSHIFTMAXR1(x) ((x) << S_RXTSHIFTMAXR1)
23021 #define G_RXTSHIFTMAXR1(x) (((x) >> S_RXTSHIFTMAXR1) & M_RXTSHIFTMAXR1)
23022 
23023 #define S_RXTSHIFTMAXR2    16
23024 #define M_RXTSHIFTMAXR2    0xfU
23025 #define V_RXTSHIFTMAXR2(x) ((x) << S_RXTSHIFTMAXR2)
23026 #define G_RXTSHIFTMAXR2(x) (((x) >> S_RXTSHIFTMAXR2) & M_RXTSHIFTMAXR2)
23027 
23028 #define S_PERSHIFTBACKOFFMAX    12
23029 #define M_PERSHIFTBACKOFFMAX    0xfU
23030 #define V_PERSHIFTBACKOFFMAX(x) ((x) << S_PERSHIFTBACKOFFMAX)
23031 #define G_PERSHIFTBACKOFFMAX(x) (((x) >> S_PERSHIFTBACKOFFMAX) & M_PERSHIFTBACKOFFMAX)
23032 
23033 #define S_PERSHIFTMAX    8
23034 #define M_PERSHIFTMAX    0xfU
23035 #define V_PERSHIFTMAX(x) ((x) << S_PERSHIFTMAX)
23036 #define G_PERSHIFTMAX(x) (((x) >> S_PERSHIFTMAX) & M_PERSHIFTMAX)
23037 
23038 #define S_KEEPALIVEMAXR1    4
23039 #define M_KEEPALIVEMAXR1    0xfU
23040 #define V_KEEPALIVEMAXR1(x) ((x) << S_KEEPALIVEMAXR1)
23041 #define G_KEEPALIVEMAXR1(x) (((x) >> S_KEEPALIVEMAXR1) & M_KEEPALIVEMAXR1)
23042 
23043 #define S_KEEPALIVEMAXR2    0
23044 #define M_KEEPALIVEMAXR2    0xfU
23045 #define V_KEEPALIVEMAXR2(x) ((x) << S_KEEPALIVEMAXR2)
23046 #define G_KEEPALIVEMAXR2(x) (((x) >> S_KEEPALIVEMAXR2) & M_KEEPALIVEMAXR2)
23047 
23048 #define S_T6_SYNSHIFTMAX    24
23049 #define M_T6_SYNSHIFTMAX    0xfU
23050 #define V_T6_SYNSHIFTMAX(x) ((x) << S_T6_SYNSHIFTMAX)
23051 #define G_T6_SYNSHIFTMAX(x) (((x) >> S_T6_SYNSHIFTMAX) & M_T6_SYNSHIFTMAX)
23052 
23053 #define A_TP_TM_CONFIG 0x7dc4
23054 
23055 #define S_CMTIMERMAXNUM    0
23056 #define M_CMTIMERMAXNUM    0x7U
23057 #define V_CMTIMERMAXNUM(x) ((x) << S_CMTIMERMAXNUM)
23058 #define G_CMTIMERMAXNUM(x) (((x) >> S_CMTIMERMAXNUM) & M_CMTIMERMAXNUM)
23059 
23060 #define A_TP_TIME_LO 0x7dc8
23061 #define A_TP_TIME_HI 0x7dcc
23062 #define A_TP_PORT_MTU_0 0x7dd0
23063 
23064 #define S_PORT1MTUVALUE    16
23065 #define M_PORT1MTUVALUE    0xffffU
23066 #define V_PORT1MTUVALUE(x) ((x) << S_PORT1MTUVALUE)
23067 #define G_PORT1MTUVALUE(x) (((x) >> S_PORT1MTUVALUE) & M_PORT1MTUVALUE)
23068 
23069 #define S_PORT0MTUVALUE    0
23070 #define M_PORT0MTUVALUE    0xffffU
23071 #define V_PORT0MTUVALUE(x) ((x) << S_PORT0MTUVALUE)
23072 #define G_PORT0MTUVALUE(x) (((x) >> S_PORT0MTUVALUE) & M_PORT0MTUVALUE)
23073 
23074 #define A_TP_PORT_MTU_1 0x7dd4
23075 
23076 #define S_PORT3MTUVALUE    16
23077 #define M_PORT3MTUVALUE    0xffffU
23078 #define V_PORT3MTUVALUE(x) ((x) << S_PORT3MTUVALUE)
23079 #define G_PORT3MTUVALUE(x) (((x) >> S_PORT3MTUVALUE) & M_PORT3MTUVALUE)
23080 
23081 #define S_PORT2MTUVALUE    0
23082 #define M_PORT2MTUVALUE    0xffffU
23083 #define V_PORT2MTUVALUE(x) ((x) << S_PORT2MTUVALUE)
23084 #define G_PORT2MTUVALUE(x) (((x) >> S_PORT2MTUVALUE) & M_PORT2MTUVALUE)
23085 
23086 #define A_TP_PACE_TABLE 0x7dd8
23087 #define A_TP_CCTRL_TABLE 0x7ddc
23088 
23089 #define S_ROWINDEX    16
23090 #define M_ROWINDEX    0xffffU
23091 #define V_ROWINDEX(x) ((x) << S_ROWINDEX)
23092 #define G_ROWINDEX(x) (((x) >> S_ROWINDEX) & M_ROWINDEX)
23093 
23094 #define S_ROWVALUE    0
23095 #define M_ROWVALUE    0xffffU
23096 #define V_ROWVALUE(x) ((x) << S_ROWVALUE)
23097 #define G_ROWVALUE(x) (((x) >> S_ROWVALUE) & M_ROWVALUE)
23098 
23099 #define A_TP_MTU_TABLE 0x7de4
23100 
23101 #define S_MTUINDEX    24
23102 #define M_MTUINDEX    0xffU
23103 #define V_MTUINDEX(x) ((x) << S_MTUINDEX)
23104 #define G_MTUINDEX(x) (((x) >> S_MTUINDEX) & M_MTUINDEX)
23105 
23106 #define S_MTUWIDTH    16
23107 #define M_MTUWIDTH    0xfU
23108 #define V_MTUWIDTH(x) ((x) << S_MTUWIDTH)
23109 #define G_MTUWIDTH(x) (((x) >> S_MTUWIDTH) & M_MTUWIDTH)
23110 
23111 #define S_MTUVALUE    0
23112 #define M_MTUVALUE    0x3fffU
23113 #define V_MTUVALUE(x) ((x) << S_MTUVALUE)
23114 #define G_MTUVALUE(x) (((x) >> S_MTUVALUE) & M_MTUVALUE)
23115 
23116 #define A_TP_ULP_TABLE 0x7de8
23117 
23118 #define S_ULPTYPE7FIELD    28
23119 #define M_ULPTYPE7FIELD    0xfU
23120 #define V_ULPTYPE7FIELD(x) ((x) << S_ULPTYPE7FIELD)
23121 #define G_ULPTYPE7FIELD(x) (((x) >> S_ULPTYPE7FIELD) & M_ULPTYPE7FIELD)
23122 
23123 #define S_ULPTYPE6FIELD    24
23124 #define M_ULPTYPE6FIELD    0xfU
23125 #define V_ULPTYPE6FIELD(x) ((x) << S_ULPTYPE6FIELD)
23126 #define G_ULPTYPE6FIELD(x) (((x) >> S_ULPTYPE6FIELD) & M_ULPTYPE6FIELD)
23127 
23128 #define S_ULPTYPE5FIELD    20
23129 #define M_ULPTYPE5FIELD    0xfU
23130 #define V_ULPTYPE5FIELD(x) ((x) << S_ULPTYPE5FIELD)
23131 #define G_ULPTYPE5FIELD(x) (((x) >> S_ULPTYPE5FIELD) & M_ULPTYPE5FIELD)
23132 
23133 #define S_ULPTYPE4FIELD    16
23134 #define M_ULPTYPE4FIELD    0xfU
23135 #define V_ULPTYPE4FIELD(x) ((x) << S_ULPTYPE4FIELD)
23136 #define G_ULPTYPE4FIELD(x) (((x) >> S_ULPTYPE4FIELD) & M_ULPTYPE4FIELD)
23137 
23138 #define S_ULPTYPE3FIELD    12
23139 #define M_ULPTYPE3FIELD    0xfU
23140 #define V_ULPTYPE3FIELD(x) ((x) << S_ULPTYPE3FIELD)
23141 #define G_ULPTYPE3FIELD(x) (((x) >> S_ULPTYPE3FIELD) & M_ULPTYPE3FIELD)
23142 
23143 #define S_ULPTYPE2FIELD    8
23144 #define M_ULPTYPE2FIELD    0xfU
23145 #define V_ULPTYPE2FIELD(x) ((x) << S_ULPTYPE2FIELD)
23146 #define G_ULPTYPE2FIELD(x) (((x) >> S_ULPTYPE2FIELD) & M_ULPTYPE2FIELD)
23147 
23148 #define S_ULPTYPE1FIELD    4
23149 #define M_ULPTYPE1FIELD    0xfU
23150 #define V_ULPTYPE1FIELD(x) ((x) << S_ULPTYPE1FIELD)
23151 #define G_ULPTYPE1FIELD(x) (((x) >> S_ULPTYPE1FIELD) & M_ULPTYPE1FIELD)
23152 
23153 #define S_ULPTYPE0FIELD    0
23154 #define M_ULPTYPE0FIELD    0xfU
23155 #define V_ULPTYPE0FIELD(x) ((x) << S_ULPTYPE0FIELD)
23156 #define G_ULPTYPE0FIELD(x) (((x) >> S_ULPTYPE0FIELD) & M_ULPTYPE0FIELD)
23157 
23158 #define S_ULPTYPE7LENGTH    31
23159 #define V_ULPTYPE7LENGTH(x) ((x) << S_ULPTYPE7LENGTH)
23160 #define F_ULPTYPE7LENGTH    V_ULPTYPE7LENGTH(1U)
23161 
23162 #define S_ULPTYPE7OFFSET    28
23163 #define M_ULPTYPE7OFFSET    0x7U
23164 #define V_ULPTYPE7OFFSET(x) ((x) << S_ULPTYPE7OFFSET)
23165 #define G_ULPTYPE7OFFSET(x) (((x) >> S_ULPTYPE7OFFSET) & M_ULPTYPE7OFFSET)
23166 
23167 #define S_ULPTYPE6LENGTH    27
23168 #define V_ULPTYPE6LENGTH(x) ((x) << S_ULPTYPE6LENGTH)
23169 #define F_ULPTYPE6LENGTH    V_ULPTYPE6LENGTH(1U)
23170 
23171 #define S_ULPTYPE6OFFSET    24
23172 #define M_ULPTYPE6OFFSET    0x7U
23173 #define V_ULPTYPE6OFFSET(x) ((x) << S_ULPTYPE6OFFSET)
23174 #define G_ULPTYPE6OFFSET(x) (((x) >> S_ULPTYPE6OFFSET) & M_ULPTYPE6OFFSET)
23175 
23176 #define S_ULPTYPE5LENGTH    23
23177 #define V_ULPTYPE5LENGTH(x) ((x) << S_ULPTYPE5LENGTH)
23178 #define F_ULPTYPE5LENGTH    V_ULPTYPE5LENGTH(1U)
23179 
23180 #define S_ULPTYPE5OFFSET    20
23181 #define M_ULPTYPE5OFFSET    0x7U
23182 #define V_ULPTYPE5OFFSET(x) ((x) << S_ULPTYPE5OFFSET)
23183 #define G_ULPTYPE5OFFSET(x) (((x) >> S_ULPTYPE5OFFSET) & M_ULPTYPE5OFFSET)
23184 
23185 #define S_ULPTYPE4LENGTH    19
23186 #define V_ULPTYPE4LENGTH(x) ((x) << S_ULPTYPE4LENGTH)
23187 #define F_ULPTYPE4LENGTH    V_ULPTYPE4LENGTH(1U)
23188 
23189 #define S_ULPTYPE4OFFSET    16
23190 #define M_ULPTYPE4OFFSET    0x7U
23191 #define V_ULPTYPE4OFFSET(x) ((x) << S_ULPTYPE4OFFSET)
23192 #define G_ULPTYPE4OFFSET(x) (((x) >> S_ULPTYPE4OFFSET) & M_ULPTYPE4OFFSET)
23193 
23194 #define S_ULPTYPE3LENGTH    15
23195 #define V_ULPTYPE3LENGTH(x) ((x) << S_ULPTYPE3LENGTH)
23196 #define F_ULPTYPE3LENGTH    V_ULPTYPE3LENGTH(1U)
23197 
23198 #define S_ULPTYPE3OFFSET    12
23199 #define M_ULPTYPE3OFFSET    0x7U
23200 #define V_ULPTYPE3OFFSET(x) ((x) << S_ULPTYPE3OFFSET)
23201 #define G_ULPTYPE3OFFSET(x) (((x) >> S_ULPTYPE3OFFSET) & M_ULPTYPE3OFFSET)
23202 
23203 #define S_ULPTYPE2LENGTH    11
23204 #define V_ULPTYPE2LENGTH(x) ((x) << S_ULPTYPE2LENGTH)
23205 #define F_ULPTYPE2LENGTH    V_ULPTYPE2LENGTH(1U)
23206 
23207 #define S_ULPTYPE2OFFSET    8
23208 #define M_ULPTYPE2OFFSET    0x7U
23209 #define V_ULPTYPE2OFFSET(x) ((x) << S_ULPTYPE2OFFSET)
23210 #define G_ULPTYPE2OFFSET(x) (((x) >> S_ULPTYPE2OFFSET) & M_ULPTYPE2OFFSET)
23211 
23212 #define S_ULPTYPE1LENGTH    7
23213 #define V_ULPTYPE1LENGTH(x) ((x) << S_ULPTYPE1LENGTH)
23214 #define F_ULPTYPE1LENGTH    V_ULPTYPE1LENGTH(1U)
23215 
23216 #define S_ULPTYPE1OFFSET    4
23217 #define M_ULPTYPE1OFFSET    0x7U
23218 #define V_ULPTYPE1OFFSET(x) ((x) << S_ULPTYPE1OFFSET)
23219 #define G_ULPTYPE1OFFSET(x) (((x) >> S_ULPTYPE1OFFSET) & M_ULPTYPE1OFFSET)
23220 
23221 #define S_ULPTYPE0LENGTH    3
23222 #define V_ULPTYPE0LENGTH(x) ((x) << S_ULPTYPE0LENGTH)
23223 #define F_ULPTYPE0LENGTH    V_ULPTYPE0LENGTH(1U)
23224 
23225 #define S_ULPTYPE0OFFSET    0
23226 #define M_ULPTYPE0OFFSET    0x7U
23227 #define V_ULPTYPE0OFFSET(x) ((x) << S_ULPTYPE0OFFSET)
23228 #define G_ULPTYPE0OFFSET(x) (((x) >> S_ULPTYPE0OFFSET) & M_ULPTYPE0OFFSET)
23229 
23230 #define A_TP_RSS_LKP_TABLE 0x7dec
23231 
23232 #define S_LKPTBLROWVLD    31
23233 #define V_LKPTBLROWVLD(x) ((x) << S_LKPTBLROWVLD)
23234 #define F_LKPTBLROWVLD    V_LKPTBLROWVLD(1U)
23235 
23236 #define S_LKPTBLROWIDX    20
23237 #define M_LKPTBLROWIDX    0x3ffU
23238 #define V_LKPTBLROWIDX(x) ((x) << S_LKPTBLROWIDX)
23239 #define G_LKPTBLROWIDX(x) (((x) >> S_LKPTBLROWIDX) & M_LKPTBLROWIDX)
23240 
23241 #define S_LKPTBLQUEUE1    10
23242 #define M_LKPTBLQUEUE1    0x3ffU
23243 #define V_LKPTBLQUEUE1(x) ((x) << S_LKPTBLQUEUE1)
23244 #define G_LKPTBLQUEUE1(x) (((x) >> S_LKPTBLQUEUE1) & M_LKPTBLQUEUE1)
23245 
23246 #define S_LKPTBLQUEUE0    0
23247 #define M_LKPTBLQUEUE0    0x3ffU
23248 #define V_LKPTBLQUEUE0(x) ((x) << S_LKPTBLQUEUE0)
23249 #define G_LKPTBLQUEUE0(x) (((x) >> S_LKPTBLQUEUE0) & M_LKPTBLQUEUE0)
23250 
23251 #define S_T6_LKPTBLROWIDX    20
23252 #define M_T6_LKPTBLROWIDX    0x7ffU
23253 #define V_T6_LKPTBLROWIDX(x) ((x) << S_T6_LKPTBLROWIDX)
23254 #define G_T6_LKPTBLROWIDX(x) (((x) >> S_T6_LKPTBLROWIDX) & M_T6_LKPTBLROWIDX)
23255 
23256 #define A_TP_RSS_CONFIG 0x7df0
23257 
23258 #define S_TNL4TUPENIPV6    31
23259 #define V_TNL4TUPENIPV6(x) ((x) << S_TNL4TUPENIPV6)
23260 #define F_TNL4TUPENIPV6    V_TNL4TUPENIPV6(1U)
23261 
23262 #define S_TNL2TUPENIPV6    30
23263 #define V_TNL2TUPENIPV6(x) ((x) << S_TNL2TUPENIPV6)
23264 #define F_TNL2TUPENIPV6    V_TNL2TUPENIPV6(1U)
23265 
23266 #define S_TNL4TUPENIPV4    29
23267 #define V_TNL4TUPENIPV4(x) ((x) << S_TNL4TUPENIPV4)
23268 #define F_TNL4TUPENIPV4    V_TNL4TUPENIPV4(1U)
23269 
23270 #define S_TNL2TUPENIPV4    28
23271 #define V_TNL2TUPENIPV4(x) ((x) << S_TNL2TUPENIPV4)
23272 #define F_TNL2TUPENIPV4    V_TNL2TUPENIPV4(1U)
23273 
23274 #define S_TNLTCPSEL    27
23275 #define V_TNLTCPSEL(x) ((x) << S_TNLTCPSEL)
23276 #define F_TNLTCPSEL    V_TNLTCPSEL(1U)
23277 
23278 #define S_TNLIP6SEL    26
23279 #define V_TNLIP6SEL(x) ((x) << S_TNLIP6SEL)
23280 #define F_TNLIP6SEL    V_TNLIP6SEL(1U)
23281 
23282 #define S_TNLVRTSEL    25
23283 #define V_TNLVRTSEL(x) ((x) << S_TNLVRTSEL)
23284 #define F_TNLVRTSEL    V_TNLVRTSEL(1U)
23285 
23286 #define S_TNLMAPEN    24
23287 #define V_TNLMAPEN(x) ((x) << S_TNLMAPEN)
23288 #define F_TNLMAPEN    V_TNLMAPEN(1U)
23289 
23290 #define S_OFDHASHSAVE    19
23291 #define V_OFDHASHSAVE(x) ((x) << S_OFDHASHSAVE)
23292 #define F_OFDHASHSAVE    V_OFDHASHSAVE(1U)
23293 
23294 #define S_OFDVRTSEL    18
23295 #define V_OFDVRTSEL(x) ((x) << S_OFDVRTSEL)
23296 #define F_OFDVRTSEL    V_OFDVRTSEL(1U)
23297 
23298 #define S_OFDMAPEN    17
23299 #define V_OFDMAPEN(x) ((x) << S_OFDMAPEN)
23300 #define F_OFDMAPEN    V_OFDMAPEN(1U)
23301 
23302 #define S_OFDLKPEN    16
23303 #define V_OFDLKPEN(x) ((x) << S_OFDLKPEN)
23304 #define F_OFDLKPEN    V_OFDLKPEN(1U)
23305 
23306 #define S_SYN4TUPENIPV6    15
23307 #define V_SYN4TUPENIPV6(x) ((x) << S_SYN4TUPENIPV6)
23308 #define F_SYN4TUPENIPV6    V_SYN4TUPENIPV6(1U)
23309 
23310 #define S_SYN2TUPENIPV6    14
23311 #define V_SYN2TUPENIPV6(x) ((x) << S_SYN2TUPENIPV6)
23312 #define F_SYN2TUPENIPV6    V_SYN2TUPENIPV6(1U)
23313 
23314 #define S_SYN4TUPENIPV4    13
23315 #define V_SYN4TUPENIPV4(x) ((x) << S_SYN4TUPENIPV4)
23316 #define F_SYN4TUPENIPV4    V_SYN4TUPENIPV4(1U)
23317 
23318 #define S_SYN2TUPENIPV4    12
23319 #define V_SYN2TUPENIPV4(x) ((x) << S_SYN2TUPENIPV4)
23320 #define F_SYN2TUPENIPV4    V_SYN2TUPENIPV4(1U)
23321 
23322 #define S_SYNIP6SEL    11
23323 #define V_SYNIP6SEL(x) ((x) << S_SYNIP6SEL)
23324 #define F_SYNIP6SEL    V_SYNIP6SEL(1U)
23325 
23326 #define S_SYNVRTSEL    10
23327 #define V_SYNVRTSEL(x) ((x) << S_SYNVRTSEL)
23328 #define F_SYNVRTSEL    V_SYNVRTSEL(1U)
23329 
23330 #define S_SYNMAPEN    9
23331 #define V_SYNMAPEN(x) ((x) << S_SYNMAPEN)
23332 #define F_SYNMAPEN    V_SYNMAPEN(1U)
23333 
23334 #define S_SYNLKPEN    8
23335 #define V_SYNLKPEN(x) ((x) << S_SYNLKPEN)
23336 #define F_SYNLKPEN    V_SYNLKPEN(1U)
23337 
23338 #define S_CHANNELENABLE    7
23339 #define V_CHANNELENABLE(x) ((x) << S_CHANNELENABLE)
23340 #define F_CHANNELENABLE    V_CHANNELENABLE(1U)
23341 
23342 #define S_PORTENABLE    6
23343 #define V_PORTENABLE(x) ((x) << S_PORTENABLE)
23344 #define F_PORTENABLE    V_PORTENABLE(1U)
23345 
23346 #define S_TNLALLLOOKUP    5
23347 #define V_TNLALLLOOKUP(x) ((x) << S_TNLALLLOOKUP)
23348 #define F_TNLALLLOOKUP    V_TNLALLLOOKUP(1U)
23349 
23350 #define S_VIRTENABLE    4
23351 #define V_VIRTENABLE(x) ((x) << S_VIRTENABLE)
23352 #define F_VIRTENABLE    V_VIRTENABLE(1U)
23353 
23354 #define S_CONGESTIONENABLE    3
23355 #define V_CONGESTIONENABLE(x) ((x) << S_CONGESTIONENABLE)
23356 #define F_CONGESTIONENABLE    V_CONGESTIONENABLE(1U)
23357 
23358 #define S_HASHTOEPLITZ    2
23359 #define V_HASHTOEPLITZ(x) ((x) << S_HASHTOEPLITZ)
23360 #define F_HASHTOEPLITZ    V_HASHTOEPLITZ(1U)
23361 
23362 #define S_UDPENABLE    1
23363 #define V_UDPENABLE(x) ((x) << S_UDPENABLE)
23364 #define F_UDPENABLE    V_UDPENABLE(1U)
23365 
23366 #define S_DISABLE    0
23367 #define V_DISABLE(x) ((x) << S_DISABLE)
23368 #define F_DISABLE    V_DISABLE(1U)
23369 
23370 #define S_TNLFCOEMODE    23
23371 #define V_TNLFCOEMODE(x) ((x) << S_TNLFCOEMODE)
23372 #define F_TNLFCOEMODE    V_TNLFCOEMODE(1U)
23373 
23374 #define S_TNLFCOEEN    21
23375 #define V_TNLFCOEEN(x) ((x) << S_TNLFCOEEN)
23376 #define F_TNLFCOEEN    V_TNLFCOEEN(1U)
23377 
23378 #define S_HASHXOR    20
23379 #define V_HASHXOR(x) ((x) << S_HASHXOR)
23380 #define F_HASHXOR    V_HASHXOR(1U)
23381 
23382 #define S_TNLFCOESID    22
23383 #define V_TNLFCOESID(x) ((x) << S_TNLFCOESID)
23384 #define F_TNLFCOESID    V_TNLFCOESID(1U)
23385 
23386 #define A_TP_RSS_CONFIG_TNL 0x7df4
23387 
23388 #define S_MASKSIZE    28
23389 #define M_MASKSIZE    0xfU
23390 #define V_MASKSIZE(x) ((x) << S_MASKSIZE)
23391 #define G_MASKSIZE(x) (((x) >> S_MASKSIZE) & M_MASKSIZE)
23392 
23393 #define S_MASKFILTER    16
23394 #define M_MASKFILTER    0x7ffU
23395 #define V_MASKFILTER(x) ((x) << S_MASKFILTER)
23396 #define G_MASKFILTER(x) (((x) >> S_MASKFILTER) & M_MASKFILTER)
23397 
23398 #define S_USEWIRECH    0
23399 #define V_USEWIRECH(x) ((x) << S_USEWIRECH)
23400 #define F_USEWIRECH    V_USEWIRECH(1U)
23401 
23402 #define S_HASHALL    2
23403 #define V_HASHALL(x) ((x) << S_HASHALL)
23404 #define F_HASHALL    V_HASHALL(1U)
23405 
23406 #define S_HASHETH    1
23407 #define V_HASHETH(x) ((x) << S_HASHETH)
23408 #define F_HASHETH    V_HASHETH(1U)
23409 
23410 #define A_TP_RSS_CONFIG_OFD 0x7df8
23411 
23412 #define S_RRCPLMAPEN    20
23413 #define V_RRCPLMAPEN(x) ((x) << S_RRCPLMAPEN)
23414 #define F_RRCPLMAPEN    V_RRCPLMAPEN(1U)
23415 
23416 #define S_RRCPLQUEWIDTH    16
23417 #define M_RRCPLQUEWIDTH    0xfU
23418 #define V_RRCPLQUEWIDTH(x) ((x) << S_RRCPLQUEWIDTH)
23419 #define G_RRCPLQUEWIDTH(x) (((x) >> S_RRCPLQUEWIDTH) & M_RRCPLQUEWIDTH)
23420 
23421 #define S_FRMWRQUEMASK    12
23422 #define M_FRMWRQUEMASK    0xfU
23423 #define V_FRMWRQUEMASK(x) ((x) << S_FRMWRQUEMASK)
23424 #define G_FRMWRQUEMASK(x) (((x) >> S_FRMWRQUEMASK) & M_FRMWRQUEMASK)
23425 
23426 #define A_TP_RSS_CONFIG_SYN 0x7dfc
23427 #define A_TP_RSS_CONFIG_VRT 0x7e00
23428 
23429 #define S_VFRDRG    25
23430 #define V_VFRDRG(x) ((x) << S_VFRDRG)
23431 #define F_VFRDRG    V_VFRDRG(1U)
23432 
23433 #define S_VFRDEN    24
23434 #define V_VFRDEN(x) ((x) << S_VFRDEN)
23435 #define F_VFRDEN    V_VFRDEN(1U)
23436 
23437 #define S_VFPERREN    23
23438 #define V_VFPERREN(x) ((x) << S_VFPERREN)
23439 #define F_VFPERREN    V_VFPERREN(1U)
23440 
23441 #define S_KEYPERREN    22
23442 #define V_KEYPERREN(x) ((x) << S_KEYPERREN)
23443 #define F_KEYPERREN    V_KEYPERREN(1U)
23444 
23445 #define S_DISABLEVLAN    21
23446 #define V_DISABLEVLAN(x) ((x) << S_DISABLEVLAN)
23447 #define F_DISABLEVLAN    V_DISABLEVLAN(1U)
23448 
23449 #define S_ENABLEUP0    20
23450 #define V_ENABLEUP0(x) ((x) << S_ENABLEUP0)
23451 #define F_ENABLEUP0    V_ENABLEUP0(1U)
23452 
23453 #define S_HASHDELAY    16
23454 #define M_HASHDELAY    0xfU
23455 #define V_HASHDELAY(x) ((x) << S_HASHDELAY)
23456 #define G_HASHDELAY(x) (((x) >> S_HASHDELAY) & M_HASHDELAY)
23457 
23458 #define S_VFWRADDR    8
23459 #define M_VFWRADDR    0x7fU
23460 #define V_VFWRADDR(x) ((x) << S_VFWRADDR)
23461 #define G_VFWRADDR(x) (((x) >> S_VFWRADDR) & M_VFWRADDR)
23462 
23463 #define S_KEYMODE    6
23464 #define M_KEYMODE    0x3U
23465 #define V_KEYMODE(x) ((x) << S_KEYMODE)
23466 #define G_KEYMODE(x) (((x) >> S_KEYMODE) & M_KEYMODE)
23467 
23468 #define S_VFWREN    5
23469 #define V_VFWREN(x) ((x) << S_VFWREN)
23470 #define F_VFWREN    V_VFWREN(1U)
23471 
23472 #define S_KEYWREN    4
23473 #define V_KEYWREN(x) ((x) << S_KEYWREN)
23474 #define F_KEYWREN    V_KEYWREN(1U)
23475 
23476 #define S_KEYWRADDR    0
23477 #define M_KEYWRADDR    0xfU
23478 #define V_KEYWRADDR(x) ((x) << S_KEYWRADDR)
23479 #define G_KEYWRADDR(x) (((x) >> S_KEYWRADDR) & M_KEYWRADDR)
23480 
23481 #define S_VFVLANEN    21
23482 #define V_VFVLANEN(x) ((x) << S_VFVLANEN)
23483 #define F_VFVLANEN    V_VFVLANEN(1U)
23484 
23485 #define S_VFFWEN    20
23486 #define V_VFFWEN(x) ((x) << S_VFFWEN)
23487 #define F_VFFWEN    V_VFFWEN(1U)
23488 
23489 #define S_KEYWRADDRX    30
23490 #define M_KEYWRADDRX    0x3U
23491 #define V_KEYWRADDRX(x) ((x) << S_KEYWRADDRX)
23492 #define G_KEYWRADDRX(x) (((x) >> S_KEYWRADDRX) & M_KEYWRADDRX)
23493 
23494 #define S_KEYEXTEND    26
23495 #define V_KEYEXTEND(x) ((x) << S_KEYEXTEND)
23496 #define F_KEYEXTEND    V_KEYEXTEND(1U)
23497 
23498 #define S_T6_VFWRADDR    8
23499 #define M_T6_VFWRADDR    0xffU
23500 #define V_T6_VFWRADDR(x) ((x) << S_T6_VFWRADDR)
23501 #define G_T6_VFWRADDR(x) (((x) >> S_T6_VFWRADDR) & M_T6_VFWRADDR)
23502 
23503 #define A_TP_RSS_CONFIG_CNG 0x7e04
23504 
23505 #define S_CHNCOUNT3    31
23506 #define V_CHNCOUNT3(x) ((x) << S_CHNCOUNT3)
23507 #define F_CHNCOUNT3    V_CHNCOUNT3(1U)
23508 
23509 #define S_CHNCOUNT2    30
23510 #define V_CHNCOUNT2(x) ((x) << S_CHNCOUNT2)
23511 #define F_CHNCOUNT2    V_CHNCOUNT2(1U)
23512 
23513 #define S_CHNCOUNT1    29
23514 #define V_CHNCOUNT1(x) ((x) << S_CHNCOUNT1)
23515 #define F_CHNCOUNT1    V_CHNCOUNT1(1U)
23516 
23517 #define S_CHNCOUNT0    28
23518 #define V_CHNCOUNT0(x) ((x) << S_CHNCOUNT0)
23519 #define F_CHNCOUNT0    V_CHNCOUNT0(1U)
23520 
23521 #define S_CHNUNDFLOW3    27
23522 #define V_CHNUNDFLOW3(x) ((x) << S_CHNUNDFLOW3)
23523 #define F_CHNUNDFLOW3    V_CHNUNDFLOW3(1U)
23524 
23525 #define S_CHNUNDFLOW2    26
23526 #define V_CHNUNDFLOW2(x) ((x) << S_CHNUNDFLOW2)
23527 #define F_CHNUNDFLOW2    V_CHNUNDFLOW2(1U)
23528 
23529 #define S_CHNUNDFLOW1    25
23530 #define V_CHNUNDFLOW1(x) ((x) << S_CHNUNDFLOW1)
23531 #define F_CHNUNDFLOW1    V_CHNUNDFLOW1(1U)
23532 
23533 #define S_CHNUNDFLOW0    24
23534 #define V_CHNUNDFLOW0(x) ((x) << S_CHNUNDFLOW0)
23535 #define F_CHNUNDFLOW0    V_CHNUNDFLOW0(1U)
23536 
23537 #define S_CHNOVRFLOW3    23
23538 #define V_CHNOVRFLOW3(x) ((x) << S_CHNOVRFLOW3)
23539 #define F_CHNOVRFLOW3    V_CHNOVRFLOW3(1U)
23540 
23541 #define S_CHNOVRFLOW2    22
23542 #define V_CHNOVRFLOW2(x) ((x) << S_CHNOVRFLOW2)
23543 #define F_CHNOVRFLOW2    V_CHNOVRFLOW2(1U)
23544 
23545 #define S_CHNOVRFLOW1    21
23546 #define V_CHNOVRFLOW1(x) ((x) << S_CHNOVRFLOW1)
23547 #define F_CHNOVRFLOW1    V_CHNOVRFLOW1(1U)
23548 
23549 #define S_CHNOVRFLOW0    20
23550 #define V_CHNOVRFLOW0(x) ((x) << S_CHNOVRFLOW0)
23551 #define F_CHNOVRFLOW0    V_CHNOVRFLOW0(1U)
23552 
23553 #define S_RSTCHN3    19
23554 #define V_RSTCHN3(x) ((x) << S_RSTCHN3)
23555 #define F_RSTCHN3    V_RSTCHN3(1U)
23556 
23557 #define S_RSTCHN2    18
23558 #define V_RSTCHN2(x) ((x) << S_RSTCHN2)
23559 #define F_RSTCHN2    V_RSTCHN2(1U)
23560 
23561 #define S_RSTCHN1    17
23562 #define V_RSTCHN1(x) ((x) << S_RSTCHN1)
23563 #define F_RSTCHN1    V_RSTCHN1(1U)
23564 
23565 #define S_RSTCHN0    16
23566 #define V_RSTCHN0(x) ((x) << S_RSTCHN0)
23567 #define F_RSTCHN0    V_RSTCHN0(1U)
23568 
23569 #define S_UPDVLD    15
23570 #define V_UPDVLD(x) ((x) << S_UPDVLD)
23571 #define F_UPDVLD    V_UPDVLD(1U)
23572 
23573 #define S_XOFF    14
23574 #define V_XOFF(x) ((x) << S_XOFF)
23575 #define F_XOFF    V_XOFF(1U)
23576 
23577 #define S_UPDCHN3    13
23578 #define V_UPDCHN3(x) ((x) << S_UPDCHN3)
23579 #define F_UPDCHN3    V_UPDCHN3(1U)
23580 
23581 #define S_UPDCHN2    12
23582 #define V_UPDCHN2(x) ((x) << S_UPDCHN2)
23583 #define F_UPDCHN2    V_UPDCHN2(1U)
23584 
23585 #define S_UPDCHN1    11
23586 #define V_UPDCHN1(x) ((x) << S_UPDCHN1)
23587 #define F_UPDCHN1    V_UPDCHN1(1U)
23588 
23589 #define S_UPDCHN0    10
23590 #define V_UPDCHN0(x) ((x) << S_UPDCHN0)
23591 #define F_UPDCHN0    V_UPDCHN0(1U)
23592 
23593 #define S_QUEUE    0
23594 #define M_QUEUE    0x3ffU
23595 #define V_QUEUE(x) ((x) << S_QUEUE)
23596 #define G_QUEUE(x) (((x) >> S_QUEUE) & M_QUEUE)
23597 
23598 #define A_TP_LA_TABLE_0 0x7e10
23599 
23600 #define S_VIRTPORT1TABLE    16
23601 #define M_VIRTPORT1TABLE    0xffffU
23602 #define V_VIRTPORT1TABLE(x) ((x) << S_VIRTPORT1TABLE)
23603 #define G_VIRTPORT1TABLE(x) (((x) >> S_VIRTPORT1TABLE) & M_VIRTPORT1TABLE)
23604 
23605 #define S_VIRTPORT0TABLE    0
23606 #define M_VIRTPORT0TABLE    0xffffU
23607 #define V_VIRTPORT0TABLE(x) ((x) << S_VIRTPORT0TABLE)
23608 #define G_VIRTPORT0TABLE(x) (((x) >> S_VIRTPORT0TABLE) & M_VIRTPORT0TABLE)
23609 
23610 #define A_TP_LA_TABLE_1 0x7e14
23611 
23612 #define S_VIRTPORT3TABLE    16
23613 #define M_VIRTPORT3TABLE    0xffffU
23614 #define V_VIRTPORT3TABLE(x) ((x) << S_VIRTPORT3TABLE)
23615 #define G_VIRTPORT3TABLE(x) (((x) >> S_VIRTPORT3TABLE) & M_VIRTPORT3TABLE)
23616 
23617 #define S_VIRTPORT2TABLE    0
23618 #define M_VIRTPORT2TABLE    0xffffU
23619 #define V_VIRTPORT2TABLE(x) ((x) << S_VIRTPORT2TABLE)
23620 #define G_VIRTPORT2TABLE(x) (((x) >> S_VIRTPORT2TABLE) & M_VIRTPORT2TABLE)
23621 
23622 #define A_TP_TM_PIO_ADDR 0x7e18
23623 #define A_TP_TM_PIO_DATA 0x7e1c
23624 #define A_TP_MOD_CONFIG 0x7e24
23625 
23626 #define S_RXCHANNELWEIGHT1    24
23627 #define M_RXCHANNELWEIGHT1    0xffU
23628 #define V_RXCHANNELWEIGHT1(x) ((x) << S_RXCHANNELWEIGHT1)
23629 #define G_RXCHANNELWEIGHT1(x) (((x) >> S_RXCHANNELWEIGHT1) & M_RXCHANNELWEIGHT1)
23630 
23631 #define S_RXCHANNELWEIGHT0    16
23632 #define M_RXCHANNELWEIGHT0    0xffU
23633 #define V_RXCHANNELWEIGHT0(x) ((x) << S_RXCHANNELWEIGHT0)
23634 #define G_RXCHANNELWEIGHT0(x) (((x) >> S_RXCHANNELWEIGHT0) & M_RXCHANNELWEIGHT0)
23635 
23636 #define S_TIMERMODE    8
23637 #define M_TIMERMODE    0xffU
23638 #define V_TIMERMODE(x) ((x) << S_TIMERMODE)
23639 #define G_TIMERMODE(x) (((x) >> S_TIMERMODE) & M_TIMERMODE)
23640 
23641 #define S_TXCHANNELXOFFEN    0
23642 #define M_TXCHANNELXOFFEN    0xfU
23643 #define V_TXCHANNELXOFFEN(x) ((x) << S_TXCHANNELXOFFEN)
23644 #define G_TXCHANNELXOFFEN(x) (((x) >> S_TXCHANNELXOFFEN) & M_TXCHANNELXOFFEN)
23645 
23646 #define A_TP_TX_MOD_QUEUE_REQ_MAP 0x7e28
23647 
23648 #define S_RX_MOD_WEIGHT    24
23649 #define M_RX_MOD_WEIGHT    0xffU
23650 #define V_RX_MOD_WEIGHT(x) ((x) << S_RX_MOD_WEIGHT)
23651 #define G_RX_MOD_WEIGHT(x) (((x) >> S_RX_MOD_WEIGHT) & M_RX_MOD_WEIGHT)
23652 
23653 #define S_TX_MOD_WEIGHT    16
23654 #define M_TX_MOD_WEIGHT    0xffU
23655 #define V_TX_MOD_WEIGHT(x) ((x) << S_TX_MOD_WEIGHT)
23656 #define G_TX_MOD_WEIGHT(x) (((x) >> S_TX_MOD_WEIGHT) & M_TX_MOD_WEIGHT)
23657 
23658 #define S_TX_MOD_QUEUE_REQ_MAP    0
23659 #define M_TX_MOD_QUEUE_REQ_MAP    0xffffU
23660 #define V_TX_MOD_QUEUE_REQ_MAP(x) ((x) << S_TX_MOD_QUEUE_REQ_MAP)
23661 #define G_TX_MOD_QUEUE_REQ_MAP(x) (((x) >> S_TX_MOD_QUEUE_REQ_MAP) & M_TX_MOD_QUEUE_REQ_MAP)
23662 
23663 #define A_TP_TX_MOD_QUEUE_WEIGHT1 0x7e2c
23664 
23665 #define S_TX_MODQ_WEIGHT7    24
23666 #define M_TX_MODQ_WEIGHT7    0xffU
23667 #define V_TX_MODQ_WEIGHT7(x) ((x) << S_TX_MODQ_WEIGHT7)
23668 #define G_TX_MODQ_WEIGHT7(x) (((x) >> S_TX_MODQ_WEIGHT7) & M_TX_MODQ_WEIGHT7)
23669 
23670 #define S_TX_MODQ_WEIGHT6    16
23671 #define M_TX_MODQ_WEIGHT6    0xffU
23672 #define V_TX_MODQ_WEIGHT6(x) ((x) << S_TX_MODQ_WEIGHT6)
23673 #define G_TX_MODQ_WEIGHT6(x) (((x) >> S_TX_MODQ_WEIGHT6) & M_TX_MODQ_WEIGHT6)
23674 
23675 #define S_TX_MODQ_WEIGHT5    8
23676 #define M_TX_MODQ_WEIGHT5    0xffU
23677 #define V_TX_MODQ_WEIGHT5(x) ((x) << S_TX_MODQ_WEIGHT5)
23678 #define G_TX_MODQ_WEIGHT5(x) (((x) >> S_TX_MODQ_WEIGHT5) & M_TX_MODQ_WEIGHT5)
23679 
23680 #define S_TX_MODQ_WEIGHT4    0
23681 #define M_TX_MODQ_WEIGHT4    0xffU
23682 #define V_TX_MODQ_WEIGHT4(x) ((x) << S_TX_MODQ_WEIGHT4)
23683 #define G_TX_MODQ_WEIGHT4(x) (((x) >> S_TX_MODQ_WEIGHT4) & M_TX_MODQ_WEIGHT4)
23684 
23685 #define A_TP_TX_MOD_QUEUE_WEIGHT0 0x7e30
23686 
23687 #define S_TX_MODQ_WEIGHT3    24
23688 #define M_TX_MODQ_WEIGHT3    0xffU
23689 #define V_TX_MODQ_WEIGHT3(x) ((x) << S_TX_MODQ_WEIGHT3)
23690 #define G_TX_MODQ_WEIGHT3(x) (((x) >> S_TX_MODQ_WEIGHT3) & M_TX_MODQ_WEIGHT3)
23691 
23692 #define S_TX_MODQ_WEIGHT2    16
23693 #define M_TX_MODQ_WEIGHT2    0xffU
23694 #define V_TX_MODQ_WEIGHT2(x) ((x) << S_TX_MODQ_WEIGHT2)
23695 #define G_TX_MODQ_WEIGHT2(x) (((x) >> S_TX_MODQ_WEIGHT2) & M_TX_MODQ_WEIGHT2)
23696 
23697 #define S_TX_MODQ_WEIGHT1    8
23698 #define M_TX_MODQ_WEIGHT1    0xffU
23699 #define V_TX_MODQ_WEIGHT1(x) ((x) << S_TX_MODQ_WEIGHT1)
23700 #define G_TX_MODQ_WEIGHT1(x) (((x) >> S_TX_MODQ_WEIGHT1) & M_TX_MODQ_WEIGHT1)
23701 
23702 #define S_TX_MODQ_WEIGHT0    0
23703 #define M_TX_MODQ_WEIGHT0    0xffU
23704 #define V_TX_MODQ_WEIGHT0(x) ((x) << S_TX_MODQ_WEIGHT0)
23705 #define G_TX_MODQ_WEIGHT0(x) (((x) >> S_TX_MODQ_WEIGHT0) & M_TX_MODQ_WEIGHT0)
23706 
23707 #define A_TP_TX_MOD_CHANNEL_WEIGHT 0x7e34
23708 #define A_TP_MOD_RATE_LIMIT 0x7e38
23709 
23710 #define S_RX_MOD_RATE_LIMIT_INC    24
23711 #define M_RX_MOD_RATE_LIMIT_INC    0xffU
23712 #define V_RX_MOD_RATE_LIMIT_INC(x) ((x) << S_RX_MOD_RATE_LIMIT_INC)
23713 #define G_RX_MOD_RATE_LIMIT_INC(x) (((x) >> S_RX_MOD_RATE_LIMIT_INC) & M_RX_MOD_RATE_LIMIT_INC)
23714 
23715 #define S_RX_MOD_RATE_LIMIT_TICK    16
23716 #define M_RX_MOD_RATE_LIMIT_TICK    0xffU
23717 #define V_RX_MOD_RATE_LIMIT_TICK(x) ((x) << S_RX_MOD_RATE_LIMIT_TICK)
23718 #define G_RX_MOD_RATE_LIMIT_TICK(x) (((x) >> S_RX_MOD_RATE_LIMIT_TICK) & M_RX_MOD_RATE_LIMIT_TICK)
23719 
23720 #define S_TX_MOD_RATE_LIMIT_INC    8
23721 #define M_TX_MOD_RATE_LIMIT_INC    0xffU
23722 #define V_TX_MOD_RATE_LIMIT_INC(x) ((x) << S_TX_MOD_RATE_LIMIT_INC)
23723 #define G_TX_MOD_RATE_LIMIT_INC(x) (((x) >> S_TX_MOD_RATE_LIMIT_INC) & M_TX_MOD_RATE_LIMIT_INC)
23724 
23725 #define S_TX_MOD_RATE_LIMIT_TICK    0
23726 #define M_TX_MOD_RATE_LIMIT_TICK    0xffU
23727 #define V_TX_MOD_RATE_LIMIT_TICK(x) ((x) << S_TX_MOD_RATE_LIMIT_TICK)
23728 #define G_TX_MOD_RATE_LIMIT_TICK(x) (((x) >> S_TX_MOD_RATE_LIMIT_TICK) & M_TX_MOD_RATE_LIMIT_TICK)
23729 
23730 #define A_TP_PIO_ADDR 0x7e40
23731 #define A_TP_PIO_DATA 0x7e44
23732 #define A_TP_RESET 0x7e4c
23733 
23734 #define S_FLSTINITENABLE    1
23735 #define V_FLSTINITENABLE(x) ((x) << S_FLSTINITENABLE)
23736 #define F_FLSTINITENABLE    V_FLSTINITENABLE(1U)
23737 
23738 #define S_TPRESET    0
23739 #define V_TPRESET(x) ((x) << S_TPRESET)
23740 #define F_TPRESET    V_TPRESET(1U)
23741 
23742 #define A_TP_MIB_INDEX 0x7e50
23743 #define A_TP_MIB_DATA 0x7e54
23744 #define A_TP_SYNC_TIME_HI 0x7e58
23745 #define A_TP_SYNC_TIME_LO 0x7e5c
23746 #define A_TP_CMM_MM_RX_FLST_BASE 0x7e60
23747 #define A_TP_CMM_MM_TX_FLST_BASE 0x7e64
23748 #define A_TP_CMM_MM_PS_FLST_BASE 0x7e68
23749 #define A_TP_CMM_MM_MAX_PSTRUCT 0x7e6c
23750 
23751 #define S_CMMAXPSTRUCT    0
23752 #define M_CMMAXPSTRUCT    0x1fffffU
23753 #define V_CMMAXPSTRUCT(x) ((x) << S_CMMAXPSTRUCT)
23754 #define G_CMMAXPSTRUCT(x) (((x) >> S_CMMAXPSTRUCT) & M_CMMAXPSTRUCT)
23755 
23756 #define A_TP_INT_ENABLE 0x7e70
23757 
23758 #define S_FLMTXFLSTEMPTY    30
23759 #define V_FLMTXFLSTEMPTY(x) ((x) << S_FLMTXFLSTEMPTY)
23760 #define F_FLMTXFLSTEMPTY    V_FLMTXFLSTEMPTY(1U)
23761 
23762 #define S_RSSLKPPERR    29
23763 #define V_RSSLKPPERR(x) ((x) << S_RSSLKPPERR)
23764 #define F_RSSLKPPERR    V_RSSLKPPERR(1U)
23765 
23766 #define S_FLMPERRSET    28
23767 #define V_FLMPERRSET(x) ((x) << S_FLMPERRSET)
23768 #define F_FLMPERRSET    V_FLMPERRSET(1U)
23769 
23770 #define S_PROTOCOLSRAMPERR    27
23771 #define V_PROTOCOLSRAMPERR(x) ((x) << S_PROTOCOLSRAMPERR)
23772 #define F_PROTOCOLSRAMPERR    V_PROTOCOLSRAMPERR(1U)
23773 
23774 #define S_ARPLUTPERR    26
23775 #define V_ARPLUTPERR(x) ((x) << S_ARPLUTPERR)
23776 #define F_ARPLUTPERR    V_ARPLUTPERR(1U)
23777 
23778 #define S_CMRCFOPPERR    25
23779 #define V_CMRCFOPPERR(x) ((x) << S_CMRCFOPPERR)
23780 #define F_CMRCFOPPERR    V_CMRCFOPPERR(1U)
23781 
23782 #define S_CMCACHEPERR    24
23783 #define V_CMCACHEPERR(x) ((x) << S_CMCACHEPERR)
23784 #define F_CMCACHEPERR    V_CMCACHEPERR(1U)
23785 
23786 #define S_CMRCFDATAPERR    23
23787 #define V_CMRCFDATAPERR(x) ((x) << S_CMRCFDATAPERR)
23788 #define F_CMRCFDATAPERR    V_CMRCFDATAPERR(1U)
23789 
23790 #define S_DBL2TLUTPERR    22
23791 #define V_DBL2TLUTPERR(x) ((x) << S_DBL2TLUTPERR)
23792 #define F_DBL2TLUTPERR    V_DBL2TLUTPERR(1U)
23793 
23794 #define S_DBTXTIDPERR    21
23795 #define V_DBTXTIDPERR(x) ((x) << S_DBTXTIDPERR)
23796 #define F_DBTXTIDPERR    V_DBTXTIDPERR(1U)
23797 
23798 #define S_DBEXTPERR    20
23799 #define V_DBEXTPERR(x) ((x) << S_DBEXTPERR)
23800 #define F_DBEXTPERR    V_DBEXTPERR(1U)
23801 
23802 #define S_DBOPPERR    19
23803 #define V_DBOPPERR(x) ((x) << S_DBOPPERR)
23804 #define F_DBOPPERR    V_DBOPPERR(1U)
23805 
23806 #define S_TMCACHEPERR    18
23807 #define V_TMCACHEPERR(x) ((x) << S_TMCACHEPERR)
23808 #define F_TMCACHEPERR    V_TMCACHEPERR(1U)
23809 
23810 #define S_ETPOUTCPLFIFOPERR    17
23811 #define V_ETPOUTCPLFIFOPERR(x) ((x) << S_ETPOUTCPLFIFOPERR)
23812 #define F_ETPOUTCPLFIFOPERR    V_ETPOUTCPLFIFOPERR(1U)
23813 
23814 #define S_ETPOUTTCPFIFOPERR    16
23815 #define V_ETPOUTTCPFIFOPERR(x) ((x) << S_ETPOUTTCPFIFOPERR)
23816 #define F_ETPOUTTCPFIFOPERR    V_ETPOUTTCPFIFOPERR(1U)
23817 
23818 #define S_ETPOUTIPFIFOPERR    15
23819 #define V_ETPOUTIPFIFOPERR(x) ((x) << S_ETPOUTIPFIFOPERR)
23820 #define F_ETPOUTIPFIFOPERR    V_ETPOUTIPFIFOPERR(1U)
23821 
23822 #define S_ETPOUTETHFIFOPERR    14
23823 #define V_ETPOUTETHFIFOPERR(x) ((x) << S_ETPOUTETHFIFOPERR)
23824 #define F_ETPOUTETHFIFOPERR    V_ETPOUTETHFIFOPERR(1U)
23825 
23826 #define S_ETPINCPLFIFOPERR    13
23827 #define V_ETPINCPLFIFOPERR(x) ((x) << S_ETPINCPLFIFOPERR)
23828 #define F_ETPINCPLFIFOPERR    V_ETPINCPLFIFOPERR(1U)
23829 
23830 #define S_ETPINTCPOPTFIFOPERR    12
23831 #define V_ETPINTCPOPTFIFOPERR(x) ((x) << S_ETPINTCPOPTFIFOPERR)
23832 #define F_ETPINTCPOPTFIFOPERR    V_ETPINTCPOPTFIFOPERR(1U)
23833 
23834 #define S_ETPINTCPFIFOPERR    11
23835 #define V_ETPINTCPFIFOPERR(x) ((x) << S_ETPINTCPFIFOPERR)
23836 #define F_ETPINTCPFIFOPERR    V_ETPINTCPFIFOPERR(1U)
23837 
23838 #define S_ETPINIPFIFOPERR    10
23839 #define V_ETPINIPFIFOPERR(x) ((x) << S_ETPINIPFIFOPERR)
23840 #define F_ETPINIPFIFOPERR    V_ETPINIPFIFOPERR(1U)
23841 
23842 #define S_ETPINETHFIFOPERR    9
23843 #define V_ETPINETHFIFOPERR(x) ((x) << S_ETPINETHFIFOPERR)
23844 #define F_ETPINETHFIFOPERR    V_ETPINETHFIFOPERR(1U)
23845 
23846 #define S_CTPOUTCPLFIFOPERR    8
23847 #define V_CTPOUTCPLFIFOPERR(x) ((x) << S_CTPOUTCPLFIFOPERR)
23848 #define F_CTPOUTCPLFIFOPERR    V_CTPOUTCPLFIFOPERR(1U)
23849 
23850 #define S_CTPOUTTCPFIFOPERR    7
23851 #define V_CTPOUTTCPFIFOPERR(x) ((x) << S_CTPOUTTCPFIFOPERR)
23852 #define F_CTPOUTTCPFIFOPERR    V_CTPOUTTCPFIFOPERR(1U)
23853 
23854 #define S_CTPOUTIPFIFOPERR    6
23855 #define V_CTPOUTIPFIFOPERR(x) ((x) << S_CTPOUTIPFIFOPERR)
23856 #define F_CTPOUTIPFIFOPERR    V_CTPOUTIPFIFOPERR(1U)
23857 
23858 #define S_CTPOUTETHFIFOPERR    5
23859 #define V_CTPOUTETHFIFOPERR(x) ((x) << S_CTPOUTETHFIFOPERR)
23860 #define F_CTPOUTETHFIFOPERR    V_CTPOUTETHFIFOPERR(1U)
23861 
23862 #define S_CTPINCPLFIFOPERR    4
23863 #define V_CTPINCPLFIFOPERR(x) ((x) << S_CTPINCPLFIFOPERR)
23864 #define F_CTPINCPLFIFOPERR    V_CTPINCPLFIFOPERR(1U)
23865 
23866 #define S_CTPINTCPOPFIFOPERR    3
23867 #define V_CTPINTCPOPFIFOPERR(x) ((x) << S_CTPINTCPOPFIFOPERR)
23868 #define F_CTPINTCPOPFIFOPERR    V_CTPINTCPOPFIFOPERR(1U)
23869 
23870 #define S_PDUFBKFIFOPERR    2
23871 #define V_PDUFBKFIFOPERR(x) ((x) << S_PDUFBKFIFOPERR)
23872 #define F_PDUFBKFIFOPERR    V_PDUFBKFIFOPERR(1U)
23873 
23874 #define S_CMOPEXTFIFOPERR    1
23875 #define V_CMOPEXTFIFOPERR(x) ((x) << S_CMOPEXTFIFOPERR)
23876 #define F_CMOPEXTFIFOPERR    V_CMOPEXTFIFOPERR(1U)
23877 
23878 #define S_DELINVFIFOPERR    0
23879 #define V_DELINVFIFOPERR(x) ((x) << S_DELINVFIFOPERR)
23880 #define F_DELINVFIFOPERR    V_DELINVFIFOPERR(1U)
23881 
23882 #define S_CTPOUTPLDFIFOPERR    7
23883 #define V_CTPOUTPLDFIFOPERR(x) ((x) << S_CTPOUTPLDFIFOPERR)
23884 #define F_CTPOUTPLDFIFOPERR    V_CTPOUTPLDFIFOPERR(1U)
23885 
23886 #define S_SRQTABLEPERR    1
23887 #define V_SRQTABLEPERR(x) ((x) << S_SRQTABLEPERR)
23888 #define F_SRQTABLEPERR    V_SRQTABLEPERR(1U)
23889 
23890 #define A_TP_INT_CAUSE 0x7e74
23891 #define A_TP_PER_ENABLE 0x7e78
23892 #define A_TP_FLM_FREE_PS_CNT 0x7e80
23893 
23894 #define S_FREEPSTRUCTCOUNT    0
23895 #define M_FREEPSTRUCTCOUNT    0x1fffffU
23896 #define V_FREEPSTRUCTCOUNT(x) ((x) << S_FREEPSTRUCTCOUNT)
23897 #define G_FREEPSTRUCTCOUNT(x) (((x) >> S_FREEPSTRUCTCOUNT) & M_FREEPSTRUCTCOUNT)
23898 
23899 #define A_TP_FLM_FREE_RX_CNT 0x7e84
23900 
23901 #define S_FREERXPAGECHN    28
23902 #define V_FREERXPAGECHN(x) ((x) << S_FREERXPAGECHN)
23903 #define F_FREERXPAGECHN    V_FREERXPAGECHN(1U)
23904 
23905 #define S_FREERXPAGECOUNT    0
23906 #define M_FREERXPAGECOUNT    0x1fffffU
23907 #define V_FREERXPAGECOUNT(x) ((x) << S_FREERXPAGECOUNT)
23908 #define G_FREERXPAGECOUNT(x) (((x) >> S_FREERXPAGECOUNT) & M_FREERXPAGECOUNT)
23909 
23910 #define A_TP_FLM_FREE_TX_CNT 0x7e88
23911 
23912 #define S_FREETXPAGECHN    28
23913 #define M_FREETXPAGECHN    0x3U
23914 #define V_FREETXPAGECHN(x) ((x) << S_FREETXPAGECHN)
23915 #define G_FREETXPAGECHN(x) (((x) >> S_FREETXPAGECHN) & M_FREETXPAGECHN)
23916 
23917 #define S_FREETXPAGECOUNT    0
23918 #define M_FREETXPAGECOUNT    0x1fffffU
23919 #define V_FREETXPAGECOUNT(x) ((x) << S_FREETXPAGECOUNT)
23920 #define G_FREETXPAGECOUNT(x) (((x) >> S_FREETXPAGECOUNT) & M_FREETXPAGECOUNT)
23921 
23922 #define A_TP_TM_HEAP_PUSH_CNT 0x7e8c
23923 #define A_TP_TM_HEAP_POP_CNT 0x7e90
23924 #define A_TP_TM_DACK_PUSH_CNT 0x7e94
23925 #define A_TP_TM_DACK_POP_CNT 0x7e98
23926 #define A_TP_TM_MOD_PUSH_CNT 0x7e9c
23927 #define A_TP_MOD_POP_CNT 0x7ea0
23928 #define A_TP_TIMER_SEPARATOR 0x7ea4
23929 
23930 #define S_TIMERSEPARATOR    16
23931 #define M_TIMERSEPARATOR    0xffffU
23932 #define V_TIMERSEPARATOR(x) ((x) << S_TIMERSEPARATOR)
23933 #define G_TIMERSEPARATOR(x) (((x) >> S_TIMERSEPARATOR) & M_TIMERSEPARATOR)
23934 
23935 #define S_DISABLETIMEFREEZE    0
23936 #define V_DISABLETIMEFREEZE(x) ((x) << S_DISABLETIMEFREEZE)
23937 #define F_DISABLETIMEFREEZE    V_DISABLETIMEFREEZE(1U)
23938 
23939 #define A_TP_STAMP_TIME 0x7ea8
23940 #define A_TP_DEBUG_FLAGS 0x7eac
23941 
23942 #define S_RXTIMERDACKFIRST    26
23943 #define V_RXTIMERDACKFIRST(x) ((x) << S_RXTIMERDACKFIRST)
23944 #define F_RXTIMERDACKFIRST    V_RXTIMERDACKFIRST(1U)
23945 
23946 #define S_RXTIMERDACK    25
23947 #define V_RXTIMERDACK(x) ((x) << S_RXTIMERDACK)
23948 #define F_RXTIMERDACK    V_RXTIMERDACK(1U)
23949 
23950 #define S_RXTIMERHEARTBEAT    24
23951 #define V_RXTIMERHEARTBEAT(x) ((x) << S_RXTIMERHEARTBEAT)
23952 #define F_RXTIMERHEARTBEAT    V_RXTIMERHEARTBEAT(1U)
23953 
23954 #define S_RXPAWSDROP    23
23955 #define V_RXPAWSDROP(x) ((x) << S_RXPAWSDROP)
23956 #define F_RXPAWSDROP    V_RXPAWSDROP(1U)
23957 
23958 #define S_RXURGDATADROP    22
23959 #define V_RXURGDATADROP(x) ((x) << S_RXURGDATADROP)
23960 #define F_RXURGDATADROP    V_RXURGDATADROP(1U)
23961 
23962 #define S_RXFUTUREDATA    21
23963 #define V_RXFUTUREDATA(x) ((x) << S_RXFUTUREDATA)
23964 #define F_RXFUTUREDATA    V_RXFUTUREDATA(1U)
23965 
23966 #define S_RXRCVRXMDATA    20
23967 #define V_RXRCVRXMDATA(x) ((x) << S_RXRCVRXMDATA)
23968 #define F_RXRCVRXMDATA    V_RXRCVRXMDATA(1U)
23969 
23970 #define S_RXRCVOOODATAFIN    19
23971 #define V_RXRCVOOODATAFIN(x) ((x) << S_RXRCVOOODATAFIN)
23972 #define F_RXRCVOOODATAFIN    V_RXRCVOOODATAFIN(1U)
23973 
23974 #define S_RXRCVOOODATA    18
23975 #define V_RXRCVOOODATA(x) ((x) << S_RXRCVOOODATA)
23976 #define F_RXRCVOOODATA    V_RXRCVOOODATA(1U)
23977 
23978 #define S_RXRCVWNDZERO    17
23979 #define V_RXRCVWNDZERO(x) ((x) << S_RXRCVWNDZERO)
23980 #define F_RXRCVWNDZERO    V_RXRCVWNDZERO(1U)
23981 
23982 #define S_RXRCVWNDLTMSS    16
23983 #define V_RXRCVWNDLTMSS(x) ((x) << S_RXRCVWNDLTMSS)
23984 #define F_RXRCVWNDLTMSS    V_RXRCVWNDLTMSS(1U)
23985 
23986 #define S_TXDUPACKINC    11
23987 #define V_TXDUPACKINC(x) ((x) << S_TXDUPACKINC)
23988 #define F_TXDUPACKINC    V_TXDUPACKINC(1U)
23989 
23990 #define S_TXRXMURG    10
23991 #define V_TXRXMURG(x) ((x) << S_TXRXMURG)
23992 #define F_TXRXMURG    V_TXRXMURG(1U)
23993 
23994 #define S_TXRXMFIN    9
23995 #define V_TXRXMFIN(x) ((x) << S_TXRXMFIN)
23996 #define F_TXRXMFIN    V_TXRXMFIN(1U)
23997 
23998 #define S_TXRXMSYN    8
23999 #define V_TXRXMSYN(x) ((x) << S_TXRXMSYN)
24000 #define F_TXRXMSYN    V_TXRXMSYN(1U)
24001 
24002 #define S_TXRXMNEWRENO    7
24003 #define V_TXRXMNEWRENO(x) ((x) << S_TXRXMNEWRENO)
24004 #define F_TXRXMNEWRENO    V_TXRXMNEWRENO(1U)
24005 
24006 #define S_TXRXMFAST    6
24007 #define V_TXRXMFAST(x) ((x) << S_TXRXMFAST)
24008 #define F_TXRXMFAST    V_TXRXMFAST(1U)
24009 
24010 #define S_TXRXMTIMER    5
24011 #define V_TXRXMTIMER(x) ((x) << S_TXRXMTIMER)
24012 #define F_TXRXMTIMER    V_TXRXMTIMER(1U)
24013 
24014 #define S_TXRXMTIMERKEEPALIVE    4
24015 #define V_TXRXMTIMERKEEPALIVE(x) ((x) << S_TXRXMTIMERKEEPALIVE)
24016 #define F_TXRXMTIMERKEEPALIVE    V_TXRXMTIMERKEEPALIVE(1U)
24017 
24018 #define S_TXRXMTIMERPERSIST    3
24019 #define V_TXRXMTIMERPERSIST(x) ((x) << S_TXRXMTIMERPERSIST)
24020 #define F_TXRXMTIMERPERSIST    V_TXRXMTIMERPERSIST(1U)
24021 
24022 #define S_TXRCVADVSHRUNK    2
24023 #define V_TXRCVADVSHRUNK(x) ((x) << S_TXRCVADVSHRUNK)
24024 #define F_TXRCVADVSHRUNK    V_TXRCVADVSHRUNK(1U)
24025 
24026 #define S_TXRCVADVZERO    1
24027 #define V_TXRCVADVZERO(x) ((x) << S_TXRCVADVZERO)
24028 #define F_TXRCVADVZERO    V_TXRCVADVZERO(1U)
24029 
24030 #define S_TXRCVADVLTMSS    0
24031 #define V_TXRCVADVLTMSS(x) ((x) << S_TXRCVADVLTMSS)
24032 #define F_TXRCVADVLTMSS    V_TXRCVADVLTMSS(1U)
24033 
24034 #define S_RXTIMERCOMPBUFFER    27
24035 #define V_RXTIMERCOMPBUFFER(x) ((x) << S_RXTIMERCOMPBUFFER)
24036 #define F_RXTIMERCOMPBUFFER    V_RXTIMERCOMPBUFFER(1U)
24037 
24038 #define S_TXDFRFAST    13
24039 #define V_TXDFRFAST(x) ((x) << S_TXDFRFAST)
24040 #define F_TXDFRFAST    V_TXDFRFAST(1U)
24041 
24042 #define S_TXRXMMISC    12
24043 #define V_TXRXMMISC(x) ((x) << S_TXRXMMISC)
24044 #define F_TXRXMMISC    V_TXRXMMISC(1U)
24045 
24046 #define A_TP_RX_SCHED 0x7eb0
24047 
24048 #define S_RXCOMMITRESET1    31
24049 #define V_RXCOMMITRESET1(x) ((x) << S_RXCOMMITRESET1)
24050 #define F_RXCOMMITRESET1    V_RXCOMMITRESET1(1U)
24051 
24052 #define S_RXCOMMITRESET0    30
24053 #define V_RXCOMMITRESET0(x) ((x) << S_RXCOMMITRESET0)
24054 #define F_RXCOMMITRESET0    V_RXCOMMITRESET0(1U)
24055 
24056 #define S_RXFORCECONG1    29
24057 #define V_RXFORCECONG1(x) ((x) << S_RXFORCECONG1)
24058 #define F_RXFORCECONG1    V_RXFORCECONG1(1U)
24059 
24060 #define S_RXFORCECONG0    28
24061 #define V_RXFORCECONG0(x) ((x) << S_RXFORCECONG0)
24062 #define F_RXFORCECONG0    V_RXFORCECONG0(1U)
24063 
24064 #define S_ENABLELPBKFULL1    26
24065 #define M_ENABLELPBKFULL1    0x3U
24066 #define V_ENABLELPBKFULL1(x) ((x) << S_ENABLELPBKFULL1)
24067 #define G_ENABLELPBKFULL1(x) (((x) >> S_ENABLELPBKFULL1) & M_ENABLELPBKFULL1)
24068 
24069 #define S_ENABLELPBKFULL0    24
24070 #define M_ENABLELPBKFULL0    0x3U
24071 #define V_ENABLELPBKFULL0(x) ((x) << S_ENABLELPBKFULL0)
24072 #define G_ENABLELPBKFULL0(x) (((x) >> S_ENABLELPBKFULL0) & M_ENABLELPBKFULL0)
24073 
24074 #define S_ENABLEFIFOFULL1    22
24075 #define M_ENABLEFIFOFULL1    0x3U
24076 #define V_ENABLEFIFOFULL1(x) ((x) << S_ENABLEFIFOFULL1)
24077 #define G_ENABLEFIFOFULL1(x) (((x) >> S_ENABLEFIFOFULL1) & M_ENABLEFIFOFULL1)
24078 
24079 #define S_ENABLEPCMDFULL1    20
24080 #define M_ENABLEPCMDFULL1    0x3U
24081 #define V_ENABLEPCMDFULL1(x) ((x) << S_ENABLEPCMDFULL1)
24082 #define G_ENABLEPCMDFULL1(x) (((x) >> S_ENABLEPCMDFULL1) & M_ENABLEPCMDFULL1)
24083 
24084 #define S_ENABLEHDRFULL1    18
24085 #define M_ENABLEHDRFULL1    0x3U
24086 #define V_ENABLEHDRFULL1(x) ((x) << S_ENABLEHDRFULL1)
24087 #define G_ENABLEHDRFULL1(x) (((x) >> S_ENABLEHDRFULL1) & M_ENABLEHDRFULL1)
24088 
24089 #define S_ENABLEFIFOFULL0    16
24090 #define M_ENABLEFIFOFULL0    0x3U
24091 #define V_ENABLEFIFOFULL0(x) ((x) << S_ENABLEFIFOFULL0)
24092 #define G_ENABLEFIFOFULL0(x) (((x) >> S_ENABLEFIFOFULL0) & M_ENABLEFIFOFULL0)
24093 
24094 #define S_ENABLEPCMDFULL0    14
24095 #define M_ENABLEPCMDFULL0    0x3U
24096 #define V_ENABLEPCMDFULL0(x) ((x) << S_ENABLEPCMDFULL0)
24097 #define G_ENABLEPCMDFULL0(x) (((x) >> S_ENABLEPCMDFULL0) & M_ENABLEPCMDFULL0)
24098 
24099 #define S_ENABLEHDRFULL0    12
24100 #define M_ENABLEHDRFULL0    0x3U
24101 #define V_ENABLEHDRFULL0(x) ((x) << S_ENABLEHDRFULL0)
24102 #define G_ENABLEHDRFULL0(x) (((x) >> S_ENABLEHDRFULL0) & M_ENABLEHDRFULL0)
24103 
24104 #define S_COMMITLIMIT1    6
24105 #define M_COMMITLIMIT1    0x3fU
24106 #define V_COMMITLIMIT1(x) ((x) << S_COMMITLIMIT1)
24107 #define G_COMMITLIMIT1(x) (((x) >> S_COMMITLIMIT1) & M_COMMITLIMIT1)
24108 
24109 #define S_COMMITLIMIT0    0
24110 #define M_COMMITLIMIT0    0x3fU
24111 #define V_COMMITLIMIT0(x) ((x) << S_COMMITLIMIT0)
24112 #define G_COMMITLIMIT0(x) (((x) >> S_COMMITLIMIT0) & M_COMMITLIMIT0)
24113 
24114 #define A_TP_TX_SCHED 0x7eb4
24115 
24116 #define S_COMMITRESET3    31
24117 #define V_COMMITRESET3(x) ((x) << S_COMMITRESET3)
24118 #define F_COMMITRESET3    V_COMMITRESET3(1U)
24119 
24120 #define S_COMMITRESET2    30
24121 #define V_COMMITRESET2(x) ((x) << S_COMMITRESET2)
24122 #define F_COMMITRESET2    V_COMMITRESET2(1U)
24123 
24124 #define S_COMMITRESET1    29
24125 #define V_COMMITRESET1(x) ((x) << S_COMMITRESET1)
24126 #define F_COMMITRESET1    V_COMMITRESET1(1U)
24127 
24128 #define S_COMMITRESET0    28
24129 #define V_COMMITRESET0(x) ((x) << S_COMMITRESET0)
24130 #define F_COMMITRESET0    V_COMMITRESET0(1U)
24131 
24132 #define S_FORCECONG3    27
24133 #define V_FORCECONG3(x) ((x) << S_FORCECONG3)
24134 #define F_FORCECONG3    V_FORCECONG3(1U)
24135 
24136 #define S_FORCECONG2    26
24137 #define V_FORCECONG2(x) ((x) << S_FORCECONG2)
24138 #define F_FORCECONG2    V_FORCECONG2(1U)
24139 
24140 #define S_FORCECONG1    25
24141 #define V_FORCECONG1(x) ((x) << S_FORCECONG1)
24142 #define F_FORCECONG1    V_FORCECONG1(1U)
24143 
24144 #define S_FORCECONG0    24
24145 #define V_FORCECONG0(x) ((x) << S_FORCECONG0)
24146 #define F_FORCECONG0    V_FORCECONG0(1U)
24147 
24148 #define S_COMMITLIMIT3    18
24149 #define M_COMMITLIMIT3    0x3fU
24150 #define V_COMMITLIMIT3(x) ((x) << S_COMMITLIMIT3)
24151 #define G_COMMITLIMIT3(x) (((x) >> S_COMMITLIMIT3) & M_COMMITLIMIT3)
24152 
24153 #define S_COMMITLIMIT2    12
24154 #define M_COMMITLIMIT2    0x3fU
24155 #define V_COMMITLIMIT2(x) ((x) << S_COMMITLIMIT2)
24156 #define G_COMMITLIMIT2(x) (((x) >> S_COMMITLIMIT2) & M_COMMITLIMIT2)
24157 
24158 #define A_TP_FX_SCHED 0x7eb8
24159 
24160 #define S_TXCHNXOFF3    19
24161 #define V_TXCHNXOFF3(x) ((x) << S_TXCHNXOFF3)
24162 #define F_TXCHNXOFF3    V_TXCHNXOFF3(1U)
24163 
24164 #define S_TXCHNXOFF2    18
24165 #define V_TXCHNXOFF2(x) ((x) << S_TXCHNXOFF2)
24166 #define F_TXCHNXOFF2    V_TXCHNXOFF2(1U)
24167 
24168 #define S_TXCHNXOFF1    17
24169 #define V_TXCHNXOFF1(x) ((x) << S_TXCHNXOFF1)
24170 #define F_TXCHNXOFF1    V_TXCHNXOFF1(1U)
24171 
24172 #define S_TXCHNXOFF0    16
24173 #define V_TXCHNXOFF0(x) ((x) << S_TXCHNXOFF0)
24174 #define F_TXCHNXOFF0    V_TXCHNXOFF0(1U)
24175 
24176 #define S_TXMODXOFF7    15
24177 #define V_TXMODXOFF7(x) ((x) << S_TXMODXOFF7)
24178 #define F_TXMODXOFF7    V_TXMODXOFF7(1U)
24179 
24180 #define S_TXMODXOFF6    14
24181 #define V_TXMODXOFF6(x) ((x) << S_TXMODXOFF6)
24182 #define F_TXMODXOFF6    V_TXMODXOFF6(1U)
24183 
24184 #define S_TXMODXOFF5    13
24185 #define V_TXMODXOFF5(x) ((x) << S_TXMODXOFF5)
24186 #define F_TXMODXOFF5    V_TXMODXOFF5(1U)
24187 
24188 #define S_TXMODXOFF4    12
24189 #define V_TXMODXOFF4(x) ((x) << S_TXMODXOFF4)
24190 #define F_TXMODXOFF4    V_TXMODXOFF4(1U)
24191 
24192 #define S_TXMODXOFF3    11
24193 #define V_TXMODXOFF3(x) ((x) << S_TXMODXOFF3)
24194 #define F_TXMODXOFF3    V_TXMODXOFF3(1U)
24195 
24196 #define S_TXMODXOFF2    10
24197 #define V_TXMODXOFF2(x) ((x) << S_TXMODXOFF2)
24198 #define F_TXMODXOFF2    V_TXMODXOFF2(1U)
24199 
24200 #define S_TXMODXOFF1    9
24201 #define V_TXMODXOFF1(x) ((x) << S_TXMODXOFF1)
24202 #define F_TXMODXOFF1    V_TXMODXOFF1(1U)
24203 
24204 #define S_TXMODXOFF0    8
24205 #define V_TXMODXOFF0(x) ((x) << S_TXMODXOFF0)
24206 #define F_TXMODXOFF0    V_TXMODXOFF0(1U)
24207 
24208 #define S_RXCHNXOFF3    7
24209 #define V_RXCHNXOFF3(x) ((x) << S_RXCHNXOFF3)
24210 #define F_RXCHNXOFF3    V_RXCHNXOFF3(1U)
24211 
24212 #define S_RXCHNXOFF2    6
24213 #define V_RXCHNXOFF2(x) ((x) << S_RXCHNXOFF2)
24214 #define F_RXCHNXOFF2    V_RXCHNXOFF2(1U)
24215 
24216 #define S_RXCHNXOFF1    5
24217 #define V_RXCHNXOFF1(x) ((x) << S_RXCHNXOFF1)
24218 #define F_RXCHNXOFF1    V_RXCHNXOFF1(1U)
24219 
24220 #define S_RXCHNXOFF0    4
24221 #define V_RXCHNXOFF0(x) ((x) << S_RXCHNXOFF0)
24222 #define F_RXCHNXOFF0    V_RXCHNXOFF0(1U)
24223 
24224 #define S_RXMODXOFF1    1
24225 #define V_RXMODXOFF1(x) ((x) << S_RXMODXOFF1)
24226 #define F_RXMODXOFF1    V_RXMODXOFF1(1U)
24227 
24228 #define S_RXMODXOFF0    0
24229 #define V_RXMODXOFF0(x) ((x) << S_RXMODXOFF0)
24230 #define F_RXMODXOFF0    V_RXMODXOFF0(1U)
24231 
24232 #define A_TP_TX_ORATE 0x7ebc
24233 
24234 #define S_OFDRATE3    24
24235 #define M_OFDRATE3    0xffU
24236 #define V_OFDRATE3(x) ((x) << S_OFDRATE3)
24237 #define G_OFDRATE3(x) (((x) >> S_OFDRATE3) & M_OFDRATE3)
24238 
24239 #define S_OFDRATE2    16
24240 #define M_OFDRATE2    0xffU
24241 #define V_OFDRATE2(x) ((x) << S_OFDRATE2)
24242 #define G_OFDRATE2(x) (((x) >> S_OFDRATE2) & M_OFDRATE2)
24243 
24244 #define S_OFDRATE1    8
24245 #define M_OFDRATE1    0xffU
24246 #define V_OFDRATE1(x) ((x) << S_OFDRATE1)
24247 #define G_OFDRATE1(x) (((x) >> S_OFDRATE1) & M_OFDRATE1)
24248 
24249 #define S_OFDRATE0    0
24250 #define M_OFDRATE0    0xffU
24251 #define V_OFDRATE0(x) ((x) << S_OFDRATE0)
24252 #define G_OFDRATE0(x) (((x) >> S_OFDRATE0) & M_OFDRATE0)
24253 
24254 #define A_TP_IX_SCHED0 0x7ec0
24255 #define A_TP_IX_SCHED1 0x7ec4
24256 #define A_TP_IX_SCHED2 0x7ec8
24257 #define A_TP_IX_SCHED3 0x7ecc
24258 #define A_TP_TX_TRATE 0x7ed0
24259 
24260 #define S_TNLRATE3    24
24261 #define M_TNLRATE3    0xffU
24262 #define V_TNLRATE3(x) ((x) << S_TNLRATE3)
24263 #define G_TNLRATE3(x) (((x) >> S_TNLRATE3) & M_TNLRATE3)
24264 
24265 #define S_TNLRATE2    16
24266 #define M_TNLRATE2    0xffU
24267 #define V_TNLRATE2(x) ((x) << S_TNLRATE2)
24268 #define G_TNLRATE2(x) (((x) >> S_TNLRATE2) & M_TNLRATE2)
24269 
24270 #define S_TNLRATE1    8
24271 #define M_TNLRATE1    0xffU
24272 #define V_TNLRATE1(x) ((x) << S_TNLRATE1)
24273 #define G_TNLRATE1(x) (((x) >> S_TNLRATE1) & M_TNLRATE1)
24274 
24275 #define S_TNLRATE0    0
24276 #define M_TNLRATE0    0xffU
24277 #define V_TNLRATE0(x) ((x) << S_TNLRATE0)
24278 #define G_TNLRATE0(x) (((x) >> S_TNLRATE0) & M_TNLRATE0)
24279 
24280 #define A_TP_DBG_LA_CONFIG 0x7ed4
24281 
24282 #define S_DBGLAOPCENABLE    24
24283 #define M_DBGLAOPCENABLE    0xffU
24284 #define V_DBGLAOPCENABLE(x) ((x) << S_DBGLAOPCENABLE)
24285 #define G_DBGLAOPCENABLE(x) (((x) >> S_DBGLAOPCENABLE) & M_DBGLAOPCENABLE)
24286 
24287 #define S_DBGLAWHLF    23
24288 #define V_DBGLAWHLF(x) ((x) << S_DBGLAWHLF)
24289 #define F_DBGLAWHLF    V_DBGLAWHLF(1U)
24290 
24291 #define S_DBGLAWPTR    16
24292 #define M_DBGLAWPTR    0x7fU
24293 #define V_DBGLAWPTR(x) ((x) << S_DBGLAWPTR)
24294 #define G_DBGLAWPTR(x) (((x) >> S_DBGLAWPTR) & M_DBGLAWPTR)
24295 
24296 #define S_DBGLAMODE    14
24297 #define M_DBGLAMODE    0x3U
24298 #define V_DBGLAMODE(x) ((x) << S_DBGLAMODE)
24299 #define G_DBGLAMODE(x) (((x) >> S_DBGLAMODE) & M_DBGLAMODE)
24300 
24301 #define S_DBGLAFATALFREEZE    13
24302 #define V_DBGLAFATALFREEZE(x) ((x) << S_DBGLAFATALFREEZE)
24303 #define F_DBGLAFATALFREEZE    V_DBGLAFATALFREEZE(1U)
24304 
24305 #define S_DBGLAENABLE    12
24306 #define V_DBGLAENABLE(x) ((x) << S_DBGLAENABLE)
24307 #define F_DBGLAENABLE    V_DBGLAENABLE(1U)
24308 
24309 #define S_DBGLARPTR    0
24310 #define M_DBGLARPTR    0x7fU
24311 #define V_DBGLARPTR(x) ((x) << S_DBGLARPTR)
24312 #define G_DBGLARPTR(x) (((x) >> S_DBGLARPTR) & M_DBGLARPTR)
24313 
24314 #define A_TP_DBG_LA_DATAL 0x7ed8
24315 #define A_TP_DBG_LA_DATAH 0x7edc
24316 #define A_TP_PROTOCOL_CNTRL 0x7ee8
24317 
24318 #define S_WRITEENABLE    31
24319 #define V_WRITEENABLE(x) ((x) << S_WRITEENABLE)
24320 #define F_WRITEENABLE    V_WRITEENABLE(1U)
24321 
24322 #define S_TCAMENABLE    10
24323 #define V_TCAMENABLE(x) ((x) << S_TCAMENABLE)
24324 #define F_TCAMENABLE    V_TCAMENABLE(1U)
24325 
24326 #define S_BLOCKSELECT    8
24327 #define M_BLOCKSELECT    0x3U
24328 #define V_BLOCKSELECT(x) ((x) << S_BLOCKSELECT)
24329 #define G_BLOCKSELECT(x) (((x) >> S_BLOCKSELECT) & M_BLOCKSELECT)
24330 
24331 #define S_LINEADDRESS    1
24332 #define M_LINEADDRESS    0x7fU
24333 #define V_LINEADDRESS(x) ((x) << S_LINEADDRESS)
24334 #define G_LINEADDRESS(x) (((x) >> S_LINEADDRESS) & M_LINEADDRESS)
24335 
24336 #define S_REQUESTDONE    0
24337 #define V_REQUESTDONE(x) ((x) << S_REQUESTDONE)
24338 #define F_REQUESTDONE    V_REQUESTDONE(1U)
24339 
24340 #define A_TP_PROTOCOL_DATA0 0x7eec
24341 #define A_TP_PROTOCOL_DATA1 0x7ef0
24342 #define A_TP_PROTOCOL_DATA2 0x7ef4
24343 #define A_TP_PROTOCOL_DATA3 0x7ef8
24344 #define A_TP_PROTOCOL_DATA4 0x7efc
24345 
24346 #define S_PROTOCOLDATAFIELD    0
24347 #define M_PROTOCOLDATAFIELD    0xfU
24348 #define V_PROTOCOLDATAFIELD(x) ((x) << S_PROTOCOLDATAFIELD)
24349 #define G_PROTOCOLDATAFIELD(x) (((x) >> S_PROTOCOLDATAFIELD) & M_PROTOCOLDATAFIELD)
24350 
24351 #define A_TP_TX_MOD_Q7_Q6_TIMER_SEPARATOR 0x0
24352 
24353 #define S_TXTIMERSEPQ7    16
24354 #define M_TXTIMERSEPQ7    0xffffU
24355 #define V_TXTIMERSEPQ7(x) ((x) << S_TXTIMERSEPQ7)
24356 #define G_TXTIMERSEPQ7(x) (((x) >> S_TXTIMERSEPQ7) & M_TXTIMERSEPQ7)
24357 
24358 #define S_TXTIMERSEPQ6    0
24359 #define M_TXTIMERSEPQ6    0xffffU
24360 #define V_TXTIMERSEPQ6(x) ((x) << S_TXTIMERSEPQ6)
24361 #define G_TXTIMERSEPQ6(x) (((x) >> S_TXTIMERSEPQ6) & M_TXTIMERSEPQ6)
24362 
24363 #define A_TP_TX_MOD_Q5_Q4_TIMER_SEPARATOR 0x1
24364 
24365 #define S_TXTIMERSEPQ5    16
24366 #define M_TXTIMERSEPQ5    0xffffU
24367 #define V_TXTIMERSEPQ5(x) ((x) << S_TXTIMERSEPQ5)
24368 #define G_TXTIMERSEPQ5(x) (((x) >> S_TXTIMERSEPQ5) & M_TXTIMERSEPQ5)
24369 
24370 #define S_TXTIMERSEPQ4    0
24371 #define M_TXTIMERSEPQ4    0xffffU
24372 #define V_TXTIMERSEPQ4(x) ((x) << S_TXTIMERSEPQ4)
24373 #define G_TXTIMERSEPQ4(x) (((x) >> S_TXTIMERSEPQ4) & M_TXTIMERSEPQ4)
24374 
24375 #define A_TP_TX_MOD_Q3_Q2_TIMER_SEPARATOR 0x2
24376 
24377 #define S_TXTIMERSEPQ3    16
24378 #define M_TXTIMERSEPQ3    0xffffU
24379 #define V_TXTIMERSEPQ3(x) ((x) << S_TXTIMERSEPQ3)
24380 #define G_TXTIMERSEPQ3(x) (((x) >> S_TXTIMERSEPQ3) & M_TXTIMERSEPQ3)
24381 
24382 #define S_TXTIMERSEPQ2    0
24383 #define M_TXTIMERSEPQ2    0xffffU
24384 #define V_TXTIMERSEPQ2(x) ((x) << S_TXTIMERSEPQ2)
24385 #define G_TXTIMERSEPQ2(x) (((x) >> S_TXTIMERSEPQ2) & M_TXTIMERSEPQ2)
24386 
24387 #define A_TP_TX_MOD_Q1_Q0_TIMER_SEPARATOR 0x3
24388 
24389 #define S_TXTIMERSEPQ1    16
24390 #define M_TXTIMERSEPQ1    0xffffU
24391 #define V_TXTIMERSEPQ1(x) ((x) << S_TXTIMERSEPQ1)
24392 #define G_TXTIMERSEPQ1(x) (((x) >> S_TXTIMERSEPQ1) & M_TXTIMERSEPQ1)
24393 
24394 #define S_TXTIMERSEPQ0    0
24395 #define M_TXTIMERSEPQ0    0xffffU
24396 #define V_TXTIMERSEPQ0(x) ((x) << S_TXTIMERSEPQ0)
24397 #define G_TXTIMERSEPQ0(x) (((x) >> S_TXTIMERSEPQ0) & M_TXTIMERSEPQ0)
24398 
24399 #define A_TP_RX_MOD_Q1_Q0_TIMER_SEPARATOR 0x4
24400 
24401 #define S_RXTIMERSEPQ1    16
24402 #define M_RXTIMERSEPQ1    0xffffU
24403 #define V_RXTIMERSEPQ1(x) ((x) << S_RXTIMERSEPQ1)
24404 #define G_RXTIMERSEPQ1(x) (((x) >> S_RXTIMERSEPQ1) & M_RXTIMERSEPQ1)
24405 
24406 #define S_RXTIMERSEPQ0    0
24407 #define M_RXTIMERSEPQ0    0xffffU
24408 #define V_RXTIMERSEPQ0(x) ((x) << S_RXTIMERSEPQ0)
24409 #define G_RXTIMERSEPQ0(x) (((x) >> S_RXTIMERSEPQ0) & M_RXTIMERSEPQ0)
24410 
24411 #define A_TP_TX_MOD_Q7_Q6_RATE_LIMIT 0x5
24412 
24413 #define S_TXRATEINCQ7    24
24414 #define M_TXRATEINCQ7    0xffU
24415 #define V_TXRATEINCQ7(x) ((x) << S_TXRATEINCQ7)
24416 #define G_TXRATEINCQ7(x) (((x) >> S_TXRATEINCQ7) & M_TXRATEINCQ7)
24417 
24418 #define S_TXRATETCKQ7    16
24419 #define M_TXRATETCKQ7    0xffU
24420 #define V_TXRATETCKQ7(x) ((x) << S_TXRATETCKQ7)
24421 #define G_TXRATETCKQ7(x) (((x) >> S_TXRATETCKQ7) & M_TXRATETCKQ7)
24422 
24423 #define S_TXRATEINCQ6    8
24424 #define M_TXRATEINCQ6    0xffU
24425 #define V_TXRATEINCQ6(x) ((x) << S_TXRATEINCQ6)
24426 #define G_TXRATEINCQ6(x) (((x) >> S_TXRATEINCQ6) & M_TXRATEINCQ6)
24427 
24428 #define S_TXRATETCKQ6    0
24429 #define M_TXRATETCKQ6    0xffU
24430 #define V_TXRATETCKQ6(x) ((x) << S_TXRATETCKQ6)
24431 #define G_TXRATETCKQ6(x) (((x) >> S_TXRATETCKQ6) & M_TXRATETCKQ6)
24432 
24433 #define A_TP_TX_MOD_Q5_Q4_RATE_LIMIT 0x6
24434 
24435 #define S_TXRATEINCQ5    24
24436 #define M_TXRATEINCQ5    0xffU
24437 #define V_TXRATEINCQ5(x) ((x) << S_TXRATEINCQ5)
24438 #define G_TXRATEINCQ5(x) (((x) >> S_TXRATEINCQ5) & M_TXRATEINCQ5)
24439 
24440 #define S_TXRATETCKQ5    16
24441 #define M_TXRATETCKQ5    0xffU
24442 #define V_TXRATETCKQ5(x) ((x) << S_TXRATETCKQ5)
24443 #define G_TXRATETCKQ5(x) (((x) >> S_TXRATETCKQ5) & M_TXRATETCKQ5)
24444 
24445 #define S_TXRATEINCQ4    8
24446 #define M_TXRATEINCQ4    0xffU
24447 #define V_TXRATEINCQ4(x) ((x) << S_TXRATEINCQ4)
24448 #define G_TXRATEINCQ4(x) (((x) >> S_TXRATEINCQ4) & M_TXRATEINCQ4)
24449 
24450 #define S_TXRATETCKQ4    0
24451 #define M_TXRATETCKQ4    0xffU
24452 #define V_TXRATETCKQ4(x) ((x) << S_TXRATETCKQ4)
24453 #define G_TXRATETCKQ4(x) (((x) >> S_TXRATETCKQ4) & M_TXRATETCKQ4)
24454 
24455 #define A_TP_TX_MOD_Q3_Q2_RATE_LIMIT 0x7
24456 
24457 #define S_TXRATEINCQ3    24
24458 #define M_TXRATEINCQ3    0xffU
24459 #define V_TXRATEINCQ3(x) ((x) << S_TXRATEINCQ3)
24460 #define G_TXRATEINCQ3(x) (((x) >> S_TXRATEINCQ3) & M_TXRATEINCQ3)
24461 
24462 #define S_TXRATETCKQ3    16
24463 #define M_TXRATETCKQ3    0xffU
24464 #define V_TXRATETCKQ3(x) ((x) << S_TXRATETCKQ3)
24465 #define G_TXRATETCKQ3(x) (((x) >> S_TXRATETCKQ3) & M_TXRATETCKQ3)
24466 
24467 #define S_TXRATEINCQ2    8
24468 #define M_TXRATEINCQ2    0xffU
24469 #define V_TXRATEINCQ2(x) ((x) << S_TXRATEINCQ2)
24470 #define G_TXRATEINCQ2(x) (((x) >> S_TXRATEINCQ2) & M_TXRATEINCQ2)
24471 
24472 #define S_TXRATETCKQ2    0
24473 #define M_TXRATETCKQ2    0xffU
24474 #define V_TXRATETCKQ2(x) ((x) << S_TXRATETCKQ2)
24475 #define G_TXRATETCKQ2(x) (((x) >> S_TXRATETCKQ2) & M_TXRATETCKQ2)
24476 
24477 #define A_TP_TX_MOD_Q1_Q0_RATE_LIMIT 0x8
24478 
24479 #define S_TXRATEINCQ1    24
24480 #define M_TXRATEINCQ1    0xffU
24481 #define V_TXRATEINCQ1(x) ((x) << S_TXRATEINCQ1)
24482 #define G_TXRATEINCQ1(x) (((x) >> S_TXRATEINCQ1) & M_TXRATEINCQ1)
24483 
24484 #define S_TXRATETCKQ1    16
24485 #define M_TXRATETCKQ1    0xffU
24486 #define V_TXRATETCKQ1(x) ((x) << S_TXRATETCKQ1)
24487 #define G_TXRATETCKQ1(x) (((x) >> S_TXRATETCKQ1) & M_TXRATETCKQ1)
24488 
24489 #define S_TXRATEINCQ0    8
24490 #define M_TXRATEINCQ0    0xffU
24491 #define V_TXRATEINCQ0(x) ((x) << S_TXRATEINCQ0)
24492 #define G_TXRATEINCQ0(x) (((x) >> S_TXRATEINCQ0) & M_TXRATEINCQ0)
24493 
24494 #define S_TXRATETCKQ0    0
24495 #define M_TXRATETCKQ0    0xffU
24496 #define V_TXRATETCKQ0(x) ((x) << S_TXRATETCKQ0)
24497 #define G_TXRATETCKQ0(x) (((x) >> S_TXRATETCKQ0) & M_TXRATETCKQ0)
24498 
24499 #define A_TP_RX_MOD_Q1_Q0_RATE_LIMIT 0x9
24500 
24501 #define S_RXRATEINCQ1    24
24502 #define M_RXRATEINCQ1    0xffU
24503 #define V_RXRATEINCQ1(x) ((x) << S_RXRATEINCQ1)
24504 #define G_RXRATEINCQ1(x) (((x) >> S_RXRATEINCQ1) & M_RXRATEINCQ1)
24505 
24506 #define S_RXRATETCKQ1    16
24507 #define M_RXRATETCKQ1    0xffU
24508 #define V_RXRATETCKQ1(x) ((x) << S_RXRATETCKQ1)
24509 #define G_RXRATETCKQ1(x) (((x) >> S_RXRATETCKQ1) & M_RXRATETCKQ1)
24510 
24511 #define S_RXRATEINCQ0    8
24512 #define M_RXRATEINCQ0    0xffU
24513 #define V_RXRATEINCQ0(x) ((x) << S_RXRATEINCQ0)
24514 #define G_RXRATEINCQ0(x) (((x) >> S_RXRATEINCQ0) & M_RXRATEINCQ0)
24515 
24516 #define S_RXRATETCKQ0    0
24517 #define M_RXRATETCKQ0    0xffU
24518 #define V_RXRATETCKQ0(x) ((x) << S_RXRATETCKQ0)
24519 #define G_RXRATETCKQ0(x) (((x) >> S_RXRATETCKQ0) & M_RXRATETCKQ0)
24520 
24521 #define A_TP_TX_MOD_C3_C2_RATE_LIMIT 0xa
24522 #define A_TP_TX_MOD_C1_C0_RATE_LIMIT 0xb
24523 #define A_TP_RX_SCHED_MAP 0x20
24524 
24525 #define S_RXMAPCHANNEL3    24
24526 #define M_RXMAPCHANNEL3    0xffU
24527 #define V_RXMAPCHANNEL3(x) ((x) << S_RXMAPCHANNEL3)
24528 #define G_RXMAPCHANNEL3(x) (((x) >> S_RXMAPCHANNEL3) & M_RXMAPCHANNEL3)
24529 
24530 #define S_RXMAPCHANNEL2    16
24531 #define M_RXMAPCHANNEL2    0xffU
24532 #define V_RXMAPCHANNEL2(x) ((x) << S_RXMAPCHANNEL2)
24533 #define G_RXMAPCHANNEL2(x) (((x) >> S_RXMAPCHANNEL2) & M_RXMAPCHANNEL2)
24534 
24535 #define S_RXMAPCHANNEL1    8
24536 #define M_RXMAPCHANNEL1    0xffU
24537 #define V_RXMAPCHANNEL1(x) ((x) << S_RXMAPCHANNEL1)
24538 #define G_RXMAPCHANNEL1(x) (((x) >> S_RXMAPCHANNEL1) & M_RXMAPCHANNEL1)
24539 
24540 #define S_RXMAPCHANNEL0    0
24541 #define M_RXMAPCHANNEL0    0xffU
24542 #define V_RXMAPCHANNEL0(x) ((x) << S_RXMAPCHANNEL0)
24543 #define G_RXMAPCHANNEL0(x) (((x) >> S_RXMAPCHANNEL0) & M_RXMAPCHANNEL0)
24544 
24545 #define A_TP_RX_SCHED_SGE 0x21
24546 
24547 #define S_RXSGEMOD1    12
24548 #define M_RXSGEMOD1    0xfU
24549 #define V_RXSGEMOD1(x) ((x) << S_RXSGEMOD1)
24550 #define G_RXSGEMOD1(x) (((x) >> S_RXSGEMOD1) & M_RXSGEMOD1)
24551 
24552 #define S_RXSGEMOD0    8
24553 #define M_RXSGEMOD0    0xfU
24554 #define V_RXSGEMOD0(x) ((x) << S_RXSGEMOD0)
24555 #define G_RXSGEMOD0(x) (((x) >> S_RXSGEMOD0) & M_RXSGEMOD0)
24556 
24557 #define S_RXSGECHANNEL3    3
24558 #define V_RXSGECHANNEL3(x) ((x) << S_RXSGECHANNEL3)
24559 #define F_RXSGECHANNEL3    V_RXSGECHANNEL3(1U)
24560 
24561 #define S_RXSGECHANNEL2    2
24562 #define V_RXSGECHANNEL2(x) ((x) << S_RXSGECHANNEL2)
24563 #define F_RXSGECHANNEL2    V_RXSGECHANNEL2(1U)
24564 
24565 #define S_RXSGECHANNEL1    1
24566 #define V_RXSGECHANNEL1(x) ((x) << S_RXSGECHANNEL1)
24567 #define F_RXSGECHANNEL1    V_RXSGECHANNEL1(1U)
24568 
24569 #define S_RXSGECHANNEL0    0
24570 #define V_RXSGECHANNEL0(x) ((x) << S_RXSGECHANNEL0)
24571 #define F_RXSGECHANNEL0    V_RXSGECHANNEL0(1U)
24572 
24573 #define A_TP_TX_SCHED_MAP 0x22
24574 
24575 #define S_TXMAPCHANNEL3    12
24576 #define M_TXMAPCHANNEL3    0xfU
24577 #define V_TXMAPCHANNEL3(x) ((x) << S_TXMAPCHANNEL3)
24578 #define G_TXMAPCHANNEL3(x) (((x) >> S_TXMAPCHANNEL3) & M_TXMAPCHANNEL3)
24579 
24580 #define S_TXMAPCHANNEL2    8
24581 #define M_TXMAPCHANNEL2    0xfU
24582 #define V_TXMAPCHANNEL2(x) ((x) << S_TXMAPCHANNEL2)
24583 #define G_TXMAPCHANNEL2(x) (((x) >> S_TXMAPCHANNEL2) & M_TXMAPCHANNEL2)
24584 
24585 #define S_TXMAPCHANNEL1    4
24586 #define M_TXMAPCHANNEL1    0xfU
24587 #define V_TXMAPCHANNEL1(x) ((x) << S_TXMAPCHANNEL1)
24588 #define G_TXMAPCHANNEL1(x) (((x) >> S_TXMAPCHANNEL1) & M_TXMAPCHANNEL1)
24589 
24590 #define S_TXMAPCHANNEL0    0
24591 #define M_TXMAPCHANNEL0    0xfU
24592 #define V_TXMAPCHANNEL0(x) ((x) << S_TXMAPCHANNEL0)
24593 #define G_TXMAPCHANNEL0(x) (((x) >> S_TXMAPCHANNEL0) & M_TXMAPCHANNEL0)
24594 
24595 #define S_TXLPKCHANNEL1    17
24596 #define V_TXLPKCHANNEL1(x) ((x) << S_TXLPKCHANNEL1)
24597 #define F_TXLPKCHANNEL1    V_TXLPKCHANNEL1(1U)
24598 
24599 #define S_TXLPKCHANNEL0    16
24600 #define V_TXLPKCHANNEL0(x) ((x) << S_TXLPKCHANNEL0)
24601 #define F_TXLPKCHANNEL0    V_TXLPKCHANNEL0(1U)
24602 
24603 #define A_TP_TX_SCHED_HDR 0x23
24604 
24605 #define S_TXMAPHDRCHANNEL7    28
24606 #define M_TXMAPHDRCHANNEL7    0xfU
24607 #define V_TXMAPHDRCHANNEL7(x) ((x) << S_TXMAPHDRCHANNEL7)
24608 #define G_TXMAPHDRCHANNEL7(x) (((x) >> S_TXMAPHDRCHANNEL7) & M_TXMAPHDRCHANNEL7)
24609 
24610 #define S_TXMAPHDRCHANNEL6    24
24611 #define M_TXMAPHDRCHANNEL6    0xfU
24612 #define V_TXMAPHDRCHANNEL6(x) ((x) << S_TXMAPHDRCHANNEL6)
24613 #define G_TXMAPHDRCHANNEL6(x) (((x) >> S_TXMAPHDRCHANNEL6) & M_TXMAPHDRCHANNEL6)
24614 
24615 #define S_TXMAPHDRCHANNEL5    20
24616 #define M_TXMAPHDRCHANNEL5    0xfU
24617 #define V_TXMAPHDRCHANNEL5(x) ((x) << S_TXMAPHDRCHANNEL5)
24618 #define G_TXMAPHDRCHANNEL5(x) (((x) >> S_TXMAPHDRCHANNEL5) & M_TXMAPHDRCHANNEL5)
24619 
24620 #define S_TXMAPHDRCHANNEL4    16
24621 #define M_TXMAPHDRCHANNEL4    0xfU
24622 #define V_TXMAPHDRCHANNEL4(x) ((x) << S_TXMAPHDRCHANNEL4)
24623 #define G_TXMAPHDRCHANNEL4(x) (((x) >> S_TXMAPHDRCHANNEL4) & M_TXMAPHDRCHANNEL4)
24624 
24625 #define S_TXMAPHDRCHANNEL3    12
24626 #define M_TXMAPHDRCHANNEL3    0xfU
24627 #define V_TXMAPHDRCHANNEL3(x) ((x) << S_TXMAPHDRCHANNEL3)
24628 #define G_TXMAPHDRCHANNEL3(x) (((x) >> S_TXMAPHDRCHANNEL3) & M_TXMAPHDRCHANNEL3)
24629 
24630 #define S_TXMAPHDRCHANNEL2    8
24631 #define M_TXMAPHDRCHANNEL2    0xfU
24632 #define V_TXMAPHDRCHANNEL2(x) ((x) << S_TXMAPHDRCHANNEL2)
24633 #define G_TXMAPHDRCHANNEL2(x) (((x) >> S_TXMAPHDRCHANNEL2) & M_TXMAPHDRCHANNEL2)
24634 
24635 #define S_TXMAPHDRCHANNEL1    4
24636 #define M_TXMAPHDRCHANNEL1    0xfU
24637 #define V_TXMAPHDRCHANNEL1(x) ((x) << S_TXMAPHDRCHANNEL1)
24638 #define G_TXMAPHDRCHANNEL1(x) (((x) >> S_TXMAPHDRCHANNEL1) & M_TXMAPHDRCHANNEL1)
24639 
24640 #define S_TXMAPHDRCHANNEL0    0
24641 #define M_TXMAPHDRCHANNEL0    0xfU
24642 #define V_TXMAPHDRCHANNEL0(x) ((x) << S_TXMAPHDRCHANNEL0)
24643 #define G_TXMAPHDRCHANNEL0(x) (((x) >> S_TXMAPHDRCHANNEL0) & M_TXMAPHDRCHANNEL0)
24644 
24645 #define A_TP_TX_SCHED_FIFO 0x24
24646 
24647 #define S_TXMAPFIFOCHANNEL7    28
24648 #define M_TXMAPFIFOCHANNEL7    0xfU
24649 #define V_TXMAPFIFOCHANNEL7(x) ((x) << S_TXMAPFIFOCHANNEL7)
24650 #define G_TXMAPFIFOCHANNEL7(x) (((x) >> S_TXMAPFIFOCHANNEL7) & M_TXMAPFIFOCHANNEL7)
24651 
24652 #define S_TXMAPFIFOCHANNEL6    24
24653 #define M_TXMAPFIFOCHANNEL6    0xfU
24654 #define V_TXMAPFIFOCHANNEL6(x) ((x) << S_TXMAPFIFOCHANNEL6)
24655 #define G_TXMAPFIFOCHANNEL6(x) (((x) >> S_TXMAPFIFOCHANNEL6) & M_TXMAPFIFOCHANNEL6)
24656 
24657 #define S_TXMAPFIFOCHANNEL5    20
24658 #define M_TXMAPFIFOCHANNEL5    0xfU
24659 #define V_TXMAPFIFOCHANNEL5(x) ((x) << S_TXMAPFIFOCHANNEL5)
24660 #define G_TXMAPFIFOCHANNEL5(x) (((x) >> S_TXMAPFIFOCHANNEL5) & M_TXMAPFIFOCHANNEL5)
24661 
24662 #define S_TXMAPFIFOCHANNEL4    16
24663 #define M_TXMAPFIFOCHANNEL4    0xfU
24664 #define V_TXMAPFIFOCHANNEL4(x) ((x) << S_TXMAPFIFOCHANNEL4)
24665 #define G_TXMAPFIFOCHANNEL4(x) (((x) >> S_TXMAPFIFOCHANNEL4) & M_TXMAPFIFOCHANNEL4)
24666 
24667 #define S_TXMAPFIFOCHANNEL3    12
24668 #define M_TXMAPFIFOCHANNEL3    0xfU
24669 #define V_TXMAPFIFOCHANNEL3(x) ((x) << S_TXMAPFIFOCHANNEL3)
24670 #define G_TXMAPFIFOCHANNEL3(x) (((x) >> S_TXMAPFIFOCHANNEL3) & M_TXMAPFIFOCHANNEL3)
24671 
24672 #define S_TXMAPFIFOCHANNEL2    8
24673 #define M_TXMAPFIFOCHANNEL2    0xfU
24674 #define V_TXMAPFIFOCHANNEL2(x) ((x) << S_TXMAPFIFOCHANNEL2)
24675 #define G_TXMAPFIFOCHANNEL2(x) (((x) >> S_TXMAPFIFOCHANNEL2) & M_TXMAPFIFOCHANNEL2)
24676 
24677 #define S_TXMAPFIFOCHANNEL1    4
24678 #define M_TXMAPFIFOCHANNEL1    0xfU
24679 #define V_TXMAPFIFOCHANNEL1(x) ((x) << S_TXMAPFIFOCHANNEL1)
24680 #define G_TXMAPFIFOCHANNEL1(x) (((x) >> S_TXMAPFIFOCHANNEL1) & M_TXMAPFIFOCHANNEL1)
24681 
24682 #define S_TXMAPFIFOCHANNEL0    0
24683 #define M_TXMAPFIFOCHANNEL0    0xfU
24684 #define V_TXMAPFIFOCHANNEL0(x) ((x) << S_TXMAPFIFOCHANNEL0)
24685 #define G_TXMAPFIFOCHANNEL0(x) (((x) >> S_TXMAPFIFOCHANNEL0) & M_TXMAPFIFOCHANNEL0)
24686 
24687 #define A_TP_TX_SCHED_PCMD 0x25
24688 
24689 #define S_TXMAPPCMDCHANNEL7    28
24690 #define M_TXMAPPCMDCHANNEL7    0xfU
24691 #define V_TXMAPPCMDCHANNEL7(x) ((x) << S_TXMAPPCMDCHANNEL7)
24692 #define G_TXMAPPCMDCHANNEL7(x) (((x) >> S_TXMAPPCMDCHANNEL7) & M_TXMAPPCMDCHANNEL7)
24693 
24694 #define S_TXMAPPCMDCHANNEL6    24
24695 #define M_TXMAPPCMDCHANNEL6    0xfU
24696 #define V_TXMAPPCMDCHANNEL6(x) ((x) << S_TXMAPPCMDCHANNEL6)
24697 #define G_TXMAPPCMDCHANNEL6(x) (((x) >> S_TXMAPPCMDCHANNEL6) & M_TXMAPPCMDCHANNEL6)
24698 
24699 #define S_TXMAPPCMDCHANNEL5    20
24700 #define M_TXMAPPCMDCHANNEL5    0xfU
24701 #define V_TXMAPPCMDCHANNEL5(x) ((x) << S_TXMAPPCMDCHANNEL5)
24702 #define G_TXMAPPCMDCHANNEL5(x) (((x) >> S_TXMAPPCMDCHANNEL5) & M_TXMAPPCMDCHANNEL5)
24703 
24704 #define S_TXMAPPCMDCHANNEL4    16
24705 #define M_TXMAPPCMDCHANNEL4    0xfU
24706 #define V_TXMAPPCMDCHANNEL4(x) ((x) << S_TXMAPPCMDCHANNEL4)
24707 #define G_TXMAPPCMDCHANNEL4(x) (((x) >> S_TXMAPPCMDCHANNEL4) & M_TXMAPPCMDCHANNEL4)
24708 
24709 #define S_TXMAPPCMDCHANNEL3    12
24710 #define M_TXMAPPCMDCHANNEL3    0xfU
24711 #define V_TXMAPPCMDCHANNEL3(x) ((x) << S_TXMAPPCMDCHANNEL3)
24712 #define G_TXMAPPCMDCHANNEL3(x) (((x) >> S_TXMAPPCMDCHANNEL3) & M_TXMAPPCMDCHANNEL3)
24713 
24714 #define S_TXMAPPCMDCHANNEL2    8
24715 #define M_TXMAPPCMDCHANNEL2    0xfU
24716 #define V_TXMAPPCMDCHANNEL2(x) ((x) << S_TXMAPPCMDCHANNEL2)
24717 #define G_TXMAPPCMDCHANNEL2(x) (((x) >> S_TXMAPPCMDCHANNEL2) & M_TXMAPPCMDCHANNEL2)
24718 
24719 #define S_TXMAPPCMDCHANNEL1    4
24720 #define M_TXMAPPCMDCHANNEL1    0xfU
24721 #define V_TXMAPPCMDCHANNEL1(x) ((x) << S_TXMAPPCMDCHANNEL1)
24722 #define G_TXMAPPCMDCHANNEL1(x) (((x) >> S_TXMAPPCMDCHANNEL1) & M_TXMAPPCMDCHANNEL1)
24723 
24724 #define S_TXMAPPCMDCHANNEL0    0
24725 #define M_TXMAPPCMDCHANNEL0    0xfU
24726 #define V_TXMAPPCMDCHANNEL0(x) ((x) << S_TXMAPPCMDCHANNEL0)
24727 #define G_TXMAPPCMDCHANNEL0(x) (((x) >> S_TXMAPPCMDCHANNEL0) & M_TXMAPPCMDCHANNEL0)
24728 
24729 #define A_TP_TX_SCHED_LPBK 0x26
24730 
24731 #define S_TXMAPLPBKCHANNEL7    28
24732 #define M_TXMAPLPBKCHANNEL7    0xfU
24733 #define V_TXMAPLPBKCHANNEL7(x) ((x) << S_TXMAPLPBKCHANNEL7)
24734 #define G_TXMAPLPBKCHANNEL7(x) (((x) >> S_TXMAPLPBKCHANNEL7) & M_TXMAPLPBKCHANNEL7)
24735 
24736 #define S_TXMAPLPBKCHANNEL6    24
24737 #define M_TXMAPLPBKCHANNEL6    0xfU
24738 #define V_TXMAPLPBKCHANNEL6(x) ((x) << S_TXMAPLPBKCHANNEL6)
24739 #define G_TXMAPLPBKCHANNEL6(x) (((x) >> S_TXMAPLPBKCHANNEL6) & M_TXMAPLPBKCHANNEL6)
24740 
24741 #define S_TXMAPLPBKCHANNEL5    20
24742 #define M_TXMAPLPBKCHANNEL5    0xfU
24743 #define V_TXMAPLPBKCHANNEL5(x) ((x) << S_TXMAPLPBKCHANNEL5)
24744 #define G_TXMAPLPBKCHANNEL5(x) (((x) >> S_TXMAPLPBKCHANNEL5) & M_TXMAPLPBKCHANNEL5)
24745 
24746 #define S_TXMAPLPBKCHANNEL4    16
24747 #define M_TXMAPLPBKCHANNEL4    0xfU
24748 #define V_TXMAPLPBKCHANNEL4(x) ((x) << S_TXMAPLPBKCHANNEL4)
24749 #define G_TXMAPLPBKCHANNEL4(x) (((x) >> S_TXMAPLPBKCHANNEL4) & M_TXMAPLPBKCHANNEL4)
24750 
24751 #define S_TXMAPLPBKCHANNEL3    12
24752 #define M_TXMAPLPBKCHANNEL3    0xfU
24753 #define V_TXMAPLPBKCHANNEL3(x) ((x) << S_TXMAPLPBKCHANNEL3)
24754 #define G_TXMAPLPBKCHANNEL3(x) (((x) >> S_TXMAPLPBKCHANNEL3) & M_TXMAPLPBKCHANNEL3)
24755 
24756 #define S_TXMAPLPBKCHANNEL2    8
24757 #define M_TXMAPLPBKCHANNEL2    0xfU
24758 #define V_TXMAPLPBKCHANNEL2(x) ((x) << S_TXMAPLPBKCHANNEL2)
24759 #define G_TXMAPLPBKCHANNEL2(x) (((x) >> S_TXMAPLPBKCHANNEL2) & M_TXMAPLPBKCHANNEL2)
24760 
24761 #define S_TXMAPLPBKCHANNEL1    4
24762 #define M_TXMAPLPBKCHANNEL1    0xfU
24763 #define V_TXMAPLPBKCHANNEL1(x) ((x) << S_TXMAPLPBKCHANNEL1)
24764 #define G_TXMAPLPBKCHANNEL1(x) (((x) >> S_TXMAPLPBKCHANNEL1) & M_TXMAPLPBKCHANNEL1)
24765 
24766 #define S_TXMAPLPBKCHANNEL0    0
24767 #define M_TXMAPLPBKCHANNEL0    0xfU
24768 #define V_TXMAPLPBKCHANNEL0(x) ((x) << S_TXMAPLPBKCHANNEL0)
24769 #define G_TXMAPLPBKCHANNEL0(x) (((x) >> S_TXMAPLPBKCHANNEL0) & M_TXMAPLPBKCHANNEL0)
24770 
24771 #define A_TP_CHANNEL_MAP 0x27
24772 
24773 #define S_RXMAPCHANNELELN    16
24774 #define M_RXMAPCHANNELELN    0xfU
24775 #define V_RXMAPCHANNELELN(x) ((x) << S_RXMAPCHANNELELN)
24776 #define G_RXMAPCHANNELELN(x) (((x) >> S_RXMAPCHANNELELN) & M_RXMAPCHANNELELN)
24777 
24778 #define S_RXMAPE2LCHANNEL3    14
24779 #define M_RXMAPE2LCHANNEL3    0x3U
24780 #define V_RXMAPE2LCHANNEL3(x) ((x) << S_RXMAPE2LCHANNEL3)
24781 #define G_RXMAPE2LCHANNEL3(x) (((x) >> S_RXMAPE2LCHANNEL3) & M_RXMAPE2LCHANNEL3)
24782 
24783 #define S_RXMAPE2LCHANNEL2    12
24784 #define M_RXMAPE2LCHANNEL2    0x3U
24785 #define V_RXMAPE2LCHANNEL2(x) ((x) << S_RXMAPE2LCHANNEL2)
24786 #define G_RXMAPE2LCHANNEL2(x) (((x) >> S_RXMAPE2LCHANNEL2) & M_RXMAPE2LCHANNEL2)
24787 
24788 #define S_RXMAPE2LCHANNEL1    10
24789 #define M_RXMAPE2LCHANNEL1    0x3U
24790 #define V_RXMAPE2LCHANNEL1(x) ((x) << S_RXMAPE2LCHANNEL1)
24791 #define G_RXMAPE2LCHANNEL1(x) (((x) >> S_RXMAPE2LCHANNEL1) & M_RXMAPE2LCHANNEL1)
24792 
24793 #define S_RXMAPE2LCHANNEL0    8
24794 #define M_RXMAPE2LCHANNEL0    0x3U
24795 #define V_RXMAPE2LCHANNEL0(x) ((x) << S_RXMAPE2LCHANNEL0)
24796 #define G_RXMAPE2LCHANNEL0(x) (((x) >> S_RXMAPE2LCHANNEL0) & M_RXMAPE2LCHANNEL0)
24797 
24798 #define S_RXMAPC2CCHANNEL3    7
24799 #define V_RXMAPC2CCHANNEL3(x) ((x) << S_RXMAPC2CCHANNEL3)
24800 #define F_RXMAPC2CCHANNEL3    V_RXMAPC2CCHANNEL3(1U)
24801 
24802 #define S_RXMAPC2CCHANNEL2    6
24803 #define V_RXMAPC2CCHANNEL2(x) ((x) << S_RXMAPC2CCHANNEL2)
24804 #define F_RXMAPC2CCHANNEL2    V_RXMAPC2CCHANNEL2(1U)
24805 
24806 #define S_RXMAPC2CCHANNEL1    5
24807 #define V_RXMAPC2CCHANNEL1(x) ((x) << S_RXMAPC2CCHANNEL1)
24808 #define F_RXMAPC2CCHANNEL1    V_RXMAPC2CCHANNEL1(1U)
24809 
24810 #define S_RXMAPC2CCHANNEL0    4
24811 #define V_RXMAPC2CCHANNEL0(x) ((x) << S_RXMAPC2CCHANNEL0)
24812 #define F_RXMAPC2CCHANNEL0    V_RXMAPC2CCHANNEL0(1U)
24813 
24814 #define S_RXMAPE2CCHANNEL3    3
24815 #define V_RXMAPE2CCHANNEL3(x) ((x) << S_RXMAPE2CCHANNEL3)
24816 #define F_RXMAPE2CCHANNEL3    V_RXMAPE2CCHANNEL3(1U)
24817 
24818 #define S_RXMAPE2CCHANNEL2    2
24819 #define V_RXMAPE2CCHANNEL2(x) ((x) << S_RXMAPE2CCHANNEL2)
24820 #define F_RXMAPE2CCHANNEL2    V_RXMAPE2CCHANNEL2(1U)
24821 
24822 #define S_RXMAPE2CCHANNEL1    1
24823 #define V_RXMAPE2CCHANNEL1(x) ((x) << S_RXMAPE2CCHANNEL1)
24824 #define F_RXMAPE2CCHANNEL1    V_RXMAPE2CCHANNEL1(1U)
24825 
24826 #define S_RXMAPE2CCHANNEL0    0
24827 #define V_RXMAPE2CCHANNEL0(x) ((x) << S_RXMAPE2CCHANNEL0)
24828 #define F_RXMAPE2CCHANNEL0    V_RXMAPE2CCHANNEL0(1U)
24829 
24830 #define A_TP_RX_LPBK 0x28
24831 #define A_TP_TX_LPBK 0x29
24832 #define A_TP_TX_SCHED_PPP 0x2a
24833 
24834 #define S_TXPPPENPORT3    24
24835 #define M_TXPPPENPORT3    0xffU
24836 #define V_TXPPPENPORT3(x) ((x) << S_TXPPPENPORT3)
24837 #define G_TXPPPENPORT3(x) (((x) >> S_TXPPPENPORT3) & M_TXPPPENPORT3)
24838 
24839 #define S_TXPPPENPORT2    16
24840 #define M_TXPPPENPORT2    0xffU
24841 #define V_TXPPPENPORT2(x) ((x) << S_TXPPPENPORT2)
24842 #define G_TXPPPENPORT2(x) (((x) >> S_TXPPPENPORT2) & M_TXPPPENPORT2)
24843 
24844 #define S_TXPPPENPORT1    8
24845 #define M_TXPPPENPORT1    0xffU
24846 #define V_TXPPPENPORT1(x) ((x) << S_TXPPPENPORT1)
24847 #define G_TXPPPENPORT1(x) (((x) >> S_TXPPPENPORT1) & M_TXPPPENPORT1)
24848 
24849 #define S_TXPPPENPORT0    0
24850 #define M_TXPPPENPORT0    0xffU
24851 #define V_TXPPPENPORT0(x) ((x) << S_TXPPPENPORT0)
24852 #define G_TXPPPENPORT0(x) (((x) >> S_TXPPPENPORT0) & M_TXPPPENPORT0)
24853 
24854 #define A_TP_RX_SCHED_FIFO 0x2b
24855 
24856 #define S_COMMITLIMIT1H    24
24857 #define M_COMMITLIMIT1H    0xffU
24858 #define V_COMMITLIMIT1H(x) ((x) << S_COMMITLIMIT1H)
24859 #define G_COMMITLIMIT1H(x) (((x) >> S_COMMITLIMIT1H) & M_COMMITLIMIT1H)
24860 
24861 #define S_COMMITLIMIT1L    16
24862 #define M_COMMITLIMIT1L    0xffU
24863 #define V_COMMITLIMIT1L(x) ((x) << S_COMMITLIMIT1L)
24864 #define G_COMMITLIMIT1L(x) (((x) >> S_COMMITLIMIT1L) & M_COMMITLIMIT1L)
24865 
24866 #define S_COMMITLIMIT0H    8
24867 #define M_COMMITLIMIT0H    0xffU
24868 #define V_COMMITLIMIT0H(x) ((x) << S_COMMITLIMIT0H)
24869 #define G_COMMITLIMIT0H(x) (((x) >> S_COMMITLIMIT0H) & M_COMMITLIMIT0H)
24870 
24871 #define S_COMMITLIMIT0L    0
24872 #define M_COMMITLIMIT0L    0xffU
24873 #define V_COMMITLIMIT0L(x) ((x) << S_COMMITLIMIT0L)
24874 #define G_COMMITLIMIT0L(x) (((x) >> S_COMMITLIMIT0L) & M_COMMITLIMIT0L)
24875 
24876 #define A_TP_IPMI_CFG1 0x2e
24877 
24878 #define S_VLANENABLE    31
24879 #define V_VLANENABLE(x) ((x) << S_VLANENABLE)
24880 #define F_VLANENABLE    V_VLANENABLE(1U)
24881 
24882 #define S_PRIMARYPORTENABLE    30
24883 #define V_PRIMARYPORTENABLE(x) ((x) << S_PRIMARYPORTENABLE)
24884 #define F_PRIMARYPORTENABLE    V_PRIMARYPORTENABLE(1U)
24885 
24886 #define S_SECUREPORTENABLE    29
24887 #define V_SECUREPORTENABLE(x) ((x) << S_SECUREPORTENABLE)
24888 #define F_SECUREPORTENABLE    V_SECUREPORTENABLE(1U)
24889 
24890 #define S_ARPENABLE    28
24891 #define V_ARPENABLE(x) ((x) << S_ARPENABLE)
24892 #define F_ARPENABLE    V_ARPENABLE(1U)
24893 
24894 #define S_IPMI_VLAN    0
24895 #define M_IPMI_VLAN    0xffffU
24896 #define V_IPMI_VLAN(x) ((x) << S_IPMI_VLAN)
24897 #define G_IPMI_VLAN(x) (((x) >> S_IPMI_VLAN) & M_IPMI_VLAN)
24898 
24899 #define A_TP_IPMI_CFG2 0x2f
24900 
24901 #define S_SECUREPORT    16
24902 #define M_SECUREPORT    0xffffU
24903 #define V_SECUREPORT(x) ((x) << S_SECUREPORT)
24904 #define G_SECUREPORT(x) (((x) >> S_SECUREPORT) & M_SECUREPORT)
24905 
24906 #define S_PRIMARYPORT    0
24907 #define M_PRIMARYPORT    0xffffU
24908 #define V_PRIMARYPORT(x) ((x) << S_PRIMARYPORT)
24909 #define G_PRIMARYPORT(x) (((x) >> S_PRIMARYPORT) & M_PRIMARYPORT)
24910 
24911 #define A_TP_RSS_PF0_CONFIG 0x30
24912 
24913 #define S_MAPENABLE    31
24914 #define V_MAPENABLE(x) ((x) << S_MAPENABLE)
24915 #define F_MAPENABLE    V_MAPENABLE(1U)
24916 
24917 #define S_CHNENABLE    30
24918 #define V_CHNENABLE(x) ((x) << S_CHNENABLE)
24919 #define F_CHNENABLE    V_CHNENABLE(1U)
24920 
24921 #define S_PRTENABLE    29
24922 #define V_PRTENABLE(x) ((x) << S_PRTENABLE)
24923 #define F_PRTENABLE    V_PRTENABLE(1U)
24924 
24925 #define S_UDPFOURTUPEN    28
24926 #define V_UDPFOURTUPEN(x) ((x) << S_UDPFOURTUPEN)
24927 #define F_UDPFOURTUPEN    V_UDPFOURTUPEN(1U)
24928 
24929 #define S_IP6FOURTUPEN    27
24930 #define V_IP6FOURTUPEN(x) ((x) << S_IP6FOURTUPEN)
24931 #define F_IP6FOURTUPEN    V_IP6FOURTUPEN(1U)
24932 
24933 #define S_IP6TWOTUPEN    26
24934 #define V_IP6TWOTUPEN(x) ((x) << S_IP6TWOTUPEN)
24935 #define F_IP6TWOTUPEN    V_IP6TWOTUPEN(1U)
24936 
24937 #define S_IP4FOURTUPEN    25
24938 #define V_IP4FOURTUPEN(x) ((x) << S_IP4FOURTUPEN)
24939 #define F_IP4FOURTUPEN    V_IP4FOURTUPEN(1U)
24940 
24941 #define S_IP4TWOTUPEN    24
24942 #define V_IP4TWOTUPEN(x) ((x) << S_IP4TWOTUPEN)
24943 #define F_IP4TWOTUPEN    V_IP4TWOTUPEN(1U)
24944 
24945 #define S_IVFWIDTH    20
24946 #define M_IVFWIDTH    0xfU
24947 #define V_IVFWIDTH(x) ((x) << S_IVFWIDTH)
24948 #define G_IVFWIDTH(x) (((x) >> S_IVFWIDTH) & M_IVFWIDTH)
24949 
24950 #define S_CH1DEFAULTQUEUE    10
24951 #define M_CH1DEFAULTQUEUE    0x3ffU
24952 #define V_CH1DEFAULTQUEUE(x) ((x) << S_CH1DEFAULTQUEUE)
24953 #define G_CH1DEFAULTQUEUE(x) (((x) >> S_CH1DEFAULTQUEUE) & M_CH1DEFAULTQUEUE)
24954 
24955 #define S_CH0DEFAULTQUEUE    0
24956 #define M_CH0DEFAULTQUEUE    0x3ffU
24957 #define V_CH0DEFAULTQUEUE(x) ((x) << S_CH0DEFAULTQUEUE)
24958 #define G_CH0DEFAULTQUEUE(x) (((x) >> S_CH0DEFAULTQUEUE) & M_CH0DEFAULTQUEUE)
24959 
24960 #define S_PRIENABLE    30
24961 #define V_PRIENABLE(x) ((x) << S_PRIENABLE)
24962 #define F_PRIENABLE    V_PRIENABLE(1U)
24963 
24964 #define S_T6_CHNENABLE    29
24965 #define V_T6_CHNENABLE(x) ((x) << S_T6_CHNENABLE)
24966 #define F_T6_CHNENABLE    V_T6_CHNENABLE(1U)
24967 
24968 #define A_TP_RSS_PF1_CONFIG 0x31
24969 
24970 #define S_T6_CHNENABLE    29
24971 #define V_T6_CHNENABLE(x) ((x) << S_T6_CHNENABLE)
24972 #define F_T6_CHNENABLE    V_T6_CHNENABLE(1U)
24973 
24974 #define A_TP_RSS_PF2_CONFIG 0x32
24975 
24976 #define S_T6_CHNENABLE    29
24977 #define V_T6_CHNENABLE(x) ((x) << S_T6_CHNENABLE)
24978 #define F_T6_CHNENABLE    V_T6_CHNENABLE(1U)
24979 
24980 #define A_TP_RSS_PF3_CONFIG 0x33
24981 
24982 #define S_T6_CHNENABLE    29
24983 #define V_T6_CHNENABLE(x) ((x) << S_T6_CHNENABLE)
24984 #define F_T6_CHNENABLE    V_T6_CHNENABLE(1U)
24985 
24986 #define A_TP_RSS_PF4_CONFIG 0x34
24987 
24988 #define S_T6_CHNENABLE    29
24989 #define V_T6_CHNENABLE(x) ((x) << S_T6_CHNENABLE)
24990 #define F_T6_CHNENABLE    V_T6_CHNENABLE(1U)
24991 
24992 #define A_TP_RSS_PF5_CONFIG 0x35
24993 
24994 #define S_T6_CHNENABLE    29
24995 #define V_T6_CHNENABLE(x) ((x) << S_T6_CHNENABLE)
24996 #define F_T6_CHNENABLE    V_T6_CHNENABLE(1U)
24997 
24998 #define A_TP_RSS_PF6_CONFIG 0x36
24999 
25000 #define S_T6_CHNENABLE    29
25001 #define V_T6_CHNENABLE(x) ((x) << S_T6_CHNENABLE)
25002 #define F_T6_CHNENABLE    V_T6_CHNENABLE(1U)
25003 
25004 #define A_TP_RSS_PF7_CONFIG 0x37
25005 
25006 #define S_T6_CHNENABLE    29
25007 #define V_T6_CHNENABLE(x) ((x) << S_T6_CHNENABLE)
25008 #define F_T6_CHNENABLE    V_T6_CHNENABLE(1U)
25009 
25010 #define A_TP_RSS_PF_MAP 0x38
25011 
25012 #define S_LKPIDXSIZE    24
25013 #define M_LKPIDXSIZE    0x3U
25014 #define V_LKPIDXSIZE(x) ((x) << S_LKPIDXSIZE)
25015 #define G_LKPIDXSIZE(x) (((x) >> S_LKPIDXSIZE) & M_LKPIDXSIZE)
25016 
25017 #define S_PF7LKPIDX    21
25018 #define M_PF7LKPIDX    0x7U
25019 #define V_PF7LKPIDX(x) ((x) << S_PF7LKPIDX)
25020 #define G_PF7LKPIDX(x) (((x) >> S_PF7LKPIDX) & M_PF7LKPIDX)
25021 
25022 #define S_PF6LKPIDX    18
25023 #define M_PF6LKPIDX    0x7U
25024 #define V_PF6LKPIDX(x) ((x) << S_PF6LKPIDX)
25025 #define G_PF6LKPIDX(x) (((x) >> S_PF6LKPIDX) & M_PF6LKPIDX)
25026 
25027 #define S_PF5LKPIDX    15
25028 #define M_PF5LKPIDX    0x7U
25029 #define V_PF5LKPIDX(x) ((x) << S_PF5LKPIDX)
25030 #define G_PF5LKPIDX(x) (((x) >> S_PF5LKPIDX) & M_PF5LKPIDX)
25031 
25032 #define S_PF4LKPIDX    12
25033 #define M_PF4LKPIDX    0x7U
25034 #define V_PF4LKPIDX(x) ((x) << S_PF4LKPIDX)
25035 #define G_PF4LKPIDX(x) (((x) >> S_PF4LKPIDX) & M_PF4LKPIDX)
25036 
25037 #define S_PF3LKPIDX    9
25038 #define M_PF3LKPIDX    0x7U
25039 #define V_PF3LKPIDX(x) ((x) << S_PF3LKPIDX)
25040 #define G_PF3LKPIDX(x) (((x) >> S_PF3LKPIDX) & M_PF3LKPIDX)
25041 
25042 #define S_PF2LKPIDX    6
25043 #define M_PF2LKPIDX    0x7U
25044 #define V_PF2LKPIDX(x) ((x) << S_PF2LKPIDX)
25045 #define G_PF2LKPIDX(x) (((x) >> S_PF2LKPIDX) & M_PF2LKPIDX)
25046 
25047 #define S_PF1LKPIDX    3
25048 #define M_PF1LKPIDX    0x7U
25049 #define V_PF1LKPIDX(x) ((x) << S_PF1LKPIDX)
25050 #define G_PF1LKPIDX(x) (((x) >> S_PF1LKPIDX) & M_PF1LKPIDX)
25051 
25052 #define S_PF0LKPIDX    0
25053 #define M_PF0LKPIDX    0x7U
25054 #define V_PF0LKPIDX(x) ((x) << S_PF0LKPIDX)
25055 #define G_PF0LKPIDX(x) (((x) >> S_PF0LKPIDX) & M_PF0LKPIDX)
25056 
25057 #define A_TP_RSS_PF_MSK 0x39
25058 
25059 #define S_PF7MSKSIZE    28
25060 #define M_PF7MSKSIZE    0xfU
25061 #define V_PF7MSKSIZE(x) ((x) << S_PF7MSKSIZE)
25062 #define G_PF7MSKSIZE(x) (((x) >> S_PF7MSKSIZE) & M_PF7MSKSIZE)
25063 
25064 #define S_PF6MSKSIZE    24
25065 #define M_PF6MSKSIZE    0xfU
25066 #define V_PF6MSKSIZE(x) ((x) << S_PF6MSKSIZE)
25067 #define G_PF6MSKSIZE(x) (((x) >> S_PF6MSKSIZE) & M_PF6MSKSIZE)
25068 
25069 #define S_PF5MSKSIZE    20
25070 #define M_PF5MSKSIZE    0xfU
25071 #define V_PF5MSKSIZE(x) ((x) << S_PF5MSKSIZE)
25072 #define G_PF5MSKSIZE(x) (((x) >> S_PF5MSKSIZE) & M_PF5MSKSIZE)
25073 
25074 #define S_PF4MSKSIZE    16
25075 #define M_PF4MSKSIZE    0xfU
25076 #define V_PF4MSKSIZE(x) ((x) << S_PF4MSKSIZE)
25077 #define G_PF4MSKSIZE(x) (((x) >> S_PF4MSKSIZE) & M_PF4MSKSIZE)
25078 
25079 #define S_PF3MSKSIZE    12
25080 #define M_PF3MSKSIZE    0xfU
25081 #define V_PF3MSKSIZE(x) ((x) << S_PF3MSKSIZE)
25082 #define G_PF3MSKSIZE(x) (((x) >> S_PF3MSKSIZE) & M_PF3MSKSIZE)
25083 
25084 #define S_PF2MSKSIZE    8
25085 #define M_PF2MSKSIZE    0xfU
25086 #define V_PF2MSKSIZE(x) ((x) << S_PF2MSKSIZE)
25087 #define G_PF2MSKSIZE(x) (((x) >> S_PF2MSKSIZE) & M_PF2MSKSIZE)
25088 
25089 #define S_PF1MSKSIZE    4
25090 #define M_PF1MSKSIZE    0xfU
25091 #define V_PF1MSKSIZE(x) ((x) << S_PF1MSKSIZE)
25092 #define G_PF1MSKSIZE(x) (((x) >> S_PF1MSKSIZE) & M_PF1MSKSIZE)
25093 
25094 #define S_PF0MSKSIZE    0
25095 #define M_PF0MSKSIZE    0xfU
25096 #define V_PF0MSKSIZE(x) ((x) << S_PF0MSKSIZE)
25097 #define G_PF0MSKSIZE(x) (((x) >> S_PF0MSKSIZE) & M_PF0MSKSIZE)
25098 
25099 #define A_TP_RSS_VFL_CONFIG 0x3a
25100 #define A_TP_RSS_VFH_CONFIG 0x3b
25101 
25102 #define S_ENABLEUDPHASH    31
25103 #define V_ENABLEUDPHASH(x) ((x) << S_ENABLEUDPHASH)
25104 #define F_ENABLEUDPHASH    V_ENABLEUDPHASH(1U)
25105 
25106 #define S_VFUPEN    30
25107 #define V_VFUPEN(x) ((x) << S_VFUPEN)
25108 #define F_VFUPEN    V_VFUPEN(1U)
25109 
25110 #define S_VFVLNEX    28
25111 #define V_VFVLNEX(x) ((x) << S_VFVLNEX)
25112 #define F_VFVLNEX    V_VFVLNEX(1U)
25113 
25114 #define S_VFPRTEN    27
25115 #define V_VFPRTEN(x) ((x) << S_VFPRTEN)
25116 #define F_VFPRTEN    V_VFPRTEN(1U)
25117 
25118 #define S_VFCHNEN    26
25119 #define V_VFCHNEN(x) ((x) << S_VFCHNEN)
25120 #define F_VFCHNEN    V_VFCHNEN(1U)
25121 
25122 #define S_DEFAULTQUEUE    16
25123 #define M_DEFAULTQUEUE    0x3ffU
25124 #define V_DEFAULTQUEUE(x) ((x) << S_DEFAULTQUEUE)
25125 #define G_DEFAULTQUEUE(x) (((x) >> S_DEFAULTQUEUE) & M_DEFAULTQUEUE)
25126 
25127 #define S_VFLKPIDX    8
25128 #define M_VFLKPIDX    0xffU
25129 #define V_VFLKPIDX(x) ((x) << S_VFLKPIDX)
25130 #define G_VFLKPIDX(x) (((x) >> S_VFLKPIDX) & M_VFLKPIDX)
25131 
25132 #define S_VFIP6FOURTUPEN    7
25133 #define V_VFIP6FOURTUPEN(x) ((x) << S_VFIP6FOURTUPEN)
25134 #define F_VFIP6FOURTUPEN    V_VFIP6FOURTUPEN(1U)
25135 
25136 #define S_VFIP6TWOTUPEN    6
25137 #define V_VFIP6TWOTUPEN(x) ((x) << S_VFIP6TWOTUPEN)
25138 #define F_VFIP6TWOTUPEN    V_VFIP6TWOTUPEN(1U)
25139 
25140 #define S_VFIP4FOURTUPEN    5
25141 #define V_VFIP4FOURTUPEN(x) ((x) << S_VFIP4FOURTUPEN)
25142 #define F_VFIP4FOURTUPEN    V_VFIP4FOURTUPEN(1U)
25143 
25144 #define S_VFIP4TWOTUPEN    4
25145 #define V_VFIP4TWOTUPEN(x) ((x) << S_VFIP4TWOTUPEN)
25146 #define F_VFIP4TWOTUPEN    V_VFIP4TWOTUPEN(1U)
25147 
25148 #define S_KEYINDEX    0
25149 #define M_KEYINDEX    0xfU
25150 #define V_KEYINDEX(x) ((x) << S_KEYINDEX)
25151 #define G_KEYINDEX(x) (((x) >> S_KEYINDEX) & M_KEYINDEX)
25152 
25153 #define A_TP_RSS_SECRET_KEY0 0x40
25154 #define A_TP_RSS_SECRET_KEY1 0x41
25155 #define A_TP_RSS_SECRET_KEY2 0x42
25156 #define A_TP_RSS_SECRET_KEY3 0x43
25157 #define A_TP_RSS_SECRET_KEY4 0x44
25158 #define A_TP_RSS_SECRET_KEY5 0x45
25159 #define A_TP_RSS_SECRET_KEY6 0x46
25160 #define A_TP_RSS_SECRET_KEY7 0x47
25161 #define A_TP_RSS_SECRET_KEY8 0x48
25162 #define A_TP_RSS_SECRET_KEY9 0x49
25163 #define A_TP_ETHER_TYPE_VL 0x50
25164 
25165 #define S_CQFCTYPE    16
25166 #define M_CQFCTYPE    0xffffU
25167 #define V_CQFCTYPE(x) ((x) << S_CQFCTYPE)
25168 #define G_CQFCTYPE(x) (((x) >> S_CQFCTYPE) & M_CQFCTYPE)
25169 
25170 #define S_VLANTYPE    0
25171 #define M_VLANTYPE    0xffffU
25172 #define V_VLANTYPE(x) ((x) << S_VLANTYPE)
25173 #define G_VLANTYPE(x) (((x) >> S_VLANTYPE) & M_VLANTYPE)
25174 
25175 #define A_TP_ETHER_TYPE_IP 0x51
25176 
25177 #define S_IPV6TYPE    16
25178 #define M_IPV6TYPE    0xffffU
25179 #define V_IPV6TYPE(x) ((x) << S_IPV6TYPE)
25180 #define G_IPV6TYPE(x) (((x) >> S_IPV6TYPE) & M_IPV6TYPE)
25181 
25182 #define S_IPV4TYPE    0
25183 #define M_IPV4TYPE    0xffffU
25184 #define V_IPV4TYPE(x) ((x) << S_IPV4TYPE)
25185 #define G_IPV4TYPE(x) (((x) >> S_IPV4TYPE) & M_IPV4TYPE)
25186 
25187 #define A_TP_ETHER_TYPE_FW 0x52
25188 
25189 #define S_ETHTYPE1    16
25190 #define M_ETHTYPE1    0xffffU
25191 #define V_ETHTYPE1(x) ((x) << S_ETHTYPE1)
25192 #define G_ETHTYPE1(x) (((x) >> S_ETHTYPE1) & M_ETHTYPE1)
25193 
25194 #define S_ETHTYPE0    0
25195 #define M_ETHTYPE0    0xffffU
25196 #define V_ETHTYPE0(x) ((x) << S_ETHTYPE0)
25197 #define G_ETHTYPE0(x) (((x) >> S_ETHTYPE0) & M_ETHTYPE0)
25198 
25199 #define A_TP_VXLAN_HEADER 0x53
25200 
25201 #define S_VXLANPORT    0
25202 #define M_VXLANPORT    0xffffU
25203 #define V_VXLANPORT(x) ((x) << S_VXLANPORT)
25204 #define G_VXLANPORT(x) (((x) >> S_VXLANPORT) & M_VXLANPORT)
25205 
25206 #define A_TP_CORE_POWER 0x54
25207 
25208 #define S_SLEEPRDYVNT    12
25209 #define V_SLEEPRDYVNT(x) ((x) << S_SLEEPRDYVNT)
25210 #define F_SLEEPRDYVNT    V_SLEEPRDYVNT(1U)
25211 
25212 #define S_SLEEPRDYTBL    11
25213 #define V_SLEEPRDYTBL(x) ((x) << S_SLEEPRDYTBL)
25214 #define F_SLEEPRDYTBL    V_SLEEPRDYTBL(1U)
25215 
25216 #define S_SLEEPRDYMIB    10
25217 #define V_SLEEPRDYMIB(x) ((x) << S_SLEEPRDYMIB)
25218 #define F_SLEEPRDYMIB    V_SLEEPRDYMIB(1U)
25219 
25220 #define S_SLEEPRDYARP    9
25221 #define V_SLEEPRDYARP(x) ((x) << S_SLEEPRDYARP)
25222 #define F_SLEEPRDYARP    V_SLEEPRDYARP(1U)
25223 
25224 #define S_SLEEPRDYRSS    8
25225 #define V_SLEEPRDYRSS(x) ((x) << S_SLEEPRDYRSS)
25226 #define F_SLEEPRDYRSS    V_SLEEPRDYRSS(1U)
25227 
25228 #define S_SLEEPREQVNT    4
25229 #define V_SLEEPREQVNT(x) ((x) << S_SLEEPREQVNT)
25230 #define F_SLEEPREQVNT    V_SLEEPREQVNT(1U)
25231 
25232 #define S_SLEEPREQTBL    3
25233 #define V_SLEEPREQTBL(x) ((x) << S_SLEEPREQTBL)
25234 #define F_SLEEPREQTBL    V_SLEEPREQTBL(1U)
25235 
25236 #define S_SLEEPREQMIB    2
25237 #define V_SLEEPREQMIB(x) ((x) << S_SLEEPREQMIB)
25238 #define F_SLEEPREQMIB    V_SLEEPREQMIB(1U)
25239 
25240 #define S_SLEEPREQARP    1
25241 #define V_SLEEPREQARP(x) ((x) << S_SLEEPREQARP)
25242 #define F_SLEEPREQARP    V_SLEEPREQARP(1U)
25243 
25244 #define S_SLEEPREQRSS    0
25245 #define V_SLEEPREQRSS(x) ((x) << S_SLEEPREQRSS)
25246 #define F_SLEEPREQRSS    V_SLEEPREQRSS(1U)
25247 
25248 #define A_TP_CORE_RDMA 0x55
25249 
25250 #define S_IMMEDIATEOP    20
25251 #define M_IMMEDIATEOP    0xfU
25252 #define V_IMMEDIATEOP(x) ((x) << S_IMMEDIATEOP)
25253 #define G_IMMEDIATEOP(x) (((x) >> S_IMMEDIATEOP) & M_IMMEDIATEOP)
25254 
25255 #define S_IMMEDIATESE    16
25256 #define M_IMMEDIATESE    0xfU
25257 #define V_IMMEDIATESE(x) ((x) << S_IMMEDIATESE)
25258 #define G_IMMEDIATESE(x) (((x) >> S_IMMEDIATESE) & M_IMMEDIATESE)
25259 
25260 #define S_ATOMICREQOP    12
25261 #define M_ATOMICREQOP    0xfU
25262 #define V_ATOMICREQOP(x) ((x) << S_ATOMICREQOP)
25263 #define G_ATOMICREQOP(x) (((x) >> S_ATOMICREQOP) & M_ATOMICREQOP)
25264 
25265 #define S_ATOMICRSPOP    8
25266 #define M_ATOMICRSPOP    0xfU
25267 #define V_ATOMICRSPOP(x) ((x) << S_ATOMICRSPOP)
25268 #define G_ATOMICRSPOP(x) (((x) >> S_ATOMICRSPOP) & M_ATOMICRSPOP)
25269 
25270 #define S_IMMEDIASEEN    1
25271 #define V_IMMEDIASEEN(x) ((x) << S_IMMEDIASEEN)
25272 #define F_IMMEDIASEEN    V_IMMEDIASEEN(1U)
25273 
25274 #define S_IMMEDIATEEN    0
25275 #define V_IMMEDIATEEN(x) ((x) << S_IMMEDIATEEN)
25276 #define F_IMMEDIATEEN    V_IMMEDIATEEN(1U)
25277 
25278 #define S_SHAREDRQEN    31
25279 #define V_SHAREDRQEN(x) ((x) << S_SHAREDRQEN)
25280 #define F_SHAREDRQEN    V_SHAREDRQEN(1U)
25281 
25282 #define S_SHAREDXRC    30
25283 #define V_SHAREDXRC(x) ((x) << S_SHAREDXRC)
25284 #define F_SHAREDXRC    V_SHAREDXRC(1U)
25285 
25286 #define A_TP_FRAG_CONFIG 0x56
25287 
25288 #define S_TLSMODE    16
25289 #define M_TLSMODE    0x3U
25290 #define V_TLSMODE(x) ((x) << S_TLSMODE)
25291 #define G_TLSMODE(x) (((x) >> S_TLSMODE) & M_TLSMODE)
25292 
25293 #define S_USERMODE    14
25294 #define M_USERMODE    0x3U
25295 #define V_USERMODE(x) ((x) << S_USERMODE)
25296 #define G_USERMODE(x) (((x) >> S_USERMODE) & M_USERMODE)
25297 
25298 #define S_FCOEMODE    12
25299 #define M_FCOEMODE    0x3U
25300 #define V_FCOEMODE(x) ((x) << S_FCOEMODE)
25301 #define G_FCOEMODE(x) (((x) >> S_FCOEMODE) & M_FCOEMODE)
25302 
25303 #define S_IANDPMODE    10
25304 #define M_IANDPMODE    0x3U
25305 #define V_IANDPMODE(x) ((x) << S_IANDPMODE)
25306 #define G_IANDPMODE(x) (((x) >> S_IANDPMODE) & M_IANDPMODE)
25307 
25308 #define S_RDDPMODE    8
25309 #define M_RDDPMODE    0x3U
25310 #define V_RDDPMODE(x) ((x) << S_RDDPMODE)
25311 #define G_RDDPMODE(x) (((x) >> S_RDDPMODE) & M_RDDPMODE)
25312 
25313 #define S_IWARPMODE    6
25314 #define M_IWARPMODE    0x3U
25315 #define V_IWARPMODE(x) ((x) << S_IWARPMODE)
25316 #define G_IWARPMODE(x) (((x) >> S_IWARPMODE) & M_IWARPMODE)
25317 
25318 #define S_ISCSIMODE    4
25319 #define M_ISCSIMODE    0x3U
25320 #define V_ISCSIMODE(x) ((x) << S_ISCSIMODE)
25321 #define G_ISCSIMODE(x) (((x) >> S_ISCSIMODE) & M_ISCSIMODE)
25322 
25323 #define S_DDPMODE    2
25324 #define M_DDPMODE    0x3U
25325 #define V_DDPMODE(x) ((x) << S_DDPMODE)
25326 #define G_DDPMODE(x) (((x) >> S_DDPMODE) & M_DDPMODE)
25327 
25328 #define S_PASSMODE    0
25329 #define M_PASSMODE    0x3U
25330 #define V_PASSMODE(x) ((x) << S_PASSMODE)
25331 #define G_PASSMODE(x) (((x) >> S_PASSMODE) & M_PASSMODE)
25332 
25333 #define A_TP_CMM_CONFIG 0x57
25334 
25335 #define S_WRCNTIDLE    16
25336 #define M_WRCNTIDLE    0xffffU
25337 #define V_WRCNTIDLE(x) ((x) << S_WRCNTIDLE)
25338 #define G_WRCNTIDLE(x) (((x) >> S_WRCNTIDLE) & M_WRCNTIDLE)
25339 
25340 #define S_RDTHRESHOLD    8
25341 #define M_RDTHRESHOLD    0x3fU
25342 #define V_RDTHRESHOLD(x) ((x) << S_RDTHRESHOLD)
25343 #define G_RDTHRESHOLD(x) (((x) >> S_RDTHRESHOLD) & M_RDTHRESHOLD)
25344 
25345 #define S_WRTHRLEVEL2    7
25346 #define V_WRTHRLEVEL2(x) ((x) << S_WRTHRLEVEL2)
25347 #define F_WRTHRLEVEL2    V_WRTHRLEVEL2(1U)
25348 
25349 #define S_WRTHRLEVEL1    6
25350 #define V_WRTHRLEVEL1(x) ((x) << S_WRTHRLEVEL1)
25351 #define F_WRTHRLEVEL1    V_WRTHRLEVEL1(1U)
25352 
25353 #define S_WRTHRTHRESHEN    5
25354 #define V_WRTHRTHRESHEN(x) ((x) << S_WRTHRTHRESHEN)
25355 #define F_WRTHRTHRESHEN    V_WRTHRTHRESHEN(1U)
25356 
25357 #define S_WRTHRTHRESH    0
25358 #define M_WRTHRTHRESH    0x1fU
25359 #define V_WRTHRTHRESH(x) ((x) << S_WRTHRTHRESH)
25360 #define G_WRTHRTHRESH(x) (((x) >> S_WRTHRTHRESH) & M_WRTHRTHRESH)
25361 
25362 #define A_TP_VXLAN_CONFIG 0x58
25363 
25364 #define S_VXLANFLAGS    16
25365 #define M_VXLANFLAGS    0xffffU
25366 #define V_VXLANFLAGS(x) ((x) << S_VXLANFLAGS)
25367 #define G_VXLANFLAGS(x) (((x) >> S_VXLANFLAGS) & M_VXLANFLAGS)
25368 
25369 #define S_VXLANTYPE    0
25370 #define M_VXLANTYPE    0xffffU
25371 #define V_VXLANTYPE(x) ((x) << S_VXLANTYPE)
25372 #define G_VXLANTYPE(x) (((x) >> S_VXLANTYPE) & M_VXLANTYPE)
25373 
25374 #define A_TP_NVGRE_CONFIG 0x59
25375 
25376 #define S_GREFLAGS    16
25377 #define M_GREFLAGS    0xffffU
25378 #define V_GREFLAGS(x) ((x) << S_GREFLAGS)
25379 #define G_GREFLAGS(x) (((x) >> S_GREFLAGS) & M_GREFLAGS)
25380 
25381 #define S_GRETYPE    0
25382 #define M_GRETYPE    0xffffU
25383 #define V_GRETYPE(x) ((x) << S_GRETYPE)
25384 #define G_GRETYPE(x) (((x) >> S_GRETYPE) & M_GRETYPE)
25385 
25386 #define A_TP_DBG_CLEAR 0x60
25387 #define A_TP_DBG_CORE_HDR0 0x61
25388 
25389 #define S_E_TCP_OP_SRDY    16
25390 #define V_E_TCP_OP_SRDY(x) ((x) << S_E_TCP_OP_SRDY)
25391 #define F_E_TCP_OP_SRDY    V_E_TCP_OP_SRDY(1U)
25392 
25393 #define S_E_PLD_TXZEROP_SRDY    15
25394 #define V_E_PLD_TXZEROP_SRDY(x) ((x) << S_E_PLD_TXZEROP_SRDY)
25395 #define F_E_PLD_TXZEROP_SRDY    V_E_PLD_TXZEROP_SRDY(1U)
25396 
25397 #define S_E_PLD_RX_SRDY    14
25398 #define V_E_PLD_RX_SRDY(x) ((x) << S_E_PLD_RX_SRDY)
25399 #define F_E_PLD_RX_SRDY    V_E_PLD_RX_SRDY(1U)
25400 
25401 #define S_E_RX_ERROR_SRDY    13
25402 #define V_E_RX_ERROR_SRDY(x) ((x) << S_E_RX_ERROR_SRDY)
25403 #define F_E_RX_ERROR_SRDY    V_E_RX_ERROR_SRDY(1U)
25404 
25405 #define S_E_RX_ISS_SRDY    12
25406 #define V_E_RX_ISS_SRDY(x) ((x) << S_E_RX_ISS_SRDY)
25407 #define F_E_RX_ISS_SRDY    V_E_RX_ISS_SRDY(1U)
25408 
25409 #define S_C_TCP_OP_SRDY    11
25410 #define V_C_TCP_OP_SRDY(x) ((x) << S_C_TCP_OP_SRDY)
25411 #define F_C_TCP_OP_SRDY    V_C_TCP_OP_SRDY(1U)
25412 
25413 #define S_C_PLD_TXZEROP_SRDY    10
25414 #define V_C_PLD_TXZEROP_SRDY(x) ((x) << S_C_PLD_TXZEROP_SRDY)
25415 #define F_C_PLD_TXZEROP_SRDY    V_C_PLD_TXZEROP_SRDY(1U)
25416 
25417 #define S_C_PLD_RX_SRDY    9
25418 #define V_C_PLD_RX_SRDY(x) ((x) << S_C_PLD_RX_SRDY)
25419 #define F_C_PLD_RX_SRDY    V_C_PLD_RX_SRDY(1U)
25420 
25421 #define S_C_RX_ERROR_SRDY    8
25422 #define V_C_RX_ERROR_SRDY(x) ((x) << S_C_RX_ERROR_SRDY)
25423 #define F_C_RX_ERROR_SRDY    V_C_RX_ERROR_SRDY(1U)
25424 
25425 #define S_C_RX_ISS_SRDY    7
25426 #define V_C_RX_ISS_SRDY(x) ((x) << S_C_RX_ISS_SRDY)
25427 #define F_C_RX_ISS_SRDY    V_C_RX_ISS_SRDY(1U)
25428 
25429 #define S_E_CPL5_TXVALID    6
25430 #define V_E_CPL5_TXVALID(x) ((x) << S_E_CPL5_TXVALID)
25431 #define F_E_CPL5_TXVALID    V_E_CPL5_TXVALID(1U)
25432 
25433 #define S_E_ETH_TXVALID    5
25434 #define V_E_ETH_TXVALID(x) ((x) << S_E_ETH_TXVALID)
25435 #define F_E_ETH_TXVALID    V_E_ETH_TXVALID(1U)
25436 
25437 #define S_E_IP_TXVALID    4
25438 #define V_E_IP_TXVALID(x) ((x) << S_E_IP_TXVALID)
25439 #define F_E_IP_TXVALID    V_E_IP_TXVALID(1U)
25440 
25441 #define S_E_TCP_TXVALID    3
25442 #define V_E_TCP_TXVALID(x) ((x) << S_E_TCP_TXVALID)
25443 #define F_E_TCP_TXVALID    V_E_TCP_TXVALID(1U)
25444 
25445 #define S_C_CPL5_RXVALID    2
25446 #define V_C_CPL5_RXVALID(x) ((x) << S_C_CPL5_RXVALID)
25447 #define F_C_CPL5_RXVALID    V_C_CPL5_RXVALID(1U)
25448 
25449 #define S_C_CPL5_TXVALID    1
25450 #define V_C_CPL5_TXVALID(x) ((x) << S_C_CPL5_TXVALID)
25451 #define F_C_CPL5_TXVALID    V_C_CPL5_TXVALID(1U)
25452 
25453 #define S_E_TCP_OPT_RXVALID    0
25454 #define V_E_TCP_OPT_RXVALID(x) ((x) << S_E_TCP_OPT_RXVALID)
25455 #define F_E_TCP_OPT_RXVALID    V_E_TCP_OPT_RXVALID(1U)
25456 
25457 #define A_TP_DBG_CORE_HDR1 0x62
25458 
25459 #define S_E_CPL5_TXFULL    6
25460 #define V_E_CPL5_TXFULL(x) ((x) << S_E_CPL5_TXFULL)
25461 #define F_E_CPL5_TXFULL    V_E_CPL5_TXFULL(1U)
25462 
25463 #define S_E_ETH_TXFULL    5
25464 #define V_E_ETH_TXFULL(x) ((x) << S_E_ETH_TXFULL)
25465 #define F_E_ETH_TXFULL    V_E_ETH_TXFULL(1U)
25466 
25467 #define S_E_IP_TXFULL    4
25468 #define V_E_IP_TXFULL(x) ((x) << S_E_IP_TXFULL)
25469 #define F_E_IP_TXFULL    V_E_IP_TXFULL(1U)
25470 
25471 #define S_E_TCP_TXFULL    3
25472 #define V_E_TCP_TXFULL(x) ((x) << S_E_TCP_TXFULL)
25473 #define F_E_TCP_TXFULL    V_E_TCP_TXFULL(1U)
25474 
25475 #define S_C_CPL5_RXFULL    2
25476 #define V_C_CPL5_RXFULL(x) ((x) << S_C_CPL5_RXFULL)
25477 #define F_C_CPL5_RXFULL    V_C_CPL5_RXFULL(1U)
25478 
25479 #define S_C_CPL5_TXFULL    1
25480 #define V_C_CPL5_TXFULL(x) ((x) << S_C_CPL5_TXFULL)
25481 #define F_C_CPL5_TXFULL    V_C_CPL5_TXFULL(1U)
25482 
25483 #define S_E_TCP_OPT_RXFULL    0
25484 #define V_E_TCP_OPT_RXFULL(x) ((x) << S_E_TCP_OPT_RXFULL)
25485 #define F_E_TCP_OPT_RXFULL    V_E_TCP_OPT_RXFULL(1U)
25486 
25487 #define A_TP_DBG_CORE_FATAL 0x63
25488 
25489 #define S_EMSGFATAL    31
25490 #define V_EMSGFATAL(x) ((x) << S_EMSGFATAL)
25491 #define F_EMSGFATAL    V_EMSGFATAL(1U)
25492 
25493 #define S_CMSGFATAL    30
25494 #define V_CMSGFATAL(x) ((x) << S_CMSGFATAL)
25495 #define F_CMSGFATAL    V_CMSGFATAL(1U)
25496 
25497 #define S_PAWSFATAL    29
25498 #define V_PAWSFATAL(x) ((x) << S_PAWSFATAL)
25499 #define F_PAWSFATAL    V_PAWSFATAL(1U)
25500 
25501 #define S_SRAMFATAL    28
25502 #define V_SRAMFATAL(x) ((x) << S_SRAMFATAL)
25503 #define F_SRAMFATAL    V_SRAMFATAL(1U)
25504 
25505 #define S_CPCMDCONG    24
25506 #define M_CPCMDCONG    0xfU
25507 #define V_CPCMDCONG(x) ((x) << S_CPCMDCONG)
25508 #define G_CPCMDCONG(x) (((x) >> S_CPCMDCONG) & M_CPCMDCONG)
25509 
25510 #define S_EPCMDCONG    22
25511 #define M_EPCMDCONG    0x3U
25512 #define V_EPCMDCONG(x) ((x) << S_EPCMDCONG)
25513 #define G_EPCMDCONG(x) (((x) >> S_EPCMDCONG) & M_EPCMDCONG)
25514 
25515 #define S_CPCMDLENFATAL    21
25516 #define V_CPCMDLENFATAL(x) ((x) << S_CPCMDLENFATAL)
25517 #define F_CPCMDLENFATAL    V_CPCMDLENFATAL(1U)
25518 
25519 #define S_EPCMDLENFATAL    20
25520 #define V_EPCMDLENFATAL(x) ((x) << S_EPCMDLENFATAL)
25521 #define F_EPCMDLENFATAL    V_EPCMDLENFATAL(1U)
25522 
25523 #define S_CPCMDVALID    16
25524 #define M_CPCMDVALID    0xfU
25525 #define V_CPCMDVALID(x) ((x) << S_CPCMDVALID)
25526 #define G_CPCMDVALID(x) (((x) >> S_CPCMDVALID) & M_CPCMDVALID)
25527 
25528 #define S_CPCMDAFULL    12
25529 #define M_CPCMDAFULL    0xfU
25530 #define V_CPCMDAFULL(x) ((x) << S_CPCMDAFULL)
25531 #define G_CPCMDAFULL(x) (((x) >> S_CPCMDAFULL) & M_CPCMDAFULL)
25532 
25533 #define S_EPCMDVALID    10
25534 #define M_EPCMDVALID    0x3U
25535 #define V_EPCMDVALID(x) ((x) << S_EPCMDVALID)
25536 #define G_EPCMDVALID(x) (((x) >> S_EPCMDVALID) & M_EPCMDVALID)
25537 
25538 #define S_EPCMDAFULL    8
25539 #define M_EPCMDAFULL    0x3U
25540 #define V_EPCMDAFULL(x) ((x) << S_EPCMDAFULL)
25541 #define G_EPCMDAFULL(x) (((x) >> S_EPCMDAFULL) & M_EPCMDAFULL)
25542 
25543 #define S_CPCMDEOIFATAL    7
25544 #define V_CPCMDEOIFATAL(x) ((x) << S_CPCMDEOIFATAL)
25545 #define F_CPCMDEOIFATAL    V_CPCMDEOIFATAL(1U)
25546 
25547 #define S_CMDBRQFATAL    4
25548 #define V_CMDBRQFATAL(x) ((x) << S_CMDBRQFATAL)
25549 #define F_CMDBRQFATAL    V_CMDBRQFATAL(1U)
25550 
25551 #define S_CNONZEROPPOPCNT    2
25552 #define M_CNONZEROPPOPCNT    0x3U
25553 #define V_CNONZEROPPOPCNT(x) ((x) << S_CNONZEROPPOPCNT)
25554 #define G_CNONZEROPPOPCNT(x) (((x) >> S_CNONZEROPPOPCNT) & M_CNONZEROPPOPCNT)
25555 
25556 #define S_CPCMDEOICNT    0
25557 #define M_CPCMDEOICNT    0x3U
25558 #define V_CPCMDEOICNT(x) ((x) << S_CPCMDEOICNT)
25559 #define G_CPCMDEOICNT(x) (((x) >> S_CPCMDEOICNT) & M_CPCMDEOICNT)
25560 
25561 #define S_CPCMDTTLFATAL    6
25562 #define V_CPCMDTTLFATAL(x) ((x) << S_CPCMDTTLFATAL)
25563 #define F_CPCMDTTLFATAL    V_CPCMDTTLFATAL(1U)
25564 
25565 #define S_CDATACHNFATAL    5
25566 #define V_CDATACHNFATAL(x) ((x) << S_CDATACHNFATAL)
25567 #define F_CDATACHNFATAL    V_CDATACHNFATAL(1U)
25568 
25569 #define A_TP_DBG_CORE_OUT 0x64
25570 
25571 #define S_CCPLENC    26
25572 #define V_CCPLENC(x) ((x) << S_CCPLENC)
25573 #define F_CCPLENC    V_CCPLENC(1U)
25574 
25575 #define S_CWRCPLPKT    25
25576 #define V_CWRCPLPKT(x) ((x) << S_CWRCPLPKT)
25577 #define F_CWRCPLPKT    V_CWRCPLPKT(1U)
25578 
25579 #define S_CWRETHPKT    24
25580 #define V_CWRETHPKT(x) ((x) << S_CWRETHPKT)
25581 #define F_CWRETHPKT    V_CWRETHPKT(1U)
25582 
25583 #define S_CWRIPPKT    23
25584 #define V_CWRIPPKT(x) ((x) << S_CWRIPPKT)
25585 #define F_CWRIPPKT    V_CWRIPPKT(1U)
25586 
25587 #define S_CWRTCPPKT    22
25588 #define V_CWRTCPPKT(x) ((x) << S_CWRTCPPKT)
25589 #define F_CWRTCPPKT    V_CWRTCPPKT(1U)
25590 
25591 #define S_CWRZEROP    21
25592 #define V_CWRZEROP(x) ((x) << S_CWRZEROP)
25593 #define F_CWRZEROP    V_CWRZEROP(1U)
25594 
25595 #define S_CCPLTXFULL    20
25596 #define V_CCPLTXFULL(x) ((x) << S_CCPLTXFULL)
25597 #define F_CCPLTXFULL    V_CCPLTXFULL(1U)
25598 
25599 #define S_CETHTXFULL    19
25600 #define V_CETHTXFULL(x) ((x) << S_CETHTXFULL)
25601 #define F_CETHTXFULL    V_CETHTXFULL(1U)
25602 
25603 #define S_CIPTXFULL    18
25604 #define V_CIPTXFULL(x) ((x) << S_CIPTXFULL)
25605 #define F_CIPTXFULL    V_CIPTXFULL(1U)
25606 
25607 #define S_CTCPTXFULL    17
25608 #define V_CTCPTXFULL(x) ((x) << S_CTCPTXFULL)
25609 #define F_CTCPTXFULL    V_CTCPTXFULL(1U)
25610 
25611 #define S_CPLDTXZEROPDRDY    16
25612 #define V_CPLDTXZEROPDRDY(x) ((x) << S_CPLDTXZEROPDRDY)
25613 #define F_CPLDTXZEROPDRDY    V_CPLDTXZEROPDRDY(1U)
25614 
25615 #define S_ECPLENC    10
25616 #define V_ECPLENC(x) ((x) << S_ECPLENC)
25617 #define F_ECPLENC    V_ECPLENC(1U)
25618 
25619 #define S_EWRCPLPKT    9
25620 #define V_EWRCPLPKT(x) ((x) << S_EWRCPLPKT)
25621 #define F_EWRCPLPKT    V_EWRCPLPKT(1U)
25622 
25623 #define S_EWRETHPKT    8
25624 #define V_EWRETHPKT(x) ((x) << S_EWRETHPKT)
25625 #define F_EWRETHPKT    V_EWRETHPKT(1U)
25626 
25627 #define S_EWRIPPKT    7
25628 #define V_EWRIPPKT(x) ((x) << S_EWRIPPKT)
25629 #define F_EWRIPPKT    V_EWRIPPKT(1U)
25630 
25631 #define S_EWRTCPPKT    6
25632 #define V_EWRTCPPKT(x) ((x) << S_EWRTCPPKT)
25633 #define F_EWRTCPPKT    V_EWRTCPPKT(1U)
25634 
25635 #define S_EWRZEROP    5
25636 #define V_EWRZEROP(x) ((x) << S_EWRZEROP)
25637 #define F_EWRZEROP    V_EWRZEROP(1U)
25638 
25639 #define S_ECPLTXFULL    4
25640 #define V_ECPLTXFULL(x) ((x) << S_ECPLTXFULL)
25641 #define F_ECPLTXFULL    V_ECPLTXFULL(1U)
25642 
25643 #define S_EETHTXFULL    3
25644 #define V_EETHTXFULL(x) ((x) << S_EETHTXFULL)
25645 #define F_EETHTXFULL    V_EETHTXFULL(1U)
25646 
25647 #define S_EIPTXFULL    2
25648 #define V_EIPTXFULL(x) ((x) << S_EIPTXFULL)
25649 #define F_EIPTXFULL    V_EIPTXFULL(1U)
25650 
25651 #define S_ETCPTXFULL    1
25652 #define V_ETCPTXFULL(x) ((x) << S_ETCPTXFULL)
25653 #define F_ETCPTXFULL    V_ETCPTXFULL(1U)
25654 
25655 #define S_EPLDTXZEROPDRDY    0
25656 #define V_EPLDTXZEROPDRDY(x) ((x) << S_EPLDTXZEROPDRDY)
25657 #define F_EPLDTXZEROPDRDY    V_EPLDTXZEROPDRDY(1U)
25658 
25659 #define S_CRXBUSYOUT    31
25660 #define V_CRXBUSYOUT(x) ((x) << S_CRXBUSYOUT)
25661 #define F_CRXBUSYOUT    V_CRXBUSYOUT(1U)
25662 
25663 #define S_CTXBUSYOUT    30
25664 #define V_CTXBUSYOUT(x) ((x) << S_CTXBUSYOUT)
25665 #define F_CTXBUSYOUT    V_CTXBUSYOUT(1U)
25666 
25667 #define S_CRDCPLPKT    29
25668 #define V_CRDCPLPKT(x) ((x) << S_CRDCPLPKT)
25669 #define F_CRDCPLPKT    V_CRDCPLPKT(1U)
25670 
25671 #define S_CRDTCPPKT    28
25672 #define V_CRDTCPPKT(x) ((x) << S_CRDTCPPKT)
25673 #define F_CRDTCPPKT    V_CRDTCPPKT(1U)
25674 
25675 #define S_CNEWMSG    27
25676 #define V_CNEWMSG(x) ((x) << S_CNEWMSG)
25677 #define F_CNEWMSG    V_CNEWMSG(1U)
25678 
25679 #define S_ERXBUSYOUT    15
25680 #define V_ERXBUSYOUT(x) ((x) << S_ERXBUSYOUT)
25681 #define F_ERXBUSYOUT    V_ERXBUSYOUT(1U)
25682 
25683 #define S_ETXBUSYOUT    14
25684 #define V_ETXBUSYOUT(x) ((x) << S_ETXBUSYOUT)
25685 #define F_ETXBUSYOUT    V_ETXBUSYOUT(1U)
25686 
25687 #define S_ERDCPLPKT    13
25688 #define V_ERDCPLPKT(x) ((x) << S_ERDCPLPKT)
25689 #define F_ERDCPLPKT    V_ERDCPLPKT(1U)
25690 
25691 #define S_ERDTCPPKT    12
25692 #define V_ERDTCPPKT(x) ((x) << S_ERDTCPPKT)
25693 #define F_ERDTCPPKT    V_ERDTCPPKT(1U)
25694 
25695 #define S_ENEWMSG    11
25696 #define V_ENEWMSG(x) ((x) << S_ENEWMSG)
25697 #define F_ENEWMSG    V_ENEWMSG(1U)
25698 
25699 #define A_TP_DBG_CORE_TID 0x65
25700 
25701 #define S_LINENUMBER    24
25702 #define M_LINENUMBER    0x7fU
25703 #define V_LINENUMBER(x) ((x) << S_LINENUMBER)
25704 #define G_LINENUMBER(x) (((x) >> S_LINENUMBER) & M_LINENUMBER)
25705 
25706 #define S_SPURIOUSMSG    23
25707 #define V_SPURIOUSMSG(x) ((x) << S_SPURIOUSMSG)
25708 #define F_SPURIOUSMSG    V_SPURIOUSMSG(1U)
25709 
25710 #define S_SYNLEARNED    20
25711 #define V_SYNLEARNED(x) ((x) << S_SYNLEARNED)
25712 #define F_SYNLEARNED    V_SYNLEARNED(1U)
25713 
25714 #define S_TIDVALUE    0
25715 #define M_TIDVALUE    0xfffffU
25716 #define V_TIDVALUE(x) ((x) << S_TIDVALUE)
25717 #define G_TIDVALUE(x) (((x) >> S_TIDVALUE) & M_TIDVALUE)
25718 
25719 #define S_SRC    21
25720 #define M_SRC    0x3U
25721 #define V_SRC(x) ((x) << S_SRC)
25722 #define G_SRC(x) (((x) >> S_SRC) & M_SRC)
25723 
25724 #define A_TP_DBG_ENG_RES0 0x66
25725 
25726 #define S_RESOURCESREADY    31
25727 #define V_RESOURCESREADY(x) ((x) << S_RESOURCESREADY)
25728 #define F_RESOURCESREADY    V_RESOURCESREADY(1U)
25729 
25730 #define S_RCFOPCODEOUTSRDY    30
25731 #define V_RCFOPCODEOUTSRDY(x) ((x) << S_RCFOPCODEOUTSRDY)
25732 #define F_RCFOPCODEOUTSRDY    V_RCFOPCODEOUTSRDY(1U)
25733 
25734 #define S_RCFDATAOUTSRDY    29
25735 #define V_RCFDATAOUTSRDY(x) ((x) << S_RCFDATAOUTSRDY)
25736 #define F_RCFDATAOUTSRDY    V_RCFDATAOUTSRDY(1U)
25737 
25738 #define S_FLUSHINPUTMSG    28
25739 #define V_FLUSHINPUTMSG(x) ((x) << S_FLUSHINPUTMSG)
25740 #define F_FLUSHINPUTMSG    V_FLUSHINPUTMSG(1U)
25741 
25742 #define S_RCFOPSRCOUT    26
25743 #define M_RCFOPSRCOUT    0x3U
25744 #define V_RCFOPSRCOUT(x) ((x) << S_RCFOPSRCOUT)
25745 #define G_RCFOPSRCOUT(x) (((x) >> S_RCFOPSRCOUT) & M_RCFOPSRCOUT)
25746 
25747 #define S_C_MSG    25
25748 #define V_C_MSG(x) ((x) << S_C_MSG)
25749 #define F_C_MSG    V_C_MSG(1U)
25750 
25751 #define S_E_MSG    24
25752 #define V_E_MSG(x) ((x) << S_E_MSG)
25753 #define F_E_MSG    V_E_MSG(1U)
25754 
25755 #define S_RCFOPCODEOUT    20
25756 #define M_RCFOPCODEOUT    0xfU
25757 #define V_RCFOPCODEOUT(x) ((x) << S_RCFOPCODEOUT)
25758 #define G_RCFOPCODEOUT(x) (((x) >> S_RCFOPCODEOUT) & M_RCFOPCODEOUT)
25759 
25760 #define S_EFFRCFOPCODEOUT    16
25761 #define M_EFFRCFOPCODEOUT    0xfU
25762 #define V_EFFRCFOPCODEOUT(x) ((x) << S_EFFRCFOPCODEOUT)
25763 #define G_EFFRCFOPCODEOUT(x) (((x) >> S_EFFRCFOPCODEOUT) & M_EFFRCFOPCODEOUT)
25764 
25765 #define S_SEENRESOURCESREADY    15
25766 #define V_SEENRESOURCESREADY(x) ((x) << S_SEENRESOURCESREADY)
25767 #define F_SEENRESOURCESREADY    V_SEENRESOURCESREADY(1U)
25768 
25769 #define S_RESOURCESREADYCOPY    14
25770 #define V_RESOURCESREADYCOPY(x) ((x) << S_RESOURCESREADYCOPY)
25771 #define F_RESOURCESREADYCOPY    V_RESOURCESREADYCOPY(1U)
25772 
25773 #define S_OPCODEWAITSFORDATA    13
25774 #define V_OPCODEWAITSFORDATA(x) ((x) << S_OPCODEWAITSFORDATA)
25775 #define F_OPCODEWAITSFORDATA    V_OPCODEWAITSFORDATA(1U)
25776 
25777 #define S_CPLDRXSRDY    12
25778 #define V_CPLDRXSRDY(x) ((x) << S_CPLDRXSRDY)
25779 #define F_CPLDRXSRDY    V_CPLDRXSRDY(1U)
25780 
25781 #define S_CPLDRXZEROPSRDY    11
25782 #define V_CPLDRXZEROPSRDY(x) ((x) << S_CPLDRXZEROPSRDY)
25783 #define F_CPLDRXZEROPSRDY    V_CPLDRXZEROPSRDY(1U)
25784 
25785 #define S_EPLDRXZEROPSRDY    10
25786 #define V_EPLDRXZEROPSRDY(x) ((x) << S_EPLDRXZEROPSRDY)
25787 #define F_EPLDRXZEROPSRDY    V_EPLDRXZEROPSRDY(1U)
25788 
25789 #define S_ERXERRORSRDY    9
25790 #define V_ERXERRORSRDY(x) ((x) << S_ERXERRORSRDY)
25791 #define F_ERXERRORSRDY    V_ERXERRORSRDY(1U)
25792 
25793 #define S_EPLDRXSRDY    8
25794 #define V_EPLDRXSRDY(x) ((x) << S_EPLDRXSRDY)
25795 #define F_EPLDRXSRDY    V_EPLDRXSRDY(1U)
25796 
25797 #define S_CRXBUSY    7
25798 #define V_CRXBUSY(x) ((x) << S_CRXBUSY)
25799 #define F_CRXBUSY    V_CRXBUSY(1U)
25800 
25801 #define S_ERXBUSY    6
25802 #define V_ERXBUSY(x) ((x) << S_ERXBUSY)
25803 #define F_ERXBUSY    V_ERXBUSY(1U)
25804 
25805 #define S_TIMERINSERTBUSY    5
25806 #define V_TIMERINSERTBUSY(x) ((x) << S_TIMERINSERTBUSY)
25807 #define F_TIMERINSERTBUSY    V_TIMERINSERTBUSY(1U)
25808 
25809 #define S_WCFBUSY    4
25810 #define V_WCFBUSY(x) ((x) << S_WCFBUSY)
25811 #define F_WCFBUSY    V_WCFBUSY(1U)
25812 
25813 #define S_CTXBUSY    3
25814 #define V_CTXBUSY(x) ((x) << S_CTXBUSY)
25815 #define F_CTXBUSY    V_CTXBUSY(1U)
25816 
25817 #define S_CPCMDBUSY    2
25818 #define V_CPCMDBUSY(x) ((x) << S_CPCMDBUSY)
25819 #define F_CPCMDBUSY    V_CPCMDBUSY(1U)
25820 
25821 #define S_EPCMDBUSY    1
25822 #define V_EPCMDBUSY(x) ((x) << S_EPCMDBUSY)
25823 #define F_EPCMDBUSY    V_EPCMDBUSY(1U)
25824 
25825 #define S_ETXBUSY    0
25826 #define V_ETXBUSY(x) ((x) << S_ETXBUSY)
25827 #define F_ETXBUSY    V_ETXBUSY(1U)
25828 
25829 #define S_EFFOPCODEOUT    16
25830 #define M_EFFOPCODEOUT    0xfU
25831 #define V_EFFOPCODEOUT(x) ((x) << S_EFFOPCODEOUT)
25832 #define G_EFFOPCODEOUT(x) (((x) >> S_EFFOPCODEOUT) & M_EFFOPCODEOUT)
25833 
25834 #define S_DELDRDY    14
25835 #define V_DELDRDY(x) ((x) << S_DELDRDY)
25836 #define F_DELDRDY    V_DELDRDY(1U)
25837 
25838 #define S_T5_ETXBUSY    1
25839 #define V_T5_ETXBUSY(x) ((x) << S_T5_ETXBUSY)
25840 #define F_T5_ETXBUSY    V_T5_ETXBUSY(1U)
25841 
25842 #define S_T5_EPCMDBUSY    0
25843 #define V_T5_EPCMDBUSY(x) ((x) << S_T5_EPCMDBUSY)
25844 #define F_T5_EPCMDBUSY    V_T5_EPCMDBUSY(1U)
25845 
25846 #define S_T6_ETXBUSY    1
25847 #define V_T6_ETXBUSY(x) ((x) << S_T6_ETXBUSY)
25848 #define F_T6_ETXBUSY    V_T6_ETXBUSY(1U)
25849 
25850 #define S_T6_EPCMDBUSY    0
25851 #define V_T6_EPCMDBUSY(x) ((x) << S_T6_EPCMDBUSY)
25852 #define F_T6_EPCMDBUSY    V_T6_EPCMDBUSY(1U)
25853 
25854 #define A_TP_DBG_ENG_RES1 0x67
25855 
25856 #define S_RXCPLSRDY    31
25857 #define V_RXCPLSRDY(x) ((x) << S_RXCPLSRDY)
25858 #define F_RXCPLSRDY    V_RXCPLSRDY(1U)
25859 
25860 #define S_RXOPTSRDY    30
25861 #define V_RXOPTSRDY(x) ((x) << S_RXOPTSRDY)
25862 #define F_RXOPTSRDY    V_RXOPTSRDY(1U)
25863 
25864 #define S_RXPLDLENSRDY    29
25865 #define V_RXPLDLENSRDY(x) ((x) << S_RXPLDLENSRDY)
25866 #define F_RXPLDLENSRDY    V_RXPLDLENSRDY(1U)
25867 
25868 #define S_RXNOTBUSY    28
25869 #define V_RXNOTBUSY(x) ((x) << S_RXNOTBUSY)
25870 #define F_RXNOTBUSY    V_RXNOTBUSY(1U)
25871 
25872 #define S_CPLCMDIN    20
25873 #define M_CPLCMDIN    0xffU
25874 #define V_CPLCMDIN(x) ((x) << S_CPLCMDIN)
25875 #define G_CPLCMDIN(x) (((x) >> S_CPLCMDIN) & M_CPLCMDIN)
25876 
25877 #define S_RCFPTIDSRDY    19
25878 #define V_RCFPTIDSRDY(x) ((x) << S_RCFPTIDSRDY)
25879 #define F_RCFPTIDSRDY    V_RCFPTIDSRDY(1U)
25880 
25881 #define S_EPDUHDRSRDY    18
25882 #define V_EPDUHDRSRDY(x) ((x) << S_EPDUHDRSRDY)
25883 #define F_EPDUHDRSRDY    V_EPDUHDRSRDY(1U)
25884 
25885 #define S_TUNNELPKTREG    17
25886 #define V_TUNNELPKTREG(x) ((x) << S_TUNNELPKTREG)
25887 #define F_TUNNELPKTREG    V_TUNNELPKTREG(1U)
25888 
25889 #define S_TXPKTCSUMSRDY    16
25890 #define V_TXPKTCSUMSRDY(x) ((x) << S_TXPKTCSUMSRDY)
25891 #define F_TXPKTCSUMSRDY    V_TXPKTCSUMSRDY(1U)
25892 
25893 #define S_TABLEACCESSLATENCY    12
25894 #define M_TABLEACCESSLATENCY    0xfU
25895 #define V_TABLEACCESSLATENCY(x) ((x) << S_TABLEACCESSLATENCY)
25896 #define G_TABLEACCESSLATENCY(x) (((x) >> S_TABLEACCESSLATENCY) & M_TABLEACCESSLATENCY)
25897 
25898 #define S_MMGRDONE    11
25899 #define V_MMGRDONE(x) ((x) << S_MMGRDONE)
25900 #define F_MMGRDONE    V_MMGRDONE(1U)
25901 
25902 #define S_SEENMMGRDONE    10
25903 #define V_SEENMMGRDONE(x) ((x) << S_SEENMMGRDONE)
25904 #define F_SEENMMGRDONE    V_SEENMMGRDONE(1U)
25905 
25906 #define S_RXERRORSRDY    9
25907 #define V_RXERRORSRDY(x) ((x) << S_RXERRORSRDY)
25908 #define F_RXERRORSRDY    V_RXERRORSRDY(1U)
25909 
25910 #define S_RCFOPTIONSTCPSRDY    8
25911 #define V_RCFOPTIONSTCPSRDY(x) ((x) << S_RCFOPTIONSTCPSRDY)
25912 #define F_RCFOPTIONSTCPSRDY    V_RCFOPTIONSTCPSRDY(1U)
25913 
25914 #define S_ENGINESTATE    6
25915 #define M_ENGINESTATE    0x3U
25916 #define V_ENGINESTATE(x) ((x) << S_ENGINESTATE)
25917 #define G_ENGINESTATE(x) (((x) >> S_ENGINESTATE) & M_ENGINESTATE)
25918 
25919 #define S_TABLEACCESINCREMENT    5
25920 #define V_TABLEACCESINCREMENT(x) ((x) << S_TABLEACCESINCREMENT)
25921 #define F_TABLEACCESINCREMENT    V_TABLEACCESINCREMENT(1U)
25922 
25923 #define S_TABLEACCESCOMPLETE    4
25924 #define V_TABLEACCESCOMPLETE(x) ((x) << S_TABLEACCESCOMPLETE)
25925 #define F_TABLEACCESCOMPLETE    V_TABLEACCESCOMPLETE(1U)
25926 
25927 #define S_RCFOPCODEOUTUSABLE    3
25928 #define V_RCFOPCODEOUTUSABLE(x) ((x) << S_RCFOPCODEOUTUSABLE)
25929 #define F_RCFOPCODEOUTUSABLE    V_RCFOPCODEOUTUSABLE(1U)
25930 
25931 #define S_RCFDATAOUTUSABLE    2
25932 #define V_RCFDATAOUTUSABLE(x) ((x) << S_RCFDATAOUTUSABLE)
25933 #define F_RCFDATAOUTUSABLE    V_RCFDATAOUTUSABLE(1U)
25934 
25935 #define S_RCFDATAWAITAFTERRD    1
25936 #define V_RCFDATAWAITAFTERRD(x) ((x) << S_RCFDATAWAITAFTERRD)
25937 #define F_RCFDATAWAITAFTERRD    V_RCFDATAWAITAFTERRD(1U)
25938 
25939 #define S_RCFDATACMRDY    0
25940 #define V_RCFDATACMRDY(x) ((x) << S_RCFDATACMRDY)
25941 #define F_RCFDATACMRDY    V_RCFDATACMRDY(1U)
25942 
25943 #define S_RXISSSRDY    28
25944 #define V_RXISSSRDY(x) ((x) << S_RXISSSRDY)
25945 #define F_RXISSSRDY    V_RXISSSRDY(1U)
25946 
25947 #define A_TP_DBG_ENG_RES2 0x68
25948 
25949 #define S_CPLCMDRAW    24
25950 #define M_CPLCMDRAW    0xffU
25951 #define V_CPLCMDRAW(x) ((x) << S_CPLCMDRAW)
25952 #define G_CPLCMDRAW(x) (((x) >> S_CPLCMDRAW) & M_CPLCMDRAW)
25953 
25954 #define S_RXMACPORT    20
25955 #define M_RXMACPORT    0xfU
25956 #define V_RXMACPORT(x) ((x) << S_RXMACPORT)
25957 #define G_RXMACPORT(x) (((x) >> S_RXMACPORT) & M_RXMACPORT)
25958 
25959 #define S_TXECHANNEL    18
25960 #define M_TXECHANNEL    0x3U
25961 #define V_TXECHANNEL(x) ((x) << S_TXECHANNEL)
25962 #define G_TXECHANNEL(x) (((x) >> S_TXECHANNEL) & M_TXECHANNEL)
25963 
25964 #define S_RXECHANNEL    16
25965 #define M_RXECHANNEL    0x3U
25966 #define V_RXECHANNEL(x) ((x) << S_RXECHANNEL)
25967 #define G_RXECHANNEL(x) (((x) >> S_RXECHANNEL) & M_RXECHANNEL)
25968 
25969 #define S_CDATAOUT    15
25970 #define V_CDATAOUT(x) ((x) << S_CDATAOUT)
25971 #define F_CDATAOUT    V_CDATAOUT(1U)
25972 
25973 #define S_CREADPDU    14
25974 #define V_CREADPDU(x) ((x) << S_CREADPDU)
25975 #define F_CREADPDU    V_CREADPDU(1U)
25976 
25977 #define S_EDATAOUT    13
25978 #define V_EDATAOUT(x) ((x) << S_EDATAOUT)
25979 #define F_EDATAOUT    V_EDATAOUT(1U)
25980 
25981 #define S_EREADPDU    12
25982 #define V_EREADPDU(x) ((x) << S_EREADPDU)
25983 #define F_EREADPDU    V_EREADPDU(1U)
25984 
25985 #define S_ETCPOPSRDY    11
25986 #define V_ETCPOPSRDY(x) ((x) << S_ETCPOPSRDY)
25987 #define F_ETCPOPSRDY    V_ETCPOPSRDY(1U)
25988 
25989 #define S_CTCPOPSRDY    10
25990 #define V_CTCPOPSRDY(x) ((x) << S_CTCPOPSRDY)
25991 #define F_CTCPOPSRDY    V_CTCPOPSRDY(1U)
25992 
25993 #define S_CPKTOUT    9
25994 #define V_CPKTOUT(x) ((x) << S_CPKTOUT)
25995 #define F_CPKTOUT    V_CPKTOUT(1U)
25996 
25997 #define S_CMDBRSPSRDY    8
25998 #define V_CMDBRSPSRDY(x) ((x) << S_CMDBRSPSRDY)
25999 #define F_CMDBRSPSRDY    V_CMDBRSPSRDY(1U)
26000 
26001 #define S_RXPSTRUCTSFULL    6
26002 #define M_RXPSTRUCTSFULL    0x3U
26003 #define V_RXPSTRUCTSFULL(x) ((x) << S_RXPSTRUCTSFULL)
26004 #define G_RXPSTRUCTSFULL(x) (((x) >> S_RXPSTRUCTSFULL) & M_RXPSTRUCTSFULL)
26005 
26006 #define S_RXPAGEPOOLFULL    4
26007 #define M_RXPAGEPOOLFULL    0x3U
26008 #define V_RXPAGEPOOLFULL(x) ((x) << S_RXPAGEPOOLFULL)
26009 #define G_RXPAGEPOOLFULL(x) (((x) >> S_RXPAGEPOOLFULL) & M_RXPAGEPOOLFULL)
26010 
26011 #define S_RCFREASONOUT    0
26012 #define M_RCFREASONOUT    0xfU
26013 #define V_RCFREASONOUT(x) ((x) << S_RCFREASONOUT)
26014 #define G_RCFREASONOUT(x) (((x) >> S_RCFREASONOUT) & M_RCFREASONOUT)
26015 
26016 #define A_TP_DBG_CORE_PCMD 0x69
26017 
26018 #define S_CPCMDEOPCNT    30
26019 #define M_CPCMDEOPCNT    0x3U
26020 #define V_CPCMDEOPCNT(x) ((x) << S_CPCMDEOPCNT)
26021 #define G_CPCMDEOPCNT(x) (((x) >> S_CPCMDEOPCNT) & M_CPCMDEOPCNT)
26022 
26023 #define S_CPCMDLENSAVE    16
26024 #define M_CPCMDLENSAVE    0x3fffU
26025 #define V_CPCMDLENSAVE(x) ((x) << S_CPCMDLENSAVE)
26026 #define G_CPCMDLENSAVE(x) (((x) >> S_CPCMDLENSAVE) & M_CPCMDLENSAVE)
26027 
26028 #define S_EPCMDEOPCNT    14
26029 #define M_EPCMDEOPCNT    0x3U
26030 #define V_EPCMDEOPCNT(x) ((x) << S_EPCMDEOPCNT)
26031 #define G_EPCMDEOPCNT(x) (((x) >> S_EPCMDEOPCNT) & M_EPCMDEOPCNT)
26032 
26033 #define S_EPCMDLENSAVE    0
26034 #define M_EPCMDLENSAVE    0x3fffU
26035 #define V_EPCMDLENSAVE(x) ((x) << S_EPCMDLENSAVE)
26036 #define G_EPCMDLENSAVE(x) (((x) >> S_EPCMDLENSAVE) & M_EPCMDLENSAVE)
26037 
26038 #define A_TP_DBG_SCHED_TX 0x6a
26039 
26040 #define S_TXCHNXOFF    28
26041 #define M_TXCHNXOFF    0xfU
26042 #define V_TXCHNXOFF(x) ((x) << S_TXCHNXOFF)
26043 #define G_TXCHNXOFF(x) (((x) >> S_TXCHNXOFF) & M_TXCHNXOFF)
26044 
26045 #define S_TXFIFOCNG    24
26046 #define M_TXFIFOCNG    0xfU
26047 #define V_TXFIFOCNG(x) ((x) << S_TXFIFOCNG)
26048 #define G_TXFIFOCNG(x) (((x) >> S_TXFIFOCNG) & M_TXFIFOCNG)
26049 
26050 #define S_TXPCMDCNG    20
26051 #define M_TXPCMDCNG    0xfU
26052 #define V_TXPCMDCNG(x) ((x) << S_TXPCMDCNG)
26053 #define G_TXPCMDCNG(x) (((x) >> S_TXPCMDCNG) & M_TXPCMDCNG)
26054 
26055 #define S_TXLPBKCNG    16
26056 #define M_TXLPBKCNG    0xfU
26057 #define V_TXLPBKCNG(x) ((x) << S_TXLPBKCNG)
26058 #define G_TXLPBKCNG(x) (((x) >> S_TXLPBKCNG) & M_TXLPBKCNG)
26059 
26060 #define S_TXHDRCNG    8
26061 #define M_TXHDRCNG    0xffU
26062 #define V_TXHDRCNG(x) ((x) << S_TXHDRCNG)
26063 #define G_TXHDRCNG(x) (((x) >> S_TXHDRCNG) & M_TXHDRCNG)
26064 
26065 #define S_TXMODXOFF    0
26066 #define M_TXMODXOFF    0xffU
26067 #define V_TXMODXOFF(x) ((x) << S_TXMODXOFF)
26068 #define G_TXMODXOFF(x) (((x) >> S_TXMODXOFF) & M_TXMODXOFF)
26069 
26070 #define A_TP_DBG_SCHED_RX 0x6b
26071 
26072 #define S_RXCHNXOFF    28
26073 #define M_RXCHNXOFF    0xfU
26074 #define V_RXCHNXOFF(x) ((x) << S_RXCHNXOFF)
26075 #define G_RXCHNXOFF(x) (((x) >> S_RXCHNXOFF) & M_RXCHNXOFF)
26076 
26077 #define S_RXSGECNG    24
26078 #define M_RXSGECNG    0xfU
26079 #define V_RXSGECNG(x) ((x) << S_RXSGECNG)
26080 #define G_RXSGECNG(x) (((x) >> S_RXSGECNG) & M_RXSGECNG)
26081 
26082 #define S_RXFIFOCNG    22
26083 #define M_RXFIFOCNG    0x3U
26084 #define V_RXFIFOCNG(x) ((x) << S_RXFIFOCNG)
26085 #define G_RXFIFOCNG(x) (((x) >> S_RXFIFOCNG) & M_RXFIFOCNG)
26086 
26087 #define S_RXPCMDCNG    20
26088 #define M_RXPCMDCNG    0x3U
26089 #define V_RXPCMDCNG(x) ((x) << S_RXPCMDCNG)
26090 #define G_RXPCMDCNG(x) (((x) >> S_RXPCMDCNG) & M_RXPCMDCNG)
26091 
26092 #define S_RXLPBKCNG    16
26093 #define M_RXLPBKCNG    0xfU
26094 #define V_RXLPBKCNG(x) ((x) << S_RXLPBKCNG)
26095 #define G_RXLPBKCNG(x) (((x) >> S_RXLPBKCNG) & M_RXLPBKCNG)
26096 
26097 #define S_RXHDRCNG    8
26098 #define M_RXHDRCNG    0xfU
26099 #define V_RXHDRCNG(x) ((x) << S_RXHDRCNG)
26100 #define G_RXHDRCNG(x) (((x) >> S_RXHDRCNG) & M_RXHDRCNG)
26101 
26102 #define S_RXMODXOFF    0
26103 #define M_RXMODXOFF    0x3U
26104 #define V_RXMODXOFF(x) ((x) << S_RXMODXOFF)
26105 #define G_RXMODXOFF(x) (((x) >> S_RXMODXOFF) & M_RXMODXOFF)
26106 
26107 #define S_T5_RXFIFOCNG    20
26108 #define M_T5_RXFIFOCNG    0xfU
26109 #define V_T5_RXFIFOCNG(x) ((x) << S_T5_RXFIFOCNG)
26110 #define G_T5_RXFIFOCNG(x) (((x) >> S_T5_RXFIFOCNG) & M_T5_RXFIFOCNG)
26111 
26112 #define S_T5_RXPCMDCNG    14
26113 #define M_T5_RXPCMDCNG    0x3U
26114 #define V_T5_RXPCMDCNG(x) ((x) << S_T5_RXPCMDCNG)
26115 #define G_T5_RXPCMDCNG(x) (((x) >> S_T5_RXPCMDCNG) & M_T5_RXPCMDCNG)
26116 
26117 #define S_T6_RXFIFOCNG    20
26118 #define M_T6_RXFIFOCNG    0xfU
26119 #define V_T6_RXFIFOCNG(x) ((x) << S_T6_RXFIFOCNG)
26120 #define G_T6_RXFIFOCNG(x) (((x) >> S_T6_RXFIFOCNG) & M_T6_RXFIFOCNG)
26121 
26122 #define S_T6_RXPCMDCNG    14
26123 #define M_T6_RXPCMDCNG    0x3U
26124 #define V_T6_RXPCMDCNG(x) ((x) << S_T6_RXPCMDCNG)
26125 #define G_T6_RXPCMDCNG(x) (((x) >> S_T6_RXPCMDCNG) & M_T6_RXPCMDCNG)
26126 
26127 #define A_TP_DBG_ERROR_CNT 0x6c
26128 #define A_TP_DBG_CORE_CPL 0x6d
26129 
26130 #define S_CPLCMDOUT3    24
26131 #define M_CPLCMDOUT3    0xffU
26132 #define V_CPLCMDOUT3(x) ((x) << S_CPLCMDOUT3)
26133 #define G_CPLCMDOUT3(x) (((x) >> S_CPLCMDOUT3) & M_CPLCMDOUT3)
26134 
26135 #define S_CPLCMDOUT2    16
26136 #define M_CPLCMDOUT2    0xffU
26137 #define V_CPLCMDOUT2(x) ((x) << S_CPLCMDOUT2)
26138 #define G_CPLCMDOUT2(x) (((x) >> S_CPLCMDOUT2) & M_CPLCMDOUT2)
26139 
26140 #define S_CPLCMDOUT1    8
26141 #define M_CPLCMDOUT1    0xffU
26142 #define V_CPLCMDOUT1(x) ((x) << S_CPLCMDOUT1)
26143 #define G_CPLCMDOUT1(x) (((x) >> S_CPLCMDOUT1) & M_CPLCMDOUT1)
26144 
26145 #define S_CPLCMDOUT0    0
26146 #define M_CPLCMDOUT0    0xffU
26147 #define V_CPLCMDOUT0(x) ((x) << S_CPLCMDOUT0)
26148 #define G_CPLCMDOUT0(x) (((x) >> S_CPLCMDOUT0) & M_CPLCMDOUT0)
26149 
26150 #define A_TP_MIB_DEBUG 0x6f
26151 
26152 #define S_SRC3    31
26153 #define V_SRC3(x) ((x) << S_SRC3)
26154 #define F_SRC3    V_SRC3(1U)
26155 
26156 #define S_LINENUM3    24
26157 #define M_LINENUM3    0x7fU
26158 #define V_LINENUM3(x) ((x) << S_LINENUM3)
26159 #define G_LINENUM3(x) (((x) >> S_LINENUM3) & M_LINENUM3)
26160 
26161 #define S_SRC2    23
26162 #define V_SRC2(x) ((x) << S_SRC2)
26163 #define F_SRC2    V_SRC2(1U)
26164 
26165 #define S_LINENUM2    16
26166 #define M_LINENUM2    0x7fU
26167 #define V_LINENUM2(x) ((x) << S_LINENUM2)
26168 #define G_LINENUM2(x) (((x) >> S_LINENUM2) & M_LINENUM2)
26169 
26170 #define S_SRC1    15
26171 #define V_SRC1(x) ((x) << S_SRC1)
26172 #define F_SRC1    V_SRC1(1U)
26173 
26174 #define S_LINENUM1    8
26175 #define M_LINENUM1    0x7fU
26176 #define V_LINENUM1(x) ((x) << S_LINENUM1)
26177 #define G_LINENUM1(x) (((x) >> S_LINENUM1) & M_LINENUM1)
26178 
26179 #define S_SRC0    7
26180 #define V_SRC0(x) ((x) << S_SRC0)
26181 #define F_SRC0    V_SRC0(1U)
26182 
26183 #define S_LINENUM0    0
26184 #define M_LINENUM0    0x7fU
26185 #define V_LINENUM0(x) ((x) << S_LINENUM0)
26186 #define G_LINENUM0(x) (((x) >> S_LINENUM0) & M_LINENUM0)
26187 
26188 #define A_TP_DBG_CACHE_WR_ALL 0x70
26189 #define A_TP_DBG_CACHE_WR_HIT 0x71
26190 #define A_TP_DBG_CACHE_RD_ALL 0x72
26191 #define A_TP_DBG_CACHE_RD_HIT 0x73
26192 #define A_TP_DBG_CACHE_MC_REQ 0x74
26193 #define A_TP_DBG_CACHE_MC_RSP 0x75
26194 #define A_TP_T5_TX_DROP_CNT_CH0 0x120
26195 #define A_TP_T5_TX_DROP_CNT_CH1 0x121
26196 #define A_TP_TX_DROP_CNT_CH2 0x122
26197 #define A_TP_TX_DROP_CNT_CH3 0x123
26198 #define A_TP_TX_DROP_CFG_CH0 0x12b
26199 
26200 #define S_TIMERENABLED    31
26201 #define V_TIMERENABLED(x) ((x) << S_TIMERENABLED)
26202 #define F_TIMERENABLED    V_TIMERENABLED(1U)
26203 
26204 #define S_TIMERERRORENABLE    30
26205 #define V_TIMERERRORENABLE(x) ((x) << S_TIMERERRORENABLE)
26206 #define F_TIMERERRORENABLE    V_TIMERERRORENABLE(1U)
26207 
26208 #define S_TIMERTHRESHOLD    4
26209 #define M_TIMERTHRESHOLD    0x3ffffffU
26210 #define V_TIMERTHRESHOLD(x) ((x) << S_TIMERTHRESHOLD)
26211 #define G_TIMERTHRESHOLD(x) (((x) >> S_TIMERTHRESHOLD) & M_TIMERTHRESHOLD)
26212 
26213 #define S_PACKETDROPS    0
26214 #define M_PACKETDROPS    0xfU
26215 #define V_PACKETDROPS(x) ((x) << S_PACKETDROPS)
26216 #define G_PACKETDROPS(x) (((x) >> S_PACKETDROPS) & M_PACKETDROPS)
26217 
26218 #define A_TP_TX_DROP_CFG_CH1 0x12c
26219 #define A_TP_TX_DROP_CNT_CH0 0x12d
26220 
26221 #define S_TXDROPCNTCH0SENT    16
26222 #define M_TXDROPCNTCH0SENT    0xffffU
26223 #define V_TXDROPCNTCH0SENT(x) ((x) << S_TXDROPCNTCH0SENT)
26224 #define G_TXDROPCNTCH0SENT(x) (((x) >> S_TXDROPCNTCH0SENT) & M_TXDROPCNTCH0SENT)
26225 
26226 #define S_TXDROPCNTCH0RCVD    0
26227 #define M_TXDROPCNTCH0RCVD    0xffffU
26228 #define V_TXDROPCNTCH0RCVD(x) ((x) << S_TXDROPCNTCH0RCVD)
26229 #define G_TXDROPCNTCH0RCVD(x) (((x) >> S_TXDROPCNTCH0RCVD) & M_TXDROPCNTCH0RCVD)
26230 
26231 #define A_TP_TX_DROP_CNT_CH1 0x12e
26232 
26233 #define S_TXDROPCNTCH1SENT    16
26234 #define M_TXDROPCNTCH1SENT    0xffffU
26235 #define V_TXDROPCNTCH1SENT(x) ((x) << S_TXDROPCNTCH1SENT)
26236 #define G_TXDROPCNTCH1SENT(x) (((x) >> S_TXDROPCNTCH1SENT) & M_TXDROPCNTCH1SENT)
26237 
26238 #define S_TXDROPCNTCH1RCVD    0
26239 #define M_TXDROPCNTCH1RCVD    0xffffU
26240 #define V_TXDROPCNTCH1RCVD(x) ((x) << S_TXDROPCNTCH1RCVD)
26241 #define G_TXDROPCNTCH1RCVD(x) (((x) >> S_TXDROPCNTCH1RCVD) & M_TXDROPCNTCH1RCVD)
26242 
26243 #define A_TP_TX_DROP_MODE 0x12f
26244 
26245 #define S_TXDROPMODECH3    3
26246 #define V_TXDROPMODECH3(x) ((x) << S_TXDROPMODECH3)
26247 #define F_TXDROPMODECH3    V_TXDROPMODECH3(1U)
26248 
26249 #define S_TXDROPMODECH2    2
26250 #define V_TXDROPMODECH2(x) ((x) << S_TXDROPMODECH2)
26251 #define F_TXDROPMODECH2    V_TXDROPMODECH2(1U)
26252 
26253 #define S_TXDROPMODECH1    1
26254 #define V_TXDROPMODECH1(x) ((x) << S_TXDROPMODECH1)
26255 #define F_TXDROPMODECH1    V_TXDROPMODECH1(1U)
26256 
26257 #define S_TXDROPMODECH0    0
26258 #define V_TXDROPMODECH0(x) ((x) << S_TXDROPMODECH0)
26259 #define F_TXDROPMODECH0    V_TXDROPMODECH0(1U)
26260 
26261 #define A_TP_DBG_ESIDE_PKT0 0x130
26262 
26263 #define S_ETXSOPCNT    28
26264 #define M_ETXSOPCNT    0xfU
26265 #define V_ETXSOPCNT(x) ((x) << S_ETXSOPCNT)
26266 #define G_ETXSOPCNT(x) (((x) >> S_ETXSOPCNT) & M_ETXSOPCNT)
26267 
26268 #define S_ETXEOPCNT    24
26269 #define M_ETXEOPCNT    0xfU
26270 #define V_ETXEOPCNT(x) ((x) << S_ETXEOPCNT)
26271 #define G_ETXEOPCNT(x) (((x) >> S_ETXEOPCNT) & M_ETXEOPCNT)
26272 
26273 #define S_ETXPLDSOPCNT    20
26274 #define M_ETXPLDSOPCNT    0xfU
26275 #define V_ETXPLDSOPCNT(x) ((x) << S_ETXPLDSOPCNT)
26276 #define G_ETXPLDSOPCNT(x) (((x) >> S_ETXPLDSOPCNT) & M_ETXPLDSOPCNT)
26277 
26278 #define S_ETXPLDEOPCNT    16
26279 #define M_ETXPLDEOPCNT    0xfU
26280 #define V_ETXPLDEOPCNT(x) ((x) << S_ETXPLDEOPCNT)
26281 #define G_ETXPLDEOPCNT(x) (((x) >> S_ETXPLDEOPCNT) & M_ETXPLDEOPCNT)
26282 
26283 #define S_ERXSOPCNT    12
26284 #define M_ERXSOPCNT    0xfU
26285 #define V_ERXSOPCNT(x) ((x) << S_ERXSOPCNT)
26286 #define G_ERXSOPCNT(x) (((x) >> S_ERXSOPCNT) & M_ERXSOPCNT)
26287 
26288 #define S_ERXEOPCNT    8
26289 #define M_ERXEOPCNT    0xfU
26290 #define V_ERXEOPCNT(x) ((x) << S_ERXEOPCNT)
26291 #define G_ERXEOPCNT(x) (((x) >> S_ERXEOPCNT) & M_ERXEOPCNT)
26292 
26293 #define S_ERXPLDSOPCNT    4
26294 #define M_ERXPLDSOPCNT    0xfU
26295 #define V_ERXPLDSOPCNT(x) ((x) << S_ERXPLDSOPCNT)
26296 #define G_ERXPLDSOPCNT(x) (((x) >> S_ERXPLDSOPCNT) & M_ERXPLDSOPCNT)
26297 
26298 #define S_ERXPLDEOPCNT    0
26299 #define M_ERXPLDEOPCNT    0xfU
26300 #define V_ERXPLDEOPCNT(x) ((x) << S_ERXPLDEOPCNT)
26301 #define G_ERXPLDEOPCNT(x) (((x) >> S_ERXPLDEOPCNT) & M_ERXPLDEOPCNT)
26302 
26303 #define A_TP_DBG_ESIDE_PKT1 0x131
26304 #define A_TP_DBG_ESIDE_PKT2 0x132
26305 #define A_TP_DBG_ESIDE_PKT3 0x133
26306 #define A_TP_DBG_ESIDE_FIFO0 0x134
26307 
26308 #define S_PLDRXCSUMVALID1    31
26309 #define V_PLDRXCSUMVALID1(x) ((x) << S_PLDRXCSUMVALID1)
26310 #define F_PLDRXCSUMVALID1    V_PLDRXCSUMVALID1(1U)
26311 
26312 #define S_PLDRXZEROPSRDY1    30
26313 #define V_PLDRXZEROPSRDY1(x) ((x) << S_PLDRXZEROPSRDY1)
26314 #define F_PLDRXZEROPSRDY1    V_PLDRXZEROPSRDY1(1U)
26315 
26316 #define S_PLDRXVALID1    29
26317 #define V_PLDRXVALID1(x) ((x) << S_PLDRXVALID1)
26318 #define F_PLDRXVALID1    V_PLDRXVALID1(1U)
26319 
26320 #define S_TCPRXVALID1    28
26321 #define V_TCPRXVALID1(x) ((x) << S_TCPRXVALID1)
26322 #define F_TCPRXVALID1    V_TCPRXVALID1(1U)
26323 
26324 #define S_IPRXVALID1    27
26325 #define V_IPRXVALID1(x) ((x) << S_IPRXVALID1)
26326 #define F_IPRXVALID1    V_IPRXVALID1(1U)
26327 
26328 #define S_ETHRXVALID1    26
26329 #define V_ETHRXVALID1(x) ((x) << S_ETHRXVALID1)
26330 #define F_ETHRXVALID1    V_ETHRXVALID1(1U)
26331 
26332 #define S_CPLRXVALID1    25
26333 #define V_CPLRXVALID1(x) ((x) << S_CPLRXVALID1)
26334 #define F_CPLRXVALID1    V_CPLRXVALID1(1U)
26335 
26336 #define S_FSTATIC1    24
26337 #define V_FSTATIC1(x) ((x) << S_FSTATIC1)
26338 #define F_FSTATIC1    V_FSTATIC1(1U)
26339 
26340 #define S_ERRORSRDY1    23
26341 #define V_ERRORSRDY1(x) ((x) << S_ERRORSRDY1)
26342 #define F_ERRORSRDY1    V_ERRORSRDY1(1U)
26343 
26344 #define S_PLDTXSRDY1    22
26345 #define V_PLDTXSRDY1(x) ((x) << S_PLDTXSRDY1)
26346 #define F_PLDTXSRDY1    V_PLDTXSRDY1(1U)
26347 
26348 #define S_DBVLD1    21
26349 #define V_DBVLD1(x) ((x) << S_DBVLD1)
26350 #define F_DBVLD1    V_DBVLD1(1U)
26351 
26352 #define S_PLDTXVALID1    20
26353 #define V_PLDTXVALID1(x) ((x) << S_PLDTXVALID1)
26354 #define F_PLDTXVALID1    V_PLDTXVALID1(1U)
26355 
26356 #define S_ETXVALID1    19
26357 #define V_ETXVALID1(x) ((x) << S_ETXVALID1)
26358 #define F_ETXVALID1    V_ETXVALID1(1U)
26359 
26360 #define S_ETXFULL1    18
26361 #define V_ETXFULL1(x) ((x) << S_ETXFULL1)
26362 #define F_ETXFULL1    V_ETXFULL1(1U)
26363 
26364 #define S_ERXVALID1    17
26365 #define V_ERXVALID1(x) ((x) << S_ERXVALID1)
26366 #define F_ERXVALID1    V_ERXVALID1(1U)
26367 
26368 #define S_ERXFULL1    16
26369 #define V_ERXFULL1(x) ((x) << S_ERXFULL1)
26370 #define F_ERXFULL1    V_ERXFULL1(1U)
26371 
26372 #define S_PLDRXCSUMVALID0    15
26373 #define V_PLDRXCSUMVALID0(x) ((x) << S_PLDRXCSUMVALID0)
26374 #define F_PLDRXCSUMVALID0    V_PLDRXCSUMVALID0(1U)
26375 
26376 #define S_PLDRXZEROPSRDY0    14
26377 #define V_PLDRXZEROPSRDY0(x) ((x) << S_PLDRXZEROPSRDY0)
26378 #define F_PLDRXZEROPSRDY0    V_PLDRXZEROPSRDY0(1U)
26379 
26380 #define S_PLDRXVALID0    13
26381 #define V_PLDRXVALID0(x) ((x) << S_PLDRXVALID0)
26382 #define F_PLDRXVALID0    V_PLDRXVALID0(1U)
26383 
26384 #define S_TCPRXVALID0    12
26385 #define V_TCPRXVALID0(x) ((x) << S_TCPRXVALID0)
26386 #define F_TCPRXVALID0    V_TCPRXVALID0(1U)
26387 
26388 #define S_IPRXVALID0    11
26389 #define V_IPRXVALID0(x) ((x) << S_IPRXVALID0)
26390 #define F_IPRXVALID0    V_IPRXVALID0(1U)
26391 
26392 #define S_ETHRXVALID0    10
26393 #define V_ETHRXVALID0(x) ((x) << S_ETHRXVALID0)
26394 #define F_ETHRXVALID0    V_ETHRXVALID0(1U)
26395 
26396 #define S_CPLRXVALID0    9
26397 #define V_CPLRXVALID0(x) ((x) << S_CPLRXVALID0)
26398 #define F_CPLRXVALID0    V_CPLRXVALID0(1U)
26399 
26400 #define S_FSTATIC0    8
26401 #define V_FSTATIC0(x) ((x) << S_FSTATIC0)
26402 #define F_FSTATIC0    V_FSTATIC0(1U)
26403 
26404 #define S_ERRORSRDY0    7
26405 #define V_ERRORSRDY0(x) ((x) << S_ERRORSRDY0)
26406 #define F_ERRORSRDY0    V_ERRORSRDY0(1U)
26407 
26408 #define S_PLDTXSRDY0    6
26409 #define V_PLDTXSRDY0(x) ((x) << S_PLDTXSRDY0)
26410 #define F_PLDTXSRDY0    V_PLDTXSRDY0(1U)
26411 
26412 #define S_DBVLD0    5
26413 #define V_DBVLD0(x) ((x) << S_DBVLD0)
26414 #define F_DBVLD0    V_DBVLD0(1U)
26415 
26416 #define S_PLDTXVALID0    4
26417 #define V_PLDTXVALID0(x) ((x) << S_PLDTXVALID0)
26418 #define F_PLDTXVALID0    V_PLDTXVALID0(1U)
26419 
26420 #define S_ETXVALID0    3
26421 #define V_ETXVALID0(x) ((x) << S_ETXVALID0)
26422 #define F_ETXVALID0    V_ETXVALID0(1U)
26423 
26424 #define S_ETXFULL0    2
26425 #define V_ETXFULL0(x) ((x) << S_ETXFULL0)
26426 #define F_ETXFULL0    V_ETXFULL0(1U)
26427 
26428 #define S_ERXVALID0    1
26429 #define V_ERXVALID0(x) ((x) << S_ERXVALID0)
26430 #define F_ERXVALID0    V_ERXVALID0(1U)
26431 
26432 #define S_ERXFULL0    0
26433 #define V_ERXFULL0(x) ((x) << S_ERXFULL0)
26434 #define F_ERXFULL0    V_ERXFULL0(1U)
26435 
26436 #define A_TP_DBG_ESIDE_FIFO1 0x135
26437 
26438 #define S_PLDRXCSUMVALID3    31
26439 #define V_PLDRXCSUMVALID3(x) ((x) << S_PLDRXCSUMVALID3)
26440 #define F_PLDRXCSUMVALID3    V_PLDRXCSUMVALID3(1U)
26441 
26442 #define S_PLDRXZEROPSRDY3    30
26443 #define V_PLDRXZEROPSRDY3(x) ((x) << S_PLDRXZEROPSRDY3)
26444 #define F_PLDRXZEROPSRDY3    V_PLDRXZEROPSRDY3(1U)
26445 
26446 #define S_PLDRXVALID3    29
26447 #define V_PLDRXVALID3(x) ((x) << S_PLDRXVALID3)
26448 #define F_PLDRXVALID3    V_PLDRXVALID3(1U)
26449 
26450 #define S_TCPRXVALID3    28
26451 #define V_TCPRXVALID3(x) ((x) << S_TCPRXVALID3)
26452 #define F_TCPRXVALID3    V_TCPRXVALID3(1U)
26453 
26454 #define S_IPRXVALID3    27
26455 #define V_IPRXVALID3(x) ((x) << S_IPRXVALID3)
26456 #define F_IPRXVALID3    V_IPRXVALID3(1U)
26457 
26458 #define S_ETHRXVALID3    26
26459 #define V_ETHRXVALID3(x) ((x) << S_ETHRXVALID3)
26460 #define F_ETHRXVALID3    V_ETHRXVALID3(1U)
26461 
26462 #define S_CPLRXVALID3    25
26463 #define V_CPLRXVALID3(x) ((x) << S_CPLRXVALID3)
26464 #define F_CPLRXVALID3    V_CPLRXVALID3(1U)
26465 
26466 #define S_FSTATIC3    24
26467 #define V_FSTATIC3(x) ((x) << S_FSTATIC3)
26468 #define F_FSTATIC3    V_FSTATIC3(1U)
26469 
26470 #define S_ERRORSRDY3    23
26471 #define V_ERRORSRDY3(x) ((x) << S_ERRORSRDY3)
26472 #define F_ERRORSRDY3    V_ERRORSRDY3(1U)
26473 
26474 #define S_PLDTXSRDY3    22
26475 #define V_PLDTXSRDY3(x) ((x) << S_PLDTXSRDY3)
26476 #define F_PLDTXSRDY3    V_PLDTXSRDY3(1U)
26477 
26478 #define S_DBVLD3    21
26479 #define V_DBVLD3(x) ((x) << S_DBVLD3)
26480 #define F_DBVLD3    V_DBVLD3(1U)
26481 
26482 #define S_PLDTXVALID3    20
26483 #define V_PLDTXVALID3(x) ((x) << S_PLDTXVALID3)
26484 #define F_PLDTXVALID3    V_PLDTXVALID3(1U)
26485 
26486 #define S_ETXVALID3    19
26487 #define V_ETXVALID3(x) ((x) << S_ETXVALID3)
26488 #define F_ETXVALID3    V_ETXVALID3(1U)
26489 
26490 #define S_ETXFULL3    18
26491 #define V_ETXFULL3(x) ((x) << S_ETXFULL3)
26492 #define F_ETXFULL3    V_ETXFULL3(1U)
26493 
26494 #define S_ERXVALID3    17
26495 #define V_ERXVALID3(x) ((x) << S_ERXVALID3)
26496 #define F_ERXVALID3    V_ERXVALID3(1U)
26497 
26498 #define S_ERXFULL3    16
26499 #define V_ERXFULL3(x) ((x) << S_ERXFULL3)
26500 #define F_ERXFULL3    V_ERXFULL3(1U)
26501 
26502 #define S_PLDRXCSUMVALID2    15
26503 #define V_PLDRXCSUMVALID2(x) ((x) << S_PLDRXCSUMVALID2)
26504 #define F_PLDRXCSUMVALID2    V_PLDRXCSUMVALID2(1U)
26505 
26506 #define S_PLDRXZEROPSRDY2    14
26507 #define V_PLDRXZEROPSRDY2(x) ((x) << S_PLDRXZEROPSRDY2)
26508 #define F_PLDRXZEROPSRDY2    V_PLDRXZEROPSRDY2(1U)
26509 
26510 #define S_PLDRXVALID2    13
26511 #define V_PLDRXVALID2(x) ((x) << S_PLDRXVALID2)
26512 #define F_PLDRXVALID2    V_PLDRXVALID2(1U)
26513 
26514 #define S_TCPRXVALID2    12
26515 #define V_TCPRXVALID2(x) ((x) << S_TCPRXVALID2)
26516 #define F_TCPRXVALID2    V_TCPRXVALID2(1U)
26517 
26518 #define S_IPRXVALID2    11
26519 #define V_IPRXVALID2(x) ((x) << S_IPRXVALID2)
26520 #define F_IPRXVALID2    V_IPRXVALID2(1U)
26521 
26522 #define S_ETHRXVALID2    10
26523 #define V_ETHRXVALID2(x) ((x) << S_ETHRXVALID2)
26524 #define F_ETHRXVALID2    V_ETHRXVALID2(1U)
26525 
26526 #define S_CPLRXVALID2    9
26527 #define V_CPLRXVALID2(x) ((x) << S_CPLRXVALID2)
26528 #define F_CPLRXVALID2    V_CPLRXVALID2(1U)
26529 
26530 #define S_FSTATIC2    8
26531 #define V_FSTATIC2(x) ((x) << S_FSTATIC2)
26532 #define F_FSTATIC2    V_FSTATIC2(1U)
26533 
26534 #define S_ERRORSRDY2    7
26535 #define V_ERRORSRDY2(x) ((x) << S_ERRORSRDY2)
26536 #define F_ERRORSRDY2    V_ERRORSRDY2(1U)
26537 
26538 #define S_PLDTXSRDY2    6
26539 #define V_PLDTXSRDY2(x) ((x) << S_PLDTXSRDY2)
26540 #define F_PLDTXSRDY2    V_PLDTXSRDY2(1U)
26541 
26542 #define S_DBVLD2    5
26543 #define V_DBVLD2(x) ((x) << S_DBVLD2)
26544 #define F_DBVLD2    V_DBVLD2(1U)
26545 
26546 #define S_PLDTXVALID2    4
26547 #define V_PLDTXVALID2(x) ((x) << S_PLDTXVALID2)
26548 #define F_PLDTXVALID2    V_PLDTXVALID2(1U)
26549 
26550 #define S_ETXVALID2    3
26551 #define V_ETXVALID2(x) ((x) << S_ETXVALID2)
26552 #define F_ETXVALID2    V_ETXVALID2(1U)
26553 
26554 #define S_ETXFULL2    2
26555 #define V_ETXFULL2(x) ((x) << S_ETXFULL2)
26556 #define F_ETXFULL2    V_ETXFULL2(1U)
26557 
26558 #define S_ERXVALID2    1
26559 #define V_ERXVALID2(x) ((x) << S_ERXVALID2)
26560 #define F_ERXVALID2    V_ERXVALID2(1U)
26561 
26562 #define S_ERXFULL2    0
26563 #define V_ERXFULL2(x) ((x) << S_ERXFULL2)
26564 #define F_ERXFULL2    V_ERXFULL2(1U)
26565 
26566 #define A_TP_DBG_ESIDE_DISP0 0x136
26567 
26568 #define S_RESRDY    31
26569 #define V_RESRDY(x) ((x) << S_RESRDY)
26570 #define F_RESRDY    V_RESRDY(1U)
26571 
26572 #define S_STATE    28
26573 #define M_STATE    0x7U
26574 #define V_STATE(x) ((x) << S_STATE)
26575 #define G_STATE(x) (((x) >> S_STATE) & M_STATE)
26576 
26577 #define S_FIFOCPL5RXVALID    27
26578 #define V_FIFOCPL5RXVALID(x) ((x) << S_FIFOCPL5RXVALID)
26579 #define F_FIFOCPL5RXVALID    V_FIFOCPL5RXVALID(1U)
26580 
26581 #define S_FIFOETHRXVALID    26
26582 #define V_FIFOETHRXVALID(x) ((x) << S_FIFOETHRXVALID)
26583 #define F_FIFOETHRXVALID    V_FIFOETHRXVALID(1U)
26584 
26585 #define S_FIFOETHRXSOCP    25
26586 #define V_FIFOETHRXSOCP(x) ((x) << S_FIFOETHRXSOCP)
26587 #define F_FIFOETHRXSOCP    V_FIFOETHRXSOCP(1U)
26588 
26589 #define S_FIFOPLDRXZEROP    24
26590 #define V_FIFOPLDRXZEROP(x) ((x) << S_FIFOPLDRXZEROP)
26591 #define F_FIFOPLDRXZEROP    V_FIFOPLDRXZEROP(1U)
26592 
26593 #define S_PLDRXVALID    23
26594 #define V_PLDRXVALID(x) ((x) << S_PLDRXVALID)
26595 #define F_PLDRXVALID    V_PLDRXVALID(1U)
26596 
26597 #define S_FIFOPLDRXZEROP_SRDY    22
26598 #define V_FIFOPLDRXZEROP_SRDY(x) ((x) << S_FIFOPLDRXZEROP_SRDY)
26599 #define F_FIFOPLDRXZEROP_SRDY    V_FIFOPLDRXZEROP_SRDY(1U)
26600 
26601 #define S_FIFOIPRXVALID    21
26602 #define V_FIFOIPRXVALID(x) ((x) << S_FIFOIPRXVALID)
26603 #define F_FIFOIPRXVALID    V_FIFOIPRXVALID(1U)
26604 
26605 #define S_FIFOTCPRXVALID    20
26606 #define V_FIFOTCPRXVALID(x) ((x) << S_FIFOTCPRXVALID)
26607 #define F_FIFOTCPRXVALID    V_FIFOTCPRXVALID(1U)
26608 
26609 #define S_PLDRXCSUMVALID    19
26610 #define V_PLDRXCSUMVALID(x) ((x) << S_PLDRXCSUMVALID)
26611 #define F_PLDRXCSUMVALID    V_PLDRXCSUMVALID(1U)
26612 
26613 #define S_FIFOIPCSUMSRDY    18
26614 #define V_FIFOIPCSUMSRDY(x) ((x) << S_FIFOIPCSUMSRDY)
26615 #define F_FIFOIPCSUMSRDY    V_FIFOIPCSUMSRDY(1U)
26616 
26617 #define S_FIFOIPPSEUDOCSUMSRDY    17
26618 #define V_FIFOIPPSEUDOCSUMSRDY(x) ((x) << S_FIFOIPPSEUDOCSUMSRDY)
26619 #define F_FIFOIPPSEUDOCSUMSRDY    V_FIFOIPPSEUDOCSUMSRDY(1U)
26620 
26621 #define S_FIFOTCPCSUMSRDY    16
26622 #define V_FIFOTCPCSUMSRDY(x) ((x) << S_FIFOTCPCSUMSRDY)
26623 #define F_FIFOTCPCSUMSRDY    V_FIFOTCPCSUMSRDY(1U)
26624 
26625 #define S_ESTATIC4    12
26626 #define M_ESTATIC4    0xfU
26627 #define V_ESTATIC4(x) ((x) << S_ESTATIC4)
26628 #define G_ESTATIC4(x) (((x) >> S_ESTATIC4) & M_ESTATIC4)
26629 
26630 #define S_FIFOCPLSOCPCNT    10
26631 #define M_FIFOCPLSOCPCNT    0x3U
26632 #define V_FIFOCPLSOCPCNT(x) ((x) << S_FIFOCPLSOCPCNT)
26633 #define G_FIFOCPLSOCPCNT(x) (((x) >> S_FIFOCPLSOCPCNT) & M_FIFOCPLSOCPCNT)
26634 
26635 #define S_FIFOETHSOCPCNT    8
26636 #define M_FIFOETHSOCPCNT    0x3U
26637 #define V_FIFOETHSOCPCNT(x) ((x) << S_FIFOETHSOCPCNT)
26638 #define G_FIFOETHSOCPCNT(x) (((x) >> S_FIFOETHSOCPCNT) & M_FIFOETHSOCPCNT)
26639 
26640 #define S_FIFOIPSOCPCNT    6
26641 #define M_FIFOIPSOCPCNT    0x3U
26642 #define V_FIFOIPSOCPCNT(x) ((x) << S_FIFOIPSOCPCNT)
26643 #define G_FIFOIPSOCPCNT(x) (((x) >> S_FIFOIPSOCPCNT) & M_FIFOIPSOCPCNT)
26644 
26645 #define S_FIFOTCPSOCPCNT    4
26646 #define M_FIFOTCPSOCPCNT    0x3U
26647 #define V_FIFOTCPSOCPCNT(x) ((x) << S_FIFOTCPSOCPCNT)
26648 #define G_FIFOTCPSOCPCNT(x) (((x) >> S_FIFOTCPSOCPCNT) & M_FIFOTCPSOCPCNT)
26649 
26650 #define S_PLD_RXZEROP_CNT    2
26651 #define M_PLD_RXZEROP_CNT    0x3U
26652 #define V_PLD_RXZEROP_CNT(x) ((x) << S_PLD_RXZEROP_CNT)
26653 #define G_PLD_RXZEROP_CNT(x) (((x) >> S_PLD_RXZEROP_CNT) & M_PLD_RXZEROP_CNT)
26654 
26655 #define S_ESTATIC6    1
26656 #define V_ESTATIC6(x) ((x) << S_ESTATIC6)
26657 #define F_ESTATIC6    V_ESTATIC6(1U)
26658 
26659 #define S_TXFULL    0
26660 #define V_TXFULL(x) ((x) << S_TXFULL)
26661 #define F_TXFULL    V_TXFULL(1U)
26662 
26663 #define S_FIFOGRERXVALID    15
26664 #define V_FIFOGRERXVALID(x) ((x) << S_FIFOGRERXVALID)
26665 #define F_FIFOGRERXVALID    V_FIFOGRERXVALID(1U)
26666 
26667 #define S_FIFOGRERXREADY    14
26668 #define V_FIFOGRERXREADY(x) ((x) << S_FIFOGRERXREADY)
26669 #define F_FIFOGRERXREADY    V_FIFOGRERXREADY(1U)
26670 
26671 #define S_FIFOGRERXSOCP    13
26672 #define V_FIFOGRERXSOCP(x) ((x) << S_FIFOGRERXSOCP)
26673 #define F_FIFOGRERXSOCP    V_FIFOGRERXSOCP(1U)
26674 
26675 #define S_T6_ESTATIC4    12
26676 #define V_T6_ESTATIC4(x) ((x) << S_T6_ESTATIC4)
26677 #define F_T6_ESTATIC4    V_T6_ESTATIC4(1U)
26678 
26679 #define S_TXFULL_ESIDE0    0
26680 #define V_TXFULL_ESIDE0(x) ((x) << S_TXFULL_ESIDE0)
26681 #define F_TXFULL_ESIDE0    V_TXFULL_ESIDE0(1U)
26682 
26683 #define A_TP_DBG_ESIDE_DISP1 0x137
26684 
26685 #define S_T6_ESTATIC4    12
26686 #define V_T6_ESTATIC4(x) ((x) << S_T6_ESTATIC4)
26687 #define F_T6_ESTATIC4    V_T6_ESTATIC4(1U)
26688 
26689 #define S_TXFULL_ESIDE1    0
26690 #define V_TXFULL_ESIDE1(x) ((x) << S_TXFULL_ESIDE1)
26691 #define F_TXFULL_ESIDE1    V_TXFULL_ESIDE1(1U)
26692 
26693 #define A_TP_MAC_MATCH_MAP0 0x138
26694 
26695 #define S_MAPVALUEWR    16
26696 #define M_MAPVALUEWR    0xffU
26697 #define V_MAPVALUEWR(x) ((x) << S_MAPVALUEWR)
26698 #define G_MAPVALUEWR(x) (((x) >> S_MAPVALUEWR) & M_MAPVALUEWR)
26699 
26700 #define S_MAPINDEX    2
26701 #define M_MAPINDEX    0x1ffU
26702 #define V_MAPINDEX(x) ((x) << S_MAPINDEX)
26703 #define G_MAPINDEX(x) (((x) >> S_MAPINDEX) & M_MAPINDEX)
26704 
26705 #define S_MAPREAD    1
26706 #define V_MAPREAD(x) ((x) << S_MAPREAD)
26707 #define F_MAPREAD    V_MAPREAD(1U)
26708 
26709 #define S_MAPWRITE    0
26710 #define V_MAPWRITE(x) ((x) << S_MAPWRITE)
26711 #define F_MAPWRITE    V_MAPWRITE(1U)
26712 
26713 #define A_TP_MAC_MATCH_MAP1 0x139
26714 
26715 #define S_MAPVALUERD    0
26716 #define M_MAPVALUERD    0x1ffU
26717 #define V_MAPVALUERD(x) ((x) << S_MAPVALUERD)
26718 #define G_MAPVALUERD(x) (((x) >> S_MAPVALUERD) & M_MAPVALUERD)
26719 
26720 #define A_TP_DBG_ESIDE_DISP2 0x13a
26721 
26722 #define S_T6_ESTATIC4    12
26723 #define V_T6_ESTATIC4(x) ((x) << S_T6_ESTATIC4)
26724 #define F_T6_ESTATIC4    V_T6_ESTATIC4(1U)
26725 
26726 #define S_TXFULL_ESIDE2    0
26727 #define V_TXFULL_ESIDE2(x) ((x) << S_TXFULL_ESIDE2)
26728 #define F_TXFULL_ESIDE2    V_TXFULL_ESIDE2(1U)
26729 
26730 #define A_TP_DBG_ESIDE_DISP3 0x13b
26731 
26732 #define S_T6_ESTATIC4    12
26733 #define V_T6_ESTATIC4(x) ((x) << S_T6_ESTATIC4)
26734 #define F_T6_ESTATIC4    V_T6_ESTATIC4(1U)
26735 
26736 #define S_TXFULL_ESIDE3    0
26737 #define V_TXFULL_ESIDE3(x) ((x) << S_TXFULL_ESIDE3)
26738 #define F_TXFULL_ESIDE3    V_TXFULL_ESIDE3(1U)
26739 
26740 #define A_TP_DBG_ESIDE_HDR0 0x13c
26741 
26742 #define S_TCPSOPCNT    28
26743 #define M_TCPSOPCNT    0xfU
26744 #define V_TCPSOPCNT(x) ((x) << S_TCPSOPCNT)
26745 #define G_TCPSOPCNT(x) (((x) >> S_TCPSOPCNT) & M_TCPSOPCNT)
26746 
26747 #define S_TCPEOPCNT    24
26748 #define M_TCPEOPCNT    0xfU
26749 #define V_TCPEOPCNT(x) ((x) << S_TCPEOPCNT)
26750 #define G_TCPEOPCNT(x) (((x) >> S_TCPEOPCNT) & M_TCPEOPCNT)
26751 
26752 #define S_IPSOPCNT    20
26753 #define M_IPSOPCNT    0xfU
26754 #define V_IPSOPCNT(x) ((x) << S_IPSOPCNT)
26755 #define G_IPSOPCNT(x) (((x) >> S_IPSOPCNT) & M_IPSOPCNT)
26756 
26757 #define S_IPEOPCNT    16
26758 #define M_IPEOPCNT    0xfU
26759 #define V_IPEOPCNT(x) ((x) << S_IPEOPCNT)
26760 #define G_IPEOPCNT(x) (((x) >> S_IPEOPCNT) & M_IPEOPCNT)
26761 
26762 #define S_ETHSOPCNT    12
26763 #define M_ETHSOPCNT    0xfU
26764 #define V_ETHSOPCNT(x) ((x) << S_ETHSOPCNT)
26765 #define G_ETHSOPCNT(x) (((x) >> S_ETHSOPCNT) & M_ETHSOPCNT)
26766 
26767 #define S_ETHEOPCNT    8
26768 #define M_ETHEOPCNT    0xfU
26769 #define V_ETHEOPCNT(x) ((x) << S_ETHEOPCNT)
26770 #define G_ETHEOPCNT(x) (((x) >> S_ETHEOPCNT) & M_ETHEOPCNT)
26771 
26772 #define S_CPLSOPCNT    4
26773 #define M_CPLSOPCNT    0xfU
26774 #define V_CPLSOPCNT(x) ((x) << S_CPLSOPCNT)
26775 #define G_CPLSOPCNT(x) (((x) >> S_CPLSOPCNT) & M_CPLSOPCNT)
26776 
26777 #define S_CPLEOPCNT    0
26778 #define M_CPLEOPCNT    0xfU
26779 #define V_CPLEOPCNT(x) ((x) << S_CPLEOPCNT)
26780 #define G_CPLEOPCNT(x) (((x) >> S_CPLEOPCNT) & M_CPLEOPCNT)
26781 
26782 #define A_TP_DBG_ESIDE_HDR1 0x13d
26783 #define A_TP_DBG_ESIDE_HDR2 0x13e
26784 #define A_TP_DBG_ESIDE_HDR3 0x13f
26785 #define A_TP_VLAN_PRI_MAP 0x140
26786 
26787 #define S_FRAGMENTATION    9
26788 #define V_FRAGMENTATION(x) ((x) << S_FRAGMENTATION)
26789 #define F_FRAGMENTATION    V_FRAGMENTATION(1U)
26790 
26791 #define S_MPSHITTYPE    8
26792 #define V_MPSHITTYPE(x) ((x) << S_MPSHITTYPE)
26793 #define F_MPSHITTYPE    V_MPSHITTYPE(1U)
26794 
26795 #define S_MACMATCH    7
26796 #define V_MACMATCH(x) ((x) << S_MACMATCH)
26797 #define F_MACMATCH    V_MACMATCH(1U)
26798 
26799 #define S_ETHERTYPE    6
26800 #define V_ETHERTYPE(x) ((x) << S_ETHERTYPE)
26801 #define F_ETHERTYPE    V_ETHERTYPE(1U)
26802 
26803 #define S_PROTOCOL    5
26804 #define V_PROTOCOL(x) ((x) << S_PROTOCOL)
26805 #define F_PROTOCOL    V_PROTOCOL(1U)
26806 
26807 #define S_TOS    4
26808 #define V_TOS(x) ((x) << S_TOS)
26809 #define F_TOS    V_TOS(1U)
26810 
26811 #define S_VLAN    3
26812 #define V_VLAN(x) ((x) << S_VLAN)
26813 #define F_VLAN    V_VLAN(1U)
26814 
26815 #define S_VNIC_ID    2
26816 #define V_VNIC_ID(x) ((x) << S_VNIC_ID)
26817 #define F_VNIC_ID    V_VNIC_ID(1U)
26818 
26819 #define S_PORT    1
26820 #define V_PORT(x) ((x) << S_PORT)
26821 #define F_PORT    V_PORT(1U)
26822 
26823 #define S_FCOE    0
26824 #define V_FCOE(x) ((x) << S_FCOE)
26825 #define F_FCOE    V_FCOE(1U)
26826 
26827 #define S_FILTERMODE    15
26828 #define V_FILTERMODE(x) ((x) << S_FILTERMODE)
26829 #define F_FILTERMODE    V_FILTERMODE(1U)
26830 
26831 #define S_FCOEMASK    14
26832 #define V_FCOEMASK(x) ((x) << S_FCOEMASK)
26833 #define F_FCOEMASK    V_FCOEMASK(1U)
26834 
26835 #define S_SRVRSRAM    13
26836 #define V_SRVRSRAM(x) ((x) << S_SRVRSRAM)
26837 #define F_SRVRSRAM    V_SRVRSRAM(1U)
26838 
26839 #define A_TP_INGRESS_CONFIG 0x141
26840 
26841 #define S_OPAQUE_TYPE    16
26842 #define M_OPAQUE_TYPE    0xffffU
26843 #define V_OPAQUE_TYPE(x) ((x) << S_OPAQUE_TYPE)
26844 #define G_OPAQUE_TYPE(x) (((x) >> S_OPAQUE_TYPE) & M_OPAQUE_TYPE)
26845 
26846 #define S_OPAQUE_RM    15
26847 #define V_OPAQUE_RM(x) ((x) << S_OPAQUE_RM)
26848 #define F_OPAQUE_RM    V_OPAQUE_RM(1U)
26849 
26850 #define S_OPAQUE_HDR_SIZE    14
26851 #define V_OPAQUE_HDR_SIZE(x) ((x) << S_OPAQUE_HDR_SIZE)
26852 #define F_OPAQUE_HDR_SIZE    V_OPAQUE_HDR_SIZE(1U)
26853 
26854 #define S_OPAQUE_RM_MAC_IN_MAC    13
26855 #define V_OPAQUE_RM_MAC_IN_MAC(x) ((x) << S_OPAQUE_RM_MAC_IN_MAC)
26856 #define F_OPAQUE_RM_MAC_IN_MAC    V_OPAQUE_RM_MAC_IN_MAC(1U)
26857 
26858 #define S_FCOE_TARGET    12
26859 #define V_FCOE_TARGET(x) ((x) << S_FCOE_TARGET)
26860 #define F_FCOE_TARGET    V_FCOE_TARGET(1U)
26861 
26862 #define S_VNIC    11
26863 #define V_VNIC(x) ((x) << S_VNIC)
26864 #define F_VNIC    V_VNIC(1U)
26865 
26866 #define S_CSUM_HAS_PSEUDO_HDR    10
26867 #define V_CSUM_HAS_PSEUDO_HDR(x) ((x) << S_CSUM_HAS_PSEUDO_HDR)
26868 #define F_CSUM_HAS_PSEUDO_HDR    V_CSUM_HAS_PSEUDO_HDR(1U)
26869 
26870 #define S_RM_OVLAN    9
26871 #define V_RM_OVLAN(x) ((x) << S_RM_OVLAN)
26872 #define F_RM_OVLAN    V_RM_OVLAN(1U)
26873 
26874 #define S_LOOKUPEVERYPKT    8
26875 #define V_LOOKUPEVERYPKT(x) ((x) << S_LOOKUPEVERYPKT)
26876 #define F_LOOKUPEVERYPKT    V_LOOKUPEVERYPKT(1U)
26877 
26878 #define S_IPV6_EXT_HDR_SKIP    0
26879 #define M_IPV6_EXT_HDR_SKIP    0xffU
26880 #define V_IPV6_EXT_HDR_SKIP(x) ((x) << S_IPV6_EXT_HDR_SKIP)
26881 #define G_IPV6_EXT_HDR_SKIP(x) (((x) >> S_IPV6_EXT_HDR_SKIP) & M_IPV6_EXT_HDR_SKIP)
26882 
26883 #define S_FRAG_LEN_MOD8_COMPAT    12
26884 #define V_FRAG_LEN_MOD8_COMPAT(x) ((x) << S_FRAG_LEN_MOD8_COMPAT)
26885 #define F_FRAG_LEN_MOD8_COMPAT    V_FRAG_LEN_MOD8_COMPAT(1U)
26886 
26887 #define S_USE_ENC_IDX    13
26888 #define V_USE_ENC_IDX(x) ((x) << S_USE_ENC_IDX)
26889 #define F_USE_ENC_IDX    V_USE_ENC_IDX(1U)
26890 
26891 #define A_TP_TX_DROP_CFG_CH2 0x142
26892 #define A_TP_TX_DROP_CFG_CH3 0x143
26893 #define A_TP_EGRESS_CONFIG 0x145
26894 
26895 #define S_REWRITEFORCETOSIZE    0
26896 #define V_REWRITEFORCETOSIZE(x) ((x) << S_REWRITEFORCETOSIZE)
26897 #define F_REWRITEFORCETOSIZE    V_REWRITEFORCETOSIZE(1U)
26898 
26899 #define A_TP_INGRESS_CONFIG2 0x145
26900 
26901 #define S_IPV6_UDP_CSUM_COMPAT    31
26902 #define V_IPV6_UDP_CSUM_COMPAT(x) ((x) << S_IPV6_UDP_CSUM_COMPAT)
26903 #define F_IPV6_UDP_CSUM_COMPAT    V_IPV6_UDP_CSUM_COMPAT(1U)
26904 
26905 #define S_VNTAGPLDENABLE    30
26906 #define V_VNTAGPLDENABLE(x) ((x) << S_VNTAGPLDENABLE)
26907 #define F_VNTAGPLDENABLE    V_VNTAGPLDENABLE(1U)
26908 
26909 #define S_TCP_PLD_FILTER_OFFSET    20
26910 #define M_TCP_PLD_FILTER_OFFSET    0x3ffU
26911 #define V_TCP_PLD_FILTER_OFFSET(x) ((x) << S_TCP_PLD_FILTER_OFFSET)
26912 #define G_TCP_PLD_FILTER_OFFSET(x) (((x) >> S_TCP_PLD_FILTER_OFFSET) & M_TCP_PLD_FILTER_OFFSET)
26913 
26914 #define S_UDP_PLD_FILTER_OFFSET    10
26915 #define M_UDP_PLD_FILTER_OFFSET    0x3ffU
26916 #define V_UDP_PLD_FILTER_OFFSET(x) ((x) << S_UDP_PLD_FILTER_OFFSET)
26917 #define G_UDP_PLD_FILTER_OFFSET(x) (((x) >> S_UDP_PLD_FILTER_OFFSET) & M_UDP_PLD_FILTER_OFFSET)
26918 
26919 #define S_TNL_PLD_FILTER_OFFSET    0
26920 #define M_TNL_PLD_FILTER_OFFSET    0x3ffU
26921 #define V_TNL_PLD_FILTER_OFFSET(x) ((x) << S_TNL_PLD_FILTER_OFFSET)
26922 #define G_TNL_PLD_FILTER_OFFSET(x) (((x) >> S_TNL_PLD_FILTER_OFFSET) & M_TNL_PLD_FILTER_OFFSET)
26923 
26924 #define A_TP_EHDR_CONFIG_LO 0x146
26925 
26926 #define S_CPLLIMIT    24
26927 #define M_CPLLIMIT    0xffU
26928 #define V_CPLLIMIT(x) ((x) << S_CPLLIMIT)
26929 #define G_CPLLIMIT(x) (((x) >> S_CPLLIMIT) & M_CPLLIMIT)
26930 
26931 #define S_ETHLIMIT    16
26932 #define M_ETHLIMIT    0xffU
26933 #define V_ETHLIMIT(x) ((x) << S_ETHLIMIT)
26934 #define G_ETHLIMIT(x) (((x) >> S_ETHLIMIT) & M_ETHLIMIT)
26935 
26936 #define S_IPLIMIT    8
26937 #define M_IPLIMIT    0xffU
26938 #define V_IPLIMIT(x) ((x) << S_IPLIMIT)
26939 #define G_IPLIMIT(x) (((x) >> S_IPLIMIT) & M_IPLIMIT)
26940 
26941 #define S_TCPLIMIT    0
26942 #define M_TCPLIMIT    0xffU
26943 #define V_TCPLIMIT(x) ((x) << S_TCPLIMIT)
26944 #define G_TCPLIMIT(x) (((x) >> S_TCPLIMIT) & M_TCPLIMIT)
26945 
26946 #define A_TP_EHDR_CONFIG_HI 0x147
26947 #define A_TP_DBG_ESIDE_INT 0x148
26948 
26949 #define S_ERXSOP2X    28
26950 #define M_ERXSOP2X    0xfU
26951 #define V_ERXSOP2X(x) ((x) << S_ERXSOP2X)
26952 #define G_ERXSOP2X(x) (((x) >> S_ERXSOP2X) & M_ERXSOP2X)
26953 
26954 #define S_ERXEOP2X    24
26955 #define M_ERXEOP2X    0xfU
26956 #define V_ERXEOP2X(x) ((x) << S_ERXEOP2X)
26957 #define G_ERXEOP2X(x) (((x) >> S_ERXEOP2X) & M_ERXEOP2X)
26958 
26959 #define S_ERXVALID2X    20
26960 #define M_ERXVALID2X    0xfU
26961 #define V_ERXVALID2X(x) ((x) << S_ERXVALID2X)
26962 #define G_ERXVALID2X(x) (((x) >> S_ERXVALID2X) & M_ERXVALID2X)
26963 
26964 #define S_ERXAFULL2X    16
26965 #define M_ERXAFULL2X    0xfU
26966 #define V_ERXAFULL2X(x) ((x) << S_ERXAFULL2X)
26967 #define G_ERXAFULL2X(x) (((x) >> S_ERXAFULL2X) & M_ERXAFULL2X)
26968 
26969 #define S_PLD2XTXVALID    12
26970 #define M_PLD2XTXVALID    0xfU
26971 #define V_PLD2XTXVALID(x) ((x) << S_PLD2XTXVALID)
26972 #define G_PLD2XTXVALID(x) (((x) >> S_PLD2XTXVALID) & M_PLD2XTXVALID)
26973 
26974 #define S_PLD2XTXAFULL    8
26975 #define M_PLD2XTXAFULL    0xfU
26976 #define V_PLD2XTXAFULL(x) ((x) << S_PLD2XTXAFULL)
26977 #define G_PLD2XTXAFULL(x) (((x) >> S_PLD2XTXAFULL) & M_PLD2XTXAFULL)
26978 
26979 #define S_ERRORSRDY    7
26980 #define V_ERRORSRDY(x) ((x) << S_ERRORSRDY)
26981 #define F_ERRORSRDY    V_ERRORSRDY(1U)
26982 
26983 #define S_ERRORDRDY    6
26984 #define V_ERRORDRDY(x) ((x) << S_ERRORDRDY)
26985 #define F_ERRORDRDY    V_ERRORDRDY(1U)
26986 
26987 #define S_TCPOPSRDY    5
26988 #define V_TCPOPSRDY(x) ((x) << S_TCPOPSRDY)
26989 #define F_TCPOPSRDY    V_TCPOPSRDY(1U)
26990 
26991 #define S_TCPOPDRDY    4
26992 #define V_TCPOPDRDY(x) ((x) << S_TCPOPDRDY)
26993 #define F_TCPOPDRDY    V_TCPOPDRDY(1U)
26994 
26995 #define S_PLDTXSRDY    3
26996 #define V_PLDTXSRDY(x) ((x) << S_PLDTXSRDY)
26997 #define F_PLDTXSRDY    V_PLDTXSRDY(1U)
26998 
26999 #define S_PLDTXDRDY    2
27000 #define V_PLDTXDRDY(x) ((x) << S_PLDTXDRDY)
27001 #define F_PLDTXDRDY    V_PLDTXDRDY(1U)
27002 
27003 #define S_TCPOPTTXVALID    1
27004 #define V_TCPOPTTXVALID(x) ((x) << S_TCPOPTTXVALID)
27005 #define F_TCPOPTTXVALID    V_TCPOPTTXVALID(1U)
27006 
27007 #define S_TCPOPTTXFULL    0
27008 #define V_TCPOPTTXFULL(x) ((x) << S_TCPOPTTXFULL)
27009 #define F_TCPOPTTXFULL    V_TCPOPTTXFULL(1U)
27010 
27011 #define S_PKTATTRSRDY    3
27012 #define V_PKTATTRSRDY(x) ((x) << S_PKTATTRSRDY)
27013 #define F_PKTATTRSRDY    V_PKTATTRSRDY(1U)
27014 
27015 #define S_PKTATTRDRDY    2
27016 #define V_PKTATTRDRDY(x) ((x) << S_PKTATTRDRDY)
27017 #define F_PKTATTRDRDY    V_PKTATTRDRDY(1U)
27018 
27019 #define A_TP_DBG_ESIDE_DEMUX 0x149
27020 
27021 #define S_EALLDONE    28
27022 #define M_EALLDONE    0xfU
27023 #define V_EALLDONE(x) ((x) << S_EALLDONE)
27024 #define G_EALLDONE(x) (((x) >> S_EALLDONE) & M_EALLDONE)
27025 
27026 #define S_EFIFOPLDDONE    24
27027 #define M_EFIFOPLDDONE    0xfU
27028 #define V_EFIFOPLDDONE(x) ((x) << S_EFIFOPLDDONE)
27029 #define G_EFIFOPLDDONE(x) (((x) >> S_EFIFOPLDDONE) & M_EFIFOPLDDONE)
27030 
27031 #define S_EDBDONE    20
27032 #define M_EDBDONE    0xfU
27033 #define V_EDBDONE(x) ((x) << S_EDBDONE)
27034 #define G_EDBDONE(x) (((x) >> S_EDBDONE) & M_EDBDONE)
27035 
27036 #define S_EISSFIFODONE    16
27037 #define M_EISSFIFODONE    0xfU
27038 #define V_EISSFIFODONE(x) ((x) << S_EISSFIFODONE)
27039 #define G_EISSFIFODONE(x) (((x) >> S_EISSFIFODONE) & M_EISSFIFODONE)
27040 
27041 #define S_EACKERRFIFODONE    12
27042 #define M_EACKERRFIFODONE    0xfU
27043 #define V_EACKERRFIFODONE(x) ((x) << S_EACKERRFIFODONE)
27044 #define G_EACKERRFIFODONE(x) (((x) >> S_EACKERRFIFODONE) & M_EACKERRFIFODONE)
27045 
27046 #define S_EFIFOERRORDONE    8
27047 #define M_EFIFOERRORDONE    0xfU
27048 #define V_EFIFOERRORDONE(x) ((x) << S_EFIFOERRORDONE)
27049 #define G_EFIFOERRORDONE(x) (((x) >> S_EFIFOERRORDONE) & M_EFIFOERRORDONE)
27050 
27051 #define S_ERXPKTATTRFIFOFDONE    4
27052 #define M_ERXPKTATTRFIFOFDONE    0xfU
27053 #define V_ERXPKTATTRFIFOFDONE(x) ((x) << S_ERXPKTATTRFIFOFDONE)
27054 #define G_ERXPKTATTRFIFOFDONE(x) (((x) >> S_ERXPKTATTRFIFOFDONE) & M_ERXPKTATTRFIFOFDONE)
27055 
27056 #define S_ETCPOPDONE    0
27057 #define M_ETCPOPDONE    0xfU
27058 #define V_ETCPOPDONE(x) ((x) << S_ETCPOPDONE)
27059 #define G_ETCPOPDONE(x) (((x) >> S_ETCPOPDONE) & M_ETCPOPDONE)
27060 
27061 #define A_TP_DBG_ESIDE_IN0 0x14a
27062 
27063 #define S_RXVALID    31
27064 #define V_RXVALID(x) ((x) << S_RXVALID)
27065 #define F_RXVALID    V_RXVALID(1U)
27066 
27067 #define S_RXFULL    30
27068 #define V_RXFULL(x) ((x) << S_RXFULL)
27069 #define F_RXFULL    V_RXFULL(1U)
27070 
27071 #define S_RXSOCP    29
27072 #define V_RXSOCP(x) ((x) << S_RXSOCP)
27073 #define F_RXSOCP    V_RXSOCP(1U)
27074 
27075 #define S_RXEOP    28
27076 #define V_RXEOP(x) ((x) << S_RXEOP)
27077 #define F_RXEOP    V_RXEOP(1U)
27078 
27079 #define S_RXVALID_I    27
27080 #define V_RXVALID_I(x) ((x) << S_RXVALID_I)
27081 #define F_RXVALID_I    V_RXVALID_I(1U)
27082 
27083 #define S_RXFULL_I    26
27084 #define V_RXFULL_I(x) ((x) << S_RXFULL_I)
27085 #define F_RXFULL_I    V_RXFULL_I(1U)
27086 
27087 #define S_RXSOCP_I    25
27088 #define V_RXSOCP_I(x) ((x) << S_RXSOCP_I)
27089 #define F_RXSOCP_I    V_RXSOCP_I(1U)
27090 
27091 #define S_RXEOP_I    24
27092 #define V_RXEOP_I(x) ((x) << S_RXEOP_I)
27093 #define F_RXEOP_I    V_RXEOP_I(1U)
27094 
27095 #define S_RXVALID_I2    23
27096 #define V_RXVALID_I2(x) ((x) << S_RXVALID_I2)
27097 #define F_RXVALID_I2    V_RXVALID_I2(1U)
27098 
27099 #define S_RXFULL_I2    22
27100 #define V_RXFULL_I2(x) ((x) << S_RXFULL_I2)
27101 #define F_RXFULL_I2    V_RXFULL_I2(1U)
27102 
27103 #define S_RXSOCP_I2    21
27104 #define V_RXSOCP_I2(x) ((x) << S_RXSOCP_I2)
27105 #define F_RXSOCP_I2    V_RXSOCP_I2(1U)
27106 
27107 #define S_RXEOP_I2    20
27108 #define V_RXEOP_I2(x) ((x) << S_RXEOP_I2)
27109 #define F_RXEOP_I2    V_RXEOP_I2(1U)
27110 
27111 #define S_CT_MPA_TXVALID_FIFO    19
27112 #define V_CT_MPA_TXVALID_FIFO(x) ((x) << S_CT_MPA_TXVALID_FIFO)
27113 #define F_CT_MPA_TXVALID_FIFO    V_CT_MPA_TXVALID_FIFO(1U)
27114 
27115 #define S_CT_MPA_TXFULL_FIFO    18
27116 #define V_CT_MPA_TXFULL_FIFO(x) ((x) << S_CT_MPA_TXFULL_FIFO)
27117 #define F_CT_MPA_TXFULL_FIFO    V_CT_MPA_TXFULL_FIFO(1U)
27118 
27119 #define S_CT_MPA_TXVALID    17
27120 #define V_CT_MPA_TXVALID(x) ((x) << S_CT_MPA_TXVALID)
27121 #define F_CT_MPA_TXVALID    V_CT_MPA_TXVALID(1U)
27122 
27123 #define S_CT_MPA_TXFULL    16
27124 #define V_CT_MPA_TXFULL(x) ((x) << S_CT_MPA_TXFULL)
27125 #define F_CT_MPA_TXFULL    V_CT_MPA_TXFULL(1U)
27126 
27127 #define S_RXVALID_BUF    15
27128 #define V_RXVALID_BUF(x) ((x) << S_RXVALID_BUF)
27129 #define F_RXVALID_BUF    V_RXVALID_BUF(1U)
27130 
27131 #define S_RXFULL_BUF    14
27132 #define V_RXFULL_BUF(x) ((x) << S_RXFULL_BUF)
27133 #define F_RXFULL_BUF    V_RXFULL_BUF(1U)
27134 
27135 #define S_PLD_TXVALID    13
27136 #define V_PLD_TXVALID(x) ((x) << S_PLD_TXVALID)
27137 #define F_PLD_TXVALID    V_PLD_TXVALID(1U)
27138 
27139 #define S_PLD_TXFULL    12
27140 #define V_PLD_TXFULL(x) ((x) << S_PLD_TXFULL)
27141 #define F_PLD_TXFULL    V_PLD_TXFULL(1U)
27142 
27143 #define S_ISS_FIFO_SRDY    11
27144 #define V_ISS_FIFO_SRDY(x) ((x) << S_ISS_FIFO_SRDY)
27145 #define F_ISS_FIFO_SRDY    V_ISS_FIFO_SRDY(1U)
27146 
27147 #define S_ISS_FIFO_DRDY    10
27148 #define V_ISS_FIFO_DRDY(x) ((x) << S_ISS_FIFO_DRDY)
27149 #define F_ISS_FIFO_DRDY    V_ISS_FIFO_DRDY(1U)
27150 
27151 #define S_CT_TCP_OP_ISS_SRDY    9
27152 #define V_CT_TCP_OP_ISS_SRDY(x) ((x) << S_CT_TCP_OP_ISS_SRDY)
27153 #define F_CT_TCP_OP_ISS_SRDY    V_CT_TCP_OP_ISS_SRDY(1U)
27154 
27155 #define S_CT_TCP_OP_ISS_DRDY    8
27156 #define V_CT_TCP_OP_ISS_DRDY(x) ((x) << S_CT_TCP_OP_ISS_DRDY)
27157 #define F_CT_TCP_OP_ISS_DRDY    V_CT_TCP_OP_ISS_DRDY(1U)
27158 
27159 #define S_P2CSUMERROR_SRDY    7
27160 #define V_P2CSUMERROR_SRDY(x) ((x) << S_P2CSUMERROR_SRDY)
27161 #define F_P2CSUMERROR_SRDY    V_P2CSUMERROR_SRDY(1U)
27162 
27163 #define S_P2CSUMERROR_DRDY    6
27164 #define V_P2CSUMERROR_DRDY(x) ((x) << S_P2CSUMERROR_DRDY)
27165 #define F_P2CSUMERROR_DRDY    V_P2CSUMERROR_DRDY(1U)
27166 
27167 #define S_FIFO_ERROR_SRDY    5
27168 #define V_FIFO_ERROR_SRDY(x) ((x) << S_FIFO_ERROR_SRDY)
27169 #define F_FIFO_ERROR_SRDY    V_FIFO_ERROR_SRDY(1U)
27170 
27171 #define S_FIFO_ERROR_DRDY    4
27172 #define V_FIFO_ERROR_DRDY(x) ((x) << S_FIFO_ERROR_DRDY)
27173 #define F_FIFO_ERROR_DRDY    V_FIFO_ERROR_DRDY(1U)
27174 
27175 #define S_PLD_SRDY    3
27176 #define V_PLD_SRDY(x) ((x) << S_PLD_SRDY)
27177 #define F_PLD_SRDY    V_PLD_SRDY(1U)
27178 
27179 #define S_PLD_DRDY    2
27180 #define V_PLD_DRDY(x) ((x) << S_PLD_DRDY)
27181 #define F_PLD_DRDY    V_PLD_DRDY(1U)
27182 
27183 #define S_RX_PKT_ATTR_SRDY    1
27184 #define V_RX_PKT_ATTR_SRDY(x) ((x) << S_RX_PKT_ATTR_SRDY)
27185 #define F_RX_PKT_ATTR_SRDY    V_RX_PKT_ATTR_SRDY(1U)
27186 
27187 #define S_RX_PKT_ATTR_DRDY    0
27188 #define V_RX_PKT_ATTR_DRDY(x) ((x) << S_RX_PKT_ATTR_DRDY)
27189 #define F_RX_PKT_ATTR_DRDY    V_RX_PKT_ATTR_DRDY(1U)
27190 
27191 #define S_RXRUNT    25
27192 #define V_RXRUNT(x) ((x) << S_RXRUNT)
27193 #define F_RXRUNT    V_RXRUNT(1U)
27194 
27195 #define S_RXRUNTPARSER    24
27196 #define V_RXRUNTPARSER(x) ((x) << S_RXRUNTPARSER)
27197 #define F_RXRUNTPARSER    V_RXRUNTPARSER(1U)
27198 
27199 #define S_ERROR_SRDY    5
27200 #define V_ERROR_SRDY(x) ((x) << S_ERROR_SRDY)
27201 #define F_ERROR_SRDY    V_ERROR_SRDY(1U)
27202 
27203 #define S_ERROR_DRDY    4
27204 #define V_ERROR_DRDY(x) ((x) << S_ERROR_DRDY)
27205 #define F_ERROR_DRDY    V_ERROR_DRDY(1U)
27206 
27207 #define A_TP_DBG_ESIDE_IN1 0x14b
27208 #define A_TP_DBG_ESIDE_IN2 0x14c
27209 #define A_TP_DBG_ESIDE_IN3 0x14d
27210 #define A_TP_DBG_ESIDE_FRM 0x14e
27211 
27212 #define S_ERX2XERROR    28
27213 #define M_ERX2XERROR    0xfU
27214 #define V_ERX2XERROR(x) ((x) << S_ERX2XERROR)
27215 #define G_ERX2XERROR(x) (((x) >> S_ERX2XERROR) & M_ERX2XERROR)
27216 
27217 #define S_EPLDTX2XERROR    24
27218 #define M_EPLDTX2XERROR    0xfU
27219 #define V_EPLDTX2XERROR(x) ((x) << S_EPLDTX2XERROR)
27220 #define G_EPLDTX2XERROR(x) (((x) >> S_EPLDTX2XERROR) & M_EPLDTX2XERROR)
27221 
27222 #define S_ETXERROR    20
27223 #define M_ETXERROR    0xfU
27224 #define V_ETXERROR(x) ((x) << S_ETXERROR)
27225 #define G_ETXERROR(x) (((x) >> S_ETXERROR) & M_ETXERROR)
27226 
27227 #define S_EPLDRXERROR    16
27228 #define M_EPLDRXERROR    0xfU
27229 #define V_EPLDRXERROR(x) ((x) << S_EPLDRXERROR)
27230 #define G_EPLDRXERROR(x) (((x) >> S_EPLDRXERROR) & M_EPLDRXERROR)
27231 
27232 #define S_ERXSIZEERROR3    12
27233 #define M_ERXSIZEERROR3    0xfU
27234 #define V_ERXSIZEERROR3(x) ((x) << S_ERXSIZEERROR3)
27235 #define G_ERXSIZEERROR3(x) (((x) >> S_ERXSIZEERROR3) & M_ERXSIZEERROR3)
27236 
27237 #define S_ERXSIZEERROR2    8
27238 #define M_ERXSIZEERROR2    0xfU
27239 #define V_ERXSIZEERROR2(x) ((x) << S_ERXSIZEERROR2)
27240 #define G_ERXSIZEERROR2(x) (((x) >> S_ERXSIZEERROR2) & M_ERXSIZEERROR2)
27241 
27242 #define S_ERXSIZEERROR1    4
27243 #define M_ERXSIZEERROR1    0xfU
27244 #define V_ERXSIZEERROR1(x) ((x) << S_ERXSIZEERROR1)
27245 #define G_ERXSIZEERROR1(x) (((x) >> S_ERXSIZEERROR1) & M_ERXSIZEERROR1)
27246 
27247 #define S_ERXSIZEERROR0    0
27248 #define M_ERXSIZEERROR0    0xfU
27249 #define V_ERXSIZEERROR0(x) ((x) << S_ERXSIZEERROR0)
27250 #define G_ERXSIZEERROR0(x) (((x) >> S_ERXSIZEERROR0) & M_ERXSIZEERROR0)
27251 
27252 #define A_TP_DBG_ESIDE_DRP 0x14f
27253 
27254 #define S_RXDROP3    24
27255 #define M_RXDROP3    0xffU
27256 #define V_RXDROP3(x) ((x) << S_RXDROP3)
27257 #define G_RXDROP3(x) (((x) >> S_RXDROP3) & M_RXDROP3)
27258 
27259 #define S_RXDROP2    16
27260 #define M_RXDROP2    0xffU
27261 #define V_RXDROP2(x) ((x) << S_RXDROP2)
27262 #define G_RXDROP2(x) (((x) >> S_RXDROP2) & M_RXDROP2)
27263 
27264 #define S_RXDROP1    8
27265 #define M_RXDROP1    0xffU
27266 #define V_RXDROP1(x) ((x) << S_RXDROP1)
27267 #define G_RXDROP1(x) (((x) >> S_RXDROP1) & M_RXDROP1)
27268 
27269 #define S_RXDROP0    0
27270 #define M_RXDROP0    0xffU
27271 #define V_RXDROP0(x) ((x) << S_RXDROP0)
27272 #define G_RXDROP0(x) (((x) >> S_RXDROP0) & M_RXDROP0)
27273 
27274 #define A_TP_DBG_ESIDE_TX 0x150
27275 
27276 #define S_ETXVALID    4
27277 #define M_ETXVALID    0xfU
27278 #define V_ETXVALID(x) ((x) << S_ETXVALID)
27279 #define G_ETXVALID(x) (((x) >> S_ETXVALID) & M_ETXVALID)
27280 
27281 #define S_ETXFULL    0
27282 #define M_ETXFULL    0xfU
27283 #define V_ETXFULL(x) ((x) << S_ETXFULL)
27284 #define G_ETXFULL(x) (((x) >> S_ETXFULL) & M_ETXFULL)
27285 
27286 #define S_TXERRORCNT    8
27287 #define M_TXERRORCNT    0xffffffU
27288 #define V_TXERRORCNT(x) ((x) << S_TXERRORCNT)
27289 #define G_TXERRORCNT(x) (((x) >> S_TXERRORCNT) & M_TXERRORCNT)
27290 
27291 #define A_TP_ESIDE_SVID_MASK 0x151
27292 #define A_TP_ESIDE_DVID_MASK 0x152
27293 #define A_TP_ESIDE_ALIGN_MASK 0x153
27294 
27295 #define S_USE_LOOP_BIT    24
27296 #define V_USE_LOOP_BIT(x) ((x) << S_USE_LOOP_BIT)
27297 #define F_USE_LOOP_BIT    V_USE_LOOP_BIT(1U)
27298 
27299 #define S_LOOP_OFFSET    16
27300 #define M_LOOP_OFFSET    0xffU
27301 #define V_LOOP_OFFSET(x) ((x) << S_LOOP_OFFSET)
27302 #define G_LOOP_OFFSET(x) (((x) >> S_LOOP_OFFSET) & M_LOOP_OFFSET)
27303 
27304 #define S_DVID_ID_OFFSET    8
27305 #define M_DVID_ID_OFFSET    0xffU
27306 #define V_DVID_ID_OFFSET(x) ((x) << S_DVID_ID_OFFSET)
27307 #define G_DVID_ID_OFFSET(x) (((x) >> S_DVID_ID_OFFSET) & M_DVID_ID_OFFSET)
27308 
27309 #define S_SVID_ID_OFFSET    0
27310 #define M_SVID_ID_OFFSET    0xffU
27311 #define V_SVID_ID_OFFSET(x) ((x) << S_SVID_ID_OFFSET)
27312 #define G_SVID_ID_OFFSET(x) (((x) >> S_SVID_ID_OFFSET) & M_SVID_ID_OFFSET)
27313 
27314 #define A_TP_DBG_ESIDE_OP 0x154
27315 
27316 #define S_OPT_PARSER_FATAL_CHANNEL0    29
27317 #define V_OPT_PARSER_FATAL_CHANNEL0(x) ((x) << S_OPT_PARSER_FATAL_CHANNEL0)
27318 #define F_OPT_PARSER_FATAL_CHANNEL0    V_OPT_PARSER_FATAL_CHANNEL0(1U)
27319 
27320 #define S_OPT_PARSER_BUSY_CHANNEL0    28
27321 #define V_OPT_PARSER_BUSY_CHANNEL0(x) ((x) << S_OPT_PARSER_BUSY_CHANNEL0)
27322 #define F_OPT_PARSER_BUSY_CHANNEL0    V_OPT_PARSER_BUSY_CHANNEL0(1U)
27323 
27324 #define S_OPT_PARSER_ITCP_STATE_CHANNEL0    26
27325 #define M_OPT_PARSER_ITCP_STATE_CHANNEL0    0x3U
27326 #define V_OPT_PARSER_ITCP_STATE_CHANNEL0(x) ((x) << S_OPT_PARSER_ITCP_STATE_CHANNEL0)
27327 #define G_OPT_PARSER_ITCP_STATE_CHANNEL0(x) (((x) >> S_OPT_PARSER_ITCP_STATE_CHANNEL0) & M_OPT_PARSER_ITCP_STATE_CHANNEL0)
27328 
27329 #define S_OPT_PARSER_OTK_STATE_CHANNEL0    24
27330 #define M_OPT_PARSER_OTK_STATE_CHANNEL0    0x3U
27331 #define V_OPT_PARSER_OTK_STATE_CHANNEL0(x) ((x) << S_OPT_PARSER_OTK_STATE_CHANNEL0)
27332 #define G_OPT_PARSER_OTK_STATE_CHANNEL0(x) (((x) >> S_OPT_PARSER_OTK_STATE_CHANNEL0) & M_OPT_PARSER_OTK_STATE_CHANNEL0)
27333 
27334 #define S_OPT_PARSER_FATAL_CHANNEL1    21
27335 #define V_OPT_PARSER_FATAL_CHANNEL1(x) ((x) << S_OPT_PARSER_FATAL_CHANNEL1)
27336 #define F_OPT_PARSER_FATAL_CHANNEL1    V_OPT_PARSER_FATAL_CHANNEL1(1U)
27337 
27338 #define S_OPT_PARSER_BUSY_CHANNEL1    20
27339 #define V_OPT_PARSER_BUSY_CHANNEL1(x) ((x) << S_OPT_PARSER_BUSY_CHANNEL1)
27340 #define F_OPT_PARSER_BUSY_CHANNEL1    V_OPT_PARSER_BUSY_CHANNEL1(1U)
27341 
27342 #define S_OPT_PARSER_ITCP_STATE_CHANNEL1    18
27343 #define M_OPT_PARSER_ITCP_STATE_CHANNEL1    0x3U
27344 #define V_OPT_PARSER_ITCP_STATE_CHANNEL1(x) ((x) << S_OPT_PARSER_ITCP_STATE_CHANNEL1)
27345 #define G_OPT_PARSER_ITCP_STATE_CHANNEL1(x) (((x) >> S_OPT_PARSER_ITCP_STATE_CHANNEL1) & M_OPT_PARSER_ITCP_STATE_CHANNEL1)
27346 
27347 #define S_OPT_PARSER_OTK_STATE_CHANNEL1    16
27348 #define M_OPT_PARSER_OTK_STATE_CHANNEL1    0x3U
27349 #define V_OPT_PARSER_OTK_STATE_CHANNEL1(x) ((x) << S_OPT_PARSER_OTK_STATE_CHANNEL1)
27350 #define G_OPT_PARSER_OTK_STATE_CHANNEL1(x) (((x) >> S_OPT_PARSER_OTK_STATE_CHANNEL1) & M_OPT_PARSER_OTK_STATE_CHANNEL1)
27351 
27352 #define S_OPT_PARSER_FATAL_CHANNEL2    13
27353 #define V_OPT_PARSER_FATAL_CHANNEL2(x) ((x) << S_OPT_PARSER_FATAL_CHANNEL2)
27354 #define F_OPT_PARSER_FATAL_CHANNEL2    V_OPT_PARSER_FATAL_CHANNEL2(1U)
27355 
27356 #define S_OPT_PARSER_BUSY_CHANNEL2    12
27357 #define V_OPT_PARSER_BUSY_CHANNEL2(x) ((x) << S_OPT_PARSER_BUSY_CHANNEL2)
27358 #define F_OPT_PARSER_BUSY_CHANNEL2    V_OPT_PARSER_BUSY_CHANNEL2(1U)
27359 
27360 #define S_OPT_PARSER_ITCP_STATE_CHANNEL2    10
27361 #define M_OPT_PARSER_ITCP_STATE_CHANNEL2    0x3U
27362 #define V_OPT_PARSER_ITCP_STATE_CHANNEL2(x) ((x) << S_OPT_PARSER_ITCP_STATE_CHANNEL2)
27363 #define G_OPT_PARSER_ITCP_STATE_CHANNEL2(x) (((x) >> S_OPT_PARSER_ITCP_STATE_CHANNEL2) & M_OPT_PARSER_ITCP_STATE_CHANNEL2)
27364 
27365 #define S_OPT_PARSER_OTK_STATE_CHANNEL2    8
27366 #define M_OPT_PARSER_OTK_STATE_CHANNEL2    0x3U
27367 #define V_OPT_PARSER_OTK_STATE_CHANNEL2(x) ((x) << S_OPT_PARSER_OTK_STATE_CHANNEL2)
27368 #define G_OPT_PARSER_OTK_STATE_CHANNEL2(x) (((x) >> S_OPT_PARSER_OTK_STATE_CHANNEL2) & M_OPT_PARSER_OTK_STATE_CHANNEL2)
27369 
27370 #define S_OPT_PARSER_FATAL_CHANNEL3    5
27371 #define V_OPT_PARSER_FATAL_CHANNEL3(x) ((x) << S_OPT_PARSER_FATAL_CHANNEL3)
27372 #define F_OPT_PARSER_FATAL_CHANNEL3    V_OPT_PARSER_FATAL_CHANNEL3(1U)
27373 
27374 #define S_OPT_PARSER_BUSY_CHANNEL3    4
27375 #define V_OPT_PARSER_BUSY_CHANNEL3(x) ((x) << S_OPT_PARSER_BUSY_CHANNEL3)
27376 #define F_OPT_PARSER_BUSY_CHANNEL3    V_OPT_PARSER_BUSY_CHANNEL3(1U)
27377 
27378 #define S_OPT_PARSER_ITCP_STATE_CHANNEL3    2
27379 #define M_OPT_PARSER_ITCP_STATE_CHANNEL3    0x3U
27380 #define V_OPT_PARSER_ITCP_STATE_CHANNEL3(x) ((x) << S_OPT_PARSER_ITCP_STATE_CHANNEL3)
27381 #define G_OPT_PARSER_ITCP_STATE_CHANNEL3(x) (((x) >> S_OPT_PARSER_ITCP_STATE_CHANNEL3) & M_OPT_PARSER_ITCP_STATE_CHANNEL3)
27382 
27383 #define S_OPT_PARSER_OTK_STATE_CHANNEL3    0
27384 #define M_OPT_PARSER_OTK_STATE_CHANNEL3    0x3U
27385 #define V_OPT_PARSER_OTK_STATE_CHANNEL3(x) ((x) << S_OPT_PARSER_OTK_STATE_CHANNEL3)
27386 #define G_OPT_PARSER_OTK_STATE_CHANNEL3(x) (((x) >> S_OPT_PARSER_OTK_STATE_CHANNEL3) & M_OPT_PARSER_OTK_STATE_CHANNEL3)
27387 
27388 #define A_TP_DBG_ESIDE_OP_ALT 0x155
27389 
27390 #define S_OPT_PARSER_PSTATE_FATAL_CHANNEL0    29
27391 #define V_OPT_PARSER_PSTATE_FATAL_CHANNEL0(x) ((x) << S_OPT_PARSER_PSTATE_FATAL_CHANNEL0)
27392 #define F_OPT_PARSER_PSTATE_FATAL_CHANNEL0    V_OPT_PARSER_PSTATE_FATAL_CHANNEL0(1U)
27393 
27394 #define S_OPT_PARSER_PSTATE_ERRNO_CHANNEL0    24
27395 #define M_OPT_PARSER_PSTATE_ERRNO_CHANNEL0    0x1fU
27396 #define V_OPT_PARSER_PSTATE_ERRNO_CHANNEL0(x) ((x) << S_OPT_PARSER_PSTATE_ERRNO_CHANNEL0)
27397 #define G_OPT_PARSER_PSTATE_ERRNO_CHANNEL0(x) (((x) >> S_OPT_PARSER_PSTATE_ERRNO_CHANNEL0) & M_OPT_PARSER_PSTATE_ERRNO_CHANNEL0)
27398 
27399 #define S_OPT_PARSER_PSTATE_FATAL_CHANNEL1    21
27400 #define V_OPT_PARSER_PSTATE_FATAL_CHANNEL1(x) ((x) << S_OPT_PARSER_PSTATE_FATAL_CHANNEL1)
27401 #define F_OPT_PARSER_PSTATE_FATAL_CHANNEL1    V_OPT_PARSER_PSTATE_FATAL_CHANNEL1(1U)
27402 
27403 #define S_OPT_PARSER_PSTATE_ERRNO_CHANNEL1    16
27404 #define M_OPT_PARSER_PSTATE_ERRNO_CHANNEL1    0x1fU
27405 #define V_OPT_PARSER_PSTATE_ERRNO_CHANNEL1(x) ((x) << S_OPT_PARSER_PSTATE_ERRNO_CHANNEL1)
27406 #define G_OPT_PARSER_PSTATE_ERRNO_CHANNEL1(x) (((x) >> S_OPT_PARSER_PSTATE_ERRNO_CHANNEL1) & M_OPT_PARSER_PSTATE_ERRNO_CHANNEL1)
27407 
27408 #define S_OPT_PARSER_PSTATE_FATAL_CHANNEL2    13
27409 #define V_OPT_PARSER_PSTATE_FATAL_CHANNEL2(x) ((x) << S_OPT_PARSER_PSTATE_FATAL_CHANNEL2)
27410 #define F_OPT_PARSER_PSTATE_FATAL_CHANNEL2    V_OPT_PARSER_PSTATE_FATAL_CHANNEL2(1U)
27411 
27412 #define S_OPT_PARSER_PSTATE_ERRNO_CHANNEL2    8
27413 #define M_OPT_PARSER_PSTATE_ERRNO_CHANNEL2    0x1fU
27414 #define V_OPT_PARSER_PSTATE_ERRNO_CHANNEL2(x) ((x) << S_OPT_PARSER_PSTATE_ERRNO_CHANNEL2)
27415 #define G_OPT_PARSER_PSTATE_ERRNO_CHANNEL2(x) (((x) >> S_OPT_PARSER_PSTATE_ERRNO_CHANNEL2) & M_OPT_PARSER_PSTATE_ERRNO_CHANNEL2)
27416 
27417 #define S_OPT_PARSER_PSTATE_FATAL_CHANNEL3    5
27418 #define V_OPT_PARSER_PSTATE_FATAL_CHANNEL3(x) ((x) << S_OPT_PARSER_PSTATE_FATAL_CHANNEL3)
27419 #define F_OPT_PARSER_PSTATE_FATAL_CHANNEL3    V_OPT_PARSER_PSTATE_FATAL_CHANNEL3(1U)
27420 
27421 #define S_OPT_PARSER_PSTATE_ERRNO_CHANNEL3    0
27422 #define M_OPT_PARSER_PSTATE_ERRNO_CHANNEL3    0x1fU
27423 #define V_OPT_PARSER_PSTATE_ERRNO_CHANNEL3(x) ((x) << S_OPT_PARSER_PSTATE_ERRNO_CHANNEL3)
27424 #define G_OPT_PARSER_PSTATE_ERRNO_CHANNEL3(x) (((x) >> S_OPT_PARSER_PSTATE_ERRNO_CHANNEL3) & M_OPT_PARSER_PSTATE_ERRNO_CHANNEL3)
27425 
27426 #define A_TP_DBG_ESIDE_OP_BUSY 0x156
27427 
27428 #define S_OPT_PARSER_BUSY_VEC_CHANNEL3    24
27429 #define M_OPT_PARSER_BUSY_VEC_CHANNEL3    0xffU
27430 #define V_OPT_PARSER_BUSY_VEC_CHANNEL3(x) ((x) << S_OPT_PARSER_BUSY_VEC_CHANNEL3)
27431 #define G_OPT_PARSER_BUSY_VEC_CHANNEL3(x) (((x) >> S_OPT_PARSER_BUSY_VEC_CHANNEL3) & M_OPT_PARSER_BUSY_VEC_CHANNEL3)
27432 
27433 #define S_OPT_PARSER_BUSY_VEC_CHANNEL2    16
27434 #define M_OPT_PARSER_BUSY_VEC_CHANNEL2    0xffU
27435 #define V_OPT_PARSER_BUSY_VEC_CHANNEL2(x) ((x) << S_OPT_PARSER_BUSY_VEC_CHANNEL2)
27436 #define G_OPT_PARSER_BUSY_VEC_CHANNEL2(x) (((x) >> S_OPT_PARSER_BUSY_VEC_CHANNEL2) & M_OPT_PARSER_BUSY_VEC_CHANNEL2)
27437 
27438 #define S_OPT_PARSER_BUSY_VEC_CHANNEL1    8
27439 #define M_OPT_PARSER_BUSY_VEC_CHANNEL1    0xffU
27440 #define V_OPT_PARSER_BUSY_VEC_CHANNEL1(x) ((x) << S_OPT_PARSER_BUSY_VEC_CHANNEL1)
27441 #define G_OPT_PARSER_BUSY_VEC_CHANNEL1(x) (((x) >> S_OPT_PARSER_BUSY_VEC_CHANNEL1) & M_OPT_PARSER_BUSY_VEC_CHANNEL1)
27442 
27443 #define S_OPT_PARSER_BUSY_VEC_CHANNEL0    0
27444 #define M_OPT_PARSER_BUSY_VEC_CHANNEL0    0xffU
27445 #define V_OPT_PARSER_BUSY_VEC_CHANNEL0(x) ((x) << S_OPT_PARSER_BUSY_VEC_CHANNEL0)
27446 #define G_OPT_PARSER_BUSY_VEC_CHANNEL0(x) (((x) >> S_OPT_PARSER_BUSY_VEC_CHANNEL0) & M_OPT_PARSER_BUSY_VEC_CHANNEL0)
27447 
27448 #define A_TP_DBG_ESIDE_OP_COOKIE 0x157
27449 
27450 #define S_OPT_PARSER_COOKIE_CHANNEL3    24
27451 #define M_OPT_PARSER_COOKIE_CHANNEL3    0xffU
27452 #define V_OPT_PARSER_COOKIE_CHANNEL3(x) ((x) << S_OPT_PARSER_COOKIE_CHANNEL3)
27453 #define G_OPT_PARSER_COOKIE_CHANNEL3(x) (((x) >> S_OPT_PARSER_COOKIE_CHANNEL3) & M_OPT_PARSER_COOKIE_CHANNEL3)
27454 
27455 #define S_OPT_PARSER_COOKIE_CHANNEL2    16
27456 #define M_OPT_PARSER_COOKIE_CHANNEL2    0xffU
27457 #define V_OPT_PARSER_COOKIE_CHANNEL2(x) ((x) << S_OPT_PARSER_COOKIE_CHANNEL2)
27458 #define G_OPT_PARSER_COOKIE_CHANNEL2(x) (((x) >> S_OPT_PARSER_COOKIE_CHANNEL2) & M_OPT_PARSER_COOKIE_CHANNEL2)
27459 
27460 #define S_OPT_PARSER_COOKIE_CHANNEL1    8
27461 #define M_OPT_PARSER_COOKIE_CHANNEL1    0xffU
27462 #define V_OPT_PARSER_COOKIE_CHANNEL1(x) ((x) << S_OPT_PARSER_COOKIE_CHANNEL1)
27463 #define G_OPT_PARSER_COOKIE_CHANNEL1(x) (((x) >> S_OPT_PARSER_COOKIE_CHANNEL1) & M_OPT_PARSER_COOKIE_CHANNEL1)
27464 
27465 #define S_OPT_PARSER_COOKIE_CHANNEL0    0
27466 #define M_OPT_PARSER_COOKIE_CHANNEL0    0xffU
27467 #define V_OPT_PARSER_COOKIE_CHANNEL0(x) ((x) << S_OPT_PARSER_COOKIE_CHANNEL0)
27468 #define G_OPT_PARSER_COOKIE_CHANNEL0(x) (((x) >> S_OPT_PARSER_COOKIE_CHANNEL0) & M_OPT_PARSER_COOKIE_CHANNEL0)
27469 
27470 #define A_TP_DBG_ESIDE_DEMUX_WAIT0 0x158
27471 #define A_TP_DBG_ESIDE_DEMUX_WAIT1 0x159
27472 #define A_TP_DBG_ESIDE_DEMUX_CNT0 0x15a
27473 #define A_TP_DBG_ESIDE_DEMUX_CNT1 0x15b
27474 #define A_TP_ESIDE_CONFIG 0x160
27475 
27476 #define S_VNI_EN    26
27477 #define V_VNI_EN(x) ((x) << S_VNI_EN)
27478 #define F_VNI_EN    V_VNI_EN(1U)
27479 
27480 #define S_ENC_RX_EN    25
27481 #define V_ENC_RX_EN(x) ((x) << S_ENC_RX_EN)
27482 #define F_ENC_RX_EN    V_ENC_RX_EN(1U)
27483 
27484 #define S_TNL_LKP_INNER_SEL    24
27485 #define V_TNL_LKP_INNER_SEL(x) ((x) << S_TNL_LKP_INNER_SEL)
27486 #define F_TNL_LKP_INNER_SEL    V_TNL_LKP_INNER_SEL(1U)
27487 
27488 #define S_ROCEV2UDPPORT    0
27489 #define M_ROCEV2UDPPORT    0xffffU
27490 #define V_ROCEV2UDPPORT(x) ((x) << S_ROCEV2UDPPORT)
27491 #define G_ROCEV2UDPPORT(x) (((x) >> S_ROCEV2UDPPORT) & M_ROCEV2UDPPORT)
27492 
27493 #define A_TP_DBG_CSIDE_RX0 0x230
27494 
27495 #define S_CRXSOPCNT    28
27496 #define M_CRXSOPCNT    0xfU
27497 #define V_CRXSOPCNT(x) ((x) << S_CRXSOPCNT)
27498 #define G_CRXSOPCNT(x) (((x) >> S_CRXSOPCNT) & M_CRXSOPCNT)
27499 
27500 #define S_CRXEOPCNT    24
27501 #define M_CRXEOPCNT    0xfU
27502 #define V_CRXEOPCNT(x) ((x) << S_CRXEOPCNT)
27503 #define G_CRXEOPCNT(x) (((x) >> S_CRXEOPCNT) & M_CRXEOPCNT)
27504 
27505 #define S_CRXPLDSOPCNT    20
27506 #define M_CRXPLDSOPCNT    0xfU
27507 #define V_CRXPLDSOPCNT(x) ((x) << S_CRXPLDSOPCNT)
27508 #define G_CRXPLDSOPCNT(x) (((x) >> S_CRXPLDSOPCNT) & M_CRXPLDSOPCNT)
27509 
27510 #define S_CRXPLDEOPCNT    16
27511 #define M_CRXPLDEOPCNT    0xfU
27512 #define V_CRXPLDEOPCNT(x) ((x) << S_CRXPLDEOPCNT)
27513 #define G_CRXPLDEOPCNT(x) (((x) >> S_CRXPLDEOPCNT) & M_CRXPLDEOPCNT)
27514 
27515 #define S_CRXARBSOPCNT    12
27516 #define M_CRXARBSOPCNT    0xfU
27517 #define V_CRXARBSOPCNT(x) ((x) << S_CRXARBSOPCNT)
27518 #define G_CRXARBSOPCNT(x) (((x) >> S_CRXARBSOPCNT) & M_CRXARBSOPCNT)
27519 
27520 #define S_CRXARBEOPCNT    8
27521 #define M_CRXARBEOPCNT    0xfU
27522 #define V_CRXARBEOPCNT(x) ((x) << S_CRXARBEOPCNT)
27523 #define G_CRXARBEOPCNT(x) (((x) >> S_CRXARBEOPCNT) & M_CRXARBEOPCNT)
27524 
27525 #define S_CRXCPLSOPCNT    4
27526 #define M_CRXCPLSOPCNT    0xfU
27527 #define V_CRXCPLSOPCNT(x) ((x) << S_CRXCPLSOPCNT)
27528 #define G_CRXCPLSOPCNT(x) (((x) >> S_CRXCPLSOPCNT) & M_CRXCPLSOPCNT)
27529 
27530 #define S_CRXCPLEOPCNT    0
27531 #define M_CRXCPLEOPCNT    0xfU
27532 #define V_CRXCPLEOPCNT(x) ((x) << S_CRXCPLEOPCNT)
27533 #define G_CRXCPLEOPCNT(x) (((x) >> S_CRXCPLEOPCNT) & M_CRXCPLEOPCNT)
27534 
27535 #define A_TP_DBG_CSIDE_RX1 0x231
27536 #define A_TP_DBG_CSIDE_RX2 0x232
27537 #define A_TP_DBG_CSIDE_RX3 0x233
27538 #define A_TP_DBG_CSIDE_TX0 0x234
27539 
27540 #define S_TXSOPCNT    28
27541 #define M_TXSOPCNT    0xfU
27542 #define V_TXSOPCNT(x) ((x) << S_TXSOPCNT)
27543 #define G_TXSOPCNT(x) (((x) >> S_TXSOPCNT) & M_TXSOPCNT)
27544 
27545 #define S_TXEOPCNT    24
27546 #define M_TXEOPCNT    0xfU
27547 #define V_TXEOPCNT(x) ((x) << S_TXEOPCNT)
27548 #define G_TXEOPCNT(x) (((x) >> S_TXEOPCNT) & M_TXEOPCNT)
27549 
27550 #define S_TXPLDSOPCNT    20
27551 #define M_TXPLDSOPCNT    0xfU
27552 #define V_TXPLDSOPCNT(x) ((x) << S_TXPLDSOPCNT)
27553 #define G_TXPLDSOPCNT(x) (((x) >> S_TXPLDSOPCNT) & M_TXPLDSOPCNT)
27554 
27555 #define S_TXPLDEOPCNT    16
27556 #define M_TXPLDEOPCNT    0xfU
27557 #define V_TXPLDEOPCNT(x) ((x) << S_TXPLDEOPCNT)
27558 #define G_TXPLDEOPCNT(x) (((x) >> S_TXPLDEOPCNT) & M_TXPLDEOPCNT)
27559 
27560 #define S_TXARBSOPCNT    12
27561 #define M_TXARBSOPCNT    0xfU
27562 #define V_TXARBSOPCNT(x) ((x) << S_TXARBSOPCNT)
27563 #define G_TXARBSOPCNT(x) (((x) >> S_TXARBSOPCNT) & M_TXARBSOPCNT)
27564 
27565 #define S_TXARBEOPCNT    8
27566 #define M_TXARBEOPCNT    0xfU
27567 #define V_TXARBEOPCNT(x) ((x) << S_TXARBEOPCNT)
27568 #define G_TXARBEOPCNT(x) (((x) >> S_TXARBEOPCNT) & M_TXARBEOPCNT)
27569 
27570 #define S_TXCPLSOPCNT    4
27571 #define M_TXCPLSOPCNT    0xfU
27572 #define V_TXCPLSOPCNT(x) ((x) << S_TXCPLSOPCNT)
27573 #define G_TXCPLSOPCNT(x) (((x) >> S_TXCPLSOPCNT) & M_TXCPLSOPCNT)
27574 
27575 #define S_TXCPLEOPCNT    0
27576 #define M_TXCPLEOPCNT    0xfU
27577 #define V_TXCPLEOPCNT(x) ((x) << S_TXCPLEOPCNT)
27578 #define G_TXCPLEOPCNT(x) (((x) >> S_TXCPLEOPCNT) & M_TXCPLEOPCNT)
27579 
27580 #define A_TP_DBG_CSIDE_TX1 0x235
27581 #define A_TP_DBG_CSIDE_TX2 0x236
27582 #define A_TP_DBG_CSIDE_TX3 0x237
27583 #define A_TP_DBG_CSIDE_FIFO0 0x238
27584 
27585 #define S_PLD_RXZEROP_SRDY1    31
27586 #define V_PLD_RXZEROP_SRDY1(x) ((x) << S_PLD_RXZEROP_SRDY1)
27587 #define F_PLD_RXZEROP_SRDY1    V_PLD_RXZEROP_SRDY1(1U)
27588 
27589 #define S_PLD_RXZEROP_DRDY1    30
27590 #define V_PLD_RXZEROP_DRDY1(x) ((x) << S_PLD_RXZEROP_DRDY1)
27591 #define F_PLD_RXZEROP_DRDY1    V_PLD_RXZEROP_DRDY1(1U)
27592 
27593 #define S_PLD_TXZEROP_SRDY1    29
27594 #define V_PLD_TXZEROP_SRDY1(x) ((x) << S_PLD_TXZEROP_SRDY1)
27595 #define F_PLD_TXZEROP_SRDY1    V_PLD_TXZEROP_SRDY1(1U)
27596 
27597 #define S_PLD_TXZEROP_DRDY1    28
27598 #define V_PLD_TXZEROP_DRDY1(x) ((x) << S_PLD_TXZEROP_DRDY1)
27599 #define F_PLD_TXZEROP_DRDY1    V_PLD_TXZEROP_DRDY1(1U)
27600 
27601 #define S_PLD_TX_SRDY1    27
27602 #define V_PLD_TX_SRDY1(x) ((x) << S_PLD_TX_SRDY1)
27603 #define F_PLD_TX_SRDY1    V_PLD_TX_SRDY1(1U)
27604 
27605 #define S_PLD_TX_DRDY1    26
27606 #define V_PLD_TX_DRDY1(x) ((x) << S_PLD_TX_DRDY1)
27607 #define F_PLD_TX_DRDY1    V_PLD_TX_DRDY1(1U)
27608 
27609 #define S_ERROR_SRDY1    25
27610 #define V_ERROR_SRDY1(x) ((x) << S_ERROR_SRDY1)
27611 #define F_ERROR_SRDY1    V_ERROR_SRDY1(1U)
27612 
27613 #define S_ERROR_DRDY1    24
27614 #define V_ERROR_DRDY1(x) ((x) << S_ERROR_DRDY1)
27615 #define F_ERROR_DRDY1    V_ERROR_DRDY1(1U)
27616 
27617 #define S_DB_VLD1    23
27618 #define V_DB_VLD1(x) ((x) << S_DB_VLD1)
27619 #define F_DB_VLD1    V_DB_VLD1(1U)
27620 
27621 #define S_DB_GT1    22
27622 #define V_DB_GT1(x) ((x) << S_DB_GT1)
27623 #define F_DB_GT1    V_DB_GT1(1U)
27624 
27625 #define S_TXVALID1    21
27626 #define V_TXVALID1(x) ((x) << S_TXVALID1)
27627 #define F_TXVALID1    V_TXVALID1(1U)
27628 
27629 #define S_TXFULL1    20
27630 #define V_TXFULL1(x) ((x) << S_TXFULL1)
27631 #define F_TXFULL1    V_TXFULL1(1U)
27632 
27633 #define S_PLD_TXVALID1    19
27634 #define V_PLD_TXVALID1(x) ((x) << S_PLD_TXVALID1)
27635 #define F_PLD_TXVALID1    V_PLD_TXVALID1(1U)
27636 
27637 #define S_PLD_TXFULL1    18
27638 #define V_PLD_TXFULL1(x) ((x) << S_PLD_TXFULL1)
27639 #define F_PLD_TXFULL1    V_PLD_TXFULL1(1U)
27640 
27641 #define S_CPL5_TXVALID1    17
27642 #define V_CPL5_TXVALID1(x) ((x) << S_CPL5_TXVALID1)
27643 #define F_CPL5_TXVALID1    V_CPL5_TXVALID1(1U)
27644 
27645 #define S_CPL5_TXFULL1    16
27646 #define V_CPL5_TXFULL1(x) ((x) << S_CPL5_TXFULL1)
27647 #define F_CPL5_TXFULL1    V_CPL5_TXFULL1(1U)
27648 
27649 #define S_PLD_RXZEROP_SRDY0    15
27650 #define V_PLD_RXZEROP_SRDY0(x) ((x) << S_PLD_RXZEROP_SRDY0)
27651 #define F_PLD_RXZEROP_SRDY0    V_PLD_RXZEROP_SRDY0(1U)
27652 
27653 #define S_PLD_RXZEROP_DRDY0    14
27654 #define V_PLD_RXZEROP_DRDY0(x) ((x) << S_PLD_RXZEROP_DRDY0)
27655 #define F_PLD_RXZEROP_DRDY0    V_PLD_RXZEROP_DRDY0(1U)
27656 
27657 #define S_PLD_TXZEROP_SRDY0    13
27658 #define V_PLD_TXZEROP_SRDY0(x) ((x) << S_PLD_TXZEROP_SRDY0)
27659 #define F_PLD_TXZEROP_SRDY0    V_PLD_TXZEROP_SRDY0(1U)
27660 
27661 #define S_PLD_TXZEROP_DRDY0    12
27662 #define V_PLD_TXZEROP_DRDY0(x) ((x) << S_PLD_TXZEROP_DRDY0)
27663 #define F_PLD_TXZEROP_DRDY0    V_PLD_TXZEROP_DRDY0(1U)
27664 
27665 #define S_PLD_TX_SRDY0    11
27666 #define V_PLD_TX_SRDY0(x) ((x) << S_PLD_TX_SRDY0)
27667 #define F_PLD_TX_SRDY0    V_PLD_TX_SRDY0(1U)
27668 
27669 #define S_PLD_TX_DRDY0    10
27670 #define V_PLD_TX_DRDY0(x) ((x) << S_PLD_TX_DRDY0)
27671 #define F_PLD_TX_DRDY0    V_PLD_TX_DRDY0(1U)
27672 
27673 #define S_ERROR_SRDY0    9
27674 #define V_ERROR_SRDY0(x) ((x) << S_ERROR_SRDY0)
27675 #define F_ERROR_SRDY0    V_ERROR_SRDY0(1U)
27676 
27677 #define S_ERROR_DRDY0    8
27678 #define V_ERROR_DRDY0(x) ((x) << S_ERROR_DRDY0)
27679 #define F_ERROR_DRDY0    V_ERROR_DRDY0(1U)
27680 
27681 #define S_DB_VLD0    7
27682 #define V_DB_VLD0(x) ((x) << S_DB_VLD0)
27683 #define F_DB_VLD0    V_DB_VLD0(1U)
27684 
27685 #define S_DB_GT0    6
27686 #define V_DB_GT0(x) ((x) << S_DB_GT0)
27687 #define F_DB_GT0    V_DB_GT0(1U)
27688 
27689 #define S_TXVALID0    5
27690 #define V_TXVALID0(x) ((x) << S_TXVALID0)
27691 #define F_TXVALID0    V_TXVALID0(1U)
27692 
27693 #define S_TXFULL0    4
27694 #define V_TXFULL0(x) ((x) << S_TXFULL0)
27695 #define F_TXFULL0    V_TXFULL0(1U)
27696 
27697 #define S_PLD_TXVALID0    3
27698 #define V_PLD_TXVALID0(x) ((x) << S_PLD_TXVALID0)
27699 #define F_PLD_TXVALID0    V_PLD_TXVALID0(1U)
27700 
27701 #define S_PLD_TXFULL0    2
27702 #define V_PLD_TXFULL0(x) ((x) << S_PLD_TXFULL0)
27703 #define F_PLD_TXFULL0    V_PLD_TXFULL0(1U)
27704 
27705 #define S_CPL5_TXVALID0    1
27706 #define V_CPL5_TXVALID0(x) ((x) << S_CPL5_TXVALID0)
27707 #define F_CPL5_TXVALID0    V_CPL5_TXVALID0(1U)
27708 
27709 #define S_CPL5_TXFULL0    0
27710 #define V_CPL5_TXFULL0(x) ((x) << S_CPL5_TXFULL0)
27711 #define F_CPL5_TXFULL0    V_CPL5_TXFULL0(1U)
27712 
27713 #define A_TP_DBG_CSIDE_FIFO1 0x239
27714 
27715 #define S_PLD_RXZEROP_SRDY3    31
27716 #define V_PLD_RXZEROP_SRDY3(x) ((x) << S_PLD_RXZEROP_SRDY3)
27717 #define F_PLD_RXZEROP_SRDY3    V_PLD_RXZEROP_SRDY3(1U)
27718 
27719 #define S_PLD_RXZEROP_DRDY3    30
27720 #define V_PLD_RXZEROP_DRDY3(x) ((x) << S_PLD_RXZEROP_DRDY3)
27721 #define F_PLD_RXZEROP_DRDY3    V_PLD_RXZEROP_DRDY3(1U)
27722 
27723 #define S_PLD_TXZEROP_SRDY3    29
27724 #define V_PLD_TXZEROP_SRDY3(x) ((x) << S_PLD_TXZEROP_SRDY3)
27725 #define F_PLD_TXZEROP_SRDY3    V_PLD_TXZEROP_SRDY3(1U)
27726 
27727 #define S_PLD_TXZEROP_DRDY3    28
27728 #define V_PLD_TXZEROP_DRDY3(x) ((x) << S_PLD_TXZEROP_DRDY3)
27729 #define F_PLD_TXZEROP_DRDY3    V_PLD_TXZEROP_DRDY3(1U)
27730 
27731 #define S_PLD_TX_SRDY3    27
27732 #define V_PLD_TX_SRDY3(x) ((x) << S_PLD_TX_SRDY3)
27733 #define F_PLD_TX_SRDY3    V_PLD_TX_SRDY3(1U)
27734 
27735 #define S_PLD_TX_DRDY3    26
27736 #define V_PLD_TX_DRDY3(x) ((x) << S_PLD_TX_DRDY3)
27737 #define F_PLD_TX_DRDY3    V_PLD_TX_DRDY3(1U)
27738 
27739 #define S_ERROR_SRDY3    25
27740 #define V_ERROR_SRDY3(x) ((x) << S_ERROR_SRDY3)
27741 #define F_ERROR_SRDY3    V_ERROR_SRDY3(1U)
27742 
27743 #define S_ERROR_DRDY3    24
27744 #define V_ERROR_DRDY3(x) ((x) << S_ERROR_DRDY3)
27745 #define F_ERROR_DRDY3    V_ERROR_DRDY3(1U)
27746 
27747 #define S_DB_VLD3    23
27748 #define V_DB_VLD3(x) ((x) << S_DB_VLD3)
27749 #define F_DB_VLD3    V_DB_VLD3(1U)
27750 
27751 #define S_DB_GT3    22
27752 #define V_DB_GT3(x) ((x) << S_DB_GT3)
27753 #define F_DB_GT3    V_DB_GT3(1U)
27754 
27755 #define S_TXVALID3    21
27756 #define V_TXVALID3(x) ((x) << S_TXVALID3)
27757 #define F_TXVALID3    V_TXVALID3(1U)
27758 
27759 #define S_TXFULL3    20
27760 #define V_TXFULL3(x) ((x) << S_TXFULL3)
27761 #define F_TXFULL3    V_TXFULL3(1U)
27762 
27763 #define S_PLD_TXVALID3    19
27764 #define V_PLD_TXVALID3(x) ((x) << S_PLD_TXVALID3)
27765 #define F_PLD_TXVALID3    V_PLD_TXVALID3(1U)
27766 
27767 #define S_PLD_TXFULL3    18
27768 #define V_PLD_TXFULL3(x) ((x) << S_PLD_TXFULL3)
27769 #define F_PLD_TXFULL3    V_PLD_TXFULL3(1U)
27770 
27771 #define S_CPL5_TXVALID3    17
27772 #define V_CPL5_TXVALID3(x) ((x) << S_CPL5_TXVALID3)
27773 #define F_CPL5_TXVALID3    V_CPL5_TXVALID3(1U)
27774 
27775 #define S_CPL5_TXFULL3    16
27776 #define V_CPL5_TXFULL3(x) ((x) << S_CPL5_TXFULL3)
27777 #define F_CPL5_TXFULL3    V_CPL5_TXFULL3(1U)
27778 
27779 #define S_PLD_RXZEROP_SRDY2    15
27780 #define V_PLD_RXZEROP_SRDY2(x) ((x) << S_PLD_RXZEROP_SRDY2)
27781 #define F_PLD_RXZEROP_SRDY2    V_PLD_RXZEROP_SRDY2(1U)
27782 
27783 #define S_PLD_RXZEROP_DRDY2    14
27784 #define V_PLD_RXZEROP_DRDY2(x) ((x) << S_PLD_RXZEROP_DRDY2)
27785 #define F_PLD_RXZEROP_DRDY2    V_PLD_RXZEROP_DRDY2(1U)
27786 
27787 #define S_PLD_TXZEROP_SRDY2    13
27788 #define V_PLD_TXZEROP_SRDY2(x) ((x) << S_PLD_TXZEROP_SRDY2)
27789 #define F_PLD_TXZEROP_SRDY2    V_PLD_TXZEROP_SRDY2(1U)
27790 
27791 #define S_PLD_TXZEROP_DRDY2    12
27792 #define V_PLD_TXZEROP_DRDY2(x) ((x) << S_PLD_TXZEROP_DRDY2)
27793 #define F_PLD_TXZEROP_DRDY2    V_PLD_TXZEROP_DRDY2(1U)
27794 
27795 #define S_PLD_TX_SRDY2    11
27796 #define V_PLD_TX_SRDY2(x) ((x) << S_PLD_TX_SRDY2)
27797 #define F_PLD_TX_SRDY2    V_PLD_TX_SRDY2(1U)
27798 
27799 #define S_PLD_TX_DRDY2    10
27800 #define V_PLD_TX_DRDY2(x) ((x) << S_PLD_TX_DRDY2)
27801 #define F_PLD_TX_DRDY2    V_PLD_TX_DRDY2(1U)
27802 
27803 #define S_ERROR_SRDY2    9
27804 #define V_ERROR_SRDY2(x) ((x) << S_ERROR_SRDY2)
27805 #define F_ERROR_SRDY2    V_ERROR_SRDY2(1U)
27806 
27807 #define S_ERROR_DRDY2    8
27808 #define V_ERROR_DRDY2(x) ((x) << S_ERROR_DRDY2)
27809 #define F_ERROR_DRDY2    V_ERROR_DRDY2(1U)
27810 
27811 #define S_DB_VLD2    7
27812 #define V_DB_VLD2(x) ((x) << S_DB_VLD2)
27813 #define F_DB_VLD2    V_DB_VLD2(1U)
27814 
27815 #define S_DB_GT2    6
27816 #define V_DB_GT2(x) ((x) << S_DB_GT2)
27817 #define F_DB_GT2    V_DB_GT2(1U)
27818 
27819 #define S_TXVALID2    5
27820 #define V_TXVALID2(x) ((x) << S_TXVALID2)
27821 #define F_TXVALID2    V_TXVALID2(1U)
27822 
27823 #define S_TXFULL2    4
27824 #define V_TXFULL2(x) ((x) << S_TXFULL2)
27825 #define F_TXFULL2    V_TXFULL2(1U)
27826 
27827 #define S_PLD_TXVALID2    3
27828 #define V_PLD_TXVALID2(x) ((x) << S_PLD_TXVALID2)
27829 #define F_PLD_TXVALID2    V_PLD_TXVALID2(1U)
27830 
27831 #define S_PLD_TXFULL2    2
27832 #define V_PLD_TXFULL2(x) ((x) << S_PLD_TXFULL2)
27833 #define F_PLD_TXFULL2    V_PLD_TXFULL2(1U)
27834 
27835 #define S_CPL5_TXVALID2    1
27836 #define V_CPL5_TXVALID2(x) ((x) << S_CPL5_TXVALID2)
27837 #define F_CPL5_TXVALID2    V_CPL5_TXVALID2(1U)
27838 
27839 #define S_CPL5_TXFULL2    0
27840 #define V_CPL5_TXFULL2(x) ((x) << S_CPL5_TXFULL2)
27841 #define F_CPL5_TXFULL2    V_CPL5_TXFULL2(1U)
27842 
27843 #define A_TP_DBG_CSIDE_DISP0 0x23a
27844 
27845 #define S_CPL5RXVALID    27
27846 #define V_CPL5RXVALID(x) ((x) << S_CPL5RXVALID)
27847 #define F_CPL5RXVALID    V_CPL5RXVALID(1U)
27848 
27849 #define S_CSTATIC1    26
27850 #define V_CSTATIC1(x) ((x) << S_CSTATIC1)
27851 #define F_CSTATIC1    V_CSTATIC1(1U)
27852 
27853 #define S_CSTATIC2    25
27854 #define V_CSTATIC2(x) ((x) << S_CSTATIC2)
27855 #define F_CSTATIC2    V_CSTATIC2(1U)
27856 
27857 #define S_PLD_RXZEROP    24
27858 #define V_PLD_RXZEROP(x) ((x) << S_PLD_RXZEROP)
27859 #define F_PLD_RXZEROP    V_PLD_RXZEROP(1U)
27860 
27861 #define S_DDP_IN_PROGRESS    23
27862 #define V_DDP_IN_PROGRESS(x) ((x) << S_DDP_IN_PROGRESS)
27863 #define F_DDP_IN_PROGRESS    V_DDP_IN_PROGRESS(1U)
27864 
27865 #define S_PLD_RXZEROP_SRDY    22
27866 #define V_PLD_RXZEROP_SRDY(x) ((x) << S_PLD_RXZEROP_SRDY)
27867 #define F_PLD_RXZEROP_SRDY    V_PLD_RXZEROP_SRDY(1U)
27868 
27869 #define S_CSTATIC3    21
27870 #define V_CSTATIC3(x) ((x) << S_CSTATIC3)
27871 #define F_CSTATIC3    V_CSTATIC3(1U)
27872 
27873 #define S_DDP_DRDY    20
27874 #define V_DDP_DRDY(x) ((x) << S_DDP_DRDY)
27875 #define F_DDP_DRDY    V_DDP_DRDY(1U)
27876 
27877 #define S_DDP_PRE_STATE    17
27878 #define M_DDP_PRE_STATE    0x7U
27879 #define V_DDP_PRE_STATE(x) ((x) << S_DDP_PRE_STATE)
27880 #define G_DDP_PRE_STATE(x) (((x) >> S_DDP_PRE_STATE) & M_DDP_PRE_STATE)
27881 
27882 #define S_DDP_SRDY    16
27883 #define V_DDP_SRDY(x) ((x) << S_DDP_SRDY)
27884 #define F_DDP_SRDY    V_DDP_SRDY(1U)
27885 
27886 #define S_DDP_MSG_CODE    12
27887 #define M_DDP_MSG_CODE    0xfU
27888 #define V_DDP_MSG_CODE(x) ((x) << S_DDP_MSG_CODE)
27889 #define G_DDP_MSG_CODE(x) (((x) >> S_DDP_MSG_CODE) & M_DDP_MSG_CODE)
27890 
27891 #define S_CPL5_SOCP_CNT    10
27892 #define M_CPL5_SOCP_CNT    0x3U
27893 #define V_CPL5_SOCP_CNT(x) ((x) << S_CPL5_SOCP_CNT)
27894 #define G_CPL5_SOCP_CNT(x) (((x) >> S_CPL5_SOCP_CNT) & M_CPL5_SOCP_CNT)
27895 
27896 #define S_CSTATIC4    4
27897 #define M_CSTATIC4    0x3fU
27898 #define V_CSTATIC4(x) ((x) << S_CSTATIC4)
27899 #define G_CSTATIC4(x) (((x) >> S_CSTATIC4) & M_CSTATIC4)
27900 
27901 #define S_CMD_SEL    1
27902 #define V_CMD_SEL(x) ((x) << S_CMD_SEL)
27903 #define F_CMD_SEL    V_CMD_SEL(1U)
27904 
27905 #define S_T5_TXFULL    31
27906 #define V_T5_TXFULL(x) ((x) << S_T5_TXFULL)
27907 #define F_T5_TXFULL    V_T5_TXFULL(1U)
27908 
27909 #define S_CPL5RXFULL    26
27910 #define V_CPL5RXFULL(x) ((x) << S_CPL5RXFULL)
27911 #define F_CPL5RXFULL    V_CPL5RXFULL(1U)
27912 
27913 #define S_T5_PLD_RXZEROP_SRDY    25
27914 #define V_T5_PLD_RXZEROP_SRDY(x) ((x) << S_T5_PLD_RXZEROP_SRDY)
27915 #define F_T5_PLD_RXZEROP_SRDY    V_T5_PLD_RXZEROP_SRDY(1U)
27916 
27917 #define S_PLD2XRXVALID    23
27918 #define V_PLD2XRXVALID(x) ((x) << S_PLD2XRXVALID)
27919 #define F_PLD2XRXVALID    V_PLD2XRXVALID(1U)
27920 
27921 #define S_T5_DDP_SRDY    22
27922 #define V_T5_DDP_SRDY(x) ((x) << S_T5_DDP_SRDY)
27923 #define F_T5_DDP_SRDY    V_T5_DDP_SRDY(1U)
27924 
27925 #define S_T5_DDP_DRDY    21
27926 #define V_T5_DDP_DRDY(x) ((x) << S_T5_DDP_DRDY)
27927 #define F_T5_DDP_DRDY    V_T5_DDP_DRDY(1U)
27928 
27929 #define S_DDPSTATE    16
27930 #define M_DDPSTATE    0x1fU
27931 #define V_DDPSTATE(x) ((x) << S_DDPSTATE)
27932 #define G_DDPSTATE(x) (((x) >> S_DDPSTATE) & M_DDPSTATE)
27933 
27934 #define S_DDPMSGCODE    12
27935 #define M_DDPMSGCODE    0xfU
27936 #define V_DDPMSGCODE(x) ((x) << S_DDPMSGCODE)
27937 #define G_DDPMSGCODE(x) (((x) >> S_DDPMSGCODE) & M_DDPMSGCODE)
27938 
27939 #define S_CPL5SOCPCNT    8
27940 #define M_CPL5SOCPCNT    0xfU
27941 #define V_CPL5SOCPCNT(x) ((x) << S_CPL5SOCPCNT)
27942 #define G_CPL5SOCPCNT(x) (((x) >> S_CPL5SOCPCNT) & M_CPL5SOCPCNT)
27943 
27944 #define S_PLDRXZEROPCNT    4
27945 #define M_PLDRXZEROPCNT    0xfU
27946 #define V_PLDRXZEROPCNT(x) ((x) << S_PLDRXZEROPCNT)
27947 #define G_PLDRXZEROPCNT(x) (((x) >> S_PLDRXZEROPCNT) & M_PLDRXZEROPCNT)
27948 
27949 #define S_TXFRMERR2    3
27950 #define V_TXFRMERR2(x) ((x) << S_TXFRMERR2)
27951 #define F_TXFRMERR2    V_TXFRMERR2(1U)
27952 
27953 #define S_TXFRMERR1    2
27954 #define V_TXFRMERR1(x) ((x) << S_TXFRMERR1)
27955 #define F_TXFRMERR1    V_TXFRMERR1(1U)
27956 
27957 #define S_TXVALID2X    1
27958 #define V_TXVALID2X(x) ((x) << S_TXVALID2X)
27959 #define F_TXVALID2X    V_TXVALID2X(1U)
27960 
27961 #define S_TXFULL2X    0
27962 #define V_TXFULL2X(x) ((x) << S_TXFULL2X)
27963 #define F_TXFULL2X    V_TXFULL2X(1U)
27964 
27965 #define S_T6_TXFULL    31
27966 #define V_T6_TXFULL(x) ((x) << S_T6_TXFULL)
27967 #define F_T6_TXFULL    V_T6_TXFULL(1U)
27968 
27969 #define S_T6_PLD_RXZEROP_SRDY    25
27970 #define V_T6_PLD_RXZEROP_SRDY(x) ((x) << S_T6_PLD_RXZEROP_SRDY)
27971 #define F_T6_PLD_RXZEROP_SRDY    V_T6_PLD_RXZEROP_SRDY(1U)
27972 
27973 #define S_T6_DDP_SRDY    22
27974 #define V_T6_DDP_SRDY(x) ((x) << S_T6_DDP_SRDY)
27975 #define F_T6_DDP_SRDY    V_T6_DDP_SRDY(1U)
27976 
27977 #define S_T6_DDP_DRDY    21
27978 #define V_T6_DDP_DRDY(x) ((x) << S_T6_DDP_DRDY)
27979 #define F_T6_DDP_DRDY    V_T6_DDP_DRDY(1U)
27980 
27981 #define A_TP_DBG_CSIDE_DISP1 0x23b
27982 
27983 #define S_T5_TXFULL    31
27984 #define V_T5_TXFULL(x) ((x) << S_T5_TXFULL)
27985 #define F_T5_TXFULL    V_T5_TXFULL(1U)
27986 
27987 #define S_T5_PLD_RXZEROP_SRDY    25
27988 #define V_T5_PLD_RXZEROP_SRDY(x) ((x) << S_T5_PLD_RXZEROP_SRDY)
27989 #define F_T5_PLD_RXZEROP_SRDY    V_T5_PLD_RXZEROP_SRDY(1U)
27990 
27991 #define S_T5_DDP_SRDY    22
27992 #define V_T5_DDP_SRDY(x) ((x) << S_T5_DDP_SRDY)
27993 #define F_T5_DDP_SRDY    V_T5_DDP_SRDY(1U)
27994 
27995 #define S_T5_DDP_DRDY    21
27996 #define V_T5_DDP_DRDY(x) ((x) << S_T5_DDP_DRDY)
27997 #define F_T5_DDP_DRDY    V_T5_DDP_DRDY(1U)
27998 
27999 #define S_T6_TXFULL    31
28000 #define V_T6_TXFULL(x) ((x) << S_T6_TXFULL)
28001 #define F_T6_TXFULL    V_T6_TXFULL(1U)
28002 
28003 #define S_T6_PLD_RXZEROP_SRDY    25
28004 #define V_T6_PLD_RXZEROP_SRDY(x) ((x) << S_T6_PLD_RXZEROP_SRDY)
28005 #define F_T6_PLD_RXZEROP_SRDY    V_T6_PLD_RXZEROP_SRDY(1U)
28006 
28007 #define S_T6_DDP_SRDY    22
28008 #define V_T6_DDP_SRDY(x) ((x) << S_T6_DDP_SRDY)
28009 #define F_T6_DDP_SRDY    V_T6_DDP_SRDY(1U)
28010 
28011 #define S_T6_DDP_DRDY    21
28012 #define V_T6_DDP_DRDY(x) ((x) << S_T6_DDP_DRDY)
28013 #define F_T6_DDP_DRDY    V_T6_DDP_DRDY(1U)
28014 
28015 #define A_TP_DBG_CSIDE_DDP0 0x23c
28016 
28017 #define S_DDPMSGLATEST7    28
28018 #define M_DDPMSGLATEST7    0xfU
28019 #define V_DDPMSGLATEST7(x) ((x) << S_DDPMSGLATEST7)
28020 #define G_DDPMSGLATEST7(x) (((x) >> S_DDPMSGLATEST7) & M_DDPMSGLATEST7)
28021 
28022 #define S_DDPMSGLATEST6    24
28023 #define M_DDPMSGLATEST6    0xfU
28024 #define V_DDPMSGLATEST6(x) ((x) << S_DDPMSGLATEST6)
28025 #define G_DDPMSGLATEST6(x) (((x) >> S_DDPMSGLATEST6) & M_DDPMSGLATEST6)
28026 
28027 #define S_DDPMSGLATEST5    20
28028 #define M_DDPMSGLATEST5    0xfU
28029 #define V_DDPMSGLATEST5(x) ((x) << S_DDPMSGLATEST5)
28030 #define G_DDPMSGLATEST5(x) (((x) >> S_DDPMSGLATEST5) & M_DDPMSGLATEST5)
28031 
28032 #define S_DDPMSGLATEST4    16
28033 #define M_DDPMSGLATEST4    0xfU
28034 #define V_DDPMSGLATEST4(x) ((x) << S_DDPMSGLATEST4)
28035 #define G_DDPMSGLATEST4(x) (((x) >> S_DDPMSGLATEST4) & M_DDPMSGLATEST4)
28036 
28037 #define S_DDPMSGLATEST3    12
28038 #define M_DDPMSGLATEST3    0xfU
28039 #define V_DDPMSGLATEST3(x) ((x) << S_DDPMSGLATEST3)
28040 #define G_DDPMSGLATEST3(x) (((x) >> S_DDPMSGLATEST3) & M_DDPMSGLATEST3)
28041 
28042 #define S_DDPMSGLATEST2    8
28043 #define M_DDPMSGLATEST2    0xfU
28044 #define V_DDPMSGLATEST2(x) ((x) << S_DDPMSGLATEST2)
28045 #define G_DDPMSGLATEST2(x) (((x) >> S_DDPMSGLATEST2) & M_DDPMSGLATEST2)
28046 
28047 #define S_DDPMSGLATEST1    4
28048 #define M_DDPMSGLATEST1    0xfU
28049 #define V_DDPMSGLATEST1(x) ((x) << S_DDPMSGLATEST1)
28050 #define G_DDPMSGLATEST1(x) (((x) >> S_DDPMSGLATEST1) & M_DDPMSGLATEST1)
28051 
28052 #define S_DDPMSGLATEST0    0
28053 #define M_DDPMSGLATEST0    0xfU
28054 #define V_DDPMSGLATEST0(x) ((x) << S_DDPMSGLATEST0)
28055 #define G_DDPMSGLATEST0(x) (((x) >> S_DDPMSGLATEST0) & M_DDPMSGLATEST0)
28056 
28057 #define A_TP_DBG_CSIDE_DDP1 0x23d
28058 #define A_TP_DBG_CSIDE_FRM 0x23e
28059 
28060 #define S_CRX2XERROR    28
28061 #define M_CRX2XERROR    0xfU
28062 #define V_CRX2XERROR(x) ((x) << S_CRX2XERROR)
28063 #define G_CRX2XERROR(x) (((x) >> S_CRX2XERROR) & M_CRX2XERROR)
28064 
28065 #define S_CPLDTX2XERROR    24
28066 #define M_CPLDTX2XERROR    0xfU
28067 #define V_CPLDTX2XERROR(x) ((x) << S_CPLDTX2XERROR)
28068 #define G_CPLDTX2XERROR(x) (((x) >> S_CPLDTX2XERROR) & M_CPLDTX2XERROR)
28069 
28070 #define S_CTXERROR    22
28071 #define M_CTXERROR    0x3U
28072 #define V_CTXERROR(x) ((x) << S_CTXERROR)
28073 #define G_CTXERROR(x) (((x) >> S_CTXERROR) & M_CTXERROR)
28074 
28075 #define S_CPLDRXERROR    20
28076 #define M_CPLDRXERROR    0x3U
28077 #define V_CPLDRXERROR(x) ((x) << S_CPLDRXERROR)
28078 #define G_CPLDRXERROR(x) (((x) >> S_CPLDRXERROR) & M_CPLDRXERROR)
28079 
28080 #define S_CPLRXERROR    18
28081 #define M_CPLRXERROR    0x3U
28082 #define V_CPLRXERROR(x) ((x) << S_CPLRXERROR)
28083 #define G_CPLRXERROR(x) (((x) >> S_CPLRXERROR) & M_CPLRXERROR)
28084 
28085 #define S_CPLTXERROR    16
28086 #define M_CPLTXERROR    0x3U
28087 #define V_CPLTXERROR(x) ((x) << S_CPLTXERROR)
28088 #define G_CPLTXERROR(x) (((x) >> S_CPLTXERROR) & M_CPLTXERROR)
28089 
28090 #define S_CPRSERROR    0
28091 #define M_CPRSERROR    0xfU
28092 #define V_CPRSERROR(x) ((x) << S_CPRSERROR)
28093 #define G_CPRSERROR(x) (((x) >> S_CPRSERROR) & M_CPRSERROR)
28094 
28095 #define A_TP_DBG_CSIDE_INT 0x23f
28096 
28097 #define S_CRXVALID2X    28
28098 #define M_CRXVALID2X    0xfU
28099 #define V_CRXVALID2X(x) ((x) << S_CRXVALID2X)
28100 #define G_CRXVALID2X(x) (((x) >> S_CRXVALID2X) & M_CRXVALID2X)
28101 
28102 #define S_CRXAFULL2X    24
28103 #define M_CRXAFULL2X    0xfU
28104 #define V_CRXAFULL2X(x) ((x) << S_CRXAFULL2X)
28105 #define G_CRXAFULL2X(x) (((x) >> S_CRXAFULL2X) & M_CRXAFULL2X)
28106 
28107 #define S_CTXVALID2X    22
28108 #define M_CTXVALID2X    0x3U
28109 #define V_CTXVALID2X(x) ((x) << S_CTXVALID2X)
28110 #define G_CTXVALID2X(x) (((x) >> S_CTXVALID2X) & M_CTXVALID2X)
28111 
28112 #define S_CTXAFULL2X    20
28113 #define M_CTXAFULL2X    0x3U
28114 #define V_CTXAFULL2X(x) ((x) << S_CTXAFULL2X)
28115 #define G_CTXAFULL2X(x) (((x) >> S_CTXAFULL2X) & M_CTXAFULL2X)
28116 
28117 #define S_PLD2X_RXVALID    18
28118 #define M_PLD2X_RXVALID    0x3U
28119 #define V_PLD2X_RXVALID(x) ((x) << S_PLD2X_RXVALID)
28120 #define G_PLD2X_RXVALID(x) (((x) >> S_PLD2X_RXVALID) & M_PLD2X_RXVALID)
28121 
28122 #define S_PLD2X_RXAFULL    16
28123 #define M_PLD2X_RXAFULL    0x3U
28124 #define V_PLD2X_RXAFULL(x) ((x) << S_PLD2X_RXAFULL)
28125 #define G_PLD2X_RXAFULL(x) (((x) >> S_PLD2X_RXAFULL) & M_PLD2X_RXAFULL)
28126 
28127 #define S_CSIDE_DDP_VALID    14
28128 #define M_CSIDE_DDP_VALID    0x3U
28129 #define V_CSIDE_DDP_VALID(x) ((x) << S_CSIDE_DDP_VALID)
28130 #define G_CSIDE_DDP_VALID(x) (((x) >> S_CSIDE_DDP_VALID) & M_CSIDE_DDP_VALID)
28131 
28132 #define S_DDP_AFULL    12
28133 #define M_DDP_AFULL    0x3U
28134 #define V_DDP_AFULL(x) ((x) << S_DDP_AFULL)
28135 #define G_DDP_AFULL(x) (((x) >> S_DDP_AFULL) & M_DDP_AFULL)
28136 
28137 #define S_TRC_RXVALID    11
28138 #define V_TRC_RXVALID(x) ((x) << S_TRC_RXVALID)
28139 #define F_TRC_RXVALID    V_TRC_RXVALID(1U)
28140 
28141 #define S_TRC_RXFULL    10
28142 #define V_TRC_RXFULL(x) ((x) << S_TRC_RXFULL)
28143 #define F_TRC_RXFULL    V_TRC_RXFULL(1U)
28144 
28145 #define S_CPL5_TXVALID    9
28146 #define V_CPL5_TXVALID(x) ((x) << S_CPL5_TXVALID)
28147 #define F_CPL5_TXVALID    V_CPL5_TXVALID(1U)
28148 
28149 #define S_CPL5_TXFULL    8
28150 #define V_CPL5_TXFULL(x) ((x) << S_CPL5_TXFULL)
28151 #define F_CPL5_TXFULL    V_CPL5_TXFULL(1U)
28152 
28153 #define S_PLD2X_TXVALID    4
28154 #define M_PLD2X_TXVALID    0xfU
28155 #define V_PLD2X_TXVALID(x) ((x) << S_PLD2X_TXVALID)
28156 #define G_PLD2X_TXVALID(x) (((x) >> S_PLD2X_TXVALID) & M_PLD2X_TXVALID)
28157 
28158 #define S_PLD2X_TXAFULL    0
28159 #define M_PLD2X_TXAFULL    0xfU
28160 #define V_PLD2X_TXAFULL(x) ((x) << S_PLD2X_TXAFULL)
28161 #define G_PLD2X_TXAFULL(x) (((x) >> S_PLD2X_TXAFULL) & M_PLD2X_TXAFULL)
28162 
28163 #define A_TP_CHDR_CONFIG 0x240
28164 
28165 #define S_CH1HIGH    24
28166 #define M_CH1HIGH    0xffU
28167 #define V_CH1HIGH(x) ((x) << S_CH1HIGH)
28168 #define G_CH1HIGH(x) (((x) >> S_CH1HIGH) & M_CH1HIGH)
28169 
28170 #define S_CH1LOW    16
28171 #define M_CH1LOW    0xffU
28172 #define V_CH1LOW(x) ((x) << S_CH1LOW)
28173 #define G_CH1LOW(x) (((x) >> S_CH1LOW) & M_CH1LOW)
28174 
28175 #define S_CH0HIGH    8
28176 #define M_CH0HIGH    0xffU
28177 #define V_CH0HIGH(x) ((x) << S_CH0HIGH)
28178 #define G_CH0HIGH(x) (((x) >> S_CH0HIGH) & M_CH0HIGH)
28179 
28180 #define S_CH0LOW    0
28181 #define M_CH0LOW    0xffU
28182 #define V_CH0LOW(x) ((x) << S_CH0LOW)
28183 #define G_CH0LOW(x) (((x) >> S_CH0LOW) & M_CH0LOW)
28184 
28185 #define A_TP_UTRN_CONFIG 0x241
28186 
28187 #define S_CH2FIFOLIMIT    16
28188 #define M_CH2FIFOLIMIT    0xffU
28189 #define V_CH2FIFOLIMIT(x) ((x) << S_CH2FIFOLIMIT)
28190 #define G_CH2FIFOLIMIT(x) (((x) >> S_CH2FIFOLIMIT) & M_CH2FIFOLIMIT)
28191 
28192 #define S_CH1FIFOLIMIT    8
28193 #define M_CH1FIFOLIMIT    0xffU
28194 #define V_CH1FIFOLIMIT(x) ((x) << S_CH1FIFOLIMIT)
28195 #define G_CH1FIFOLIMIT(x) (((x) >> S_CH1FIFOLIMIT) & M_CH1FIFOLIMIT)
28196 
28197 #define S_CH0FIFOLIMIT    0
28198 #define M_CH0FIFOLIMIT    0xffU
28199 #define V_CH0FIFOLIMIT(x) ((x) << S_CH0FIFOLIMIT)
28200 #define G_CH0FIFOLIMIT(x) (((x) >> S_CH0FIFOLIMIT) & M_CH0FIFOLIMIT)
28201 
28202 #define A_TP_CDSP_CONFIG 0x242
28203 
28204 #define S_WRITEZEROEN    4
28205 #define V_WRITEZEROEN(x) ((x) << S_WRITEZEROEN)
28206 #define F_WRITEZEROEN    V_WRITEZEROEN(1U)
28207 
28208 #define S_WRITEZEROOP    0
28209 #define M_WRITEZEROOP    0xfU
28210 #define V_WRITEZEROOP(x) ((x) << S_WRITEZEROOP)
28211 #define G_WRITEZEROOP(x) (((x) >> S_WRITEZEROOP) & M_WRITEZEROOP)
28212 
28213 #define S_STARTSKIPPLD    7
28214 #define V_STARTSKIPPLD(x) ((x) << S_STARTSKIPPLD)
28215 #define F_STARTSKIPPLD    V_STARTSKIPPLD(1U)
28216 
28217 #define S_ATOMICCMDEN    5
28218 #define V_ATOMICCMDEN(x) ((x) << S_ATOMICCMDEN)
28219 #define F_ATOMICCMDEN    V_ATOMICCMDEN(1U)
28220 
28221 #define S_ISCSICMDMODE    28
28222 #define V_ISCSICMDMODE(x) ((x) << S_ISCSICMDMODE)
28223 #define F_ISCSICMDMODE    V_ISCSICMDMODE(1U)
28224 
28225 #define A_TP_CSPI_POWER 0x243
28226 
28227 #define S_GATECHNTX3    11
28228 #define V_GATECHNTX3(x) ((x) << S_GATECHNTX3)
28229 #define F_GATECHNTX3    V_GATECHNTX3(1U)
28230 
28231 #define S_GATECHNTX2    10
28232 #define V_GATECHNTX2(x) ((x) << S_GATECHNTX2)
28233 #define F_GATECHNTX2    V_GATECHNTX2(1U)
28234 
28235 #define S_GATECHNTX1    9
28236 #define V_GATECHNTX1(x) ((x) << S_GATECHNTX1)
28237 #define F_GATECHNTX1    V_GATECHNTX1(1U)
28238 
28239 #define S_GATECHNTX0    8
28240 #define V_GATECHNTX0(x) ((x) << S_GATECHNTX0)
28241 #define F_GATECHNTX0    V_GATECHNTX0(1U)
28242 
28243 #define S_GATECHNRX1    7
28244 #define V_GATECHNRX1(x) ((x) << S_GATECHNRX1)
28245 #define F_GATECHNRX1    V_GATECHNRX1(1U)
28246 
28247 #define S_GATECHNRX0    6
28248 #define V_GATECHNRX0(x) ((x) << S_GATECHNRX0)
28249 #define F_GATECHNRX0    V_GATECHNRX0(1U)
28250 
28251 #define S_SLEEPRDYUTRN    4
28252 #define V_SLEEPRDYUTRN(x) ((x) << S_SLEEPRDYUTRN)
28253 #define F_SLEEPRDYUTRN    V_SLEEPRDYUTRN(1U)
28254 
28255 #define S_SLEEPREQUTRN    0
28256 #define V_SLEEPREQUTRN(x) ((x) << S_SLEEPREQUTRN)
28257 #define F_SLEEPREQUTRN    V_SLEEPREQUTRN(1U)
28258 
28259 #define A_TP_TRC_CONFIG 0x244
28260 
28261 #define S_TRCRR    1
28262 #define V_TRCRR(x) ((x) << S_TRCRR)
28263 #define F_TRCRR    V_TRCRR(1U)
28264 
28265 #define S_TRCCH    0
28266 #define V_TRCCH(x) ((x) << S_TRCCH)
28267 #define F_TRCCH    V_TRCCH(1U)
28268 
28269 #define A_TP_TAG_CONFIG 0x245
28270 
28271 #define S_ETAGTYPE    16
28272 #define M_ETAGTYPE    0xffffU
28273 #define V_ETAGTYPE(x) ((x) << S_ETAGTYPE)
28274 #define G_ETAGTYPE(x) (((x) >> S_ETAGTYPE) & M_ETAGTYPE)
28275 
28276 #define A_TP_DBG_CSIDE_PRS 0x246
28277 
28278 #define S_CPRSSTATE3    24
28279 #define M_CPRSSTATE3    0x7U
28280 #define V_CPRSSTATE3(x) ((x) << S_CPRSSTATE3)
28281 #define G_CPRSSTATE3(x) (((x) >> S_CPRSSTATE3) & M_CPRSSTATE3)
28282 
28283 #define S_CPRSSTATE2    16
28284 #define M_CPRSSTATE2    0x7U
28285 #define V_CPRSSTATE2(x) ((x) << S_CPRSSTATE2)
28286 #define G_CPRSSTATE2(x) (((x) >> S_CPRSSTATE2) & M_CPRSSTATE2)
28287 
28288 #define S_CPRSSTATE1    8
28289 #define M_CPRSSTATE1    0x7U
28290 #define V_CPRSSTATE1(x) ((x) << S_CPRSSTATE1)
28291 #define G_CPRSSTATE1(x) (((x) >> S_CPRSSTATE1) & M_CPRSSTATE1)
28292 
28293 #define S_CPRSSTATE0    0
28294 #define M_CPRSSTATE0    0x7U
28295 #define V_CPRSSTATE0(x) ((x) << S_CPRSSTATE0)
28296 #define G_CPRSSTATE0(x) (((x) >> S_CPRSSTATE0) & M_CPRSSTATE0)
28297 
28298 #define S_C4TUPBUSY3    31
28299 #define V_C4TUPBUSY3(x) ((x) << S_C4TUPBUSY3)
28300 #define F_C4TUPBUSY3    V_C4TUPBUSY3(1U)
28301 
28302 #define S_CDBVALID3    30
28303 #define V_CDBVALID3(x) ((x) << S_CDBVALID3)
28304 #define F_CDBVALID3    V_CDBVALID3(1U)
28305 
28306 #define S_CRXVALID3    29
28307 #define V_CRXVALID3(x) ((x) << S_CRXVALID3)
28308 #define F_CRXVALID3    V_CRXVALID3(1U)
28309 
28310 #define S_CRXFULL3    28
28311 #define V_CRXFULL3(x) ((x) << S_CRXFULL3)
28312 #define F_CRXFULL3    V_CRXFULL3(1U)
28313 
28314 #define S_T5_CPRSSTATE3    24
28315 #define M_T5_CPRSSTATE3    0xfU
28316 #define V_T5_CPRSSTATE3(x) ((x) << S_T5_CPRSSTATE3)
28317 #define G_T5_CPRSSTATE3(x) (((x) >> S_T5_CPRSSTATE3) & M_T5_CPRSSTATE3)
28318 
28319 #define S_C4TUPBUSY2    23
28320 #define V_C4TUPBUSY2(x) ((x) << S_C4TUPBUSY2)
28321 #define F_C4TUPBUSY2    V_C4TUPBUSY2(1U)
28322 
28323 #define S_CDBVALID2    22
28324 #define V_CDBVALID2(x) ((x) << S_CDBVALID2)
28325 #define F_CDBVALID2    V_CDBVALID2(1U)
28326 
28327 #define S_CRXVALID2    21
28328 #define V_CRXVALID2(x) ((x) << S_CRXVALID2)
28329 #define F_CRXVALID2    V_CRXVALID2(1U)
28330 
28331 #define S_CRXFULL2    20
28332 #define V_CRXFULL2(x) ((x) << S_CRXFULL2)
28333 #define F_CRXFULL2    V_CRXFULL2(1U)
28334 
28335 #define S_T5_CPRSSTATE2    16
28336 #define M_T5_CPRSSTATE2    0xfU
28337 #define V_T5_CPRSSTATE2(x) ((x) << S_T5_CPRSSTATE2)
28338 #define G_T5_CPRSSTATE2(x) (((x) >> S_T5_CPRSSTATE2) & M_T5_CPRSSTATE2)
28339 
28340 #define S_C4TUPBUSY1    15
28341 #define V_C4TUPBUSY1(x) ((x) << S_C4TUPBUSY1)
28342 #define F_C4TUPBUSY1    V_C4TUPBUSY1(1U)
28343 
28344 #define S_CDBVALID1    14
28345 #define V_CDBVALID1(x) ((x) << S_CDBVALID1)
28346 #define F_CDBVALID1    V_CDBVALID1(1U)
28347 
28348 #define S_CRXVALID1    13
28349 #define V_CRXVALID1(x) ((x) << S_CRXVALID1)
28350 #define F_CRXVALID1    V_CRXVALID1(1U)
28351 
28352 #define S_CRXFULL1    12
28353 #define V_CRXFULL1(x) ((x) << S_CRXFULL1)
28354 #define F_CRXFULL1    V_CRXFULL1(1U)
28355 
28356 #define S_T5_CPRSSTATE1    8
28357 #define M_T5_CPRSSTATE1    0xfU
28358 #define V_T5_CPRSSTATE1(x) ((x) << S_T5_CPRSSTATE1)
28359 #define G_T5_CPRSSTATE1(x) (((x) >> S_T5_CPRSSTATE1) & M_T5_CPRSSTATE1)
28360 
28361 #define S_C4TUPBUSY0    7
28362 #define V_C4TUPBUSY0(x) ((x) << S_C4TUPBUSY0)
28363 #define F_C4TUPBUSY0    V_C4TUPBUSY0(1U)
28364 
28365 #define S_CDBVALID0    6
28366 #define V_CDBVALID0(x) ((x) << S_CDBVALID0)
28367 #define F_CDBVALID0    V_CDBVALID0(1U)
28368 
28369 #define S_CRXVALID0    5
28370 #define V_CRXVALID0(x) ((x) << S_CRXVALID0)
28371 #define F_CRXVALID0    V_CRXVALID0(1U)
28372 
28373 #define S_CRXFULL0    4
28374 #define V_CRXFULL0(x) ((x) << S_CRXFULL0)
28375 #define F_CRXFULL0    V_CRXFULL0(1U)
28376 
28377 #define S_T5_CPRSSTATE0    0
28378 #define M_T5_CPRSSTATE0    0xfU
28379 #define V_T5_CPRSSTATE0(x) ((x) << S_T5_CPRSSTATE0)
28380 #define G_T5_CPRSSTATE0(x) (((x) >> S_T5_CPRSSTATE0) & M_T5_CPRSSTATE0)
28381 
28382 #define S_T6_CPRSSTATE3    24
28383 #define M_T6_CPRSSTATE3    0xfU
28384 #define V_T6_CPRSSTATE3(x) ((x) << S_T6_CPRSSTATE3)
28385 #define G_T6_CPRSSTATE3(x) (((x) >> S_T6_CPRSSTATE3) & M_T6_CPRSSTATE3)
28386 
28387 #define S_T6_CPRSSTATE2    16
28388 #define M_T6_CPRSSTATE2    0xfU
28389 #define V_T6_CPRSSTATE2(x) ((x) << S_T6_CPRSSTATE2)
28390 #define G_T6_CPRSSTATE2(x) (((x) >> S_T6_CPRSSTATE2) & M_T6_CPRSSTATE2)
28391 
28392 #define S_T6_CPRSSTATE1    8
28393 #define M_T6_CPRSSTATE1    0xfU
28394 #define V_T6_CPRSSTATE1(x) ((x) << S_T6_CPRSSTATE1)
28395 #define G_T6_CPRSSTATE1(x) (((x) >> S_T6_CPRSSTATE1) & M_T6_CPRSSTATE1)
28396 
28397 #define S_T6_CPRSSTATE0    0
28398 #define M_T6_CPRSSTATE0    0xfU
28399 #define V_T6_CPRSSTATE0(x) ((x) << S_T6_CPRSSTATE0)
28400 #define G_T6_CPRSSTATE0(x) (((x) >> S_T6_CPRSSTATE0) & M_T6_CPRSSTATE0)
28401 
28402 #define A_TP_DBG_CSIDE_DEMUX 0x247
28403 
28404 #define S_CALLDONE    28
28405 #define M_CALLDONE    0xfU
28406 #define V_CALLDONE(x) ((x) << S_CALLDONE)
28407 #define G_CALLDONE(x) (((x) >> S_CALLDONE) & M_CALLDONE)
28408 
28409 #define S_CTCPL5DONE    24
28410 #define M_CTCPL5DONE    0xfU
28411 #define V_CTCPL5DONE(x) ((x) << S_CTCPL5DONE)
28412 #define G_CTCPL5DONE(x) (((x) >> S_CTCPL5DONE) & M_CTCPL5DONE)
28413 
28414 #define S_CTXZEROPDONE    20
28415 #define M_CTXZEROPDONE    0xfU
28416 #define V_CTXZEROPDONE(x) ((x) << S_CTXZEROPDONE)
28417 #define G_CTXZEROPDONE(x) (((x) >> S_CTXZEROPDONE) & M_CTXZEROPDONE)
28418 
28419 #define S_CPLDDONE    16
28420 #define M_CPLDDONE    0xfU
28421 #define V_CPLDDONE(x) ((x) << S_CPLDDONE)
28422 #define G_CPLDDONE(x) (((x) >> S_CPLDDONE) & M_CPLDDONE)
28423 
28424 #define S_CTTCPOPDONE    12
28425 #define M_CTTCPOPDONE    0xfU
28426 #define V_CTTCPOPDONE(x) ((x) << S_CTTCPOPDONE)
28427 #define G_CTTCPOPDONE(x) (((x) >> S_CTTCPOPDONE) & M_CTTCPOPDONE)
28428 
28429 #define S_CDBDONE    8
28430 #define M_CDBDONE    0xfU
28431 #define V_CDBDONE(x) ((x) << S_CDBDONE)
28432 #define G_CDBDONE(x) (((x) >> S_CDBDONE) & M_CDBDONE)
28433 
28434 #define S_CISSFIFODONE    4
28435 #define M_CISSFIFODONE    0xfU
28436 #define V_CISSFIFODONE(x) ((x) << S_CISSFIFODONE)
28437 #define G_CISSFIFODONE(x) (((x) >> S_CISSFIFODONE) & M_CISSFIFODONE)
28438 
28439 #define S_CTXPKTCSUMDONE    0
28440 #define M_CTXPKTCSUMDONE    0xfU
28441 #define V_CTXPKTCSUMDONE(x) ((x) << S_CTXPKTCSUMDONE)
28442 #define G_CTXPKTCSUMDONE(x) (((x) >> S_CTXPKTCSUMDONE) & M_CTXPKTCSUMDONE)
28443 
28444 #define S_CARBVALID    28
28445 #define M_CARBVALID    0xfU
28446 #define V_CARBVALID(x) ((x) << S_CARBVALID)
28447 #define G_CARBVALID(x) (((x) >> S_CARBVALID) & M_CARBVALID)
28448 
28449 #define S_CCPL5DONE    24
28450 #define M_CCPL5DONE    0xfU
28451 #define V_CCPL5DONE(x) ((x) << S_CCPL5DONE)
28452 #define G_CCPL5DONE(x) (((x) >> S_CCPL5DONE) & M_CCPL5DONE)
28453 
28454 #define S_CTCPOPDONE    12
28455 #define M_CTCPOPDONE    0xfU
28456 #define V_CTCPOPDONE(x) ((x) << S_CTCPOPDONE)
28457 #define G_CTCPOPDONE(x) (((x) >> S_CTCPOPDONE) & M_CTCPOPDONE)
28458 
28459 #define A_TP_DBG_CSIDE_ARBIT 0x248
28460 
28461 #define S_CPLVALID3    31
28462 #define V_CPLVALID3(x) ((x) << S_CPLVALID3)
28463 #define F_CPLVALID3    V_CPLVALID3(1U)
28464 
28465 #define S_PLDVALID3    30
28466 #define V_PLDVALID3(x) ((x) << S_PLDVALID3)
28467 #define F_PLDVALID3    V_PLDVALID3(1U)
28468 
28469 #define S_CRCVALID3    29
28470 #define V_CRCVALID3(x) ((x) << S_CRCVALID3)
28471 #define F_CRCVALID3    V_CRCVALID3(1U)
28472 
28473 #define S_ISSVALID3    28
28474 #define V_ISSVALID3(x) ((x) << S_ISSVALID3)
28475 #define F_ISSVALID3    V_ISSVALID3(1U)
28476 
28477 #define S_DBVALID3    27
28478 #define V_DBVALID3(x) ((x) << S_DBVALID3)
28479 #define F_DBVALID3    V_DBVALID3(1U)
28480 
28481 #define S_CHKVALID3    26
28482 #define V_CHKVALID3(x) ((x) << S_CHKVALID3)
28483 #define F_CHKVALID3    V_CHKVALID3(1U)
28484 
28485 #define S_ZRPVALID3    25
28486 #define V_ZRPVALID3(x) ((x) << S_ZRPVALID3)
28487 #define F_ZRPVALID3    V_ZRPVALID3(1U)
28488 
28489 #define S_ERRVALID3    24
28490 #define V_ERRVALID3(x) ((x) << S_ERRVALID3)
28491 #define F_ERRVALID3    V_ERRVALID3(1U)
28492 
28493 #define S_CPLVALID2    23
28494 #define V_CPLVALID2(x) ((x) << S_CPLVALID2)
28495 #define F_CPLVALID2    V_CPLVALID2(1U)
28496 
28497 #define S_PLDVALID2    22
28498 #define V_PLDVALID2(x) ((x) << S_PLDVALID2)
28499 #define F_PLDVALID2    V_PLDVALID2(1U)
28500 
28501 #define S_CRCVALID2    21
28502 #define V_CRCVALID2(x) ((x) << S_CRCVALID2)
28503 #define F_CRCVALID2    V_CRCVALID2(1U)
28504 
28505 #define S_ISSVALID2    20
28506 #define V_ISSVALID2(x) ((x) << S_ISSVALID2)
28507 #define F_ISSVALID2    V_ISSVALID2(1U)
28508 
28509 #define S_DBVALID2    19
28510 #define V_DBVALID2(x) ((x) << S_DBVALID2)
28511 #define F_DBVALID2    V_DBVALID2(1U)
28512 
28513 #define S_CHKVALID2    18
28514 #define V_CHKVALID2(x) ((x) << S_CHKVALID2)
28515 #define F_CHKVALID2    V_CHKVALID2(1U)
28516 
28517 #define S_ZRPVALID2    17
28518 #define V_ZRPVALID2(x) ((x) << S_ZRPVALID2)
28519 #define F_ZRPVALID2    V_ZRPVALID2(1U)
28520 
28521 #define S_ERRVALID2    16
28522 #define V_ERRVALID2(x) ((x) << S_ERRVALID2)
28523 #define F_ERRVALID2    V_ERRVALID2(1U)
28524 
28525 #define S_CPLVALID1    15
28526 #define V_CPLVALID1(x) ((x) << S_CPLVALID1)
28527 #define F_CPLVALID1    V_CPLVALID1(1U)
28528 
28529 #define S_PLDVALID1    14
28530 #define V_PLDVALID1(x) ((x) << S_PLDVALID1)
28531 #define F_PLDVALID1    V_PLDVALID1(1U)
28532 
28533 #define S_CRCVALID1    13
28534 #define V_CRCVALID1(x) ((x) << S_CRCVALID1)
28535 #define F_CRCVALID1    V_CRCVALID1(1U)
28536 
28537 #define S_ISSVALID1    12
28538 #define V_ISSVALID1(x) ((x) << S_ISSVALID1)
28539 #define F_ISSVALID1    V_ISSVALID1(1U)
28540 
28541 #define S_DBVALID1    11
28542 #define V_DBVALID1(x) ((x) << S_DBVALID1)
28543 #define F_DBVALID1    V_DBVALID1(1U)
28544 
28545 #define S_CHKVALID1    10
28546 #define V_CHKVALID1(x) ((x) << S_CHKVALID1)
28547 #define F_CHKVALID1    V_CHKVALID1(1U)
28548 
28549 #define S_ZRPVALID1    9
28550 #define V_ZRPVALID1(x) ((x) << S_ZRPVALID1)
28551 #define F_ZRPVALID1    V_ZRPVALID1(1U)
28552 
28553 #define S_ERRVALID1    8
28554 #define V_ERRVALID1(x) ((x) << S_ERRVALID1)
28555 #define F_ERRVALID1    V_ERRVALID1(1U)
28556 
28557 #define S_CPLVALID0    7
28558 #define V_CPLVALID0(x) ((x) << S_CPLVALID0)
28559 #define F_CPLVALID0    V_CPLVALID0(1U)
28560 
28561 #define S_PLDVALID0    6
28562 #define V_PLDVALID0(x) ((x) << S_PLDVALID0)
28563 #define F_PLDVALID0    V_PLDVALID0(1U)
28564 
28565 #define S_CRCVALID0    5
28566 #define V_CRCVALID0(x) ((x) << S_CRCVALID0)
28567 #define F_CRCVALID0    V_CRCVALID0(1U)
28568 
28569 #define S_ISSVALID0    4
28570 #define V_ISSVALID0(x) ((x) << S_ISSVALID0)
28571 #define F_ISSVALID0    V_ISSVALID0(1U)
28572 
28573 #define S_DBVALID0    3
28574 #define V_DBVALID0(x) ((x) << S_DBVALID0)
28575 #define F_DBVALID0    V_DBVALID0(1U)
28576 
28577 #define S_CHKVALID0    2
28578 #define V_CHKVALID0(x) ((x) << S_CHKVALID0)
28579 #define F_CHKVALID0    V_CHKVALID0(1U)
28580 
28581 #define S_ZRPVALID0    1
28582 #define V_ZRPVALID0(x) ((x) << S_ZRPVALID0)
28583 #define F_ZRPVALID0    V_ZRPVALID0(1U)
28584 
28585 #define S_ERRVALID0    0
28586 #define V_ERRVALID0(x) ((x) << S_ERRVALID0)
28587 #define F_ERRVALID0    V_ERRVALID0(1U)
28588 
28589 #define A_TP_DBG_CSIDE_TRACE_CNT 0x24a
28590 
28591 #define S_TRCSOPCNT    24
28592 #define M_TRCSOPCNT    0xffU
28593 #define V_TRCSOPCNT(x) ((x) << S_TRCSOPCNT)
28594 #define G_TRCSOPCNT(x) (((x) >> S_TRCSOPCNT) & M_TRCSOPCNT)
28595 
28596 #define S_TRCEOPCNT    16
28597 #define M_TRCEOPCNT    0xffU
28598 #define V_TRCEOPCNT(x) ((x) << S_TRCEOPCNT)
28599 #define G_TRCEOPCNT(x) (((x) >> S_TRCEOPCNT) & M_TRCEOPCNT)
28600 
28601 #define S_TRCFLTHIT    12
28602 #define M_TRCFLTHIT    0xfU
28603 #define V_TRCFLTHIT(x) ((x) << S_TRCFLTHIT)
28604 #define G_TRCFLTHIT(x) (((x) >> S_TRCFLTHIT) & M_TRCFLTHIT)
28605 
28606 #define S_TRCRNTPKT    8
28607 #define M_TRCRNTPKT    0xfU
28608 #define V_TRCRNTPKT(x) ((x) << S_TRCRNTPKT)
28609 #define G_TRCRNTPKT(x) (((x) >> S_TRCRNTPKT) & M_TRCRNTPKT)
28610 
28611 #define S_TRCPKTLEN    0
28612 #define M_TRCPKTLEN    0xffU
28613 #define V_TRCPKTLEN(x) ((x) << S_TRCPKTLEN)
28614 #define G_TRCPKTLEN(x) (((x) >> S_TRCPKTLEN) & M_TRCPKTLEN)
28615 
28616 #define A_TP_DBG_CSIDE_TRACE_RSS 0x24b
28617 #define A_TP_VLN_CONFIG 0x24c
28618 
28619 #define S_ETHTYPEQINQ    16
28620 #define M_ETHTYPEQINQ    0xffffU
28621 #define V_ETHTYPEQINQ(x) ((x) << S_ETHTYPEQINQ)
28622 #define G_ETHTYPEQINQ(x) (((x) >> S_ETHTYPEQINQ) & M_ETHTYPEQINQ)
28623 
28624 #define S_ETHTYPEVLAN    0
28625 #define M_ETHTYPEVLAN    0xffffU
28626 #define V_ETHTYPEVLAN(x) ((x) << S_ETHTYPEVLAN)
28627 #define G_ETHTYPEVLAN(x) (((x) >> S_ETHTYPEVLAN) & M_ETHTYPEVLAN)
28628 
28629 #define A_TP_DBG_CSIDE_ARBIT_WAIT0 0x24d
28630 #define A_TP_DBG_CSIDE_ARBIT_WAIT1 0x24e
28631 #define A_TP_DBG_CSIDE_ARBIT_CNT0 0x24f
28632 #define A_TP_DBG_CSIDE_ARBIT_CNT1 0x250
28633 #define A_TP_FIFO_CONFIG 0x8c0
28634 
28635 #define S_CH1_OUTPUT    27
28636 #define M_CH1_OUTPUT    0x1fU
28637 #define V_CH1_OUTPUT(x) ((x) << S_CH1_OUTPUT)
28638 #define G_CH1_OUTPUT(x) (((x) >> S_CH1_OUTPUT) & M_CH1_OUTPUT)
28639 
28640 #define S_CH2_OUTPUT    22
28641 #define M_CH2_OUTPUT    0x1fU
28642 #define V_CH2_OUTPUT(x) ((x) << S_CH2_OUTPUT)
28643 #define G_CH2_OUTPUT(x) (((x) >> S_CH2_OUTPUT) & M_CH2_OUTPUT)
28644 
28645 #define S_STROBE1    16
28646 #define V_STROBE1(x) ((x) << S_STROBE1)
28647 #define F_STROBE1    V_STROBE1(1U)
28648 
28649 #define S_CH1_INPUT    11
28650 #define M_CH1_INPUT    0x1fU
28651 #define V_CH1_INPUT(x) ((x) << S_CH1_INPUT)
28652 #define G_CH1_INPUT(x) (((x) >> S_CH1_INPUT) & M_CH1_INPUT)
28653 
28654 #define S_CH2_INPUT    6
28655 #define M_CH2_INPUT    0x1fU
28656 #define V_CH2_INPUT(x) ((x) << S_CH2_INPUT)
28657 #define G_CH2_INPUT(x) (((x) >> S_CH2_INPUT) & M_CH2_INPUT)
28658 
28659 #define S_CH3_INPUT    1
28660 #define M_CH3_INPUT    0x1fU
28661 #define V_CH3_INPUT(x) ((x) << S_CH3_INPUT)
28662 #define G_CH3_INPUT(x) (((x) >> S_CH3_INPUT) & M_CH3_INPUT)
28663 
28664 #define S_STROBE0    0
28665 #define V_STROBE0(x) ((x) << S_STROBE0)
28666 #define F_STROBE0    V_STROBE0(1U)
28667 
28668 #define A_TP_MIB_MAC_IN_ERR_0 0x0
28669 #define A_TP_MIB_MAC_IN_ERR_1 0x1
28670 #define A_TP_MIB_MAC_IN_ERR_2 0x2
28671 #define A_TP_MIB_MAC_IN_ERR_3 0x3
28672 #define A_TP_MIB_HDR_IN_ERR_0 0x4
28673 #define A_TP_MIB_HDR_IN_ERR_1 0x5
28674 #define A_TP_MIB_HDR_IN_ERR_2 0x6
28675 #define A_TP_MIB_HDR_IN_ERR_3 0x7
28676 #define A_TP_MIB_TCP_IN_ERR_0 0x8
28677 #define A_TP_MIB_TCP_IN_ERR_1 0x9
28678 #define A_TP_MIB_TCP_IN_ERR_2 0xa
28679 #define A_TP_MIB_TCP_IN_ERR_3 0xb
28680 #define A_TP_MIB_TCP_OUT_RST 0xc
28681 #define A_TP_MIB_TCP_IN_SEG_HI 0x10
28682 #define A_TP_MIB_TCP_IN_SEG_LO 0x11
28683 #define A_TP_MIB_TCP_OUT_SEG_HI 0x12
28684 #define A_TP_MIB_TCP_OUT_SEG_LO 0x13
28685 #define A_TP_MIB_TCP_RXT_SEG_HI 0x14
28686 #define A_TP_MIB_TCP_RXT_SEG_LO 0x15
28687 #define A_TP_MIB_TNL_CNG_DROP_0 0x18
28688 #define A_TP_MIB_TNL_CNG_DROP_1 0x19
28689 #define A_TP_MIB_TNL_CNG_DROP_2 0x1a
28690 #define A_TP_MIB_TNL_CNG_DROP_3 0x1b
28691 #define A_TP_MIB_OFD_CHN_DROP_0 0x1c
28692 #define A_TP_MIB_OFD_CHN_DROP_1 0x1d
28693 #define A_TP_MIB_OFD_CHN_DROP_2 0x1e
28694 #define A_TP_MIB_OFD_CHN_DROP_3 0x1f
28695 #define A_TP_MIB_TNL_OUT_PKT_0 0x20
28696 #define A_TP_MIB_TNL_OUT_PKT_1 0x21
28697 #define A_TP_MIB_TNL_OUT_PKT_2 0x22
28698 #define A_TP_MIB_TNL_OUT_PKT_3 0x23
28699 #define A_TP_MIB_TNL_IN_PKT_0 0x24
28700 #define A_TP_MIB_TNL_IN_PKT_1 0x25
28701 #define A_TP_MIB_TNL_IN_PKT_2 0x26
28702 #define A_TP_MIB_TNL_IN_PKT_3 0x27
28703 #define A_TP_MIB_TCP_V6IN_ERR_0 0x28
28704 #define A_TP_MIB_TCP_V6IN_ERR_1 0x29
28705 #define A_TP_MIB_TCP_V6IN_ERR_2 0x2a
28706 #define A_TP_MIB_TCP_V6IN_ERR_3 0x2b
28707 #define A_TP_MIB_TCP_V6OUT_RST 0x2c
28708 #define A_TP_MIB_TCP_V6IN_SEG_HI 0x30
28709 #define A_TP_MIB_TCP_V6IN_SEG_LO 0x31
28710 #define A_TP_MIB_TCP_V6OUT_SEG_HI 0x32
28711 #define A_TP_MIB_TCP_V6OUT_SEG_LO 0x33
28712 #define A_TP_MIB_TCP_V6RXT_SEG_HI 0x34
28713 #define A_TP_MIB_TCP_V6RXT_SEG_LO 0x35
28714 #define A_TP_MIB_OFD_ARP_DROP 0x36
28715 #define A_TP_MIB_OFD_DFR_DROP 0x37
28716 #define A_TP_MIB_CPL_IN_REQ_0 0x38
28717 #define A_TP_MIB_CPL_IN_REQ_1 0x39
28718 #define A_TP_MIB_CPL_IN_REQ_2 0x3a
28719 #define A_TP_MIB_CPL_IN_REQ_3 0x3b
28720 #define A_TP_MIB_CPL_OUT_RSP_0 0x3c
28721 #define A_TP_MIB_CPL_OUT_RSP_1 0x3d
28722 #define A_TP_MIB_CPL_OUT_RSP_2 0x3e
28723 #define A_TP_MIB_CPL_OUT_RSP_3 0x3f
28724 #define A_TP_MIB_TNL_LPBK_0 0x40
28725 #define A_TP_MIB_TNL_LPBK_1 0x41
28726 #define A_TP_MIB_TNL_LPBK_2 0x42
28727 #define A_TP_MIB_TNL_LPBK_3 0x43
28728 #define A_TP_MIB_TNL_DROP_0 0x44
28729 #define A_TP_MIB_TNL_DROP_1 0x45
28730 #define A_TP_MIB_TNL_DROP_2 0x46
28731 #define A_TP_MIB_TNL_DROP_3 0x47
28732 #define A_TP_MIB_FCOE_DDP_0 0x48
28733 #define A_TP_MIB_FCOE_DDP_1 0x49
28734 #define A_TP_MIB_FCOE_DDP_2 0x4a
28735 #define A_TP_MIB_FCOE_DDP_3 0x4b
28736 #define A_TP_MIB_FCOE_DROP_0 0x4c
28737 #define A_TP_MIB_FCOE_DROP_1 0x4d
28738 #define A_TP_MIB_FCOE_DROP_2 0x4e
28739 #define A_TP_MIB_FCOE_DROP_3 0x4f
28740 #define A_TP_MIB_FCOE_BYTE_0_HI 0x50
28741 #define A_TP_MIB_FCOE_BYTE_0_LO 0x51
28742 #define A_TP_MIB_FCOE_BYTE_1_HI 0x52
28743 #define A_TP_MIB_FCOE_BYTE_1_LO 0x53
28744 #define A_TP_MIB_FCOE_BYTE_2_HI 0x54
28745 #define A_TP_MIB_FCOE_BYTE_2_LO 0x55
28746 #define A_TP_MIB_FCOE_BYTE_3_HI 0x56
28747 #define A_TP_MIB_FCOE_BYTE_3_LO 0x57
28748 #define A_TP_MIB_OFD_VLN_DROP_0 0x58
28749 #define A_TP_MIB_OFD_VLN_DROP_1 0x59
28750 #define A_TP_MIB_OFD_VLN_DROP_2 0x5a
28751 #define A_TP_MIB_OFD_VLN_DROP_3 0x5b
28752 #define A_TP_MIB_USM_PKTS 0x5c
28753 #define A_TP_MIB_USM_DROP 0x5d
28754 #define A_TP_MIB_USM_BYTES_HI 0x5e
28755 #define A_TP_MIB_USM_BYTES_LO 0x5f
28756 #define A_TP_MIB_TID_DEL 0x60
28757 #define A_TP_MIB_TID_INV 0x61
28758 #define A_TP_MIB_TID_ACT 0x62
28759 #define A_TP_MIB_TID_PAS 0x63
28760 #define A_TP_MIB_RQE_DFR_PKT 0x64
28761 #define A_TP_MIB_RQE_DFR_MOD 0x65
28762 #define A_TP_MIB_CPL_OUT_ERR_0 0x68
28763 #define A_TP_MIB_CPL_OUT_ERR_1 0x69
28764 #define A_TP_MIB_CPL_OUT_ERR_2 0x6a
28765 #define A_TP_MIB_CPL_OUT_ERR_3 0x6b
28766 #define A_TP_MIB_ENG_LINE_0 0x6c
28767 #define A_TP_MIB_ENG_LINE_1 0x6d
28768 #define A_TP_MIB_ENG_LINE_2 0x6e
28769 #define A_TP_MIB_ENG_LINE_3 0x6f
28770 #define A_TP_MIB_TNL_ERR_0 0x70
28771 #define A_TP_MIB_TNL_ERR_1 0x71
28772 #define A_TP_MIB_TNL_ERR_2 0x72
28773 #define A_TP_MIB_TNL_ERR_3 0x73
28774 
28775 /* registers for module ULP_TX */
28776 #define ULP_TX_BASE_ADDR 0x8dc0
28777 
28778 #define A_ULP_TX_CONFIG 0x8dc0
28779 
28780 #define S_STAG_MIX_ENABLE    2
28781 #define V_STAG_MIX_ENABLE(x) ((x) << S_STAG_MIX_ENABLE)
28782 #define F_STAG_MIX_ENABLE    V_STAG_MIX_ENABLE(1U)
28783 
28784 #define S_STAGF_FIX_DISABLE    1
28785 #define V_STAGF_FIX_DISABLE(x) ((x) << S_STAGF_FIX_DISABLE)
28786 #define F_STAGF_FIX_DISABLE    V_STAGF_FIX_DISABLE(1U)
28787 
28788 #define S_EXTRA_TAG_INSERTION_ENABLE    0
28789 #define V_EXTRA_TAG_INSERTION_ENABLE(x) ((x) << S_EXTRA_TAG_INSERTION_ENABLE)
28790 #define F_EXTRA_TAG_INSERTION_ENABLE    V_EXTRA_TAG_INSERTION_ENABLE(1U)
28791 
28792 #define S_PHYS_ADDR_RESP_EN    6
28793 #define V_PHYS_ADDR_RESP_EN(x) ((x) << S_PHYS_ADDR_RESP_EN)
28794 #define F_PHYS_ADDR_RESP_EN    V_PHYS_ADDR_RESP_EN(1U)
28795 
28796 #define S_ENDIANESS_CHANGE    5
28797 #define V_ENDIANESS_CHANGE(x) ((x) << S_ENDIANESS_CHANGE)
28798 #define F_ENDIANESS_CHANGE    V_ENDIANESS_CHANGE(1U)
28799 
28800 #define S_ERR_RTAG_EN    4
28801 #define V_ERR_RTAG_EN(x) ((x) << S_ERR_RTAG_EN)
28802 #define F_ERR_RTAG_EN    V_ERR_RTAG_EN(1U)
28803 
28804 #define S_TSO_ETHLEN_EN    3
28805 #define V_TSO_ETHLEN_EN(x) ((x) << S_TSO_ETHLEN_EN)
28806 #define F_TSO_ETHLEN_EN    V_TSO_ETHLEN_EN(1U)
28807 
28808 #define S_EMSG_MORE_INFO    2
28809 #define V_EMSG_MORE_INFO(x) ((x) << S_EMSG_MORE_INFO)
28810 #define F_EMSG_MORE_INFO    V_EMSG_MORE_INFO(1U)
28811 
28812 #define S_LOSDR    1
28813 #define V_LOSDR(x) ((x) << S_LOSDR)
28814 #define F_LOSDR    V_LOSDR(1U)
28815 
28816 #define S_ULIMIT_EXCLUSIVE_FIX    16
28817 #define V_ULIMIT_EXCLUSIVE_FIX(x) ((x) << S_ULIMIT_EXCLUSIVE_FIX)
28818 #define F_ULIMIT_EXCLUSIVE_FIX    V_ULIMIT_EXCLUSIVE_FIX(1U)
28819 
28820 #define S_ISO_A_FLAG_EN    15
28821 #define V_ISO_A_FLAG_EN(x) ((x) << S_ISO_A_FLAG_EN)
28822 #define F_ISO_A_FLAG_EN    V_ISO_A_FLAG_EN(1U)
28823 
28824 #define S_IWARP_SEQ_FLIT_DIS    14
28825 #define V_IWARP_SEQ_FLIT_DIS(x) ((x) << S_IWARP_SEQ_FLIT_DIS)
28826 #define F_IWARP_SEQ_FLIT_DIS    V_IWARP_SEQ_FLIT_DIS(1U)
28827 
28828 #define S_MR_SIZE_FIX_EN    13
28829 #define V_MR_SIZE_FIX_EN(x) ((x) << S_MR_SIZE_FIX_EN)
28830 #define F_MR_SIZE_FIX_EN    V_MR_SIZE_FIX_EN(1U)
28831 
28832 #define S_T10_ISO_FIX_EN    12
28833 #define V_T10_ISO_FIX_EN(x) ((x) << S_T10_ISO_FIX_EN)
28834 #define F_T10_ISO_FIX_EN    V_T10_ISO_FIX_EN(1U)
28835 
28836 #define S_CPL_FLAGS_UPDATE_EN    11
28837 #define V_CPL_FLAGS_UPDATE_EN(x) ((x) << S_CPL_FLAGS_UPDATE_EN)
28838 #define F_CPL_FLAGS_UPDATE_EN    V_CPL_FLAGS_UPDATE_EN(1U)
28839 
28840 #define S_IWARP_SEQ_UPDATE_EN    10
28841 #define V_IWARP_SEQ_UPDATE_EN(x) ((x) << S_IWARP_SEQ_UPDATE_EN)
28842 #define F_IWARP_SEQ_UPDATE_EN    V_IWARP_SEQ_UPDATE_EN(1U)
28843 
28844 #define S_SEQ_UPDATE_EN    9
28845 #define V_SEQ_UPDATE_EN(x) ((x) << S_SEQ_UPDATE_EN)
28846 #define F_SEQ_UPDATE_EN    V_SEQ_UPDATE_EN(1U)
28847 
28848 #define S_ERR_ITT_EN    8
28849 #define V_ERR_ITT_EN(x) ((x) << S_ERR_ITT_EN)
28850 #define F_ERR_ITT_EN    V_ERR_ITT_EN(1U)
28851 
28852 #define S_ATOMIC_FIX_DIS    7
28853 #define V_ATOMIC_FIX_DIS(x) ((x) << S_ATOMIC_FIX_DIS)
28854 #define F_ATOMIC_FIX_DIS    V_ATOMIC_FIX_DIS(1U)
28855 
28856 #define A_ULP_TX_PERR_INJECT 0x8dc4
28857 #define A_ULP_TX_INT_ENABLE 0x8dc8
28858 
28859 #define S_PBL_BOUND_ERR_CH3    31
28860 #define V_PBL_BOUND_ERR_CH3(x) ((x) << S_PBL_BOUND_ERR_CH3)
28861 #define F_PBL_BOUND_ERR_CH3    V_PBL_BOUND_ERR_CH3(1U)
28862 
28863 #define S_PBL_BOUND_ERR_CH2    30
28864 #define V_PBL_BOUND_ERR_CH2(x) ((x) << S_PBL_BOUND_ERR_CH2)
28865 #define F_PBL_BOUND_ERR_CH2    V_PBL_BOUND_ERR_CH2(1U)
28866 
28867 #define S_PBL_BOUND_ERR_CH1    29
28868 #define V_PBL_BOUND_ERR_CH1(x) ((x) << S_PBL_BOUND_ERR_CH1)
28869 #define F_PBL_BOUND_ERR_CH1    V_PBL_BOUND_ERR_CH1(1U)
28870 
28871 #define S_PBL_BOUND_ERR_CH0    28
28872 #define V_PBL_BOUND_ERR_CH0(x) ((x) << S_PBL_BOUND_ERR_CH0)
28873 #define F_PBL_BOUND_ERR_CH0    V_PBL_BOUND_ERR_CH0(1U)
28874 
28875 #define S_SGE2ULP_FIFO_PERR_SET3    27
28876 #define V_SGE2ULP_FIFO_PERR_SET3(x) ((x) << S_SGE2ULP_FIFO_PERR_SET3)
28877 #define F_SGE2ULP_FIFO_PERR_SET3    V_SGE2ULP_FIFO_PERR_SET3(1U)
28878 
28879 #define S_SGE2ULP_FIFO_PERR_SET2    26
28880 #define V_SGE2ULP_FIFO_PERR_SET2(x) ((x) << S_SGE2ULP_FIFO_PERR_SET2)
28881 #define F_SGE2ULP_FIFO_PERR_SET2    V_SGE2ULP_FIFO_PERR_SET2(1U)
28882 
28883 #define S_SGE2ULP_FIFO_PERR_SET1    25
28884 #define V_SGE2ULP_FIFO_PERR_SET1(x) ((x) << S_SGE2ULP_FIFO_PERR_SET1)
28885 #define F_SGE2ULP_FIFO_PERR_SET1    V_SGE2ULP_FIFO_PERR_SET1(1U)
28886 
28887 #define S_SGE2ULP_FIFO_PERR_SET0    24
28888 #define V_SGE2ULP_FIFO_PERR_SET0(x) ((x) << S_SGE2ULP_FIFO_PERR_SET0)
28889 #define F_SGE2ULP_FIFO_PERR_SET0    V_SGE2ULP_FIFO_PERR_SET0(1U)
28890 
28891 #define S_CIM2ULP_FIFO_PERR_SET3    23
28892 #define V_CIM2ULP_FIFO_PERR_SET3(x) ((x) << S_CIM2ULP_FIFO_PERR_SET3)
28893 #define F_CIM2ULP_FIFO_PERR_SET3    V_CIM2ULP_FIFO_PERR_SET3(1U)
28894 
28895 #define S_CIM2ULP_FIFO_PERR_SET2    22
28896 #define V_CIM2ULP_FIFO_PERR_SET2(x) ((x) << S_CIM2ULP_FIFO_PERR_SET2)
28897 #define F_CIM2ULP_FIFO_PERR_SET2    V_CIM2ULP_FIFO_PERR_SET2(1U)
28898 
28899 #define S_CIM2ULP_FIFO_PERR_SET1    21
28900 #define V_CIM2ULP_FIFO_PERR_SET1(x) ((x) << S_CIM2ULP_FIFO_PERR_SET1)
28901 #define F_CIM2ULP_FIFO_PERR_SET1    V_CIM2ULP_FIFO_PERR_SET1(1U)
28902 
28903 #define S_CIM2ULP_FIFO_PERR_SET0    20
28904 #define V_CIM2ULP_FIFO_PERR_SET0(x) ((x) << S_CIM2ULP_FIFO_PERR_SET0)
28905 #define F_CIM2ULP_FIFO_PERR_SET0    V_CIM2ULP_FIFO_PERR_SET0(1U)
28906 
28907 #define S_CQE_FIFO_PERR_SET3    19
28908 #define V_CQE_FIFO_PERR_SET3(x) ((x) << S_CQE_FIFO_PERR_SET3)
28909 #define F_CQE_FIFO_PERR_SET3    V_CQE_FIFO_PERR_SET3(1U)
28910 
28911 #define S_CQE_FIFO_PERR_SET2    18
28912 #define V_CQE_FIFO_PERR_SET2(x) ((x) << S_CQE_FIFO_PERR_SET2)
28913 #define F_CQE_FIFO_PERR_SET2    V_CQE_FIFO_PERR_SET2(1U)
28914 
28915 #define S_CQE_FIFO_PERR_SET1    17
28916 #define V_CQE_FIFO_PERR_SET1(x) ((x) << S_CQE_FIFO_PERR_SET1)
28917 #define F_CQE_FIFO_PERR_SET1    V_CQE_FIFO_PERR_SET1(1U)
28918 
28919 #define S_CQE_FIFO_PERR_SET0    16
28920 #define V_CQE_FIFO_PERR_SET0(x) ((x) << S_CQE_FIFO_PERR_SET0)
28921 #define F_CQE_FIFO_PERR_SET0    V_CQE_FIFO_PERR_SET0(1U)
28922 
28923 #define S_PBL_FIFO_PERR_SET3    15
28924 #define V_PBL_FIFO_PERR_SET3(x) ((x) << S_PBL_FIFO_PERR_SET3)
28925 #define F_PBL_FIFO_PERR_SET3    V_PBL_FIFO_PERR_SET3(1U)
28926 
28927 #define S_PBL_FIFO_PERR_SET2    14
28928 #define V_PBL_FIFO_PERR_SET2(x) ((x) << S_PBL_FIFO_PERR_SET2)
28929 #define F_PBL_FIFO_PERR_SET2    V_PBL_FIFO_PERR_SET2(1U)
28930 
28931 #define S_PBL_FIFO_PERR_SET1    13
28932 #define V_PBL_FIFO_PERR_SET1(x) ((x) << S_PBL_FIFO_PERR_SET1)
28933 #define F_PBL_FIFO_PERR_SET1    V_PBL_FIFO_PERR_SET1(1U)
28934 
28935 #define S_PBL_FIFO_PERR_SET0    12
28936 #define V_PBL_FIFO_PERR_SET0(x) ((x) << S_PBL_FIFO_PERR_SET0)
28937 #define F_PBL_FIFO_PERR_SET0    V_PBL_FIFO_PERR_SET0(1U)
28938 
28939 #define S_CMD_FIFO_PERR_SET3    11
28940 #define V_CMD_FIFO_PERR_SET3(x) ((x) << S_CMD_FIFO_PERR_SET3)
28941 #define F_CMD_FIFO_PERR_SET3    V_CMD_FIFO_PERR_SET3(1U)
28942 
28943 #define S_CMD_FIFO_PERR_SET2    10
28944 #define V_CMD_FIFO_PERR_SET2(x) ((x) << S_CMD_FIFO_PERR_SET2)
28945 #define F_CMD_FIFO_PERR_SET2    V_CMD_FIFO_PERR_SET2(1U)
28946 
28947 #define S_CMD_FIFO_PERR_SET1    9
28948 #define V_CMD_FIFO_PERR_SET1(x) ((x) << S_CMD_FIFO_PERR_SET1)
28949 #define F_CMD_FIFO_PERR_SET1    V_CMD_FIFO_PERR_SET1(1U)
28950 
28951 #define S_CMD_FIFO_PERR_SET0    8
28952 #define V_CMD_FIFO_PERR_SET0(x) ((x) << S_CMD_FIFO_PERR_SET0)
28953 #define F_CMD_FIFO_PERR_SET0    V_CMD_FIFO_PERR_SET0(1U)
28954 
28955 #define S_LSO_HDR_SRAM_PERR_SET3    7
28956 #define V_LSO_HDR_SRAM_PERR_SET3(x) ((x) << S_LSO_HDR_SRAM_PERR_SET3)
28957 #define F_LSO_HDR_SRAM_PERR_SET3    V_LSO_HDR_SRAM_PERR_SET3(1U)
28958 
28959 #define S_LSO_HDR_SRAM_PERR_SET2    6
28960 #define V_LSO_HDR_SRAM_PERR_SET2(x) ((x) << S_LSO_HDR_SRAM_PERR_SET2)
28961 #define F_LSO_HDR_SRAM_PERR_SET2    V_LSO_HDR_SRAM_PERR_SET2(1U)
28962 
28963 #define S_LSO_HDR_SRAM_PERR_SET1    5
28964 #define V_LSO_HDR_SRAM_PERR_SET1(x) ((x) << S_LSO_HDR_SRAM_PERR_SET1)
28965 #define F_LSO_HDR_SRAM_PERR_SET1    V_LSO_HDR_SRAM_PERR_SET1(1U)
28966 
28967 #define S_LSO_HDR_SRAM_PERR_SET0    4
28968 #define V_LSO_HDR_SRAM_PERR_SET0(x) ((x) << S_LSO_HDR_SRAM_PERR_SET0)
28969 #define F_LSO_HDR_SRAM_PERR_SET0    V_LSO_HDR_SRAM_PERR_SET0(1U)
28970 
28971 #define S_IMM_DATA_PERR_SET_CH3    3
28972 #define V_IMM_DATA_PERR_SET_CH3(x) ((x) << S_IMM_DATA_PERR_SET_CH3)
28973 #define F_IMM_DATA_PERR_SET_CH3    V_IMM_DATA_PERR_SET_CH3(1U)
28974 
28975 #define S_IMM_DATA_PERR_SET_CH2    2
28976 #define V_IMM_DATA_PERR_SET_CH2(x) ((x) << S_IMM_DATA_PERR_SET_CH2)
28977 #define F_IMM_DATA_PERR_SET_CH2    V_IMM_DATA_PERR_SET_CH2(1U)
28978 
28979 #define S_IMM_DATA_PERR_SET_CH1    1
28980 #define V_IMM_DATA_PERR_SET_CH1(x) ((x) << S_IMM_DATA_PERR_SET_CH1)
28981 #define F_IMM_DATA_PERR_SET_CH1    V_IMM_DATA_PERR_SET_CH1(1U)
28982 
28983 #define S_IMM_DATA_PERR_SET_CH0    0
28984 #define V_IMM_DATA_PERR_SET_CH0(x) ((x) << S_IMM_DATA_PERR_SET_CH0)
28985 #define F_IMM_DATA_PERR_SET_CH0    V_IMM_DATA_PERR_SET_CH0(1U)
28986 
28987 #define A_ULP_TX_INT_CAUSE 0x8dcc
28988 #define A_ULP_TX_PERR_ENABLE 0x8dd0
28989 #define A_ULP_TX_TPT_LLIMIT 0x8dd4
28990 #define A_ULP_TX_TPT_ULIMIT 0x8dd8
28991 #define A_ULP_TX_PBL_LLIMIT 0x8ddc
28992 #define A_ULP_TX_PBL_ULIMIT 0x8de0
28993 #define A_ULP_TX_CPL_ERR_OFFSET 0x8de4
28994 #define A_ULP_TX_TLS_CTL 0x8de4
28995 
28996 #define S_TLSPERREN    4
28997 #define V_TLSPERREN(x) ((x) << S_TLSPERREN)
28998 #define F_TLSPERREN    V_TLSPERREN(1U)
28999 
29000 #define S_TLSPATHCTL    3
29001 #define V_TLSPATHCTL(x) ((x) << S_TLSPATHCTL)
29002 #define F_TLSPATHCTL    V_TLSPATHCTL(1U)
29003 
29004 #define S_TLSDISABLEIFUSE    2
29005 #define V_TLSDISABLEIFUSE(x) ((x) << S_TLSDISABLEIFUSE)
29006 #define F_TLSDISABLEIFUSE    V_TLSDISABLEIFUSE(1U)
29007 
29008 #define S_TLSDISABLECFUSE    1
29009 #define V_TLSDISABLECFUSE(x) ((x) << S_TLSDISABLECFUSE)
29010 #define F_TLSDISABLECFUSE    V_TLSDISABLECFUSE(1U)
29011 
29012 #define S_TLSDISABLE    0
29013 #define V_TLSDISABLE(x) ((x) << S_TLSDISABLE)
29014 #define F_TLSDISABLE    V_TLSDISABLE(1U)
29015 
29016 #define A_ULP_TX_CPL_ERR_MASK_L 0x8de8
29017 #define A_ULP_TX_CPL_ERR_MASK_H 0x8dec
29018 #define A_ULP_TX_CPL_ERR_VALUE_L 0x8df0
29019 #define A_ULP_TX_CPL_ERR_VALUE_H 0x8df4
29020 #define A_ULP_TX_CPL_PACK_SIZE1 0x8df8
29021 
29022 #define S_CH3SIZE1    24
29023 #define M_CH3SIZE1    0xffU
29024 #define V_CH3SIZE1(x) ((x) << S_CH3SIZE1)
29025 #define G_CH3SIZE1(x) (((x) >> S_CH3SIZE1) & M_CH3SIZE1)
29026 
29027 #define S_CH2SIZE1    16
29028 #define M_CH2SIZE1    0xffU
29029 #define V_CH2SIZE1(x) ((x) << S_CH2SIZE1)
29030 #define G_CH2SIZE1(x) (((x) >> S_CH2SIZE1) & M_CH2SIZE1)
29031 
29032 #define S_CH1SIZE1    8
29033 #define M_CH1SIZE1    0xffU
29034 #define V_CH1SIZE1(x) ((x) << S_CH1SIZE1)
29035 #define G_CH1SIZE1(x) (((x) >> S_CH1SIZE1) & M_CH1SIZE1)
29036 
29037 #define S_CH0SIZE1    0
29038 #define M_CH0SIZE1    0xffU
29039 #define V_CH0SIZE1(x) ((x) << S_CH0SIZE1)
29040 #define G_CH0SIZE1(x) (((x) >> S_CH0SIZE1) & M_CH0SIZE1)
29041 
29042 #define A_ULP_TX_CPL_PACK_SIZE2 0x8dfc
29043 
29044 #define S_CH3SIZE2    24
29045 #define M_CH3SIZE2    0xffU
29046 #define V_CH3SIZE2(x) ((x) << S_CH3SIZE2)
29047 #define G_CH3SIZE2(x) (((x) >> S_CH3SIZE2) & M_CH3SIZE2)
29048 
29049 #define S_CH2SIZE2    16
29050 #define M_CH2SIZE2    0xffU
29051 #define V_CH2SIZE2(x) ((x) << S_CH2SIZE2)
29052 #define G_CH2SIZE2(x) (((x) >> S_CH2SIZE2) & M_CH2SIZE2)
29053 
29054 #define S_CH1SIZE2    8
29055 #define M_CH1SIZE2    0xffU
29056 #define V_CH1SIZE2(x) ((x) << S_CH1SIZE2)
29057 #define G_CH1SIZE2(x) (((x) >> S_CH1SIZE2) & M_CH1SIZE2)
29058 
29059 #define S_CH0SIZE2    0
29060 #define M_CH0SIZE2    0xffU
29061 #define V_CH0SIZE2(x) ((x) << S_CH0SIZE2)
29062 #define G_CH0SIZE2(x) (((x) >> S_CH0SIZE2) & M_CH0SIZE2)
29063 
29064 #define A_ULP_TX_ERR_MSG2CIM 0x8e00
29065 #define A_ULP_TX_ERR_TABLE_BASE 0x8e04
29066 #define A_ULP_TX_ERR_CNT_CH0 0x8e10
29067 
29068 #define S_ERR_CNT0    0
29069 #define M_ERR_CNT0    0xfffffU
29070 #define V_ERR_CNT0(x) ((x) << S_ERR_CNT0)
29071 #define G_ERR_CNT0(x) (((x) >> S_ERR_CNT0) & M_ERR_CNT0)
29072 
29073 #define A_ULP_TX_ERR_CNT_CH1 0x8e14
29074 
29075 #define S_ERR_CNT1    0
29076 #define M_ERR_CNT1    0xfffffU
29077 #define V_ERR_CNT1(x) ((x) << S_ERR_CNT1)
29078 #define G_ERR_CNT1(x) (((x) >> S_ERR_CNT1) & M_ERR_CNT1)
29079 
29080 #define A_ULP_TX_ERR_CNT_CH2 0x8e18
29081 
29082 #define S_ERR_CNT2    0
29083 #define M_ERR_CNT2    0xfffffU
29084 #define V_ERR_CNT2(x) ((x) << S_ERR_CNT2)
29085 #define G_ERR_CNT2(x) (((x) >> S_ERR_CNT2) & M_ERR_CNT2)
29086 
29087 #define A_ULP_TX_ERR_CNT_CH3 0x8e1c
29088 
29089 #define S_ERR_CNT3    0
29090 #define M_ERR_CNT3    0xfffffU
29091 #define V_ERR_CNT3(x) ((x) << S_ERR_CNT3)
29092 #define G_ERR_CNT3(x) (((x) >> S_ERR_CNT3) & M_ERR_CNT3)
29093 
29094 #define A_ULP_TX_FC_SOF 0x8e20
29095 
29096 #define S_SOF_FS3    24
29097 #define M_SOF_FS3    0xffU
29098 #define V_SOF_FS3(x) ((x) << S_SOF_FS3)
29099 #define G_SOF_FS3(x) (((x) >> S_SOF_FS3) & M_SOF_FS3)
29100 
29101 #define S_SOF_FS2    16
29102 #define M_SOF_FS2    0xffU
29103 #define V_SOF_FS2(x) ((x) << S_SOF_FS2)
29104 #define G_SOF_FS2(x) (((x) >> S_SOF_FS2) & M_SOF_FS2)
29105 
29106 #define S_SOF_3    8
29107 #define M_SOF_3    0xffU
29108 #define V_SOF_3(x) ((x) << S_SOF_3)
29109 #define G_SOF_3(x) (((x) >> S_SOF_3) & M_SOF_3)
29110 
29111 #define S_SOF_2    0
29112 #define M_SOF_2    0xffU
29113 #define V_SOF_2(x) ((x) << S_SOF_2)
29114 #define G_SOF_2(x) (((x) >> S_SOF_2) & M_SOF_2)
29115 
29116 #define A_ULP_TX_FC_EOF 0x8e24
29117 
29118 #define S_EOF_LS3    24
29119 #define M_EOF_LS3    0xffU
29120 #define V_EOF_LS3(x) ((x) << S_EOF_LS3)
29121 #define G_EOF_LS3(x) (((x) >> S_EOF_LS3) & M_EOF_LS3)
29122 
29123 #define S_EOF_LS2    16
29124 #define M_EOF_LS2    0xffU
29125 #define V_EOF_LS2(x) ((x) << S_EOF_LS2)
29126 #define G_EOF_LS2(x) (((x) >> S_EOF_LS2) & M_EOF_LS2)
29127 
29128 #define S_EOF_3    8
29129 #define M_EOF_3    0xffU
29130 #define V_EOF_3(x) ((x) << S_EOF_3)
29131 #define G_EOF_3(x) (((x) >> S_EOF_3) & M_EOF_3)
29132 
29133 #define S_EOF_2    0
29134 #define M_EOF_2    0xffU
29135 #define V_EOF_2(x) ((x) << S_EOF_2)
29136 #define G_EOF_2(x) (((x) >> S_EOF_2) & M_EOF_2)
29137 
29138 #define A_ULP_TX_CGEN_GLOBAL 0x8e28
29139 
29140 #define S_ULP_TX_GLOBAL_CGEN    0
29141 #define V_ULP_TX_GLOBAL_CGEN(x) ((x) << S_ULP_TX_GLOBAL_CGEN)
29142 #define F_ULP_TX_GLOBAL_CGEN    V_ULP_TX_GLOBAL_CGEN(1U)
29143 
29144 #define A_ULP_TX_CGEN 0x8e2c
29145 
29146 #define S_ULP_TX_CGEN_STORAGE    8
29147 #define M_ULP_TX_CGEN_STORAGE    0xfU
29148 #define V_ULP_TX_CGEN_STORAGE(x) ((x) << S_ULP_TX_CGEN_STORAGE)
29149 #define G_ULP_TX_CGEN_STORAGE(x) (((x) >> S_ULP_TX_CGEN_STORAGE) & M_ULP_TX_CGEN_STORAGE)
29150 
29151 #define S_ULP_TX_CGEN_RDMA    4
29152 #define M_ULP_TX_CGEN_RDMA    0xfU
29153 #define V_ULP_TX_CGEN_RDMA(x) ((x) << S_ULP_TX_CGEN_RDMA)
29154 #define G_ULP_TX_CGEN_RDMA(x) (((x) >> S_ULP_TX_CGEN_RDMA) & M_ULP_TX_CGEN_RDMA)
29155 
29156 #define S_ULP_TX_CGEN_CHANNEL    0
29157 #define M_ULP_TX_CGEN_CHANNEL    0xfU
29158 #define V_ULP_TX_CGEN_CHANNEL(x) ((x) << S_ULP_TX_CGEN_CHANNEL)
29159 #define G_ULP_TX_CGEN_CHANNEL(x) (((x) >> S_ULP_TX_CGEN_CHANNEL) & M_ULP_TX_CGEN_CHANNEL)
29160 
29161 #define A_ULP_TX_ULP2TP_BIST_CMD 0x8e30
29162 #define A_ULP_TX_MEM_CFG 0x8e30
29163 
29164 #define S_WRREQ_SZ    0
29165 #define M_WRREQ_SZ    0x7U
29166 #define V_WRREQ_SZ(x) ((x) << S_WRREQ_SZ)
29167 #define G_WRREQ_SZ(x) (((x) >> S_WRREQ_SZ) & M_WRREQ_SZ)
29168 
29169 #define A_ULP_TX_ULP2TP_BIST_ERROR_CNT 0x8e34
29170 #define A_ULP_TX_PERR_INJECT_2 0x8e34
29171 
29172 #define S_T5_MEMSEL    1
29173 #define M_T5_MEMSEL    0x7U
29174 #define V_T5_MEMSEL(x) ((x) << S_T5_MEMSEL)
29175 #define G_T5_MEMSEL(x) (((x) >> S_T5_MEMSEL) & M_T5_MEMSEL)
29176 
29177 #define S_MEMSEL_ULPTX    1
29178 #define M_MEMSEL_ULPTX    0x1fU
29179 #define V_MEMSEL_ULPTX(x) ((x) << S_MEMSEL_ULPTX)
29180 #define G_MEMSEL_ULPTX(x) (((x) >> S_MEMSEL_ULPTX) & M_MEMSEL_ULPTX)
29181 
29182 #define A_ULP_TX_FPGA_CMD_CTRL 0x8e38
29183 #define A_ULP_TX_T5_FPGA_CMD_CTRL 0x8e38
29184 
29185 #define S_CHANNEL_SEL    12
29186 #define M_CHANNEL_SEL    0x3U
29187 #define V_CHANNEL_SEL(x) ((x) << S_CHANNEL_SEL)
29188 #define G_CHANNEL_SEL(x) (((x) >> S_CHANNEL_SEL) & M_CHANNEL_SEL)
29189 
29190 #define S_INTF_SEL    4
29191 #define M_INTF_SEL    0xfU
29192 #define V_INTF_SEL(x) ((x) << S_INTF_SEL)
29193 #define G_INTF_SEL(x) (((x) >> S_INTF_SEL) & M_INTF_SEL)
29194 
29195 #define S_NUM_FLITS    1
29196 #define M_NUM_FLITS    0x7U
29197 #define V_NUM_FLITS(x) ((x) << S_NUM_FLITS)
29198 #define G_NUM_FLITS(x) (((x) >> S_NUM_FLITS) & M_NUM_FLITS)
29199 
29200 #define S_CMD_GEN_EN    0
29201 #define V_CMD_GEN_EN(x) ((x) << S_CMD_GEN_EN)
29202 #define F_CMD_GEN_EN    V_CMD_GEN_EN(1U)
29203 
29204 #define A_ULP_TX_FPGA_CMD_0 0x8e3c
29205 #define A_ULP_TX_T5_FPGA_CMD_0 0x8e3c
29206 #define A_ULP_TX_FPGA_CMD_1 0x8e40
29207 #define A_ULP_TX_T5_FPGA_CMD_1 0x8e40
29208 #define A_ULP_TX_FPGA_CMD_2 0x8e44
29209 #define A_ULP_TX_T5_FPGA_CMD_2 0x8e44
29210 #define A_ULP_TX_FPGA_CMD_3 0x8e48
29211 #define A_ULP_TX_T5_FPGA_CMD_3 0x8e48
29212 #define A_ULP_TX_FPGA_CMD_4 0x8e4c
29213 #define A_ULP_TX_T5_FPGA_CMD_4 0x8e4c
29214 #define A_ULP_TX_FPGA_CMD_5 0x8e50
29215 #define A_ULP_TX_T5_FPGA_CMD_5 0x8e50
29216 #define A_ULP_TX_FPGA_CMD_6 0x8e54
29217 #define A_ULP_TX_T5_FPGA_CMD_6 0x8e54
29218 #define A_ULP_TX_FPGA_CMD_7 0x8e58
29219 #define A_ULP_TX_T5_FPGA_CMD_7 0x8e58
29220 #define A_ULP_TX_FPGA_CMD_8 0x8e5c
29221 #define A_ULP_TX_T5_FPGA_CMD_8 0x8e5c
29222 #define A_ULP_TX_FPGA_CMD_9 0x8e60
29223 #define A_ULP_TX_T5_FPGA_CMD_9 0x8e60
29224 #define A_ULP_TX_FPGA_CMD_10 0x8e64
29225 #define A_ULP_TX_T5_FPGA_CMD_10 0x8e64
29226 #define A_ULP_TX_FPGA_CMD_11 0x8e68
29227 #define A_ULP_TX_T5_FPGA_CMD_11 0x8e68
29228 #define A_ULP_TX_FPGA_CMD_12 0x8e6c
29229 #define A_ULP_TX_T5_FPGA_CMD_12 0x8e6c
29230 #define A_ULP_TX_FPGA_CMD_13 0x8e70
29231 #define A_ULP_TX_T5_FPGA_CMD_13 0x8e70
29232 #define A_ULP_TX_FPGA_CMD_14 0x8e74
29233 #define A_ULP_TX_T5_FPGA_CMD_14 0x8e74
29234 #define A_ULP_TX_FPGA_CMD_15 0x8e78
29235 #define A_ULP_TX_T5_FPGA_CMD_15 0x8e78
29236 #define A_ULP_TX_INT_ENABLE_2 0x8e7c
29237 
29238 #define S_SMARBT2ULP_DATA_PERR_SET    12
29239 #define V_SMARBT2ULP_DATA_PERR_SET(x) ((x) << S_SMARBT2ULP_DATA_PERR_SET)
29240 #define F_SMARBT2ULP_DATA_PERR_SET    V_SMARBT2ULP_DATA_PERR_SET(1U)
29241 
29242 #define S_ULP2TP_DATA_PERR_SET    11
29243 #define V_ULP2TP_DATA_PERR_SET(x) ((x) << S_ULP2TP_DATA_PERR_SET)
29244 #define F_ULP2TP_DATA_PERR_SET    V_ULP2TP_DATA_PERR_SET(1U)
29245 
29246 #define S_MA2ULP_DATA_PERR_SET    10
29247 #define V_MA2ULP_DATA_PERR_SET(x) ((x) << S_MA2ULP_DATA_PERR_SET)
29248 #define F_MA2ULP_DATA_PERR_SET    V_MA2ULP_DATA_PERR_SET(1U)
29249 
29250 #define S_SGE2ULP_DATA_PERR_SET    9
29251 #define V_SGE2ULP_DATA_PERR_SET(x) ((x) << S_SGE2ULP_DATA_PERR_SET)
29252 #define F_SGE2ULP_DATA_PERR_SET    V_SGE2ULP_DATA_PERR_SET(1U)
29253 
29254 #define S_CIM2ULP_DATA_PERR_SET    8
29255 #define V_CIM2ULP_DATA_PERR_SET(x) ((x) << S_CIM2ULP_DATA_PERR_SET)
29256 #define F_CIM2ULP_DATA_PERR_SET    V_CIM2ULP_DATA_PERR_SET(1U)
29257 
29258 #define S_FSO_HDR_SRAM_PERR_SET3    7
29259 #define V_FSO_HDR_SRAM_PERR_SET3(x) ((x) << S_FSO_HDR_SRAM_PERR_SET3)
29260 #define F_FSO_HDR_SRAM_PERR_SET3    V_FSO_HDR_SRAM_PERR_SET3(1U)
29261 
29262 #define S_FSO_HDR_SRAM_PERR_SET2    6
29263 #define V_FSO_HDR_SRAM_PERR_SET2(x) ((x) << S_FSO_HDR_SRAM_PERR_SET2)
29264 #define F_FSO_HDR_SRAM_PERR_SET2    V_FSO_HDR_SRAM_PERR_SET2(1U)
29265 
29266 #define S_FSO_HDR_SRAM_PERR_SET1    5
29267 #define V_FSO_HDR_SRAM_PERR_SET1(x) ((x) << S_FSO_HDR_SRAM_PERR_SET1)
29268 #define F_FSO_HDR_SRAM_PERR_SET1    V_FSO_HDR_SRAM_PERR_SET1(1U)
29269 
29270 #define S_FSO_HDR_SRAM_PERR_SET0    4
29271 #define V_FSO_HDR_SRAM_PERR_SET0(x) ((x) << S_FSO_HDR_SRAM_PERR_SET0)
29272 #define F_FSO_HDR_SRAM_PERR_SET0    V_FSO_HDR_SRAM_PERR_SET0(1U)
29273 
29274 #define S_T10_PI_SRAM_PERR_SET3    3
29275 #define V_T10_PI_SRAM_PERR_SET3(x) ((x) << S_T10_PI_SRAM_PERR_SET3)
29276 #define F_T10_PI_SRAM_PERR_SET3    V_T10_PI_SRAM_PERR_SET3(1U)
29277 
29278 #define S_T10_PI_SRAM_PERR_SET2    2
29279 #define V_T10_PI_SRAM_PERR_SET2(x) ((x) << S_T10_PI_SRAM_PERR_SET2)
29280 #define F_T10_PI_SRAM_PERR_SET2    V_T10_PI_SRAM_PERR_SET2(1U)
29281 
29282 #define S_T10_PI_SRAM_PERR_SET1    1
29283 #define V_T10_PI_SRAM_PERR_SET1(x) ((x) << S_T10_PI_SRAM_PERR_SET1)
29284 #define F_T10_PI_SRAM_PERR_SET1    V_T10_PI_SRAM_PERR_SET1(1U)
29285 
29286 #define S_T10_PI_SRAM_PERR_SET0    0
29287 #define V_T10_PI_SRAM_PERR_SET0(x) ((x) << S_T10_PI_SRAM_PERR_SET0)
29288 #define F_T10_PI_SRAM_PERR_SET0    V_T10_PI_SRAM_PERR_SET0(1U)
29289 
29290 #define S_EDMA_IN_FIFO_PERR_SET3    31
29291 #define V_EDMA_IN_FIFO_PERR_SET3(x) ((x) << S_EDMA_IN_FIFO_PERR_SET3)
29292 #define F_EDMA_IN_FIFO_PERR_SET3    V_EDMA_IN_FIFO_PERR_SET3(1U)
29293 
29294 #define S_EDMA_IN_FIFO_PERR_SET2    30
29295 #define V_EDMA_IN_FIFO_PERR_SET2(x) ((x) << S_EDMA_IN_FIFO_PERR_SET2)
29296 #define F_EDMA_IN_FIFO_PERR_SET2    V_EDMA_IN_FIFO_PERR_SET2(1U)
29297 
29298 #define S_EDMA_IN_FIFO_PERR_SET1    29
29299 #define V_EDMA_IN_FIFO_PERR_SET1(x) ((x) << S_EDMA_IN_FIFO_PERR_SET1)
29300 #define F_EDMA_IN_FIFO_PERR_SET1    V_EDMA_IN_FIFO_PERR_SET1(1U)
29301 
29302 #define S_EDMA_IN_FIFO_PERR_SET0    28
29303 #define V_EDMA_IN_FIFO_PERR_SET0(x) ((x) << S_EDMA_IN_FIFO_PERR_SET0)
29304 #define F_EDMA_IN_FIFO_PERR_SET0    V_EDMA_IN_FIFO_PERR_SET0(1U)
29305 
29306 #define S_ALIGN_CTL_FIFO_PERR_SET3    27
29307 #define V_ALIGN_CTL_FIFO_PERR_SET3(x) ((x) << S_ALIGN_CTL_FIFO_PERR_SET3)
29308 #define F_ALIGN_CTL_FIFO_PERR_SET3    V_ALIGN_CTL_FIFO_PERR_SET3(1U)
29309 
29310 #define S_ALIGN_CTL_FIFO_PERR_SET2    26
29311 #define V_ALIGN_CTL_FIFO_PERR_SET2(x) ((x) << S_ALIGN_CTL_FIFO_PERR_SET2)
29312 #define F_ALIGN_CTL_FIFO_PERR_SET2    V_ALIGN_CTL_FIFO_PERR_SET2(1U)
29313 
29314 #define S_ALIGN_CTL_FIFO_PERR_SET1    25
29315 #define V_ALIGN_CTL_FIFO_PERR_SET1(x) ((x) << S_ALIGN_CTL_FIFO_PERR_SET1)
29316 #define F_ALIGN_CTL_FIFO_PERR_SET1    V_ALIGN_CTL_FIFO_PERR_SET1(1U)
29317 
29318 #define S_ALIGN_CTL_FIFO_PERR_SET0    24
29319 #define V_ALIGN_CTL_FIFO_PERR_SET0(x) ((x) << S_ALIGN_CTL_FIFO_PERR_SET0)
29320 #define F_ALIGN_CTL_FIFO_PERR_SET0    V_ALIGN_CTL_FIFO_PERR_SET0(1U)
29321 
29322 #define S_SGE_FIFO_PERR_SET3    23
29323 #define V_SGE_FIFO_PERR_SET3(x) ((x) << S_SGE_FIFO_PERR_SET3)
29324 #define F_SGE_FIFO_PERR_SET3    V_SGE_FIFO_PERR_SET3(1U)
29325 
29326 #define S_SGE_FIFO_PERR_SET2    22
29327 #define V_SGE_FIFO_PERR_SET2(x) ((x) << S_SGE_FIFO_PERR_SET2)
29328 #define F_SGE_FIFO_PERR_SET2    V_SGE_FIFO_PERR_SET2(1U)
29329 
29330 #define S_SGE_FIFO_PERR_SET1    21
29331 #define V_SGE_FIFO_PERR_SET1(x) ((x) << S_SGE_FIFO_PERR_SET1)
29332 #define F_SGE_FIFO_PERR_SET1    V_SGE_FIFO_PERR_SET1(1U)
29333 
29334 #define S_SGE_FIFO_PERR_SET0    20
29335 #define V_SGE_FIFO_PERR_SET0(x) ((x) << S_SGE_FIFO_PERR_SET0)
29336 #define F_SGE_FIFO_PERR_SET0    V_SGE_FIFO_PERR_SET0(1U)
29337 
29338 #define S_STAG_FIFO_PERR_SET3    19
29339 #define V_STAG_FIFO_PERR_SET3(x) ((x) << S_STAG_FIFO_PERR_SET3)
29340 #define F_STAG_FIFO_PERR_SET3    V_STAG_FIFO_PERR_SET3(1U)
29341 
29342 #define S_STAG_FIFO_PERR_SET2    18
29343 #define V_STAG_FIFO_PERR_SET2(x) ((x) << S_STAG_FIFO_PERR_SET2)
29344 #define F_STAG_FIFO_PERR_SET2    V_STAG_FIFO_PERR_SET2(1U)
29345 
29346 #define S_STAG_FIFO_PERR_SET1    17
29347 #define V_STAG_FIFO_PERR_SET1(x) ((x) << S_STAG_FIFO_PERR_SET1)
29348 #define F_STAG_FIFO_PERR_SET1    V_STAG_FIFO_PERR_SET1(1U)
29349 
29350 #define S_STAG_FIFO_PERR_SET0    16
29351 #define V_STAG_FIFO_PERR_SET0(x) ((x) << S_STAG_FIFO_PERR_SET0)
29352 #define F_STAG_FIFO_PERR_SET0    V_STAG_FIFO_PERR_SET0(1U)
29353 
29354 #define S_MAP_FIFO_PERR_SET3    15
29355 #define V_MAP_FIFO_PERR_SET3(x) ((x) << S_MAP_FIFO_PERR_SET3)
29356 #define F_MAP_FIFO_PERR_SET3    V_MAP_FIFO_PERR_SET3(1U)
29357 
29358 #define S_MAP_FIFO_PERR_SET2    14
29359 #define V_MAP_FIFO_PERR_SET2(x) ((x) << S_MAP_FIFO_PERR_SET2)
29360 #define F_MAP_FIFO_PERR_SET2    V_MAP_FIFO_PERR_SET2(1U)
29361 
29362 #define S_MAP_FIFO_PERR_SET1    13
29363 #define V_MAP_FIFO_PERR_SET1(x) ((x) << S_MAP_FIFO_PERR_SET1)
29364 #define F_MAP_FIFO_PERR_SET1    V_MAP_FIFO_PERR_SET1(1U)
29365 
29366 #define S_MAP_FIFO_PERR_SET0    12
29367 #define V_MAP_FIFO_PERR_SET0(x) ((x) << S_MAP_FIFO_PERR_SET0)
29368 #define F_MAP_FIFO_PERR_SET0    V_MAP_FIFO_PERR_SET0(1U)
29369 
29370 #define S_DMA_FIFO_PERR_SET3    11
29371 #define V_DMA_FIFO_PERR_SET3(x) ((x) << S_DMA_FIFO_PERR_SET3)
29372 #define F_DMA_FIFO_PERR_SET3    V_DMA_FIFO_PERR_SET3(1U)
29373 
29374 #define S_DMA_FIFO_PERR_SET2    10
29375 #define V_DMA_FIFO_PERR_SET2(x) ((x) << S_DMA_FIFO_PERR_SET2)
29376 #define F_DMA_FIFO_PERR_SET2    V_DMA_FIFO_PERR_SET2(1U)
29377 
29378 #define S_DMA_FIFO_PERR_SET1    9
29379 #define V_DMA_FIFO_PERR_SET1(x) ((x) << S_DMA_FIFO_PERR_SET1)
29380 #define F_DMA_FIFO_PERR_SET1    V_DMA_FIFO_PERR_SET1(1U)
29381 
29382 #define S_DMA_FIFO_PERR_SET0    8
29383 #define V_DMA_FIFO_PERR_SET0(x) ((x) << S_DMA_FIFO_PERR_SET0)
29384 #define F_DMA_FIFO_PERR_SET0    V_DMA_FIFO_PERR_SET0(1U)
29385 
29386 #define A_ULP_TX_INT_CAUSE_2 0x8e80
29387 #define A_ULP_TX_PERR_ENABLE_2 0x8e84
29388 #define A_ULP_TX_SE_CNT_ERR 0x8ea0
29389 
29390 #define S_ERR_CH3    12
29391 #define M_ERR_CH3    0xfU
29392 #define V_ERR_CH3(x) ((x) << S_ERR_CH3)
29393 #define G_ERR_CH3(x) (((x) >> S_ERR_CH3) & M_ERR_CH3)
29394 
29395 #define S_ERR_CH2    8
29396 #define M_ERR_CH2    0xfU
29397 #define V_ERR_CH2(x) ((x) << S_ERR_CH2)
29398 #define G_ERR_CH2(x) (((x) >> S_ERR_CH2) & M_ERR_CH2)
29399 
29400 #define S_ERR_CH1    4
29401 #define M_ERR_CH1    0xfU
29402 #define V_ERR_CH1(x) ((x) << S_ERR_CH1)
29403 #define G_ERR_CH1(x) (((x) >> S_ERR_CH1) & M_ERR_CH1)
29404 
29405 #define S_ERR_CH0    0
29406 #define M_ERR_CH0    0xfU
29407 #define V_ERR_CH0(x) ((x) << S_ERR_CH0)
29408 #define G_ERR_CH0(x) (((x) >> S_ERR_CH0) & M_ERR_CH0)
29409 
29410 #define A_ULP_TX_T5_SE_CNT_ERR 0x8ea0
29411 #define A_ULP_TX_SE_CNT_CLR 0x8ea4
29412 
29413 #define S_CLR_DROP    16
29414 #define M_CLR_DROP    0xfU
29415 #define V_CLR_DROP(x) ((x) << S_CLR_DROP)
29416 #define G_CLR_DROP(x) (((x) >> S_CLR_DROP) & M_CLR_DROP)
29417 
29418 #define S_CLR_CH3    12
29419 #define M_CLR_CH3    0xfU
29420 #define V_CLR_CH3(x) ((x) << S_CLR_CH3)
29421 #define G_CLR_CH3(x) (((x) >> S_CLR_CH3) & M_CLR_CH3)
29422 
29423 #define S_CLR_CH2    8
29424 #define M_CLR_CH2    0xfU
29425 #define V_CLR_CH2(x) ((x) << S_CLR_CH2)
29426 #define G_CLR_CH2(x) (((x) >> S_CLR_CH2) & M_CLR_CH2)
29427 
29428 #define S_CLR_CH1    4
29429 #define M_CLR_CH1    0xfU
29430 #define V_CLR_CH1(x) ((x) << S_CLR_CH1)
29431 #define G_CLR_CH1(x) (((x) >> S_CLR_CH1) & M_CLR_CH1)
29432 
29433 #define S_CLR_CH0    0
29434 #define M_CLR_CH0    0xfU
29435 #define V_CLR_CH0(x) ((x) << S_CLR_CH0)
29436 #define G_CLR_CH0(x) (((x) >> S_CLR_CH0) & M_CLR_CH0)
29437 
29438 #define A_ULP_TX_T5_SE_CNT_CLR 0x8ea4
29439 #define A_ULP_TX_SE_CNT_CH0 0x8ea8
29440 
29441 #define S_SOP_CNT_ULP2TP    28
29442 #define M_SOP_CNT_ULP2TP    0xfU
29443 #define V_SOP_CNT_ULP2TP(x) ((x) << S_SOP_CNT_ULP2TP)
29444 #define G_SOP_CNT_ULP2TP(x) (((x) >> S_SOP_CNT_ULP2TP) & M_SOP_CNT_ULP2TP)
29445 
29446 #define S_EOP_CNT_ULP2TP    24
29447 #define M_EOP_CNT_ULP2TP    0xfU
29448 #define V_EOP_CNT_ULP2TP(x) ((x) << S_EOP_CNT_ULP2TP)
29449 #define G_EOP_CNT_ULP2TP(x) (((x) >> S_EOP_CNT_ULP2TP) & M_EOP_CNT_ULP2TP)
29450 
29451 #define S_SOP_CNT_LSO_IN    20
29452 #define M_SOP_CNT_LSO_IN    0xfU
29453 #define V_SOP_CNT_LSO_IN(x) ((x) << S_SOP_CNT_LSO_IN)
29454 #define G_SOP_CNT_LSO_IN(x) (((x) >> S_SOP_CNT_LSO_IN) & M_SOP_CNT_LSO_IN)
29455 
29456 #define S_EOP_CNT_LSO_IN    16
29457 #define M_EOP_CNT_LSO_IN    0xfU
29458 #define V_EOP_CNT_LSO_IN(x) ((x) << S_EOP_CNT_LSO_IN)
29459 #define G_EOP_CNT_LSO_IN(x) (((x) >> S_EOP_CNT_LSO_IN) & M_EOP_CNT_LSO_IN)
29460 
29461 #define S_SOP_CNT_ALG_IN    12
29462 #define M_SOP_CNT_ALG_IN    0xfU
29463 #define V_SOP_CNT_ALG_IN(x) ((x) << S_SOP_CNT_ALG_IN)
29464 #define G_SOP_CNT_ALG_IN(x) (((x) >> S_SOP_CNT_ALG_IN) & M_SOP_CNT_ALG_IN)
29465 
29466 #define S_EOP_CNT_ALG_IN    8
29467 #define M_EOP_CNT_ALG_IN    0xfU
29468 #define V_EOP_CNT_ALG_IN(x) ((x) << S_EOP_CNT_ALG_IN)
29469 #define G_EOP_CNT_ALG_IN(x) (((x) >> S_EOP_CNT_ALG_IN) & M_EOP_CNT_ALG_IN)
29470 
29471 #define S_SOP_CNT_CIM2ULP    4
29472 #define M_SOP_CNT_CIM2ULP    0xfU
29473 #define V_SOP_CNT_CIM2ULP(x) ((x) << S_SOP_CNT_CIM2ULP)
29474 #define G_SOP_CNT_CIM2ULP(x) (((x) >> S_SOP_CNT_CIM2ULP) & M_SOP_CNT_CIM2ULP)
29475 
29476 #define S_EOP_CNT_CIM2ULP    0
29477 #define M_EOP_CNT_CIM2ULP    0xfU
29478 #define V_EOP_CNT_CIM2ULP(x) ((x) << S_EOP_CNT_CIM2ULP)
29479 #define G_EOP_CNT_CIM2ULP(x) (((x) >> S_EOP_CNT_CIM2ULP) & M_EOP_CNT_CIM2ULP)
29480 
29481 #define A_ULP_TX_T5_SE_CNT_CH0 0x8ea8
29482 #define A_ULP_TX_SE_CNT_CH1 0x8eac
29483 #define A_ULP_TX_T5_SE_CNT_CH1 0x8eac
29484 #define A_ULP_TX_SE_CNT_CH2 0x8eb0
29485 #define A_ULP_TX_T5_SE_CNT_CH2 0x8eb0
29486 #define A_ULP_TX_SE_CNT_CH3 0x8eb4
29487 #define A_ULP_TX_T5_SE_CNT_CH3 0x8eb4
29488 #define A_ULP_TX_DROP_CNT 0x8eb8
29489 
29490 #define S_DROP_CH3    12
29491 #define M_DROP_CH3    0xfU
29492 #define V_DROP_CH3(x) ((x) << S_DROP_CH3)
29493 #define G_DROP_CH3(x) (((x) >> S_DROP_CH3) & M_DROP_CH3)
29494 
29495 #define S_DROP_CH2    8
29496 #define M_DROP_CH2    0xfU
29497 #define V_DROP_CH2(x) ((x) << S_DROP_CH2)
29498 #define G_DROP_CH2(x) (((x) >> S_DROP_CH2) & M_DROP_CH2)
29499 
29500 #define S_DROP_CH1    4
29501 #define M_DROP_CH1    0xfU
29502 #define V_DROP_CH1(x) ((x) << S_DROP_CH1)
29503 #define G_DROP_CH1(x) (((x) >> S_DROP_CH1) & M_DROP_CH1)
29504 
29505 #define S_DROP_CH0    0
29506 #define M_DROP_CH0    0xfU
29507 #define V_DROP_CH0(x) ((x) << S_DROP_CH0)
29508 #define G_DROP_CH0(x) (((x) >> S_DROP_CH0) & M_DROP_CH0)
29509 
29510 #define A_ULP_TX_T5_DROP_CNT 0x8eb8
29511 
29512 #define S_DROP_INVLD_MC_CH3    28
29513 #define M_DROP_INVLD_MC_CH3    0xfU
29514 #define V_DROP_INVLD_MC_CH3(x) ((x) << S_DROP_INVLD_MC_CH3)
29515 #define G_DROP_INVLD_MC_CH3(x) (((x) >> S_DROP_INVLD_MC_CH3) & M_DROP_INVLD_MC_CH3)
29516 
29517 #define S_DROP_INVLD_MC_CH2    24
29518 #define M_DROP_INVLD_MC_CH2    0xfU
29519 #define V_DROP_INVLD_MC_CH2(x) ((x) << S_DROP_INVLD_MC_CH2)
29520 #define G_DROP_INVLD_MC_CH2(x) (((x) >> S_DROP_INVLD_MC_CH2) & M_DROP_INVLD_MC_CH2)
29521 
29522 #define S_DROP_INVLD_MC_CH1    20
29523 #define M_DROP_INVLD_MC_CH1    0xfU
29524 #define V_DROP_INVLD_MC_CH1(x) ((x) << S_DROP_INVLD_MC_CH1)
29525 #define G_DROP_INVLD_MC_CH1(x) (((x) >> S_DROP_INVLD_MC_CH1) & M_DROP_INVLD_MC_CH1)
29526 
29527 #define S_DROP_INVLD_MC_CH0    16
29528 #define M_DROP_INVLD_MC_CH0    0xfU
29529 #define V_DROP_INVLD_MC_CH0(x) ((x) << S_DROP_INVLD_MC_CH0)
29530 #define G_DROP_INVLD_MC_CH0(x) (((x) >> S_DROP_INVLD_MC_CH0) & M_DROP_INVLD_MC_CH0)
29531 
29532 #define A_ULP_TX_CSU_REVISION 0x8ebc
29533 #define A_ULP_TX_LA_RDPTR_0 0x8ec0
29534 #define A_ULP_TX_LA_RDDATA_0 0x8ec4
29535 #define A_ULP_TX_LA_WRPTR_0 0x8ec8
29536 #define A_ULP_TX_LA_RESERVED_0 0x8ecc
29537 #define A_ULP_TX_LA_RDPTR_1 0x8ed0
29538 #define A_ULP_TX_LA_RDDATA_1 0x8ed4
29539 #define A_ULP_TX_LA_WRPTR_1 0x8ed8
29540 #define A_ULP_TX_LA_RESERVED_1 0x8edc
29541 #define A_ULP_TX_LA_RDPTR_2 0x8ee0
29542 #define A_ULP_TX_LA_RDDATA_2 0x8ee4
29543 #define A_ULP_TX_LA_WRPTR_2 0x8ee8
29544 #define A_ULP_TX_LA_RESERVED_2 0x8eec
29545 #define A_ULP_TX_LA_RDPTR_3 0x8ef0
29546 #define A_ULP_TX_LA_RDDATA_3 0x8ef4
29547 #define A_ULP_TX_LA_WRPTR_3 0x8ef8
29548 #define A_ULP_TX_LA_RESERVED_3 0x8efc
29549 #define A_ULP_TX_LA_RDPTR_4 0x8f00
29550 #define A_ULP_TX_LA_RDDATA_4 0x8f04
29551 #define A_ULP_TX_LA_WRPTR_4 0x8f08
29552 #define A_ULP_TX_LA_RESERVED_4 0x8f0c
29553 #define A_ULP_TX_LA_RDPTR_5 0x8f10
29554 #define A_ULP_TX_LA_RDDATA_5 0x8f14
29555 #define A_ULP_TX_LA_WRPTR_5 0x8f18
29556 #define A_ULP_TX_LA_RESERVED_5 0x8f1c
29557 #define A_ULP_TX_LA_RDPTR_6 0x8f20
29558 #define A_ULP_TX_LA_RDDATA_6 0x8f24
29559 #define A_ULP_TX_LA_WRPTR_6 0x8f28
29560 #define A_ULP_TX_LA_RESERVED_6 0x8f2c
29561 #define A_ULP_TX_LA_RDPTR_7 0x8f30
29562 #define A_ULP_TX_LA_RDDATA_7 0x8f34
29563 #define A_ULP_TX_LA_WRPTR_7 0x8f38
29564 #define A_ULP_TX_LA_RESERVED_7 0x8f3c
29565 #define A_ULP_TX_LA_RDPTR_8 0x8f40
29566 #define A_ULP_TX_LA_RDDATA_8 0x8f44
29567 #define A_ULP_TX_LA_WRPTR_8 0x8f48
29568 #define A_ULP_TX_LA_RESERVED_8 0x8f4c
29569 #define A_ULP_TX_LA_RDPTR_9 0x8f50
29570 #define A_ULP_TX_LA_RDDATA_9 0x8f54
29571 #define A_ULP_TX_LA_WRPTR_9 0x8f58
29572 #define A_ULP_TX_LA_RESERVED_9 0x8f5c
29573 #define A_ULP_TX_LA_RDPTR_10 0x8f60
29574 #define A_ULP_TX_LA_RDDATA_10 0x8f64
29575 #define A_ULP_TX_LA_WRPTR_10 0x8f68
29576 #define A_ULP_TX_LA_RESERVED_10 0x8f6c
29577 #define A_ULP_TX_ASIC_DEBUG_CTRL 0x8f70
29578 
29579 #define S_LA_WR0    0
29580 #define V_LA_WR0(x) ((x) << S_LA_WR0)
29581 #define F_LA_WR0    V_LA_WR0(1U)
29582 
29583 #define A_ULP_TX_ASIC_DEBUG_0 0x8f74
29584 #define A_ULP_TX_ASIC_DEBUG_1 0x8f78
29585 #define A_ULP_TX_ASIC_DEBUG_2 0x8f7c
29586 #define A_ULP_TX_ASIC_DEBUG_3 0x8f80
29587 #define A_ULP_TX_ASIC_DEBUG_4 0x8f84
29588 #define A_ULP_TX_CPL_TX_DATA_FLAGS_MASK 0x8f88
29589 
29590 #define S_BYPASS_FIRST    26
29591 #define V_BYPASS_FIRST(x) ((x) << S_BYPASS_FIRST)
29592 #define F_BYPASS_FIRST    V_BYPASS_FIRST(1U)
29593 
29594 #define S_BYPASS_MIDDLE    25
29595 #define V_BYPASS_MIDDLE(x) ((x) << S_BYPASS_MIDDLE)
29596 #define F_BYPASS_MIDDLE    V_BYPASS_MIDDLE(1U)
29597 
29598 #define S_BYPASS_LAST    24
29599 #define V_BYPASS_LAST(x) ((x) << S_BYPASS_LAST)
29600 #define F_BYPASS_LAST    V_BYPASS_LAST(1U)
29601 
29602 #define S_PUSH_FIRST    22
29603 #define V_PUSH_FIRST(x) ((x) << S_PUSH_FIRST)
29604 #define F_PUSH_FIRST    V_PUSH_FIRST(1U)
29605 
29606 #define S_PUSH_MIDDLE    21
29607 #define V_PUSH_MIDDLE(x) ((x) << S_PUSH_MIDDLE)
29608 #define F_PUSH_MIDDLE    V_PUSH_MIDDLE(1U)
29609 
29610 #define S_PUSH_LAST    20
29611 #define V_PUSH_LAST(x) ((x) << S_PUSH_LAST)
29612 #define F_PUSH_LAST    V_PUSH_LAST(1U)
29613 
29614 #define S_SAVE_FIRST    18
29615 #define V_SAVE_FIRST(x) ((x) << S_SAVE_FIRST)
29616 #define F_SAVE_FIRST    V_SAVE_FIRST(1U)
29617 
29618 #define S_SAVE_MIDDLE    17
29619 #define V_SAVE_MIDDLE(x) ((x) << S_SAVE_MIDDLE)
29620 #define F_SAVE_MIDDLE    V_SAVE_MIDDLE(1U)
29621 
29622 #define S_SAVE_LAST    16
29623 #define V_SAVE_LAST(x) ((x) << S_SAVE_LAST)
29624 #define F_SAVE_LAST    V_SAVE_LAST(1U)
29625 
29626 #define S_FLUSH_FIRST    14
29627 #define V_FLUSH_FIRST(x) ((x) << S_FLUSH_FIRST)
29628 #define F_FLUSH_FIRST    V_FLUSH_FIRST(1U)
29629 
29630 #define S_FLUSH_MIDDLE    13
29631 #define V_FLUSH_MIDDLE(x) ((x) << S_FLUSH_MIDDLE)
29632 #define F_FLUSH_MIDDLE    V_FLUSH_MIDDLE(1U)
29633 
29634 #define S_FLUSH_LAST    12
29635 #define V_FLUSH_LAST(x) ((x) << S_FLUSH_LAST)
29636 #define F_FLUSH_LAST    V_FLUSH_LAST(1U)
29637 
29638 #define S_URGENT_FIRST    10
29639 #define V_URGENT_FIRST(x) ((x) << S_URGENT_FIRST)
29640 #define F_URGENT_FIRST    V_URGENT_FIRST(1U)
29641 
29642 #define S_URGENT_MIDDLE    9
29643 #define V_URGENT_MIDDLE(x) ((x) << S_URGENT_MIDDLE)
29644 #define F_URGENT_MIDDLE    V_URGENT_MIDDLE(1U)
29645 
29646 #define S_URGENT_LAST    8
29647 #define V_URGENT_LAST(x) ((x) << S_URGENT_LAST)
29648 #define F_URGENT_LAST    V_URGENT_LAST(1U)
29649 
29650 #define S_MORE_FIRST    6
29651 #define V_MORE_FIRST(x) ((x) << S_MORE_FIRST)
29652 #define F_MORE_FIRST    V_MORE_FIRST(1U)
29653 
29654 #define S_MORE_MIDDLE    5
29655 #define V_MORE_MIDDLE(x) ((x) << S_MORE_MIDDLE)
29656 #define F_MORE_MIDDLE    V_MORE_MIDDLE(1U)
29657 
29658 #define S_MORE_LAST    4
29659 #define V_MORE_LAST(x) ((x) << S_MORE_LAST)
29660 #define F_MORE_LAST    V_MORE_LAST(1U)
29661 
29662 #define S_SHOVE_FIRST    2
29663 #define V_SHOVE_FIRST(x) ((x) << S_SHOVE_FIRST)
29664 #define F_SHOVE_FIRST    V_SHOVE_FIRST(1U)
29665 
29666 #define S_SHOVE_MIDDLE    1
29667 #define V_SHOVE_MIDDLE(x) ((x) << S_SHOVE_MIDDLE)
29668 #define F_SHOVE_MIDDLE    V_SHOVE_MIDDLE(1U)
29669 
29670 #define S_SHOVE_LAST    0
29671 #define V_SHOVE_LAST(x) ((x) << S_SHOVE_LAST)
29672 #define F_SHOVE_LAST    V_SHOVE_LAST(1U)
29673 
29674 #define A_ULP_TX_TLS_IND_CMD 0x8fb8
29675 
29676 #define S_TLS_TX_REG_OFF_ADDR    0
29677 #define M_TLS_TX_REG_OFF_ADDR    0x3ffU
29678 #define V_TLS_TX_REG_OFF_ADDR(x) ((x) << S_TLS_TX_REG_OFF_ADDR)
29679 #define G_TLS_TX_REG_OFF_ADDR(x) (((x) >> S_TLS_TX_REG_OFF_ADDR) & M_TLS_TX_REG_OFF_ADDR)
29680 
29681 #define A_ULP_TX_TLS_IND_DATA 0x8fbc
29682 
29683 /* registers for module PM_RX */
29684 #define PM_RX_BASE_ADDR 0x8fc0
29685 
29686 #define A_PM_RX_CFG 0x8fc0
29687 #define A_PM_RX_MODE 0x8fc4
29688 
29689 #define S_RX_USE_BUNDLE_LEN    4
29690 #define V_RX_USE_BUNDLE_LEN(x) ((x) << S_RX_USE_BUNDLE_LEN)
29691 #define F_RX_USE_BUNDLE_LEN    V_RX_USE_BUNDLE_LEN(1U)
29692 
29693 #define S_STAT_TO_CH    3
29694 #define V_STAT_TO_CH(x) ((x) << S_STAT_TO_CH)
29695 #define F_STAT_TO_CH    V_STAT_TO_CH(1U)
29696 
29697 #define S_STAT_FROM_CH    1
29698 #define M_STAT_FROM_CH    0x3U
29699 #define V_STAT_FROM_CH(x) ((x) << S_STAT_FROM_CH)
29700 #define G_STAT_FROM_CH(x) (((x) >> S_STAT_FROM_CH) & M_STAT_FROM_CH)
29701 
29702 #define S_PREFETCH_ENABLE    0
29703 #define V_PREFETCH_ENABLE(x) ((x) << S_PREFETCH_ENABLE)
29704 #define F_PREFETCH_ENABLE    V_PREFETCH_ENABLE(1U)
29705 
29706 #define A_PM_RX_STAT_CONFIG 0x8fc8
29707 #define A_PM_RX_STAT_COUNT 0x8fcc
29708 #define A_PM_RX_STAT_LSB 0x8fd0
29709 #define A_PM_RX_DBG_CTRL 0x8fd0
29710 
29711 #define S_OSPIWRBUSY_T5    21
29712 #define M_OSPIWRBUSY_T5    0x3U
29713 #define V_OSPIWRBUSY_T5(x) ((x) << S_OSPIWRBUSY_T5)
29714 #define G_OSPIWRBUSY_T5(x) (((x) >> S_OSPIWRBUSY_T5) & M_OSPIWRBUSY_T5)
29715 
29716 #define S_ISPIWRBUSY    17
29717 #define M_ISPIWRBUSY    0xfU
29718 #define V_ISPIWRBUSY(x) ((x) << S_ISPIWRBUSY)
29719 #define G_ISPIWRBUSY(x) (((x) >> S_ISPIWRBUSY) & M_ISPIWRBUSY)
29720 
29721 #define S_PMDBGADDR    0
29722 #define M_PMDBGADDR    0x1ffffU
29723 #define V_PMDBGADDR(x) ((x) << S_PMDBGADDR)
29724 #define G_PMDBGADDR(x) (((x) >> S_PMDBGADDR) & M_PMDBGADDR)
29725 
29726 #define A_PM_RX_STAT_MSB 0x8fd4
29727 #define A_PM_RX_DBG_DATA 0x8fd4
29728 #define A_PM_RX_INT_ENABLE 0x8fd8
29729 
29730 #define S_ZERO_E_CMD_ERROR    22
29731 #define V_ZERO_E_CMD_ERROR(x) ((x) << S_ZERO_E_CMD_ERROR)
29732 #define F_ZERO_E_CMD_ERROR    V_ZERO_E_CMD_ERROR(1U)
29733 
29734 #define S_IESPI0_FIFO2X_RX_FRAMING_ERROR    21
29735 #define V_IESPI0_FIFO2X_RX_FRAMING_ERROR(x) ((x) << S_IESPI0_FIFO2X_RX_FRAMING_ERROR)
29736 #define F_IESPI0_FIFO2X_RX_FRAMING_ERROR    V_IESPI0_FIFO2X_RX_FRAMING_ERROR(1U)
29737 
29738 #define S_IESPI1_FIFO2X_RX_FRAMING_ERROR    20
29739 #define V_IESPI1_FIFO2X_RX_FRAMING_ERROR(x) ((x) << S_IESPI1_FIFO2X_RX_FRAMING_ERROR)
29740 #define F_IESPI1_FIFO2X_RX_FRAMING_ERROR    V_IESPI1_FIFO2X_RX_FRAMING_ERROR(1U)
29741 
29742 #define S_IESPI2_FIFO2X_RX_FRAMING_ERROR    19
29743 #define V_IESPI2_FIFO2X_RX_FRAMING_ERROR(x) ((x) << S_IESPI2_FIFO2X_RX_FRAMING_ERROR)
29744 #define F_IESPI2_FIFO2X_RX_FRAMING_ERROR    V_IESPI2_FIFO2X_RX_FRAMING_ERROR(1U)
29745 
29746 #define S_IESPI3_FIFO2X_RX_FRAMING_ERROR    18
29747 #define V_IESPI3_FIFO2X_RX_FRAMING_ERROR(x) ((x) << S_IESPI3_FIFO2X_RX_FRAMING_ERROR)
29748 #define F_IESPI3_FIFO2X_RX_FRAMING_ERROR    V_IESPI3_FIFO2X_RX_FRAMING_ERROR(1U)
29749 
29750 #define S_IESPI0_RX_FRAMING_ERROR    17
29751 #define V_IESPI0_RX_FRAMING_ERROR(x) ((x) << S_IESPI0_RX_FRAMING_ERROR)
29752 #define F_IESPI0_RX_FRAMING_ERROR    V_IESPI0_RX_FRAMING_ERROR(1U)
29753 
29754 #define S_IESPI1_RX_FRAMING_ERROR    16
29755 #define V_IESPI1_RX_FRAMING_ERROR(x) ((x) << S_IESPI1_RX_FRAMING_ERROR)
29756 #define F_IESPI1_RX_FRAMING_ERROR    V_IESPI1_RX_FRAMING_ERROR(1U)
29757 
29758 #define S_IESPI2_RX_FRAMING_ERROR    15
29759 #define V_IESPI2_RX_FRAMING_ERROR(x) ((x) << S_IESPI2_RX_FRAMING_ERROR)
29760 #define F_IESPI2_RX_FRAMING_ERROR    V_IESPI2_RX_FRAMING_ERROR(1U)
29761 
29762 #define S_IESPI3_RX_FRAMING_ERROR    14
29763 #define V_IESPI3_RX_FRAMING_ERROR(x) ((x) << S_IESPI3_RX_FRAMING_ERROR)
29764 #define F_IESPI3_RX_FRAMING_ERROR    V_IESPI3_RX_FRAMING_ERROR(1U)
29765 
29766 #define S_IESPI0_TX_FRAMING_ERROR    13
29767 #define V_IESPI0_TX_FRAMING_ERROR(x) ((x) << S_IESPI0_TX_FRAMING_ERROR)
29768 #define F_IESPI0_TX_FRAMING_ERROR    V_IESPI0_TX_FRAMING_ERROR(1U)
29769 
29770 #define S_IESPI1_TX_FRAMING_ERROR    12
29771 #define V_IESPI1_TX_FRAMING_ERROR(x) ((x) << S_IESPI1_TX_FRAMING_ERROR)
29772 #define F_IESPI1_TX_FRAMING_ERROR    V_IESPI1_TX_FRAMING_ERROR(1U)
29773 
29774 #define S_IESPI2_TX_FRAMING_ERROR    11
29775 #define V_IESPI2_TX_FRAMING_ERROR(x) ((x) << S_IESPI2_TX_FRAMING_ERROR)
29776 #define F_IESPI2_TX_FRAMING_ERROR    V_IESPI2_TX_FRAMING_ERROR(1U)
29777 
29778 #define S_IESPI3_TX_FRAMING_ERROR    10
29779 #define V_IESPI3_TX_FRAMING_ERROR(x) ((x) << S_IESPI3_TX_FRAMING_ERROR)
29780 #define F_IESPI3_TX_FRAMING_ERROR    V_IESPI3_TX_FRAMING_ERROR(1U)
29781 
29782 #define S_OCSPI0_RX_FRAMING_ERROR    9
29783 #define V_OCSPI0_RX_FRAMING_ERROR(x) ((x) << S_OCSPI0_RX_FRAMING_ERROR)
29784 #define F_OCSPI0_RX_FRAMING_ERROR    V_OCSPI0_RX_FRAMING_ERROR(1U)
29785 
29786 #define S_OCSPI1_RX_FRAMING_ERROR    8
29787 #define V_OCSPI1_RX_FRAMING_ERROR(x) ((x) << S_OCSPI1_RX_FRAMING_ERROR)
29788 #define F_OCSPI1_RX_FRAMING_ERROR    V_OCSPI1_RX_FRAMING_ERROR(1U)
29789 
29790 #define S_OCSPI0_TX_FRAMING_ERROR    7
29791 #define V_OCSPI0_TX_FRAMING_ERROR(x) ((x) << S_OCSPI0_TX_FRAMING_ERROR)
29792 #define F_OCSPI0_TX_FRAMING_ERROR    V_OCSPI0_TX_FRAMING_ERROR(1U)
29793 
29794 #define S_OCSPI1_TX_FRAMING_ERROR    6
29795 #define V_OCSPI1_TX_FRAMING_ERROR(x) ((x) << S_OCSPI1_TX_FRAMING_ERROR)
29796 #define F_OCSPI1_TX_FRAMING_ERROR    V_OCSPI1_TX_FRAMING_ERROR(1U)
29797 
29798 #define S_OCSPI0_OFIFO2X_TX_FRAMING_ERROR    5
29799 #define V_OCSPI0_OFIFO2X_TX_FRAMING_ERROR(x) ((x) << S_OCSPI0_OFIFO2X_TX_FRAMING_ERROR)
29800 #define F_OCSPI0_OFIFO2X_TX_FRAMING_ERROR    V_OCSPI0_OFIFO2X_TX_FRAMING_ERROR(1U)
29801 
29802 #define S_OCSPI1_OFIFO2X_TX_FRAMING_ERROR    4
29803 #define V_OCSPI1_OFIFO2X_TX_FRAMING_ERROR(x) ((x) << S_OCSPI1_OFIFO2X_TX_FRAMING_ERROR)
29804 #define F_OCSPI1_OFIFO2X_TX_FRAMING_ERROR    V_OCSPI1_OFIFO2X_TX_FRAMING_ERROR(1U)
29805 
29806 #define S_OCSPI_PAR_ERROR    3
29807 #define V_OCSPI_PAR_ERROR(x) ((x) << S_OCSPI_PAR_ERROR)
29808 #define F_OCSPI_PAR_ERROR    V_OCSPI_PAR_ERROR(1U)
29809 
29810 #define S_DB_OPTIONS_PAR_ERROR    2
29811 #define V_DB_OPTIONS_PAR_ERROR(x) ((x) << S_DB_OPTIONS_PAR_ERROR)
29812 #define F_DB_OPTIONS_PAR_ERROR    V_DB_OPTIONS_PAR_ERROR(1U)
29813 
29814 #define S_IESPI_PAR_ERROR    1
29815 #define V_IESPI_PAR_ERROR(x) ((x) << S_IESPI_PAR_ERROR)
29816 #define F_IESPI_PAR_ERROR    V_IESPI_PAR_ERROR(1U)
29817 
29818 #define S_E_PCMD_PAR_ERROR    0
29819 #define V_E_PCMD_PAR_ERROR(x) ((x) << S_E_PCMD_PAR_ERROR)
29820 #define F_E_PCMD_PAR_ERROR    V_E_PCMD_PAR_ERROR(1U)
29821 
29822 #define S_OSPI_OVERFLOW1    28
29823 #define V_OSPI_OVERFLOW1(x) ((x) << S_OSPI_OVERFLOW1)
29824 #define F_OSPI_OVERFLOW1    V_OSPI_OVERFLOW1(1U)
29825 
29826 #define S_OSPI_OVERFLOW0    27
29827 #define V_OSPI_OVERFLOW0(x) ((x) << S_OSPI_OVERFLOW0)
29828 #define F_OSPI_OVERFLOW0    V_OSPI_OVERFLOW0(1U)
29829 
29830 #define S_MA_INTF_SDC_ERR    26
29831 #define V_MA_INTF_SDC_ERR(x) ((x) << S_MA_INTF_SDC_ERR)
29832 #define F_MA_INTF_SDC_ERR    V_MA_INTF_SDC_ERR(1U)
29833 
29834 #define S_BUNDLE_LEN_PARERR    25
29835 #define V_BUNDLE_LEN_PARERR(x) ((x) << S_BUNDLE_LEN_PARERR)
29836 #define F_BUNDLE_LEN_PARERR    V_BUNDLE_LEN_PARERR(1U)
29837 
29838 #define S_BUNDLE_LEN_OVFL    24
29839 #define V_BUNDLE_LEN_OVFL(x) ((x) << S_BUNDLE_LEN_OVFL)
29840 #define F_BUNDLE_LEN_OVFL    V_BUNDLE_LEN_OVFL(1U)
29841 
29842 #define S_SDC_ERR    23
29843 #define V_SDC_ERR(x) ((x) << S_SDC_ERR)
29844 #define F_SDC_ERR    V_SDC_ERR(1U)
29845 
29846 #define A_PM_RX_INT_CAUSE 0x8fdc
29847 #define A_PM_RX_ISPI_DBG_4B_DATA0 0x10000
29848 #define A_PM_RX_ISPI_DBG_4B_DATA1 0x10001
29849 #define A_PM_RX_ISPI_DBG_4B_DATA2 0x10002
29850 #define A_PM_RX_ISPI_DBG_4B_DATA3 0x10003
29851 #define A_PM_RX_ISPI_DBG_4B_DATA4 0x10004
29852 #define A_PM_RX_ISPI_DBG_4B_DATA5 0x10005
29853 #define A_PM_RX_ISPI_DBG_4B_DATA6 0x10006
29854 #define A_PM_RX_ISPI_DBG_4B_DATA7 0x10007
29855 #define A_PM_RX_ISPI_DBG_4B_DATA8 0x10008
29856 #define A_PM_RX_OSPI_DBG_4B_DATA0 0x10009
29857 #define A_PM_RX_OSPI_DBG_4B_DATA1 0x1000a
29858 #define A_PM_RX_OSPI_DBG_4B_DATA2 0x1000b
29859 #define A_PM_RX_OSPI_DBG_4B_DATA3 0x1000c
29860 #define A_PM_RX_OSPI_DBG_4B_DATA4 0x1000d
29861 #define A_PM_RX_OSPI_DBG_4B_DATA5 0x1000e
29862 #define A_PM_RX_OSPI_DBG_4B_DATA6 0x1000f
29863 #define A_PM_RX_OSPI_DBG_4B_DATA7 0x10010
29864 #define A_PM_RX_OSPI_DBG_4B_DATA8 0x10011
29865 #define A_PM_RX_OSPI_DBG_4B_DATA9 0x10012
29866 #define A_PM_RX_DBG_STAT_MSB 0x10013
29867 #define A_PM_RX_DBG_STAT_LSB 0x10014
29868 #define A_PM_RX_DBG_RSVD_FLIT_CNT 0x10015
29869 
29870 #define S_I_TO_O_PATH_RSVD_FLIT_BACKUP    12
29871 #define M_I_TO_O_PATH_RSVD_FLIT_BACKUP    0xfU
29872 #define V_I_TO_O_PATH_RSVD_FLIT_BACKUP(x) ((x) << S_I_TO_O_PATH_RSVD_FLIT_BACKUP)
29873 #define G_I_TO_O_PATH_RSVD_FLIT_BACKUP(x) (((x) >> S_I_TO_O_PATH_RSVD_FLIT_BACKUP) & M_I_TO_O_PATH_RSVD_FLIT_BACKUP)
29874 
29875 #define S_I_TO_O_PATH_RSVD_FLIT    8
29876 #define M_I_TO_O_PATH_RSVD_FLIT    0xfU
29877 #define V_I_TO_O_PATH_RSVD_FLIT(x) ((x) << S_I_TO_O_PATH_RSVD_FLIT)
29878 #define G_I_TO_O_PATH_RSVD_FLIT(x) (((x) >> S_I_TO_O_PATH_RSVD_FLIT) & M_I_TO_O_PATH_RSVD_FLIT)
29879 
29880 #define S_PRFCH_RSVD_FLIT    4
29881 #define M_PRFCH_RSVD_FLIT    0xfU
29882 #define V_PRFCH_RSVD_FLIT(x) ((x) << S_PRFCH_RSVD_FLIT)
29883 #define G_PRFCH_RSVD_FLIT(x) (((x) >> S_PRFCH_RSVD_FLIT) & M_PRFCH_RSVD_FLIT)
29884 
29885 #define S_OSPI_RSVD_FLIT    0
29886 #define M_OSPI_RSVD_FLIT    0xfU
29887 #define V_OSPI_RSVD_FLIT(x) ((x) << S_OSPI_RSVD_FLIT)
29888 #define G_OSPI_RSVD_FLIT(x) (((x) >> S_OSPI_RSVD_FLIT) & M_OSPI_RSVD_FLIT)
29889 
29890 #define A_PM_RX_SDC_EN 0x10016
29891 
29892 #define S_SDC_EN    0
29893 #define V_SDC_EN(x) ((x) << S_SDC_EN)
29894 #define F_SDC_EN    V_SDC_EN(1U)
29895 
29896 #define A_PM_RX_INOUT_FIFO_DBG_CHNL_SEL 0x10017
29897 
29898 #define S_CHNL_3_SEL    3
29899 #define V_CHNL_3_SEL(x) ((x) << S_CHNL_3_SEL)
29900 #define F_CHNL_3_SEL    V_CHNL_3_SEL(1U)
29901 
29902 #define S_CHNL_2_SEL    2
29903 #define V_CHNL_2_SEL(x) ((x) << S_CHNL_2_SEL)
29904 #define F_CHNL_2_SEL    V_CHNL_2_SEL(1U)
29905 
29906 #define S_CHNL_1_SEL    1
29907 #define V_CHNL_1_SEL(x) ((x) << S_CHNL_1_SEL)
29908 #define F_CHNL_1_SEL    V_CHNL_1_SEL(1U)
29909 
29910 #define S_CHNL_0_SEL    0
29911 #define V_CHNL_0_SEL(x) ((x) << S_CHNL_0_SEL)
29912 #define F_CHNL_0_SEL    V_CHNL_0_SEL(1U)
29913 
29914 #define A_PM_RX_INOUT_FIFO_DBG_WR 0x10018
29915 
29916 #define S_O_FIFO_WRITE    3
29917 #define V_O_FIFO_WRITE(x) ((x) << S_O_FIFO_WRITE)
29918 #define F_O_FIFO_WRITE    V_O_FIFO_WRITE(1U)
29919 
29920 #define S_I_FIFO_WRITE    2
29921 #define V_I_FIFO_WRITE(x) ((x) << S_I_FIFO_WRITE)
29922 #define F_I_FIFO_WRITE    V_I_FIFO_WRITE(1U)
29923 
29924 #define S_O_FIFO_READ    1
29925 #define V_O_FIFO_READ(x) ((x) << S_O_FIFO_READ)
29926 #define F_O_FIFO_READ    V_O_FIFO_READ(1U)
29927 
29928 #define S_I_FIFO_READ    0
29929 #define V_I_FIFO_READ(x) ((x) << S_I_FIFO_READ)
29930 #define F_I_FIFO_READ    V_I_FIFO_READ(1U)
29931 
29932 #define A_PM_RX_INPUT_FIFO_STR_FWD_EN 0x10019
29933 
29934 #define S_ISPI_STR_FWD_EN    0
29935 #define V_ISPI_STR_FWD_EN(x) ((x) << S_ISPI_STR_FWD_EN)
29936 #define F_ISPI_STR_FWD_EN    V_ISPI_STR_FWD_EN(1U)
29937 
29938 #define A_PM_RX_PRFTCH_ACROSS_BNDLE_EN 0x1001a
29939 
29940 #define S_PRFTCH_ACROSS_BNDLE_EN    0
29941 #define V_PRFTCH_ACROSS_BNDLE_EN(x) ((x) << S_PRFTCH_ACROSS_BNDLE_EN)
29942 #define F_PRFTCH_ACROSS_BNDLE_EN    V_PRFTCH_ACROSS_BNDLE_EN(1U)
29943 
29944 #define A_PM_RX_PRFTCH_WRR_ENABLE 0x1001b
29945 
29946 #define S_PRFTCH_WRR_ENABLE    0
29947 #define V_PRFTCH_WRR_ENABLE(x) ((x) << S_PRFTCH_WRR_ENABLE)
29948 #define F_PRFTCH_WRR_ENABLE    V_PRFTCH_WRR_ENABLE(1U)
29949 
29950 #define A_PM_RX_PRFTCH_WRR_MAX_DEFICIT_CNT 0x1001c
29951 
29952 #define S_CHNL1_MAX_DEFICIT_CNT    16
29953 #define M_CHNL1_MAX_DEFICIT_CNT    0xffffU
29954 #define V_CHNL1_MAX_DEFICIT_CNT(x) ((x) << S_CHNL1_MAX_DEFICIT_CNT)
29955 #define G_CHNL1_MAX_DEFICIT_CNT(x) (((x) >> S_CHNL1_MAX_DEFICIT_CNT) & M_CHNL1_MAX_DEFICIT_CNT)
29956 
29957 #define S_CHNL0_MAX_DEFICIT_CNT    0
29958 #define M_CHNL0_MAX_DEFICIT_CNT    0xffffU
29959 #define V_CHNL0_MAX_DEFICIT_CNT(x) ((x) << S_CHNL0_MAX_DEFICIT_CNT)
29960 #define G_CHNL0_MAX_DEFICIT_CNT(x) (((x) >> S_CHNL0_MAX_DEFICIT_CNT) & M_CHNL0_MAX_DEFICIT_CNT)
29961 
29962 #define A_PM_RX_FEATURE_EN 0x1001d
29963 
29964 #define S_PIO_CH_DEFICIT_CTL_EN_RX    0
29965 #define V_PIO_CH_DEFICIT_CTL_EN_RX(x) ((x) << S_PIO_CH_DEFICIT_CTL_EN_RX)
29966 #define F_PIO_CH_DEFICIT_CTL_EN_RX    V_PIO_CH_DEFICIT_CTL_EN_RX(1U)
29967 
29968 #define A_PM_RX_CH0_OSPI_DEFICIT_THRSHLD 0x1001e
29969 
29970 #define S_CH0_OSPI_DEFICIT_THRSHLD    0
29971 #define M_CH0_OSPI_DEFICIT_THRSHLD    0xfffU
29972 #define V_CH0_OSPI_DEFICIT_THRSHLD(x) ((x) << S_CH0_OSPI_DEFICIT_THRSHLD)
29973 #define G_CH0_OSPI_DEFICIT_THRSHLD(x) (((x) >> S_CH0_OSPI_DEFICIT_THRSHLD) & M_CH0_OSPI_DEFICIT_THRSHLD)
29974 
29975 #define A_PM_RX_CH1_OSPI_DEFICIT_THRSHLD 0x1001f
29976 
29977 #define S_CH1_OSPI_DEFICIT_THRSHLD    0
29978 #define M_CH1_OSPI_DEFICIT_THRSHLD    0xfffU
29979 #define V_CH1_OSPI_DEFICIT_THRSHLD(x) ((x) << S_CH1_OSPI_DEFICIT_THRSHLD)
29980 #define G_CH1_OSPI_DEFICIT_THRSHLD(x) (((x) >> S_CH1_OSPI_DEFICIT_THRSHLD) & M_CH1_OSPI_DEFICIT_THRSHLD)
29981 
29982 #define A_PM_RX_INT_CAUSE_MASK_HALT 0x10020
29983 #define A_PM_RX_DBG_STAT0 0x10021
29984 
29985 #define S_RX_RD_I_BUSY    29
29986 #define V_RX_RD_I_BUSY(x) ((x) << S_RX_RD_I_BUSY)
29987 #define F_RX_RD_I_BUSY    V_RX_RD_I_BUSY(1U)
29988 
29989 #define S_RX_WR_TO_O_BUSY    28
29990 #define V_RX_WR_TO_O_BUSY(x) ((x) << S_RX_WR_TO_O_BUSY)
29991 #define F_RX_WR_TO_O_BUSY    V_RX_WR_TO_O_BUSY(1U)
29992 
29993 #define S_RX_M_TO_O_BUSY    27
29994 #define V_RX_M_TO_O_BUSY(x) ((x) << S_RX_M_TO_O_BUSY)
29995 #define F_RX_M_TO_O_BUSY    V_RX_M_TO_O_BUSY(1U)
29996 
29997 #define S_RX_I_TO_M_BUSY    26
29998 #define V_RX_I_TO_M_BUSY(x) ((x) << S_RX_I_TO_M_BUSY)
29999 #define F_RX_I_TO_M_BUSY    V_RX_I_TO_M_BUSY(1U)
30000 
30001 #define S_RX_PCMD_FB_ONLY    25
30002 #define V_RX_PCMD_FB_ONLY(x) ((x) << S_RX_PCMD_FB_ONLY)
30003 #define F_RX_PCMD_FB_ONLY    V_RX_PCMD_FB_ONLY(1U)
30004 
30005 #define S_RX_PCMD_MEM    24
30006 #define V_RX_PCMD_MEM(x) ((x) << S_RX_PCMD_MEM)
30007 #define F_RX_PCMD_MEM    V_RX_PCMD_MEM(1U)
30008 
30009 #define S_RX_PCMD_BYPASS    23
30010 #define V_RX_PCMD_BYPASS(x) ((x) << S_RX_PCMD_BYPASS)
30011 #define F_RX_PCMD_BYPASS    V_RX_PCMD_BYPASS(1U)
30012 
30013 #define S_RX_PCMD_EOP    22
30014 #define V_RX_PCMD_EOP(x) ((x) << S_RX_PCMD_EOP)
30015 #define F_RX_PCMD_EOP    V_RX_PCMD_EOP(1U)
30016 
30017 #define S_RX_DUMPLICATE_PCMD_EOP    21
30018 #define V_RX_DUMPLICATE_PCMD_EOP(x) ((x) << S_RX_DUMPLICATE_PCMD_EOP)
30019 #define F_RX_DUMPLICATE_PCMD_EOP    V_RX_DUMPLICATE_PCMD_EOP(1U)
30020 
30021 #define S_RX_PCMD_EOB    20
30022 #define V_RX_PCMD_EOB(x) ((x) << S_RX_PCMD_EOB)
30023 #define F_RX_PCMD_EOB    V_RX_PCMD_EOB(1U)
30024 
30025 #define S_RX_PCMD_FB    16
30026 #define M_RX_PCMD_FB    0xfU
30027 #define V_RX_PCMD_FB(x) ((x) << S_RX_PCMD_FB)
30028 #define G_RX_PCMD_FB(x) (((x) >> S_RX_PCMD_FB) & M_RX_PCMD_FB)
30029 
30030 #define S_RX_PCMD_LEN    0
30031 #define M_RX_PCMD_LEN    0xffffU
30032 #define V_RX_PCMD_LEN(x) ((x) << S_RX_PCMD_LEN)
30033 #define G_RX_PCMD_LEN(x) (((x) >> S_RX_PCMD_LEN) & M_RX_PCMD_LEN)
30034 
30035 #define A_PM_RX_DBG_STAT1 0x10022
30036 
30037 #define S_RX_PCMD0_MEM    30
30038 #define V_RX_PCMD0_MEM(x) ((x) << S_RX_PCMD0_MEM)
30039 #define F_RX_PCMD0_MEM    V_RX_PCMD0_MEM(1U)
30040 
30041 #define S_RX_FREE_OSPI_CNT0    18
30042 #define M_RX_FREE_OSPI_CNT0    0xfffU
30043 #define V_RX_FREE_OSPI_CNT0(x) ((x) << S_RX_FREE_OSPI_CNT0)
30044 #define G_RX_FREE_OSPI_CNT0(x) (((x) >> S_RX_FREE_OSPI_CNT0) & M_RX_FREE_OSPI_CNT0)
30045 
30046 #define S_RX_PCMD0_FLIT_LEN    6
30047 #define M_RX_PCMD0_FLIT_LEN    0xfffU
30048 #define V_RX_PCMD0_FLIT_LEN(x) ((x) << S_RX_PCMD0_FLIT_LEN)
30049 #define G_RX_PCMD0_FLIT_LEN(x) (((x) >> S_RX_PCMD0_FLIT_LEN) & M_RX_PCMD0_FLIT_LEN)
30050 
30051 #define S_RX_PCMD0_CMD    2
30052 #define M_RX_PCMD0_CMD    0xfU
30053 #define V_RX_PCMD0_CMD(x) ((x) << S_RX_PCMD0_CMD)
30054 #define G_RX_PCMD0_CMD(x) (((x) >> S_RX_PCMD0_CMD) & M_RX_PCMD0_CMD)
30055 
30056 #define S_RX_OFIFO_FULL0    1
30057 #define V_RX_OFIFO_FULL0(x) ((x) << S_RX_OFIFO_FULL0)
30058 #define F_RX_OFIFO_FULL0    V_RX_OFIFO_FULL0(1U)
30059 
30060 #define S_RX_PCMD0_BYPASS    0
30061 #define V_RX_PCMD0_BYPASS(x) ((x) << S_RX_PCMD0_BYPASS)
30062 #define F_RX_PCMD0_BYPASS    V_RX_PCMD0_BYPASS(1U)
30063 
30064 #define A_PM_RX_DBG_STAT2 0x10023
30065 
30066 #define S_RX_PCMD1_MEM    30
30067 #define V_RX_PCMD1_MEM(x) ((x) << S_RX_PCMD1_MEM)
30068 #define F_RX_PCMD1_MEM    V_RX_PCMD1_MEM(1U)
30069 
30070 #define S_RX_FREE_OSPI_CNT1    18
30071 #define M_RX_FREE_OSPI_CNT1    0xfffU
30072 #define V_RX_FREE_OSPI_CNT1(x) ((x) << S_RX_FREE_OSPI_CNT1)
30073 #define G_RX_FREE_OSPI_CNT1(x) (((x) >> S_RX_FREE_OSPI_CNT1) & M_RX_FREE_OSPI_CNT1)
30074 
30075 #define S_RX_PCMD1_FLIT_LEN    6
30076 #define M_RX_PCMD1_FLIT_LEN    0xfffU
30077 #define V_RX_PCMD1_FLIT_LEN(x) ((x) << S_RX_PCMD1_FLIT_LEN)
30078 #define G_RX_PCMD1_FLIT_LEN(x) (((x) >> S_RX_PCMD1_FLIT_LEN) & M_RX_PCMD1_FLIT_LEN)
30079 
30080 #define S_RX_PCMD1_CMD    2
30081 #define M_RX_PCMD1_CMD    0xfU
30082 #define V_RX_PCMD1_CMD(x) ((x) << S_RX_PCMD1_CMD)
30083 #define G_RX_PCMD1_CMD(x) (((x) >> S_RX_PCMD1_CMD) & M_RX_PCMD1_CMD)
30084 
30085 #define S_RX_OFIFO_FULL1    1
30086 #define V_RX_OFIFO_FULL1(x) ((x) << S_RX_OFIFO_FULL1)
30087 #define F_RX_OFIFO_FULL1    V_RX_OFIFO_FULL1(1U)
30088 
30089 #define S_RX_PCMD1_BYPASS    0
30090 #define V_RX_PCMD1_BYPASS(x) ((x) << S_RX_PCMD1_BYPASS)
30091 #define F_RX_PCMD1_BYPASS    V_RX_PCMD1_BYPASS(1U)
30092 
30093 #define A_PM_RX_DBG_STAT3 0x10024
30094 
30095 #define S_RX_SET_PCMD_RES_RDY_RD    10
30096 #define M_RX_SET_PCMD_RES_RDY_RD    0x3U
30097 #define V_RX_SET_PCMD_RES_RDY_RD(x) ((x) << S_RX_SET_PCMD_RES_RDY_RD)
30098 #define G_RX_SET_PCMD_RES_RDY_RD(x) (((x) >> S_RX_SET_PCMD_RES_RDY_RD) & M_RX_SET_PCMD_RES_RDY_RD)
30099 
30100 #define S_RX_ISSUED_PREFETCH_RD_E_CLR    8
30101 #define M_RX_ISSUED_PREFETCH_RD_E_CLR    0x3U
30102 #define V_RX_ISSUED_PREFETCH_RD_E_CLR(x) ((x) << S_RX_ISSUED_PREFETCH_RD_E_CLR)
30103 #define G_RX_ISSUED_PREFETCH_RD_E_CLR(x) (((x) >> S_RX_ISSUED_PREFETCH_RD_E_CLR) & M_RX_ISSUED_PREFETCH_RD_E_CLR)
30104 
30105 #define S_RX_ISSUED_PREFETCH_RD    6
30106 #define M_RX_ISSUED_PREFETCH_RD    0x3U
30107 #define V_RX_ISSUED_PREFETCH_RD(x) ((x) << S_RX_ISSUED_PREFETCH_RD)
30108 #define G_RX_ISSUED_PREFETCH_RD(x) (((x) >> S_RX_ISSUED_PREFETCH_RD) & M_RX_ISSUED_PREFETCH_RD)
30109 
30110 #define S_RX_PCMD_RES_RDY    4
30111 #define M_RX_PCMD_RES_RDY    0x3U
30112 #define V_RX_PCMD_RES_RDY(x) ((x) << S_RX_PCMD_RES_RDY)
30113 #define G_RX_PCMD_RES_RDY(x) (((x) >> S_RX_PCMD_RES_RDY) & M_RX_PCMD_RES_RDY)
30114 
30115 #define S_RX_DB_VLD    3
30116 #define V_RX_DB_VLD(x) ((x) << S_RX_DB_VLD)
30117 #define F_RX_DB_VLD    V_RX_DB_VLD(1U)
30118 
30119 #define S_RX_FIRST_BUNDLE    1
30120 #define M_RX_FIRST_BUNDLE    0x3U
30121 #define V_RX_FIRST_BUNDLE(x) ((x) << S_RX_FIRST_BUNDLE)
30122 #define G_RX_FIRST_BUNDLE(x) (((x) >> S_RX_FIRST_BUNDLE) & M_RX_FIRST_BUNDLE)
30123 
30124 #define S_RX_SDC_DRDY    0
30125 #define V_RX_SDC_DRDY(x) ((x) << S_RX_SDC_DRDY)
30126 #define F_RX_SDC_DRDY    V_RX_SDC_DRDY(1U)
30127 
30128 #define A_PM_RX_DBG_STAT4 0x10025
30129 
30130 #define S_RX_PCMD_VLD    26
30131 #define V_RX_PCMD_VLD(x) ((x) << S_RX_PCMD_VLD)
30132 #define F_RX_PCMD_VLD    V_RX_PCMD_VLD(1U)
30133 
30134 #define S_RX_PCMD_TO_CH    25
30135 #define V_RX_PCMD_TO_CH(x) ((x) << S_RX_PCMD_TO_CH)
30136 #define F_RX_PCMD_TO_CH    V_RX_PCMD_TO_CH(1U)
30137 
30138 #define S_RX_PCMD_FROM_CH    23
30139 #define M_RX_PCMD_FROM_CH    0x3U
30140 #define V_RX_PCMD_FROM_CH(x) ((x) << S_RX_PCMD_FROM_CH)
30141 #define G_RX_PCMD_FROM_CH(x) (((x) >> S_RX_PCMD_FROM_CH) & M_RX_PCMD_FROM_CH)
30142 
30143 #define S_RX_LINE    18
30144 #define M_RX_LINE    0x1fU
30145 #define V_RX_LINE(x) ((x) << S_RX_LINE)
30146 #define G_RX_LINE(x) (((x) >> S_RX_LINE) & M_RX_LINE)
30147 
30148 #define S_RX_IESPI_TXVALID    14
30149 #define M_RX_IESPI_TXVALID    0xfU
30150 #define V_RX_IESPI_TXVALID(x) ((x) << S_RX_IESPI_TXVALID)
30151 #define G_RX_IESPI_TXVALID(x) (((x) >> S_RX_IESPI_TXVALID) & M_RX_IESPI_TXVALID)
30152 
30153 #define S_RX_IESPI_TXFULL    10
30154 #define M_RX_IESPI_TXFULL    0xfU
30155 #define V_RX_IESPI_TXFULL(x) ((x) << S_RX_IESPI_TXFULL)
30156 #define G_RX_IESPI_TXFULL(x) (((x) >> S_RX_IESPI_TXFULL) & M_RX_IESPI_TXFULL)
30157 
30158 #define S_RX_PCMD_SRDY    8
30159 #define M_RX_PCMD_SRDY    0x3U
30160 #define V_RX_PCMD_SRDY(x) ((x) << S_RX_PCMD_SRDY)
30161 #define G_RX_PCMD_SRDY(x) (((x) >> S_RX_PCMD_SRDY) & M_RX_PCMD_SRDY)
30162 
30163 #define S_RX_PCMD_DRDY    6
30164 #define M_RX_PCMD_DRDY    0x3U
30165 #define V_RX_PCMD_DRDY(x) ((x) << S_RX_PCMD_DRDY)
30166 #define G_RX_PCMD_DRDY(x) (((x) >> S_RX_PCMD_DRDY) & M_RX_PCMD_DRDY)
30167 
30168 #define S_RX_PCMD_CMD    2
30169 #define M_RX_PCMD_CMD    0xfU
30170 #define V_RX_PCMD_CMD(x) ((x) << S_RX_PCMD_CMD)
30171 #define G_RX_PCMD_CMD(x) (((x) >> S_RX_PCMD_CMD) & M_RX_PCMD_CMD)
30172 
30173 #define S_DUPLICATE    0
30174 #define M_DUPLICATE    0x3U
30175 #define V_DUPLICATE(x) ((x) << S_DUPLICATE)
30176 #define G_DUPLICATE(x) (((x) >> S_DUPLICATE) & M_DUPLICATE)
30177 
30178 #define S_RX_PCMD_SRDY_STAT4    8
30179 #define M_RX_PCMD_SRDY_STAT4    0x3U
30180 #define V_RX_PCMD_SRDY_STAT4(x) ((x) << S_RX_PCMD_SRDY_STAT4)
30181 #define G_RX_PCMD_SRDY_STAT4(x) (((x) >> S_RX_PCMD_SRDY_STAT4) & M_RX_PCMD_SRDY_STAT4)
30182 
30183 #define S_RX_PCMD_DRDY_STAT4    6
30184 #define M_RX_PCMD_DRDY_STAT4    0x3U
30185 #define V_RX_PCMD_DRDY_STAT4(x) ((x) << S_RX_PCMD_DRDY_STAT4)
30186 #define G_RX_PCMD_DRDY_STAT4(x) (((x) >> S_RX_PCMD_DRDY_STAT4) & M_RX_PCMD_DRDY_STAT4)
30187 
30188 #define A_PM_RX_DBG_STAT5 0x10026
30189 
30190 #define S_RX_ATLST_1_PCMD_CH1    29
30191 #define V_RX_ATLST_1_PCMD_CH1(x) ((x) << S_RX_ATLST_1_PCMD_CH1)
30192 #define F_RX_ATLST_1_PCMD_CH1    V_RX_ATLST_1_PCMD_CH1(1U)
30193 
30194 #define S_RX_ATLST_1_PCMD_CH0    28
30195 #define V_RX_ATLST_1_PCMD_CH0(x) ((x) << S_RX_ATLST_1_PCMD_CH0)
30196 #define F_RX_ATLST_1_PCMD_CH0    V_RX_ATLST_1_PCMD_CH0(1U)
30197 
30198 #define S_T5_RX_PCMD_DRDY    26
30199 #define M_T5_RX_PCMD_DRDY    0x3U
30200 #define V_T5_RX_PCMD_DRDY(x) ((x) << S_T5_RX_PCMD_DRDY)
30201 #define G_T5_RX_PCMD_DRDY(x) (((x) >> S_T5_RX_PCMD_DRDY) & M_T5_RX_PCMD_DRDY)
30202 
30203 #define S_T5_RX_PCMD_SRDY    24
30204 #define M_T5_RX_PCMD_SRDY    0x3U
30205 #define V_T5_RX_PCMD_SRDY(x) ((x) << S_T5_RX_PCMD_SRDY)
30206 #define G_T5_RX_PCMD_SRDY(x) (((x) >> S_T5_RX_PCMD_SRDY) & M_T5_RX_PCMD_SRDY)
30207 
30208 #define S_RX_ISPI_TXVALID    20
30209 #define M_RX_ISPI_TXVALID    0xfU
30210 #define V_RX_ISPI_TXVALID(x) ((x) << S_RX_ISPI_TXVALID)
30211 #define G_RX_ISPI_TXVALID(x) (((x) >> S_RX_ISPI_TXVALID) & M_RX_ISPI_TXVALID)
30212 
30213 #define S_RX_ISPI_FULL    16
30214 #define M_RX_ISPI_FULL    0xfU
30215 #define V_RX_ISPI_FULL(x) ((x) << S_RX_ISPI_FULL)
30216 #define G_RX_ISPI_FULL(x) (((x) >> S_RX_ISPI_FULL) & M_RX_ISPI_FULL)
30217 
30218 #define S_RX_OSPI_TXVALID    14
30219 #define M_RX_OSPI_TXVALID    0x3U
30220 #define V_RX_OSPI_TXVALID(x) ((x) << S_RX_OSPI_TXVALID)
30221 #define G_RX_OSPI_TXVALID(x) (((x) >> S_RX_OSPI_TXVALID) & M_RX_OSPI_TXVALID)
30222 
30223 #define S_RX_OSPI_FULL    12
30224 #define M_RX_OSPI_FULL    0x3U
30225 #define V_RX_OSPI_FULL(x) ((x) << S_RX_OSPI_FULL)
30226 #define G_RX_OSPI_FULL(x) (((x) >> S_RX_OSPI_FULL) & M_RX_OSPI_FULL)
30227 
30228 #define S_RX_E_RXVALID    8
30229 #define M_RX_E_RXVALID    0xfU
30230 #define V_RX_E_RXVALID(x) ((x) << S_RX_E_RXVALID)
30231 #define G_RX_E_RXVALID(x) (((x) >> S_RX_E_RXVALID) & M_RX_E_RXVALID)
30232 
30233 #define S_RX_E_RXAFULL    4
30234 #define M_RX_E_RXAFULL    0xfU
30235 #define V_RX_E_RXAFULL(x) ((x) << S_RX_E_RXAFULL)
30236 #define G_RX_E_RXAFULL(x) (((x) >> S_RX_E_RXAFULL) & M_RX_E_RXAFULL)
30237 
30238 #define S_RX_C_TXVALID    2
30239 #define M_RX_C_TXVALID    0x3U
30240 #define V_RX_C_TXVALID(x) ((x) << S_RX_C_TXVALID)
30241 #define G_RX_C_TXVALID(x) (((x) >> S_RX_C_TXVALID) & M_RX_C_TXVALID)
30242 
30243 #define S_RX_C_TXAFULL    0
30244 #define M_RX_C_TXAFULL    0x3U
30245 #define V_RX_C_TXAFULL(x) ((x) << S_RX_C_TXAFULL)
30246 #define G_RX_C_TXAFULL(x) (((x) >> S_RX_C_TXAFULL) & M_RX_C_TXAFULL)
30247 
30248 #define S_T6_RX_PCMD_DRDY    26
30249 #define M_T6_RX_PCMD_DRDY    0x3U
30250 #define V_T6_RX_PCMD_DRDY(x) ((x) << S_T6_RX_PCMD_DRDY)
30251 #define G_T6_RX_PCMD_DRDY(x) (((x) >> S_T6_RX_PCMD_DRDY) & M_T6_RX_PCMD_DRDY)
30252 
30253 #define S_T6_RX_PCMD_SRDY    24
30254 #define M_T6_RX_PCMD_SRDY    0x3U
30255 #define V_T6_RX_PCMD_SRDY(x) ((x) << S_T6_RX_PCMD_SRDY)
30256 #define G_T6_RX_PCMD_SRDY(x) (((x) >> S_T6_RX_PCMD_SRDY) & M_T6_RX_PCMD_SRDY)
30257 
30258 #define A_PM_RX_DBG_STAT6 0x10027
30259 
30260 #define S_RX_M_INTRNL_FIFO_CNT    4
30261 #define M_RX_M_INTRNL_FIFO_CNT    0x3U
30262 #define V_RX_M_INTRNL_FIFO_CNT(x) ((x) << S_RX_M_INTRNL_FIFO_CNT)
30263 #define G_RX_M_INTRNL_FIFO_CNT(x) (((x) >> S_RX_M_INTRNL_FIFO_CNT) & M_RX_M_INTRNL_FIFO_CNT)
30264 
30265 #define S_RX_M_REQADDRRDY    3
30266 #define V_RX_M_REQADDRRDY(x) ((x) << S_RX_M_REQADDRRDY)
30267 #define F_RX_M_REQADDRRDY    V_RX_M_REQADDRRDY(1U)
30268 
30269 #define S_RX_M_REQWRITE    2
30270 #define V_RX_M_REQWRITE(x) ((x) << S_RX_M_REQWRITE)
30271 #define F_RX_M_REQWRITE    V_RX_M_REQWRITE(1U)
30272 
30273 #define S_RX_M_REQDATAVLD    1
30274 #define V_RX_M_REQDATAVLD(x) ((x) << S_RX_M_REQDATAVLD)
30275 #define F_RX_M_REQDATAVLD    V_RX_M_REQDATAVLD(1U)
30276 
30277 #define S_RX_M_REQDATARDY    0
30278 #define V_RX_M_REQDATARDY(x) ((x) << S_RX_M_REQDATARDY)
30279 #define F_RX_M_REQDATARDY    V_RX_M_REQDATARDY(1U)
30280 
30281 #define S_T6_RX_M_INTRNL_FIFO_CNT    7
30282 #define M_T6_RX_M_INTRNL_FIFO_CNT    0x3U
30283 #define V_T6_RX_M_INTRNL_FIFO_CNT(x) ((x) << S_T6_RX_M_INTRNL_FIFO_CNT)
30284 #define G_T6_RX_M_INTRNL_FIFO_CNT(x) (((x) >> S_T6_RX_M_INTRNL_FIFO_CNT) & M_T6_RX_M_INTRNL_FIFO_CNT)
30285 
30286 #define S_RX_M_RSPVLD    6
30287 #define V_RX_M_RSPVLD(x) ((x) << S_RX_M_RSPVLD)
30288 #define F_RX_M_RSPVLD    V_RX_M_RSPVLD(1U)
30289 
30290 #define S_RX_M_RSPRDY    5
30291 #define V_RX_M_RSPRDY(x) ((x) << S_RX_M_RSPRDY)
30292 #define F_RX_M_RSPRDY    V_RX_M_RSPRDY(1U)
30293 
30294 #define S_RX_M_REQADDRVLD    4
30295 #define V_RX_M_REQADDRVLD(x) ((x) << S_RX_M_REQADDRVLD)
30296 #define F_RX_M_REQADDRVLD    V_RX_M_REQADDRVLD(1U)
30297 
30298 #define A_PM_RX_DBG_STAT7 0x10028
30299 
30300 #define S_RX_PCMD1_FREE_CNT    7
30301 #define M_RX_PCMD1_FREE_CNT    0x7fU
30302 #define V_RX_PCMD1_FREE_CNT(x) ((x) << S_RX_PCMD1_FREE_CNT)
30303 #define G_RX_PCMD1_FREE_CNT(x) (((x) >> S_RX_PCMD1_FREE_CNT) & M_RX_PCMD1_FREE_CNT)
30304 
30305 #define S_RX_PCMD0_FREE_CNT    0
30306 #define M_RX_PCMD0_FREE_CNT    0x7fU
30307 #define V_RX_PCMD0_FREE_CNT(x) ((x) << S_RX_PCMD0_FREE_CNT)
30308 #define G_RX_PCMD0_FREE_CNT(x) (((x) >> S_RX_PCMD0_FREE_CNT) & M_RX_PCMD0_FREE_CNT)
30309 
30310 #define A_PM_RX_DBG_STAT8 0x10029
30311 
30312 #define S_RX_IN_EOP_CNT3    28
30313 #define M_RX_IN_EOP_CNT3    0xfU
30314 #define V_RX_IN_EOP_CNT3(x) ((x) << S_RX_IN_EOP_CNT3)
30315 #define G_RX_IN_EOP_CNT3(x) (((x) >> S_RX_IN_EOP_CNT3) & M_RX_IN_EOP_CNT3)
30316 
30317 #define S_RX_IN_EOP_CNT2    24
30318 #define M_RX_IN_EOP_CNT2    0xfU
30319 #define V_RX_IN_EOP_CNT2(x) ((x) << S_RX_IN_EOP_CNT2)
30320 #define G_RX_IN_EOP_CNT2(x) (((x) >> S_RX_IN_EOP_CNT2) & M_RX_IN_EOP_CNT2)
30321 
30322 #define S_RX_IN_EOP_CNT1    20
30323 #define M_RX_IN_EOP_CNT1    0xfU
30324 #define V_RX_IN_EOP_CNT1(x) ((x) << S_RX_IN_EOP_CNT1)
30325 #define G_RX_IN_EOP_CNT1(x) (((x) >> S_RX_IN_EOP_CNT1) & M_RX_IN_EOP_CNT1)
30326 
30327 #define S_RX_IN_EOP_CNT0    16
30328 #define M_RX_IN_EOP_CNT0    0xfU
30329 #define V_RX_IN_EOP_CNT0(x) ((x) << S_RX_IN_EOP_CNT0)
30330 #define G_RX_IN_EOP_CNT0(x) (((x) >> S_RX_IN_EOP_CNT0) & M_RX_IN_EOP_CNT0)
30331 
30332 #define S_RX_IN_SOP_CNT3    12
30333 #define M_RX_IN_SOP_CNT3    0xfU
30334 #define V_RX_IN_SOP_CNT3(x) ((x) << S_RX_IN_SOP_CNT3)
30335 #define G_RX_IN_SOP_CNT3(x) (((x) >> S_RX_IN_SOP_CNT3) & M_RX_IN_SOP_CNT3)
30336 
30337 #define S_RX_IN_SOP_CNT2    8
30338 #define M_RX_IN_SOP_CNT2    0xfU
30339 #define V_RX_IN_SOP_CNT2(x) ((x) << S_RX_IN_SOP_CNT2)
30340 #define G_RX_IN_SOP_CNT2(x) (((x) >> S_RX_IN_SOP_CNT2) & M_RX_IN_SOP_CNT2)
30341 
30342 #define S_RX_IN_SOP_CNT1    4
30343 #define M_RX_IN_SOP_CNT1    0xfU
30344 #define V_RX_IN_SOP_CNT1(x) ((x) << S_RX_IN_SOP_CNT1)
30345 #define G_RX_IN_SOP_CNT1(x) (((x) >> S_RX_IN_SOP_CNT1) & M_RX_IN_SOP_CNT1)
30346 
30347 #define S_RX_IN_SOP_CNT0    0
30348 #define M_RX_IN_SOP_CNT0    0xfU
30349 #define V_RX_IN_SOP_CNT0(x) ((x) << S_RX_IN_SOP_CNT0)
30350 #define G_RX_IN_SOP_CNT0(x) (((x) >> S_RX_IN_SOP_CNT0) & M_RX_IN_SOP_CNT0)
30351 
30352 #define A_PM_RX_DBG_STAT9 0x1002a
30353 
30354 #define S_RX_RSVD0    28
30355 #define M_RX_RSVD0    0xfU
30356 #define V_RX_RSVD0(x) ((x) << S_RX_RSVD0)
30357 #define G_RX_RSVD0(x) (((x) >> S_RX_RSVD0) & M_RX_RSVD0)
30358 
30359 #define S_RX_RSVD1    24
30360 #define M_RX_RSVD1    0xfU
30361 #define V_RX_RSVD1(x) ((x) << S_RX_RSVD1)
30362 #define G_RX_RSVD1(x) (((x) >> S_RX_RSVD1) & M_RX_RSVD1)
30363 
30364 #define S_RX_OUT_EOP_CNT1    20
30365 #define M_RX_OUT_EOP_CNT1    0xfU
30366 #define V_RX_OUT_EOP_CNT1(x) ((x) << S_RX_OUT_EOP_CNT1)
30367 #define G_RX_OUT_EOP_CNT1(x) (((x) >> S_RX_OUT_EOP_CNT1) & M_RX_OUT_EOP_CNT1)
30368 
30369 #define S_RX_OUT_EOP_CNT0    16
30370 #define M_RX_OUT_EOP_CNT0    0xfU
30371 #define V_RX_OUT_EOP_CNT0(x) ((x) << S_RX_OUT_EOP_CNT0)
30372 #define G_RX_OUT_EOP_CNT0(x) (((x) >> S_RX_OUT_EOP_CNT0) & M_RX_OUT_EOP_CNT0)
30373 
30374 #define S_RX_RSVD2    12
30375 #define M_RX_RSVD2    0xfU
30376 #define V_RX_RSVD2(x) ((x) << S_RX_RSVD2)
30377 #define G_RX_RSVD2(x) (((x) >> S_RX_RSVD2) & M_RX_RSVD2)
30378 
30379 #define S_RX_RSVD3    8
30380 #define M_RX_RSVD3    0xfU
30381 #define V_RX_RSVD3(x) ((x) << S_RX_RSVD3)
30382 #define G_RX_RSVD3(x) (((x) >> S_RX_RSVD3) & M_RX_RSVD3)
30383 
30384 #define S_RX_OUT_SOP_CNT1    4
30385 #define M_RX_OUT_SOP_CNT1    0xfU
30386 #define V_RX_OUT_SOP_CNT1(x) ((x) << S_RX_OUT_SOP_CNT1)
30387 #define G_RX_OUT_SOP_CNT1(x) (((x) >> S_RX_OUT_SOP_CNT1) & M_RX_OUT_SOP_CNT1)
30388 
30389 #define S_RX_OUT_SOP_CNT0    0
30390 #define M_RX_OUT_SOP_CNT0    0xfU
30391 #define V_RX_OUT_SOP_CNT0(x) ((x) << S_RX_OUT_SOP_CNT0)
30392 #define G_RX_OUT_SOP_CNT0(x) (((x) >> S_RX_OUT_SOP_CNT0) & M_RX_OUT_SOP_CNT0)
30393 
30394 #define A_PM_RX_DBG_STAT10 0x1002b
30395 
30396 #define S_RX_CH_DEFICIT_BLOWED    24
30397 #define V_RX_CH_DEFICIT_BLOWED(x) ((x) << S_RX_CH_DEFICIT_BLOWED)
30398 #define F_RX_CH_DEFICIT_BLOWED    V_RX_CH_DEFICIT_BLOWED(1U)
30399 
30400 #define S_RX_CH1_DEFICIT    12
30401 #define M_RX_CH1_DEFICIT    0xfffU
30402 #define V_RX_CH1_DEFICIT(x) ((x) << S_RX_CH1_DEFICIT)
30403 #define G_RX_CH1_DEFICIT(x) (((x) >> S_RX_CH1_DEFICIT) & M_RX_CH1_DEFICIT)
30404 
30405 #define S_RX_CH0_DEFICIT    0
30406 #define M_RX_CH0_DEFICIT    0xfffU
30407 #define V_RX_CH0_DEFICIT(x) ((x) << S_RX_CH0_DEFICIT)
30408 #define G_RX_CH0_DEFICIT(x) (((x) >> S_RX_CH0_DEFICIT) & M_RX_CH0_DEFICIT)
30409 
30410 #define A_PM_RX_DBG_STAT11 0x1002c
30411 
30412 #define S_RX_BUNDLE_LEN_SRDY    30
30413 #define M_RX_BUNDLE_LEN_SRDY    0x3U
30414 #define V_RX_BUNDLE_LEN_SRDY(x) ((x) << S_RX_BUNDLE_LEN_SRDY)
30415 #define G_RX_BUNDLE_LEN_SRDY(x) (((x) >> S_RX_BUNDLE_LEN_SRDY) & M_RX_BUNDLE_LEN_SRDY)
30416 
30417 #define S_RX_RSVD11_1    28
30418 #define M_RX_RSVD11_1    0x3U
30419 #define V_RX_RSVD11_1(x) ((x) << S_RX_RSVD11_1)
30420 #define G_RX_RSVD11_1(x) (((x) >> S_RX_RSVD11_1) & M_RX_RSVD11_1)
30421 
30422 #define S_RX_BUNDLE_LEN1    16
30423 #define M_RX_BUNDLE_LEN1    0xfffU
30424 #define V_RX_BUNDLE_LEN1(x) ((x) << S_RX_BUNDLE_LEN1)
30425 #define G_RX_BUNDLE_LEN1(x) (((x) >> S_RX_BUNDLE_LEN1) & M_RX_BUNDLE_LEN1)
30426 
30427 #define S_RX_RSVD11    12
30428 #define M_RX_RSVD11    0xfU
30429 #define V_RX_RSVD11(x) ((x) << S_RX_RSVD11)
30430 #define G_RX_RSVD11(x) (((x) >> S_RX_RSVD11) & M_RX_RSVD11)
30431 
30432 #define S_RX_BUNDLE_LEN0    0
30433 #define M_RX_BUNDLE_LEN0    0xfffU
30434 #define V_RX_BUNDLE_LEN0(x) ((x) << S_RX_BUNDLE_LEN0)
30435 #define G_RX_BUNDLE_LEN0(x) (((x) >> S_RX_BUNDLE_LEN0) & M_RX_BUNDLE_LEN0)
30436 
30437 /* registers for module PM_TX */
30438 #define PM_TX_BASE_ADDR 0x8fe0
30439 
30440 #define A_PM_TX_CFG 0x8fe0
30441 
30442 #define S_CH3_OUTPUT    17
30443 #define M_CH3_OUTPUT    0x1fU
30444 #define V_CH3_OUTPUT(x) ((x) << S_CH3_OUTPUT)
30445 #define G_CH3_OUTPUT(x) (((x) >> S_CH3_OUTPUT) & M_CH3_OUTPUT)
30446 
30447 #define A_PM_TX_MODE 0x8fe4
30448 
30449 #define S_CONG_THRESH3    25
30450 #define M_CONG_THRESH3    0x7fU
30451 #define V_CONG_THRESH3(x) ((x) << S_CONG_THRESH3)
30452 #define G_CONG_THRESH3(x) (((x) >> S_CONG_THRESH3) & M_CONG_THRESH3)
30453 
30454 #define S_CONG_THRESH2    18
30455 #define M_CONG_THRESH2    0x7fU
30456 #define V_CONG_THRESH2(x) ((x) << S_CONG_THRESH2)
30457 #define G_CONG_THRESH2(x) (((x) >> S_CONG_THRESH2) & M_CONG_THRESH2)
30458 
30459 #define S_CONG_THRESH1    11
30460 #define M_CONG_THRESH1    0x7fU
30461 #define V_CONG_THRESH1(x) ((x) << S_CONG_THRESH1)
30462 #define G_CONG_THRESH1(x) (((x) >> S_CONG_THRESH1) & M_CONG_THRESH1)
30463 
30464 #define S_CONG_THRESH0    4
30465 #define M_CONG_THRESH0    0x7fU
30466 #define V_CONG_THRESH0(x) ((x) << S_CONG_THRESH0)
30467 #define G_CONG_THRESH0(x) (((x) >> S_CONG_THRESH0) & M_CONG_THRESH0)
30468 
30469 #define S_TX_USE_BUNDLE_LEN    3
30470 #define V_TX_USE_BUNDLE_LEN(x) ((x) << S_TX_USE_BUNDLE_LEN)
30471 #define F_TX_USE_BUNDLE_LEN    V_TX_USE_BUNDLE_LEN(1U)
30472 
30473 #define S_STAT_CHANNEL    1
30474 #define M_STAT_CHANNEL    0x3U
30475 #define V_STAT_CHANNEL(x) ((x) << S_STAT_CHANNEL)
30476 #define G_STAT_CHANNEL(x) (((x) >> S_STAT_CHANNEL) & M_STAT_CHANNEL)
30477 
30478 #define A_PM_TX_STAT_CONFIG 0x8fe8
30479 #define A_PM_TX_STAT_COUNT 0x8fec
30480 #define A_PM_TX_STAT_LSB 0x8ff0
30481 #define A_PM_TX_DBG_CTRL 0x8ff0
30482 
30483 #define S_OSPIWRBUSY    21
30484 #define M_OSPIWRBUSY    0xfU
30485 #define V_OSPIWRBUSY(x) ((x) << S_OSPIWRBUSY)
30486 #define G_OSPIWRBUSY(x) (((x) >> S_OSPIWRBUSY) & M_OSPIWRBUSY)
30487 
30488 #define A_PM_TX_STAT_MSB 0x8ff4
30489 #define A_PM_TX_DBG_DATA 0x8ff4
30490 #define A_PM_TX_INT_ENABLE 0x8ff8
30491 
30492 #define S_PCMD_LEN_OVFL0    31
30493 #define V_PCMD_LEN_OVFL0(x) ((x) << S_PCMD_LEN_OVFL0)
30494 #define F_PCMD_LEN_OVFL0    V_PCMD_LEN_OVFL0(1U)
30495 
30496 #define S_PCMD_LEN_OVFL1    30
30497 #define V_PCMD_LEN_OVFL1(x) ((x) << S_PCMD_LEN_OVFL1)
30498 #define F_PCMD_LEN_OVFL1    V_PCMD_LEN_OVFL1(1U)
30499 
30500 #define S_PCMD_LEN_OVFL2    29
30501 #define V_PCMD_LEN_OVFL2(x) ((x) << S_PCMD_LEN_OVFL2)
30502 #define F_PCMD_LEN_OVFL2    V_PCMD_LEN_OVFL2(1U)
30503 
30504 #define S_ZERO_C_CMD_ERRO    28
30505 #define V_ZERO_C_CMD_ERRO(x) ((x) << S_ZERO_C_CMD_ERRO)
30506 #define F_ZERO_C_CMD_ERRO    V_ZERO_C_CMD_ERRO(1U)
30507 
30508 #define S_ICSPI0_FIFO2X_RX_FRAMING_ERROR    27
30509 #define V_ICSPI0_FIFO2X_RX_FRAMING_ERROR(x) ((x) << S_ICSPI0_FIFO2X_RX_FRAMING_ERROR)
30510 #define F_ICSPI0_FIFO2X_RX_FRAMING_ERROR    V_ICSPI0_FIFO2X_RX_FRAMING_ERROR(1U)
30511 
30512 #define S_ICSPI1_FIFO2X_RX_FRAMING_ERROR    26
30513 #define V_ICSPI1_FIFO2X_RX_FRAMING_ERROR(x) ((x) << S_ICSPI1_FIFO2X_RX_FRAMING_ERROR)
30514 #define F_ICSPI1_FIFO2X_RX_FRAMING_ERROR    V_ICSPI1_FIFO2X_RX_FRAMING_ERROR(1U)
30515 
30516 #define S_ICSPI2_FIFO2X_RX_FRAMING_ERROR    25
30517 #define V_ICSPI2_FIFO2X_RX_FRAMING_ERROR(x) ((x) << S_ICSPI2_FIFO2X_RX_FRAMING_ERROR)
30518 #define F_ICSPI2_FIFO2X_RX_FRAMING_ERROR    V_ICSPI2_FIFO2X_RX_FRAMING_ERROR(1U)
30519 
30520 #define S_ICSPI3_FIFO2X_RX_FRAMING_ERROR    24
30521 #define V_ICSPI3_FIFO2X_RX_FRAMING_ERROR(x) ((x) << S_ICSPI3_FIFO2X_RX_FRAMING_ERROR)
30522 #define F_ICSPI3_FIFO2X_RX_FRAMING_ERROR    V_ICSPI3_FIFO2X_RX_FRAMING_ERROR(1U)
30523 
30524 #define S_ICSPI0_RX_FRAMING_ERROR    23
30525 #define V_ICSPI0_RX_FRAMING_ERROR(x) ((x) << S_ICSPI0_RX_FRAMING_ERROR)
30526 #define F_ICSPI0_RX_FRAMING_ERROR    V_ICSPI0_RX_FRAMING_ERROR(1U)
30527 
30528 #define S_ICSPI1_RX_FRAMING_ERROR    22
30529 #define V_ICSPI1_RX_FRAMING_ERROR(x) ((x) << S_ICSPI1_RX_FRAMING_ERROR)
30530 #define F_ICSPI1_RX_FRAMING_ERROR    V_ICSPI1_RX_FRAMING_ERROR(1U)
30531 
30532 #define S_ICSPI2_RX_FRAMING_ERROR    21
30533 #define V_ICSPI2_RX_FRAMING_ERROR(x) ((x) << S_ICSPI2_RX_FRAMING_ERROR)
30534 #define F_ICSPI2_RX_FRAMING_ERROR    V_ICSPI2_RX_FRAMING_ERROR(1U)
30535 
30536 #define S_ICSPI3_RX_FRAMING_ERROR    20
30537 #define V_ICSPI3_RX_FRAMING_ERROR(x) ((x) << S_ICSPI3_RX_FRAMING_ERROR)
30538 #define F_ICSPI3_RX_FRAMING_ERROR    V_ICSPI3_RX_FRAMING_ERROR(1U)
30539 
30540 #define S_ICSPI0_TX_FRAMING_ERROR    19
30541 #define V_ICSPI0_TX_FRAMING_ERROR(x) ((x) << S_ICSPI0_TX_FRAMING_ERROR)
30542 #define F_ICSPI0_TX_FRAMING_ERROR    V_ICSPI0_TX_FRAMING_ERROR(1U)
30543 
30544 #define S_ICSPI1_TX_FRAMING_ERROR    18
30545 #define V_ICSPI1_TX_FRAMING_ERROR(x) ((x) << S_ICSPI1_TX_FRAMING_ERROR)
30546 #define F_ICSPI1_TX_FRAMING_ERROR    V_ICSPI1_TX_FRAMING_ERROR(1U)
30547 
30548 #define S_ICSPI2_TX_FRAMING_ERROR    17
30549 #define V_ICSPI2_TX_FRAMING_ERROR(x) ((x) << S_ICSPI2_TX_FRAMING_ERROR)
30550 #define F_ICSPI2_TX_FRAMING_ERROR    V_ICSPI2_TX_FRAMING_ERROR(1U)
30551 
30552 #define S_ICSPI3_TX_FRAMING_ERROR    16
30553 #define V_ICSPI3_TX_FRAMING_ERROR(x) ((x) << S_ICSPI3_TX_FRAMING_ERROR)
30554 #define F_ICSPI3_TX_FRAMING_ERROR    V_ICSPI3_TX_FRAMING_ERROR(1U)
30555 
30556 #define S_OESPI0_RX_FRAMING_ERROR    15
30557 #define V_OESPI0_RX_FRAMING_ERROR(x) ((x) << S_OESPI0_RX_FRAMING_ERROR)
30558 #define F_OESPI0_RX_FRAMING_ERROR    V_OESPI0_RX_FRAMING_ERROR(1U)
30559 
30560 #define S_OESPI1_RX_FRAMING_ERROR    14
30561 #define V_OESPI1_RX_FRAMING_ERROR(x) ((x) << S_OESPI1_RX_FRAMING_ERROR)
30562 #define F_OESPI1_RX_FRAMING_ERROR    V_OESPI1_RX_FRAMING_ERROR(1U)
30563 
30564 #define S_OESPI2_RX_FRAMING_ERROR    13
30565 #define V_OESPI2_RX_FRAMING_ERROR(x) ((x) << S_OESPI2_RX_FRAMING_ERROR)
30566 #define F_OESPI2_RX_FRAMING_ERROR    V_OESPI2_RX_FRAMING_ERROR(1U)
30567 
30568 #define S_OESPI3_RX_FRAMING_ERROR    12
30569 #define V_OESPI3_RX_FRAMING_ERROR(x) ((x) << S_OESPI3_RX_FRAMING_ERROR)
30570 #define F_OESPI3_RX_FRAMING_ERROR    V_OESPI3_RX_FRAMING_ERROR(1U)
30571 
30572 #define S_OESPI0_TX_FRAMING_ERROR    11
30573 #define V_OESPI0_TX_FRAMING_ERROR(x) ((x) << S_OESPI0_TX_FRAMING_ERROR)
30574 #define F_OESPI0_TX_FRAMING_ERROR    V_OESPI0_TX_FRAMING_ERROR(1U)
30575 
30576 #define S_OESPI1_TX_FRAMING_ERROR    10
30577 #define V_OESPI1_TX_FRAMING_ERROR(x) ((x) << S_OESPI1_TX_FRAMING_ERROR)
30578 #define F_OESPI1_TX_FRAMING_ERROR    V_OESPI1_TX_FRAMING_ERROR(1U)
30579 
30580 #define S_OESPI2_TX_FRAMING_ERROR    9
30581 #define V_OESPI2_TX_FRAMING_ERROR(x) ((x) << S_OESPI2_TX_FRAMING_ERROR)
30582 #define F_OESPI2_TX_FRAMING_ERROR    V_OESPI2_TX_FRAMING_ERROR(1U)
30583 
30584 #define S_OESPI3_TX_FRAMING_ERROR    8
30585 #define V_OESPI3_TX_FRAMING_ERROR(x) ((x) << S_OESPI3_TX_FRAMING_ERROR)
30586 #define F_OESPI3_TX_FRAMING_ERROR    V_OESPI3_TX_FRAMING_ERROR(1U)
30587 
30588 #define S_OESPI0_OFIFO2X_TX_FRAMING_ERROR    7
30589 #define V_OESPI0_OFIFO2X_TX_FRAMING_ERROR(x) ((x) << S_OESPI0_OFIFO2X_TX_FRAMING_ERROR)
30590 #define F_OESPI0_OFIFO2X_TX_FRAMING_ERROR    V_OESPI0_OFIFO2X_TX_FRAMING_ERROR(1U)
30591 
30592 #define S_OESPI1_OFIFO2X_TX_FRAMING_ERROR    6
30593 #define V_OESPI1_OFIFO2X_TX_FRAMING_ERROR(x) ((x) << S_OESPI1_OFIFO2X_TX_FRAMING_ERROR)
30594 #define F_OESPI1_OFIFO2X_TX_FRAMING_ERROR    V_OESPI1_OFIFO2X_TX_FRAMING_ERROR(1U)
30595 
30596 #define S_OESPI2_OFIFO2X_TX_FRAMING_ERROR    5
30597 #define V_OESPI2_OFIFO2X_TX_FRAMING_ERROR(x) ((x) << S_OESPI2_OFIFO2X_TX_FRAMING_ERROR)
30598 #define F_OESPI2_OFIFO2X_TX_FRAMING_ERROR    V_OESPI2_OFIFO2X_TX_FRAMING_ERROR(1U)
30599 
30600 #define S_OESPI3_OFIFO2X_TX_FRAMING_ERROR    4
30601 #define V_OESPI3_OFIFO2X_TX_FRAMING_ERROR(x) ((x) << S_OESPI3_OFIFO2X_TX_FRAMING_ERROR)
30602 #define F_OESPI3_OFIFO2X_TX_FRAMING_ERROR    V_OESPI3_OFIFO2X_TX_FRAMING_ERROR(1U)
30603 
30604 #define S_OESPI_PAR_ERROR    3
30605 #define V_OESPI_PAR_ERROR(x) ((x) << S_OESPI_PAR_ERROR)
30606 #define F_OESPI_PAR_ERROR    V_OESPI_PAR_ERROR(1U)
30607 
30608 #define S_ICSPI_PAR_ERROR    1
30609 #define V_ICSPI_PAR_ERROR(x) ((x) << S_ICSPI_PAR_ERROR)
30610 #define F_ICSPI_PAR_ERROR    V_ICSPI_PAR_ERROR(1U)
30611 
30612 #define S_C_PCMD_PAR_ERROR    0
30613 #define V_C_PCMD_PAR_ERROR(x) ((x) << S_C_PCMD_PAR_ERROR)
30614 #define F_C_PCMD_PAR_ERROR    V_C_PCMD_PAR_ERROR(1U)
30615 
30616 #define A_PM_TX_INT_CAUSE 0x8ffc
30617 
30618 #define S_ZERO_C_CMD_ERROR    28
30619 #define V_ZERO_C_CMD_ERROR(x) ((x) << S_ZERO_C_CMD_ERROR)
30620 #define F_ZERO_C_CMD_ERROR    V_ZERO_C_CMD_ERROR(1U)
30621 
30622 #define S_OSPI_OR_BUNDLE_LEN_PAR_ERR    3
30623 #define V_OSPI_OR_BUNDLE_LEN_PAR_ERR(x) ((x) << S_OSPI_OR_BUNDLE_LEN_PAR_ERR)
30624 #define F_OSPI_OR_BUNDLE_LEN_PAR_ERR    V_OSPI_OR_BUNDLE_LEN_PAR_ERR(1U)
30625 
30626 #define A_PM_TX_ISPI_DBG_4B_DATA0 0x10000
30627 #define A_PM_TX_ISPI_DBG_4B_DATA1 0x10001
30628 #define A_PM_TX_ISPI_DBG_4B_DATA2 0x10002
30629 #define A_PM_TX_ISPI_DBG_4B_DATA3 0x10003
30630 #define A_PM_TX_ISPI_DBG_4B_DATA4 0x10004
30631 #define A_PM_TX_ISPI_DBG_4B_DATA5 0x10005
30632 #define A_PM_TX_ISPI_DBG_4B_DATA6 0x10006
30633 #define A_PM_TX_ISPI_DBG_4B_DATA7 0x10007
30634 #define A_PM_TX_ISPI_DBG_4B_DATA8 0x10008
30635 #define A_PM_TX_OSPI_DBG_4B_DATA0 0x10009
30636 #define A_PM_TX_OSPI_DBG_4B_DATA1 0x1000a
30637 #define A_PM_TX_OSPI_DBG_4B_DATA2 0x1000b
30638 #define A_PM_TX_OSPI_DBG_4B_DATA3 0x1000c
30639 #define A_PM_TX_OSPI_DBG_4B_DATA4 0x1000d
30640 #define A_PM_TX_OSPI_DBG_4B_DATA5 0x1000e
30641 #define A_PM_TX_OSPI_DBG_4B_DATA6 0x1000f
30642 #define A_PM_TX_OSPI_DBG_4B_DATA7 0x10010
30643 #define A_PM_TX_OSPI_DBG_4B_DATA8 0x10011
30644 #define A_PM_TX_OSPI_DBG_4B_DATA9 0x10012
30645 #define A_PM_TX_OSPI_DBG_4B_DATA10 0x10013
30646 #define A_PM_TX_OSPI_DBG_4B_DATA11 0x10014
30647 #define A_PM_TX_OSPI_DBG_4B_DATA12 0x10015
30648 #define A_PM_TX_OSPI_DBG_4B_DATA13 0x10016
30649 #define A_PM_TX_OSPI_DBG_4B_DATA14 0x10017
30650 #define A_PM_TX_OSPI_DBG_4B_DATA15 0x10018
30651 #define A_PM_TX_OSPI_DBG_4B_DATA16 0x10019
30652 #define A_PM_TX_DBG_STAT_MSB 0x1001a
30653 #define A_PM_TX_DBG_STAT_LSB 0x1001b
30654 #define A_PM_TX_DBG_RSVD_FLIT_CNT 0x1001c
30655 #define A_PM_TX_SDC_EN 0x1001d
30656 #define A_PM_TX_INOUT_FIFO_DBG_CHNL_SEL 0x1001e
30657 #define A_PM_TX_INOUT_FIFO_DBG_WR 0x1001f
30658 #define A_PM_TX_INPUT_FIFO_STR_FWD_EN 0x10020
30659 #define A_PM_TX_FEATURE_EN 0x10021
30660 
30661 #define S_PIO_CH_DEFICIT_CTL_EN    2
30662 #define V_PIO_CH_DEFICIT_CTL_EN(x) ((x) << S_PIO_CH_DEFICIT_CTL_EN)
30663 #define F_PIO_CH_DEFICIT_CTL_EN    V_PIO_CH_DEFICIT_CTL_EN(1U)
30664 
30665 #define S_PIO_WRR_BASED_PRFTCH_EN    1
30666 #define V_PIO_WRR_BASED_PRFTCH_EN(x) ((x) << S_PIO_WRR_BASED_PRFTCH_EN)
30667 #define F_PIO_WRR_BASED_PRFTCH_EN    V_PIO_WRR_BASED_PRFTCH_EN(1U)
30668 
30669 #define A_PM_TX_T5_PM_TX_INT_ENABLE 0x10022
30670 
30671 #define S_OSPI_OVERFLOW3    7
30672 #define V_OSPI_OVERFLOW3(x) ((x) << S_OSPI_OVERFLOW3)
30673 #define F_OSPI_OVERFLOW3    V_OSPI_OVERFLOW3(1U)
30674 
30675 #define S_OSPI_OVERFLOW2    6
30676 #define V_OSPI_OVERFLOW2(x) ((x) << S_OSPI_OVERFLOW2)
30677 #define F_OSPI_OVERFLOW2    V_OSPI_OVERFLOW2(1U)
30678 
30679 #define S_T5_OSPI_OVERFLOW1    5
30680 #define V_T5_OSPI_OVERFLOW1(x) ((x) << S_T5_OSPI_OVERFLOW1)
30681 #define F_T5_OSPI_OVERFLOW1    V_T5_OSPI_OVERFLOW1(1U)
30682 
30683 #define S_T5_OSPI_OVERFLOW0    4
30684 #define V_T5_OSPI_OVERFLOW0(x) ((x) << S_T5_OSPI_OVERFLOW0)
30685 #define F_T5_OSPI_OVERFLOW0    V_T5_OSPI_OVERFLOW0(1U)
30686 
30687 #define S_M_INTFPERREN    3
30688 #define V_M_INTFPERREN(x) ((x) << S_M_INTFPERREN)
30689 #define F_M_INTFPERREN    V_M_INTFPERREN(1U)
30690 
30691 #define S_BUNDLE_LEN_PARERR_EN    2
30692 #define V_BUNDLE_LEN_PARERR_EN(x) ((x) << S_BUNDLE_LEN_PARERR_EN)
30693 #define F_BUNDLE_LEN_PARERR_EN    V_BUNDLE_LEN_PARERR_EN(1U)
30694 
30695 #define S_BUNDLE_LEN_OVFL_EN    1
30696 #define V_BUNDLE_LEN_OVFL_EN(x) ((x) << S_BUNDLE_LEN_OVFL_EN)
30697 #define F_BUNDLE_LEN_OVFL_EN    V_BUNDLE_LEN_OVFL_EN(1U)
30698 
30699 #define S_SDC_ERR_EN    0
30700 #define V_SDC_ERR_EN(x) ((x) << S_SDC_ERR_EN)
30701 #define F_SDC_ERR_EN    V_SDC_ERR_EN(1U)
30702 
30703 #define S_OSPI_OVERFLOW3_T5    7
30704 #define V_OSPI_OVERFLOW3_T5(x) ((x) << S_OSPI_OVERFLOW3_T5)
30705 #define F_OSPI_OVERFLOW3_T5    V_OSPI_OVERFLOW3_T5(1U)
30706 
30707 #define S_OSPI_OVERFLOW2_T5    6
30708 #define V_OSPI_OVERFLOW2_T5(x) ((x) << S_OSPI_OVERFLOW2_T5)
30709 #define F_OSPI_OVERFLOW2_T5    V_OSPI_OVERFLOW2_T5(1U)
30710 
30711 #define S_OSPI_OVERFLOW1_T5    5
30712 #define V_OSPI_OVERFLOW1_T5(x) ((x) << S_OSPI_OVERFLOW1_T5)
30713 #define F_OSPI_OVERFLOW1_T5    V_OSPI_OVERFLOW1_T5(1U)
30714 
30715 #define S_OSPI_OVERFLOW0_T5    4
30716 #define V_OSPI_OVERFLOW0_T5(x) ((x) << S_OSPI_OVERFLOW0_T5)
30717 #define F_OSPI_OVERFLOW0_T5    V_OSPI_OVERFLOW0_T5(1U)
30718 
30719 #define A_PM_TX_PRFTCH_WRR_WAIT_CNT_THRSHLD0 0x10023
30720 #define A_PM_TX_PRFTCH_WRR_WAIT_CNT_THRSHLD1 0x10024
30721 #define A_PM_TX_PRFTCH_WRR_WAIT_CNT_THRSHLD2 0x10025
30722 #define A_PM_TX_PRFTCH_WRR_WAIT_CNT_THRSHLD3 0x10026
30723 #define A_PM_TX_CH0_OSPI_DEFICIT_THRSHLD 0x10027
30724 #define A_PM_TX_CH1_OSPI_DEFICIT_THRSHLD 0x10028
30725 #define A_PM_TX_CH2_OSPI_DEFICIT_THRSHLD 0x10029
30726 
30727 #define S_CH2_OSPI_DEFICIT_THRSHLD    0
30728 #define M_CH2_OSPI_DEFICIT_THRSHLD    0xfffU
30729 #define V_CH2_OSPI_DEFICIT_THRSHLD(x) ((x) << S_CH2_OSPI_DEFICIT_THRSHLD)
30730 #define G_CH2_OSPI_DEFICIT_THRSHLD(x) (((x) >> S_CH2_OSPI_DEFICIT_THRSHLD) & M_CH2_OSPI_DEFICIT_THRSHLD)
30731 
30732 #define A_PM_TX_CH3_OSPI_DEFICIT_THRSHLD 0x1002a
30733 
30734 #define S_CH3_OSPI_DEFICIT_THRSHLD    0
30735 #define M_CH3_OSPI_DEFICIT_THRSHLD    0xfffU
30736 #define V_CH3_OSPI_DEFICIT_THRSHLD(x) ((x) << S_CH3_OSPI_DEFICIT_THRSHLD)
30737 #define G_CH3_OSPI_DEFICIT_THRSHLD(x) (((x) >> S_CH3_OSPI_DEFICIT_THRSHLD) & M_CH3_OSPI_DEFICIT_THRSHLD)
30738 
30739 #define A_PM_TX_INT_CAUSE_MASK_HALT 0x1002b
30740 #define A_PM_TX_DBG_STAT0 0x1002c
30741 
30742 #define S_RD_I_BUSY    29
30743 #define V_RD_I_BUSY(x) ((x) << S_RD_I_BUSY)
30744 #define F_RD_I_BUSY    V_RD_I_BUSY(1U)
30745 
30746 #define S_WR_O_BUSY    28
30747 #define V_WR_O_BUSY(x) ((x) << S_WR_O_BUSY)
30748 #define F_WR_O_BUSY    V_WR_O_BUSY(1U)
30749 
30750 #define S_M_TO_O_BUSY    27
30751 #define V_M_TO_O_BUSY(x) ((x) << S_M_TO_O_BUSY)
30752 #define F_M_TO_O_BUSY    V_M_TO_O_BUSY(1U)
30753 
30754 #define S_I_TO_M_BUSY    26
30755 #define V_I_TO_M_BUSY(x) ((x) << S_I_TO_M_BUSY)
30756 #define F_I_TO_M_BUSY    V_I_TO_M_BUSY(1U)
30757 
30758 #define S_PCMD_FB_ONLY    25
30759 #define V_PCMD_FB_ONLY(x) ((x) << S_PCMD_FB_ONLY)
30760 #define F_PCMD_FB_ONLY    V_PCMD_FB_ONLY(1U)
30761 
30762 #define S_PCMD_MEM    24
30763 #define V_PCMD_MEM(x) ((x) << S_PCMD_MEM)
30764 #define F_PCMD_MEM    V_PCMD_MEM(1U)
30765 
30766 #define S_PCMD_BYPASS    23
30767 #define V_PCMD_BYPASS(x) ((x) << S_PCMD_BYPASS)
30768 #define F_PCMD_BYPASS    V_PCMD_BYPASS(1U)
30769 
30770 #define S_PCMD_EOP2    22
30771 #define V_PCMD_EOP2(x) ((x) << S_PCMD_EOP2)
30772 #define F_PCMD_EOP2    V_PCMD_EOP2(1U)
30773 
30774 #define S_PCMD_EOP    21
30775 #define V_PCMD_EOP(x) ((x) << S_PCMD_EOP)
30776 #define F_PCMD_EOP    V_PCMD_EOP(1U)
30777 
30778 #define S_PCMD_END_BUNDLE    20
30779 #define V_PCMD_END_BUNDLE(x) ((x) << S_PCMD_END_BUNDLE)
30780 #define F_PCMD_END_BUNDLE    V_PCMD_END_BUNDLE(1U)
30781 
30782 #define S_PCMD_FB_CMD    16
30783 #define M_PCMD_FB_CMD    0xfU
30784 #define V_PCMD_FB_CMD(x) ((x) << S_PCMD_FB_CMD)
30785 #define G_PCMD_FB_CMD(x) (((x) >> S_PCMD_FB_CMD) & M_PCMD_FB_CMD)
30786 
30787 #define S_CUR_PCMD_LEN    0
30788 #define M_CUR_PCMD_LEN    0xffffU
30789 #define V_CUR_PCMD_LEN(x) ((x) << S_CUR_PCMD_LEN)
30790 #define G_CUR_PCMD_LEN(x) (((x) >> S_CUR_PCMD_LEN) & M_CUR_PCMD_LEN)
30791 
30792 #define S_T6_RD_I_BUSY    28
30793 #define V_T6_RD_I_BUSY(x) ((x) << S_T6_RD_I_BUSY)
30794 #define F_T6_RD_I_BUSY    V_T6_RD_I_BUSY(1U)
30795 
30796 #define S_T6_WR_O_BUSY    27
30797 #define V_T6_WR_O_BUSY(x) ((x) << S_T6_WR_O_BUSY)
30798 #define F_T6_WR_O_BUSY    V_T6_WR_O_BUSY(1U)
30799 
30800 #define S_T6_M_TO_O_BUSY    26
30801 #define V_T6_M_TO_O_BUSY(x) ((x) << S_T6_M_TO_O_BUSY)
30802 #define F_T6_M_TO_O_BUSY    V_T6_M_TO_O_BUSY(1U)
30803 
30804 #define S_T6_I_TO_M_BUSY    25
30805 #define V_T6_I_TO_M_BUSY(x) ((x) << S_T6_I_TO_M_BUSY)
30806 #define F_T6_I_TO_M_BUSY    V_T6_I_TO_M_BUSY(1U)
30807 
30808 #define S_T6_PCMD_FB_ONLY    24
30809 #define V_T6_PCMD_FB_ONLY(x) ((x) << S_T6_PCMD_FB_ONLY)
30810 #define F_T6_PCMD_FB_ONLY    V_T6_PCMD_FB_ONLY(1U)
30811 
30812 #define S_T6_PCMD_MEM    23
30813 #define V_T6_PCMD_MEM(x) ((x) << S_T6_PCMD_MEM)
30814 #define F_T6_PCMD_MEM    V_T6_PCMD_MEM(1U)
30815 
30816 #define S_T6_PCMD_BYPASS    22
30817 #define V_T6_PCMD_BYPASS(x) ((x) << S_T6_PCMD_BYPASS)
30818 #define F_T6_PCMD_BYPASS    V_T6_PCMD_BYPASS(1U)
30819 
30820 #define A_PM_TX_DBG_STAT1 0x1002d
30821 
30822 #define S_PCMD_MEM0    31
30823 #define V_PCMD_MEM0(x) ((x) << S_PCMD_MEM0)
30824 #define F_PCMD_MEM0    V_PCMD_MEM0(1U)
30825 
30826 #define S_FREE_OESPI_CNT0    19
30827 #define M_FREE_OESPI_CNT0    0xfffU
30828 #define V_FREE_OESPI_CNT0(x) ((x) << S_FREE_OESPI_CNT0)
30829 #define G_FREE_OESPI_CNT0(x) (((x) >> S_FREE_OESPI_CNT0) & M_FREE_OESPI_CNT0)
30830 
30831 #define S_PCMD_FLIT_LEN0    7
30832 #define M_PCMD_FLIT_LEN0    0xfffU
30833 #define V_PCMD_FLIT_LEN0(x) ((x) << S_PCMD_FLIT_LEN0)
30834 #define G_PCMD_FLIT_LEN0(x) (((x) >> S_PCMD_FLIT_LEN0) & M_PCMD_FLIT_LEN0)
30835 
30836 #define S_PCMD_CMD0    3
30837 #define M_PCMD_CMD0    0xfU
30838 #define V_PCMD_CMD0(x) ((x) << S_PCMD_CMD0)
30839 #define G_PCMD_CMD0(x) (((x) >> S_PCMD_CMD0) & M_PCMD_CMD0)
30840 
30841 #define S_OFIFO_FULL0    2
30842 #define V_OFIFO_FULL0(x) ((x) << S_OFIFO_FULL0)
30843 #define F_OFIFO_FULL0    V_OFIFO_FULL0(1U)
30844 
30845 #define S_GCSUM_DRDY0    1
30846 #define V_GCSUM_DRDY0(x) ((x) << S_GCSUM_DRDY0)
30847 #define F_GCSUM_DRDY0    V_GCSUM_DRDY0(1U)
30848 
30849 #define S_BYPASS0    0
30850 #define V_BYPASS0(x) ((x) << S_BYPASS0)
30851 #define F_BYPASS0    V_BYPASS0(1U)
30852 
30853 #define A_PM_TX_DBG_STAT2 0x1002e
30854 
30855 #define S_PCMD_MEM1    31
30856 #define V_PCMD_MEM1(x) ((x) << S_PCMD_MEM1)
30857 #define F_PCMD_MEM1    V_PCMD_MEM1(1U)
30858 
30859 #define S_FREE_OESPI_CNT1    19
30860 #define M_FREE_OESPI_CNT1    0xfffU
30861 #define V_FREE_OESPI_CNT1(x) ((x) << S_FREE_OESPI_CNT1)
30862 #define G_FREE_OESPI_CNT1(x) (((x) >> S_FREE_OESPI_CNT1) & M_FREE_OESPI_CNT1)
30863 
30864 #define S_PCMD_FLIT_LEN1    7
30865 #define M_PCMD_FLIT_LEN1    0xfffU
30866 #define V_PCMD_FLIT_LEN1(x) ((x) << S_PCMD_FLIT_LEN1)
30867 #define G_PCMD_FLIT_LEN1(x) (((x) >> S_PCMD_FLIT_LEN1) & M_PCMD_FLIT_LEN1)
30868 
30869 #define S_PCMD_CMD1    3
30870 #define M_PCMD_CMD1    0xfU
30871 #define V_PCMD_CMD1(x) ((x) << S_PCMD_CMD1)
30872 #define G_PCMD_CMD1(x) (((x) >> S_PCMD_CMD1) & M_PCMD_CMD1)
30873 
30874 #define S_OFIFO_FULL1    2
30875 #define V_OFIFO_FULL1(x) ((x) << S_OFIFO_FULL1)
30876 #define F_OFIFO_FULL1    V_OFIFO_FULL1(1U)
30877 
30878 #define S_GCSUM_DRDY1    1
30879 #define V_GCSUM_DRDY1(x) ((x) << S_GCSUM_DRDY1)
30880 #define F_GCSUM_DRDY1    V_GCSUM_DRDY1(1U)
30881 
30882 #define S_BYPASS1    0
30883 #define V_BYPASS1(x) ((x) << S_BYPASS1)
30884 #define F_BYPASS1    V_BYPASS1(1U)
30885 
30886 #define A_PM_TX_DBG_STAT3 0x1002f
30887 
30888 #define S_PCMD_MEM2    31
30889 #define V_PCMD_MEM2(x) ((x) << S_PCMD_MEM2)
30890 #define F_PCMD_MEM2    V_PCMD_MEM2(1U)
30891 
30892 #define S_FREE_OESPI_CNT2    19
30893 #define M_FREE_OESPI_CNT2    0xfffU
30894 #define V_FREE_OESPI_CNT2(x) ((x) << S_FREE_OESPI_CNT2)
30895 #define G_FREE_OESPI_CNT2(x) (((x) >> S_FREE_OESPI_CNT2) & M_FREE_OESPI_CNT2)
30896 
30897 #define S_PCMD_FLIT_LEN2    7
30898 #define M_PCMD_FLIT_LEN2    0xfffU
30899 #define V_PCMD_FLIT_LEN2(x) ((x) << S_PCMD_FLIT_LEN2)
30900 #define G_PCMD_FLIT_LEN2(x) (((x) >> S_PCMD_FLIT_LEN2) & M_PCMD_FLIT_LEN2)
30901 
30902 #define S_PCMD_CMD2    3
30903 #define M_PCMD_CMD2    0xfU
30904 #define V_PCMD_CMD2(x) ((x) << S_PCMD_CMD2)
30905 #define G_PCMD_CMD2(x) (((x) >> S_PCMD_CMD2) & M_PCMD_CMD2)
30906 
30907 #define S_OFIFO_FULL2    2
30908 #define V_OFIFO_FULL2(x) ((x) << S_OFIFO_FULL2)
30909 #define F_OFIFO_FULL2    V_OFIFO_FULL2(1U)
30910 
30911 #define S_GCSUM_DRDY2    1
30912 #define V_GCSUM_DRDY2(x) ((x) << S_GCSUM_DRDY2)
30913 #define F_GCSUM_DRDY2    V_GCSUM_DRDY2(1U)
30914 
30915 #define S_BYPASS2    0
30916 #define V_BYPASS2(x) ((x) << S_BYPASS2)
30917 #define F_BYPASS2    V_BYPASS2(1U)
30918 
30919 #define A_PM_TX_DBG_STAT4 0x10030
30920 
30921 #define S_PCMD_MEM3    31
30922 #define V_PCMD_MEM3(x) ((x) << S_PCMD_MEM3)
30923 #define F_PCMD_MEM3    V_PCMD_MEM3(1U)
30924 
30925 #define S_FREE_OESPI_CNT3    19
30926 #define M_FREE_OESPI_CNT3    0xfffU
30927 #define V_FREE_OESPI_CNT3(x) ((x) << S_FREE_OESPI_CNT3)
30928 #define G_FREE_OESPI_CNT3(x) (((x) >> S_FREE_OESPI_CNT3) & M_FREE_OESPI_CNT3)
30929 
30930 #define S_PCMD_FLIT_LEN3    7
30931 #define M_PCMD_FLIT_LEN3    0xfffU
30932 #define V_PCMD_FLIT_LEN3(x) ((x) << S_PCMD_FLIT_LEN3)
30933 #define G_PCMD_FLIT_LEN3(x) (((x) >> S_PCMD_FLIT_LEN3) & M_PCMD_FLIT_LEN3)
30934 
30935 #define S_PCMD_CMD3    3
30936 #define M_PCMD_CMD3    0xfU
30937 #define V_PCMD_CMD3(x) ((x) << S_PCMD_CMD3)
30938 #define G_PCMD_CMD3(x) (((x) >> S_PCMD_CMD3) & M_PCMD_CMD3)
30939 
30940 #define S_OFIFO_FULL3    2
30941 #define V_OFIFO_FULL3(x) ((x) << S_OFIFO_FULL3)
30942 #define F_OFIFO_FULL3    V_OFIFO_FULL3(1U)
30943 
30944 #define S_GCSUM_DRDY3    1
30945 #define V_GCSUM_DRDY3(x) ((x) << S_GCSUM_DRDY3)
30946 #define F_GCSUM_DRDY3    V_GCSUM_DRDY3(1U)
30947 
30948 #define S_BYPASS3    0
30949 #define V_BYPASS3(x) ((x) << S_BYPASS3)
30950 #define F_BYPASS3    V_BYPASS3(1U)
30951 
30952 #define A_PM_TX_DBG_STAT5 0x10031
30953 
30954 #define S_SET_PCMD_RES_RDY_RD    24
30955 #define M_SET_PCMD_RES_RDY_RD    0xfU
30956 #define V_SET_PCMD_RES_RDY_RD(x) ((x) << S_SET_PCMD_RES_RDY_RD)
30957 #define G_SET_PCMD_RES_RDY_RD(x) (((x) >> S_SET_PCMD_RES_RDY_RD) & M_SET_PCMD_RES_RDY_RD)
30958 
30959 #define S_ISSUED_PREF_RD_ER_CLR    20
30960 #define M_ISSUED_PREF_RD_ER_CLR    0xfU
30961 #define V_ISSUED_PREF_RD_ER_CLR(x) ((x) << S_ISSUED_PREF_RD_ER_CLR)
30962 #define G_ISSUED_PREF_RD_ER_CLR(x) (((x) >> S_ISSUED_PREF_RD_ER_CLR) & M_ISSUED_PREF_RD_ER_CLR)
30963 
30964 #define S_ISSUED_PREF_RD    16
30965 #define M_ISSUED_PREF_RD    0xfU
30966 #define V_ISSUED_PREF_RD(x) ((x) << S_ISSUED_PREF_RD)
30967 #define G_ISSUED_PREF_RD(x) (((x) >> S_ISSUED_PREF_RD) & M_ISSUED_PREF_RD)
30968 
30969 #define S_PCMD_RES_RDY    12
30970 #define M_PCMD_RES_RDY    0xfU
30971 #define V_PCMD_RES_RDY(x) ((x) << S_PCMD_RES_RDY)
30972 #define G_PCMD_RES_RDY(x) (((x) >> S_PCMD_RES_RDY) & M_PCMD_RES_RDY)
30973 
30974 #define S_DB_VLD    11
30975 #define V_DB_VLD(x) ((x) << S_DB_VLD)
30976 #define F_DB_VLD    V_DB_VLD(1U)
30977 
30978 #define S_INJECT0_DRDY    10
30979 #define V_INJECT0_DRDY(x) ((x) << S_INJECT0_DRDY)
30980 #define F_INJECT0_DRDY    V_INJECT0_DRDY(1U)
30981 
30982 #define S_INJECT1_DRDY    9
30983 #define V_INJECT1_DRDY(x) ((x) << S_INJECT1_DRDY)
30984 #define F_INJECT1_DRDY    V_INJECT1_DRDY(1U)
30985 
30986 #define S_FIRST_BUNDLE    5
30987 #define M_FIRST_BUNDLE    0xfU
30988 #define V_FIRST_BUNDLE(x) ((x) << S_FIRST_BUNDLE)
30989 #define G_FIRST_BUNDLE(x) (((x) >> S_FIRST_BUNDLE) & M_FIRST_BUNDLE)
30990 
30991 #define S_GCSUM_MORE_THAN_2_LEFT    1
30992 #define M_GCSUM_MORE_THAN_2_LEFT    0xfU
30993 #define V_GCSUM_MORE_THAN_2_LEFT(x) ((x) << S_GCSUM_MORE_THAN_2_LEFT)
30994 #define G_GCSUM_MORE_THAN_2_LEFT(x) (((x) >> S_GCSUM_MORE_THAN_2_LEFT) & M_GCSUM_MORE_THAN_2_LEFT)
30995 
30996 #define S_SDC_DRDY    0
30997 #define V_SDC_DRDY(x) ((x) << S_SDC_DRDY)
30998 #define F_SDC_DRDY    V_SDC_DRDY(1U)
30999 
31000 #define A_PM_TX_DBG_STAT6 0x10032
31001 
31002 #define S_PCMD_VLD    31
31003 #define V_PCMD_VLD(x) ((x) << S_PCMD_VLD)
31004 #define F_PCMD_VLD    V_PCMD_VLD(1U)
31005 
31006 #define S_PCMD_CH    29
31007 #define M_PCMD_CH    0x3U
31008 #define V_PCMD_CH(x) ((x) << S_PCMD_CH)
31009 #define G_PCMD_CH(x) (((x) >> S_PCMD_CH) & M_PCMD_CH)
31010 
31011 #define S_STATE_MACHINE_LOC    24
31012 #define M_STATE_MACHINE_LOC    0x1fU
31013 #define V_STATE_MACHINE_LOC(x) ((x) << S_STATE_MACHINE_LOC)
31014 #define G_STATE_MACHINE_LOC(x) (((x) >> S_STATE_MACHINE_LOC) & M_STATE_MACHINE_LOC)
31015 
31016 #define S_ICSPI_TXVALID    20
31017 #define M_ICSPI_TXVALID    0xfU
31018 #define V_ICSPI_TXVALID(x) ((x) << S_ICSPI_TXVALID)
31019 #define G_ICSPI_TXVALID(x) (((x) >> S_ICSPI_TXVALID) & M_ICSPI_TXVALID)
31020 
31021 #define S_ICSPI_TXFULL    16
31022 #define M_ICSPI_TXFULL    0xfU
31023 #define V_ICSPI_TXFULL(x) ((x) << S_ICSPI_TXFULL)
31024 #define G_ICSPI_TXFULL(x) (((x) >> S_ICSPI_TXFULL) & M_ICSPI_TXFULL)
31025 
31026 #define S_PCMD_SRDY    12
31027 #define M_PCMD_SRDY    0xfU
31028 #define V_PCMD_SRDY(x) ((x) << S_PCMD_SRDY)
31029 #define G_PCMD_SRDY(x) (((x) >> S_PCMD_SRDY) & M_PCMD_SRDY)
31030 
31031 #define S_PCMD_DRDY    8
31032 #define M_PCMD_DRDY    0xfU
31033 #define V_PCMD_DRDY(x) ((x) << S_PCMD_DRDY)
31034 #define G_PCMD_DRDY(x) (((x) >> S_PCMD_DRDY) & M_PCMD_DRDY)
31035 
31036 #define S_PCMD_CMD    4
31037 #define M_PCMD_CMD    0xfU
31038 #define V_PCMD_CMD(x) ((x) << S_PCMD_CMD)
31039 #define G_PCMD_CMD(x) (((x) >> S_PCMD_CMD) & M_PCMD_CMD)
31040 
31041 #define S_OEFIFO_FULL3    3
31042 #define V_OEFIFO_FULL3(x) ((x) << S_OEFIFO_FULL3)
31043 #define F_OEFIFO_FULL3    V_OEFIFO_FULL3(1U)
31044 
31045 #define S_OEFIFO_FULL2    2
31046 #define V_OEFIFO_FULL2(x) ((x) << S_OEFIFO_FULL2)
31047 #define F_OEFIFO_FULL2    V_OEFIFO_FULL2(1U)
31048 
31049 #define S_OEFIFO_FULL1    1
31050 #define V_OEFIFO_FULL1(x) ((x) << S_OEFIFO_FULL1)
31051 #define F_OEFIFO_FULL1    V_OEFIFO_FULL1(1U)
31052 
31053 #define S_OEFIFO_FULL0    0
31054 #define V_OEFIFO_FULL0(x) ((x) << S_OEFIFO_FULL0)
31055 #define F_OEFIFO_FULL0    V_OEFIFO_FULL0(1U)
31056 
31057 #define A_PM_TX_DBG_STAT7 0x10033
31058 
31059 #define S_ICSPI_RXVALID    28
31060 #define M_ICSPI_RXVALID    0xfU
31061 #define V_ICSPI_RXVALID(x) ((x) << S_ICSPI_RXVALID)
31062 #define G_ICSPI_RXVALID(x) (((x) >> S_ICSPI_RXVALID) & M_ICSPI_RXVALID)
31063 
31064 #define S_ICSPI_RXFULL    24
31065 #define M_ICSPI_RXFULL    0xfU
31066 #define V_ICSPI_RXFULL(x) ((x) << S_ICSPI_RXFULL)
31067 #define G_ICSPI_RXFULL(x) (((x) >> S_ICSPI_RXFULL) & M_ICSPI_RXFULL)
31068 
31069 #define S_OESPI_VALID    20
31070 #define M_OESPI_VALID    0xfU
31071 #define V_OESPI_VALID(x) ((x) << S_OESPI_VALID)
31072 #define G_OESPI_VALID(x) (((x) >> S_OESPI_VALID) & M_OESPI_VALID)
31073 
31074 #define S_OESPI_FULL    16
31075 #define M_OESPI_FULL    0xfU
31076 #define V_OESPI_FULL(x) ((x) << S_OESPI_FULL)
31077 #define G_OESPI_FULL(x) (((x) >> S_OESPI_FULL) & M_OESPI_FULL)
31078 
31079 #define S_C_RXVALID    12
31080 #define M_C_RXVALID    0xfU
31081 #define V_C_RXVALID(x) ((x) << S_C_RXVALID)
31082 #define G_C_RXVALID(x) (((x) >> S_C_RXVALID) & M_C_RXVALID)
31083 
31084 #define S_C_RXAFULL    8
31085 #define M_C_RXAFULL    0xfU
31086 #define V_C_RXAFULL(x) ((x) << S_C_RXAFULL)
31087 #define G_C_RXAFULL(x) (((x) >> S_C_RXAFULL) & M_C_RXAFULL)
31088 
31089 #define S_E_TXVALID3    7
31090 #define V_E_TXVALID3(x) ((x) << S_E_TXVALID3)
31091 #define F_E_TXVALID3    V_E_TXVALID3(1U)
31092 
31093 #define S_E_TXVALID2    6
31094 #define V_E_TXVALID2(x) ((x) << S_E_TXVALID2)
31095 #define F_E_TXVALID2    V_E_TXVALID2(1U)
31096 
31097 #define S_E_TXVALID1    5
31098 #define V_E_TXVALID1(x) ((x) << S_E_TXVALID1)
31099 #define F_E_TXVALID1    V_E_TXVALID1(1U)
31100 
31101 #define S_E_TXVALID0    4
31102 #define V_E_TXVALID0(x) ((x) << S_E_TXVALID0)
31103 #define F_E_TXVALID0    V_E_TXVALID0(1U)
31104 
31105 #define S_E_TXFULL3    3
31106 #define V_E_TXFULL3(x) ((x) << S_E_TXFULL3)
31107 #define F_E_TXFULL3    V_E_TXFULL3(1U)
31108 
31109 #define S_E_TXFULL2    2
31110 #define V_E_TXFULL2(x) ((x) << S_E_TXFULL2)
31111 #define F_E_TXFULL2    V_E_TXFULL2(1U)
31112 
31113 #define S_E_TXFULL1    1
31114 #define V_E_TXFULL1(x) ((x) << S_E_TXFULL1)
31115 #define F_E_TXFULL1    V_E_TXFULL1(1U)
31116 
31117 #define S_E_TXFULL0    0
31118 #define V_E_TXFULL0(x) ((x) << S_E_TXFULL0)
31119 #define F_E_TXFULL0    V_E_TXFULL0(1U)
31120 
31121 #define A_PM_TX_DBG_STAT8 0x10034
31122 
31123 #define S_MC_RSP_FIFO_CNT    24
31124 #define M_MC_RSP_FIFO_CNT    0x3U
31125 #define V_MC_RSP_FIFO_CNT(x) ((x) << S_MC_RSP_FIFO_CNT)
31126 #define G_MC_RSP_FIFO_CNT(x) (((x) >> S_MC_RSP_FIFO_CNT) & M_MC_RSP_FIFO_CNT)
31127 
31128 #define S_PCMD_FREE_CNT0    14
31129 #define M_PCMD_FREE_CNT0    0x3ffU
31130 #define V_PCMD_FREE_CNT0(x) ((x) << S_PCMD_FREE_CNT0)
31131 #define G_PCMD_FREE_CNT0(x) (((x) >> S_PCMD_FREE_CNT0) & M_PCMD_FREE_CNT0)
31132 
31133 #define S_PCMD_FREE_CNT1    4
31134 #define M_PCMD_FREE_CNT1    0x3ffU
31135 #define V_PCMD_FREE_CNT1(x) ((x) << S_PCMD_FREE_CNT1)
31136 #define G_PCMD_FREE_CNT1(x) (((x) >> S_PCMD_FREE_CNT1) & M_PCMD_FREE_CNT1)
31137 
31138 #define S_M_REQADDRRDY    3
31139 #define V_M_REQADDRRDY(x) ((x) << S_M_REQADDRRDY)
31140 #define F_M_REQADDRRDY    V_M_REQADDRRDY(1U)
31141 
31142 #define S_M_REQWRITE    2
31143 #define V_M_REQWRITE(x) ((x) << S_M_REQWRITE)
31144 #define F_M_REQWRITE    V_M_REQWRITE(1U)
31145 
31146 #define S_M_REQDATAVLD    1
31147 #define V_M_REQDATAVLD(x) ((x) << S_M_REQDATAVLD)
31148 #define F_M_REQDATAVLD    V_M_REQDATAVLD(1U)
31149 
31150 #define S_M_REQDATARDY    0
31151 #define V_M_REQDATARDY(x) ((x) << S_M_REQDATARDY)
31152 #define F_M_REQDATARDY    V_M_REQDATARDY(1U)
31153 
31154 #define S_T6_MC_RSP_FIFO_CNT    27
31155 #define M_T6_MC_RSP_FIFO_CNT    0x3U
31156 #define V_T6_MC_RSP_FIFO_CNT(x) ((x) << S_T6_MC_RSP_FIFO_CNT)
31157 #define G_T6_MC_RSP_FIFO_CNT(x) (((x) >> S_T6_MC_RSP_FIFO_CNT) & M_T6_MC_RSP_FIFO_CNT)
31158 
31159 #define S_T6_PCMD_FREE_CNT0    17
31160 #define M_T6_PCMD_FREE_CNT0    0x3ffU
31161 #define V_T6_PCMD_FREE_CNT0(x) ((x) << S_T6_PCMD_FREE_CNT0)
31162 #define G_T6_PCMD_FREE_CNT0(x) (((x) >> S_T6_PCMD_FREE_CNT0) & M_T6_PCMD_FREE_CNT0)
31163 
31164 #define S_T6_PCMD_FREE_CNT1    7
31165 #define M_T6_PCMD_FREE_CNT1    0x3ffU
31166 #define V_T6_PCMD_FREE_CNT1(x) ((x) << S_T6_PCMD_FREE_CNT1)
31167 #define G_T6_PCMD_FREE_CNT1(x) (((x) >> S_T6_PCMD_FREE_CNT1) & M_T6_PCMD_FREE_CNT1)
31168 
31169 #define S_M_RSPVLD    6
31170 #define V_M_RSPVLD(x) ((x) << S_M_RSPVLD)
31171 #define F_M_RSPVLD    V_M_RSPVLD(1U)
31172 
31173 #define S_M_RSPRDY    5
31174 #define V_M_RSPRDY(x) ((x) << S_M_RSPRDY)
31175 #define F_M_RSPRDY    V_M_RSPRDY(1U)
31176 
31177 #define S_M_REQADDRVLD    4
31178 #define V_M_REQADDRVLD(x) ((x) << S_M_REQADDRVLD)
31179 #define F_M_REQADDRVLD    V_M_REQADDRVLD(1U)
31180 
31181 #define A_PM_TX_DBG_STAT9 0x10035
31182 
31183 #define S_PCMD_FREE_CNT2    10
31184 #define M_PCMD_FREE_CNT2    0x3ffU
31185 #define V_PCMD_FREE_CNT2(x) ((x) << S_PCMD_FREE_CNT2)
31186 #define G_PCMD_FREE_CNT2(x) (((x) >> S_PCMD_FREE_CNT2) & M_PCMD_FREE_CNT2)
31187 
31188 #define S_PCMD_FREE_CNT3    0
31189 #define M_PCMD_FREE_CNT3    0x3ffU
31190 #define V_PCMD_FREE_CNT3(x) ((x) << S_PCMD_FREE_CNT3)
31191 #define G_PCMD_FREE_CNT3(x) (((x) >> S_PCMD_FREE_CNT3) & M_PCMD_FREE_CNT3)
31192 
31193 #define A_PM_TX_DBG_STAT10 0x10036
31194 
31195 #define S_IN_EOP_CNT3    28
31196 #define M_IN_EOP_CNT3    0xfU
31197 #define V_IN_EOP_CNT3(x) ((x) << S_IN_EOP_CNT3)
31198 #define G_IN_EOP_CNT3(x) (((x) >> S_IN_EOP_CNT3) & M_IN_EOP_CNT3)
31199 
31200 #define S_IN_EOP_CNT2    24
31201 #define M_IN_EOP_CNT2    0xfU
31202 #define V_IN_EOP_CNT2(x) ((x) << S_IN_EOP_CNT2)
31203 #define G_IN_EOP_CNT2(x) (((x) >> S_IN_EOP_CNT2) & M_IN_EOP_CNT2)
31204 
31205 #define S_IN_EOP_CNT1    20
31206 #define M_IN_EOP_CNT1    0xfU
31207 #define V_IN_EOP_CNT1(x) ((x) << S_IN_EOP_CNT1)
31208 #define G_IN_EOP_CNT1(x) (((x) >> S_IN_EOP_CNT1) & M_IN_EOP_CNT1)
31209 
31210 #define S_IN_EOP_CNT0    16
31211 #define M_IN_EOP_CNT0    0xfU
31212 #define V_IN_EOP_CNT0(x) ((x) << S_IN_EOP_CNT0)
31213 #define G_IN_EOP_CNT0(x) (((x) >> S_IN_EOP_CNT0) & M_IN_EOP_CNT0)
31214 
31215 #define S_IN_SOP_CNT3    12
31216 #define M_IN_SOP_CNT3    0xfU
31217 #define V_IN_SOP_CNT3(x) ((x) << S_IN_SOP_CNT3)
31218 #define G_IN_SOP_CNT3(x) (((x) >> S_IN_SOP_CNT3) & M_IN_SOP_CNT3)
31219 
31220 #define S_IN_SOP_CNT2    8
31221 #define M_IN_SOP_CNT2    0xfU
31222 #define V_IN_SOP_CNT2(x) ((x) << S_IN_SOP_CNT2)
31223 #define G_IN_SOP_CNT2(x) (((x) >> S_IN_SOP_CNT2) & M_IN_SOP_CNT2)
31224 
31225 #define S_IN_SOP_CNT1    4
31226 #define M_IN_SOP_CNT1    0xfU
31227 #define V_IN_SOP_CNT1(x) ((x) << S_IN_SOP_CNT1)
31228 #define G_IN_SOP_CNT1(x) (((x) >> S_IN_SOP_CNT1) & M_IN_SOP_CNT1)
31229 
31230 #define S_IN_SOP_CNT0    0
31231 #define M_IN_SOP_CNT0    0xfU
31232 #define V_IN_SOP_CNT0(x) ((x) << S_IN_SOP_CNT0)
31233 #define G_IN_SOP_CNT0(x) (((x) >> S_IN_SOP_CNT0) & M_IN_SOP_CNT0)
31234 
31235 #define A_PM_TX_DBG_STAT11 0x10037
31236 
31237 #define S_OUT_EOP_CNT3    28
31238 #define M_OUT_EOP_CNT3    0xfU
31239 #define V_OUT_EOP_CNT3(x) ((x) << S_OUT_EOP_CNT3)
31240 #define G_OUT_EOP_CNT3(x) (((x) >> S_OUT_EOP_CNT3) & M_OUT_EOP_CNT3)
31241 
31242 #define S_OUT_EOP_CNT2    24
31243 #define M_OUT_EOP_CNT2    0xfU
31244 #define V_OUT_EOP_CNT2(x) ((x) << S_OUT_EOP_CNT2)
31245 #define G_OUT_EOP_CNT2(x) (((x) >> S_OUT_EOP_CNT2) & M_OUT_EOP_CNT2)
31246 
31247 #define S_OUT_EOP_CNT1    20
31248 #define M_OUT_EOP_CNT1    0xfU
31249 #define V_OUT_EOP_CNT1(x) ((x) << S_OUT_EOP_CNT1)
31250 #define G_OUT_EOP_CNT1(x) (((x) >> S_OUT_EOP_CNT1) & M_OUT_EOP_CNT1)
31251 
31252 #define S_OUT_EOP_CNT0    16
31253 #define M_OUT_EOP_CNT0    0xfU
31254 #define V_OUT_EOP_CNT0(x) ((x) << S_OUT_EOP_CNT0)
31255 #define G_OUT_EOP_CNT0(x) (((x) >> S_OUT_EOP_CNT0) & M_OUT_EOP_CNT0)
31256 
31257 #define S_OUT_SOP_CNT3    12
31258 #define M_OUT_SOP_CNT3    0xfU
31259 #define V_OUT_SOP_CNT3(x) ((x) << S_OUT_SOP_CNT3)
31260 #define G_OUT_SOP_CNT3(x) (((x) >> S_OUT_SOP_CNT3) & M_OUT_SOP_CNT3)
31261 
31262 #define S_OUT_SOP_CNT2    8
31263 #define M_OUT_SOP_CNT2    0xfU
31264 #define V_OUT_SOP_CNT2(x) ((x) << S_OUT_SOP_CNT2)
31265 #define G_OUT_SOP_CNT2(x) (((x) >> S_OUT_SOP_CNT2) & M_OUT_SOP_CNT2)
31266 
31267 #define S_OUT_SOP_CNT1    4
31268 #define M_OUT_SOP_CNT1    0xfU
31269 #define V_OUT_SOP_CNT1(x) ((x) << S_OUT_SOP_CNT1)
31270 #define G_OUT_SOP_CNT1(x) (((x) >> S_OUT_SOP_CNT1) & M_OUT_SOP_CNT1)
31271 
31272 #define S_OUT_SOP_CNT0    0
31273 #define M_OUT_SOP_CNT0    0xfU
31274 #define V_OUT_SOP_CNT0(x) ((x) << S_OUT_SOP_CNT0)
31275 #define G_OUT_SOP_CNT0(x) (((x) >> S_OUT_SOP_CNT0) & M_OUT_SOP_CNT0)
31276 
31277 #define A_PM_TX_DBG_STAT12 0x10038
31278 #define A_PM_TX_DBG_STAT13 0x10039
31279 
31280 #define S_CH_DEFICIT_BLOWED    31
31281 #define V_CH_DEFICIT_BLOWED(x) ((x) << S_CH_DEFICIT_BLOWED)
31282 #define F_CH_DEFICIT_BLOWED    V_CH_DEFICIT_BLOWED(1U)
31283 
31284 #define S_CH1_DEFICIT    16
31285 #define M_CH1_DEFICIT    0xfffU
31286 #define V_CH1_DEFICIT(x) ((x) << S_CH1_DEFICIT)
31287 #define G_CH1_DEFICIT(x) (((x) >> S_CH1_DEFICIT) & M_CH1_DEFICIT)
31288 
31289 #define S_CH0_DEFICIT    0
31290 #define M_CH0_DEFICIT    0xfffU
31291 #define V_CH0_DEFICIT(x) ((x) << S_CH0_DEFICIT)
31292 #define G_CH0_DEFICIT(x) (((x) >> S_CH0_DEFICIT) & M_CH0_DEFICIT)
31293 
31294 #define A_PM_TX_DBG_STAT14 0x1003a
31295 
31296 #define S_CH3_DEFICIT    16
31297 #define M_CH3_DEFICIT    0xfffU
31298 #define V_CH3_DEFICIT(x) ((x) << S_CH3_DEFICIT)
31299 #define G_CH3_DEFICIT(x) (((x) >> S_CH3_DEFICIT) & M_CH3_DEFICIT)
31300 
31301 #define S_CH2_DEFICIT    0
31302 #define M_CH2_DEFICIT    0xfffU
31303 #define V_CH2_DEFICIT(x) ((x) << S_CH2_DEFICIT)
31304 #define G_CH2_DEFICIT(x) (((x) >> S_CH2_DEFICIT) & M_CH2_DEFICIT)
31305 
31306 #define A_PM_TX_DBG_STAT15 0x1003b
31307 
31308 #define S_BUNDLE_LEN_SRDY    28
31309 #define M_BUNDLE_LEN_SRDY    0xfU
31310 #define V_BUNDLE_LEN_SRDY(x) ((x) << S_BUNDLE_LEN_SRDY)
31311 #define G_BUNDLE_LEN_SRDY(x) (((x) >> S_BUNDLE_LEN_SRDY) & M_BUNDLE_LEN_SRDY)
31312 
31313 #define S_BUNDLE_LEN1    16
31314 #define M_BUNDLE_LEN1    0xfffU
31315 #define V_BUNDLE_LEN1(x) ((x) << S_BUNDLE_LEN1)
31316 #define G_BUNDLE_LEN1(x) (((x) >> S_BUNDLE_LEN1) & M_BUNDLE_LEN1)
31317 
31318 #define S_BUNDLE_LEN0    0
31319 #define M_BUNDLE_LEN0    0xfffU
31320 #define V_BUNDLE_LEN0(x) ((x) << S_BUNDLE_LEN0)
31321 #define G_BUNDLE_LEN0(x) (((x) >> S_BUNDLE_LEN0) & M_BUNDLE_LEN0)
31322 
31323 #define S_T6_BUNDLE_LEN_SRDY    24
31324 #define M_T6_BUNDLE_LEN_SRDY    0x3U
31325 #define V_T6_BUNDLE_LEN_SRDY(x) ((x) << S_T6_BUNDLE_LEN_SRDY)
31326 #define G_T6_BUNDLE_LEN_SRDY(x) (((x) >> S_T6_BUNDLE_LEN_SRDY) & M_T6_BUNDLE_LEN_SRDY)
31327 
31328 #define S_T6_BUNDLE_LEN1    12
31329 #define M_T6_BUNDLE_LEN1    0xfffU
31330 #define V_T6_BUNDLE_LEN1(x) ((x) << S_T6_BUNDLE_LEN1)
31331 #define G_T6_BUNDLE_LEN1(x) (((x) >> S_T6_BUNDLE_LEN1) & M_T6_BUNDLE_LEN1)
31332 
31333 #define A_PM_TX_DBG_STAT16 0x1003c
31334 
31335 #define S_BUNDLE_LEN3    16
31336 #define M_BUNDLE_LEN3    0xfffU
31337 #define V_BUNDLE_LEN3(x) ((x) << S_BUNDLE_LEN3)
31338 #define G_BUNDLE_LEN3(x) (((x) >> S_BUNDLE_LEN3) & M_BUNDLE_LEN3)
31339 
31340 #define S_BUNDLE_LEN2    0
31341 #define M_BUNDLE_LEN2    0xfffU
31342 #define V_BUNDLE_LEN2(x) ((x) << S_BUNDLE_LEN2)
31343 #define G_BUNDLE_LEN2(x) (((x) >> S_BUNDLE_LEN2) & M_BUNDLE_LEN2)
31344 
31345 /* registers for module MPS */
31346 #define MPS_BASE_ADDR 0x9000
31347 
31348 #define A_MPS_PORT_CTL 0x0
31349 
31350 #define S_LPBKEN    31
31351 #define V_LPBKEN(x) ((x) << S_LPBKEN)
31352 #define F_LPBKEN    V_LPBKEN(1U)
31353 
31354 #define S_PORTTXEN    30
31355 #define V_PORTTXEN(x) ((x) << S_PORTTXEN)
31356 #define F_PORTTXEN    V_PORTTXEN(1U)
31357 
31358 #define S_PORTRXEN    29
31359 #define V_PORTRXEN(x) ((x) << S_PORTRXEN)
31360 #define F_PORTRXEN    V_PORTRXEN(1U)
31361 
31362 #define S_PPPEN    28
31363 #define V_PPPEN(x) ((x) << S_PPPEN)
31364 #define F_PPPEN    V_PPPEN(1U)
31365 
31366 #define S_FCSSTRIPEN    27
31367 #define V_FCSSTRIPEN(x) ((x) << S_FCSSTRIPEN)
31368 #define F_FCSSTRIPEN    V_FCSSTRIPEN(1U)
31369 
31370 #define S_PPPANDPAUSE    26
31371 #define V_PPPANDPAUSE(x) ((x) << S_PPPANDPAUSE)
31372 #define F_PPPANDPAUSE    V_PPPANDPAUSE(1U)
31373 
31374 #define S_PRIOPPPENMAP    16
31375 #define M_PRIOPPPENMAP    0xffU
31376 #define V_PRIOPPPENMAP(x) ((x) << S_PRIOPPPENMAP)
31377 #define G_PRIOPPPENMAP(x) (((x) >> S_PRIOPPPENMAP) & M_PRIOPPPENMAP)
31378 
31379 #define A_MPS_VF_CTL 0x0
31380 #define A_MPS_PORT_PAUSE_CTL 0x4
31381 
31382 #define S_TIMEUNIT    0
31383 #define M_TIMEUNIT    0xffffU
31384 #define V_TIMEUNIT(x) ((x) << S_TIMEUNIT)
31385 #define G_TIMEUNIT(x) (((x) >> S_TIMEUNIT) & M_TIMEUNIT)
31386 
31387 #define A_MPS_PORT_TX_PAUSE_CTL 0x8
31388 
31389 #define S_REGSENDOFF    24
31390 #define M_REGSENDOFF    0xffU
31391 #define V_REGSENDOFF(x) ((x) << S_REGSENDOFF)
31392 #define G_REGSENDOFF(x) (((x) >> S_REGSENDOFF) & M_REGSENDOFF)
31393 
31394 #define S_REGSENDON    16
31395 #define M_REGSENDON    0xffU
31396 #define V_REGSENDON(x) ((x) << S_REGSENDON)
31397 #define G_REGSENDON(x) (((x) >> S_REGSENDON) & M_REGSENDON)
31398 
31399 #define S_SGESENDEN    8
31400 #define M_SGESENDEN    0xffU
31401 #define V_SGESENDEN(x) ((x) << S_SGESENDEN)
31402 #define G_SGESENDEN(x) (((x) >> S_SGESENDEN) & M_SGESENDEN)
31403 
31404 #define S_RXSENDEN    0
31405 #define M_RXSENDEN    0xffU
31406 #define V_RXSENDEN(x) ((x) << S_RXSENDEN)
31407 #define G_RXSENDEN(x) (((x) >> S_RXSENDEN) & M_RXSENDEN)
31408 
31409 #define A_MPS_PORT_TX_PAUSE_CTL2 0xc
31410 
31411 #define S_XOFFDISABLE    0
31412 #define V_XOFFDISABLE(x) ((x) << S_XOFFDISABLE)
31413 #define F_XOFFDISABLE    V_XOFFDISABLE(1U)
31414 
31415 #define A_MPS_PORT_RX_PAUSE_CTL 0x10
31416 
31417 #define S_REGHALTON    8
31418 #define M_REGHALTON    0xffU
31419 #define V_REGHALTON(x) ((x) << S_REGHALTON)
31420 #define G_REGHALTON(x) (((x) >> S_REGHALTON) & M_REGHALTON)
31421 
31422 #define S_RXHALTEN    0
31423 #define M_RXHALTEN    0xffU
31424 #define V_RXHALTEN(x) ((x) << S_RXHALTEN)
31425 #define G_RXHALTEN(x) (((x) >> S_RXHALTEN) & M_RXHALTEN)
31426 
31427 #define A_MPS_PORT_TX_PAUSE_STATUS 0x14
31428 
31429 #define S_REGSENDING    16
31430 #define M_REGSENDING    0xffU
31431 #define V_REGSENDING(x) ((x) << S_REGSENDING)
31432 #define G_REGSENDING(x) (((x) >> S_REGSENDING) & M_REGSENDING)
31433 
31434 #define S_SGESENDING    8
31435 #define M_SGESENDING    0xffU
31436 #define V_SGESENDING(x) ((x) << S_SGESENDING)
31437 #define G_SGESENDING(x) (((x) >> S_SGESENDING) & M_SGESENDING)
31438 
31439 #define S_RXSENDING    0
31440 #define M_RXSENDING    0xffU
31441 #define V_RXSENDING(x) ((x) << S_RXSENDING)
31442 #define G_RXSENDING(x) (((x) >> S_RXSENDING) & M_RXSENDING)
31443 
31444 #define A_MPS_PORT_RX_PAUSE_STATUS 0x18
31445 
31446 #define S_REGHALTED    8
31447 #define M_REGHALTED    0xffU
31448 #define V_REGHALTED(x) ((x) << S_REGHALTED)
31449 #define G_REGHALTED(x) (((x) >> S_REGHALTED) & M_REGHALTED)
31450 
31451 #define S_RXHALTED    0
31452 #define M_RXHALTED    0xffU
31453 #define V_RXHALTED(x) ((x) << S_RXHALTED)
31454 #define G_RXHALTED(x) (((x) >> S_RXHALTED) & M_RXHALTED)
31455 
31456 #define A_MPS_PORT_TX_PAUSE_DEST_L 0x1c
31457 #define A_MPS_PORT_TX_PAUSE_DEST_H 0x20
31458 
31459 #define S_ADDR    0
31460 #define M_ADDR    0xffffU
31461 #define V_ADDR(x) ((x) << S_ADDR)
31462 #define G_ADDR(x) (((x) >> S_ADDR) & M_ADDR)
31463 
31464 #define A_MPS_PORT_TX_PAUSE_SOURCE_L 0x24
31465 #define A_MPS_PORT_TX_PAUSE_SOURCE_H 0x28
31466 #define A_MPS_PORT_PRTY_BUFFER_GROUP_MAP 0x2c
31467 
31468 #define S_PRTY7    14
31469 #define M_PRTY7    0x3U
31470 #define V_PRTY7(x) ((x) << S_PRTY7)
31471 #define G_PRTY7(x) (((x) >> S_PRTY7) & M_PRTY7)
31472 
31473 #define S_PRTY6    12
31474 #define M_PRTY6    0x3U
31475 #define V_PRTY6(x) ((x) << S_PRTY6)
31476 #define G_PRTY6(x) (((x) >> S_PRTY6) & M_PRTY6)
31477 
31478 #define S_PRTY5    10
31479 #define M_PRTY5    0x3U
31480 #define V_PRTY5(x) ((x) << S_PRTY5)
31481 #define G_PRTY5(x) (((x) >> S_PRTY5) & M_PRTY5)
31482 
31483 #define S_PRTY4    8
31484 #define M_PRTY4    0x3U
31485 #define V_PRTY4(x) ((x) << S_PRTY4)
31486 #define G_PRTY4(x) (((x) >> S_PRTY4) & M_PRTY4)
31487 
31488 #define S_PRTY3    6
31489 #define M_PRTY3    0x3U
31490 #define V_PRTY3(x) ((x) << S_PRTY3)
31491 #define G_PRTY3(x) (((x) >> S_PRTY3) & M_PRTY3)
31492 
31493 #define S_PRTY2    4
31494 #define M_PRTY2    0x3U
31495 #define V_PRTY2(x) ((x) << S_PRTY2)
31496 #define G_PRTY2(x) (((x) >> S_PRTY2) & M_PRTY2)
31497 
31498 #define S_PRTY1    2
31499 #define M_PRTY1    0x3U
31500 #define V_PRTY1(x) ((x) << S_PRTY1)
31501 #define G_PRTY1(x) (((x) >> S_PRTY1) & M_PRTY1)
31502 
31503 #define S_PRTY0    0
31504 #define M_PRTY0    0x3U
31505 #define V_PRTY0(x) ((x) << S_PRTY0)
31506 #define G_PRTY0(x) (((x) >> S_PRTY0) & M_PRTY0)
31507 
31508 #define A_MPS_PORT_PRTY_BUFFER_GROUP_TH_MAP 0x30
31509 
31510 #define S_TXPRTY7    28
31511 #define M_TXPRTY7    0xfU
31512 #define V_TXPRTY7(x) ((x) << S_TXPRTY7)
31513 #define G_TXPRTY7(x) (((x) >> S_TXPRTY7) & M_TXPRTY7)
31514 
31515 #define S_TXPRTY6    24
31516 #define M_TXPRTY6    0xfU
31517 #define V_TXPRTY6(x) ((x) << S_TXPRTY6)
31518 #define G_TXPRTY6(x) (((x) >> S_TXPRTY6) & M_TXPRTY6)
31519 
31520 #define S_TXPRTY5    20
31521 #define M_TXPRTY5    0xfU
31522 #define V_TXPRTY5(x) ((x) << S_TXPRTY5)
31523 #define G_TXPRTY5(x) (((x) >> S_TXPRTY5) & M_TXPRTY5)
31524 
31525 #define S_TXPRTY4    16
31526 #define M_TXPRTY4    0xfU
31527 #define V_TXPRTY4(x) ((x) << S_TXPRTY4)
31528 #define G_TXPRTY4(x) (((x) >> S_TXPRTY4) & M_TXPRTY4)
31529 
31530 #define S_TXPRTY3    12
31531 #define M_TXPRTY3    0xfU
31532 #define V_TXPRTY3(x) ((x) << S_TXPRTY3)
31533 #define G_TXPRTY3(x) (((x) >> S_TXPRTY3) & M_TXPRTY3)
31534 
31535 #define S_TXPRTY2    8
31536 #define M_TXPRTY2    0xfU
31537 #define V_TXPRTY2(x) ((x) << S_TXPRTY2)
31538 #define G_TXPRTY2(x) (((x) >> S_TXPRTY2) & M_TXPRTY2)
31539 
31540 #define S_TXPRTY1    4
31541 #define M_TXPRTY1    0xfU
31542 #define V_TXPRTY1(x) ((x) << S_TXPRTY1)
31543 #define G_TXPRTY1(x) (((x) >> S_TXPRTY1) & M_TXPRTY1)
31544 
31545 #define S_TXPRTY0    0
31546 #define M_TXPRTY0    0xfU
31547 #define V_TXPRTY0(x) ((x) << S_TXPRTY0)
31548 #define G_TXPRTY0(x) (((x) >> S_TXPRTY0) & M_TXPRTY0)
31549 
31550 #define A_MPS_VF_STAT_TX_VF_BCAST_BYTES_L 0x80
31551 #define A_MPS_VF_STAT_TX_VF_BCAST_BYTES_H 0x84
31552 #define A_MPS_VF_STAT_TX_VF_BCAST_FRAMES_L 0x88
31553 #define A_MPS_VF_STAT_TX_VF_BCAST_FRAMES_H 0x8c
31554 #define A_MPS_VF_STAT_TX_VF_MCAST_BYTES_L 0x90
31555 #define A_MPS_VF_STAT_TX_VF_MCAST_BYTES_H 0x94
31556 #define A_MPS_VF_STAT_TX_VF_MCAST_FRAMES_L 0x98
31557 #define A_MPS_VF_STAT_TX_VF_MCAST_FRAMES_H 0x9c
31558 #define A_MPS_VF_STAT_TX_VF_UCAST_BYTES_L 0xa0
31559 #define A_MPS_VF_STAT_TX_VF_UCAST_BYTES_H 0xa4
31560 #define A_MPS_VF_STAT_TX_VF_UCAST_FRAMES_L 0xa8
31561 #define A_MPS_VF_STAT_TX_VF_UCAST_FRAMES_H 0xac
31562 #define A_MPS_VF_STAT_TX_VF_DROP_FRAMES_L 0xb0
31563 #define A_MPS_VF_STAT_TX_VF_DROP_FRAMES_H 0xb4
31564 #define A_MPS_VF_STAT_TX_VF_OFFLOAD_BYTES_L 0xb8
31565 #define A_MPS_VF_STAT_TX_VF_OFFLOAD_BYTES_H 0xbc
31566 #define A_MPS_VF_STAT_TX_VF_OFFLOAD_FRAMES_L 0xc0
31567 #define A_MPS_VF_STAT_TX_VF_OFFLOAD_FRAMES_H 0xc4
31568 #define A_MPS_VF_STAT_RX_VF_BCAST_BYTES_L 0xc8
31569 #define A_MPS_VF_STAT_RX_VF_BCAST_BYTES_H 0xcc
31570 #define A_MPS_VF_STAT_RX_VF_BCAST_FRAMES_L 0xd0
31571 #define A_MPS_VF_STAT_RX_VF_BCAST_FRAMES_H 0xd4
31572 #define A_MPS_VF_STAT_RX_VF_MCAST_BYTES_L 0xd8
31573 #define A_MPS_VF_STAT_RX_VF_MCAST_BYTES_H 0xdc
31574 #define A_MPS_VF_STAT_RX_VF_MCAST_FRAMES_L 0xe0
31575 #define A_MPS_VF_STAT_RX_VF_MCAST_FRAMES_H 0xe4
31576 #define A_MPS_VF_STAT_RX_VF_UCAST_BYTES_L 0xe8
31577 #define A_MPS_VF_STAT_RX_VF_UCAST_BYTES_H 0xec
31578 #define A_MPS_VF_STAT_RX_VF_UCAST_FRAMES_L 0xf0
31579 #define A_MPS_VF_STAT_RX_VF_UCAST_FRAMES_H 0xf4
31580 #define A_MPS_VF_STAT_RX_VF_ERR_FRAMES_L 0xf8
31581 #define A_MPS_VF_STAT_RX_VF_ERR_FRAMES_H 0xfc
31582 #define A_MPS_PORT_RX_CTL 0x100
31583 
31584 #define S_NO_RPLCT_M    20
31585 #define V_NO_RPLCT_M(x) ((x) << S_NO_RPLCT_M)
31586 #define F_NO_RPLCT_M    V_NO_RPLCT_M(1U)
31587 
31588 #define S_RPLCT_SEL_L    18
31589 #define M_RPLCT_SEL_L    0x3U
31590 #define V_RPLCT_SEL_L(x) ((x) << S_RPLCT_SEL_L)
31591 #define G_RPLCT_SEL_L(x) (((x) >> S_RPLCT_SEL_L) & M_RPLCT_SEL_L)
31592 
31593 #define S_FLTR_VLAN_SEL    17
31594 #define V_FLTR_VLAN_SEL(x) ((x) << S_FLTR_VLAN_SEL)
31595 #define F_FLTR_VLAN_SEL    V_FLTR_VLAN_SEL(1U)
31596 
31597 #define S_PRIO_VLAN_SEL    16
31598 #define V_PRIO_VLAN_SEL(x) ((x) << S_PRIO_VLAN_SEL)
31599 #define F_PRIO_VLAN_SEL    V_PRIO_VLAN_SEL(1U)
31600 
31601 #define S_CHK_8023_LEN_M    15
31602 #define V_CHK_8023_LEN_M(x) ((x) << S_CHK_8023_LEN_M)
31603 #define F_CHK_8023_LEN_M    V_CHK_8023_LEN_M(1U)
31604 
31605 #define S_CHK_8023_LEN_L    14
31606 #define V_CHK_8023_LEN_L(x) ((x) << S_CHK_8023_LEN_L)
31607 #define F_CHK_8023_LEN_L    V_CHK_8023_LEN_L(1U)
31608 
31609 #define S_NIV_DROP    13
31610 #define V_NIV_DROP(x) ((x) << S_NIV_DROP)
31611 #define F_NIV_DROP    V_NIV_DROP(1U)
31612 
31613 #define S_NOV_DROP    12
31614 #define V_NOV_DROP(x) ((x) << S_NOV_DROP)
31615 #define F_NOV_DROP    V_NOV_DROP(1U)
31616 
31617 #define S_CLS_PRT    11
31618 #define V_CLS_PRT(x) ((x) << S_CLS_PRT)
31619 #define F_CLS_PRT    V_CLS_PRT(1U)
31620 
31621 #define S_RX_QFC_EN    10
31622 #define V_RX_QFC_EN(x) ((x) << S_RX_QFC_EN)
31623 #define F_RX_QFC_EN    V_RX_QFC_EN(1U)
31624 
31625 #define S_QFC_FWD_UP    9
31626 #define V_QFC_FWD_UP(x) ((x) << S_QFC_FWD_UP)
31627 #define F_QFC_FWD_UP    V_QFC_FWD_UP(1U)
31628 
31629 #define S_PPP_FWD_UP    8
31630 #define V_PPP_FWD_UP(x) ((x) << S_PPP_FWD_UP)
31631 #define F_PPP_FWD_UP    V_PPP_FWD_UP(1U)
31632 
31633 #define S_PAUSE_FWD_UP    7
31634 #define V_PAUSE_FWD_UP(x) ((x) << S_PAUSE_FWD_UP)
31635 #define F_PAUSE_FWD_UP    V_PAUSE_FWD_UP(1U)
31636 
31637 #define S_LPBK_BP    6
31638 #define V_LPBK_BP(x) ((x) << S_LPBK_BP)
31639 #define F_LPBK_BP    V_LPBK_BP(1U)
31640 
31641 #define S_PASS_NO_MATCH    5
31642 #define V_PASS_NO_MATCH(x) ((x) << S_PASS_NO_MATCH)
31643 #define F_PASS_NO_MATCH    V_PASS_NO_MATCH(1U)
31644 
31645 #define S_IVLAN_EN    4
31646 #define V_IVLAN_EN(x) ((x) << S_IVLAN_EN)
31647 #define F_IVLAN_EN    V_IVLAN_EN(1U)
31648 
31649 #define S_OVLAN_EN3    3
31650 #define V_OVLAN_EN3(x) ((x) << S_OVLAN_EN3)
31651 #define F_OVLAN_EN3    V_OVLAN_EN3(1U)
31652 
31653 #define S_OVLAN_EN2    2
31654 #define V_OVLAN_EN2(x) ((x) << S_OVLAN_EN2)
31655 #define F_OVLAN_EN2    V_OVLAN_EN2(1U)
31656 
31657 #define S_OVLAN_EN1    1
31658 #define V_OVLAN_EN1(x) ((x) << S_OVLAN_EN1)
31659 #define F_OVLAN_EN1    V_OVLAN_EN1(1U)
31660 
31661 #define S_OVLAN_EN0    0
31662 #define V_OVLAN_EN0(x) ((x) << S_OVLAN_EN0)
31663 #define F_OVLAN_EN0    V_OVLAN_EN0(1U)
31664 
31665 #define S_PTP_FWD_UP    21
31666 #define V_PTP_FWD_UP(x) ((x) << S_PTP_FWD_UP)
31667 #define F_PTP_FWD_UP    V_PTP_FWD_UP(1U)
31668 
31669 #define S_HASH_PRIO_SEL_LPBK    25
31670 #define V_HASH_PRIO_SEL_LPBK(x) ((x) << S_HASH_PRIO_SEL_LPBK)
31671 #define F_HASH_PRIO_SEL_LPBK    V_HASH_PRIO_SEL_LPBK(1U)
31672 
31673 #define S_HASH_PRIO_SEL_MAC    24
31674 #define V_HASH_PRIO_SEL_MAC(x) ((x) << S_HASH_PRIO_SEL_MAC)
31675 #define F_HASH_PRIO_SEL_MAC    V_HASH_PRIO_SEL_MAC(1U)
31676 
31677 #define S_HASH_EN_LPBK    23
31678 #define V_HASH_EN_LPBK(x) ((x) << S_HASH_EN_LPBK)
31679 #define F_HASH_EN_LPBK    V_HASH_EN_LPBK(1U)
31680 
31681 #define S_HASH_EN_MAC    22
31682 #define V_HASH_EN_MAC(x) ((x) << S_HASH_EN_MAC)
31683 #define F_HASH_EN_MAC    V_HASH_EN_MAC(1U)
31684 
31685 #define A_MPS_PORT_RX_MTU 0x104
31686 #define A_MPS_PORT_RX_PF_MAP 0x108
31687 #define A_MPS_PORT_RX_VF_MAP0 0x10c
31688 #define A_MPS_PORT_RX_VF_MAP1 0x110
31689 #define A_MPS_PORT_RX_VF_MAP2 0x114
31690 #define A_MPS_PORT_RX_VF_MAP3 0x118
31691 #define A_MPS_PORT_RX_IVLAN 0x11c
31692 
31693 #define S_IVLAN_ETYPE    0
31694 #define M_IVLAN_ETYPE    0xffffU
31695 #define V_IVLAN_ETYPE(x) ((x) << S_IVLAN_ETYPE)
31696 #define G_IVLAN_ETYPE(x) (((x) >> S_IVLAN_ETYPE) & M_IVLAN_ETYPE)
31697 
31698 #define A_MPS_PORT_RX_OVLAN0 0x120
31699 
31700 #define S_OVLAN_MASK    16
31701 #define M_OVLAN_MASK    0xffffU
31702 #define V_OVLAN_MASK(x) ((x) << S_OVLAN_MASK)
31703 #define G_OVLAN_MASK(x) (((x) >> S_OVLAN_MASK) & M_OVLAN_MASK)
31704 
31705 #define S_OVLAN_ETYPE    0
31706 #define M_OVLAN_ETYPE    0xffffU
31707 #define V_OVLAN_ETYPE(x) ((x) << S_OVLAN_ETYPE)
31708 #define G_OVLAN_ETYPE(x) (((x) >> S_OVLAN_ETYPE) & M_OVLAN_ETYPE)
31709 
31710 #define A_MPS_PORT_RX_OVLAN1 0x124
31711 #define A_MPS_PORT_RX_OVLAN2 0x128
31712 #define A_MPS_PORT_RX_OVLAN3 0x12c
31713 #define A_MPS_PORT_RX_RSS_HASH 0x130
31714 #define A_MPS_PORT_RX_RSS_CONTROL 0x134
31715 
31716 #define S_RSS_CTRL    16
31717 #define M_RSS_CTRL    0xffU
31718 #define V_RSS_CTRL(x) ((x) << S_RSS_CTRL)
31719 #define G_RSS_CTRL(x) (((x) >> S_RSS_CTRL) & M_RSS_CTRL)
31720 
31721 #define S_QUE_NUM    0
31722 #define M_QUE_NUM    0xffffU
31723 #define V_QUE_NUM(x) ((x) << S_QUE_NUM)
31724 #define G_QUE_NUM(x) (((x) >> S_QUE_NUM) & M_QUE_NUM)
31725 
31726 #define A_MPS_PORT_RX_CTL1 0x138
31727 
31728 #define S_FIXED_PFVF_MAC    13
31729 #define V_FIXED_PFVF_MAC(x) ((x) << S_FIXED_PFVF_MAC)
31730 #define F_FIXED_PFVF_MAC    V_FIXED_PFVF_MAC(1U)
31731 
31732 #define S_FIXED_PFVF_LPBK    12
31733 #define V_FIXED_PFVF_LPBK(x) ((x) << S_FIXED_PFVF_LPBK)
31734 #define F_FIXED_PFVF_LPBK    V_FIXED_PFVF_LPBK(1U)
31735 
31736 #define S_FIXED_PFVF_LPBK_OV    11
31737 #define V_FIXED_PFVF_LPBK_OV(x) ((x) << S_FIXED_PFVF_LPBK_OV)
31738 #define F_FIXED_PFVF_LPBK_OV    V_FIXED_PFVF_LPBK_OV(1U)
31739 
31740 #define S_FIXED_PF    8
31741 #define M_FIXED_PF    0x7U
31742 #define V_FIXED_PF(x) ((x) << S_FIXED_PF)
31743 #define G_FIXED_PF(x) (((x) >> S_FIXED_PF) & M_FIXED_PF)
31744 
31745 #define S_FIXED_VF_VLD    7
31746 #define V_FIXED_VF_VLD(x) ((x) << S_FIXED_VF_VLD)
31747 #define F_FIXED_VF_VLD    V_FIXED_VF_VLD(1U)
31748 
31749 #define S_FIXED_VF    0
31750 #define M_FIXED_VF    0x7fU
31751 #define V_FIXED_VF(x) ((x) << S_FIXED_VF)
31752 #define G_FIXED_VF(x) (((x) >> S_FIXED_VF) & M_FIXED_VF)
31753 
31754 #define S_T6_FIXED_PFVF_MAC    14
31755 #define V_T6_FIXED_PFVF_MAC(x) ((x) << S_T6_FIXED_PFVF_MAC)
31756 #define F_T6_FIXED_PFVF_MAC    V_T6_FIXED_PFVF_MAC(1U)
31757 
31758 #define S_T6_FIXED_PFVF_LPBK    13
31759 #define V_T6_FIXED_PFVF_LPBK(x) ((x) << S_T6_FIXED_PFVF_LPBK)
31760 #define F_T6_FIXED_PFVF_LPBK    V_T6_FIXED_PFVF_LPBK(1U)
31761 
31762 #define S_T6_FIXED_PFVF_LPBK_OV    12
31763 #define V_T6_FIXED_PFVF_LPBK_OV(x) ((x) << S_T6_FIXED_PFVF_LPBK_OV)
31764 #define F_T6_FIXED_PFVF_LPBK_OV    V_T6_FIXED_PFVF_LPBK_OV(1U)
31765 
31766 #define S_T6_FIXED_PF    9
31767 #define M_T6_FIXED_PF    0x7U
31768 #define V_T6_FIXED_PF(x) ((x) << S_T6_FIXED_PF)
31769 #define G_T6_FIXED_PF(x) (((x) >> S_T6_FIXED_PF) & M_T6_FIXED_PF)
31770 
31771 #define S_T6_FIXED_VF_VLD    8
31772 #define V_T6_FIXED_VF_VLD(x) ((x) << S_T6_FIXED_VF_VLD)
31773 #define F_T6_FIXED_VF_VLD    V_T6_FIXED_VF_VLD(1U)
31774 
31775 #define S_T6_FIXED_VF    0
31776 #define M_T6_FIXED_VF    0xffU
31777 #define V_T6_FIXED_VF(x) ((x) << S_T6_FIXED_VF)
31778 #define G_T6_FIXED_VF(x) (((x) >> S_T6_FIXED_VF) & M_T6_FIXED_VF)
31779 
31780 #define A_MPS_PORT_RX_SPARE 0x13c
31781 #define A_MPS_PORT_RX_PTP_RSS_HASH 0x140
31782 #define A_MPS_PORT_RX_PTP_RSS_CONTROL 0x144
31783 #define A_MPS_PORT_RX_TS_VLD 0x148
31784 
31785 #define S_TS_VLD    0
31786 #define M_TS_VLD    0x3U
31787 #define V_TS_VLD(x) ((x) << S_TS_VLD)
31788 #define G_TS_VLD(x) (((x) >> S_TS_VLD) & M_TS_VLD)
31789 
31790 #define A_MPS_PORT_RX_TNL_LKP_INNER_SEL 0x14c
31791 
31792 #define S_LKP_SEL    0
31793 #define V_LKP_SEL(x) ((x) << S_LKP_SEL)
31794 #define F_LKP_SEL    V_LKP_SEL(1U)
31795 
31796 #define A_MPS_PORT_RX_VF_MAP4 0x150
31797 #define A_MPS_PORT_RX_VF_MAP5 0x154
31798 #define A_MPS_PORT_RX_VF_MAP6 0x158
31799 #define A_MPS_PORT_RX_VF_MAP7 0x15c
31800 #define A_MPS_PORT_RX_PRS_DEBUG_FLAG_MAC 0x160
31801 
31802 #define S_OUTER_IPV4_N_INNER_IPV4    31
31803 #define V_OUTER_IPV4_N_INNER_IPV4(x) ((x) << S_OUTER_IPV4_N_INNER_IPV4)
31804 #define F_OUTER_IPV4_N_INNER_IPV4    V_OUTER_IPV4_N_INNER_IPV4(1U)
31805 
31806 #define S_OUTER_IPV4_N_INNER_IPV6    30
31807 #define V_OUTER_IPV4_N_INNER_IPV6(x) ((x) << S_OUTER_IPV4_N_INNER_IPV6)
31808 #define F_OUTER_IPV4_N_INNER_IPV6    V_OUTER_IPV4_N_INNER_IPV6(1U)
31809 
31810 #define S_OUTER_IPV6_N_INNER_IPV4    29
31811 #define V_OUTER_IPV6_N_INNER_IPV4(x) ((x) << S_OUTER_IPV6_N_INNER_IPV4)
31812 #define F_OUTER_IPV6_N_INNER_IPV4    V_OUTER_IPV6_N_INNER_IPV4(1U)
31813 
31814 #define S_OUTER_IPV6_N_INNER_IPV6    28
31815 #define V_OUTER_IPV6_N_INNER_IPV6(x) ((x) << S_OUTER_IPV6_N_INNER_IPV6)
31816 #define F_OUTER_IPV6_N_INNER_IPV6    V_OUTER_IPV6_N_INNER_IPV6(1U)
31817 
31818 #define S_OUTER_IPV4_N_VLAN_NVGRE    27
31819 #define V_OUTER_IPV4_N_VLAN_NVGRE(x) ((x) << S_OUTER_IPV4_N_VLAN_NVGRE)
31820 #define F_OUTER_IPV4_N_VLAN_NVGRE    V_OUTER_IPV4_N_VLAN_NVGRE(1U)
31821 
31822 #define S_OUTER_IPV6_N_VLAN_NVGRE    26
31823 #define V_OUTER_IPV6_N_VLAN_NVGRE(x) ((x) << S_OUTER_IPV6_N_VLAN_NVGRE)
31824 #define F_OUTER_IPV6_N_VLAN_NVGRE    V_OUTER_IPV6_N_VLAN_NVGRE(1U)
31825 
31826 #define S_OUTER_IPV4_N_DOUBLE_VLAN_NVGRE    25
31827 #define V_OUTER_IPV4_N_DOUBLE_VLAN_NVGRE(x) ((x) << S_OUTER_IPV4_N_DOUBLE_VLAN_NVGRE)
31828 #define F_OUTER_IPV4_N_DOUBLE_VLAN_NVGRE    V_OUTER_IPV4_N_DOUBLE_VLAN_NVGRE(1U)
31829 
31830 #define S_OUTER_IPV6_N_DOUBLE_VLAN_NVGRE    24
31831 #define V_OUTER_IPV6_N_DOUBLE_VLAN_NVGRE(x) ((x) << S_OUTER_IPV6_N_DOUBLE_VLAN_NVGRE)
31832 #define F_OUTER_IPV6_N_DOUBLE_VLAN_NVGRE    V_OUTER_IPV6_N_DOUBLE_VLAN_NVGRE(1U)
31833 
31834 #define S_OUTER_IPV4_N_VLAN_GRE    23
31835 #define V_OUTER_IPV4_N_VLAN_GRE(x) ((x) << S_OUTER_IPV4_N_VLAN_GRE)
31836 #define F_OUTER_IPV4_N_VLAN_GRE    V_OUTER_IPV4_N_VLAN_GRE(1U)
31837 
31838 #define S_OUTER_IPV6_N_VLAN_GRE    22
31839 #define V_OUTER_IPV6_N_VLAN_GRE(x) ((x) << S_OUTER_IPV6_N_VLAN_GRE)
31840 #define F_OUTER_IPV6_N_VLAN_GRE    V_OUTER_IPV6_N_VLAN_GRE(1U)
31841 
31842 #define S_OUTER_IPV4_N_DOUBLE_VLAN_GRE    21
31843 #define V_OUTER_IPV4_N_DOUBLE_VLAN_GRE(x) ((x) << S_OUTER_IPV4_N_DOUBLE_VLAN_GRE)
31844 #define F_OUTER_IPV4_N_DOUBLE_VLAN_GRE    V_OUTER_IPV4_N_DOUBLE_VLAN_GRE(1U)
31845 
31846 #define S_OUTER_IPV6_N_DOUBLE_VLAN_GRE    20
31847 #define V_OUTER_IPV6_N_DOUBLE_VLAN_GRE(x) ((x) << S_OUTER_IPV6_N_DOUBLE_VLAN_GRE)
31848 #define F_OUTER_IPV6_N_DOUBLE_VLAN_GRE    V_OUTER_IPV6_N_DOUBLE_VLAN_GRE(1U)
31849 
31850 #define S_OUTER_IPV4_N_VLAN_VXLAN    19
31851 #define V_OUTER_IPV4_N_VLAN_VXLAN(x) ((x) << S_OUTER_IPV4_N_VLAN_VXLAN)
31852 #define F_OUTER_IPV4_N_VLAN_VXLAN    V_OUTER_IPV4_N_VLAN_VXLAN(1U)
31853 
31854 #define S_OUTER_IPV6_N_VLAN_VXLAN    18
31855 #define V_OUTER_IPV6_N_VLAN_VXLAN(x) ((x) << S_OUTER_IPV6_N_VLAN_VXLAN)
31856 #define F_OUTER_IPV6_N_VLAN_VXLAN    V_OUTER_IPV6_N_VLAN_VXLAN(1U)
31857 
31858 #define S_OUTER_IPV4_N_DOUBLE_VLAN_VXLAN    17
31859 #define V_OUTER_IPV4_N_DOUBLE_VLAN_VXLAN(x) ((x) << S_OUTER_IPV4_N_DOUBLE_VLAN_VXLAN)
31860 #define F_OUTER_IPV4_N_DOUBLE_VLAN_VXLAN    V_OUTER_IPV4_N_DOUBLE_VLAN_VXLAN(1U)
31861 
31862 #define S_OUTER_IPV6_N_DOUBLE_VLAN_VXLAN    16
31863 #define V_OUTER_IPV6_N_DOUBLE_VLAN_VXLAN(x) ((x) << S_OUTER_IPV6_N_DOUBLE_VLAN_VXLAN)
31864 #define F_OUTER_IPV6_N_DOUBLE_VLAN_VXLAN    V_OUTER_IPV6_N_DOUBLE_VLAN_VXLAN(1U)
31865 
31866 #define S_OUTER_IPV4_N_VLAN_GENEVE    15
31867 #define V_OUTER_IPV4_N_VLAN_GENEVE(x) ((x) << S_OUTER_IPV4_N_VLAN_GENEVE)
31868 #define F_OUTER_IPV4_N_VLAN_GENEVE    V_OUTER_IPV4_N_VLAN_GENEVE(1U)
31869 
31870 #define S_OUTER_IPV6_N_VLAN_GENEVE    14
31871 #define V_OUTER_IPV6_N_VLAN_GENEVE(x) ((x) << S_OUTER_IPV6_N_VLAN_GENEVE)
31872 #define F_OUTER_IPV6_N_VLAN_GENEVE    V_OUTER_IPV6_N_VLAN_GENEVE(1U)
31873 
31874 #define S_OUTER_IPV4_N_DOUBLE_VLAN_GENEVE    13
31875 #define V_OUTER_IPV4_N_DOUBLE_VLAN_GENEVE(x) ((x) << S_OUTER_IPV4_N_DOUBLE_VLAN_GENEVE)
31876 #define F_OUTER_IPV4_N_DOUBLE_VLAN_GENEVE    V_OUTER_IPV4_N_DOUBLE_VLAN_GENEVE(1U)
31877 
31878 #define S_OUTER_IPV6_N_DOUBLE_VLAN_GENEVE    12
31879 #define V_OUTER_IPV6_N_DOUBLE_VLAN_GENEVE(x) ((x) << S_OUTER_IPV6_N_DOUBLE_VLAN_GENEVE)
31880 #define F_OUTER_IPV6_N_DOUBLE_VLAN_GENEVE    V_OUTER_IPV6_N_DOUBLE_VLAN_GENEVE(1U)
31881 
31882 #define S_ERR_TNL_HDR_LEN    11
31883 #define V_ERR_TNL_HDR_LEN(x) ((x) << S_ERR_TNL_HDR_LEN)
31884 #define F_ERR_TNL_HDR_LEN    V_ERR_TNL_HDR_LEN(1U)
31885 
31886 #define S_NON_RUNT_FRAME    10
31887 #define V_NON_RUNT_FRAME(x) ((x) << S_NON_RUNT_FRAME)
31888 #define F_NON_RUNT_FRAME    V_NON_RUNT_FRAME(1U)
31889 
31890 #define S_INNER_VLAN_VLD    9
31891 #define V_INNER_VLAN_VLD(x) ((x) << S_INNER_VLAN_VLD)
31892 #define F_INNER_VLAN_VLD    V_INNER_VLAN_VLD(1U)
31893 
31894 #define S_ERR_IP_PAYLOAD_LEN    8
31895 #define V_ERR_IP_PAYLOAD_LEN(x) ((x) << S_ERR_IP_PAYLOAD_LEN)
31896 #define F_ERR_IP_PAYLOAD_LEN    V_ERR_IP_PAYLOAD_LEN(1U)
31897 
31898 #define S_ERR_UDP_PAYLOAD_LEN    7
31899 #define V_ERR_UDP_PAYLOAD_LEN(x) ((x) << S_ERR_UDP_PAYLOAD_LEN)
31900 #define F_ERR_UDP_PAYLOAD_LEN    V_ERR_UDP_PAYLOAD_LEN(1U)
31901 
31902 #define A_MPS_PORT_RX_PRS_DEBUG_FLAG_LPBK 0x164
31903 
31904 #define S_T6_INNER_VLAN_VLD    10
31905 #define V_T6_INNER_VLAN_VLD(x) ((x) << S_T6_INNER_VLAN_VLD)
31906 #define F_T6_INNER_VLAN_VLD    V_T6_INNER_VLAN_VLD(1U)
31907 
31908 #define S_T6_ERR_IP_PAYLOAD_LEN    9
31909 #define V_T6_ERR_IP_PAYLOAD_LEN(x) ((x) << S_T6_ERR_IP_PAYLOAD_LEN)
31910 #define F_T6_ERR_IP_PAYLOAD_LEN    V_T6_ERR_IP_PAYLOAD_LEN(1U)
31911 
31912 #define S_T6_ERR_UDP_PAYLOAD_LEN    8
31913 #define V_T6_ERR_UDP_PAYLOAD_LEN(x) ((x) << S_T6_ERR_UDP_PAYLOAD_LEN)
31914 #define F_T6_ERR_UDP_PAYLOAD_LEN    V_T6_ERR_UDP_PAYLOAD_LEN(1U)
31915 
31916 #define A_MPS_PORT_RX_REPL_VECT_SEL 0x168
31917 
31918 #define S_DIS_REPL_VECT_SEL    4
31919 #define V_DIS_REPL_VECT_SEL(x) ((x) << S_DIS_REPL_VECT_SEL)
31920 #define F_DIS_REPL_VECT_SEL    V_DIS_REPL_VECT_SEL(1U)
31921 
31922 #define S_REPL_VECT_SEL    0
31923 #define M_REPL_VECT_SEL    0xfU
31924 #define V_REPL_VECT_SEL(x) ((x) << S_REPL_VECT_SEL)
31925 #define G_REPL_VECT_SEL(x) (((x) >> S_REPL_VECT_SEL) & M_REPL_VECT_SEL)
31926 
31927 #define A_MPS_PORT_TX_MAC_RELOAD_CH0 0x190
31928 
31929 #define S_CREDIT    0
31930 #define M_CREDIT    0xffffU
31931 #define V_CREDIT(x) ((x) << S_CREDIT)
31932 #define G_CREDIT(x) (((x) >> S_CREDIT) & M_CREDIT)
31933 
31934 #define A_MPS_PORT_TX_MAC_RELOAD_CH1 0x194
31935 #define A_MPS_PORT_TX_MAC_RELOAD_CH2 0x198
31936 #define A_MPS_PORT_TX_MAC_RELOAD_CH3 0x19c
31937 #define A_MPS_PORT_TX_MAC_RELOAD_CH4 0x1a0
31938 #define A_MPS_PORT_TX_LPBK_RELOAD_CH0 0x1a8
31939 #define A_MPS_PORT_TX_LPBK_RELOAD_CH1 0x1ac
31940 #define A_MPS_PORT_TX_LPBK_RELOAD_CH2 0x1b0
31941 #define A_MPS_PORT_TX_LPBK_RELOAD_CH3 0x1b4
31942 #define A_MPS_PORT_TX_LPBK_RELOAD_CH4 0x1b8
31943 #define A_MPS_PORT_TX_FIFO_CTL 0x1c4
31944 
31945 #define S_FIFOTH    5
31946 #define M_FIFOTH    0x1ffU
31947 #define V_FIFOTH(x) ((x) << S_FIFOTH)
31948 #define G_FIFOTH(x) (((x) >> S_FIFOTH) & M_FIFOTH)
31949 
31950 #define S_FIFOEN    4
31951 #define V_FIFOEN(x) ((x) << S_FIFOEN)
31952 #define F_FIFOEN    V_FIFOEN(1U)
31953 
31954 #define S_MAXPKTCNT    0
31955 #define M_MAXPKTCNT    0xfU
31956 #define V_MAXPKTCNT(x) ((x) << S_MAXPKTCNT)
31957 #define G_MAXPKTCNT(x) (((x) >> S_MAXPKTCNT) & M_MAXPKTCNT)
31958 
31959 #define S_OUT_TH    22
31960 #define M_OUT_TH    0xffU
31961 #define V_OUT_TH(x) ((x) << S_OUT_TH)
31962 #define G_OUT_TH(x) (((x) >> S_OUT_TH) & M_OUT_TH)
31963 
31964 #define S_IN_TH    14
31965 #define M_IN_TH    0xffU
31966 #define V_IN_TH(x) ((x) << S_IN_TH)
31967 #define G_IN_TH(x) (((x) >> S_IN_TH) & M_IN_TH)
31968 
31969 #define A_MPS_PORT_FPGA_PAUSE_CTL 0x1c8
31970 
31971 #define S_FPGAPAUSEEN    0
31972 #define V_FPGAPAUSEEN(x) ((x) << S_FPGAPAUSEEN)
31973 #define F_FPGAPAUSEEN    V_FPGAPAUSEEN(1U)
31974 
31975 #define A_MPS_PORT_TX_PAUSE_PENDING_STATUS 0x1d0
31976 
31977 #define S_OFF_PENDING    8
31978 #define M_OFF_PENDING    0xffU
31979 #define V_OFF_PENDING(x) ((x) << S_OFF_PENDING)
31980 #define G_OFF_PENDING(x) (((x) >> S_OFF_PENDING) & M_OFF_PENDING)
31981 
31982 #define S_ON_PENDING    0
31983 #define M_ON_PENDING    0xffU
31984 #define V_ON_PENDING(x) ((x) << S_ON_PENDING)
31985 #define G_ON_PENDING(x) (((x) >> S_ON_PENDING) & M_ON_PENDING)
31986 
31987 #define A_MPS_PORT_CLS_HASH_SRAM 0x200
31988 
31989 #define S_VALID    20
31990 #define V_VALID(x) ((x) << S_VALID)
31991 #define F_VALID    V_VALID(1U)
31992 
31993 #define S_HASHPORTMAP    16
31994 #define M_HASHPORTMAP    0xfU
31995 #define V_HASHPORTMAP(x) ((x) << S_HASHPORTMAP)
31996 #define G_HASHPORTMAP(x) (((x) >> S_HASHPORTMAP) & M_HASHPORTMAP)
31997 
31998 #define S_MULTILISTEN    15
31999 #define V_MULTILISTEN(x) ((x) << S_MULTILISTEN)
32000 #define F_MULTILISTEN    V_MULTILISTEN(1U)
32001 
32002 #define S_PRIORITY    12
32003 #define M_PRIORITY    0x7U
32004 #define V_PRIORITY(x) ((x) << S_PRIORITY)
32005 #define G_PRIORITY(x) (((x) >> S_PRIORITY) & M_PRIORITY)
32006 
32007 #define S_REPLICATE    11
32008 #define V_REPLICATE(x) ((x) << S_REPLICATE)
32009 #define F_REPLICATE    V_REPLICATE(1U)
32010 
32011 #define S_PF    8
32012 #define M_PF    0x7U
32013 #define V_PF(x) ((x) << S_PF)
32014 #define G_PF(x) (((x) >> S_PF) & M_PF)
32015 
32016 #define S_VF_VALID    7
32017 #define V_VF_VALID(x) ((x) << S_VF_VALID)
32018 #define F_VF_VALID    V_VF_VALID(1U)
32019 
32020 #define S_VF    0
32021 #define M_VF    0x7fU
32022 #define V_VF(x) ((x) << S_VF)
32023 #define G_VF(x) (((x) >> S_VF) & M_VF)
32024 
32025 #define S_DISENCAPOUTERRPLCT    23
32026 #define V_DISENCAPOUTERRPLCT(x) ((x) << S_DISENCAPOUTERRPLCT)
32027 #define F_DISENCAPOUTERRPLCT    V_DISENCAPOUTERRPLCT(1U)
32028 
32029 #define S_DISENCAP    22
32030 #define V_DISENCAP(x) ((x) << S_DISENCAP)
32031 #define F_DISENCAP    V_DISENCAP(1U)
32032 
32033 #define S_T6_VALID    21
32034 #define V_T6_VALID(x) ((x) << S_T6_VALID)
32035 #define F_T6_VALID    V_T6_VALID(1U)
32036 
32037 #define S_T6_HASHPORTMAP    17
32038 #define M_T6_HASHPORTMAP    0xfU
32039 #define V_T6_HASHPORTMAP(x) ((x) << S_T6_HASHPORTMAP)
32040 #define G_T6_HASHPORTMAP(x) (((x) >> S_T6_HASHPORTMAP) & M_T6_HASHPORTMAP)
32041 
32042 #define S_T6_MULTILISTEN    16
32043 #define V_T6_MULTILISTEN(x) ((x) << S_T6_MULTILISTEN)
32044 #define F_T6_MULTILISTEN    V_T6_MULTILISTEN(1U)
32045 
32046 #define S_T6_PRIORITY    13
32047 #define M_T6_PRIORITY    0x7U
32048 #define V_T6_PRIORITY(x) ((x) << S_T6_PRIORITY)
32049 #define G_T6_PRIORITY(x) (((x) >> S_T6_PRIORITY) & M_T6_PRIORITY)
32050 
32051 #define S_T6_REPLICATE    12
32052 #define V_T6_REPLICATE(x) ((x) << S_T6_REPLICATE)
32053 #define F_T6_REPLICATE    V_T6_REPLICATE(1U)
32054 
32055 #define S_T6_PF    9
32056 #define M_T6_PF    0x7U
32057 #define V_T6_PF(x) ((x) << S_T6_PF)
32058 #define G_T6_PF(x) (((x) >> S_T6_PF) & M_T6_PF)
32059 
32060 #define S_T6_VF_VALID    8
32061 #define V_T6_VF_VALID(x) ((x) << S_T6_VF_VALID)
32062 #define F_T6_VF_VALID    V_T6_VF_VALID(1U)
32063 
32064 #define S_T6_VF    0
32065 #define M_T6_VF    0xffU
32066 #define V_T6_VF(x) ((x) << S_T6_VF)
32067 #define G_T6_VF(x) (((x) >> S_T6_VF) & M_T6_VF)
32068 
32069 #define A_MPS_PF_CTL 0x2c0
32070 
32071 #define S_TXEN    1
32072 #define V_TXEN(x) ((x) << S_TXEN)
32073 #define F_TXEN    V_TXEN(1U)
32074 
32075 #define S_RXEN    0
32076 #define V_RXEN(x) ((x) << S_RXEN)
32077 #define F_RXEN    V_RXEN(1U)
32078 
32079 #define A_MPS_PF_TX_QINQ_VLAN 0x2e0
32080 
32081 #define S_PROTOCOLID    16
32082 #define M_PROTOCOLID    0xffffU
32083 #define V_PROTOCOLID(x) ((x) << S_PROTOCOLID)
32084 #define G_PROTOCOLID(x) (((x) >> S_PROTOCOLID) & M_PROTOCOLID)
32085 
32086 #define S_VLAN_PRIO    13
32087 #define M_VLAN_PRIO    0x7U
32088 #define V_VLAN_PRIO(x) ((x) << S_VLAN_PRIO)
32089 #define G_VLAN_PRIO(x) (((x) >> S_VLAN_PRIO) & M_VLAN_PRIO)
32090 
32091 #define S_CFI    12
32092 #define V_CFI(x) ((x) << S_CFI)
32093 #define F_CFI    V_CFI(1U)
32094 
32095 #define S_TAG    0
32096 #define M_TAG    0xfffU
32097 #define V_TAG(x) ((x) << S_TAG)
32098 #define G_TAG(x) (((x) >> S_TAG) & M_TAG)
32099 
32100 #define A_MPS_PF_STAT_TX_PF_BCAST_BYTES_L 0x300
32101 #define A_MPS_PF_STAT_TX_PF_BCAST_BYTES_H 0x304
32102 #define A_MPS_PORT_CLS_HASH_CTL 0x304
32103 
32104 #define S_UNICASTENABLE    31
32105 #define V_UNICASTENABLE(x) ((x) << S_UNICASTENABLE)
32106 #define F_UNICASTENABLE    V_UNICASTENABLE(1U)
32107 
32108 #define A_MPS_PF_STAT_TX_PF_BCAST_FRAMES_L 0x308
32109 #define A_MPS_PORT_CLS_PROMISCUOUS_CTL 0x308
32110 
32111 #define S_PROMISCEN    31
32112 #define V_PROMISCEN(x) ((x) << S_PROMISCEN)
32113 #define F_PROMISCEN    V_PROMISCEN(1U)
32114 
32115 #define S_T6_MULTILISTEN    16
32116 #define V_T6_MULTILISTEN(x) ((x) << S_T6_MULTILISTEN)
32117 #define F_T6_MULTILISTEN    V_T6_MULTILISTEN(1U)
32118 
32119 #define S_T6_PRIORITY    13
32120 #define M_T6_PRIORITY    0x7U
32121 #define V_T6_PRIORITY(x) ((x) << S_T6_PRIORITY)
32122 #define G_T6_PRIORITY(x) (((x) >> S_T6_PRIORITY) & M_T6_PRIORITY)
32123 
32124 #define S_T6_REPLICATE    12
32125 #define V_T6_REPLICATE(x) ((x) << S_T6_REPLICATE)
32126 #define F_T6_REPLICATE    V_T6_REPLICATE(1U)
32127 
32128 #define S_T6_PF    9
32129 #define M_T6_PF    0x7U
32130 #define V_T6_PF(x) ((x) << S_T6_PF)
32131 #define G_T6_PF(x) (((x) >> S_T6_PF) & M_T6_PF)
32132 
32133 #define S_T6_VF_VALID    8
32134 #define V_T6_VF_VALID(x) ((x) << S_T6_VF_VALID)
32135 #define F_T6_VF_VALID    V_T6_VF_VALID(1U)
32136 
32137 #define S_T6_VF    0
32138 #define M_T6_VF    0xffU
32139 #define V_T6_VF(x) ((x) << S_T6_VF)
32140 #define G_T6_VF(x) (((x) >> S_T6_VF) & M_T6_VF)
32141 
32142 #define A_MPS_PF_STAT_TX_PF_BCAST_FRAMES_H 0x30c
32143 #define A_MPS_PORT_CLS_BMC_MAC_ADDR_L 0x30c
32144 #define A_MPS_PF_STAT_TX_PF_MCAST_BYTES_L 0x310
32145 #define A_MPS_PORT_CLS_BMC_MAC_ADDR_H 0x310
32146 
32147 #define S_MATCHBOTH    17
32148 #define V_MATCHBOTH(x) ((x) << S_MATCHBOTH)
32149 #define F_MATCHBOTH    V_MATCHBOTH(1U)
32150 
32151 #define S_BMC_VLD    16
32152 #define V_BMC_VLD(x) ((x) << S_BMC_VLD)
32153 #define F_BMC_VLD    V_BMC_VLD(1U)
32154 
32155 #define S_MATCHALL    18
32156 #define V_MATCHALL(x) ((x) << S_MATCHALL)
32157 #define F_MATCHALL    V_MATCHALL(1U)
32158 
32159 #define A_MPS_PF_STAT_TX_PF_MCAST_BYTES_H 0x314
32160 #define A_MPS_PORT_CLS_BMC_VLAN 0x314
32161 
32162 #define S_BMC_VLAN_SEL    13
32163 #define V_BMC_VLAN_SEL(x) ((x) << S_BMC_VLAN_SEL)
32164 #define F_BMC_VLAN_SEL    V_BMC_VLAN_SEL(1U)
32165 
32166 #define S_VLAN_VLD    12
32167 #define V_VLAN_VLD(x) ((x) << S_VLAN_VLD)
32168 #define F_VLAN_VLD    V_VLAN_VLD(1U)
32169 
32170 #define A_MPS_PF_STAT_TX_PF_MCAST_FRAMES_L 0x318
32171 #define A_MPS_PORT_CLS_CTL 0x318
32172 
32173 #define S_PF_VLAN_SEL    0
32174 #define V_PF_VLAN_SEL(x) ((x) << S_PF_VLAN_SEL)
32175 #define F_PF_VLAN_SEL    V_PF_VLAN_SEL(1U)
32176 
32177 #define S_LPBK_TCAM1_HIT_PRIORITY    14
32178 #define V_LPBK_TCAM1_HIT_PRIORITY(x) ((x) << S_LPBK_TCAM1_HIT_PRIORITY)
32179 #define F_LPBK_TCAM1_HIT_PRIORITY    V_LPBK_TCAM1_HIT_PRIORITY(1U)
32180 
32181 #define S_LPBK_TCAM0_HIT_PRIORITY    13
32182 #define V_LPBK_TCAM0_HIT_PRIORITY(x) ((x) << S_LPBK_TCAM0_HIT_PRIORITY)
32183 #define F_LPBK_TCAM0_HIT_PRIORITY    V_LPBK_TCAM0_HIT_PRIORITY(1U)
32184 
32185 #define S_LPBK_TCAM_PRIORITY    12
32186 #define V_LPBK_TCAM_PRIORITY(x) ((x) << S_LPBK_TCAM_PRIORITY)
32187 #define F_LPBK_TCAM_PRIORITY    V_LPBK_TCAM_PRIORITY(1U)
32188 
32189 #define S_LPBK_SMAC_TCAM_SEL    10
32190 #define M_LPBK_SMAC_TCAM_SEL    0x3U
32191 #define V_LPBK_SMAC_TCAM_SEL(x) ((x) << S_LPBK_SMAC_TCAM_SEL)
32192 #define G_LPBK_SMAC_TCAM_SEL(x) (((x) >> S_LPBK_SMAC_TCAM_SEL) & M_LPBK_SMAC_TCAM_SEL)
32193 
32194 #define S_LPBK_DMAC_TCAM_SEL    8
32195 #define M_LPBK_DMAC_TCAM_SEL    0x3U
32196 #define V_LPBK_DMAC_TCAM_SEL(x) ((x) << S_LPBK_DMAC_TCAM_SEL)
32197 #define G_LPBK_DMAC_TCAM_SEL(x) (((x) >> S_LPBK_DMAC_TCAM_SEL) & M_LPBK_DMAC_TCAM_SEL)
32198 
32199 #define S_TCAM1_HIT_PRIORITY    7
32200 #define V_TCAM1_HIT_PRIORITY(x) ((x) << S_TCAM1_HIT_PRIORITY)
32201 #define F_TCAM1_HIT_PRIORITY    V_TCAM1_HIT_PRIORITY(1U)
32202 
32203 #define S_TCAM0_HIT_PRIORITY    6
32204 #define V_TCAM0_HIT_PRIORITY(x) ((x) << S_TCAM0_HIT_PRIORITY)
32205 #define F_TCAM0_HIT_PRIORITY    V_TCAM0_HIT_PRIORITY(1U)
32206 
32207 #define S_TCAM_PRIORITY    5
32208 #define V_TCAM_PRIORITY(x) ((x) << S_TCAM_PRIORITY)
32209 #define F_TCAM_PRIORITY    V_TCAM_PRIORITY(1U)
32210 
32211 #define S_SMAC_TCAM_SEL    3
32212 #define M_SMAC_TCAM_SEL    0x3U
32213 #define V_SMAC_TCAM_SEL(x) ((x) << S_SMAC_TCAM_SEL)
32214 #define G_SMAC_TCAM_SEL(x) (((x) >> S_SMAC_TCAM_SEL) & M_SMAC_TCAM_SEL)
32215 
32216 #define S_DMAC_TCAM_SEL    1
32217 #define M_DMAC_TCAM_SEL    0x3U
32218 #define V_DMAC_TCAM_SEL(x) ((x) << S_DMAC_TCAM_SEL)
32219 #define G_DMAC_TCAM_SEL(x) (((x) >> S_DMAC_TCAM_SEL) & M_DMAC_TCAM_SEL)
32220 
32221 #define A_MPS_PF_STAT_TX_PF_MCAST_FRAMES_H 0x31c
32222 #define A_MPS_PORT_CLS_NCSI_ETH_TYPE 0x31c
32223 
32224 #define S_ETHTYPE2    0
32225 #define M_ETHTYPE2    0xffffU
32226 #define V_ETHTYPE2(x) ((x) << S_ETHTYPE2)
32227 #define G_ETHTYPE2(x) (((x) >> S_ETHTYPE2) & M_ETHTYPE2)
32228 
32229 #define A_MPS_PF_STAT_TX_PF_UCAST_BYTES_L 0x320
32230 #define A_MPS_PORT_CLS_NCSI_ETH_TYPE_EN 0x320
32231 
32232 #define S_EN1    1
32233 #define V_EN1(x) ((x) << S_EN1)
32234 #define F_EN1    V_EN1(1U)
32235 
32236 #define S_EN2    0
32237 #define V_EN2(x) ((x) << S_EN2)
32238 #define F_EN2    V_EN2(1U)
32239 
32240 #define A_MPS_PF_STAT_TX_PF_UCAST_BYTES_H 0x324
32241 #define A_MPS_PF_STAT_TX_PF_UCAST_FRAMES_L 0x328
32242 #define A_MPS_PF_STAT_TX_PF_UCAST_FRAMES_H 0x32c
32243 #define A_MPS_PF_STAT_TX_PF_OFFLOAD_BYTES_L 0x330
32244 #define A_MPS_PF_STAT_TX_PF_OFFLOAD_BYTES_H 0x334
32245 #define A_MPS_PF_STAT_TX_PF_OFFLOAD_FRAMES_L 0x338
32246 #define A_MPS_PF_STAT_TX_PF_OFFLOAD_FRAMES_H 0x33c
32247 #define A_MPS_PF_STAT_RX_PF_BYTES_L 0x340
32248 #define A_MPS_PF_STAT_RX_PF_BYTES_H 0x344
32249 #define A_MPS_PF_STAT_RX_PF_FRAMES_L 0x348
32250 #define A_MPS_PF_STAT_RX_PF_FRAMES_H 0x34c
32251 #define A_MPS_PF_STAT_RX_PF_BCAST_BYTES_L 0x350
32252 #define A_MPS_PF_STAT_RX_PF_BCAST_BYTES_H 0x354
32253 #define A_MPS_PF_STAT_RX_PF_BCAST_FRAMES_L 0x358
32254 #define A_MPS_PF_STAT_RX_PF_BCAST_FRAMES_H 0x35c
32255 #define A_MPS_PF_STAT_RX_PF_MCAST_BYTES_L 0x360
32256 #define A_MPS_PF_STAT_RX_PF_MCAST_BYTES_H 0x364
32257 #define A_MPS_PF_STAT_RX_PF_MCAST_FRAMES_L 0x368
32258 #define A_MPS_PF_STAT_RX_PF_MCAST_FRAMES_H 0x36c
32259 #define A_MPS_PF_STAT_RX_PF_UCAST_BYTES_L 0x370
32260 #define A_MPS_PF_STAT_RX_PF_UCAST_BYTES_H 0x374
32261 #define A_MPS_PF_STAT_RX_PF_UCAST_FRAMES_L 0x378
32262 #define A_MPS_PF_STAT_RX_PF_UCAST_FRAMES_H 0x37c
32263 #define A_MPS_PF_STAT_RX_PF_ERR_FRAMES_L 0x380
32264 #define A_MPS_PF_STAT_RX_PF_ERR_FRAMES_H 0x384
32265 #define A_MPS_PORT_STAT_TX_PORT_BYTES_L 0x400
32266 #define A_MPS_PORT_STAT_TX_PORT_BYTES_H 0x404
32267 #define A_MPS_PORT_STAT_TX_PORT_FRAMES_L 0x408
32268 #define A_MPS_PORT_STAT_TX_PORT_FRAMES_H 0x40c
32269 #define A_MPS_PORT_STAT_TX_PORT_BCAST_L 0x410
32270 #define A_MPS_PORT_STAT_TX_PORT_BCAST_H 0x414
32271 #define A_MPS_PORT_STAT_TX_PORT_MCAST_L 0x418
32272 #define A_MPS_PORT_STAT_TX_PORT_MCAST_H 0x41c
32273 #define A_MPS_PORT_STAT_TX_PORT_UCAST_L 0x420
32274 #define A_MPS_PORT_STAT_TX_PORT_UCAST_H 0x424
32275 #define A_MPS_PORT_STAT_TX_PORT_ERROR_L 0x428
32276 #define A_MPS_PORT_STAT_TX_PORT_ERROR_H 0x42c
32277 #define A_MPS_PORT_STAT_TX_PORT_64B_L 0x430
32278 #define A_MPS_PORT_STAT_TX_PORT_64B_H 0x434
32279 #define A_MPS_PORT_STAT_TX_PORT_65B_127B_L 0x438
32280 #define A_MPS_PORT_STAT_TX_PORT_65B_127B_H 0x43c
32281 #define A_MPS_PORT_STAT_TX_PORT_128B_255B_L 0x440
32282 #define A_MPS_PORT_STAT_TX_PORT_128B_255B_H 0x444
32283 #define A_MPS_PORT_STAT_TX_PORT_256B_511B_L 0x448
32284 #define A_MPS_PORT_STAT_TX_PORT_256B_511B_H 0x44c
32285 #define A_MPS_PORT_STAT_TX_PORT_512B_1023B_L 0x450
32286 #define A_MPS_PORT_STAT_TX_PORT_512B_1023B_H 0x454
32287 #define A_MPS_PORT_STAT_TX_PORT_1024B_1518B_L 0x458
32288 #define A_MPS_PORT_STAT_TX_PORT_1024B_1518B_H 0x45c
32289 #define A_MPS_PORT_STAT_TX_PORT_1519B_MAX_L 0x460
32290 #define A_MPS_PORT_STAT_TX_PORT_1519B_MAX_H 0x464
32291 #define A_MPS_PORT_STAT_TX_PORT_DROP_L 0x468
32292 #define A_MPS_PORT_STAT_TX_PORT_DROP_H 0x46c
32293 #define A_MPS_PORT_STAT_TX_PORT_PAUSE_L 0x470
32294 #define A_MPS_PORT_STAT_TX_PORT_PAUSE_H 0x474
32295 #define A_MPS_PORT_STAT_TX_PORT_PPP0_L 0x478
32296 #define A_MPS_PORT_STAT_TX_PORT_PPP0_H 0x47c
32297 #define A_MPS_PORT_STAT_TX_PORT_PPP1_L 0x480
32298 #define A_MPS_PORT_STAT_TX_PORT_PPP1_H 0x484
32299 #define A_MPS_PORT_STAT_TX_PORT_PPP2_L 0x488
32300 #define A_MPS_PORT_STAT_TX_PORT_PPP2_H 0x48c
32301 #define A_MPS_PORT_STAT_TX_PORT_PPP3_L 0x490
32302 #define A_MPS_PORT_STAT_TX_PORT_PPP3_H 0x494
32303 #define A_MPS_PORT_STAT_TX_PORT_PPP4_L 0x498
32304 #define A_MPS_PORT_STAT_TX_PORT_PPP4_H 0x49c
32305 #define A_MPS_PORT_STAT_TX_PORT_PPP5_L 0x4a0
32306 #define A_MPS_PORT_STAT_TX_PORT_PPP5_H 0x4a4
32307 #define A_MPS_PORT_STAT_TX_PORT_PPP6_L 0x4a8
32308 #define A_MPS_PORT_STAT_TX_PORT_PPP6_H 0x4ac
32309 #define A_MPS_PORT_STAT_TX_PORT_PPP7_L 0x4b0
32310 #define A_MPS_PORT_STAT_TX_PORT_PPP7_H 0x4b4
32311 #define A_MPS_PORT_STAT_LB_PORT_BYTES_L 0x4c0
32312 #define A_MPS_PORT_STAT_LB_PORT_BYTES_H 0x4c4
32313 #define A_MPS_PORT_STAT_LB_PORT_FRAMES_L 0x4c8
32314 #define A_MPS_PORT_STAT_LB_PORT_FRAMES_H 0x4cc
32315 #define A_MPS_PORT_STAT_LB_PORT_BCAST_L 0x4d0
32316 #define A_MPS_PORT_STAT_LB_PORT_BCAST_H 0x4d4
32317 #define A_MPS_PORT_STAT_LB_PORT_MCAST_L 0x4d8
32318 #define A_MPS_PORT_STAT_LB_PORT_MCAST_H 0x4dc
32319 #define A_MPS_PORT_STAT_LB_PORT_UCAST_L 0x4e0
32320 #define A_MPS_PORT_STAT_LB_PORT_UCAST_H 0x4e4
32321 #define A_MPS_PORT_STAT_LB_PORT_ERROR_L 0x4e8
32322 #define A_MPS_PORT_STAT_LB_PORT_ERROR_H 0x4ec
32323 #define A_MPS_PORT_STAT_LB_PORT_64B_L 0x4f0
32324 #define A_MPS_PORT_STAT_LB_PORT_64B_H 0x4f4
32325 #define A_MPS_PORT_STAT_LB_PORT_65B_127B_L 0x4f8
32326 #define A_MPS_PORT_STAT_LB_PORT_65B_127B_H 0x4fc
32327 #define A_MPS_PORT_STAT_LB_PORT_128B_255B_L 0x500
32328 #define A_MPS_PORT_STAT_LB_PORT_128B_255B_H 0x504
32329 #define A_MPS_PORT_STAT_LB_PORT_256B_511B_L 0x508
32330 #define A_MPS_PORT_STAT_LB_PORT_256B_511B_H 0x50c
32331 #define A_MPS_PORT_STAT_LB_PORT_512B_1023B_L 0x510
32332 #define A_MPS_PORT_STAT_LB_PORT_512B_1023B_H 0x514
32333 #define A_MPS_PORT_STAT_LB_PORT_1024B_1518B_L 0x518
32334 #define A_MPS_PORT_STAT_LB_PORT_1024B_1518B_H 0x51c
32335 #define A_MPS_PORT_STAT_LB_PORT_1519B_MAX_L 0x520
32336 #define A_MPS_PORT_STAT_LB_PORT_1519B_MAX_H 0x524
32337 #define A_MPS_PORT_STAT_LB_PORT_DROP_FRAMES 0x528
32338 #define A_MPS_PORT_STAT_LB_PORT_DROP_FRAMES_L 0x528
32339 #define A_MPS_PORT_STAT_LB_PORT_DROP_FRAMES_H 0x52c
32340 #define A_MPS_PORT_STAT_RX_PORT_BYTES_L 0x540
32341 #define A_MPS_PORT_STAT_RX_PORT_BYTES_H 0x544
32342 #define A_MPS_PORT_STAT_RX_PORT_FRAMES_L 0x548
32343 #define A_MPS_PORT_STAT_RX_PORT_FRAMES_H 0x54c
32344 #define A_MPS_PORT_STAT_RX_PORT_BCAST_L 0x550
32345 #define A_MPS_PORT_STAT_RX_PORT_BCAST_H 0x554
32346 #define A_MPS_PORT_STAT_RX_PORT_MCAST_L 0x558
32347 #define A_MPS_PORT_STAT_RX_PORT_MCAST_H 0x55c
32348 #define A_MPS_PORT_STAT_RX_PORT_UCAST_L 0x560
32349 #define A_MPS_PORT_STAT_RX_PORT_UCAST_H 0x564
32350 #define A_MPS_PORT_STAT_RX_PORT_MTU_ERROR_L 0x568
32351 #define A_MPS_PORT_STAT_RX_PORT_MTU_ERROR_H 0x56c
32352 #define A_MPS_PORT_STAT_RX_PORT_MTU_CRC_ERROR_L 0x570
32353 #define A_MPS_PORT_STAT_RX_PORT_MTU_CRC_ERROR_H 0x574
32354 #define A_MPS_PORT_STAT_RX_PORT_CRC_ERROR_L 0x578
32355 #define A_MPS_PORT_STAT_RX_PORT_CRC_ERROR_H 0x57c
32356 #define A_MPS_PORT_STAT_RX_PORT_LEN_ERROR_L 0x580
32357 #define A_MPS_PORT_STAT_RX_PORT_LEN_ERROR_H 0x584
32358 #define A_MPS_PORT_STAT_RX_PORT_SYM_ERROR_L 0x588
32359 #define A_MPS_PORT_STAT_RX_PORT_SYM_ERROR_H 0x58c
32360 #define A_MPS_PORT_STAT_RX_PORT_64B_L 0x590
32361 #define A_MPS_PORT_STAT_RX_PORT_64B_H 0x594
32362 #define A_MPS_PORT_STAT_RX_PORT_65B_127B_L 0x598
32363 #define A_MPS_PORT_STAT_RX_PORT_65B_127B_H 0x59c
32364 #define A_MPS_PORT_STAT_RX_PORT_128B_255B_L 0x5a0
32365 #define A_MPS_PORT_STAT_RX_PORT_128B_255B_H 0x5a4
32366 #define A_MPS_PORT_STAT_RX_PORT_256B_511B_L 0x5a8
32367 #define A_MPS_PORT_STAT_RX_PORT_256B_511B_H 0x5ac
32368 #define A_MPS_PORT_STAT_RX_PORT_512B_1023B_L 0x5b0
32369 #define A_MPS_PORT_STAT_RX_PORT_512B_1023B_H 0x5b4
32370 #define A_MPS_PORT_STAT_RX_PORT_1024B_1518B_L 0x5b8
32371 #define A_MPS_PORT_STAT_RX_PORT_1024B_1518B_H 0x5bc
32372 #define A_MPS_PORT_STAT_RX_PORT_1519B_MAX_L 0x5c0
32373 #define A_MPS_PORT_STAT_RX_PORT_1519B_MAX_H 0x5c4
32374 #define A_MPS_PORT_STAT_RX_PORT_PAUSE_L 0x5c8
32375 #define A_MPS_PORT_STAT_RX_PORT_PAUSE_H 0x5cc
32376 #define A_MPS_PORT_STAT_RX_PORT_PPP0_L 0x5d0
32377 #define A_MPS_PORT_STAT_RX_PORT_PPP0_H 0x5d4
32378 #define A_MPS_PORT_STAT_RX_PORT_PPP1_L 0x5d8
32379 #define A_MPS_PORT_STAT_RX_PORT_PPP1_H 0x5dc
32380 #define A_MPS_PORT_STAT_RX_PORT_PPP2_L 0x5e0
32381 #define A_MPS_PORT_STAT_RX_PORT_PPP2_H 0x5e4
32382 #define A_MPS_PORT_STAT_RX_PORT_PPP3_L 0x5e8
32383 #define A_MPS_PORT_STAT_RX_PORT_PPP3_H 0x5ec
32384 #define A_MPS_PORT_STAT_RX_PORT_PPP4_L 0x5f0
32385 #define A_MPS_PORT_STAT_RX_PORT_PPP4_H 0x5f4
32386 #define A_MPS_PORT_STAT_RX_PORT_PPP5_L 0x5f8
32387 #define A_MPS_PORT_STAT_RX_PORT_PPP5_H 0x5fc
32388 #define A_MPS_PORT_STAT_RX_PORT_PPP6_L 0x600
32389 #define A_MPS_PORT_STAT_RX_PORT_PPP6_H 0x604
32390 #define A_MPS_PORT_STAT_RX_PORT_PPP7_L 0x608
32391 #define A_MPS_PORT_STAT_RX_PORT_PPP7_H 0x60c
32392 #define A_MPS_PORT_STAT_RX_PORT_LESS_64B_L 0x610
32393 #define A_MPS_PORT_STAT_RX_PORT_LESS_64B_H 0x614
32394 #define A_MPS_PORT_STAT_RX_PORT_MAC_ERROR_L 0x618
32395 #define A_MPS_PORT_STAT_RX_PORT_MAC_ERROR_H 0x61c
32396 #define A_MPS_CMN_CTL 0x9000
32397 
32398 #define S_DETECT8023    3
32399 #define V_DETECT8023(x) ((x) << S_DETECT8023)
32400 #define F_DETECT8023    V_DETECT8023(1U)
32401 
32402 #define S_VFDIRECTACCESS    2
32403 #define V_VFDIRECTACCESS(x) ((x) << S_VFDIRECTACCESS)
32404 #define F_VFDIRECTACCESS    V_VFDIRECTACCESS(1U)
32405 
32406 #define S_NUMPORTS    0
32407 #define M_NUMPORTS    0x3U
32408 #define V_NUMPORTS(x) ((x) << S_NUMPORTS)
32409 #define G_NUMPORTS(x) (((x) >> S_NUMPORTS) & M_NUMPORTS)
32410 
32411 #define S_LPBKCRDTCTRL    4
32412 #define V_LPBKCRDTCTRL(x) ((x) << S_LPBKCRDTCTRL)
32413 #define F_LPBKCRDTCTRL    V_LPBKCRDTCTRL(1U)
32414 
32415 #define S_TX_PORT_STATS_MODE    8
32416 #define V_TX_PORT_STATS_MODE(x) ((x) << S_TX_PORT_STATS_MODE)
32417 #define F_TX_PORT_STATS_MODE    V_TX_PORT_STATS_MODE(1U)
32418 
32419 #define S_T5MODE    7
32420 #define V_T5MODE(x) ((x) << S_T5MODE)
32421 #define F_T5MODE    V_T5MODE(1U)
32422 
32423 #define S_SPEEDMODE    5
32424 #define M_SPEEDMODE    0x3U
32425 #define V_SPEEDMODE(x) ((x) << S_SPEEDMODE)
32426 #define G_SPEEDMODE(x) (((x) >> S_SPEEDMODE) & M_SPEEDMODE)
32427 
32428 #define A_MPS_INT_ENABLE 0x9004
32429 
32430 #define S_STATINTENB    5
32431 #define V_STATINTENB(x) ((x) << S_STATINTENB)
32432 #define F_STATINTENB    V_STATINTENB(1U)
32433 
32434 #define S_TXINTENB    4
32435 #define V_TXINTENB(x) ((x) << S_TXINTENB)
32436 #define F_TXINTENB    V_TXINTENB(1U)
32437 
32438 #define S_RXINTENB    3
32439 #define V_RXINTENB(x) ((x) << S_RXINTENB)
32440 #define F_RXINTENB    V_RXINTENB(1U)
32441 
32442 #define S_TRCINTENB    2
32443 #define V_TRCINTENB(x) ((x) << S_TRCINTENB)
32444 #define F_TRCINTENB    V_TRCINTENB(1U)
32445 
32446 #define S_CLSINTENB    1
32447 #define V_CLSINTENB(x) ((x) << S_CLSINTENB)
32448 #define F_CLSINTENB    V_CLSINTENB(1U)
32449 
32450 #define S_PLINTENB    0
32451 #define V_PLINTENB(x) ((x) << S_PLINTENB)
32452 #define F_PLINTENB    V_PLINTENB(1U)
32453 
32454 #define A_MPS_INT_CAUSE 0x9008
32455 
32456 #define S_STATINT    5
32457 #define V_STATINT(x) ((x) << S_STATINT)
32458 #define F_STATINT    V_STATINT(1U)
32459 
32460 #define S_TXINT    4
32461 #define V_TXINT(x) ((x) << S_TXINT)
32462 #define F_TXINT    V_TXINT(1U)
32463 
32464 #define S_RXINT    3
32465 #define V_RXINT(x) ((x) << S_RXINT)
32466 #define F_RXINT    V_RXINT(1U)
32467 
32468 #define S_TRCINT    2
32469 #define V_TRCINT(x) ((x) << S_TRCINT)
32470 #define F_TRCINT    V_TRCINT(1U)
32471 
32472 #define S_CLSINT    1
32473 #define V_CLSINT(x) ((x) << S_CLSINT)
32474 #define F_CLSINT    V_CLSINT(1U)
32475 
32476 #define S_PLINT    0
32477 #define V_PLINT(x) ((x) << S_PLINT)
32478 #define F_PLINT    V_PLINT(1U)
32479 
32480 #define A_MPS_CGEN_GLOBAL 0x900c
32481 
32482 #define S_MPS_GLOBAL_CGEN    0
32483 #define V_MPS_GLOBAL_CGEN(x) ((x) << S_MPS_GLOBAL_CGEN)
32484 #define F_MPS_GLOBAL_CGEN    V_MPS_GLOBAL_CGEN(1U)
32485 
32486 #define A_MPS_VF_TX_CTL_31_0 0x9010
32487 #define A_MPS_VF_TX_CTL_63_32 0x9014
32488 #define A_MPS_VF_TX_CTL_95_64 0x9018
32489 #define A_MPS_VF_TX_CTL_127_96 0x901c
32490 #define A_MPS_VF_RX_CTL_31_0 0x9020
32491 #define A_MPS_VF_RX_CTL_63_32 0x9024
32492 #define A_MPS_VF_RX_CTL_95_64 0x9028
32493 #define A_MPS_VF_RX_CTL_127_96 0x902c
32494 #define A_MPS_TX_PAUSE_DURATION_BUF_GRP0 0x9030
32495 
32496 #define S_VALUE    0
32497 #define M_VALUE    0xffffU
32498 #define V_VALUE(x) ((x) << S_VALUE)
32499 #define G_VALUE(x) (((x) >> S_VALUE) & M_VALUE)
32500 
32501 #define A_MPS_TX_PAUSE_DURATION_BUF_GRP1 0x9034
32502 #define A_MPS_TX_PAUSE_DURATION_BUF_GRP2 0x9038
32503 #define A_MPS_TX_PAUSE_DURATION_BUF_GRP3 0x903c
32504 #define A_MPS_TX_PAUSE_RETRANS_BUF_GRP0 0x9040
32505 #define A_MPS_TX_PAUSE_RETRANS_BUF_GRP1 0x9044
32506 #define A_MPS_TX_PAUSE_RETRANS_BUF_GRP2 0x9048
32507 #define A_MPS_TX_PAUSE_RETRANS_BUF_GRP3 0x904c
32508 #define A_MPS_TP_CSIDE_MUX_CTL_P0 0x9050
32509 
32510 #define S_WEIGHT    0
32511 #define M_WEIGHT    0xfffU
32512 #define V_WEIGHT(x) ((x) << S_WEIGHT)
32513 #define G_WEIGHT(x) (((x) >> S_WEIGHT) & M_WEIGHT)
32514 
32515 #define A_MPS_TP_CSIDE_MUX_CTL_P1 0x9054
32516 #define A_MPS_WOL_CTL_MODE 0x9058
32517 
32518 #define S_WOL_MODE    0
32519 #define V_WOL_MODE(x) ((x) << S_WOL_MODE)
32520 #define F_WOL_MODE    V_WOL_MODE(1U)
32521 
32522 #define A_MPS_FPGA_DEBUG 0x9060
32523 
32524 #define S_LPBK_EN    8
32525 #define V_LPBK_EN(x) ((x) << S_LPBK_EN)
32526 #define F_LPBK_EN    V_LPBK_EN(1U)
32527 
32528 #define S_CH_MAP3    6
32529 #define M_CH_MAP3    0x3U
32530 #define V_CH_MAP3(x) ((x) << S_CH_MAP3)
32531 #define G_CH_MAP3(x) (((x) >> S_CH_MAP3) & M_CH_MAP3)
32532 
32533 #define S_CH_MAP2    4
32534 #define M_CH_MAP2    0x3U
32535 #define V_CH_MAP2(x) ((x) << S_CH_MAP2)
32536 #define G_CH_MAP2(x) (((x) >> S_CH_MAP2) & M_CH_MAP2)
32537 
32538 #define S_CH_MAP1    2
32539 #define M_CH_MAP1    0x3U
32540 #define V_CH_MAP1(x) ((x) << S_CH_MAP1)
32541 #define G_CH_MAP1(x) (((x) >> S_CH_MAP1) & M_CH_MAP1)
32542 
32543 #define S_CH_MAP0    0
32544 #define M_CH_MAP0    0x3U
32545 #define V_CH_MAP0(x) ((x) << S_CH_MAP0)
32546 #define G_CH_MAP0(x) (((x) >> S_CH_MAP0) & M_CH_MAP0)
32547 
32548 #define S_FPGA_PTP_PORT    9
32549 #define M_FPGA_PTP_PORT    0x3U
32550 #define V_FPGA_PTP_PORT(x) ((x) << S_FPGA_PTP_PORT)
32551 #define G_FPGA_PTP_PORT(x) (((x) >> S_FPGA_PTP_PORT) & M_FPGA_PTP_PORT)
32552 
32553 #define A_MPS_DEBUG_CTL 0x9068
32554 
32555 #define S_DBGMODECTL_H    11
32556 #define V_DBGMODECTL_H(x) ((x) << S_DBGMODECTL_H)
32557 #define F_DBGMODECTL_H    V_DBGMODECTL_H(1U)
32558 
32559 #define S_DBGSEL_H    6
32560 #define M_DBGSEL_H    0x1fU
32561 #define V_DBGSEL_H(x) ((x) << S_DBGSEL_H)
32562 #define G_DBGSEL_H(x) (((x) >> S_DBGSEL_H) & M_DBGSEL_H)
32563 
32564 #define S_DBGMODECTL_L    5
32565 #define V_DBGMODECTL_L(x) ((x) << S_DBGMODECTL_L)
32566 #define F_DBGMODECTL_L    V_DBGMODECTL_L(1U)
32567 
32568 #define S_DBGSEL_L    0
32569 #define M_DBGSEL_L    0x1fU
32570 #define V_DBGSEL_L(x) ((x) << S_DBGSEL_L)
32571 #define G_DBGSEL_L(x) (((x) >> S_DBGSEL_L) & M_DBGSEL_L)
32572 
32573 #define A_MPS_DEBUG_DATA_REG_L 0x906c
32574 #define A_MPS_DEBUG_DATA_REG_H 0x9070
32575 #define A_MPS_TOP_SPARE 0x9074
32576 
32577 #define S_TOPSPARE    8
32578 #define M_TOPSPARE    0xffffffU
32579 #define V_TOPSPARE(x) ((x) << S_TOPSPARE)
32580 #define G_TOPSPARE(x) (((x) >> S_TOPSPARE) & M_TOPSPARE)
32581 
32582 #define S_OVLANSELLPBK3    7
32583 #define V_OVLANSELLPBK3(x) ((x) << S_OVLANSELLPBK3)
32584 #define F_OVLANSELLPBK3    V_OVLANSELLPBK3(1U)
32585 
32586 #define S_OVLANSELLPBK2    6
32587 #define V_OVLANSELLPBK2(x) ((x) << S_OVLANSELLPBK2)
32588 #define F_OVLANSELLPBK2    V_OVLANSELLPBK2(1U)
32589 
32590 #define S_OVLANSELLPBK1    5
32591 #define V_OVLANSELLPBK1(x) ((x) << S_OVLANSELLPBK1)
32592 #define F_OVLANSELLPBK1    V_OVLANSELLPBK1(1U)
32593 
32594 #define S_OVLANSELLPBK0    4
32595 #define V_OVLANSELLPBK0(x) ((x) << S_OVLANSELLPBK0)
32596 #define F_OVLANSELLPBK0    V_OVLANSELLPBK0(1U)
32597 
32598 #define S_OVLANSELMAC3    3
32599 #define V_OVLANSELMAC3(x) ((x) << S_OVLANSELMAC3)
32600 #define F_OVLANSELMAC3    V_OVLANSELMAC3(1U)
32601 
32602 #define S_OVLANSELMAC2    2
32603 #define V_OVLANSELMAC2(x) ((x) << S_OVLANSELMAC2)
32604 #define F_OVLANSELMAC2    V_OVLANSELMAC2(1U)
32605 
32606 #define S_OVLANSELMAC1    1
32607 #define V_OVLANSELMAC1(x) ((x) << S_OVLANSELMAC1)
32608 #define F_OVLANSELMAC1    V_OVLANSELMAC1(1U)
32609 
32610 #define S_OVLANSELMAC0    0
32611 #define V_OVLANSELMAC0(x) ((x) << S_OVLANSELMAC0)
32612 #define F_OVLANSELMAC0    V_OVLANSELMAC0(1U)
32613 
32614 #define S_T5_TOPSPARE    8
32615 #define M_T5_TOPSPARE    0xffffffU
32616 #define V_T5_TOPSPARE(x) ((x) << S_T5_TOPSPARE)
32617 #define G_T5_TOPSPARE(x) (((x) >> S_T5_TOPSPARE) & M_T5_TOPSPARE)
32618 
32619 #define A_MPS_T5_BUILD_REVISION 0x9078
32620 #define A_MPS_TX_PAUSE_DURATION_BUF_GRP_TH0 0x907c
32621 #define A_MPS_TX_PAUSE_DURATION_BUF_GRP_TH1 0x9080
32622 #define A_MPS_TX_PAUSE_DURATION_BUF_GRP_TH2 0x9084
32623 #define A_MPS_TX_PAUSE_DURATION_BUF_GRP_TH3 0x9088
32624 #define A_MPS_TX_PAUSE_DURATION_BUF_GRP_TH4 0x908c
32625 #define A_MPS_TX_PAUSE_DURATION_BUF_GRP_TH5 0x9090
32626 #define A_MPS_TX_PAUSE_DURATION_BUF_GRP_TH6 0x9094
32627 #define A_MPS_TX_PAUSE_DURATION_BUF_GRP_TH7 0x9098
32628 #define A_MPS_TX_PAUSE_DURATION_BUF_GRP_TH8 0x909c
32629 #define A_MPS_TX_PAUSE_DURATION_BUF_GRP_TH9 0x90a0
32630 #define A_MPS_TX_PAUSE_DURATION_BUF_GRP_TH10 0x90a4
32631 #define A_MPS_TX_PAUSE_DURATION_BUF_GRP_TH11 0x90a8
32632 #define A_MPS_TX_PAUSE_DURATION_BUF_GRP_TH12 0x90ac
32633 #define A_MPS_TX_PAUSE_DURATION_BUF_GRP_TH13 0x90b0
32634 #define A_MPS_TX_PAUSE_DURATION_BUF_GRP_TH14 0x90b4
32635 #define A_MPS_TX_PAUSE_DURATION_BUF_GRP_TH15 0x90b8
32636 #define A_MPS_TX_PAUSE_RETRANS_BUF_GRP_TH0 0x90bc
32637 #define A_MPS_TX_PAUSE_RETRANS_BUF_GRP_TH1 0x90c0
32638 #define A_MPS_TX_PAUSE_RETRANS_BUF_GRP_TH2 0x90c4
32639 #define A_MPS_TX_PAUSE_RETRANS_BUF_GRP_TH3 0x90c8
32640 #define A_MPS_TX_PAUSE_RETRANS_BUF_GRP_TH4 0x90cc
32641 #define A_MPS_TX_PAUSE_RETRANS_BUF_GRP_TH5 0x90d0
32642 #define A_MPS_TX_PAUSE_RETRANS_BUF_GRP_TH6 0x90d4
32643 #define A_MPS_TX_PAUSE_RETRANS_BUF_GRP_TH7 0x90d8
32644 #define A_MPS_TX_PAUSE_RETRANS_BUF_GRP_TH8 0x90dc
32645 #define A_MPS_TX_PAUSE_RETRANS_BUF_GRP_TH9 0x90e0
32646 #define A_MPS_TX_PAUSE_RETRANS_BUF_GRP_TH10 0x90e4
32647 #define A_MPS_TX_PAUSE_RETRANS_BUF_GRP_TH11 0x90e8
32648 #define A_MPS_TX_PAUSE_RETRANS_BUF_GRP_TH12 0x90ec
32649 #define A_MPS_TX_PAUSE_RETRANS_BUF_GRP_TH13 0x90f0
32650 #define A_MPS_TX_PAUSE_RETRANS_BUF_GRP_TH14 0x90f4
32651 #define A_MPS_TX_PAUSE_RETRANS_BUF_GRP_TH15 0x90f8
32652 #define A_MPS_BUILD_REVISION 0x90fc
32653 #define A_MPS_VF_TX_CTL_159_128 0x9100
32654 #define A_MPS_VF_TX_CTL_191_160 0x9104
32655 #define A_MPS_VF_TX_CTL_223_192 0x9108
32656 #define A_MPS_VF_TX_CTL_255_224 0x910c
32657 #define A_MPS_VF_RX_CTL_159_128 0x9110
32658 #define A_MPS_VF_RX_CTL_191_160 0x9114
32659 #define A_MPS_VF_RX_CTL_223_192 0x9118
32660 #define A_MPS_VF_RX_CTL_255_224 0x911c
32661 #define A_MPS_FPGA_BIST_CFG_P0 0x9120
32662 
32663 #define S_ADDRMASK    16
32664 #define M_ADDRMASK    0xffffU
32665 #define V_ADDRMASK(x) ((x) << S_ADDRMASK)
32666 #define G_ADDRMASK(x) (((x) >> S_ADDRMASK) & M_ADDRMASK)
32667 
32668 #define S_T6_BASEADDR    0
32669 #define M_T6_BASEADDR    0xffffU
32670 #define V_T6_BASEADDR(x) ((x) << S_T6_BASEADDR)
32671 #define G_T6_BASEADDR(x) (((x) >> S_T6_BASEADDR) & M_T6_BASEADDR)
32672 
32673 #define A_MPS_FPGA_BIST_CFG_P1 0x9124
32674 
32675 #define S_T6_BASEADDR    0
32676 #define M_T6_BASEADDR    0xffffU
32677 #define V_T6_BASEADDR(x) ((x) << S_T6_BASEADDR)
32678 #define G_T6_BASEADDR(x) (((x) >> S_T6_BASEADDR) & M_T6_BASEADDR)
32679 
32680 #define A_MPS_TX_PRTY_SEL 0x9400
32681 
32682 #define S_CH4_PRTY    20
32683 #define M_CH4_PRTY    0x7U
32684 #define V_CH4_PRTY(x) ((x) << S_CH4_PRTY)
32685 #define G_CH4_PRTY(x) (((x) >> S_CH4_PRTY) & M_CH4_PRTY)
32686 
32687 #define S_CH3_PRTY    16
32688 #define M_CH3_PRTY    0x7U
32689 #define V_CH3_PRTY(x) ((x) << S_CH3_PRTY)
32690 #define G_CH3_PRTY(x) (((x) >> S_CH3_PRTY) & M_CH3_PRTY)
32691 
32692 #define S_CH2_PRTY    12
32693 #define M_CH2_PRTY    0x7U
32694 #define V_CH2_PRTY(x) ((x) << S_CH2_PRTY)
32695 #define G_CH2_PRTY(x) (((x) >> S_CH2_PRTY) & M_CH2_PRTY)
32696 
32697 #define S_CH1_PRTY    8
32698 #define M_CH1_PRTY    0x7U
32699 #define V_CH1_PRTY(x) ((x) << S_CH1_PRTY)
32700 #define G_CH1_PRTY(x) (((x) >> S_CH1_PRTY) & M_CH1_PRTY)
32701 
32702 #define S_CH0_PRTY    4
32703 #define M_CH0_PRTY    0x7U
32704 #define V_CH0_PRTY(x) ((x) << S_CH0_PRTY)
32705 #define G_CH0_PRTY(x) (((x) >> S_CH0_PRTY) & M_CH0_PRTY)
32706 
32707 #define S_TP_SOURCE    2
32708 #define M_TP_SOURCE    0x3U
32709 #define V_TP_SOURCE(x) ((x) << S_TP_SOURCE)
32710 #define G_TP_SOURCE(x) (((x) >> S_TP_SOURCE) & M_TP_SOURCE)
32711 
32712 #define S_NCSI_SOURCE    0
32713 #define M_NCSI_SOURCE    0x3U
32714 #define V_NCSI_SOURCE(x) ((x) << S_NCSI_SOURCE)
32715 #define G_NCSI_SOURCE(x) (((x) >> S_NCSI_SOURCE) & M_NCSI_SOURCE)
32716 
32717 #define A_MPS_TX_INT_ENABLE 0x9404
32718 
32719 #define S_PORTERR    16
32720 #define V_PORTERR(x) ((x) << S_PORTERR)
32721 #define F_PORTERR    V_PORTERR(1U)
32722 
32723 #define S_FRMERR    15
32724 #define V_FRMERR(x) ((x) << S_FRMERR)
32725 #define F_FRMERR    V_FRMERR(1U)
32726 
32727 #define S_SECNTERR    14
32728 #define V_SECNTERR(x) ((x) << S_SECNTERR)
32729 #define F_SECNTERR    V_SECNTERR(1U)
32730 
32731 #define S_BUBBLE    13
32732 #define V_BUBBLE(x) ((x) << S_BUBBLE)
32733 #define F_BUBBLE    V_BUBBLE(1U)
32734 
32735 #define S_TXDESCFIFO    9
32736 #define M_TXDESCFIFO    0xfU
32737 #define V_TXDESCFIFO(x) ((x) << S_TXDESCFIFO)
32738 #define G_TXDESCFIFO(x) (((x) >> S_TXDESCFIFO) & M_TXDESCFIFO)
32739 
32740 #define S_TXDATAFIFO    5
32741 #define M_TXDATAFIFO    0xfU
32742 #define V_TXDATAFIFO(x) ((x) << S_TXDATAFIFO)
32743 #define G_TXDATAFIFO(x) (((x) >> S_TXDATAFIFO) & M_TXDATAFIFO)
32744 
32745 #define S_NCSIFIFO    4
32746 #define V_NCSIFIFO(x) ((x) << S_NCSIFIFO)
32747 #define F_NCSIFIFO    V_NCSIFIFO(1U)
32748 
32749 #define S_TPFIFO    0
32750 #define M_TPFIFO    0xfU
32751 #define V_TPFIFO(x) ((x) << S_TPFIFO)
32752 #define G_TPFIFO(x) (((x) >> S_TPFIFO) & M_TPFIFO)
32753 
32754 #define A_MPS_TX_INT_CAUSE 0x9408
32755 #define A_MPS_TX_NCSI2MPS_CNT 0x940c
32756 #define A_MPS_TX_PERR_ENABLE 0x9410
32757 #define A_MPS_TX_PERR_INJECT 0x9414
32758 
32759 #define S_MPSTXMEMSEL    1
32760 #define M_MPSTXMEMSEL    0x1fU
32761 #define V_MPSTXMEMSEL(x) ((x) << S_MPSTXMEMSEL)
32762 #define G_MPSTXMEMSEL(x) (((x) >> S_MPSTXMEMSEL) & M_MPSTXMEMSEL)
32763 
32764 #define A_MPS_TX_SE_CNT_TP01 0x9418
32765 #define A_MPS_TX_SE_CNT_TP23 0x941c
32766 #define A_MPS_TX_SE_CNT_MAC01 0x9420
32767 #define A_MPS_TX_SE_CNT_MAC23 0x9424
32768 #define A_MPS_TX_SECNT_SPI_BUBBLE_ERR 0x9428
32769 
32770 #define S_BUBBLEERR    16
32771 #define M_BUBBLEERR    0xffU
32772 #define V_BUBBLEERR(x) ((x) << S_BUBBLEERR)
32773 #define G_BUBBLEERR(x) (((x) >> S_BUBBLEERR) & M_BUBBLEERR)
32774 
32775 #define S_SPI    8
32776 #define M_SPI    0xffU
32777 #define V_SPI(x) ((x) << S_SPI)
32778 #define G_SPI(x) (((x) >> S_SPI) & M_SPI)
32779 
32780 #define S_SECNT    0
32781 #define M_SECNT    0xffU
32782 #define V_SECNT(x) ((x) << S_SECNT)
32783 #define G_SECNT(x) (((x) >> S_SECNT) & M_SECNT)
32784 
32785 #define A_MPS_TX_SECNT_BUBBLE_CLR 0x942c
32786 
32787 #define S_BUBBLECLR    8
32788 #define M_BUBBLECLR    0xffU
32789 #define V_BUBBLECLR(x) ((x) << S_BUBBLECLR)
32790 #define G_BUBBLECLR(x) (((x) >> S_BUBBLECLR) & M_BUBBLECLR)
32791 
32792 #define S_NCSISECNT    20
32793 #define V_NCSISECNT(x) ((x) << S_NCSISECNT)
32794 #define F_NCSISECNT    V_NCSISECNT(1U)
32795 
32796 #define S_LPBKSECNT    16
32797 #define M_LPBKSECNT    0xfU
32798 #define V_LPBKSECNT(x) ((x) << S_LPBKSECNT)
32799 #define G_LPBKSECNT(x) (((x) >> S_LPBKSECNT) & M_LPBKSECNT)
32800 
32801 #define A_MPS_TX_PORT_ERR 0x9430
32802 
32803 #define S_LPBKPT3    7
32804 #define V_LPBKPT3(x) ((x) << S_LPBKPT3)
32805 #define F_LPBKPT3    V_LPBKPT3(1U)
32806 
32807 #define S_LPBKPT2    6
32808 #define V_LPBKPT2(x) ((x) << S_LPBKPT2)
32809 #define F_LPBKPT2    V_LPBKPT2(1U)
32810 
32811 #define S_LPBKPT1    5
32812 #define V_LPBKPT1(x) ((x) << S_LPBKPT1)
32813 #define F_LPBKPT1    V_LPBKPT1(1U)
32814 
32815 #define S_LPBKPT0    4
32816 #define V_LPBKPT0(x) ((x) << S_LPBKPT0)
32817 #define F_LPBKPT0    V_LPBKPT0(1U)
32818 
32819 #define S_PT3    3
32820 #define V_PT3(x) ((x) << S_PT3)
32821 #define F_PT3    V_PT3(1U)
32822 
32823 #define S_PT2    2
32824 #define V_PT2(x) ((x) << S_PT2)
32825 #define F_PT2    V_PT2(1U)
32826 
32827 #define S_PT1    1
32828 #define V_PT1(x) ((x) << S_PT1)
32829 #define F_PT1    V_PT1(1U)
32830 
32831 #define S_PT0    0
32832 #define V_PT0(x) ((x) << S_PT0)
32833 #define F_PT0    V_PT0(1U)
32834 
32835 #define A_MPS_TX_LPBK_DROP_BP_CTL_CH0 0x9434
32836 
32837 #define S_BPEN    1
32838 #define V_BPEN(x) ((x) << S_BPEN)
32839 #define F_BPEN    V_BPEN(1U)
32840 
32841 #define S_DROPEN    0
32842 #define V_DROPEN(x) ((x) << S_DROPEN)
32843 #define F_DROPEN    V_DROPEN(1U)
32844 
32845 #define A_MPS_TX_LPBK_DROP_BP_CTL_CH1 0x9438
32846 #define A_MPS_TX_LPBK_DROP_BP_CTL_CH2 0x943c
32847 #define A_MPS_TX_LPBK_DROP_BP_CTL_CH3 0x9440
32848 #define A_MPS_TX_DEBUG_REG_TP2TX_10 0x9444
32849 
32850 #define S_SOPCH1    31
32851 #define V_SOPCH1(x) ((x) << S_SOPCH1)
32852 #define F_SOPCH1    V_SOPCH1(1U)
32853 
32854 #define S_EOPCH1    30
32855 #define V_EOPCH1(x) ((x) << S_EOPCH1)
32856 #define F_EOPCH1    V_EOPCH1(1U)
32857 
32858 #define S_SIZECH1    27
32859 #define M_SIZECH1    0x7U
32860 #define V_SIZECH1(x) ((x) << S_SIZECH1)
32861 #define G_SIZECH1(x) (((x) >> S_SIZECH1) & M_SIZECH1)
32862 
32863 #define S_ERRCH1    26
32864 #define V_ERRCH1(x) ((x) << S_ERRCH1)
32865 #define F_ERRCH1    V_ERRCH1(1U)
32866 
32867 #define S_FULLCH1    25
32868 #define V_FULLCH1(x) ((x) << S_FULLCH1)
32869 #define F_FULLCH1    V_FULLCH1(1U)
32870 
32871 #define S_VALIDCH1    24
32872 #define V_VALIDCH1(x) ((x) << S_VALIDCH1)
32873 #define F_VALIDCH1    V_VALIDCH1(1U)
32874 
32875 #define S_DATACH1    16
32876 #define M_DATACH1    0xffU
32877 #define V_DATACH1(x) ((x) << S_DATACH1)
32878 #define G_DATACH1(x) (((x) >> S_DATACH1) & M_DATACH1)
32879 
32880 #define S_SOPCH0    15
32881 #define V_SOPCH0(x) ((x) << S_SOPCH0)
32882 #define F_SOPCH0    V_SOPCH0(1U)
32883 
32884 #define S_EOPCH0    14
32885 #define V_EOPCH0(x) ((x) << S_EOPCH0)
32886 #define F_EOPCH0    V_EOPCH0(1U)
32887 
32888 #define S_SIZECH0    11
32889 #define M_SIZECH0    0x7U
32890 #define V_SIZECH0(x) ((x) << S_SIZECH0)
32891 #define G_SIZECH0(x) (((x) >> S_SIZECH0) & M_SIZECH0)
32892 
32893 #define S_ERRCH0    10
32894 #define V_ERRCH0(x) ((x) << S_ERRCH0)
32895 #define F_ERRCH0    V_ERRCH0(1U)
32896 
32897 #define S_FULLCH0    9
32898 #define V_FULLCH0(x) ((x) << S_FULLCH0)
32899 #define F_FULLCH0    V_FULLCH0(1U)
32900 
32901 #define S_VALIDCH0    8
32902 #define V_VALIDCH0(x) ((x) << S_VALIDCH0)
32903 #define F_VALIDCH0    V_VALIDCH0(1U)
32904 
32905 #define S_DATACH0    0
32906 #define M_DATACH0    0xffU
32907 #define V_DATACH0(x) ((x) << S_DATACH0)
32908 #define G_DATACH0(x) (((x) >> S_DATACH0) & M_DATACH0)
32909 
32910 #define S_T5_SIZECH1    26
32911 #define M_T5_SIZECH1    0xfU
32912 #define V_T5_SIZECH1(x) ((x) << S_T5_SIZECH1)
32913 #define G_T5_SIZECH1(x) (((x) >> S_T5_SIZECH1) & M_T5_SIZECH1)
32914 
32915 #define S_T5_ERRCH1    25
32916 #define V_T5_ERRCH1(x) ((x) << S_T5_ERRCH1)
32917 #define F_T5_ERRCH1    V_T5_ERRCH1(1U)
32918 
32919 #define S_T5_FULLCH1    24
32920 #define V_T5_FULLCH1(x) ((x) << S_T5_FULLCH1)
32921 #define F_T5_FULLCH1    V_T5_FULLCH1(1U)
32922 
32923 #define S_T5_VALIDCH1    23
32924 #define V_T5_VALIDCH1(x) ((x) << S_T5_VALIDCH1)
32925 #define F_T5_VALIDCH1    V_T5_VALIDCH1(1U)
32926 
32927 #define S_T5_DATACH1    16
32928 #define M_T5_DATACH1    0x7fU
32929 #define V_T5_DATACH1(x) ((x) << S_T5_DATACH1)
32930 #define G_T5_DATACH1(x) (((x) >> S_T5_DATACH1) & M_T5_DATACH1)
32931 
32932 #define S_T5_SIZECH0    10
32933 #define M_T5_SIZECH0    0xfU
32934 #define V_T5_SIZECH0(x) ((x) << S_T5_SIZECH0)
32935 #define G_T5_SIZECH0(x) (((x) >> S_T5_SIZECH0) & M_T5_SIZECH0)
32936 
32937 #define S_T5_ERRCH0    9
32938 #define V_T5_ERRCH0(x) ((x) << S_T5_ERRCH0)
32939 #define F_T5_ERRCH0    V_T5_ERRCH0(1U)
32940 
32941 #define S_T5_FULLCH0    8
32942 #define V_T5_FULLCH0(x) ((x) << S_T5_FULLCH0)
32943 #define F_T5_FULLCH0    V_T5_FULLCH0(1U)
32944 
32945 #define S_T5_VALIDCH0    7
32946 #define V_T5_VALIDCH0(x) ((x) << S_T5_VALIDCH0)
32947 #define F_T5_VALIDCH0    V_T5_VALIDCH0(1U)
32948 
32949 #define S_T5_DATACH0    0
32950 #define M_T5_DATACH0    0x7fU
32951 #define V_T5_DATACH0(x) ((x) << S_T5_DATACH0)
32952 #define G_T5_DATACH0(x) (((x) >> S_T5_DATACH0) & M_T5_DATACH0)
32953 
32954 #define A_MPS_TX_DEBUG_REG_TP2TX_32 0x9448
32955 
32956 #define S_SOPCH3    31
32957 #define V_SOPCH3(x) ((x) << S_SOPCH3)
32958 #define F_SOPCH3    V_SOPCH3(1U)
32959 
32960 #define S_EOPCH3    30
32961 #define V_EOPCH3(x) ((x) << S_EOPCH3)
32962 #define F_EOPCH3    V_EOPCH3(1U)
32963 
32964 #define S_SIZECH3    27
32965 #define M_SIZECH3    0x7U
32966 #define V_SIZECH3(x) ((x) << S_SIZECH3)
32967 #define G_SIZECH3(x) (((x) >> S_SIZECH3) & M_SIZECH3)
32968 
32969 #define S_ERRCH3    26
32970 #define V_ERRCH3(x) ((x) << S_ERRCH3)
32971 #define F_ERRCH3    V_ERRCH3(1U)
32972 
32973 #define S_FULLCH3    25
32974 #define V_FULLCH3(x) ((x) << S_FULLCH3)
32975 #define F_FULLCH3    V_FULLCH3(1U)
32976 
32977 #define S_VALIDCH3    24
32978 #define V_VALIDCH3(x) ((x) << S_VALIDCH3)
32979 #define F_VALIDCH3    V_VALIDCH3(1U)
32980 
32981 #define S_DATACH3    16
32982 #define M_DATACH3    0xffU
32983 #define V_DATACH3(x) ((x) << S_DATACH3)
32984 #define G_DATACH3(x) (((x) >> S_DATACH3) & M_DATACH3)
32985 
32986 #define S_SOPCH2    15
32987 #define V_SOPCH2(x) ((x) << S_SOPCH2)
32988 #define F_SOPCH2    V_SOPCH2(1U)
32989 
32990 #define S_EOPCH2    14
32991 #define V_EOPCH2(x) ((x) << S_EOPCH2)
32992 #define F_EOPCH2    V_EOPCH2(1U)
32993 
32994 #define S_SIZECH2    11
32995 #define M_SIZECH2    0x7U
32996 #define V_SIZECH2(x) ((x) << S_SIZECH2)
32997 #define G_SIZECH2(x) (((x) >> S_SIZECH2) & M_SIZECH2)
32998 
32999 #define S_ERRCH2    10
33000 #define V_ERRCH2(x) ((x) << S_ERRCH2)
33001 #define F_ERRCH2    V_ERRCH2(1U)
33002 
33003 #define S_FULLCH2    9
33004 #define V_FULLCH2(x) ((x) << S_FULLCH2)
33005 #define F_FULLCH2    V_FULLCH2(1U)
33006 
33007 #define S_VALIDCH2    8
33008 #define V_VALIDCH2(x) ((x) << S_VALIDCH2)
33009 #define F_VALIDCH2    V_VALIDCH2(1U)
33010 
33011 #define S_DATACH2    0
33012 #define M_DATACH2    0xffU
33013 #define V_DATACH2(x) ((x) << S_DATACH2)
33014 #define G_DATACH2(x) (((x) >> S_DATACH2) & M_DATACH2)
33015 
33016 #define S_T5_SIZECH3    26
33017 #define M_T5_SIZECH3    0xfU
33018 #define V_T5_SIZECH3(x) ((x) << S_T5_SIZECH3)
33019 #define G_T5_SIZECH3(x) (((x) >> S_T5_SIZECH3) & M_T5_SIZECH3)
33020 
33021 #define S_T5_ERRCH3    25
33022 #define V_T5_ERRCH3(x) ((x) << S_T5_ERRCH3)
33023 #define F_T5_ERRCH3    V_T5_ERRCH3(1U)
33024 
33025 #define S_T5_FULLCH3    24
33026 #define V_T5_FULLCH3(x) ((x) << S_T5_FULLCH3)
33027 #define F_T5_FULLCH3    V_T5_FULLCH3(1U)
33028 
33029 #define S_T5_VALIDCH3    23
33030 #define V_T5_VALIDCH3(x) ((x) << S_T5_VALIDCH3)
33031 #define F_T5_VALIDCH3    V_T5_VALIDCH3(1U)
33032 
33033 #define S_T5_DATACH3    16
33034 #define M_T5_DATACH3    0x7fU
33035 #define V_T5_DATACH3(x) ((x) << S_T5_DATACH3)
33036 #define G_T5_DATACH3(x) (((x) >> S_T5_DATACH3) & M_T5_DATACH3)
33037 
33038 #define S_T5_SIZECH2    10
33039 #define M_T5_SIZECH2    0xfU
33040 #define V_T5_SIZECH2(x) ((x) << S_T5_SIZECH2)
33041 #define G_T5_SIZECH2(x) (((x) >> S_T5_SIZECH2) & M_T5_SIZECH2)
33042 
33043 #define S_T5_ERRCH2    9
33044 #define V_T5_ERRCH2(x) ((x) << S_T5_ERRCH2)
33045 #define F_T5_ERRCH2    V_T5_ERRCH2(1U)
33046 
33047 #define S_T5_FULLCH2    8
33048 #define V_T5_FULLCH2(x) ((x) << S_T5_FULLCH2)
33049 #define F_T5_FULLCH2    V_T5_FULLCH2(1U)
33050 
33051 #define S_T5_VALIDCH2    7
33052 #define V_T5_VALIDCH2(x) ((x) << S_T5_VALIDCH2)
33053 #define F_T5_VALIDCH2    V_T5_VALIDCH2(1U)
33054 
33055 #define S_T5_DATACH2    0
33056 #define M_T5_DATACH2    0x7fU
33057 #define V_T5_DATACH2(x) ((x) << S_T5_DATACH2)
33058 #define G_T5_DATACH2(x) (((x) >> S_T5_DATACH2) & M_T5_DATACH2)
33059 
33060 #define A_MPS_TX_DEBUG_REG_TX2MAC_10 0x944c
33061 
33062 #define S_SOPPT1    31
33063 #define V_SOPPT1(x) ((x) << S_SOPPT1)
33064 #define F_SOPPT1    V_SOPPT1(1U)
33065 
33066 #define S_EOPPT1    30
33067 #define V_EOPPT1(x) ((x) << S_EOPPT1)
33068 #define F_EOPPT1    V_EOPPT1(1U)
33069 
33070 #define S_SIZEPT1    27
33071 #define M_SIZEPT1    0x7U
33072 #define V_SIZEPT1(x) ((x) << S_SIZEPT1)
33073 #define G_SIZEPT1(x) (((x) >> S_SIZEPT1) & M_SIZEPT1)
33074 
33075 #define S_ERRPT1    26
33076 #define V_ERRPT1(x) ((x) << S_ERRPT1)
33077 #define F_ERRPT1    V_ERRPT1(1U)
33078 
33079 #define S_FULLPT1    25
33080 #define V_FULLPT1(x) ((x) << S_FULLPT1)
33081 #define F_FULLPT1    V_FULLPT1(1U)
33082 
33083 #define S_VALIDPT1    24
33084 #define V_VALIDPT1(x) ((x) << S_VALIDPT1)
33085 #define F_VALIDPT1    V_VALIDPT1(1U)
33086 
33087 #define S_DATAPT1    16
33088 #define M_DATAPT1    0xffU
33089 #define V_DATAPT1(x) ((x) << S_DATAPT1)
33090 #define G_DATAPT1(x) (((x) >> S_DATAPT1) & M_DATAPT1)
33091 
33092 #define S_SOPPT0    15
33093 #define V_SOPPT0(x) ((x) << S_SOPPT0)
33094 #define F_SOPPT0    V_SOPPT0(1U)
33095 
33096 #define S_EOPPT0    14
33097 #define V_EOPPT0(x) ((x) << S_EOPPT0)
33098 #define F_EOPPT0    V_EOPPT0(1U)
33099 
33100 #define S_SIZEPT0    11
33101 #define M_SIZEPT0    0x7U
33102 #define V_SIZEPT0(x) ((x) << S_SIZEPT0)
33103 #define G_SIZEPT0(x) (((x) >> S_SIZEPT0) & M_SIZEPT0)
33104 
33105 #define S_ERRPT0    10
33106 #define V_ERRPT0(x) ((x) << S_ERRPT0)
33107 #define F_ERRPT0    V_ERRPT0(1U)
33108 
33109 #define S_FULLPT0    9
33110 #define V_FULLPT0(x) ((x) << S_FULLPT0)
33111 #define F_FULLPT0    V_FULLPT0(1U)
33112 
33113 #define S_VALIDPT0    8
33114 #define V_VALIDPT0(x) ((x) << S_VALIDPT0)
33115 #define F_VALIDPT0    V_VALIDPT0(1U)
33116 
33117 #define S_DATAPT0    0
33118 #define M_DATAPT0    0xffU
33119 #define V_DATAPT0(x) ((x) << S_DATAPT0)
33120 #define G_DATAPT0(x) (((x) >> S_DATAPT0) & M_DATAPT0)
33121 
33122 #define S_T5_SIZEPT1    26
33123 #define M_T5_SIZEPT1    0xfU
33124 #define V_T5_SIZEPT1(x) ((x) << S_T5_SIZEPT1)
33125 #define G_T5_SIZEPT1(x) (((x) >> S_T5_SIZEPT1) & M_T5_SIZEPT1)
33126 
33127 #define S_T5_ERRPT1    25
33128 #define V_T5_ERRPT1(x) ((x) << S_T5_ERRPT1)
33129 #define F_T5_ERRPT1    V_T5_ERRPT1(1U)
33130 
33131 #define S_T5_FULLPT1    24
33132 #define V_T5_FULLPT1(x) ((x) << S_T5_FULLPT1)
33133 #define F_T5_FULLPT1    V_T5_FULLPT1(1U)
33134 
33135 #define S_T5_VALIDPT1    23
33136 #define V_T5_VALIDPT1(x) ((x) << S_T5_VALIDPT1)
33137 #define F_T5_VALIDPT1    V_T5_VALIDPT1(1U)
33138 
33139 #define S_T5_DATAPT1    16
33140 #define M_T5_DATAPT1    0x7fU
33141 #define V_T5_DATAPT1(x) ((x) << S_T5_DATAPT1)
33142 #define G_T5_DATAPT1(x) (((x) >> S_T5_DATAPT1) & M_T5_DATAPT1)
33143 
33144 #define S_T5_SIZEPT0    10
33145 #define M_T5_SIZEPT0    0xfU
33146 #define V_T5_SIZEPT0(x) ((x) << S_T5_SIZEPT0)
33147 #define G_T5_SIZEPT0(x) (((x) >> S_T5_SIZEPT0) & M_T5_SIZEPT0)
33148 
33149 #define S_T5_ERRPT0    9
33150 #define V_T5_ERRPT0(x) ((x) << S_T5_ERRPT0)
33151 #define F_T5_ERRPT0    V_T5_ERRPT0(1U)
33152 
33153 #define S_T5_FULLPT0    8
33154 #define V_T5_FULLPT0(x) ((x) << S_T5_FULLPT0)
33155 #define F_T5_FULLPT0    V_T5_FULLPT0(1U)
33156 
33157 #define S_T5_VALIDPT0    7
33158 #define V_T5_VALIDPT0(x) ((x) << S_T5_VALIDPT0)
33159 #define F_T5_VALIDPT0    V_T5_VALIDPT0(1U)
33160 
33161 #define S_T5_DATAPT0    0
33162 #define M_T5_DATAPT0    0x7fU
33163 #define V_T5_DATAPT0(x) ((x) << S_T5_DATAPT0)
33164 #define G_T5_DATAPT0(x) (((x) >> S_T5_DATAPT0) & M_T5_DATAPT0)
33165 
33166 #define A_MPS_TX_DEBUG_REG_TX2MAC_32 0x9450
33167 
33168 #define S_SOPPT3    31
33169 #define V_SOPPT3(x) ((x) << S_SOPPT3)
33170 #define F_SOPPT3    V_SOPPT3(1U)
33171 
33172 #define S_EOPPT3    30
33173 #define V_EOPPT3(x) ((x) << S_EOPPT3)
33174 #define F_EOPPT3    V_EOPPT3(1U)
33175 
33176 #define S_SIZEPT3    27
33177 #define M_SIZEPT3    0x7U
33178 #define V_SIZEPT3(x) ((x) << S_SIZEPT3)
33179 #define G_SIZEPT3(x) (((x) >> S_SIZEPT3) & M_SIZEPT3)
33180 
33181 #define S_ERRPT3    26
33182 #define V_ERRPT3(x) ((x) << S_ERRPT3)
33183 #define F_ERRPT3    V_ERRPT3(1U)
33184 
33185 #define S_FULLPT3    25
33186 #define V_FULLPT3(x) ((x) << S_FULLPT3)
33187 #define F_FULLPT3    V_FULLPT3(1U)
33188 
33189 #define S_VALIDPT3    24
33190 #define V_VALIDPT3(x) ((x) << S_VALIDPT3)
33191 #define F_VALIDPT3    V_VALIDPT3(1U)
33192 
33193 #define S_DATAPT3    16
33194 #define M_DATAPT3    0xffU
33195 #define V_DATAPT3(x) ((x) << S_DATAPT3)
33196 #define G_DATAPT3(x) (((x) >> S_DATAPT3) & M_DATAPT3)
33197 
33198 #define S_SOPPT2    15
33199 #define V_SOPPT2(x) ((x) << S_SOPPT2)
33200 #define F_SOPPT2    V_SOPPT2(1U)
33201 
33202 #define S_EOPPT2    14
33203 #define V_EOPPT2(x) ((x) << S_EOPPT2)
33204 #define F_EOPPT2    V_EOPPT2(1U)
33205 
33206 #define S_SIZEPT2    11
33207 #define M_SIZEPT2    0x7U
33208 #define V_SIZEPT2(x) ((x) << S_SIZEPT2)
33209 #define G_SIZEPT2(x) (((x) >> S_SIZEPT2) & M_SIZEPT2)
33210 
33211 #define S_ERRPT2    10
33212 #define V_ERRPT2(x) ((x) << S_ERRPT2)
33213 #define F_ERRPT2    V_ERRPT2(1U)
33214 
33215 #define S_FULLPT2    9
33216 #define V_FULLPT2(x) ((x) << S_FULLPT2)
33217 #define F_FULLPT2    V_FULLPT2(1U)
33218 
33219 #define S_VALIDPT2    8
33220 #define V_VALIDPT2(x) ((x) << S_VALIDPT2)
33221 #define F_VALIDPT2    V_VALIDPT2(1U)
33222 
33223 #define S_DATAPT2    0
33224 #define M_DATAPT2    0xffU
33225 #define V_DATAPT2(x) ((x) << S_DATAPT2)
33226 #define G_DATAPT2(x) (((x) >> S_DATAPT2) & M_DATAPT2)
33227 
33228 #define S_T5_SIZEPT3    26
33229 #define M_T5_SIZEPT3    0xfU
33230 #define V_T5_SIZEPT3(x) ((x) << S_T5_SIZEPT3)
33231 #define G_T5_SIZEPT3(x) (((x) >> S_T5_SIZEPT3) & M_T5_SIZEPT3)
33232 
33233 #define S_T5_ERRPT3    25
33234 #define V_T5_ERRPT3(x) ((x) << S_T5_ERRPT3)
33235 #define F_T5_ERRPT3    V_T5_ERRPT3(1U)
33236 
33237 #define S_T5_FULLPT3    24
33238 #define V_T5_FULLPT3(x) ((x) << S_T5_FULLPT3)
33239 #define F_T5_FULLPT3    V_T5_FULLPT3(1U)
33240 
33241 #define S_T5_VALIDPT3    23
33242 #define V_T5_VALIDPT3(x) ((x) << S_T5_VALIDPT3)
33243 #define F_T5_VALIDPT3    V_T5_VALIDPT3(1U)
33244 
33245 #define S_T5_DATAPT3    16
33246 #define M_T5_DATAPT3    0x7fU
33247 #define V_T5_DATAPT3(x) ((x) << S_T5_DATAPT3)
33248 #define G_T5_DATAPT3(x) (((x) >> S_T5_DATAPT3) & M_T5_DATAPT3)
33249 
33250 #define S_T5_SIZEPT2    10
33251 #define M_T5_SIZEPT2    0xfU
33252 #define V_T5_SIZEPT2(x) ((x) << S_T5_SIZEPT2)
33253 #define G_T5_SIZEPT2(x) (((x) >> S_T5_SIZEPT2) & M_T5_SIZEPT2)
33254 
33255 #define S_T5_ERRPT2    9
33256 #define V_T5_ERRPT2(x) ((x) << S_T5_ERRPT2)
33257 #define F_T5_ERRPT2    V_T5_ERRPT2(1U)
33258 
33259 #define S_T5_FULLPT2    8
33260 #define V_T5_FULLPT2(x) ((x) << S_T5_FULLPT2)
33261 #define F_T5_FULLPT2    V_T5_FULLPT2(1U)
33262 
33263 #define S_T5_VALIDPT2    7
33264 #define V_T5_VALIDPT2(x) ((x) << S_T5_VALIDPT2)
33265 #define F_T5_VALIDPT2    V_T5_VALIDPT2(1U)
33266 
33267 #define S_T5_DATAPT2    0
33268 #define M_T5_DATAPT2    0x7fU
33269 #define V_T5_DATAPT2(x) ((x) << S_T5_DATAPT2)
33270 #define G_T5_DATAPT2(x) (((x) >> S_T5_DATAPT2) & M_T5_DATAPT2)
33271 
33272 #define A_MPS_TX_SGE_CH_PAUSE_IGNR 0x9454
33273 
33274 #define S_SGEPAUSEIGNR    0
33275 #define M_SGEPAUSEIGNR    0xfU
33276 #define V_SGEPAUSEIGNR(x) ((x) << S_SGEPAUSEIGNR)
33277 #define G_SGEPAUSEIGNR(x) (((x) >> S_SGEPAUSEIGNR) & M_SGEPAUSEIGNR)
33278 
33279 #define A_MPS_T5_TX_SGE_CH_PAUSE_IGNR 0x9454
33280 
33281 #define S_T5SGEPAUSEIGNR    0
33282 #define M_T5SGEPAUSEIGNR    0xffffU
33283 #define V_T5SGEPAUSEIGNR(x) ((x) << S_T5SGEPAUSEIGNR)
33284 #define G_T5SGEPAUSEIGNR(x) (((x) >> S_T5SGEPAUSEIGNR) & M_T5SGEPAUSEIGNR)
33285 
33286 #define A_MPS_TX_DEBUG_SUBPART_SEL 0x9458
33287 
33288 #define S_SUBPRTH    11
33289 #define M_SUBPRTH    0x1fU
33290 #define V_SUBPRTH(x) ((x) << S_SUBPRTH)
33291 #define G_SUBPRTH(x) (((x) >> S_SUBPRTH) & M_SUBPRTH)
33292 
33293 #define S_PORTH    8
33294 #define M_PORTH    0x7U
33295 #define V_PORTH(x) ((x) << S_PORTH)
33296 #define G_PORTH(x) (((x) >> S_PORTH) & M_PORTH)
33297 
33298 #define S_SUBPRTL    3
33299 #define M_SUBPRTL    0x1fU
33300 #define V_SUBPRTL(x) ((x) << S_SUBPRTL)
33301 #define G_SUBPRTL(x) (((x) >> S_SUBPRTL) & M_SUBPRTL)
33302 
33303 #define S_PORTL    0
33304 #define M_PORTL    0x7U
33305 #define V_PORTL(x) ((x) << S_PORTL)
33306 #define G_PORTL(x) (((x) >> S_PORTL) & M_PORTL)
33307 
33308 #define A_MPS_TX_PAD_CTL 0x945c
33309 
33310 #define S_LPBKPADENPT3    7
33311 #define V_LPBKPADENPT3(x) ((x) << S_LPBKPADENPT3)
33312 #define F_LPBKPADENPT3    V_LPBKPADENPT3(1U)
33313 
33314 #define S_LPBKPADENPT2    6
33315 #define V_LPBKPADENPT2(x) ((x) << S_LPBKPADENPT2)
33316 #define F_LPBKPADENPT2    V_LPBKPADENPT2(1U)
33317 
33318 #define S_LPBKPADENPT1    5
33319 #define V_LPBKPADENPT1(x) ((x) << S_LPBKPADENPT1)
33320 #define F_LPBKPADENPT1    V_LPBKPADENPT1(1U)
33321 
33322 #define S_LPBKPADENPT0    4
33323 #define V_LPBKPADENPT0(x) ((x) << S_LPBKPADENPT0)
33324 #define F_LPBKPADENPT0    V_LPBKPADENPT0(1U)
33325 
33326 #define S_MACPADENPT3    3
33327 #define V_MACPADENPT3(x) ((x) << S_MACPADENPT3)
33328 #define F_MACPADENPT3    V_MACPADENPT3(1U)
33329 
33330 #define S_MACPADENPT2    2
33331 #define V_MACPADENPT2(x) ((x) << S_MACPADENPT2)
33332 #define F_MACPADENPT2    V_MACPADENPT2(1U)
33333 
33334 #define S_MACPADENPT1    1
33335 #define V_MACPADENPT1(x) ((x) << S_MACPADENPT1)
33336 #define F_MACPADENPT1    V_MACPADENPT1(1U)
33337 
33338 #define S_MACPADENPT0    0
33339 #define V_MACPADENPT0(x) ((x) << S_MACPADENPT0)
33340 #define F_MACPADENPT0    V_MACPADENPT0(1U)
33341 
33342 #define A_MPS_TX_PFVF_PORT_DROP_TP 0x9460
33343 
33344 #define S_TP2MPS_CH3    24
33345 #define M_TP2MPS_CH3    0xffU
33346 #define V_TP2MPS_CH3(x) ((x) << S_TP2MPS_CH3)
33347 #define G_TP2MPS_CH3(x) (((x) >> S_TP2MPS_CH3) & M_TP2MPS_CH3)
33348 
33349 #define S_TP2MPS_CH2    16
33350 #define M_TP2MPS_CH2    0xffU
33351 #define V_TP2MPS_CH2(x) ((x) << S_TP2MPS_CH2)
33352 #define G_TP2MPS_CH2(x) (((x) >> S_TP2MPS_CH2) & M_TP2MPS_CH2)
33353 
33354 #define S_TP2MPS_CH1    8
33355 #define M_TP2MPS_CH1    0xffU
33356 #define V_TP2MPS_CH1(x) ((x) << S_TP2MPS_CH1)
33357 #define G_TP2MPS_CH1(x) (((x) >> S_TP2MPS_CH1) & M_TP2MPS_CH1)
33358 
33359 #define S_TP2MPS_CH0    0
33360 #define M_TP2MPS_CH0    0xffU
33361 #define V_TP2MPS_CH0(x) ((x) << S_TP2MPS_CH0)
33362 #define G_TP2MPS_CH0(x) (((x) >> S_TP2MPS_CH0) & M_TP2MPS_CH0)
33363 
33364 #define A_MPS_TX_PFVF_PORT_DROP_NCSI 0x9464
33365 
33366 #define S_NCSI_CH4    0
33367 #define M_NCSI_CH4    0xffU
33368 #define V_NCSI_CH4(x) ((x) << S_NCSI_CH4)
33369 #define G_NCSI_CH4(x) (((x) >> S_NCSI_CH4) & M_NCSI_CH4)
33370 
33371 #define A_MPS_TX_PFVF_PORT_DROP_CTL 0x9468
33372 
33373 #define S_PFNOVFDROP    5
33374 #define V_PFNOVFDROP(x) ((x) << S_PFNOVFDROP)
33375 #define F_PFNOVFDROP    V_PFNOVFDROP(1U)
33376 
33377 #define S_NCSI_CH4_CLR    4
33378 #define V_NCSI_CH4_CLR(x) ((x) << S_NCSI_CH4_CLR)
33379 #define F_NCSI_CH4_CLR    V_NCSI_CH4_CLR(1U)
33380 
33381 #define S_TP2MPS_CH3_CLR    3
33382 #define V_TP2MPS_CH3_CLR(x) ((x) << S_TP2MPS_CH3_CLR)
33383 #define F_TP2MPS_CH3_CLR    V_TP2MPS_CH3_CLR(1U)
33384 
33385 #define S_TP2MPS_CH2_CLR    2
33386 #define V_TP2MPS_CH2_CLR(x) ((x) << S_TP2MPS_CH2_CLR)
33387 #define F_TP2MPS_CH2_CLR    V_TP2MPS_CH2_CLR(1U)
33388 
33389 #define S_TP2MPS_CH1_CLR    1
33390 #define V_TP2MPS_CH1_CLR(x) ((x) << S_TP2MPS_CH1_CLR)
33391 #define F_TP2MPS_CH1_CLR    V_TP2MPS_CH1_CLR(1U)
33392 
33393 #define S_TP2MPS_CH0_CLR    0
33394 #define V_TP2MPS_CH0_CLR(x) ((x) << S_TP2MPS_CH0_CLR)
33395 #define F_TP2MPS_CH0_CLR    V_TP2MPS_CH0_CLR(1U)
33396 
33397 #define A_MPS_TX_CGEN 0x946c
33398 
33399 #define S_TXOUTLPBK3_CGEN    31
33400 #define V_TXOUTLPBK3_CGEN(x) ((x) << S_TXOUTLPBK3_CGEN)
33401 #define F_TXOUTLPBK3_CGEN    V_TXOUTLPBK3_CGEN(1U)
33402 
33403 #define S_TXOUTLPBK2_CGEN    30
33404 #define V_TXOUTLPBK2_CGEN(x) ((x) << S_TXOUTLPBK2_CGEN)
33405 #define F_TXOUTLPBK2_CGEN    V_TXOUTLPBK2_CGEN(1U)
33406 
33407 #define S_TXOUTLPBK1_CGEN    29
33408 #define V_TXOUTLPBK1_CGEN(x) ((x) << S_TXOUTLPBK1_CGEN)
33409 #define F_TXOUTLPBK1_CGEN    V_TXOUTLPBK1_CGEN(1U)
33410 
33411 #define S_TXOUTLPBK0_CGEN    28
33412 #define V_TXOUTLPBK0_CGEN(x) ((x) << S_TXOUTLPBK0_CGEN)
33413 #define F_TXOUTLPBK0_CGEN    V_TXOUTLPBK0_CGEN(1U)
33414 
33415 #define S_TXOUTMAC3_CGEN    27
33416 #define V_TXOUTMAC3_CGEN(x) ((x) << S_TXOUTMAC3_CGEN)
33417 #define F_TXOUTMAC3_CGEN    V_TXOUTMAC3_CGEN(1U)
33418 
33419 #define S_TXOUTMAC2_CGEN    26
33420 #define V_TXOUTMAC2_CGEN(x) ((x) << S_TXOUTMAC2_CGEN)
33421 #define F_TXOUTMAC2_CGEN    V_TXOUTMAC2_CGEN(1U)
33422 
33423 #define S_TXOUTMAC1_CGEN    25
33424 #define V_TXOUTMAC1_CGEN(x) ((x) << S_TXOUTMAC1_CGEN)
33425 #define F_TXOUTMAC1_CGEN    V_TXOUTMAC1_CGEN(1U)
33426 
33427 #define S_TXOUTMAC0_CGEN    24
33428 #define V_TXOUTMAC0_CGEN(x) ((x) << S_TXOUTMAC0_CGEN)
33429 #define F_TXOUTMAC0_CGEN    V_TXOUTMAC0_CGEN(1U)
33430 
33431 #define S_TXSCHLPBK3_CGEN    23
33432 #define V_TXSCHLPBK3_CGEN(x) ((x) << S_TXSCHLPBK3_CGEN)
33433 #define F_TXSCHLPBK3_CGEN    V_TXSCHLPBK3_CGEN(1U)
33434 
33435 #define S_TXSCHLPBK2_CGEN    22
33436 #define V_TXSCHLPBK2_CGEN(x) ((x) << S_TXSCHLPBK2_CGEN)
33437 #define F_TXSCHLPBK2_CGEN    V_TXSCHLPBK2_CGEN(1U)
33438 
33439 #define S_TXSCHLPBK1_CGEN    21
33440 #define V_TXSCHLPBK1_CGEN(x) ((x) << S_TXSCHLPBK1_CGEN)
33441 #define F_TXSCHLPBK1_CGEN    V_TXSCHLPBK1_CGEN(1U)
33442 
33443 #define S_TXSCHLPBK0_CGEN    20
33444 #define V_TXSCHLPBK0_CGEN(x) ((x) << S_TXSCHLPBK0_CGEN)
33445 #define F_TXSCHLPBK0_CGEN    V_TXSCHLPBK0_CGEN(1U)
33446 
33447 #define S_TXSCHMAC3_CGEN    19
33448 #define V_TXSCHMAC3_CGEN(x) ((x) << S_TXSCHMAC3_CGEN)
33449 #define F_TXSCHMAC3_CGEN    V_TXSCHMAC3_CGEN(1U)
33450 
33451 #define S_TXSCHMAC2_CGEN    18
33452 #define V_TXSCHMAC2_CGEN(x) ((x) << S_TXSCHMAC2_CGEN)
33453 #define F_TXSCHMAC2_CGEN    V_TXSCHMAC2_CGEN(1U)
33454 
33455 #define S_TXSCHMAC1_CGEN    17
33456 #define V_TXSCHMAC1_CGEN(x) ((x) << S_TXSCHMAC1_CGEN)
33457 #define F_TXSCHMAC1_CGEN    V_TXSCHMAC1_CGEN(1U)
33458 
33459 #define S_TXSCHMAC0_CGEN    16
33460 #define V_TXSCHMAC0_CGEN(x) ((x) << S_TXSCHMAC0_CGEN)
33461 #define F_TXSCHMAC0_CGEN    V_TXSCHMAC0_CGEN(1U)
33462 
33463 #define S_TXINCH4_CGEN    15
33464 #define V_TXINCH4_CGEN(x) ((x) << S_TXINCH4_CGEN)
33465 #define F_TXINCH4_CGEN    V_TXINCH4_CGEN(1U)
33466 
33467 #define S_TXINCH3_CGEN    14
33468 #define V_TXINCH3_CGEN(x) ((x) << S_TXINCH3_CGEN)
33469 #define F_TXINCH3_CGEN    V_TXINCH3_CGEN(1U)
33470 
33471 #define S_TXINCH2_CGEN    13
33472 #define V_TXINCH2_CGEN(x) ((x) << S_TXINCH2_CGEN)
33473 #define F_TXINCH2_CGEN    V_TXINCH2_CGEN(1U)
33474 
33475 #define S_TXINCH1_CGEN    12
33476 #define V_TXINCH1_CGEN(x) ((x) << S_TXINCH1_CGEN)
33477 #define F_TXINCH1_CGEN    V_TXINCH1_CGEN(1U)
33478 
33479 #define S_TXINCH0_CGEN    11
33480 #define V_TXINCH0_CGEN(x) ((x) << S_TXINCH0_CGEN)
33481 #define F_TXINCH0_CGEN    V_TXINCH0_CGEN(1U)
33482 
33483 #define A_MPS_TX_CGEN_DYNAMIC 0x9470
33484 #define A_MPS_STAT_CTL 0x9600
33485 
33486 #define S_COUNTVFINPF    1
33487 #define V_COUNTVFINPF(x) ((x) << S_COUNTVFINPF)
33488 #define F_COUNTVFINPF    V_COUNTVFINPF(1U)
33489 
33490 #define S_LPBKERRSTAT    0
33491 #define V_LPBKERRSTAT(x) ((x) << S_LPBKERRSTAT)
33492 #define F_LPBKERRSTAT    V_LPBKERRSTAT(1U)
33493 
33494 #define S_STATSTOPCTRL    10
33495 #define V_STATSTOPCTRL(x) ((x) << S_STATSTOPCTRL)
33496 #define F_STATSTOPCTRL    V_STATSTOPCTRL(1U)
33497 
33498 #define S_STOPSTAT    9
33499 #define V_STOPSTAT(x) ((x) << S_STOPSTAT)
33500 #define F_STOPSTAT    V_STOPSTAT(1U)
33501 
33502 #define S_STATWRITECTRL    8
33503 #define V_STATWRITECTRL(x) ((x) << S_STATWRITECTRL)
33504 #define F_STATWRITECTRL    V_STATWRITECTRL(1U)
33505 
33506 #define S_COUNTLBPF    7
33507 #define V_COUNTLBPF(x) ((x) << S_COUNTLBPF)
33508 #define F_COUNTLBPF    V_COUNTLBPF(1U)
33509 
33510 #define S_COUNTLBVF    6
33511 #define V_COUNTLBVF(x) ((x) << S_COUNTLBVF)
33512 #define F_COUNTLBVF    V_COUNTLBVF(1U)
33513 
33514 #define S_COUNTPAUSEMCRX    5
33515 #define V_COUNTPAUSEMCRX(x) ((x) << S_COUNTPAUSEMCRX)
33516 #define F_COUNTPAUSEMCRX    V_COUNTPAUSEMCRX(1U)
33517 
33518 #define S_COUNTPAUSESTATRX    4
33519 #define V_COUNTPAUSESTATRX(x) ((x) << S_COUNTPAUSESTATRX)
33520 #define F_COUNTPAUSESTATRX    V_COUNTPAUSESTATRX(1U)
33521 
33522 #define S_COUNTPAUSEMCTX    3
33523 #define V_COUNTPAUSEMCTX(x) ((x) << S_COUNTPAUSEMCTX)
33524 #define F_COUNTPAUSEMCTX    V_COUNTPAUSEMCTX(1U)
33525 
33526 #define S_COUNTPAUSESTATTX    2
33527 #define V_COUNTPAUSESTATTX(x) ((x) << S_COUNTPAUSESTATTX)
33528 #define F_COUNTPAUSESTATTX    V_COUNTPAUSESTATTX(1U)
33529 
33530 #define A_MPS_STAT_INT_ENABLE 0x9608
33531 
33532 #define S_PLREADSYNCERR    0
33533 #define V_PLREADSYNCERR(x) ((x) << S_PLREADSYNCERR)
33534 #define F_PLREADSYNCERR    V_PLREADSYNCERR(1U)
33535 
33536 #define A_MPS_STAT_INT_CAUSE 0x960c
33537 #define A_MPS_STAT_PERR_INT_ENABLE_SRAM 0x9610
33538 
33539 #define S_RXBG    20
33540 #define V_RXBG(x) ((x) << S_RXBG)
33541 #define F_RXBG    V_RXBG(1U)
33542 
33543 #define S_RXVF    18
33544 #define M_RXVF    0x3U
33545 #define V_RXVF(x) ((x) << S_RXVF)
33546 #define G_RXVF(x) (((x) >> S_RXVF) & M_RXVF)
33547 
33548 #define S_TXVF    16
33549 #define M_TXVF    0x3U
33550 #define V_TXVF(x) ((x) << S_TXVF)
33551 #define G_TXVF(x) (((x) >> S_TXVF) & M_TXVF)
33552 
33553 #define S_RXPF    13
33554 #define M_RXPF    0x7U
33555 #define V_RXPF(x) ((x) << S_RXPF)
33556 #define G_RXPF(x) (((x) >> S_RXPF) & M_RXPF)
33557 
33558 #define S_TXPF    11
33559 #define M_TXPF    0x3U
33560 #define V_TXPF(x) ((x) << S_TXPF)
33561 #define G_TXPF(x) (((x) >> S_TXPF) & M_TXPF)
33562 
33563 #define S_RXPORT    7
33564 #define M_RXPORT    0xfU
33565 #define V_RXPORT(x) ((x) << S_RXPORT)
33566 #define G_RXPORT(x) (((x) >> S_RXPORT) & M_RXPORT)
33567 
33568 #define S_LBPORT    4
33569 #define M_LBPORT    0x7U
33570 #define V_LBPORT(x) ((x) << S_LBPORT)
33571 #define G_LBPORT(x) (((x) >> S_LBPORT) & M_LBPORT)
33572 
33573 #define S_TXPORT    0
33574 #define M_TXPORT    0xfU
33575 #define V_TXPORT(x) ((x) << S_TXPORT)
33576 #define G_TXPORT(x) (((x) >> S_TXPORT) & M_TXPORT)
33577 
33578 #define S_T5_RXBG    27
33579 #define M_T5_RXBG    0x3U
33580 #define V_T5_RXBG(x) ((x) << S_T5_RXBG)
33581 #define G_T5_RXBG(x) (((x) >> S_T5_RXBG) & M_T5_RXBG)
33582 
33583 #define S_T5_RXPF    22
33584 #define M_T5_RXPF    0x1fU
33585 #define V_T5_RXPF(x) ((x) << S_T5_RXPF)
33586 #define G_T5_RXPF(x) (((x) >> S_T5_RXPF) & M_T5_RXPF)
33587 
33588 #define S_T5_TXPF    18
33589 #define M_T5_TXPF    0xfU
33590 #define V_T5_TXPF(x) ((x) << S_T5_TXPF)
33591 #define G_T5_TXPF(x) (((x) >> S_T5_TXPF) & M_T5_TXPF)
33592 
33593 #define S_T5_RXPORT    11
33594 #define M_T5_RXPORT    0x7fU
33595 #define V_T5_RXPORT(x) ((x) << S_T5_RXPORT)
33596 #define G_T5_RXPORT(x) (((x) >> S_T5_RXPORT) & M_T5_RXPORT)
33597 
33598 #define S_T5_LBPORT    6
33599 #define M_T5_LBPORT    0x1fU
33600 #define V_T5_LBPORT(x) ((x) << S_T5_LBPORT)
33601 #define G_T5_LBPORT(x) (((x) >> S_T5_LBPORT) & M_T5_LBPORT)
33602 
33603 #define S_T5_TXPORT    0
33604 #define M_T5_TXPORT    0x3fU
33605 #define V_T5_TXPORT(x) ((x) << S_T5_TXPORT)
33606 #define G_T5_TXPORT(x) (((x) >> S_T5_TXPORT) & M_T5_TXPORT)
33607 
33608 #define A_MPS_STAT_PERR_INT_CAUSE_SRAM 0x9614
33609 #define A_MPS_STAT_PERR_ENABLE_SRAM 0x9618
33610 #define A_MPS_STAT_PERR_INT_ENABLE_TX_FIFO 0x961c
33611 
33612 #define S_TX    12
33613 #define M_TX    0xffU
33614 #define V_TX(x) ((x) << S_TX)
33615 #define G_TX(x) (((x) >> S_TX) & M_TX)
33616 
33617 #define S_TXPAUSEFIFO    8
33618 #define M_TXPAUSEFIFO    0xfU
33619 #define V_TXPAUSEFIFO(x) ((x) << S_TXPAUSEFIFO)
33620 #define G_TXPAUSEFIFO(x) (((x) >> S_TXPAUSEFIFO) & M_TXPAUSEFIFO)
33621 
33622 #define S_DROP    0
33623 #define M_DROP    0xffU
33624 #define V_DROP(x) ((x) << S_DROP)
33625 #define G_DROP(x) (((x) >> S_DROP) & M_DROP)
33626 
33627 #define S_TXCH    20
33628 #define M_TXCH    0xfU
33629 #define V_TXCH(x) ((x) << S_TXCH)
33630 #define G_TXCH(x) (((x) >> S_TXCH) & M_TXCH)
33631 
33632 #define A_MPS_STAT_PERR_INT_CAUSE_TX_FIFO 0x9620
33633 #define A_MPS_STAT_PERR_ENABLE_TX_FIFO 0x9624
33634 #define A_MPS_STAT_PERR_INT_ENABLE_RX_FIFO 0x9628
33635 
33636 #define S_PAUSEFIFO    20
33637 #define M_PAUSEFIFO    0xfU
33638 #define V_PAUSEFIFO(x) ((x) << S_PAUSEFIFO)
33639 #define G_PAUSEFIFO(x) (((x) >> S_PAUSEFIFO) & M_PAUSEFIFO)
33640 
33641 #define S_LPBK    16
33642 #define M_LPBK    0xfU
33643 #define V_LPBK(x) ((x) << S_LPBK)
33644 #define G_LPBK(x) (((x) >> S_LPBK) & M_LPBK)
33645 
33646 #define S_NQ    8
33647 #define M_NQ    0xffU
33648 #define V_NQ(x) ((x) << S_NQ)
33649 #define G_NQ(x) (((x) >> S_NQ) & M_NQ)
33650 
33651 #define S_PV    4
33652 #define M_PV    0xfU
33653 #define V_PV(x) ((x) << S_PV)
33654 #define G_PV(x) (((x) >> S_PV) & M_PV)
33655 
33656 #define S_MAC    0
33657 #define M_MAC    0xfU
33658 #define V_MAC(x) ((x) << S_MAC)
33659 #define G_MAC(x) (((x) >> S_MAC) & M_MAC)
33660 
33661 #define A_MPS_STAT_PERR_INT_CAUSE_RX_FIFO 0x962c
33662 #define A_MPS_STAT_PERR_ENABLE_RX_FIFO 0x9630
33663 #define A_MPS_STAT_PERR_INJECT 0x9634
33664 
33665 #define S_STATMEMSEL    1
33666 #define M_STATMEMSEL    0x7fU
33667 #define V_STATMEMSEL(x) ((x) << S_STATMEMSEL)
33668 #define G_STATMEMSEL(x) (((x) >> S_STATMEMSEL) & M_STATMEMSEL)
33669 
33670 #define A_MPS_STAT_DEBUG_SUB_SEL 0x9638
33671 
33672 #define S_STATSSUBPRTH    5
33673 #define M_STATSSUBPRTH    0x1fU
33674 #define V_STATSSUBPRTH(x) ((x) << S_STATSSUBPRTH)
33675 #define G_STATSSUBPRTH(x) (((x) >> S_STATSSUBPRTH) & M_STATSSUBPRTH)
33676 
33677 #define S_STATSSUBPRTL    0
33678 #define M_STATSSUBPRTL    0x1fU
33679 #define V_STATSSUBPRTL(x) ((x) << S_STATSSUBPRTL)
33680 #define G_STATSSUBPRTL(x) (((x) >> S_STATSSUBPRTL) & M_STATSSUBPRTL)
33681 
33682 #define S_STATSUBPRTH    5
33683 #define M_STATSUBPRTH    0x1fU
33684 #define V_STATSUBPRTH(x) ((x) << S_STATSUBPRTH)
33685 #define G_STATSUBPRTH(x) (((x) >> S_STATSUBPRTH) & M_STATSUBPRTH)
33686 
33687 #define A_MPS_STAT_RX_BG_0_MAC_DROP_FRAME_L 0x9640
33688 #define A_MPS_STAT_RX_BG_0_MAC_DROP_FRAME_H 0x9644
33689 #define A_MPS_STAT_RX_BG_1_MAC_DROP_FRAME_L 0x9648
33690 #define A_MPS_STAT_RX_BG_1_MAC_DROP_FRAME_H 0x964c
33691 #define A_MPS_STAT_RX_BG_2_MAC_DROP_FRAME_L 0x9650
33692 #define A_MPS_STAT_RX_BG_2_MAC_DROP_FRAME_H 0x9654
33693 #define A_MPS_STAT_RX_BG_3_MAC_DROP_FRAME_L 0x9658
33694 #define A_MPS_STAT_RX_BG_3_MAC_DROP_FRAME_H 0x965c
33695 #define A_MPS_STAT_RX_BG_0_LB_DROP_FRAME_L 0x9660
33696 #define A_MPS_STAT_RX_BG_0_LB_DROP_FRAME_H 0x9664
33697 #define A_MPS_STAT_RX_BG_1_LB_DROP_FRAME_L 0x9668
33698 #define A_MPS_STAT_RX_BG_1_LB_DROP_FRAME_H 0x966c
33699 #define A_MPS_STAT_RX_BG_2_LB_DROP_FRAME_L 0x9670
33700 #define A_MPS_STAT_RX_BG_2_LB_DROP_FRAME_H 0x9674
33701 #define A_MPS_STAT_RX_BG_3_LB_DROP_FRAME_L 0x9678
33702 #define A_MPS_STAT_RX_BG_3_LB_DROP_FRAME_H 0x967c
33703 #define A_MPS_STAT_RX_BG_0_MAC_TRUNC_FRAME_L 0x9680
33704 #define A_MPS_STAT_RX_BG_0_MAC_TRUNC_FRAME_H 0x9684
33705 #define A_MPS_STAT_RX_BG_1_MAC_TRUNC_FRAME_L 0x9688
33706 #define A_MPS_STAT_RX_BG_1_MAC_TRUNC_FRAME_H 0x968c
33707 #define A_MPS_STAT_RX_BG_2_MAC_TRUNC_FRAME_L 0x9690
33708 #define A_MPS_STAT_RX_BG_2_MAC_TRUNC_FRAME_H 0x9694
33709 #define A_MPS_STAT_RX_BG_3_MAC_TRUNC_FRAME_L 0x9698
33710 #define A_MPS_STAT_RX_BG_3_MAC_TRUNC_FRAME_H 0x969c
33711 #define A_MPS_STAT_RX_BG_0_LB_TRUNC_FRAME_L 0x96a0
33712 #define A_MPS_STAT_RX_BG_0_LB_TRUNC_FRAME_H 0x96a4
33713 #define A_MPS_STAT_RX_BG_1_LB_TRUNC_FRAME_L 0x96a8
33714 #define A_MPS_STAT_RX_BG_1_LB_TRUNC_FRAME_H 0x96ac
33715 #define A_MPS_STAT_RX_BG_2_LB_TRUNC_FRAME_L 0x96b0
33716 #define A_MPS_STAT_RX_BG_2_LB_TRUNC_FRAME_H 0x96b4
33717 #define A_MPS_STAT_RX_BG_3_LB_TRUNC_FRAME_L 0x96b8
33718 #define A_MPS_STAT_RX_BG_3_LB_TRUNC_FRAME_H 0x96bc
33719 #define A_MPS_STAT_PERR_INT_ENABLE_SRAM1 0x96c0
33720 
33721 #define S_T5_RXVF    5
33722 #define M_T5_RXVF    0x7U
33723 #define V_T5_RXVF(x) ((x) << S_T5_RXVF)
33724 #define G_T5_RXVF(x) (((x) >> S_T5_RXVF) & M_T5_RXVF)
33725 
33726 #define S_T5_TXVF    0
33727 #define M_T5_TXVF    0x1fU
33728 #define V_T5_TXVF(x) ((x) << S_T5_TXVF)
33729 #define G_T5_TXVF(x) (((x) >> S_T5_TXVF) & M_T5_TXVF)
33730 
33731 #define A_MPS_STAT_PERR_INT_CAUSE_SRAM1 0x96c4
33732 #define A_MPS_STAT_PERR_ENABLE_SRAM1 0x96c8
33733 #define A_MPS_STAT_STOP_UPD_BG 0x96cc
33734 
33735 #define S_BGRX    0
33736 #define M_BGRX    0xfU
33737 #define V_BGRX(x) ((x) << S_BGRX)
33738 #define G_BGRX(x) (((x) >> S_BGRX) & M_BGRX)
33739 
33740 #define A_MPS_STAT_STOP_UPD_PORT 0x96d0
33741 
33742 #define S_PTLPBK    8
33743 #define M_PTLPBK    0xfU
33744 #define V_PTLPBK(x) ((x) << S_PTLPBK)
33745 #define G_PTLPBK(x) (((x) >> S_PTLPBK) & M_PTLPBK)
33746 
33747 #define S_PTTX    4
33748 #define M_PTTX    0xfU
33749 #define V_PTTX(x) ((x) << S_PTTX)
33750 #define G_PTTX(x) (((x) >> S_PTTX) & M_PTTX)
33751 
33752 #define S_PTRX    0
33753 #define M_PTRX    0xfU
33754 #define V_PTRX(x) ((x) << S_PTRX)
33755 #define G_PTRX(x) (((x) >> S_PTRX) & M_PTRX)
33756 
33757 #define A_MPS_STAT_STOP_UPD_PF 0x96d4
33758 
33759 #define S_PFTX    8
33760 #define M_PFTX    0xffU
33761 #define V_PFTX(x) ((x) << S_PFTX)
33762 #define G_PFTX(x) (((x) >> S_PFTX) & M_PFTX)
33763 
33764 #define S_PFRX    0
33765 #define M_PFRX    0xffU
33766 #define V_PFRX(x) ((x) << S_PFRX)
33767 #define G_PFRX(x) (((x) >> S_PFRX) & M_PFRX)
33768 
33769 #define A_MPS_STAT_STOP_UPD_TX_VF_0_31 0x96d8
33770 #define A_MPS_STAT_STOP_UPD_TX_VF_32_63 0x96dc
33771 #define A_MPS_STAT_STOP_UPD_TX_VF_64_95 0x96e0
33772 #define A_MPS_STAT_STOP_UPD_TX_VF_96_127 0x96e4
33773 #define A_MPS_STAT_STOP_UPD_RX_VF_0_31 0x96e8
33774 #define A_MPS_STAT_STOP_UPD_RX_VF_32_63 0x96ec
33775 #define A_MPS_STAT_STOP_UPD_RX_VF_64_95 0x96f0
33776 #define A_MPS_STAT_STOP_UPD_RX_VF_96_127 0x96f4
33777 #define A_MPS_STAT_STOP_UPD_RX_VF_128_159 0x96f8
33778 #define A_MPS_STAT_STOP_UPD_RX_VF_160_191 0x96fc
33779 #define A_MPS_STAT_STOP_UPD_RX_VF_192_223 0x9700
33780 #define A_MPS_STAT_STOP_UPD_RX_VF_224_255 0x9704
33781 #define A_MPS_STAT_STOP_UPD_TX_VF_128_159 0x9710
33782 #define A_MPS_STAT_STOP_UPD_TX_VF_160_191 0x9714
33783 #define A_MPS_STAT_STOP_UPD_TX_VF_192_223 0x9718
33784 #define A_MPS_STAT_STOP_UPD_TX_VF_224_255 0x971c
33785 #define A_MPS_TRC_CFG 0x9800
33786 
33787 #define S_TRCFIFOEMPTY    4
33788 #define V_TRCFIFOEMPTY(x) ((x) << S_TRCFIFOEMPTY)
33789 #define F_TRCFIFOEMPTY    V_TRCFIFOEMPTY(1U)
33790 
33791 #define S_TRCIGNOREDROPINPUT    3
33792 #define V_TRCIGNOREDROPINPUT(x) ((x) << S_TRCIGNOREDROPINPUT)
33793 #define F_TRCIGNOREDROPINPUT    V_TRCIGNOREDROPINPUT(1U)
33794 
33795 #define S_TRCKEEPDUPLICATES    2
33796 #define V_TRCKEEPDUPLICATES(x) ((x) << S_TRCKEEPDUPLICATES)
33797 #define F_TRCKEEPDUPLICATES    V_TRCKEEPDUPLICATES(1U)
33798 
33799 #define S_TRCEN    1
33800 #define V_TRCEN(x) ((x) << S_TRCEN)
33801 #define F_TRCEN    V_TRCEN(1U)
33802 
33803 #define S_TRCMULTIFILTER    0
33804 #define V_TRCMULTIFILTER(x) ((x) << S_TRCMULTIFILTER)
33805 #define F_TRCMULTIFILTER    V_TRCMULTIFILTER(1U)
33806 
33807 #define S_TRCMULTIRSSFILTER    5
33808 #define V_TRCMULTIRSSFILTER(x) ((x) << S_TRCMULTIRSSFILTER)
33809 #define F_TRCMULTIRSSFILTER    V_TRCMULTIRSSFILTER(1U)
33810 
33811 #define A_MPS_TRC_RSS_HASH 0x9804
33812 #define A_MPS_TRC_FILTER0_RSS_HASH 0x9804
33813 #define A_MPS_TRC_RSS_CONTROL 0x9808
33814 
33815 #define S_RSSCONTROL    16
33816 #define M_RSSCONTROL    0xffU
33817 #define V_RSSCONTROL(x) ((x) << S_RSSCONTROL)
33818 #define G_RSSCONTROL(x) (((x) >> S_RSSCONTROL) & M_RSSCONTROL)
33819 
33820 #define S_QUEUENUMBER    0
33821 #define M_QUEUENUMBER    0xffffU
33822 #define V_QUEUENUMBER(x) ((x) << S_QUEUENUMBER)
33823 #define G_QUEUENUMBER(x) (((x) >> S_QUEUENUMBER) & M_QUEUENUMBER)
33824 
33825 #define A_MPS_TRC_FILTER0_RSS_CONTROL 0x9808
33826 #define A_MPS_TRC_FILTER_MATCH_CTL_A 0x9810
33827 
33828 #define S_TFINVERTMATCH    24
33829 #define V_TFINVERTMATCH(x) ((x) << S_TFINVERTMATCH)
33830 #define F_TFINVERTMATCH    V_TFINVERTMATCH(1U)
33831 
33832 #define S_TFPKTTOOLARGE    23
33833 #define V_TFPKTTOOLARGE(x) ((x) << S_TFPKTTOOLARGE)
33834 #define F_TFPKTTOOLARGE    V_TFPKTTOOLARGE(1U)
33835 
33836 #define S_TFEN    22
33837 #define V_TFEN(x) ((x) << S_TFEN)
33838 #define F_TFEN    V_TFEN(1U)
33839 
33840 #define S_TFPORT    18
33841 #define M_TFPORT    0xfU
33842 #define V_TFPORT(x) ((x) << S_TFPORT)
33843 #define G_TFPORT(x) (((x) >> S_TFPORT) & M_TFPORT)
33844 
33845 #define S_TFDROP    17
33846 #define V_TFDROP(x) ((x) << S_TFDROP)
33847 #define F_TFDROP    V_TFDROP(1U)
33848 
33849 #define S_TFSOPEOPERR    16
33850 #define V_TFSOPEOPERR(x) ((x) << S_TFSOPEOPERR)
33851 #define F_TFSOPEOPERR    V_TFSOPEOPERR(1U)
33852 
33853 #define S_TFLENGTH    8
33854 #define M_TFLENGTH    0x1fU
33855 #define V_TFLENGTH(x) ((x) << S_TFLENGTH)
33856 #define G_TFLENGTH(x) (((x) >> S_TFLENGTH) & M_TFLENGTH)
33857 
33858 #define S_TFOFFSET    0
33859 #define M_TFOFFSET    0x1fU
33860 #define V_TFOFFSET(x) ((x) << S_TFOFFSET)
33861 #define G_TFOFFSET(x) (((x) >> S_TFOFFSET) & M_TFOFFSET)
33862 
33863 #define S_TFINSERTACTLEN    27
33864 #define V_TFINSERTACTLEN(x) ((x) << S_TFINSERTACTLEN)
33865 #define F_TFINSERTACTLEN    V_TFINSERTACTLEN(1U)
33866 
33867 #define S_TFINSERTTIMER    26
33868 #define V_TFINSERTTIMER(x) ((x) << S_TFINSERTTIMER)
33869 #define F_TFINSERTTIMER    V_TFINSERTTIMER(1U)
33870 
33871 #define S_T5_TFINVERTMATCH    25
33872 #define V_T5_TFINVERTMATCH(x) ((x) << S_T5_TFINVERTMATCH)
33873 #define F_T5_TFINVERTMATCH    V_T5_TFINVERTMATCH(1U)
33874 
33875 #define S_T5_TFPKTTOOLARGE    24
33876 #define V_T5_TFPKTTOOLARGE(x) ((x) << S_T5_TFPKTTOOLARGE)
33877 #define F_T5_TFPKTTOOLARGE    V_T5_TFPKTTOOLARGE(1U)
33878 
33879 #define S_T5_TFEN    23
33880 #define V_T5_TFEN(x) ((x) << S_T5_TFEN)
33881 #define F_T5_TFEN    V_T5_TFEN(1U)
33882 
33883 #define S_T5_TFPORT    18
33884 #define M_T5_TFPORT    0x1fU
33885 #define V_T5_TFPORT(x) ((x) << S_T5_TFPORT)
33886 #define G_T5_TFPORT(x) (((x) >> S_T5_TFPORT) & M_T5_TFPORT)
33887 
33888 #define A_MPS_TRC_FILTER_MATCH_CTL_B 0x9820
33889 
33890 #define S_TFMINPKTSIZE    16
33891 #define M_TFMINPKTSIZE    0x1ffU
33892 #define V_TFMINPKTSIZE(x) ((x) << S_TFMINPKTSIZE)
33893 #define G_TFMINPKTSIZE(x) (((x) >> S_TFMINPKTSIZE) & M_TFMINPKTSIZE)
33894 
33895 #define S_TFCAPTUREMAX    0
33896 #define M_TFCAPTUREMAX    0x3fffU
33897 #define V_TFCAPTUREMAX(x) ((x) << S_TFCAPTUREMAX)
33898 #define G_TFCAPTUREMAX(x) (((x) >> S_TFCAPTUREMAX) & M_TFCAPTUREMAX)
33899 
33900 #define A_MPS_TRC_FILTER_RUNT_CTL 0x9830
33901 
33902 #define S_TFRUNTSIZE    0
33903 #define M_TFRUNTSIZE    0x3fU
33904 #define V_TFRUNTSIZE(x) ((x) << S_TFRUNTSIZE)
33905 #define G_TFRUNTSIZE(x) (((x) >> S_TFRUNTSIZE) & M_TFRUNTSIZE)
33906 
33907 #define A_MPS_TRC_FILTER_DROP 0x9840
33908 
33909 #define S_TFDROPINPCOUNT    16
33910 #define M_TFDROPINPCOUNT    0xffffU
33911 #define V_TFDROPINPCOUNT(x) ((x) << S_TFDROPINPCOUNT)
33912 #define G_TFDROPINPCOUNT(x) (((x) >> S_TFDROPINPCOUNT) & M_TFDROPINPCOUNT)
33913 
33914 #define S_TFDROPBUFFERCOUNT    0
33915 #define M_TFDROPBUFFERCOUNT    0xffffU
33916 #define V_TFDROPBUFFERCOUNT(x) ((x) << S_TFDROPBUFFERCOUNT)
33917 #define G_TFDROPBUFFERCOUNT(x) (((x) >> S_TFDROPBUFFERCOUNT) & M_TFDROPBUFFERCOUNT)
33918 
33919 #define A_MPS_TRC_PERR_INJECT 0x9850
33920 
33921 #define S_TRCMEMSEL    1
33922 #define M_TRCMEMSEL    0xfU
33923 #define V_TRCMEMSEL(x) ((x) << S_TRCMEMSEL)
33924 #define G_TRCMEMSEL(x) (((x) >> S_TRCMEMSEL) & M_TRCMEMSEL)
33925 
33926 #define A_MPS_TRC_PERR_ENABLE 0x9854
33927 
33928 #define S_MISCPERR    8
33929 #define V_MISCPERR(x) ((x) << S_MISCPERR)
33930 #define F_MISCPERR    V_MISCPERR(1U)
33931 
33932 #define S_PKTFIFO    4
33933 #define M_PKTFIFO    0xfU
33934 #define V_PKTFIFO(x) ((x) << S_PKTFIFO)
33935 #define G_PKTFIFO(x) (((x) >> S_PKTFIFO) & M_PKTFIFO)
33936 
33937 #define S_FILTMEM    0
33938 #define M_FILTMEM    0xfU
33939 #define V_FILTMEM(x) ((x) << S_FILTMEM)
33940 #define G_FILTMEM(x) (((x) >> S_FILTMEM) & M_FILTMEM)
33941 
33942 #define A_MPS_TRC_INT_ENABLE 0x9858
33943 
33944 #define S_TRCPLERRENB    9
33945 #define V_TRCPLERRENB(x) ((x) << S_TRCPLERRENB)
33946 #define F_TRCPLERRENB    V_TRCPLERRENB(1U)
33947 
33948 #define A_MPS_TRC_INT_CAUSE 0x985c
33949 #define A_MPS_TRC_TIMESTAMP_L 0x9860
33950 #define A_MPS_TRC_TIMESTAMP_H 0x9864
33951 #define A_MPS_TRC_FILTER0_MATCH 0x9c00
33952 #define A_MPS_TRC_FILTER0_DONT_CARE 0x9c80
33953 #define A_MPS_TRC_FILTER1_MATCH 0x9d00
33954 #define A_MPS_TRC_FILTER1_DONT_CARE 0x9d80
33955 #define A_MPS_TRC_FILTER2_MATCH 0x9e00
33956 #define A_MPS_TRC_FILTER2_DONT_CARE 0x9e80
33957 #define A_MPS_TRC_FILTER3_MATCH 0x9f00
33958 #define A_MPS_TRC_FILTER3_DONT_CARE 0x9f80
33959 #define A_MPS_TRC_FILTER1_RSS_HASH 0x9ff0
33960 #define A_MPS_TRC_FILTER1_RSS_CONTROL 0x9ff4
33961 #define A_MPS_TRC_FILTER2_RSS_HASH 0x9ff8
33962 #define A_MPS_TRC_FILTER2_RSS_CONTROL 0x9ffc
33963 #define A_MPS_TRC_FILTER3_RSS_HASH 0xa000
33964 #define A_MPS_TRC_FILTER3_RSS_CONTROL 0xa004
33965 #define A_MPS_T5_TRC_RSS_HASH 0xa008
33966 #define A_MPS_T5_TRC_RSS_CONTROL 0xa00c
33967 #define A_MPS_TRC_VF_OFF_FILTER_0 0xa010
33968 
33969 #define S_TRCMPS2TP_MACONLY    20
33970 #define V_TRCMPS2TP_MACONLY(x) ((x) << S_TRCMPS2TP_MACONLY)
33971 #define F_TRCMPS2TP_MACONLY    V_TRCMPS2TP_MACONLY(1U)
33972 
33973 #define S_TRCALLMPS2TP    19
33974 #define V_TRCALLMPS2TP(x) ((x) << S_TRCALLMPS2TP)
33975 #define F_TRCALLMPS2TP    V_TRCALLMPS2TP(1U)
33976 
33977 #define S_TRCALLTP2MPS    18
33978 #define V_TRCALLTP2MPS(x) ((x) << S_TRCALLTP2MPS)
33979 #define F_TRCALLTP2MPS    V_TRCALLTP2MPS(1U)
33980 
33981 #define S_TRCALLVF    17
33982 #define V_TRCALLVF(x) ((x) << S_TRCALLVF)
33983 #define F_TRCALLVF    V_TRCALLVF(1U)
33984 
33985 #define S_TRC_OFLD_EN    16
33986 #define V_TRC_OFLD_EN(x) ((x) << S_TRC_OFLD_EN)
33987 #define F_TRC_OFLD_EN    V_TRC_OFLD_EN(1U)
33988 
33989 #define S_VFFILTEN    15
33990 #define V_VFFILTEN(x) ((x) << S_VFFILTEN)
33991 #define F_VFFILTEN    V_VFFILTEN(1U)
33992 
33993 #define S_VFFILTMASK    8
33994 #define M_VFFILTMASK    0x7fU
33995 #define V_VFFILTMASK(x) ((x) << S_VFFILTMASK)
33996 #define G_VFFILTMASK(x) (((x) >> S_VFFILTMASK) & M_VFFILTMASK)
33997 
33998 #define S_VFFILTVALID    7
33999 #define V_VFFILTVALID(x) ((x) << S_VFFILTVALID)
34000 #define F_VFFILTVALID    V_VFFILTVALID(1U)
34001 
34002 #define S_VFFILTDATA    0
34003 #define M_VFFILTDATA    0x7fU
34004 #define V_VFFILTDATA(x) ((x) << S_VFFILTDATA)
34005 #define G_VFFILTDATA(x) (((x) >> S_VFFILTDATA) & M_VFFILTDATA)
34006 
34007 #define S_T6_TRCMPS2TP_MACONLY    22
34008 #define V_T6_TRCMPS2TP_MACONLY(x) ((x) << S_T6_TRCMPS2TP_MACONLY)
34009 #define F_T6_TRCMPS2TP_MACONLY    V_T6_TRCMPS2TP_MACONLY(1U)
34010 
34011 #define S_T6_TRCALLMPS2TP    21
34012 #define V_T6_TRCALLMPS2TP(x) ((x) << S_T6_TRCALLMPS2TP)
34013 #define F_T6_TRCALLMPS2TP    V_T6_TRCALLMPS2TP(1U)
34014 
34015 #define S_T6_TRCALLTP2MPS    20
34016 #define V_T6_TRCALLTP2MPS(x) ((x) << S_T6_TRCALLTP2MPS)
34017 #define F_T6_TRCALLTP2MPS    V_T6_TRCALLTP2MPS(1U)
34018 
34019 #define S_T6_TRCALLVF    19
34020 #define V_T6_TRCALLVF(x) ((x) << S_T6_TRCALLVF)
34021 #define F_T6_TRCALLVF    V_T6_TRCALLVF(1U)
34022 
34023 #define S_T6_TRC_OFLD_EN    18
34024 #define V_T6_TRC_OFLD_EN(x) ((x) << S_T6_TRC_OFLD_EN)
34025 #define F_T6_TRC_OFLD_EN    V_T6_TRC_OFLD_EN(1U)
34026 
34027 #define S_T6_VFFILTEN    17
34028 #define V_T6_VFFILTEN(x) ((x) << S_T6_VFFILTEN)
34029 #define F_T6_VFFILTEN    V_T6_VFFILTEN(1U)
34030 
34031 #define S_T6_VFFILTMASK    9
34032 #define M_T6_VFFILTMASK    0xffU
34033 #define V_T6_VFFILTMASK(x) ((x) << S_T6_VFFILTMASK)
34034 #define G_T6_VFFILTMASK(x) (((x) >> S_T6_VFFILTMASK) & M_T6_VFFILTMASK)
34035 
34036 #define S_T6_VFFILTVALID    8
34037 #define V_T6_VFFILTVALID(x) ((x) << S_T6_VFFILTVALID)
34038 #define F_T6_VFFILTVALID    V_T6_VFFILTVALID(1U)
34039 
34040 #define S_T6_VFFILTDATA    0
34041 #define M_T6_VFFILTDATA    0xffU
34042 #define V_T6_VFFILTDATA(x) ((x) << S_T6_VFFILTDATA)
34043 #define G_T6_VFFILTDATA(x) (((x) >> S_T6_VFFILTDATA) & M_T6_VFFILTDATA)
34044 
34045 #define A_MPS_TRC_VF_OFF_FILTER_1 0xa014
34046 
34047 #define S_T6_TRCMPS2TP_MACONLY    22
34048 #define V_T6_TRCMPS2TP_MACONLY(x) ((x) << S_T6_TRCMPS2TP_MACONLY)
34049 #define F_T6_TRCMPS2TP_MACONLY    V_T6_TRCMPS2TP_MACONLY(1U)
34050 
34051 #define S_T6_TRCALLMPS2TP    21
34052 #define V_T6_TRCALLMPS2TP(x) ((x) << S_T6_TRCALLMPS2TP)
34053 #define F_T6_TRCALLMPS2TP    V_T6_TRCALLMPS2TP(1U)
34054 
34055 #define S_T6_TRCALLTP2MPS    20
34056 #define V_T6_TRCALLTP2MPS(x) ((x) << S_T6_TRCALLTP2MPS)
34057 #define F_T6_TRCALLTP2MPS    V_T6_TRCALLTP2MPS(1U)
34058 
34059 #define S_T6_TRCALLVF    19
34060 #define V_T6_TRCALLVF(x) ((x) << S_T6_TRCALLVF)
34061 #define F_T6_TRCALLVF    V_T6_TRCALLVF(1U)
34062 
34063 #define S_T6_TRC_OFLD_EN    18
34064 #define V_T6_TRC_OFLD_EN(x) ((x) << S_T6_TRC_OFLD_EN)
34065 #define F_T6_TRC_OFLD_EN    V_T6_TRC_OFLD_EN(1U)
34066 
34067 #define S_T6_VFFILTEN    17
34068 #define V_T6_VFFILTEN(x) ((x) << S_T6_VFFILTEN)
34069 #define F_T6_VFFILTEN    V_T6_VFFILTEN(1U)
34070 
34071 #define S_T6_VFFILTMASK    9
34072 #define M_T6_VFFILTMASK    0xffU
34073 #define V_T6_VFFILTMASK(x) ((x) << S_T6_VFFILTMASK)
34074 #define G_T6_VFFILTMASK(x) (((x) >> S_T6_VFFILTMASK) & M_T6_VFFILTMASK)
34075 
34076 #define S_T6_VFFILTVALID    8
34077 #define V_T6_VFFILTVALID(x) ((x) << S_T6_VFFILTVALID)
34078 #define F_T6_VFFILTVALID    V_T6_VFFILTVALID(1U)
34079 
34080 #define S_T6_VFFILTDATA    0
34081 #define M_T6_VFFILTDATA    0xffU
34082 #define V_T6_VFFILTDATA(x) ((x) << S_T6_VFFILTDATA)
34083 #define G_T6_VFFILTDATA(x) (((x) >> S_T6_VFFILTDATA) & M_T6_VFFILTDATA)
34084 
34085 #define A_MPS_TRC_VF_OFF_FILTER_2 0xa018
34086 
34087 #define S_T6_TRCMPS2TP_MACONLY    22
34088 #define V_T6_TRCMPS2TP_MACONLY(x) ((x) << S_T6_TRCMPS2TP_MACONLY)
34089 #define F_T6_TRCMPS2TP_MACONLY    V_T6_TRCMPS2TP_MACONLY(1U)
34090 
34091 #define S_T6_TRCALLMPS2TP    21
34092 #define V_T6_TRCALLMPS2TP(x) ((x) << S_T6_TRCALLMPS2TP)
34093 #define F_T6_TRCALLMPS2TP    V_T6_TRCALLMPS2TP(1U)
34094 
34095 #define S_T6_TRCALLTP2MPS    20
34096 #define V_T6_TRCALLTP2MPS(x) ((x) << S_T6_TRCALLTP2MPS)
34097 #define F_T6_TRCALLTP2MPS    V_T6_TRCALLTP2MPS(1U)
34098 
34099 #define S_T6_TRCALLVF    19
34100 #define V_T6_TRCALLVF(x) ((x) << S_T6_TRCALLVF)
34101 #define F_T6_TRCALLVF    V_T6_TRCALLVF(1U)
34102 
34103 #define S_T6_TRC_OFLD_EN    18
34104 #define V_T6_TRC_OFLD_EN(x) ((x) << S_T6_TRC_OFLD_EN)
34105 #define F_T6_TRC_OFLD_EN    V_T6_TRC_OFLD_EN(1U)
34106 
34107 #define S_T6_VFFILTEN    17
34108 #define V_T6_VFFILTEN(x) ((x) << S_T6_VFFILTEN)
34109 #define F_T6_VFFILTEN    V_T6_VFFILTEN(1U)
34110 
34111 #define S_T6_VFFILTMASK    9
34112 #define M_T6_VFFILTMASK    0xffU
34113 #define V_T6_VFFILTMASK(x) ((x) << S_T6_VFFILTMASK)
34114 #define G_T6_VFFILTMASK(x) (((x) >> S_T6_VFFILTMASK) & M_T6_VFFILTMASK)
34115 
34116 #define S_T6_VFFILTVALID    8
34117 #define V_T6_VFFILTVALID(x) ((x) << S_T6_VFFILTVALID)
34118 #define F_T6_VFFILTVALID    V_T6_VFFILTVALID(1U)
34119 
34120 #define S_T6_VFFILTDATA    0
34121 #define M_T6_VFFILTDATA    0xffU
34122 #define V_T6_VFFILTDATA(x) ((x) << S_T6_VFFILTDATA)
34123 #define G_T6_VFFILTDATA(x) (((x) >> S_T6_VFFILTDATA) & M_T6_VFFILTDATA)
34124 
34125 #define A_MPS_TRC_VF_OFF_FILTER_3 0xa01c
34126 
34127 #define S_T6_TRCMPS2TP_MACONLY    22
34128 #define V_T6_TRCMPS2TP_MACONLY(x) ((x) << S_T6_TRCMPS2TP_MACONLY)
34129 #define F_T6_TRCMPS2TP_MACONLY    V_T6_TRCMPS2TP_MACONLY(1U)
34130 
34131 #define S_T6_TRCALLMPS2TP    21
34132 #define V_T6_TRCALLMPS2TP(x) ((x) << S_T6_TRCALLMPS2TP)
34133 #define F_T6_TRCALLMPS2TP    V_T6_TRCALLMPS2TP(1U)
34134 
34135 #define S_T6_TRCALLTP2MPS    20
34136 #define V_T6_TRCALLTP2MPS(x) ((x) << S_T6_TRCALLTP2MPS)
34137 #define F_T6_TRCALLTP2MPS    V_T6_TRCALLTP2MPS(1U)
34138 
34139 #define S_T6_TRCALLVF    19
34140 #define V_T6_TRCALLVF(x) ((x) << S_T6_TRCALLVF)
34141 #define F_T6_TRCALLVF    V_T6_TRCALLVF(1U)
34142 
34143 #define S_T6_TRC_OFLD_EN    18
34144 #define V_T6_TRC_OFLD_EN(x) ((x) << S_T6_TRC_OFLD_EN)
34145 #define F_T6_TRC_OFLD_EN    V_T6_TRC_OFLD_EN(1U)
34146 
34147 #define S_T6_VFFILTEN    17
34148 #define V_T6_VFFILTEN(x) ((x) << S_T6_VFFILTEN)
34149 #define F_T6_VFFILTEN    V_T6_VFFILTEN(1U)
34150 
34151 #define S_T6_VFFILTMASK    9
34152 #define M_T6_VFFILTMASK    0xffU
34153 #define V_T6_VFFILTMASK(x) ((x) << S_T6_VFFILTMASK)
34154 #define G_T6_VFFILTMASK(x) (((x) >> S_T6_VFFILTMASK) & M_T6_VFFILTMASK)
34155 
34156 #define S_T6_VFFILTVALID    8
34157 #define V_T6_VFFILTVALID(x) ((x) << S_T6_VFFILTVALID)
34158 #define F_T6_VFFILTVALID    V_T6_VFFILTVALID(1U)
34159 
34160 #define S_T6_VFFILTDATA    0
34161 #define M_T6_VFFILTDATA    0xffU
34162 #define V_T6_VFFILTDATA(x) ((x) << S_T6_VFFILTDATA)
34163 #define G_T6_VFFILTDATA(x) (((x) >> S_T6_VFFILTDATA) & M_T6_VFFILTDATA)
34164 
34165 #define A_MPS_TRC_CGEN 0xa020
34166 
34167 #define S_MPSTRCCGEN    0
34168 #define M_MPSTRCCGEN    0xfU
34169 #define V_MPSTRCCGEN(x) ((x) << S_MPSTRCCGEN)
34170 #define G_MPSTRCCGEN(x) (((x) >> S_MPSTRCCGEN) & M_MPSTRCCGEN)
34171 
34172 #define A_MPS_CLS_CTL 0xd000
34173 
34174 #define S_MEMWRITEFAULT    4
34175 #define V_MEMWRITEFAULT(x) ((x) << S_MEMWRITEFAULT)
34176 #define F_MEMWRITEFAULT    V_MEMWRITEFAULT(1U)
34177 
34178 #define S_MEMWRITEWAITING    3
34179 #define V_MEMWRITEWAITING(x) ((x) << S_MEMWRITEWAITING)
34180 #define F_MEMWRITEWAITING    V_MEMWRITEWAITING(1U)
34181 
34182 #define S_CIMNOPROMISCUOUS    2
34183 #define V_CIMNOPROMISCUOUS(x) ((x) << S_CIMNOPROMISCUOUS)
34184 #define F_CIMNOPROMISCUOUS    V_CIMNOPROMISCUOUS(1U)
34185 
34186 #define S_HYPERVISORONLY    1
34187 #define V_HYPERVISORONLY(x) ((x) << S_HYPERVISORONLY)
34188 #define F_HYPERVISORONLY    V_HYPERVISORONLY(1U)
34189 
34190 #define S_VLANCLSEN    0
34191 #define V_VLANCLSEN(x) ((x) << S_VLANCLSEN)
34192 #define F_VLANCLSEN    V_VLANCLSEN(1U)
34193 
34194 #define S_VLANCLSEN_IN    7
34195 #define V_VLANCLSEN_IN(x) ((x) << S_VLANCLSEN_IN)
34196 #define F_VLANCLSEN_IN    V_VLANCLSEN_IN(1U)
34197 
34198 #define S_DISTCAMPARCHK    6
34199 #define V_DISTCAMPARCHK(x) ((x) << S_DISTCAMPARCHK)
34200 #define F_DISTCAMPARCHK    V_DISTCAMPARCHK(1U)
34201 
34202 #define S_VLANLKPEN    5
34203 #define V_VLANLKPEN(x) ((x) << S_VLANLKPEN)
34204 #define F_VLANLKPEN    V_VLANLKPEN(1U)
34205 
34206 #define A_MPS_CLS_ARB_WEIGHT 0xd004
34207 
34208 #define S_PLWEIGHT    16
34209 #define M_PLWEIGHT    0x1fU
34210 #define V_PLWEIGHT(x) ((x) << S_PLWEIGHT)
34211 #define G_PLWEIGHT(x) (((x) >> S_PLWEIGHT) & M_PLWEIGHT)
34212 
34213 #define S_CIMWEIGHT    8
34214 #define M_CIMWEIGHT    0x1fU
34215 #define V_CIMWEIGHT(x) ((x) << S_CIMWEIGHT)
34216 #define G_CIMWEIGHT(x) (((x) >> S_CIMWEIGHT) & M_CIMWEIGHT)
34217 
34218 #define S_LPBKWEIGHT    0
34219 #define M_LPBKWEIGHT    0x1fU
34220 #define V_LPBKWEIGHT(x) ((x) << S_LPBKWEIGHT)
34221 #define G_LPBKWEIGHT(x) (((x) >> S_LPBKWEIGHT) & M_LPBKWEIGHT)
34222 
34223 #define A_MPS_CLS_NCSI_ETH_TYPE 0xd008
34224 #define A_MPS_CLS_NCSI_ETH_TYPE_EN 0xd00c
34225 #define A_MPS_CLS_BMC_MAC_ADDR_L 0xd010
34226 #define A_MPS_CLS_BMC_MAC_ADDR_H 0xd014
34227 #define A_MPS_CLS_BMC_VLAN 0xd018
34228 #define A_MPS_CLS_PERR_INJECT 0xd01c
34229 
34230 #define S_CLS_MEMSEL    1
34231 #define M_CLS_MEMSEL    0x3U
34232 #define V_CLS_MEMSEL(x) ((x) << S_CLS_MEMSEL)
34233 #define G_CLS_MEMSEL(x) (((x) >> S_CLS_MEMSEL) & M_CLS_MEMSEL)
34234 
34235 #define A_MPS_CLS_PERR_ENABLE 0xd020
34236 
34237 #define S_HASHSRAM    2
34238 #define V_HASHSRAM(x) ((x) << S_HASHSRAM)
34239 #define F_HASHSRAM    V_HASHSRAM(1U)
34240 
34241 #define S_MATCHTCAM    1
34242 #define V_MATCHTCAM(x) ((x) << S_MATCHTCAM)
34243 #define F_MATCHTCAM    V_MATCHTCAM(1U)
34244 
34245 #define S_MATCHSRAM    0
34246 #define V_MATCHSRAM(x) ((x) << S_MATCHSRAM)
34247 #define F_MATCHSRAM    V_MATCHSRAM(1U)
34248 
34249 #define A_MPS_CLS_INT_ENABLE 0xd024
34250 
34251 #define S_PLERRENB    3
34252 #define V_PLERRENB(x) ((x) << S_PLERRENB)
34253 #define F_PLERRENB    V_PLERRENB(1U)
34254 
34255 #define A_MPS_CLS_INT_CAUSE 0xd028
34256 #define A_MPS_CLS_PL_TEST_DATA_L 0xd02c
34257 #define A_MPS_CLS_PL_TEST_DATA_H 0xd030
34258 #define A_MPS_CLS_PL_TEST_RES_DATA 0xd034
34259 
34260 #define S_CLS_PRIORITY    24
34261 #define M_CLS_PRIORITY    0x7U
34262 #define V_CLS_PRIORITY(x) ((x) << S_CLS_PRIORITY)
34263 #define G_CLS_PRIORITY(x) (((x) >> S_CLS_PRIORITY) & M_CLS_PRIORITY)
34264 
34265 #define S_CLS_REPLICATE    23
34266 #define V_CLS_REPLICATE(x) ((x) << S_CLS_REPLICATE)
34267 #define F_CLS_REPLICATE    V_CLS_REPLICATE(1U)
34268 
34269 #define S_CLS_INDEX    14
34270 #define M_CLS_INDEX    0x1ffU
34271 #define V_CLS_INDEX(x) ((x) << S_CLS_INDEX)
34272 #define G_CLS_INDEX(x) (((x) >> S_CLS_INDEX) & M_CLS_INDEX)
34273 
34274 #define S_CLS_VF    7
34275 #define M_CLS_VF    0x7fU
34276 #define V_CLS_VF(x) ((x) << S_CLS_VF)
34277 #define G_CLS_VF(x) (((x) >> S_CLS_VF) & M_CLS_VF)
34278 
34279 #define S_CLS_VF_VLD    6
34280 #define V_CLS_VF_VLD(x) ((x) << S_CLS_VF_VLD)
34281 #define F_CLS_VF_VLD    V_CLS_VF_VLD(1U)
34282 
34283 #define S_CLS_PF    3
34284 #define M_CLS_PF    0x7U
34285 #define V_CLS_PF(x) ((x) << S_CLS_PF)
34286 #define G_CLS_PF(x) (((x) >> S_CLS_PF) & M_CLS_PF)
34287 
34288 #define S_CLS_MATCH    0
34289 #define M_CLS_MATCH    0x7U
34290 #define V_CLS_MATCH(x) ((x) << S_CLS_MATCH)
34291 #define G_CLS_MATCH(x) (((x) >> S_CLS_MATCH) & M_CLS_MATCH)
34292 
34293 #define S_CLS_SPARE    28
34294 #define M_CLS_SPARE    0xfU
34295 #define V_CLS_SPARE(x) ((x) << S_CLS_SPARE)
34296 #define G_CLS_SPARE(x) (((x) >> S_CLS_SPARE) & M_CLS_SPARE)
34297 
34298 #define S_T6_CLS_PRIORITY    25
34299 #define M_T6_CLS_PRIORITY    0x7U
34300 #define V_T6_CLS_PRIORITY(x) ((x) << S_T6_CLS_PRIORITY)
34301 #define G_T6_CLS_PRIORITY(x) (((x) >> S_T6_CLS_PRIORITY) & M_T6_CLS_PRIORITY)
34302 
34303 #define S_T6_CLS_REPLICATE    24
34304 #define V_T6_CLS_REPLICATE(x) ((x) << S_T6_CLS_REPLICATE)
34305 #define F_T6_CLS_REPLICATE    V_T6_CLS_REPLICATE(1U)
34306 
34307 #define S_T6_CLS_INDEX    15
34308 #define M_T6_CLS_INDEX    0x1ffU
34309 #define V_T6_CLS_INDEX(x) ((x) << S_T6_CLS_INDEX)
34310 #define G_T6_CLS_INDEX(x) (((x) >> S_T6_CLS_INDEX) & M_T6_CLS_INDEX)
34311 
34312 #define S_T6_CLS_VF    7
34313 #define M_T6_CLS_VF    0xffU
34314 #define V_T6_CLS_VF(x) ((x) << S_T6_CLS_VF)
34315 #define G_T6_CLS_VF(x) (((x) >> S_T6_CLS_VF) & M_T6_CLS_VF)
34316 
34317 #define A_MPS_CLS_PL_TEST_CTL 0xd038
34318 
34319 #define S_PLTESTCTL    0
34320 #define V_PLTESTCTL(x) ((x) << S_PLTESTCTL)
34321 #define F_PLTESTCTL    V_PLTESTCTL(1U)
34322 
34323 #define A_MPS_CLS_PORT_BMC_CTL 0xd03c
34324 
34325 #define S_PRTBMCCTL    0
34326 #define V_PRTBMCCTL(x) ((x) << S_PRTBMCCTL)
34327 #define F_PRTBMCCTL    V_PRTBMCCTL(1U)
34328 
34329 #define A_MPS_CLS_MATCH_CNT_TCAM 0xd100
34330 #define A_MPS_CLS_MATCH_CNT_HASH 0xd104
34331 #define A_MPS_CLS_MATCH_CNT_BCAST 0xd108
34332 #define A_MPS_CLS_MATCH_CNT_BMC 0xd10c
34333 #define A_MPS_CLS_MATCH_CNT_PROM 0xd110
34334 #define A_MPS_CLS_MATCH_CNT_HPROM 0xd114
34335 #define A_MPS_CLS_MISS_CNT 0xd118
34336 #define A_MPS_CLS_REQUEST_TRACE_MAC_DA_L 0xd200
34337 #define A_MPS_CLS_REQUEST_TRACE_MAC_DA_H 0xd204
34338 
34339 #define S_CLSTRCMACDAHI    0
34340 #define M_CLSTRCMACDAHI    0xffffU
34341 #define V_CLSTRCMACDAHI(x) ((x) << S_CLSTRCMACDAHI)
34342 #define G_CLSTRCMACDAHI(x) (((x) >> S_CLSTRCMACDAHI) & M_CLSTRCMACDAHI)
34343 
34344 #define A_MPS_CLS_REQUEST_TRACE_MAC_SA_L 0xd208
34345 #define A_MPS_CLS_REQUEST_TRACE_MAC_SA_H 0xd20c
34346 
34347 #define S_CLSTRCMACSAHI    0
34348 #define M_CLSTRCMACSAHI    0xffffU
34349 #define V_CLSTRCMACSAHI(x) ((x) << S_CLSTRCMACSAHI)
34350 #define G_CLSTRCMACSAHI(x) (((x) >> S_CLSTRCMACSAHI) & M_CLSTRCMACSAHI)
34351 
34352 #define A_MPS_CLS_REQUEST_TRACE_PORT_VLAN 0xd210
34353 
34354 #define S_CLSTRCVLANVLD    31
34355 #define V_CLSTRCVLANVLD(x) ((x) << S_CLSTRCVLANVLD)
34356 #define F_CLSTRCVLANVLD    V_CLSTRCVLANVLD(1U)
34357 
34358 #define S_CLSTRCVLANID    16
34359 #define M_CLSTRCVLANID    0xfffU
34360 #define V_CLSTRCVLANID(x) ((x) << S_CLSTRCVLANID)
34361 #define G_CLSTRCVLANID(x) (((x) >> S_CLSTRCVLANID) & M_CLSTRCVLANID)
34362 
34363 #define S_CLSTRCREQPORT    0
34364 #define M_CLSTRCREQPORT    0xfU
34365 #define V_CLSTRCREQPORT(x) ((x) << S_CLSTRCREQPORT)
34366 #define G_CLSTRCREQPORT(x) (((x) >> S_CLSTRCREQPORT) & M_CLSTRCREQPORT)
34367 
34368 #define A_MPS_CLS_REQUEST_TRACE_ENCAP 0xd214
34369 
34370 #define S_CLSTRCLKPTYPE    31
34371 #define V_CLSTRCLKPTYPE(x) ((x) << S_CLSTRCLKPTYPE)
34372 #define F_CLSTRCLKPTYPE    V_CLSTRCLKPTYPE(1U)
34373 
34374 #define S_CLSTRCDIPHIT    30
34375 #define V_CLSTRCDIPHIT(x) ((x) << S_CLSTRCDIPHIT)
34376 #define F_CLSTRCDIPHIT    V_CLSTRCDIPHIT(1U)
34377 
34378 #define S_CLSTRCVNI    0
34379 #define M_CLSTRCVNI    0xffffffU
34380 #define V_CLSTRCVNI(x) ((x) << S_CLSTRCVNI)
34381 #define G_CLSTRCVNI(x) (((x) >> S_CLSTRCVNI) & M_CLSTRCVNI)
34382 
34383 #define A_MPS_CLS_RESULT_TRACE 0xd300
34384 
34385 #define S_CLSTRCPORTNUM    31
34386 #define V_CLSTRCPORTNUM(x) ((x) << S_CLSTRCPORTNUM)
34387 #define F_CLSTRCPORTNUM    V_CLSTRCPORTNUM(1U)
34388 
34389 #define S_CLSTRCPRIORITY    28
34390 #define M_CLSTRCPRIORITY    0x7U
34391 #define V_CLSTRCPRIORITY(x) ((x) << S_CLSTRCPRIORITY)
34392 #define G_CLSTRCPRIORITY(x) (((x) >> S_CLSTRCPRIORITY) & M_CLSTRCPRIORITY)
34393 
34394 #define S_CLSTRCMULTILISTEN    27
34395 #define V_CLSTRCMULTILISTEN(x) ((x) << S_CLSTRCMULTILISTEN)
34396 #define F_CLSTRCMULTILISTEN    V_CLSTRCMULTILISTEN(1U)
34397 
34398 #define S_CLSTRCREPLICATE    26
34399 #define V_CLSTRCREPLICATE(x) ((x) << S_CLSTRCREPLICATE)
34400 #define F_CLSTRCREPLICATE    V_CLSTRCREPLICATE(1U)
34401 
34402 #define S_CLSTRCPORTMAP    24
34403 #define M_CLSTRCPORTMAP    0x3U
34404 #define V_CLSTRCPORTMAP(x) ((x) << S_CLSTRCPORTMAP)
34405 #define G_CLSTRCPORTMAP(x) (((x) >> S_CLSTRCPORTMAP) & M_CLSTRCPORTMAP)
34406 
34407 #define S_CLSTRCMATCH    21
34408 #define M_CLSTRCMATCH    0x7U
34409 #define V_CLSTRCMATCH(x) ((x) << S_CLSTRCMATCH)
34410 #define G_CLSTRCMATCH(x) (((x) >> S_CLSTRCMATCH) & M_CLSTRCMATCH)
34411 
34412 #define S_CLSTRCINDEX    12
34413 #define M_CLSTRCINDEX    0x1ffU
34414 #define V_CLSTRCINDEX(x) ((x) << S_CLSTRCINDEX)
34415 #define G_CLSTRCINDEX(x) (((x) >> S_CLSTRCINDEX) & M_CLSTRCINDEX)
34416 
34417 #define S_CLSTRCVF_VLD    11
34418 #define V_CLSTRCVF_VLD(x) ((x) << S_CLSTRCVF_VLD)
34419 #define F_CLSTRCVF_VLD    V_CLSTRCVF_VLD(1U)
34420 
34421 #define S_CLSTRCPF    3
34422 #define M_CLSTRCPF    0xffU
34423 #define V_CLSTRCPF(x) ((x) << S_CLSTRCPF)
34424 #define G_CLSTRCPF(x) (((x) >> S_CLSTRCPF) & M_CLSTRCPF)
34425 
34426 #define S_CLSTRCVF    0
34427 #define M_CLSTRCVF    0x7U
34428 #define V_CLSTRCVF(x) ((x) << S_CLSTRCVF)
34429 #define G_CLSTRCVF(x) (((x) >> S_CLSTRCVF) & M_CLSTRCVF)
34430 
34431 #define A_MPS_CLS_VLAN_TABLE 0xdfc0
34432 
34433 #define S_VLAN_MASK    16
34434 #define M_VLAN_MASK    0xfffU
34435 #define V_VLAN_MASK(x) ((x) << S_VLAN_MASK)
34436 #define G_VLAN_MASK(x) (((x) >> S_VLAN_MASK) & M_VLAN_MASK)
34437 
34438 #define S_VLANPF    13
34439 #define M_VLANPF    0x7U
34440 #define V_VLANPF(x) ((x) << S_VLANPF)
34441 #define G_VLANPF(x) (((x) >> S_VLANPF) & M_VLANPF)
34442 
34443 #define S_VLAN_VALID    12
34444 #define V_VLAN_VALID(x) ((x) << S_VLAN_VALID)
34445 #define F_VLAN_VALID    V_VLAN_VALID(1U)
34446 
34447 #define A_MPS_CLS_SRAM_L 0xe000
34448 
34449 #define S_MULTILISTEN3    28
34450 #define V_MULTILISTEN3(x) ((x) << S_MULTILISTEN3)
34451 #define F_MULTILISTEN3    V_MULTILISTEN3(1U)
34452 
34453 #define S_MULTILISTEN2    27
34454 #define V_MULTILISTEN2(x) ((x) << S_MULTILISTEN2)
34455 #define F_MULTILISTEN2    V_MULTILISTEN2(1U)
34456 
34457 #define S_MULTILISTEN1    26
34458 #define V_MULTILISTEN1(x) ((x) << S_MULTILISTEN1)
34459 #define F_MULTILISTEN1    V_MULTILISTEN1(1U)
34460 
34461 #define S_MULTILISTEN0    25
34462 #define V_MULTILISTEN0(x) ((x) << S_MULTILISTEN0)
34463 #define F_MULTILISTEN0    V_MULTILISTEN0(1U)
34464 
34465 #define S_SRAM_PRIO3    22
34466 #define M_SRAM_PRIO3    0x7U
34467 #define V_SRAM_PRIO3(x) ((x) << S_SRAM_PRIO3)
34468 #define G_SRAM_PRIO3(x) (((x) >> S_SRAM_PRIO3) & M_SRAM_PRIO3)
34469 
34470 #define S_SRAM_PRIO2    19
34471 #define M_SRAM_PRIO2    0x7U
34472 #define V_SRAM_PRIO2(x) ((x) << S_SRAM_PRIO2)
34473 #define G_SRAM_PRIO2(x) (((x) >> S_SRAM_PRIO2) & M_SRAM_PRIO2)
34474 
34475 #define S_SRAM_PRIO1    16
34476 #define M_SRAM_PRIO1    0x7U
34477 #define V_SRAM_PRIO1(x) ((x) << S_SRAM_PRIO1)
34478 #define G_SRAM_PRIO1(x) (((x) >> S_SRAM_PRIO1) & M_SRAM_PRIO1)
34479 
34480 #define S_SRAM_PRIO0    13
34481 #define M_SRAM_PRIO0    0x7U
34482 #define V_SRAM_PRIO0(x) ((x) << S_SRAM_PRIO0)
34483 #define G_SRAM_PRIO0(x) (((x) >> S_SRAM_PRIO0) & M_SRAM_PRIO0)
34484 
34485 #define S_SRAM_VLD    12
34486 #define V_SRAM_VLD(x) ((x) << S_SRAM_VLD)
34487 #define F_SRAM_VLD    V_SRAM_VLD(1U)
34488 
34489 #define A_MPS_T5_CLS_SRAM_L 0xe000
34490 
34491 #define S_T6_DISENCAPOUTERRPLCT    31
34492 #define V_T6_DISENCAPOUTERRPLCT(x) ((x) << S_T6_DISENCAPOUTERRPLCT)
34493 #define F_T6_DISENCAPOUTERRPLCT    V_T6_DISENCAPOUTERRPLCT(1U)
34494 
34495 #define S_T6_DISENCAP    30
34496 #define V_T6_DISENCAP(x) ((x) << S_T6_DISENCAP)
34497 #define F_T6_DISENCAP    V_T6_DISENCAP(1U)
34498 
34499 #define S_T6_MULTILISTEN3    29
34500 #define V_T6_MULTILISTEN3(x) ((x) << S_T6_MULTILISTEN3)
34501 #define F_T6_MULTILISTEN3    V_T6_MULTILISTEN3(1U)
34502 
34503 #define S_T6_MULTILISTEN2    28
34504 #define V_T6_MULTILISTEN2(x) ((x) << S_T6_MULTILISTEN2)
34505 #define F_T6_MULTILISTEN2    V_T6_MULTILISTEN2(1U)
34506 
34507 #define S_T6_MULTILISTEN1    27
34508 #define V_T6_MULTILISTEN1(x) ((x) << S_T6_MULTILISTEN1)
34509 #define F_T6_MULTILISTEN1    V_T6_MULTILISTEN1(1U)
34510 
34511 #define S_T6_MULTILISTEN0    26
34512 #define V_T6_MULTILISTEN0(x) ((x) << S_T6_MULTILISTEN0)
34513 #define F_T6_MULTILISTEN0    V_T6_MULTILISTEN0(1U)
34514 
34515 #define S_T6_SRAM_PRIO3    23
34516 #define M_T6_SRAM_PRIO3    0x7U
34517 #define V_T6_SRAM_PRIO3(x) ((x) << S_T6_SRAM_PRIO3)
34518 #define G_T6_SRAM_PRIO3(x) (((x) >> S_T6_SRAM_PRIO3) & M_T6_SRAM_PRIO3)
34519 
34520 #define S_T6_SRAM_PRIO2    20
34521 #define M_T6_SRAM_PRIO2    0x7U
34522 #define V_T6_SRAM_PRIO2(x) ((x) << S_T6_SRAM_PRIO2)
34523 #define G_T6_SRAM_PRIO2(x) (((x) >> S_T6_SRAM_PRIO2) & M_T6_SRAM_PRIO2)
34524 
34525 #define S_T6_SRAM_PRIO1    17
34526 #define M_T6_SRAM_PRIO1    0x7U
34527 #define V_T6_SRAM_PRIO1(x) ((x) << S_T6_SRAM_PRIO1)
34528 #define G_T6_SRAM_PRIO1(x) (((x) >> S_T6_SRAM_PRIO1) & M_T6_SRAM_PRIO1)
34529 
34530 #define S_T6_SRAM_PRIO0    14
34531 #define M_T6_SRAM_PRIO0    0x7U
34532 #define V_T6_SRAM_PRIO0(x) ((x) << S_T6_SRAM_PRIO0)
34533 #define G_T6_SRAM_PRIO0(x) (((x) >> S_T6_SRAM_PRIO0) & M_T6_SRAM_PRIO0)
34534 
34535 #define S_T6_SRAM_VLD    13
34536 #define V_T6_SRAM_VLD(x) ((x) << S_T6_SRAM_VLD)
34537 #define F_T6_SRAM_VLD    V_T6_SRAM_VLD(1U)
34538 
34539 #define S_T6_REPLICATE    12
34540 #define V_T6_REPLICATE(x) ((x) << S_T6_REPLICATE)
34541 #define F_T6_REPLICATE    V_T6_REPLICATE(1U)
34542 
34543 #define S_T6_PF    9
34544 #define M_T6_PF    0x7U
34545 #define V_T6_PF(x) ((x) << S_T6_PF)
34546 #define G_T6_PF(x) (((x) >> S_T6_PF) & M_T6_PF)
34547 
34548 #define S_T6_VF_VALID    8
34549 #define V_T6_VF_VALID(x) ((x) << S_T6_VF_VALID)
34550 #define F_T6_VF_VALID    V_T6_VF_VALID(1U)
34551 
34552 #define S_T6_VF    0
34553 #define M_T6_VF    0xffU
34554 #define V_T6_VF(x) ((x) << S_T6_VF)
34555 #define G_T6_VF(x) (((x) >> S_T6_VF) & M_T6_VF)
34556 
34557 #define A_MPS_CLS_SRAM_H 0xe004
34558 
34559 #define S_MACPARITY1    9
34560 #define V_MACPARITY1(x) ((x) << S_MACPARITY1)
34561 #define F_MACPARITY1    V_MACPARITY1(1U)
34562 
34563 #define S_MACPARITY0    8
34564 #define V_MACPARITY0(x) ((x) << S_MACPARITY0)
34565 #define F_MACPARITY0    V_MACPARITY0(1U)
34566 
34567 #define S_MACPARITYMASKSIZE    4
34568 #define M_MACPARITYMASKSIZE    0xfU
34569 #define V_MACPARITYMASKSIZE(x) ((x) << S_MACPARITYMASKSIZE)
34570 #define G_MACPARITYMASKSIZE(x) (((x) >> S_MACPARITYMASKSIZE) & M_MACPARITYMASKSIZE)
34571 
34572 #define S_PORTMAP    0
34573 #define M_PORTMAP    0xfU
34574 #define V_PORTMAP(x) ((x) << S_PORTMAP)
34575 #define G_PORTMAP(x) (((x) >> S_PORTMAP) & M_PORTMAP)
34576 
34577 #define A_MPS_T5_CLS_SRAM_H 0xe004
34578 
34579 #define S_MACPARITY2    10
34580 #define V_MACPARITY2(x) ((x) << S_MACPARITY2)
34581 #define F_MACPARITY2    V_MACPARITY2(1U)
34582 
34583 #define A_MPS_CLS_TCAM_Y_L 0xf000
34584 #define A_MPS_CLS_TCAM_DATA0 0xf000
34585 #define A_MPS_CLS_TCAM_Y_H 0xf004
34586 
34587 #define S_TCAMYH    0
34588 #define M_TCAMYH    0xffffU
34589 #define V_TCAMYH(x) ((x) << S_TCAMYH)
34590 #define G_TCAMYH(x) (((x) >> S_TCAMYH) & M_TCAMYH)
34591 
34592 #define A_MPS_CLS_TCAM_DATA1 0xf004
34593 
34594 #define S_VIDL    16
34595 #define M_VIDL    0xffffU
34596 #define V_VIDL(x) ((x) << S_VIDL)
34597 #define G_VIDL(x) (((x) >> S_VIDL) & M_VIDL)
34598 
34599 #define S_DMACH    0
34600 #define M_DMACH    0xffffU
34601 #define V_DMACH(x) ((x) << S_DMACH)
34602 #define G_DMACH(x) (((x) >> S_DMACH) & M_DMACH)
34603 
34604 #define A_MPS_CLS_TCAM_X_L 0xf008
34605 #define A_MPS_CLS_TCAM_DATA2_CTL 0xf008
34606 
34607 #define S_CTLCMDTYPE    31
34608 #define V_CTLCMDTYPE(x) ((x) << S_CTLCMDTYPE)
34609 #define F_CTLCMDTYPE    V_CTLCMDTYPE(1U)
34610 
34611 #define S_CTLREQID    30
34612 #define V_CTLREQID(x) ((x) << S_CTLREQID)
34613 #define F_CTLREQID    V_CTLREQID(1U)
34614 
34615 #define S_CTLTCAMSEL    25
34616 #define V_CTLTCAMSEL(x) ((x) << S_CTLTCAMSEL)
34617 #define F_CTLTCAMSEL    V_CTLTCAMSEL(1U)
34618 
34619 #define S_CTLTCAMINDEX    17
34620 #define M_CTLTCAMINDEX    0xffU
34621 #define V_CTLTCAMINDEX(x) ((x) << S_CTLTCAMINDEX)
34622 #define G_CTLTCAMINDEX(x) (((x) >> S_CTLTCAMINDEX) & M_CTLTCAMINDEX)
34623 
34624 #define S_CTLXYBITSEL    16
34625 #define V_CTLXYBITSEL(x) ((x) << S_CTLXYBITSEL)
34626 #define F_CTLXYBITSEL    V_CTLXYBITSEL(1U)
34627 
34628 #define S_DATAPORTNUM    12
34629 #define M_DATAPORTNUM    0xfU
34630 #define V_DATAPORTNUM(x) ((x) << S_DATAPORTNUM)
34631 #define G_DATAPORTNUM(x) (((x) >> S_DATAPORTNUM) & M_DATAPORTNUM)
34632 
34633 #define S_DATALKPTYPE    10
34634 #define M_DATALKPTYPE    0x3U
34635 #define V_DATALKPTYPE(x) ((x) << S_DATALKPTYPE)
34636 #define G_DATALKPTYPE(x) (((x) >> S_DATALKPTYPE) & M_DATALKPTYPE)
34637 
34638 #define S_DATADIPHIT    8
34639 #define V_DATADIPHIT(x) ((x) << S_DATADIPHIT)
34640 #define F_DATADIPHIT    V_DATADIPHIT(1U)
34641 
34642 #define S_DATAVIDH2    7
34643 #define V_DATAVIDH2(x) ((x) << S_DATAVIDH2)
34644 #define F_DATAVIDH2    V_DATAVIDH2(1U)
34645 
34646 #define S_DATAVIDH1    0
34647 #define M_DATAVIDH1    0x7fU
34648 #define V_DATAVIDH1(x) ((x) << S_DATAVIDH1)
34649 #define G_DATAVIDH1(x) (((x) >> S_DATAVIDH1) & M_DATAVIDH1)
34650 
34651 #define A_MPS_CLS_TCAM_X_H 0xf00c
34652 
34653 #define S_TCAMXH    0
34654 #define M_TCAMXH    0xffffU
34655 #define V_TCAMXH(x) ((x) << S_TCAMXH)
34656 #define G_TCAMXH(x) (((x) >> S_TCAMXH) & M_TCAMXH)
34657 
34658 #define A_MPS_CLS_TCAM_RDATA0_REQ_ID0 0xf010
34659 #define A_MPS_CLS_TCAM_RDATA1_REQ_ID0 0xf014
34660 #define A_MPS_CLS_TCAM_RDATA2_REQ_ID0 0xf018
34661 #define A_MPS_CLS_TCAM_RDATA0_REQ_ID1 0xf020
34662 #define A_MPS_CLS_TCAM_RDATA1_REQ_ID1 0xf024
34663 #define A_MPS_CLS_TCAM_RDATA2_REQ_ID1 0xf028
34664 #define A_MPS_RX_CTL 0x11000
34665 
34666 #define S_FILT_VLAN_SEL    17
34667 #define V_FILT_VLAN_SEL(x) ((x) << S_FILT_VLAN_SEL)
34668 #define F_FILT_VLAN_SEL    V_FILT_VLAN_SEL(1U)
34669 
34670 #define S_CBA_EN    16
34671 #define V_CBA_EN(x) ((x) << S_CBA_EN)
34672 #define F_CBA_EN    V_CBA_EN(1U)
34673 
34674 #define S_BLK_SNDR    12
34675 #define M_BLK_SNDR    0xfU
34676 #define V_BLK_SNDR(x) ((x) << S_BLK_SNDR)
34677 #define G_BLK_SNDR(x) (((x) >> S_BLK_SNDR) & M_BLK_SNDR)
34678 
34679 #define S_CMPRS    8
34680 #define M_CMPRS    0xfU
34681 #define V_CMPRS(x) ((x) << S_CMPRS)
34682 #define G_CMPRS(x) (((x) >> S_CMPRS) & M_CMPRS)
34683 
34684 #define S_SNF    0
34685 #define M_SNF    0xffU
34686 #define V_SNF(x) ((x) << S_SNF)
34687 #define G_SNF(x) (((x) >> S_SNF) & M_SNF)
34688 
34689 #define A_MPS_RX_PORT_MUX_CTL 0x11004
34690 
34691 #define S_CTL_P3    12
34692 #define M_CTL_P3    0xfU
34693 #define V_CTL_P3(x) ((x) << S_CTL_P3)
34694 #define G_CTL_P3(x) (((x) >> S_CTL_P3) & M_CTL_P3)
34695 
34696 #define S_CTL_P2    8
34697 #define M_CTL_P2    0xfU
34698 #define V_CTL_P2(x) ((x) << S_CTL_P2)
34699 #define G_CTL_P2(x) (((x) >> S_CTL_P2) & M_CTL_P2)
34700 
34701 #define S_CTL_P1    4
34702 #define M_CTL_P1    0xfU
34703 #define V_CTL_P1(x) ((x) << S_CTL_P1)
34704 #define G_CTL_P1(x) (((x) >> S_CTL_P1) & M_CTL_P1)
34705 
34706 #define S_CTL_P0    0
34707 #define M_CTL_P0    0xfU
34708 #define V_CTL_P0(x) ((x) << S_CTL_P0)
34709 #define G_CTL_P0(x) (((x) >> S_CTL_P0) & M_CTL_P0)
34710 
34711 #define A_MPS_RX_PG_FL 0x11008
34712 
34713 #define S_RST    16
34714 #define V_RST(x) ((x) << S_RST)
34715 #define F_RST    V_RST(1U)
34716 
34717 #define S_CNT    0
34718 #define M_CNT    0xffffU
34719 #define V_CNT(x) ((x) << S_CNT)
34720 #define G_CNT(x) (((x) >> S_CNT) & M_CNT)
34721 
34722 #define A_MPS_RX_FIFO_0_CTL 0x11008
34723 
34724 #define S_DEST_SELECT    0
34725 #define M_DEST_SELECT    0xfU
34726 #define V_DEST_SELECT(x) ((x) << S_DEST_SELECT)
34727 #define G_DEST_SELECT(x) (((x) >> S_DEST_SELECT) & M_DEST_SELECT)
34728 
34729 #define A_MPS_RX_PKT_FL 0x1100c
34730 #define A_MPS_RX_FIFO_1_CTL 0x1100c
34731 #define A_MPS_RX_PG_RSV0 0x11010
34732 
34733 #define S_CLR_INTR    31
34734 #define V_CLR_INTR(x) ((x) << S_CLR_INTR)
34735 #define F_CLR_INTR    V_CLR_INTR(1U)
34736 
34737 #define S_SET_INTR    30
34738 #define V_SET_INTR(x) ((x) << S_SET_INTR)
34739 #define F_SET_INTR    V_SET_INTR(1U)
34740 
34741 #define S_USED    16
34742 #define M_USED    0x7ffU
34743 #define V_USED(x) ((x) << S_USED)
34744 #define G_USED(x) (((x) >> S_USED) & M_USED)
34745 
34746 #define S_ALLOC    0
34747 #define M_ALLOC    0x7ffU
34748 #define V_ALLOC(x) ((x) << S_ALLOC)
34749 #define G_ALLOC(x) (((x) >> S_ALLOC) & M_ALLOC)
34750 
34751 #define S_T5_USED    16
34752 #define M_T5_USED    0xfffU
34753 #define V_T5_USED(x) ((x) << S_T5_USED)
34754 #define G_T5_USED(x) (((x) >> S_T5_USED) & M_T5_USED)
34755 
34756 #define S_T5_ALLOC    0
34757 #define M_T5_ALLOC    0xfffU
34758 #define V_T5_ALLOC(x) ((x) << S_T5_ALLOC)
34759 #define G_T5_ALLOC(x) (((x) >> S_T5_ALLOC) & M_T5_ALLOC)
34760 
34761 #define A_MPS_RX_FIFO_2_CTL 0x11010
34762 #define A_MPS_RX_PG_RSV1 0x11014
34763 #define A_MPS_RX_FIFO_3_CTL 0x11014
34764 #define A_MPS_RX_PG_RSV2 0x11018
34765 #define A_MPS_RX_PG_RSV3 0x1101c
34766 #define A_MPS_RX_PG_RSV4 0x11020
34767 #define A_MPS_RX_PG_RSV5 0x11024
34768 #define A_MPS_RX_PG_RSV6 0x11028
34769 #define A_MPS_RX_PG_RSV7 0x1102c
34770 #define A_MPS_RX_PG_SHR_BG0 0x11030
34771 
34772 #define S_EN    31
34773 #define V_EN(x) ((x) << S_EN)
34774 #define F_EN    V_EN(1U)
34775 
34776 #define S_SEL    30
34777 #define V_SEL(x) ((x) << S_SEL)
34778 #define F_SEL    V_SEL(1U)
34779 
34780 #define S_MAX    16
34781 #define M_MAX    0x7ffU
34782 #define V_MAX(x) ((x) << S_MAX)
34783 #define G_MAX(x) (((x) >> S_MAX) & M_MAX)
34784 
34785 #define S_BORW    0
34786 #define M_BORW    0x7ffU
34787 #define V_BORW(x) ((x) << S_BORW)
34788 #define G_BORW(x) (((x) >> S_BORW) & M_BORW)
34789 
34790 #define S_T5_MAX    16
34791 #define M_T5_MAX    0xfffU
34792 #define V_T5_MAX(x) ((x) << S_T5_MAX)
34793 #define G_T5_MAX(x) (((x) >> S_T5_MAX) & M_T5_MAX)
34794 
34795 #define S_T5_BORW    0
34796 #define M_T5_BORW    0xfffU
34797 #define V_T5_BORW(x) ((x) << S_T5_BORW)
34798 #define G_T5_BORW(x) (((x) >> S_T5_BORW) & M_T5_BORW)
34799 
34800 #define A_MPS_RX_PG_SHR_BG1 0x11034
34801 #define A_MPS_RX_PG_SHR_BG2 0x11038
34802 #define A_MPS_RX_PG_SHR_BG3 0x1103c
34803 #define A_MPS_RX_PG_SHR0 0x11040
34804 
34805 #define S_QUOTA    16
34806 #define M_QUOTA    0x7ffU
34807 #define V_QUOTA(x) ((x) << S_QUOTA)
34808 #define G_QUOTA(x) (((x) >> S_QUOTA) & M_QUOTA)
34809 
34810 #define S_SHR_USED    0
34811 #define M_SHR_USED    0x7ffU
34812 #define V_SHR_USED(x) ((x) << S_SHR_USED)
34813 #define G_SHR_USED(x) (((x) >> S_SHR_USED) & M_SHR_USED)
34814 
34815 #define S_T5_QUOTA    16
34816 #define M_T5_QUOTA    0xfffU
34817 #define V_T5_QUOTA(x) ((x) << S_T5_QUOTA)
34818 #define G_T5_QUOTA(x) (((x) >> S_T5_QUOTA) & M_T5_QUOTA)
34819 
34820 #define S_T5_SHR_USED    0
34821 #define M_T5_SHR_USED    0xfffU
34822 #define V_T5_SHR_USED(x) ((x) << S_T5_SHR_USED)
34823 #define G_T5_SHR_USED(x) (((x) >> S_T5_SHR_USED) & M_T5_SHR_USED)
34824 
34825 #define A_MPS_RX_PG_SHR1 0x11044
34826 #define A_MPS_RX_PG_HYST_BG0 0x11048
34827 
34828 #define S_TH    0
34829 #define M_TH    0x7ffU
34830 #define V_TH(x) ((x) << S_TH)
34831 #define G_TH(x) (((x) >> S_TH) & M_TH)
34832 
34833 #define S_T5_TH    0
34834 #define M_T5_TH    0xfffU
34835 #define V_T5_TH(x) ((x) << S_T5_TH)
34836 #define G_T5_TH(x) (((x) >> S_T5_TH) & M_T5_TH)
34837 
34838 #define S_T6_TH    0
34839 #define M_T6_TH    0x7ffU
34840 #define V_T6_TH(x) ((x) << S_T6_TH)
34841 #define G_T6_TH(x) (((x) >> S_T6_TH) & M_T6_TH)
34842 
34843 #define A_MPS_RX_PG_HYST_BG1 0x1104c
34844 #define A_MPS_RX_PG_HYST_BG2 0x11050
34845 #define A_MPS_RX_PG_HYST_BG3 0x11054
34846 #define A_MPS_RX_OCH_CTL 0x11058
34847 
34848 #define S_DROP_WT    27
34849 #define M_DROP_WT    0x1fU
34850 #define V_DROP_WT(x) ((x) << S_DROP_WT)
34851 #define G_DROP_WT(x) (((x) >> S_DROP_WT) & M_DROP_WT)
34852 
34853 #define S_TRUNC_WT    22
34854 #define M_TRUNC_WT    0x1fU
34855 #define V_TRUNC_WT(x) ((x) << S_TRUNC_WT)
34856 #define G_TRUNC_WT(x) (((x) >> S_TRUNC_WT) & M_TRUNC_WT)
34857 
34858 #define S_OCH_DRAIN    13
34859 #define M_OCH_DRAIN    0x1fU
34860 #define V_OCH_DRAIN(x) ((x) << S_OCH_DRAIN)
34861 #define G_OCH_DRAIN(x) (((x) >> S_OCH_DRAIN) & M_OCH_DRAIN)
34862 
34863 #define S_OCH_DROP    8
34864 #define M_OCH_DROP    0x1fU
34865 #define V_OCH_DROP(x) ((x) << S_OCH_DROP)
34866 #define G_OCH_DROP(x) (((x) >> S_OCH_DROP) & M_OCH_DROP)
34867 
34868 #define S_STOP    0
34869 #define M_STOP    0x1fU
34870 #define V_STOP(x) ((x) << S_STOP)
34871 #define G_STOP(x) (((x) >> S_STOP) & M_STOP)
34872 
34873 #define A_MPS_RX_LPBK_BP0 0x1105c
34874 
34875 #define S_THRESH    0
34876 #define M_THRESH    0x7ffU
34877 #define V_THRESH(x) ((x) << S_THRESH)
34878 #define G_THRESH(x) (((x) >> S_THRESH) & M_THRESH)
34879 
34880 #define A_MPS_RX_LPBK_BP1 0x11060
34881 #define A_MPS_RX_LPBK_BP2 0x11064
34882 #define A_MPS_RX_LPBK_BP3 0x11068
34883 #define A_MPS_RX_PORT_GAP 0x1106c
34884 
34885 #define S_GAP    0
34886 #define M_GAP    0xfffffU
34887 #define V_GAP(x) ((x) << S_GAP)
34888 #define G_GAP(x) (((x) >> S_GAP) & M_GAP)
34889 
34890 #define A_MPS_RX_CHMN_CNT 0x11070
34891 #define A_MPS_RX_PERR_INT_CAUSE 0x11074
34892 
34893 #define S_FF    23
34894 #define V_FF(x) ((x) << S_FF)
34895 #define F_FF    V_FF(1U)
34896 
34897 #define S_PGMO    22
34898 #define V_PGMO(x) ((x) << S_PGMO)
34899 #define F_PGMO    V_PGMO(1U)
34900 
34901 #define S_PGME    21
34902 #define V_PGME(x) ((x) << S_PGME)
34903 #define F_PGME    V_PGME(1U)
34904 
34905 #define S_CHMN    20
34906 #define V_CHMN(x) ((x) << S_CHMN)
34907 #define F_CHMN    V_CHMN(1U)
34908 
34909 #define S_RPLC    19
34910 #define V_RPLC(x) ((x) << S_RPLC)
34911 #define F_RPLC    V_RPLC(1U)
34912 
34913 #define S_ATRB    18
34914 #define V_ATRB(x) ((x) << S_ATRB)
34915 #define F_ATRB    V_ATRB(1U)
34916 
34917 #define S_PSMX    17
34918 #define V_PSMX(x) ((x) << S_PSMX)
34919 #define F_PSMX    V_PSMX(1U)
34920 
34921 #define S_PGLL    16
34922 #define V_PGLL(x) ((x) << S_PGLL)
34923 #define F_PGLL    V_PGLL(1U)
34924 
34925 #define S_PGFL    15
34926 #define V_PGFL(x) ((x) << S_PGFL)
34927 #define F_PGFL    V_PGFL(1U)
34928 
34929 #define S_PKTQ    14
34930 #define V_PKTQ(x) ((x) << S_PKTQ)
34931 #define F_PKTQ    V_PKTQ(1U)
34932 
34933 #define S_PKFL    13
34934 #define V_PKFL(x) ((x) << S_PKFL)
34935 #define F_PKFL    V_PKFL(1U)
34936 
34937 #define S_PPM3    12
34938 #define V_PPM3(x) ((x) << S_PPM3)
34939 #define F_PPM3    V_PPM3(1U)
34940 
34941 #define S_PPM2    11
34942 #define V_PPM2(x) ((x) << S_PPM2)
34943 #define F_PPM2    V_PPM2(1U)
34944 
34945 #define S_PPM1    10
34946 #define V_PPM1(x) ((x) << S_PPM1)
34947 #define F_PPM1    V_PPM1(1U)
34948 
34949 #define S_PPM0    9
34950 #define V_PPM0(x) ((x) << S_PPM0)
34951 #define F_PPM0    V_PPM0(1U)
34952 
34953 #define S_SPMX    8
34954 #define V_SPMX(x) ((x) << S_SPMX)
34955 #define F_SPMX    V_SPMX(1U)
34956 
34957 #define S_CDL3    7
34958 #define V_CDL3(x) ((x) << S_CDL3)
34959 #define F_CDL3    V_CDL3(1U)
34960 
34961 #define S_CDL2    6
34962 #define V_CDL2(x) ((x) << S_CDL2)
34963 #define F_CDL2    V_CDL2(1U)
34964 
34965 #define S_CDL1    5
34966 #define V_CDL1(x) ((x) << S_CDL1)
34967 #define F_CDL1    V_CDL1(1U)
34968 
34969 #define S_CDL0    4
34970 #define V_CDL0(x) ((x) << S_CDL0)
34971 #define F_CDL0    V_CDL0(1U)
34972 
34973 #define S_CDM3    3
34974 #define V_CDM3(x) ((x) << S_CDM3)
34975 #define F_CDM3    V_CDM3(1U)
34976 
34977 #define S_CDM2    2
34978 #define V_CDM2(x) ((x) << S_CDM2)
34979 #define F_CDM2    V_CDM2(1U)
34980 
34981 #define S_CDM1    1
34982 #define V_CDM1(x) ((x) << S_CDM1)
34983 #define F_CDM1    V_CDM1(1U)
34984 
34985 #define S_CDM0    0
34986 #define V_CDM0(x) ((x) << S_CDM0)
34987 #define F_CDM0    V_CDM0(1U)
34988 
34989 #define S_T6_INT_ERR_INT    24
34990 #define V_T6_INT_ERR_INT(x) ((x) << S_T6_INT_ERR_INT)
34991 #define F_T6_INT_ERR_INT    V_T6_INT_ERR_INT(1U)
34992 
34993 #define A_MPS_RX_PERR_INT_ENABLE 0x11078
34994 
34995 #define S_T6_INT_ERR_INT    24
34996 #define V_T6_INT_ERR_INT(x) ((x) << S_T6_INT_ERR_INT)
34997 #define F_T6_INT_ERR_INT    V_T6_INT_ERR_INT(1U)
34998 
34999 #define A_MPS_RX_PERR_ENABLE 0x1107c
35000 
35001 #define S_T6_INT_ERR_INT    24
35002 #define V_T6_INT_ERR_INT(x) ((x) << S_T6_INT_ERR_INT)
35003 #define F_T6_INT_ERR_INT    V_T6_INT_ERR_INT(1U)
35004 
35005 #define A_MPS_RX_PERR_INJECT 0x11080
35006 #define A_MPS_RX_FUNC_INT_CAUSE 0x11084
35007 
35008 #define S_INT_ERR_INT    8
35009 #define M_INT_ERR_INT    0x1fU
35010 #define V_INT_ERR_INT(x) ((x) << S_INT_ERR_INT)
35011 #define G_INT_ERR_INT(x) (((x) >> S_INT_ERR_INT) & M_INT_ERR_INT)
35012 
35013 #define S_PG_TH_INT7    7
35014 #define V_PG_TH_INT7(x) ((x) << S_PG_TH_INT7)
35015 #define F_PG_TH_INT7    V_PG_TH_INT7(1U)
35016 
35017 #define S_PG_TH_INT6    6
35018 #define V_PG_TH_INT6(x) ((x) << S_PG_TH_INT6)
35019 #define F_PG_TH_INT6    V_PG_TH_INT6(1U)
35020 
35021 #define S_PG_TH_INT5    5
35022 #define V_PG_TH_INT5(x) ((x) << S_PG_TH_INT5)
35023 #define F_PG_TH_INT5    V_PG_TH_INT5(1U)
35024 
35025 #define S_PG_TH_INT4    4
35026 #define V_PG_TH_INT4(x) ((x) << S_PG_TH_INT4)
35027 #define F_PG_TH_INT4    V_PG_TH_INT4(1U)
35028 
35029 #define S_PG_TH_INT3    3
35030 #define V_PG_TH_INT3(x) ((x) << S_PG_TH_INT3)
35031 #define F_PG_TH_INT3    V_PG_TH_INT3(1U)
35032 
35033 #define S_PG_TH_INT2    2
35034 #define V_PG_TH_INT2(x) ((x) << S_PG_TH_INT2)
35035 #define F_PG_TH_INT2    V_PG_TH_INT2(1U)
35036 
35037 #define S_PG_TH_INT1    1
35038 #define V_PG_TH_INT1(x) ((x) << S_PG_TH_INT1)
35039 #define F_PG_TH_INT1    V_PG_TH_INT1(1U)
35040 
35041 #define S_PG_TH_INT0    0
35042 #define V_PG_TH_INT0(x) ((x) << S_PG_TH_INT0)
35043 #define F_PG_TH_INT0    V_PG_TH_INT0(1U)
35044 
35045 #define S_MTU_ERR_INT3    19
35046 #define V_MTU_ERR_INT3(x) ((x) << S_MTU_ERR_INT3)
35047 #define F_MTU_ERR_INT3    V_MTU_ERR_INT3(1U)
35048 
35049 #define S_MTU_ERR_INT2    18
35050 #define V_MTU_ERR_INT2(x) ((x) << S_MTU_ERR_INT2)
35051 #define F_MTU_ERR_INT2    V_MTU_ERR_INT2(1U)
35052 
35053 #define S_MTU_ERR_INT1    17
35054 #define V_MTU_ERR_INT1(x) ((x) << S_MTU_ERR_INT1)
35055 #define F_MTU_ERR_INT1    V_MTU_ERR_INT1(1U)
35056 
35057 #define S_MTU_ERR_INT0    16
35058 #define V_MTU_ERR_INT0(x) ((x) << S_MTU_ERR_INT0)
35059 #define F_MTU_ERR_INT0    V_MTU_ERR_INT0(1U)
35060 
35061 #define S_SE_CNT_ERR_INT    15
35062 #define V_SE_CNT_ERR_INT(x) ((x) << S_SE_CNT_ERR_INT)
35063 #define F_SE_CNT_ERR_INT    V_SE_CNT_ERR_INT(1U)
35064 
35065 #define S_FRM_ERR_INT    14
35066 #define V_FRM_ERR_INT(x) ((x) << S_FRM_ERR_INT)
35067 #define F_FRM_ERR_INT    V_FRM_ERR_INT(1U)
35068 
35069 #define S_LEN_ERR_INT    13
35070 #define V_LEN_ERR_INT(x) ((x) << S_LEN_ERR_INT)
35071 #define F_LEN_ERR_INT    V_LEN_ERR_INT(1U)
35072 
35073 #define A_MPS_RX_FUNC_INT_ENABLE 0x11088
35074 #define A_MPS_RX_PAUSE_GEN_TH_0 0x1108c
35075 
35076 #define S_TH_HIGH    16
35077 #define M_TH_HIGH    0xffffU
35078 #define V_TH_HIGH(x) ((x) << S_TH_HIGH)
35079 #define G_TH_HIGH(x) (((x) >> S_TH_HIGH) & M_TH_HIGH)
35080 
35081 #define S_TH_LOW    0
35082 #define M_TH_LOW    0xffffU
35083 #define V_TH_LOW(x) ((x) << S_TH_LOW)
35084 #define G_TH_LOW(x) (((x) >> S_TH_LOW) & M_TH_LOW)
35085 
35086 #define A_MPS_RX_PAUSE_GEN_TH_1 0x11090
35087 #define A_MPS_RX_PAUSE_GEN_TH_2 0x11094
35088 #define A_MPS_RX_PAUSE_GEN_TH_3 0x11098
35089 #define A_MPS_RX_REPL_CTL 0x11098
35090 
35091 #define S_INDEX_SEL    0
35092 #define V_INDEX_SEL(x) ((x) << S_INDEX_SEL)
35093 #define F_INDEX_SEL    V_INDEX_SEL(1U)
35094 
35095 #define A_MPS_RX_PPP_ATRB 0x1109c
35096 
35097 #define S_ETYPE    16
35098 #define M_ETYPE    0xffffU
35099 #define V_ETYPE(x) ((x) << S_ETYPE)
35100 #define G_ETYPE(x) (((x) >> S_ETYPE) & M_ETYPE)
35101 
35102 #define S_OPCODE    0
35103 #define M_OPCODE    0xffffU
35104 #define V_OPCODE(x) ((x) << S_OPCODE)
35105 #define G_OPCODE(x) (((x) >> S_OPCODE) & M_OPCODE)
35106 
35107 #define A_MPS_RX_QFC0_ATRB 0x110a0
35108 
35109 #define S_DA    0
35110 #define M_DA    0xffffU
35111 #define V_DA(x) ((x) << S_DA)
35112 #define G_DA(x) (((x) >> S_DA) & M_DA)
35113 
35114 #define A_MPS_RX_QFC1_ATRB 0x110a4
35115 #define A_MPS_RX_PT_ARB0 0x110a8
35116 
35117 #define S_LPBK_WT    16
35118 #define M_LPBK_WT    0x3fffU
35119 #define V_LPBK_WT(x) ((x) << S_LPBK_WT)
35120 #define G_LPBK_WT(x) (((x) >> S_LPBK_WT) & M_LPBK_WT)
35121 
35122 #define S_MAC_WT    0
35123 #define M_MAC_WT    0x3fffU
35124 #define V_MAC_WT(x) ((x) << S_MAC_WT)
35125 #define G_MAC_WT(x) (((x) >> S_MAC_WT) & M_MAC_WT)
35126 
35127 #define A_MPS_RX_PT_ARB1 0x110ac
35128 #define A_MPS_RX_PT_ARB2 0x110b0
35129 #define A_MPS_RX_PT_ARB3 0x110b4
35130 #define A_T6_MPS_PF_OUT_EN 0x110b4
35131 #define A_MPS_RX_PT_ARB4 0x110b8
35132 #define A_T6_MPS_BMC_MTU 0x110b8
35133 #define A_MPS_PF_OUT_EN 0x110bc
35134 
35135 #define S_OUTEN    0
35136 #define M_OUTEN    0xffU
35137 #define V_OUTEN(x) ((x) << S_OUTEN)
35138 #define G_OUTEN(x) (((x) >> S_OUTEN) & M_OUTEN)
35139 
35140 #define A_T6_MPS_BMC_PKT_CNT 0x110bc
35141 #define A_MPS_BMC_MTU 0x110c0
35142 
35143 #define S_MTU    0
35144 #define M_MTU    0x3fffU
35145 #define V_MTU(x) ((x) << S_MTU)
35146 #define G_MTU(x) (((x) >> S_MTU) & M_MTU)
35147 
35148 #define A_T6_MPS_BMC_BYTE_CNT 0x110c0
35149 #define A_MPS_BMC_PKT_CNT 0x110c4
35150 #define A_T6_MPS_PFVF_ATRB_CTL 0x110c4
35151 
35152 #define S_T6_PFVF    0
35153 #define M_T6_PFVF    0x1ffU
35154 #define V_T6_PFVF(x) ((x) << S_T6_PFVF)
35155 #define G_T6_PFVF(x) (((x) >> S_T6_PFVF) & M_T6_PFVF)
35156 
35157 #define A_MPS_BMC_BYTE_CNT 0x110c8
35158 #define A_T6_MPS_PFVF_ATRB 0x110c8
35159 
35160 #define S_FULL_FRAME_MODE    14
35161 #define V_FULL_FRAME_MODE(x) ((x) << S_FULL_FRAME_MODE)
35162 #define F_FULL_FRAME_MODE    V_FULL_FRAME_MODE(1U)
35163 
35164 #define A_MPS_PFVF_ATRB_CTL 0x110cc
35165 
35166 #define S_RD_WRN    31
35167 #define V_RD_WRN(x) ((x) << S_RD_WRN)
35168 #define F_RD_WRN    V_RD_WRN(1U)
35169 
35170 #define S_PFVF    0
35171 #define M_PFVF    0xffU
35172 #define V_PFVF(x) ((x) << S_PFVF)
35173 #define G_PFVF(x) (((x) >> S_PFVF) & M_PFVF)
35174 
35175 #define A_T6_MPS_PFVF_ATRB_FLTR0 0x110cc
35176 #define A_MPS_PFVF_ATRB 0x110d0
35177 
35178 #define S_ATTR_PF    28
35179 #define M_ATTR_PF    0x7U
35180 #define V_ATTR_PF(x) ((x) << S_ATTR_PF)
35181 #define G_ATTR_PF(x) (((x) >> S_ATTR_PF) & M_ATTR_PF)
35182 
35183 #define S_OFF    18
35184 #define V_OFF(x) ((x) << S_OFF)
35185 #define F_OFF    V_OFF(1U)
35186 
35187 #define S_NV_DROP    17
35188 #define V_NV_DROP(x) ((x) << S_NV_DROP)
35189 #define F_NV_DROP    V_NV_DROP(1U)
35190 
35191 #define S_ATTR_MODE    16
35192 #define V_ATTR_MODE(x) ((x) << S_ATTR_MODE)
35193 #define F_ATTR_MODE    V_ATTR_MODE(1U)
35194 
35195 #define A_T6_MPS_PFVF_ATRB_FLTR1 0x110d0
35196 #define A_MPS_PFVF_ATRB_FLTR0 0x110d4
35197 
35198 #define S_VLAN_EN    16
35199 #define V_VLAN_EN(x) ((x) << S_VLAN_EN)
35200 #define F_VLAN_EN    V_VLAN_EN(1U)
35201 
35202 #define S_VLAN_ID    0
35203 #define M_VLAN_ID    0xfffU
35204 #define V_VLAN_ID(x) ((x) << S_VLAN_ID)
35205 #define G_VLAN_ID(x) (((x) >> S_VLAN_ID) & M_VLAN_ID)
35206 
35207 #define A_T6_MPS_PFVF_ATRB_FLTR2 0x110d4
35208 #define A_MPS_PFVF_ATRB_FLTR1 0x110d8
35209 #define A_T6_MPS_PFVF_ATRB_FLTR3 0x110d8
35210 #define A_MPS_PFVF_ATRB_FLTR2 0x110dc
35211 #define A_T6_MPS_PFVF_ATRB_FLTR4 0x110dc
35212 #define A_MPS_PFVF_ATRB_FLTR3 0x110e0
35213 #define A_T6_MPS_PFVF_ATRB_FLTR5 0x110e0
35214 #define A_MPS_PFVF_ATRB_FLTR4 0x110e4
35215 #define A_T6_MPS_PFVF_ATRB_FLTR6 0x110e4
35216 #define A_MPS_PFVF_ATRB_FLTR5 0x110e8
35217 #define A_T6_MPS_PFVF_ATRB_FLTR7 0x110e8
35218 #define A_MPS_PFVF_ATRB_FLTR6 0x110ec
35219 #define A_T6_MPS_PFVF_ATRB_FLTR8 0x110ec
35220 #define A_MPS_PFVF_ATRB_FLTR7 0x110f0
35221 #define A_T6_MPS_PFVF_ATRB_FLTR9 0x110f0
35222 #define A_MPS_PFVF_ATRB_FLTR8 0x110f4
35223 #define A_T6_MPS_PFVF_ATRB_FLTR10 0x110f4
35224 #define A_MPS_PFVF_ATRB_FLTR9 0x110f8
35225 #define A_T6_MPS_PFVF_ATRB_FLTR11 0x110f8
35226 #define A_MPS_PFVF_ATRB_FLTR10 0x110fc
35227 #define A_T6_MPS_PFVF_ATRB_FLTR12 0x110fc
35228 #define A_MPS_PFVF_ATRB_FLTR11 0x11100
35229 #define A_T6_MPS_PFVF_ATRB_FLTR13 0x11100
35230 #define A_MPS_PFVF_ATRB_FLTR12 0x11104
35231 #define A_T6_MPS_PFVF_ATRB_FLTR14 0x11104
35232 #define A_MPS_PFVF_ATRB_FLTR13 0x11108
35233 #define A_T6_MPS_PFVF_ATRB_FLTR15 0x11108
35234 #define A_MPS_PFVF_ATRB_FLTR14 0x1110c
35235 #define A_T6_MPS_RPLC_MAP_CTL 0x1110c
35236 #define A_MPS_PFVF_ATRB_FLTR15 0x11110
35237 #define A_T6_MPS_PF_RPLCT_MAP 0x11110
35238 #define A_MPS_RPLC_MAP_CTL 0x11114
35239 
35240 #define S_RPLC_MAP_ADDR    0
35241 #define M_RPLC_MAP_ADDR    0x3ffU
35242 #define V_RPLC_MAP_ADDR(x) ((x) << S_RPLC_MAP_ADDR)
35243 #define G_RPLC_MAP_ADDR(x) (((x) >> S_RPLC_MAP_ADDR) & M_RPLC_MAP_ADDR)
35244 
35245 #define A_T6_MPS_VF_RPLCT_MAP0 0x11114
35246 #define A_MPS_PF_RPLCT_MAP 0x11118
35247 
35248 #define S_PF_EN    0
35249 #define M_PF_EN    0xffU
35250 #define V_PF_EN(x) ((x) << S_PF_EN)
35251 #define G_PF_EN(x) (((x) >> S_PF_EN) & M_PF_EN)
35252 
35253 #define A_T6_MPS_VF_RPLCT_MAP1 0x11118
35254 #define A_MPS_VF_RPLCT_MAP0 0x1111c
35255 #define A_T6_MPS_VF_RPLCT_MAP2 0x1111c
35256 #define A_MPS_VF_RPLCT_MAP1 0x11120
35257 #define A_T6_MPS_VF_RPLCT_MAP3 0x11120
35258 #define A_MPS_VF_RPLCT_MAP2 0x11124
35259 #define A_MPS_VF_RPLCT_MAP3 0x11128
35260 #define A_MPS_MEM_DBG_CTL 0x1112c
35261 
35262 #define S_PKD    17
35263 #define V_PKD(x) ((x) << S_PKD)
35264 #define F_PKD    V_PKD(1U)
35265 
35266 #define S_PGD    16
35267 #define V_PGD(x) ((x) << S_PGD)
35268 #define F_PGD    V_PGD(1U)
35269 
35270 #define A_MPS_PKD_MEM_DATA0 0x11130
35271 #define A_MPS_PKD_MEM_DATA1 0x11134
35272 #define A_MPS_PKD_MEM_DATA2 0x11138
35273 #define A_MPS_PGD_MEM_DATA 0x1113c
35274 #define A_MPS_RX_SE_CNT_ERR 0x11140
35275 
35276 #define S_RX_SE_ERRMAP    0
35277 #define M_RX_SE_ERRMAP    0xfffffU
35278 #define V_RX_SE_ERRMAP(x) ((x) << S_RX_SE_ERRMAP)
35279 #define G_RX_SE_ERRMAP(x) (((x) >> S_RX_SE_ERRMAP) & M_RX_SE_ERRMAP)
35280 
35281 #define A_MPS_RX_SE_CNT_CLR 0x11144
35282 #define A_MPS_RX_SE_CNT_IN0 0x11148
35283 
35284 #define S_SOP_CNT_PM    24
35285 #define M_SOP_CNT_PM    0xffU
35286 #define V_SOP_CNT_PM(x) ((x) << S_SOP_CNT_PM)
35287 #define G_SOP_CNT_PM(x) (((x) >> S_SOP_CNT_PM) & M_SOP_CNT_PM)
35288 
35289 #define S_EOP_CNT_PM    16
35290 #define M_EOP_CNT_PM    0xffU
35291 #define V_EOP_CNT_PM(x) ((x) << S_EOP_CNT_PM)
35292 #define G_EOP_CNT_PM(x) (((x) >> S_EOP_CNT_PM) & M_EOP_CNT_PM)
35293 
35294 #define S_SOP_CNT_IN    8
35295 #define M_SOP_CNT_IN    0xffU
35296 #define V_SOP_CNT_IN(x) ((x) << S_SOP_CNT_IN)
35297 #define G_SOP_CNT_IN(x) (((x) >> S_SOP_CNT_IN) & M_SOP_CNT_IN)
35298 
35299 #define S_EOP_CNT_IN    0
35300 #define M_EOP_CNT_IN    0xffU
35301 #define V_EOP_CNT_IN(x) ((x) << S_EOP_CNT_IN)
35302 #define G_EOP_CNT_IN(x) (((x) >> S_EOP_CNT_IN) & M_EOP_CNT_IN)
35303 
35304 #define A_MPS_RX_SE_CNT_IN1 0x1114c
35305 #define A_MPS_RX_SE_CNT_IN2 0x11150
35306 #define A_MPS_RX_SE_CNT_IN3 0x11154
35307 #define A_MPS_RX_SE_CNT_IN4 0x11158
35308 #define A_MPS_RX_SE_CNT_IN5 0x1115c
35309 #define A_MPS_RX_SE_CNT_IN6 0x11160
35310 #define A_MPS_RX_SE_CNT_IN7 0x11164
35311 #define A_MPS_RX_SE_CNT_OUT01 0x11168
35312 
35313 #define S_SOP_CNT_1    24
35314 #define M_SOP_CNT_1    0xffU
35315 #define V_SOP_CNT_1(x) ((x) << S_SOP_CNT_1)
35316 #define G_SOP_CNT_1(x) (((x) >> S_SOP_CNT_1) & M_SOP_CNT_1)
35317 
35318 #define S_EOP_CNT_1    16
35319 #define M_EOP_CNT_1    0xffU
35320 #define V_EOP_CNT_1(x) ((x) << S_EOP_CNT_1)
35321 #define G_EOP_CNT_1(x) (((x) >> S_EOP_CNT_1) & M_EOP_CNT_1)
35322 
35323 #define S_SOP_CNT_0    8
35324 #define M_SOP_CNT_0    0xffU
35325 #define V_SOP_CNT_0(x) ((x) << S_SOP_CNT_0)
35326 #define G_SOP_CNT_0(x) (((x) >> S_SOP_CNT_0) & M_SOP_CNT_0)
35327 
35328 #define S_EOP_CNT_0    0
35329 #define M_EOP_CNT_0    0xffU
35330 #define V_EOP_CNT_0(x) ((x) << S_EOP_CNT_0)
35331 #define G_EOP_CNT_0(x) (((x) >> S_EOP_CNT_0) & M_EOP_CNT_0)
35332 
35333 #define A_MPS_RX_SE_CNT_OUT23 0x1116c
35334 
35335 #define S_SOP_CNT_3    24
35336 #define M_SOP_CNT_3    0xffU
35337 #define V_SOP_CNT_3(x) ((x) << S_SOP_CNT_3)
35338 #define G_SOP_CNT_3(x) (((x) >> S_SOP_CNT_3) & M_SOP_CNT_3)
35339 
35340 #define S_EOP_CNT_3    16
35341 #define M_EOP_CNT_3    0xffU
35342 #define V_EOP_CNT_3(x) ((x) << S_EOP_CNT_3)
35343 #define G_EOP_CNT_3(x) (((x) >> S_EOP_CNT_3) & M_EOP_CNT_3)
35344 
35345 #define S_SOP_CNT_2    8
35346 #define M_SOP_CNT_2    0xffU
35347 #define V_SOP_CNT_2(x) ((x) << S_SOP_CNT_2)
35348 #define G_SOP_CNT_2(x) (((x) >> S_SOP_CNT_2) & M_SOP_CNT_2)
35349 
35350 #define S_EOP_CNT_2    0
35351 #define M_EOP_CNT_2    0xffU
35352 #define V_EOP_CNT_2(x) ((x) << S_EOP_CNT_2)
35353 #define G_EOP_CNT_2(x) (((x) >> S_EOP_CNT_2) & M_EOP_CNT_2)
35354 
35355 #define A_MPS_RX_SPI_ERR 0x11170
35356 
35357 #define S_LENERR    21
35358 #define M_LENERR    0xfU
35359 #define V_LENERR(x) ((x) << S_LENERR)
35360 #define G_LENERR(x) (((x) >> S_LENERR) & M_LENERR)
35361 
35362 #define S_SPIERR    0
35363 #define M_SPIERR    0x1fffffU
35364 #define V_SPIERR(x) ((x) << S_SPIERR)
35365 #define G_SPIERR(x) (((x) >> S_SPIERR) & M_SPIERR)
35366 
35367 #define A_MPS_RX_IN_BUS_STATE 0x11174
35368 
35369 #define S_ST3    24
35370 #define M_ST3    0xffU
35371 #define V_ST3(x) ((x) << S_ST3)
35372 #define G_ST3(x) (((x) >> S_ST3) & M_ST3)
35373 
35374 #define S_ST2    16
35375 #define M_ST2    0xffU
35376 #define V_ST2(x) ((x) << S_ST2)
35377 #define G_ST2(x) (((x) >> S_ST2) & M_ST2)
35378 
35379 #define S_ST1    8
35380 #define M_ST1    0xffU
35381 #define V_ST1(x) ((x) << S_ST1)
35382 #define G_ST1(x) (((x) >> S_ST1) & M_ST1)
35383 
35384 #define S_ST0    0
35385 #define M_ST0    0xffU
35386 #define V_ST0(x) ((x) << S_ST0)
35387 #define G_ST0(x) (((x) >> S_ST0) & M_ST0)
35388 
35389 #define A_MPS_RX_OUT_BUS_STATE 0x11178
35390 
35391 #define S_ST_NCSI    23
35392 #define M_ST_NCSI    0x1ffU
35393 #define V_ST_NCSI(x) ((x) << S_ST_NCSI)
35394 #define G_ST_NCSI(x) (((x) >> S_ST_NCSI) & M_ST_NCSI)
35395 
35396 #define S_ST_TP    0
35397 #define M_ST_TP    0x7fffffU
35398 #define V_ST_TP(x) ((x) << S_ST_TP)
35399 #define G_ST_TP(x) (((x) >> S_ST_TP) & M_ST_TP)
35400 
35401 #define A_MPS_RX_DBG_CTL 0x1117c
35402 
35403 #define S_OUT_DBG_CHNL    8
35404 #define M_OUT_DBG_CHNL    0x7U
35405 #define V_OUT_DBG_CHNL(x) ((x) << S_OUT_DBG_CHNL)
35406 #define G_OUT_DBG_CHNL(x) (((x) >> S_OUT_DBG_CHNL) & M_OUT_DBG_CHNL)
35407 
35408 #define S_DBG_PKD_QSEL    7
35409 #define V_DBG_PKD_QSEL(x) ((x) << S_DBG_PKD_QSEL)
35410 #define F_DBG_PKD_QSEL    V_DBG_PKD_QSEL(1U)
35411 
35412 #define S_DBG_CDS_INV    6
35413 #define V_DBG_CDS_INV(x) ((x) << S_DBG_CDS_INV)
35414 #define F_DBG_CDS_INV    V_DBG_CDS_INV(1U)
35415 
35416 #define S_IN_DBG_PORT    3
35417 #define M_IN_DBG_PORT    0x7U
35418 #define V_IN_DBG_PORT(x) ((x) << S_IN_DBG_PORT)
35419 #define G_IN_DBG_PORT(x) (((x) >> S_IN_DBG_PORT) & M_IN_DBG_PORT)
35420 
35421 #define S_IN_DBG_CHNL    0
35422 #define M_IN_DBG_CHNL    0x7U
35423 #define V_IN_DBG_CHNL(x) ((x) << S_IN_DBG_CHNL)
35424 #define G_IN_DBG_CHNL(x) (((x) >> S_IN_DBG_CHNL) & M_IN_DBG_CHNL)
35425 
35426 #define A_MPS_RX_CLS_DROP_CNT0 0x11180
35427 
35428 #define S_LPBK_CNT0    16
35429 #define M_LPBK_CNT0    0xffffU
35430 #define V_LPBK_CNT0(x) ((x) << S_LPBK_CNT0)
35431 #define G_LPBK_CNT0(x) (((x) >> S_LPBK_CNT0) & M_LPBK_CNT0)
35432 
35433 #define S_MAC_CNT0    0
35434 #define M_MAC_CNT0    0xffffU
35435 #define V_MAC_CNT0(x) ((x) << S_MAC_CNT0)
35436 #define G_MAC_CNT0(x) (((x) >> S_MAC_CNT0) & M_MAC_CNT0)
35437 
35438 #define A_MPS_RX_CLS_DROP_CNT1 0x11184
35439 
35440 #define S_LPBK_CNT1    16
35441 #define M_LPBK_CNT1    0xffffU
35442 #define V_LPBK_CNT1(x) ((x) << S_LPBK_CNT1)
35443 #define G_LPBK_CNT1(x) (((x) >> S_LPBK_CNT1) & M_LPBK_CNT1)
35444 
35445 #define S_MAC_CNT1    0
35446 #define M_MAC_CNT1    0xffffU
35447 #define V_MAC_CNT1(x) ((x) << S_MAC_CNT1)
35448 #define G_MAC_CNT1(x) (((x) >> S_MAC_CNT1) & M_MAC_CNT1)
35449 
35450 #define A_MPS_RX_CLS_DROP_CNT2 0x11188
35451 
35452 #define S_LPBK_CNT2    16
35453 #define M_LPBK_CNT2    0xffffU
35454 #define V_LPBK_CNT2(x) ((x) << S_LPBK_CNT2)
35455 #define G_LPBK_CNT2(x) (((x) >> S_LPBK_CNT2) & M_LPBK_CNT2)
35456 
35457 #define S_MAC_CNT2    0
35458 #define M_MAC_CNT2    0xffffU
35459 #define V_MAC_CNT2(x) ((x) << S_MAC_CNT2)
35460 #define G_MAC_CNT2(x) (((x) >> S_MAC_CNT2) & M_MAC_CNT2)
35461 
35462 #define A_MPS_RX_CLS_DROP_CNT3 0x1118c
35463 
35464 #define S_LPBK_CNT3    16
35465 #define M_LPBK_CNT3    0xffffU
35466 #define V_LPBK_CNT3(x) ((x) << S_LPBK_CNT3)
35467 #define G_LPBK_CNT3(x) (((x) >> S_LPBK_CNT3) & M_LPBK_CNT3)
35468 
35469 #define S_MAC_CNT3    0
35470 #define M_MAC_CNT3    0xffffU
35471 #define V_MAC_CNT3(x) ((x) << S_MAC_CNT3)
35472 #define G_MAC_CNT3(x) (((x) >> S_MAC_CNT3) & M_MAC_CNT3)
35473 
35474 #define A_MPS_RX_SPARE 0x11190
35475 #define A_MPS_RX_PTP_ETYPE 0x11194
35476 
35477 #define S_PETYPE2    16
35478 #define M_PETYPE2    0xffffU
35479 #define V_PETYPE2(x) ((x) << S_PETYPE2)
35480 #define G_PETYPE2(x) (((x) >> S_PETYPE2) & M_PETYPE2)
35481 
35482 #define S_PETYPE1    0
35483 #define M_PETYPE1    0xffffU
35484 #define V_PETYPE1(x) ((x) << S_PETYPE1)
35485 #define G_PETYPE1(x) (((x) >> S_PETYPE1) & M_PETYPE1)
35486 
35487 #define A_MPS_RX_PTP_TCP 0x11198
35488 
35489 #define S_PTCPORT2    16
35490 #define M_PTCPORT2    0xffffU
35491 #define V_PTCPORT2(x) ((x) << S_PTCPORT2)
35492 #define G_PTCPORT2(x) (((x) >> S_PTCPORT2) & M_PTCPORT2)
35493 
35494 #define S_PTCPORT1    0
35495 #define M_PTCPORT1    0xffffU
35496 #define V_PTCPORT1(x) ((x) << S_PTCPORT1)
35497 #define G_PTCPORT1(x) (((x) >> S_PTCPORT1) & M_PTCPORT1)
35498 
35499 #define A_MPS_RX_PTP_UDP 0x1119c
35500 
35501 #define S_PUDPORT2    16
35502 #define M_PUDPORT2    0xffffU
35503 #define V_PUDPORT2(x) ((x) << S_PUDPORT2)
35504 #define G_PUDPORT2(x) (((x) >> S_PUDPORT2) & M_PUDPORT2)
35505 
35506 #define S_PUDPORT1    0
35507 #define M_PUDPORT1    0xffffU
35508 #define V_PUDPORT1(x) ((x) << S_PUDPORT1)
35509 #define G_PUDPORT1(x) (((x) >> S_PUDPORT1) & M_PUDPORT1)
35510 
35511 #define A_MPS_RX_PTP_CTL 0x111a0
35512 
35513 #define S_MIN_PTP_SPACE    24
35514 #define M_MIN_PTP_SPACE    0x7fU
35515 #define V_MIN_PTP_SPACE(x) ((x) << S_MIN_PTP_SPACE)
35516 #define G_MIN_PTP_SPACE(x) (((x) >> S_MIN_PTP_SPACE) & M_MIN_PTP_SPACE)
35517 
35518 #define S_PUDP2EN    20
35519 #define M_PUDP2EN    0xfU
35520 #define V_PUDP2EN(x) ((x) << S_PUDP2EN)
35521 #define G_PUDP2EN(x) (((x) >> S_PUDP2EN) & M_PUDP2EN)
35522 
35523 #define S_PUDP1EN    16
35524 #define M_PUDP1EN    0xfU
35525 #define V_PUDP1EN(x) ((x) << S_PUDP1EN)
35526 #define G_PUDP1EN(x) (((x) >> S_PUDP1EN) & M_PUDP1EN)
35527 
35528 #define S_PTCP2EN    12
35529 #define M_PTCP2EN    0xfU
35530 #define V_PTCP2EN(x) ((x) << S_PTCP2EN)
35531 #define G_PTCP2EN(x) (((x) >> S_PTCP2EN) & M_PTCP2EN)
35532 
35533 #define S_PTCP1EN    8
35534 #define M_PTCP1EN    0xfU
35535 #define V_PTCP1EN(x) ((x) << S_PTCP1EN)
35536 #define G_PTCP1EN(x) (((x) >> S_PTCP1EN) & M_PTCP1EN)
35537 
35538 #define S_PETYPE2EN    4
35539 #define M_PETYPE2EN    0xfU
35540 #define V_PETYPE2EN(x) ((x) << S_PETYPE2EN)
35541 #define G_PETYPE2EN(x) (((x) >> S_PETYPE2EN) & M_PETYPE2EN)
35542 
35543 #define S_PETYPE1EN    0
35544 #define M_PETYPE1EN    0xfU
35545 #define V_PETYPE1EN(x) ((x) << S_PETYPE1EN)
35546 #define G_PETYPE1EN(x) (((x) >> S_PETYPE1EN) & M_PETYPE1EN)
35547 
35548 #define A_MPS_RX_PAUSE_GEN_TH_0_0 0x111a4
35549 #define A_MPS_RX_PAUSE_GEN_TH_0_1 0x111a8
35550 #define A_MPS_RX_PAUSE_GEN_TH_0_2 0x111ac
35551 #define A_MPS_RX_PAUSE_GEN_TH_0_3 0x111b0
35552 #define A_MPS_RX_PAUSE_GEN_TH_1_0 0x111b4
35553 #define A_MPS_RX_PAUSE_GEN_TH_1_1 0x111b8
35554 #define A_MPS_RX_PAUSE_GEN_TH_1_2 0x111bc
35555 #define A_MPS_RX_PAUSE_GEN_TH_1_3 0x111c0
35556 #define A_MPS_RX_PAUSE_GEN_TH_2_0 0x111c4
35557 #define A_MPS_RX_PAUSE_GEN_TH_2_1 0x111c8
35558 #define A_MPS_RX_PAUSE_GEN_TH_2_2 0x111cc
35559 #define A_MPS_RX_PAUSE_GEN_TH_2_3 0x111d0
35560 #define A_MPS_RX_PAUSE_GEN_TH_3_0 0x111d4
35561 #define A_MPS_RX_PAUSE_GEN_TH_3_1 0x111d8
35562 #define A_MPS_RX_PAUSE_GEN_TH_3_2 0x111dc
35563 #define A_MPS_RX_PAUSE_GEN_TH_3_3 0x111e0
35564 #define A_MPS_RX_MAC_CLS_DROP_CNT0 0x111e4
35565 #define A_MPS_RX_MAC_CLS_DROP_CNT1 0x111e8
35566 #define A_MPS_RX_MAC_CLS_DROP_CNT2 0x111ec
35567 #define A_MPS_RX_MAC_CLS_DROP_CNT3 0x111f0
35568 #define A_MPS_RX_LPBK_CLS_DROP_CNT0 0x111f4
35569 #define A_MPS_RX_LPBK_CLS_DROP_CNT1 0x111f8
35570 #define A_MPS_RX_LPBK_CLS_DROP_CNT2 0x111fc
35571 #define A_MPS_RX_LPBK_CLS_DROP_CNT3 0x11200
35572 #define A_MPS_RX_CGEN 0x11204
35573 
35574 #define S_MPS_RX_CGEN_NCSI    12
35575 #define V_MPS_RX_CGEN_NCSI(x) ((x) << S_MPS_RX_CGEN_NCSI)
35576 #define F_MPS_RX_CGEN_NCSI    V_MPS_RX_CGEN_NCSI(1U)
35577 
35578 #define S_MPS_RX_CGEN_OUT    8
35579 #define M_MPS_RX_CGEN_OUT    0xfU
35580 #define V_MPS_RX_CGEN_OUT(x) ((x) << S_MPS_RX_CGEN_OUT)
35581 #define G_MPS_RX_CGEN_OUT(x) (((x) >> S_MPS_RX_CGEN_OUT) & M_MPS_RX_CGEN_OUT)
35582 
35583 #define S_MPS_RX_CGEN_LPBK_IN    4
35584 #define M_MPS_RX_CGEN_LPBK_IN    0xfU
35585 #define V_MPS_RX_CGEN_LPBK_IN(x) ((x) << S_MPS_RX_CGEN_LPBK_IN)
35586 #define G_MPS_RX_CGEN_LPBK_IN(x) (((x) >> S_MPS_RX_CGEN_LPBK_IN) & M_MPS_RX_CGEN_LPBK_IN)
35587 
35588 #define S_MPS_RX_CGEN_MAC_IN    0
35589 #define M_MPS_RX_CGEN_MAC_IN    0xfU
35590 #define V_MPS_RX_CGEN_MAC_IN(x) ((x) << S_MPS_RX_CGEN_MAC_IN)
35591 #define G_MPS_RX_CGEN_MAC_IN(x) (((x) >> S_MPS_RX_CGEN_MAC_IN) & M_MPS_RX_CGEN_MAC_IN)
35592 
35593 #define A_MPS_RX_MAC_BG_PG_CNT0 0x11208
35594 
35595 #define S_MAC_USED    16
35596 #define M_MAC_USED    0x7ffU
35597 #define V_MAC_USED(x) ((x) << S_MAC_USED)
35598 #define G_MAC_USED(x) (((x) >> S_MAC_USED) & M_MAC_USED)
35599 
35600 #define S_MAC_ALLOC    0
35601 #define M_MAC_ALLOC    0x7ffU
35602 #define V_MAC_ALLOC(x) ((x) << S_MAC_ALLOC)
35603 #define G_MAC_ALLOC(x) (((x) >> S_MAC_ALLOC) & M_MAC_ALLOC)
35604 
35605 #define A_MPS_RX_MAC_BG_PG_CNT1 0x1120c
35606 #define A_MPS_RX_MAC_BG_PG_CNT2 0x11210
35607 #define A_MPS_RX_MAC_BG_PG_CNT3 0x11214
35608 #define A_MPS_RX_LPBK_BG_PG_CNT0 0x11218
35609 
35610 #define S_LPBK_USED    16
35611 #define M_LPBK_USED    0x7ffU
35612 #define V_LPBK_USED(x) ((x) << S_LPBK_USED)
35613 #define G_LPBK_USED(x) (((x) >> S_LPBK_USED) & M_LPBK_USED)
35614 
35615 #define S_LPBK_ALLOC    0
35616 #define M_LPBK_ALLOC    0x7ffU
35617 #define V_LPBK_ALLOC(x) ((x) << S_LPBK_ALLOC)
35618 #define G_LPBK_ALLOC(x) (((x) >> S_LPBK_ALLOC) & M_LPBK_ALLOC)
35619 
35620 #define A_MPS_RX_LPBK_BG_PG_CNT1 0x1121c
35621 #define A_MPS_RX_CONGESTION_THRESHOLD_BG0 0x11220
35622 
35623 #define S_CONG_EN    31
35624 #define V_CONG_EN(x) ((x) << S_CONG_EN)
35625 #define F_CONG_EN    V_CONG_EN(1U)
35626 
35627 #define S_CONG_TH    0
35628 #define M_CONG_TH    0xfffffU
35629 #define V_CONG_TH(x) ((x) << S_CONG_TH)
35630 #define G_CONG_TH(x) (((x) >> S_CONG_TH) & M_CONG_TH)
35631 
35632 #define A_MPS_RX_CONGESTION_THRESHOLD_BG1 0x11224
35633 #define A_MPS_RX_CONGESTION_THRESHOLD_BG2 0x11228
35634 #define A_MPS_RX_CONGESTION_THRESHOLD_BG3 0x1122c
35635 #define A_MPS_RX_GRE_PROT_TYPE 0x11230
35636 
35637 #define S_NVGRE_EN    9
35638 #define V_NVGRE_EN(x) ((x) << S_NVGRE_EN)
35639 #define F_NVGRE_EN    V_NVGRE_EN(1U)
35640 
35641 #define S_GRE_EN    8
35642 #define V_GRE_EN(x) ((x) << S_GRE_EN)
35643 #define F_GRE_EN    V_GRE_EN(1U)
35644 
35645 #define S_GRE    0
35646 #define M_GRE    0xffU
35647 #define V_GRE(x) ((x) << S_GRE)
35648 #define G_GRE(x) (((x) >> S_GRE) & M_GRE)
35649 
35650 #define A_MPS_RX_VXLAN_TYPE 0x11234
35651 
35652 #define S_VXLAN_EN    16
35653 #define V_VXLAN_EN(x) ((x) << S_VXLAN_EN)
35654 #define F_VXLAN_EN    V_VXLAN_EN(1U)
35655 
35656 #define S_VXLAN    0
35657 #define M_VXLAN    0xffffU
35658 #define V_VXLAN(x) ((x) << S_VXLAN)
35659 #define G_VXLAN(x) (((x) >> S_VXLAN) & M_VXLAN)
35660 
35661 #define A_MPS_RX_GENEVE_TYPE 0x11238
35662 
35663 #define S_GENEVE_EN    16
35664 #define V_GENEVE_EN(x) ((x) << S_GENEVE_EN)
35665 #define F_GENEVE_EN    V_GENEVE_EN(1U)
35666 
35667 #define S_GENEVE    0
35668 #define M_GENEVE    0xffffU
35669 #define V_GENEVE(x) ((x) << S_GENEVE)
35670 #define G_GENEVE(x) (((x) >> S_GENEVE) & M_GENEVE)
35671 
35672 #define A_MPS_RX_INNER_HDR_IVLAN 0x1123c
35673 
35674 #define S_T6_IVLAN_EN    16
35675 #define V_T6_IVLAN_EN(x) ((x) << S_T6_IVLAN_EN)
35676 #define F_T6_IVLAN_EN    V_T6_IVLAN_EN(1U)
35677 
35678 #define A_MPS_RX_ENCAP_NVGRE 0x11240
35679 
35680 #define S_ETYPE_EN    16
35681 #define V_ETYPE_EN(x) ((x) << S_ETYPE_EN)
35682 #define F_ETYPE_EN    V_ETYPE_EN(1U)
35683 
35684 #define S_T6_ETYPE    0
35685 #define M_T6_ETYPE    0xffffU
35686 #define V_T6_ETYPE(x) ((x) << S_T6_ETYPE)
35687 #define G_T6_ETYPE(x) (((x) >> S_T6_ETYPE) & M_T6_ETYPE)
35688 
35689 #define A_MPS_RX_ENCAP_GENEVE 0x11244
35690 
35691 #define S_T6_ETYPE    0
35692 #define M_T6_ETYPE    0xffffU
35693 #define V_T6_ETYPE(x) ((x) << S_T6_ETYPE)
35694 #define G_T6_ETYPE(x) (((x) >> S_T6_ETYPE) & M_T6_ETYPE)
35695 
35696 #define A_MPS_RX_TCP 0x11248
35697 
35698 #define S_PROT_TYPE_EN    8
35699 #define V_PROT_TYPE_EN(x) ((x) << S_PROT_TYPE_EN)
35700 #define F_PROT_TYPE_EN    V_PROT_TYPE_EN(1U)
35701 
35702 #define S_PROT_TYPE    0
35703 #define M_PROT_TYPE    0xffU
35704 #define V_PROT_TYPE(x) ((x) << S_PROT_TYPE)
35705 #define G_PROT_TYPE(x) (((x) >> S_PROT_TYPE) & M_PROT_TYPE)
35706 
35707 #define A_MPS_RX_UDP 0x1124c
35708 #define A_MPS_RX_PAUSE 0x11250
35709 #define A_MPS_RX_LENGTH 0x11254
35710 
35711 #define S_SAP_VALUE    16
35712 #define M_SAP_VALUE    0xffffU
35713 #define V_SAP_VALUE(x) ((x) << S_SAP_VALUE)
35714 #define G_SAP_VALUE(x) (((x) >> S_SAP_VALUE) & M_SAP_VALUE)
35715 
35716 #define S_LENGTH_ETYPE    0
35717 #define M_LENGTH_ETYPE    0xffffU
35718 #define V_LENGTH_ETYPE(x) ((x) << S_LENGTH_ETYPE)
35719 #define G_LENGTH_ETYPE(x) (((x) >> S_LENGTH_ETYPE) & M_LENGTH_ETYPE)
35720 
35721 #define A_MPS_RX_CTL_ORG 0x11258
35722 
35723 #define S_CTL_VALUE    24
35724 #define M_CTL_VALUE    0xffU
35725 #define V_CTL_VALUE(x) ((x) << S_CTL_VALUE)
35726 #define G_CTL_VALUE(x) (((x) >> S_CTL_VALUE) & M_CTL_VALUE)
35727 
35728 #define S_ORG_VALUE    0
35729 #define M_ORG_VALUE    0xffffffU
35730 #define V_ORG_VALUE(x) ((x) << S_ORG_VALUE)
35731 #define G_ORG_VALUE(x) (((x) >> S_ORG_VALUE) & M_ORG_VALUE)
35732 
35733 #define A_MPS_RX_IPV4 0x1125c
35734 
35735 #define S_ETYPE_IPV4    0
35736 #define M_ETYPE_IPV4    0xffffU
35737 #define V_ETYPE_IPV4(x) ((x) << S_ETYPE_IPV4)
35738 #define G_ETYPE_IPV4(x) (((x) >> S_ETYPE_IPV4) & M_ETYPE_IPV4)
35739 
35740 #define A_MPS_RX_IPV6 0x11260
35741 
35742 #define S_ETYPE_IPV6    0
35743 #define M_ETYPE_IPV6    0xffffU
35744 #define V_ETYPE_IPV6(x) ((x) << S_ETYPE_IPV6)
35745 #define G_ETYPE_IPV6(x) (((x) >> S_ETYPE_IPV6) & M_ETYPE_IPV6)
35746 
35747 #define A_MPS_RX_TTL 0x11264
35748 
35749 #define S_TTL_IPV4    10
35750 #define M_TTL_IPV4    0xffU
35751 #define V_TTL_IPV4(x) ((x) << S_TTL_IPV4)
35752 #define G_TTL_IPV4(x) (((x) >> S_TTL_IPV4) & M_TTL_IPV4)
35753 
35754 #define S_TTL_IPV6    2
35755 #define M_TTL_IPV6    0xffU
35756 #define V_TTL_IPV6(x) ((x) << S_TTL_IPV6)
35757 #define G_TTL_IPV6(x) (((x) >> S_TTL_IPV6) & M_TTL_IPV6)
35758 
35759 #define S_TTL_CHK_EN_IPV4    1
35760 #define V_TTL_CHK_EN_IPV4(x) ((x) << S_TTL_CHK_EN_IPV4)
35761 #define F_TTL_CHK_EN_IPV4    V_TTL_CHK_EN_IPV4(1U)
35762 
35763 #define S_TTL_CHK_EN_IPV6    0
35764 #define V_TTL_CHK_EN_IPV6(x) ((x) << S_TTL_CHK_EN_IPV6)
35765 #define F_TTL_CHK_EN_IPV6    V_TTL_CHK_EN_IPV6(1U)
35766 
35767 #define A_MPS_RX_DEFAULT_VNI 0x11268
35768 
35769 #define S_VNI    0
35770 #define M_VNI    0xffffffU
35771 #define V_VNI(x) ((x) << S_VNI)
35772 #define G_VNI(x) (((x) >> S_VNI) & M_VNI)
35773 
35774 #define A_MPS_RX_PRS_CTL 0x1126c
35775 
35776 #define S_CTL_CHK_EN    28
35777 #define V_CTL_CHK_EN(x) ((x) << S_CTL_CHK_EN)
35778 #define F_CTL_CHK_EN    V_CTL_CHK_EN(1U)
35779 
35780 #define S_ORG_CHK_EN    27
35781 #define V_ORG_CHK_EN(x) ((x) << S_ORG_CHK_EN)
35782 #define F_ORG_CHK_EN    V_ORG_CHK_EN(1U)
35783 
35784 #define S_SAP_CHK_EN    26
35785 #define V_SAP_CHK_EN(x) ((x) << S_SAP_CHK_EN)
35786 #define F_SAP_CHK_EN    V_SAP_CHK_EN(1U)
35787 
35788 #define S_VXLAN_FLAG_CHK_EN    25
35789 #define V_VXLAN_FLAG_CHK_EN(x) ((x) << S_VXLAN_FLAG_CHK_EN)
35790 #define F_VXLAN_FLAG_CHK_EN    V_VXLAN_FLAG_CHK_EN(1U)
35791 
35792 #define S_VXLAN_FLAG_MASK    17
35793 #define M_VXLAN_FLAG_MASK    0xffU
35794 #define V_VXLAN_FLAG_MASK(x) ((x) << S_VXLAN_FLAG_MASK)
35795 #define G_VXLAN_FLAG_MASK(x) (((x) >> S_VXLAN_FLAG_MASK) & M_VXLAN_FLAG_MASK)
35796 
35797 #define S_VXLAN_FLAG    9
35798 #define M_VXLAN_FLAG    0xffU
35799 #define V_VXLAN_FLAG(x) ((x) << S_VXLAN_FLAG)
35800 #define G_VXLAN_FLAG(x) (((x) >> S_VXLAN_FLAG) & M_VXLAN_FLAG)
35801 
35802 #define S_GRE_VER_CHK_EN    8
35803 #define V_GRE_VER_CHK_EN(x) ((x) << S_GRE_VER_CHK_EN)
35804 #define F_GRE_VER_CHK_EN    V_GRE_VER_CHK_EN(1U)
35805 
35806 #define S_GRE_VER    5
35807 #define M_GRE_VER    0x7U
35808 #define V_GRE_VER(x) ((x) << S_GRE_VER)
35809 #define G_GRE_VER(x) (((x) >> S_GRE_VER) & M_GRE_VER)
35810 
35811 #define S_GENEVE_VER_CHK_EN    4
35812 #define V_GENEVE_VER_CHK_EN(x) ((x) << S_GENEVE_VER_CHK_EN)
35813 #define F_GENEVE_VER_CHK_EN    V_GENEVE_VER_CHK_EN(1U)
35814 
35815 #define S_GENEVE_VER    2
35816 #define M_GENEVE_VER    0x3U
35817 #define V_GENEVE_VER(x) ((x) << S_GENEVE_VER)
35818 #define G_GENEVE_VER(x) (((x) >> S_GENEVE_VER) & M_GENEVE_VER)
35819 
35820 #define S_DIP_EN    1
35821 #define V_DIP_EN(x) ((x) << S_DIP_EN)
35822 #define F_DIP_EN    V_DIP_EN(1U)
35823 
35824 #define A_MPS_RX_PRS_CTL_2 0x11270
35825 
35826 #define S_EN_UDP_CSUM_CHK    4
35827 #define V_EN_UDP_CSUM_CHK(x) ((x) << S_EN_UDP_CSUM_CHK)
35828 #define F_EN_UDP_CSUM_CHK    V_EN_UDP_CSUM_CHK(1U)
35829 
35830 #define S_EN_UDP_LEN_CHK    3
35831 #define V_EN_UDP_LEN_CHK(x) ((x) << S_EN_UDP_LEN_CHK)
35832 #define F_EN_UDP_LEN_CHK    V_EN_UDP_LEN_CHK(1U)
35833 
35834 #define S_EN_IP_CSUM_CHK    2
35835 #define V_EN_IP_CSUM_CHK(x) ((x) << S_EN_IP_CSUM_CHK)
35836 #define F_EN_IP_CSUM_CHK    V_EN_IP_CSUM_CHK(1U)
35837 
35838 #define S_EN_IP_PAYLOAD_LEN_CHK    1
35839 #define V_EN_IP_PAYLOAD_LEN_CHK(x) ((x) << S_EN_IP_PAYLOAD_LEN_CHK)
35840 #define F_EN_IP_PAYLOAD_LEN_CHK    V_EN_IP_PAYLOAD_LEN_CHK(1U)
35841 
35842 #define S_T6_IPV6_UDP_CSUM_COMPAT    0
35843 #define V_T6_IPV6_UDP_CSUM_COMPAT(x) ((x) << S_T6_IPV6_UDP_CSUM_COMPAT)
35844 #define F_T6_IPV6_UDP_CSUM_COMPAT    V_T6_IPV6_UDP_CSUM_COMPAT(1U)
35845 
35846 #define A_MPS_RX_MPS2NCSI_CNT 0x11274
35847 #define A_MPS_RX_MAX_TNL_HDR_LEN 0x11278
35848 
35849 #define S_T6_LEN    0
35850 #define M_T6_LEN    0x1ffU
35851 #define V_T6_LEN(x) ((x) << S_T6_LEN)
35852 #define G_T6_LEN(x) (((x) >> S_T6_LEN) & M_T6_LEN)
35853 
35854 #define A_MPS_RX_PAUSE_DA_H 0x1127c
35855 #define A_MPS_RX_PAUSE_DA_L 0x11280
35856 #define A_MPS_RX_CNT_NVGRE_PKT_MAC0 0x11284
35857 #define A_MPS_RX_CNT_VXLAN_PKT_MAC0 0x11288
35858 #define A_MPS_RX_CNT_GENEVE_PKT_MAC0 0x1128c
35859 #define A_MPS_RX_CNT_TNL_ERR_PKT_MAC0 0x11290
35860 #define A_MPS_RX_CNT_NVGRE_PKT_MAC1 0x11294
35861 #define A_MPS_RX_CNT_VXLAN_PKT_MAC1 0x11298
35862 #define A_MPS_RX_CNT_GENEVE_PKT_MAC1 0x1129c
35863 #define A_MPS_RX_CNT_TNL_ERR_PKT_MAC1 0x112a0
35864 #define A_MPS_RX_CNT_NVGRE_PKT_LPBK0 0x112a4
35865 #define A_MPS_RX_CNT_VXLAN_PKT_LPBK0 0x112a8
35866 #define A_MPS_RX_CNT_GENEVE_PKT_LPBK0 0x112ac
35867 #define A_MPS_RX_CNT_TNL_ERR_PKT_LPBK0 0x112b0
35868 #define A_MPS_RX_CNT_NVGRE_PKT_LPBK1 0x112b4
35869 #define A_MPS_RX_CNT_VXLAN_PKT_LPBK1 0x112b8
35870 #define A_MPS_RX_CNT_GENEVE_PKT_LPBK1 0x112bc
35871 #define A_MPS_RX_CNT_TNL_ERR_PKT_LPBK1 0x112c0
35872 #define A_MPS_RX_CNT_NVGRE_PKT_TO_TP0 0x112c4
35873 #define A_MPS_RX_CNT_VXLAN_PKT_TO_TP0 0x112c8
35874 #define A_MPS_RX_CNT_GENEVE_PKT_TO_TP0 0x112cc
35875 #define A_MPS_RX_CNT_TNL_ERR_PKT_TO_TP0 0x112d0
35876 #define A_MPS_RX_CNT_NVGRE_PKT_TO_TP1 0x112d4
35877 #define A_MPS_RX_CNT_VXLAN_PKT_TO_TP1 0x112d8
35878 #define A_MPS_RX_CNT_GENEVE_PKT_TO_TP1 0x112dc
35879 #define A_MPS_RX_CNT_TNL_ERR_PKT_TO_TP1 0x112e0
35880 #define A_MPS_VF_RPLCT_MAP4 0x11300
35881 #define A_MPS_VF_RPLCT_MAP5 0x11304
35882 #define A_MPS_VF_RPLCT_MAP6 0x11308
35883 #define A_MPS_VF_RPLCT_MAP7 0x1130c
35884 #define A_MPS_CLS_DIPIPV4_ID_TABLE 0x12000
35885 #define A_MPS_CLS_DIPIPV4_MASK_TABLE 0x12004
35886 #define A_MPS_CLS_DIPIPV6ID_0_TABLE 0x12020
35887 #define A_MPS_CLS_DIPIPV6ID_1_TABLE 0x12024
35888 #define A_MPS_CLS_DIPIPV6ID_2_TABLE 0x12028
35889 #define A_MPS_CLS_DIPIPV6ID_3_TABLE 0x1202c
35890 #define A_MPS_CLS_DIPIPV6MASK_0_TABLE 0x12030
35891 #define A_MPS_CLS_DIPIPV6MASK_1_TABLE 0x12034
35892 #define A_MPS_CLS_DIPIPV6MASK_2_TABLE 0x12038
35893 #define A_MPS_CLS_DIPIPV6MASK_3_TABLE 0x1203c
35894 #define A_MPS_RX_HASH_LKP_TABLE 0x12060
35895 
35896 /* registers for module CPL_SWITCH */
35897 #define CPL_SWITCH_BASE_ADDR 0x19040
35898 
35899 #define A_CPL_SWITCH_CNTRL 0x19040
35900 
35901 #define S_CPL_PKT_TID    8
35902 #define M_CPL_PKT_TID    0xffffffU
35903 #define V_CPL_PKT_TID(x) ((x) << S_CPL_PKT_TID)
35904 #define G_CPL_PKT_TID(x) (((x) >> S_CPL_PKT_TID) & M_CPL_PKT_TID)
35905 
35906 #define S_CIM_TRUNCATE_ENABLE    5
35907 #define V_CIM_TRUNCATE_ENABLE(x) ((x) << S_CIM_TRUNCATE_ENABLE)
35908 #define F_CIM_TRUNCATE_ENABLE    V_CIM_TRUNCATE_ENABLE(1U)
35909 
35910 #define S_CIM_TO_UP_FULL_SIZE    4
35911 #define V_CIM_TO_UP_FULL_SIZE(x) ((x) << S_CIM_TO_UP_FULL_SIZE)
35912 #define F_CIM_TO_UP_FULL_SIZE    V_CIM_TO_UP_FULL_SIZE(1U)
35913 
35914 #define S_CPU_NO_ENABLE    3
35915 #define V_CPU_NO_ENABLE(x) ((x) << S_CPU_NO_ENABLE)
35916 #define F_CPU_NO_ENABLE    V_CPU_NO_ENABLE(1U)
35917 
35918 #define S_SWITCH_TABLE_ENABLE    2
35919 #define V_SWITCH_TABLE_ENABLE(x) ((x) << S_SWITCH_TABLE_ENABLE)
35920 #define F_SWITCH_TABLE_ENABLE    V_SWITCH_TABLE_ENABLE(1U)
35921 
35922 #define S_SGE_ENABLE    1
35923 #define V_SGE_ENABLE(x) ((x) << S_SGE_ENABLE)
35924 #define F_SGE_ENABLE    V_SGE_ENABLE(1U)
35925 
35926 #define S_CIM_ENABLE    0
35927 #define V_CIM_ENABLE(x) ((x) << S_CIM_ENABLE)
35928 #define F_CIM_ENABLE    V_CIM_ENABLE(1U)
35929 
35930 #define S_CIM_SPLIT_ENABLE    6
35931 #define V_CIM_SPLIT_ENABLE(x) ((x) << S_CIM_SPLIT_ENABLE)
35932 #define F_CIM_SPLIT_ENABLE    V_CIM_SPLIT_ENABLE(1U)
35933 
35934 #define A_CPL_SWITCH_TBL_IDX 0x19044
35935 
35936 #define S_SWITCH_TBL_IDX    0
35937 #define M_SWITCH_TBL_IDX    0xfU
35938 #define V_SWITCH_TBL_IDX(x) ((x) << S_SWITCH_TBL_IDX)
35939 #define G_SWITCH_TBL_IDX(x) (((x) >> S_SWITCH_TBL_IDX) & M_SWITCH_TBL_IDX)
35940 
35941 #define A_CPL_SWITCH_TBL_DATA 0x19048
35942 #define A_CPL_SWITCH_ZERO_ERROR 0x1904c
35943 
35944 #define S_ZERO_CMD_CH1    8
35945 #define M_ZERO_CMD_CH1    0xffU
35946 #define V_ZERO_CMD_CH1(x) ((x) << S_ZERO_CMD_CH1)
35947 #define G_ZERO_CMD_CH1(x) (((x) >> S_ZERO_CMD_CH1) & M_ZERO_CMD_CH1)
35948 
35949 #define S_ZERO_CMD_CH0    0
35950 #define M_ZERO_CMD_CH0    0xffU
35951 #define V_ZERO_CMD_CH0(x) ((x) << S_ZERO_CMD_CH0)
35952 #define G_ZERO_CMD_CH0(x) (((x) >> S_ZERO_CMD_CH0) & M_ZERO_CMD_CH0)
35953 
35954 #define A_CPL_INTR_ENABLE 0x19050
35955 
35956 #define S_CIM_OP_MAP_PERR    5
35957 #define V_CIM_OP_MAP_PERR(x) ((x) << S_CIM_OP_MAP_PERR)
35958 #define F_CIM_OP_MAP_PERR    V_CIM_OP_MAP_PERR(1U)
35959 
35960 #define S_CIM_OVFL_ERROR    4
35961 #define V_CIM_OVFL_ERROR(x) ((x) << S_CIM_OVFL_ERROR)
35962 #define F_CIM_OVFL_ERROR    V_CIM_OVFL_ERROR(1U)
35963 
35964 #define S_TP_FRAMING_ERROR    3
35965 #define V_TP_FRAMING_ERROR(x) ((x) << S_TP_FRAMING_ERROR)
35966 #define F_TP_FRAMING_ERROR    V_TP_FRAMING_ERROR(1U)
35967 
35968 #define S_SGE_FRAMING_ERROR    2
35969 #define V_SGE_FRAMING_ERROR(x) ((x) << S_SGE_FRAMING_ERROR)
35970 #define F_SGE_FRAMING_ERROR    V_SGE_FRAMING_ERROR(1U)
35971 
35972 #define S_CIM_FRAMING_ERROR    1
35973 #define V_CIM_FRAMING_ERROR(x) ((x) << S_CIM_FRAMING_ERROR)
35974 #define F_CIM_FRAMING_ERROR    V_CIM_FRAMING_ERROR(1U)
35975 
35976 #define S_ZERO_SWITCH_ERROR    0
35977 #define V_ZERO_SWITCH_ERROR(x) ((x) << S_ZERO_SWITCH_ERROR)
35978 #define F_ZERO_SWITCH_ERROR    V_ZERO_SWITCH_ERROR(1U)
35979 
35980 #define S_PERR_CPL_128TO128_1    7
35981 #define V_PERR_CPL_128TO128_1(x) ((x) << S_PERR_CPL_128TO128_1)
35982 #define F_PERR_CPL_128TO128_1    V_PERR_CPL_128TO128_1(1U)
35983 
35984 #define S_PERR_CPL_128TO128_0    6
35985 #define V_PERR_CPL_128TO128_0(x) ((x) << S_PERR_CPL_128TO128_0)
35986 #define F_PERR_CPL_128TO128_0    V_PERR_CPL_128TO128_0(1U)
35987 
35988 #define A_CPL_INTR_CAUSE 0x19054
35989 #define A_CPL_MAP_TBL_IDX 0x19058
35990 
35991 #define S_MAP_TBL_IDX    0
35992 #define M_MAP_TBL_IDX    0xffU
35993 #define V_MAP_TBL_IDX(x) ((x) << S_MAP_TBL_IDX)
35994 #define G_MAP_TBL_IDX(x) (((x) >> S_MAP_TBL_IDX) & M_MAP_TBL_IDX)
35995 
35996 #define S_CIM_SPLIT_OPCODE_PROGRAM    8
35997 #define V_CIM_SPLIT_OPCODE_PROGRAM(x) ((x) << S_CIM_SPLIT_OPCODE_PROGRAM)
35998 #define F_CIM_SPLIT_OPCODE_PROGRAM    V_CIM_SPLIT_OPCODE_PROGRAM(1U)
35999 
36000 #define A_CPL_MAP_TBL_DATA 0x1905c
36001 
36002 #define S_MAP_TBL_DATA    0
36003 #define M_MAP_TBL_DATA    0xffU
36004 #define V_MAP_TBL_DATA(x) ((x) << S_MAP_TBL_DATA)
36005 #define G_MAP_TBL_DATA(x) (((x) >> S_MAP_TBL_DATA) & M_MAP_TBL_DATA)
36006 
36007 /* registers for module SMB */
36008 #define SMB_BASE_ADDR 0x19060
36009 
36010 #define A_SMB_GLOBAL_TIME_CFG 0x19060
36011 
36012 #define S_MACROCNTCFG    8
36013 #define M_MACROCNTCFG    0x1fU
36014 #define V_MACROCNTCFG(x) ((x) << S_MACROCNTCFG)
36015 #define G_MACROCNTCFG(x) (((x) >> S_MACROCNTCFG) & M_MACROCNTCFG)
36016 
36017 #define S_MICROCNTCFG    0
36018 #define M_MICROCNTCFG    0xffU
36019 #define V_MICROCNTCFG(x) ((x) << S_MICROCNTCFG)
36020 #define G_MICROCNTCFG(x) (((x) >> S_MICROCNTCFG) & M_MICROCNTCFG)
36021 
36022 #define A_SMB_MST_TIMEOUT_CFG 0x19064
36023 
36024 #define S_MSTTIMEOUTCFG    0
36025 #define M_MSTTIMEOUTCFG    0xffffffU
36026 #define V_MSTTIMEOUTCFG(x) ((x) << S_MSTTIMEOUTCFG)
36027 #define G_MSTTIMEOUTCFG(x) (((x) >> S_MSTTIMEOUTCFG) & M_MSTTIMEOUTCFG)
36028 
36029 #define A_SMB_MST_CTL_CFG 0x19068
36030 
36031 #define S_MSTFIFODBG    31
36032 #define V_MSTFIFODBG(x) ((x) << S_MSTFIFODBG)
36033 #define F_MSTFIFODBG    V_MSTFIFODBG(1U)
36034 
36035 #define S_MSTFIFODBGCLR    30
36036 #define V_MSTFIFODBGCLR(x) ((x) << S_MSTFIFODBGCLR)
36037 #define F_MSTFIFODBGCLR    V_MSTFIFODBGCLR(1U)
36038 
36039 #define S_MSTRXBYTECFG    12
36040 #define M_MSTRXBYTECFG    0x3fU
36041 #define V_MSTRXBYTECFG(x) ((x) << S_MSTRXBYTECFG)
36042 #define G_MSTRXBYTECFG(x) (((x) >> S_MSTRXBYTECFG) & M_MSTRXBYTECFG)
36043 
36044 #define S_MSTTXBYTECFG    6
36045 #define M_MSTTXBYTECFG    0x3fU
36046 #define V_MSTTXBYTECFG(x) ((x) << S_MSTTXBYTECFG)
36047 #define G_MSTTXBYTECFG(x) (((x) >> S_MSTTXBYTECFG) & M_MSTTXBYTECFG)
36048 
36049 #define S_MSTRESET    1
36050 #define V_MSTRESET(x) ((x) << S_MSTRESET)
36051 #define F_MSTRESET    V_MSTRESET(1U)
36052 
36053 #define S_MSTCTLEN    0
36054 #define V_MSTCTLEN(x) ((x) << S_MSTCTLEN)
36055 #define F_MSTCTLEN    V_MSTCTLEN(1U)
36056 
36057 #define A_SMB_MST_CTL_STS 0x1906c
36058 
36059 #define S_MSTRXBYTECNT    12
36060 #define M_MSTRXBYTECNT    0x3fU
36061 #define V_MSTRXBYTECNT(x) ((x) << S_MSTRXBYTECNT)
36062 #define G_MSTRXBYTECNT(x) (((x) >> S_MSTRXBYTECNT) & M_MSTRXBYTECNT)
36063 
36064 #define S_MSTTXBYTECNT    6
36065 #define M_MSTTXBYTECNT    0x3fU
36066 #define V_MSTTXBYTECNT(x) ((x) << S_MSTTXBYTECNT)
36067 #define G_MSTTXBYTECNT(x) (((x) >> S_MSTTXBYTECNT) & M_MSTTXBYTECNT)
36068 
36069 #define S_MSTBUSYSTS    0
36070 #define V_MSTBUSYSTS(x) ((x) << S_MSTBUSYSTS)
36071 #define F_MSTBUSYSTS    V_MSTBUSYSTS(1U)
36072 
36073 #define A_SMB_MST_TX_FIFO_RDWR 0x19070
36074 #define A_SMB_MST_RX_FIFO_RDWR 0x19074
36075 #define A_SMB_SLV_TIMEOUT_CFG 0x19078
36076 
36077 #define S_SLVTIMEOUTCFG    0
36078 #define M_SLVTIMEOUTCFG    0xffffffU
36079 #define V_SLVTIMEOUTCFG(x) ((x) << S_SLVTIMEOUTCFG)
36080 #define G_SLVTIMEOUTCFG(x) (((x) >> S_SLVTIMEOUTCFG) & M_SLVTIMEOUTCFG)
36081 
36082 #define A_SMB_SLV_CTL_CFG 0x1907c
36083 
36084 #define S_SLVFIFODBG    31
36085 #define V_SLVFIFODBG(x) ((x) << S_SLVFIFODBG)
36086 #define F_SLVFIFODBG    V_SLVFIFODBG(1U)
36087 
36088 #define S_SLVFIFODBGCLR    30
36089 #define V_SLVFIFODBGCLR(x) ((x) << S_SLVFIFODBGCLR)
36090 #define F_SLVFIFODBGCLR    V_SLVFIFODBGCLR(1U)
36091 
36092 #define S_SLVCRCOUTBITINV    21
36093 #define V_SLVCRCOUTBITINV(x) ((x) << S_SLVCRCOUTBITINV)
36094 #define F_SLVCRCOUTBITINV    V_SLVCRCOUTBITINV(1U)
36095 
36096 #define S_SLVCRCOUTBITREV    20
36097 #define V_SLVCRCOUTBITREV(x) ((x) << S_SLVCRCOUTBITREV)
36098 #define F_SLVCRCOUTBITREV    V_SLVCRCOUTBITREV(1U)
36099 
36100 #define S_SLVCRCINBITREV    19
36101 #define V_SLVCRCINBITREV(x) ((x) << S_SLVCRCINBITREV)
36102 #define F_SLVCRCINBITREV    V_SLVCRCINBITREV(1U)
36103 
36104 #define S_SLVCRCPRESET    11
36105 #define M_SLVCRCPRESET    0xffU
36106 #define V_SLVCRCPRESET(x) ((x) << S_SLVCRCPRESET)
36107 #define G_SLVCRCPRESET(x) (((x) >> S_SLVCRCPRESET) & M_SLVCRCPRESET)
36108 
36109 #define S_SLVADDRCFG    4
36110 #define M_SLVADDRCFG    0x7fU
36111 #define V_SLVADDRCFG(x) ((x) << S_SLVADDRCFG)
36112 #define G_SLVADDRCFG(x) (((x) >> S_SLVADDRCFG) & M_SLVADDRCFG)
36113 
36114 #define S_SLVALRTSET    2
36115 #define V_SLVALRTSET(x) ((x) << S_SLVALRTSET)
36116 #define F_SLVALRTSET    V_SLVALRTSET(1U)
36117 
36118 #define S_SLVRESET    1
36119 #define V_SLVRESET(x) ((x) << S_SLVRESET)
36120 #define F_SLVRESET    V_SLVRESET(1U)
36121 
36122 #define S_SLVCTLEN    0
36123 #define V_SLVCTLEN(x) ((x) << S_SLVCTLEN)
36124 #define F_SLVCTLEN    V_SLVCTLEN(1U)
36125 
36126 #define A_SMB_SLV_CTL_STS 0x19080
36127 
36128 #define S_SLVFIFOTXCNT    12
36129 #define M_SLVFIFOTXCNT    0x3fU
36130 #define V_SLVFIFOTXCNT(x) ((x) << S_SLVFIFOTXCNT)
36131 #define G_SLVFIFOTXCNT(x) (((x) >> S_SLVFIFOTXCNT) & M_SLVFIFOTXCNT)
36132 
36133 #define S_SLVFIFOCNT    6
36134 #define M_SLVFIFOCNT    0x3fU
36135 #define V_SLVFIFOCNT(x) ((x) << S_SLVFIFOCNT)
36136 #define G_SLVFIFOCNT(x) (((x) >> S_SLVFIFOCNT) & M_SLVFIFOCNT)
36137 
36138 #define S_SLVALRTSTS    2
36139 #define V_SLVALRTSTS(x) ((x) << S_SLVALRTSTS)
36140 #define F_SLVALRTSTS    V_SLVALRTSTS(1U)
36141 
36142 #define S_SLVBUSYSTS    0
36143 #define V_SLVBUSYSTS(x) ((x) << S_SLVBUSYSTS)
36144 #define F_SLVBUSYSTS    V_SLVBUSYSTS(1U)
36145 
36146 #define A_SMB_SLV_FIFO_RDWR 0x19084
36147 #define A_SMB_INT_ENABLE 0x1908c
36148 
36149 #define S_MSTTXFIFOPAREN    21
36150 #define V_MSTTXFIFOPAREN(x) ((x) << S_MSTTXFIFOPAREN)
36151 #define F_MSTTXFIFOPAREN    V_MSTTXFIFOPAREN(1U)
36152 
36153 #define S_MSTRXFIFOPAREN    20
36154 #define V_MSTRXFIFOPAREN(x) ((x) << S_MSTRXFIFOPAREN)
36155 #define F_MSTRXFIFOPAREN    V_MSTRXFIFOPAREN(1U)
36156 
36157 #define S_SLVFIFOPAREN    19
36158 #define V_SLVFIFOPAREN(x) ((x) << S_SLVFIFOPAREN)
36159 #define F_SLVFIFOPAREN    V_SLVFIFOPAREN(1U)
36160 
36161 #define S_SLVUNEXPBUSSTOPEN    18
36162 #define V_SLVUNEXPBUSSTOPEN(x) ((x) << S_SLVUNEXPBUSSTOPEN)
36163 #define F_SLVUNEXPBUSSTOPEN    V_SLVUNEXPBUSSTOPEN(1U)
36164 
36165 #define S_SLVUNEXPBUSSTARTEN    17
36166 #define V_SLVUNEXPBUSSTARTEN(x) ((x) << S_SLVUNEXPBUSSTARTEN)
36167 #define F_SLVUNEXPBUSSTARTEN    V_SLVUNEXPBUSSTARTEN(1U)
36168 
36169 #define S_SLVCOMMANDCODEINVEN    16
36170 #define V_SLVCOMMANDCODEINVEN(x) ((x) << S_SLVCOMMANDCODEINVEN)
36171 #define F_SLVCOMMANDCODEINVEN    V_SLVCOMMANDCODEINVEN(1U)
36172 
36173 #define S_SLVBYTECNTERREN    15
36174 #define V_SLVBYTECNTERREN(x) ((x) << S_SLVBYTECNTERREN)
36175 #define F_SLVBYTECNTERREN    V_SLVBYTECNTERREN(1U)
36176 
36177 #define S_SLVUNEXPACKMSTEN    14
36178 #define V_SLVUNEXPACKMSTEN(x) ((x) << S_SLVUNEXPACKMSTEN)
36179 #define F_SLVUNEXPACKMSTEN    V_SLVUNEXPACKMSTEN(1U)
36180 
36181 #define S_SLVUNEXPNACKMSTEN    13
36182 #define V_SLVUNEXPNACKMSTEN(x) ((x) << S_SLVUNEXPNACKMSTEN)
36183 #define F_SLVUNEXPNACKMSTEN    V_SLVUNEXPNACKMSTEN(1U)
36184 
36185 #define S_SLVNOBUSSTOPEN    12
36186 #define V_SLVNOBUSSTOPEN(x) ((x) << S_SLVNOBUSSTOPEN)
36187 #define F_SLVNOBUSSTOPEN    V_SLVNOBUSSTOPEN(1U)
36188 
36189 #define S_SLVNOREPSTARTEN    11
36190 #define V_SLVNOREPSTARTEN(x) ((x) << S_SLVNOREPSTARTEN)
36191 #define F_SLVNOREPSTARTEN    V_SLVNOREPSTARTEN(1U)
36192 
36193 #define S_SLVRXADDRINTEN    10
36194 #define V_SLVRXADDRINTEN(x) ((x) << S_SLVRXADDRINTEN)
36195 #define F_SLVRXADDRINTEN    V_SLVRXADDRINTEN(1U)
36196 
36197 #define S_SLVRXPECERRINTEN    9
36198 #define V_SLVRXPECERRINTEN(x) ((x) << S_SLVRXPECERRINTEN)
36199 #define F_SLVRXPECERRINTEN    V_SLVRXPECERRINTEN(1U)
36200 
36201 #define S_SLVPREPTOARPINTEN    8
36202 #define V_SLVPREPTOARPINTEN(x) ((x) << S_SLVPREPTOARPINTEN)
36203 #define F_SLVPREPTOARPINTEN    V_SLVPREPTOARPINTEN(1U)
36204 
36205 #define S_SLVTIMEOUTINTEN    7
36206 #define V_SLVTIMEOUTINTEN(x) ((x) << S_SLVTIMEOUTINTEN)
36207 #define F_SLVTIMEOUTINTEN    V_SLVTIMEOUTINTEN(1U)
36208 
36209 #define S_SLVERRINTEN    6
36210 #define V_SLVERRINTEN(x) ((x) << S_SLVERRINTEN)
36211 #define F_SLVERRINTEN    V_SLVERRINTEN(1U)
36212 
36213 #define S_SLVDONEINTEN    5
36214 #define V_SLVDONEINTEN(x) ((x) << S_SLVDONEINTEN)
36215 #define F_SLVDONEINTEN    V_SLVDONEINTEN(1U)
36216 
36217 #define S_SLVRXRDYINTEN    4
36218 #define V_SLVRXRDYINTEN(x) ((x) << S_SLVRXRDYINTEN)
36219 #define F_SLVRXRDYINTEN    V_SLVRXRDYINTEN(1U)
36220 
36221 #define S_MSTTIMEOUTINTEN    3
36222 #define V_MSTTIMEOUTINTEN(x) ((x) << S_MSTTIMEOUTINTEN)
36223 #define F_MSTTIMEOUTINTEN    V_MSTTIMEOUTINTEN(1U)
36224 
36225 #define S_MSTNACKINTEN    2
36226 #define V_MSTNACKINTEN(x) ((x) << S_MSTNACKINTEN)
36227 #define F_MSTNACKINTEN    V_MSTNACKINTEN(1U)
36228 
36229 #define S_MSTLOSTARBINTEN    1
36230 #define V_MSTLOSTARBINTEN(x) ((x) << S_MSTLOSTARBINTEN)
36231 #define F_MSTLOSTARBINTEN    V_MSTLOSTARBINTEN(1U)
36232 
36233 #define S_MSTDONEINTEN    0
36234 #define V_MSTDONEINTEN(x) ((x) << S_MSTDONEINTEN)
36235 #define F_MSTDONEINTEN    V_MSTDONEINTEN(1U)
36236 
36237 #define A_SMB_INT_CAUSE 0x19090
36238 
36239 #define S_MSTTXFIFOPARINT    21
36240 #define V_MSTTXFIFOPARINT(x) ((x) << S_MSTTXFIFOPARINT)
36241 #define F_MSTTXFIFOPARINT    V_MSTTXFIFOPARINT(1U)
36242 
36243 #define S_MSTRXFIFOPARINT    20
36244 #define V_MSTRXFIFOPARINT(x) ((x) << S_MSTRXFIFOPARINT)
36245 #define F_MSTRXFIFOPARINT    V_MSTRXFIFOPARINT(1U)
36246 
36247 #define S_SLVFIFOPARINT    19
36248 #define V_SLVFIFOPARINT(x) ((x) << S_SLVFIFOPARINT)
36249 #define F_SLVFIFOPARINT    V_SLVFIFOPARINT(1U)
36250 
36251 #define S_SLVUNEXPBUSSTOPINT    18
36252 #define V_SLVUNEXPBUSSTOPINT(x) ((x) << S_SLVUNEXPBUSSTOPINT)
36253 #define F_SLVUNEXPBUSSTOPINT    V_SLVUNEXPBUSSTOPINT(1U)
36254 
36255 #define S_SLVUNEXPBUSSTARTINT    17
36256 #define V_SLVUNEXPBUSSTARTINT(x) ((x) << S_SLVUNEXPBUSSTARTINT)
36257 #define F_SLVUNEXPBUSSTARTINT    V_SLVUNEXPBUSSTARTINT(1U)
36258 
36259 #define S_SLVCOMMANDCODEINVINT    16
36260 #define V_SLVCOMMANDCODEINVINT(x) ((x) << S_SLVCOMMANDCODEINVINT)
36261 #define F_SLVCOMMANDCODEINVINT    V_SLVCOMMANDCODEINVINT(1U)
36262 
36263 #define S_SLVBYTECNTERRINT    15
36264 #define V_SLVBYTECNTERRINT(x) ((x) << S_SLVBYTECNTERRINT)
36265 #define F_SLVBYTECNTERRINT    V_SLVBYTECNTERRINT(1U)
36266 
36267 #define S_SLVUNEXPACKMSTINT    14
36268 #define V_SLVUNEXPACKMSTINT(x) ((x) << S_SLVUNEXPACKMSTINT)
36269 #define F_SLVUNEXPACKMSTINT    V_SLVUNEXPACKMSTINT(1U)
36270 
36271 #define S_SLVUNEXPNACKMSTINT    13
36272 #define V_SLVUNEXPNACKMSTINT(x) ((x) << S_SLVUNEXPNACKMSTINT)
36273 #define F_SLVUNEXPNACKMSTINT    V_SLVUNEXPNACKMSTINT(1U)
36274 
36275 #define S_SLVNOBUSSTOPINT    12
36276 #define V_SLVNOBUSSTOPINT(x) ((x) << S_SLVNOBUSSTOPINT)
36277 #define F_SLVNOBUSSTOPINT    V_SLVNOBUSSTOPINT(1U)
36278 
36279 #define S_SLVNOREPSTARTINT    11
36280 #define V_SLVNOREPSTARTINT(x) ((x) << S_SLVNOREPSTARTINT)
36281 #define F_SLVNOREPSTARTINT    V_SLVNOREPSTARTINT(1U)
36282 
36283 #define S_SLVRXADDRINT    10
36284 #define V_SLVRXADDRINT(x) ((x) << S_SLVRXADDRINT)
36285 #define F_SLVRXADDRINT    V_SLVRXADDRINT(1U)
36286 
36287 #define S_SLVRXPECERRINT    9
36288 #define V_SLVRXPECERRINT(x) ((x) << S_SLVRXPECERRINT)
36289 #define F_SLVRXPECERRINT    V_SLVRXPECERRINT(1U)
36290 
36291 #define S_SLVPREPTOARPINT    8
36292 #define V_SLVPREPTOARPINT(x) ((x) << S_SLVPREPTOARPINT)
36293 #define F_SLVPREPTOARPINT    V_SLVPREPTOARPINT(1U)
36294 
36295 #define S_SLVTIMEOUTINT    7
36296 #define V_SLVTIMEOUTINT(x) ((x) << S_SLVTIMEOUTINT)
36297 #define F_SLVTIMEOUTINT    V_SLVTIMEOUTINT(1U)
36298 
36299 #define S_SLVERRINT    6
36300 #define V_SLVERRINT(x) ((x) << S_SLVERRINT)
36301 #define F_SLVERRINT    V_SLVERRINT(1U)
36302 
36303 #define S_SLVDONEINT    5
36304 #define V_SLVDONEINT(x) ((x) << S_SLVDONEINT)
36305 #define F_SLVDONEINT    V_SLVDONEINT(1U)
36306 
36307 #define S_SLVRXRDYINT    4
36308 #define V_SLVRXRDYINT(x) ((x) << S_SLVRXRDYINT)
36309 #define F_SLVRXRDYINT    V_SLVRXRDYINT(1U)
36310 
36311 #define S_MSTTIMEOUTINT    3
36312 #define V_MSTTIMEOUTINT(x) ((x) << S_MSTTIMEOUTINT)
36313 #define F_MSTTIMEOUTINT    V_MSTTIMEOUTINT(1U)
36314 
36315 #define S_MSTNACKINT    2
36316 #define V_MSTNACKINT(x) ((x) << S_MSTNACKINT)
36317 #define F_MSTNACKINT    V_MSTNACKINT(1U)
36318 
36319 #define S_MSTLOSTARBINT    1
36320 #define V_MSTLOSTARBINT(x) ((x) << S_MSTLOSTARBINT)
36321 #define F_MSTLOSTARBINT    V_MSTLOSTARBINT(1U)
36322 
36323 #define S_MSTDONEINT    0
36324 #define V_MSTDONEINT(x) ((x) << S_MSTDONEINT)
36325 #define F_MSTDONEINT    V_MSTDONEINT(1U)
36326 
36327 #define A_SMB_DEBUG_DATA 0x19094
36328 
36329 #define S_DEBUGDATAH    16
36330 #define M_DEBUGDATAH    0xffffU
36331 #define V_DEBUGDATAH(x) ((x) << S_DEBUGDATAH)
36332 #define G_DEBUGDATAH(x) (((x) >> S_DEBUGDATAH) & M_DEBUGDATAH)
36333 
36334 #define S_DEBUGDATAL    0
36335 #define M_DEBUGDATAL    0xffffU
36336 #define V_DEBUGDATAL(x) ((x) << S_DEBUGDATAL)
36337 #define G_DEBUGDATAL(x) (((x) >> S_DEBUGDATAL) & M_DEBUGDATAL)
36338 
36339 #define A_SMB_PERR_EN 0x19098
36340 
36341 #define S_MSTTXFIFOPERREN    2
36342 #define V_MSTTXFIFOPERREN(x) ((x) << S_MSTTXFIFOPERREN)
36343 #define F_MSTTXFIFOPERREN    V_MSTTXFIFOPERREN(1U)
36344 
36345 #define S_MSTRXFIFOPERREN    1
36346 #define V_MSTRXFIFOPERREN(x) ((x) << S_MSTRXFIFOPERREN)
36347 #define F_MSTRXFIFOPERREN    V_MSTRXFIFOPERREN(1U)
36348 
36349 #define S_SLVFIFOPERREN    0
36350 #define V_SLVFIFOPERREN(x) ((x) << S_SLVFIFOPERREN)
36351 #define F_SLVFIFOPERREN    V_SLVFIFOPERREN(1U)
36352 
36353 #define S_MSTTXFIFO    21
36354 #define V_MSTTXFIFO(x) ((x) << S_MSTTXFIFO)
36355 #define F_MSTTXFIFO    V_MSTTXFIFO(1U)
36356 
36357 #define S_MSTRXFIFO    19
36358 #define V_MSTRXFIFO(x) ((x) << S_MSTRXFIFO)
36359 #define F_MSTRXFIFO    V_MSTRXFIFO(1U)
36360 
36361 #define S_SLVFIFO    18
36362 #define V_SLVFIFO(x) ((x) << S_SLVFIFO)
36363 #define F_SLVFIFO    V_SLVFIFO(1U)
36364 
36365 #define A_SMB_PERR_INJ 0x1909c
36366 
36367 #define S_MSTTXINJDATAERR    3
36368 #define V_MSTTXINJDATAERR(x) ((x) << S_MSTTXINJDATAERR)
36369 #define F_MSTTXINJDATAERR    V_MSTTXINJDATAERR(1U)
36370 
36371 #define S_MSTRXINJDATAERR    2
36372 #define V_MSTRXINJDATAERR(x) ((x) << S_MSTRXINJDATAERR)
36373 #define F_MSTRXINJDATAERR    V_MSTRXINJDATAERR(1U)
36374 
36375 #define S_SLVINJDATAERR    1
36376 #define V_SLVINJDATAERR(x) ((x) << S_SLVINJDATAERR)
36377 #define F_SLVINJDATAERR    V_SLVINJDATAERR(1U)
36378 
36379 #define S_FIFOINJDATAERREN    0
36380 #define V_FIFOINJDATAERREN(x) ((x) << S_FIFOINJDATAERREN)
36381 #define F_FIFOINJDATAERREN    V_FIFOINJDATAERREN(1U)
36382 
36383 #define A_SMB_SLV_ARP_CTL 0x190a0
36384 
36385 #define S_ARPCOMMANDCODE    2
36386 #define M_ARPCOMMANDCODE    0xffU
36387 #define V_ARPCOMMANDCODE(x) ((x) << S_ARPCOMMANDCODE)
36388 #define G_ARPCOMMANDCODE(x) (((x) >> S_ARPCOMMANDCODE) & M_ARPCOMMANDCODE)
36389 
36390 #define S_ARPADDRRES    1
36391 #define V_ARPADDRRES(x) ((x) << S_ARPADDRRES)
36392 #define F_ARPADDRRES    V_ARPADDRRES(1U)
36393 
36394 #define S_ARPADDRVAL    0
36395 #define V_ARPADDRVAL(x) ((x) << S_ARPADDRVAL)
36396 #define F_ARPADDRVAL    V_ARPADDRVAL(1U)
36397 
36398 #define A_SMB_ARP_UDID0 0x190a4
36399 #define A_SMB_ARP_UDID1 0x190a8
36400 
36401 #define S_SUBSYSTEMVENDORID    16
36402 #define M_SUBSYSTEMVENDORID    0xffffU
36403 #define V_SUBSYSTEMVENDORID(x) ((x) << S_SUBSYSTEMVENDORID)
36404 #define G_SUBSYSTEMVENDORID(x) (((x) >> S_SUBSYSTEMVENDORID) & M_SUBSYSTEMVENDORID)
36405 
36406 #define S_SUBSYSTEMDEVICEID    0
36407 #define M_SUBSYSTEMDEVICEID    0xffffU
36408 #define V_SUBSYSTEMDEVICEID(x) ((x) << S_SUBSYSTEMDEVICEID)
36409 #define G_SUBSYSTEMDEVICEID(x) (((x) >> S_SUBSYSTEMDEVICEID) & M_SUBSYSTEMDEVICEID)
36410 
36411 #define A_SMB_ARP_UDID2 0x190ac
36412 
36413 #define S_DEVICEID    16
36414 #define M_DEVICEID    0xffffU
36415 #define V_DEVICEID(x) ((x) << S_DEVICEID)
36416 #define G_DEVICEID(x) (((x) >> S_DEVICEID) & M_DEVICEID)
36417 
36418 #define S_INTERFACE    0
36419 #define M_INTERFACE    0xffffU
36420 #define V_INTERFACE(x) ((x) << S_INTERFACE)
36421 #define G_INTERFACE(x) (((x) >> S_INTERFACE) & M_INTERFACE)
36422 
36423 #define A_SMB_ARP_UDID3 0x190b0
36424 
36425 #define S_DEVICECAP    24
36426 #define M_DEVICECAP    0xffU
36427 #define V_DEVICECAP(x) ((x) << S_DEVICECAP)
36428 #define G_DEVICECAP(x) (((x) >> S_DEVICECAP) & M_DEVICECAP)
36429 
36430 #define S_VERSIONID    16
36431 #define M_VERSIONID    0xffU
36432 #define V_VERSIONID(x) ((x) << S_VERSIONID)
36433 #define G_VERSIONID(x) (((x) >> S_VERSIONID) & M_VERSIONID)
36434 
36435 #define S_VENDORID    0
36436 #define M_VENDORID    0xffffU
36437 #define V_VENDORID(x) ((x) << S_VENDORID)
36438 #define G_VENDORID(x) (((x) >> S_VENDORID) & M_VENDORID)
36439 
36440 #define A_SMB_SLV_AUX_ADDR0 0x190b4
36441 
36442 #define S_AUXADDR0VAL    6
36443 #define V_AUXADDR0VAL(x) ((x) << S_AUXADDR0VAL)
36444 #define F_AUXADDR0VAL    V_AUXADDR0VAL(1U)
36445 
36446 #define S_AUXADDR0    0
36447 #define M_AUXADDR0    0x3fU
36448 #define V_AUXADDR0(x) ((x) << S_AUXADDR0)
36449 #define G_AUXADDR0(x) (((x) >> S_AUXADDR0) & M_AUXADDR0)
36450 
36451 #define A_SMB_SLV_AUX_ADDR1 0x190b8
36452 
36453 #define S_AUXADDR1VAL    6
36454 #define V_AUXADDR1VAL(x) ((x) << S_AUXADDR1VAL)
36455 #define F_AUXADDR1VAL    V_AUXADDR1VAL(1U)
36456 
36457 #define S_AUXADDR1    0
36458 #define M_AUXADDR1    0x3fU
36459 #define V_AUXADDR1(x) ((x) << S_AUXADDR1)
36460 #define G_AUXADDR1(x) (((x) >> S_AUXADDR1) & M_AUXADDR1)
36461 
36462 #define A_SMB_SLV_AUX_ADDR2 0x190bc
36463 
36464 #define S_AUXADDR2VAL    6
36465 #define V_AUXADDR2VAL(x) ((x) << S_AUXADDR2VAL)
36466 #define F_AUXADDR2VAL    V_AUXADDR2VAL(1U)
36467 
36468 #define S_AUXADDR2    0
36469 #define M_AUXADDR2    0x3fU
36470 #define V_AUXADDR2(x) ((x) << S_AUXADDR2)
36471 #define G_AUXADDR2(x) (((x) >> S_AUXADDR2) & M_AUXADDR2)
36472 
36473 #define A_SMB_SLV_AUX_ADDR3 0x190c0
36474 
36475 #define S_AUXADDR3VAL    6
36476 #define V_AUXADDR3VAL(x) ((x) << S_AUXADDR3VAL)
36477 #define F_AUXADDR3VAL    V_AUXADDR3VAL(1U)
36478 
36479 #define S_AUXADDR3    0
36480 #define M_AUXADDR3    0x3fU
36481 #define V_AUXADDR3(x) ((x) << S_AUXADDR3)
36482 #define G_AUXADDR3(x) (((x) >> S_AUXADDR3) & M_AUXADDR3)
36483 
36484 #define A_SMB_COMMAND_CODE0 0x190c4
36485 
36486 #define S_SMBUSCOMMANDCODE0    0
36487 #define M_SMBUSCOMMANDCODE0    0xffU
36488 #define V_SMBUSCOMMANDCODE0(x) ((x) << S_SMBUSCOMMANDCODE0)
36489 #define G_SMBUSCOMMANDCODE0(x) (((x) >> S_SMBUSCOMMANDCODE0) & M_SMBUSCOMMANDCODE0)
36490 
36491 #define A_SMB_COMMAND_CODE1 0x190c8
36492 
36493 #define S_SMBUSCOMMANDCODE1    0
36494 #define M_SMBUSCOMMANDCODE1    0xffU
36495 #define V_SMBUSCOMMANDCODE1(x) ((x) << S_SMBUSCOMMANDCODE1)
36496 #define G_SMBUSCOMMANDCODE1(x) (((x) >> S_SMBUSCOMMANDCODE1) & M_SMBUSCOMMANDCODE1)
36497 
36498 #define A_SMB_COMMAND_CODE2 0x190cc
36499 
36500 #define S_SMBUSCOMMANDCODE2    0
36501 #define M_SMBUSCOMMANDCODE2    0xffU
36502 #define V_SMBUSCOMMANDCODE2(x) ((x) << S_SMBUSCOMMANDCODE2)
36503 #define G_SMBUSCOMMANDCODE2(x) (((x) >> S_SMBUSCOMMANDCODE2) & M_SMBUSCOMMANDCODE2)
36504 
36505 #define A_SMB_COMMAND_CODE3 0x190d0
36506 
36507 #define S_SMBUSCOMMANDCODE3    0
36508 #define M_SMBUSCOMMANDCODE3    0xffU
36509 #define V_SMBUSCOMMANDCODE3(x) ((x) << S_SMBUSCOMMANDCODE3)
36510 #define G_SMBUSCOMMANDCODE3(x) (((x) >> S_SMBUSCOMMANDCODE3) & M_SMBUSCOMMANDCODE3)
36511 
36512 #define A_SMB_COMMAND_CODE4 0x190d4
36513 
36514 #define S_SMBUSCOMMANDCODE4    0
36515 #define M_SMBUSCOMMANDCODE4    0xffU
36516 #define V_SMBUSCOMMANDCODE4(x) ((x) << S_SMBUSCOMMANDCODE4)
36517 #define G_SMBUSCOMMANDCODE4(x) (((x) >> S_SMBUSCOMMANDCODE4) & M_SMBUSCOMMANDCODE4)
36518 
36519 #define A_SMB_COMMAND_CODE5 0x190d8
36520 
36521 #define S_SMBUSCOMMANDCODE5    0
36522 #define M_SMBUSCOMMANDCODE5    0xffU
36523 #define V_SMBUSCOMMANDCODE5(x) ((x) << S_SMBUSCOMMANDCODE5)
36524 #define G_SMBUSCOMMANDCODE5(x) (((x) >> S_SMBUSCOMMANDCODE5) & M_SMBUSCOMMANDCODE5)
36525 
36526 #define A_SMB_COMMAND_CODE6 0x190dc
36527 
36528 #define S_SMBUSCOMMANDCODE6    0
36529 #define M_SMBUSCOMMANDCODE6    0xffU
36530 #define V_SMBUSCOMMANDCODE6(x) ((x) << S_SMBUSCOMMANDCODE6)
36531 #define G_SMBUSCOMMANDCODE6(x) (((x) >> S_SMBUSCOMMANDCODE6) & M_SMBUSCOMMANDCODE6)
36532 
36533 #define A_SMB_COMMAND_CODE7 0x190e0
36534 
36535 #define S_SMBUSCOMMANDCODE7    0
36536 #define M_SMBUSCOMMANDCODE7    0xffU
36537 #define V_SMBUSCOMMANDCODE7(x) ((x) << S_SMBUSCOMMANDCODE7)
36538 #define G_SMBUSCOMMANDCODE7(x) (((x) >> S_SMBUSCOMMANDCODE7) & M_SMBUSCOMMANDCODE7)
36539 
36540 #define A_SMB_MICRO_CNT_CLK_CFG 0x190e4
36541 
36542 #define S_MACROCNTCLKCFG    8
36543 #define M_MACROCNTCLKCFG    0x1fU
36544 #define V_MACROCNTCLKCFG(x) ((x) << S_MACROCNTCLKCFG)
36545 #define G_MACROCNTCLKCFG(x) (((x) >> S_MACROCNTCLKCFG) & M_MACROCNTCLKCFG)
36546 
36547 #define S_MICROCNTCLKCFG    0
36548 #define M_MICROCNTCLKCFG    0xffU
36549 #define V_MICROCNTCLKCFG(x) ((x) << S_MICROCNTCLKCFG)
36550 #define G_MICROCNTCLKCFG(x) (((x) >> S_MICROCNTCLKCFG) & M_MICROCNTCLKCFG)
36551 
36552 #define A_SMB_CTL_STATUS 0x190e8
36553 
36554 #define S_MSTBUSBUSY    2
36555 #define V_MSTBUSBUSY(x) ((x) << S_MSTBUSBUSY)
36556 #define F_MSTBUSBUSY    V_MSTBUSBUSY(1U)
36557 
36558 #define S_SLVBUSBUSY    1
36559 #define V_SLVBUSBUSY(x) ((x) << S_SLVBUSBUSY)
36560 #define F_SLVBUSBUSY    V_SLVBUSBUSY(1U)
36561 
36562 #define S_BUSBUSY    0
36563 #define V_BUSBUSY(x) ((x) << S_BUSBUSY)
36564 #define F_BUSBUSY    V_BUSBUSY(1U)
36565 
36566 /* registers for module I2CM */
36567 #define I2CM_BASE_ADDR 0x190f0
36568 
36569 #define A_I2CM_CFG 0x190f0
36570 
36571 #define S_I2C_CLKDIV    0
36572 #define M_I2C_CLKDIV    0xfffU
36573 #define V_I2C_CLKDIV(x) ((x) << S_I2C_CLKDIV)
36574 #define G_I2C_CLKDIV(x) (((x) >> S_I2C_CLKDIV) & M_I2C_CLKDIV)
36575 
36576 #define S_I2C_CLKDIV16B    0
36577 #define M_I2C_CLKDIV16B    0xffffU
36578 #define V_I2C_CLKDIV16B(x) ((x) << S_I2C_CLKDIV16B)
36579 #define G_I2C_CLKDIV16B(x) (((x) >> S_I2C_CLKDIV16B) & M_I2C_CLKDIV16B)
36580 
36581 #define A_I2CM_DATA 0x190f4
36582 
36583 #define S_I2C_DATA    0
36584 #define M_I2C_DATA    0xffU
36585 #define V_I2C_DATA(x) ((x) << S_I2C_DATA)
36586 #define G_I2C_DATA(x) (((x) >> S_I2C_DATA) & M_I2C_DATA)
36587 
36588 #define A_I2CM_OP 0x190f8
36589 
36590 #define S_I2C_ACK    30
36591 #define V_I2C_ACK(x) ((x) << S_I2C_ACK)
36592 #define F_I2C_ACK    V_I2C_ACK(1U)
36593 
36594 #define S_I2C_CONT    1
36595 #define V_I2C_CONT(x) ((x) << S_I2C_CONT)
36596 #define F_I2C_CONT    V_I2C_CONT(1U)
36597 
36598 #define S_OP    0
36599 #define V_OP(x) ((x) << S_OP)
36600 #define F_OP    V_OP(1U)
36601 
36602 /* registers for module MI */
36603 #define MI_BASE_ADDR 0x19100
36604 
36605 #define A_MI_CFG 0x19100
36606 
36607 #define S_T4_ST    14
36608 #define V_T4_ST(x) ((x) << S_T4_ST)
36609 #define F_T4_ST    V_T4_ST(1U)
36610 
36611 #define S_CLKDIV    5
36612 #define M_CLKDIV    0xffU
36613 #define V_CLKDIV(x) ((x) << S_CLKDIV)
36614 #define G_CLKDIV(x) (((x) >> S_CLKDIV) & M_CLKDIV)
36615 
36616 #define S_ST    3
36617 #define M_ST    0x3U
36618 #define V_ST(x) ((x) << S_ST)
36619 #define G_ST(x) (((x) >> S_ST) & M_ST)
36620 
36621 #define S_PREEN    2
36622 #define V_PREEN(x) ((x) << S_PREEN)
36623 #define F_PREEN    V_PREEN(1U)
36624 
36625 #define S_MDIINV    1
36626 #define V_MDIINV(x) ((x) << S_MDIINV)
36627 #define F_MDIINV    V_MDIINV(1U)
36628 
36629 #define S_MDIO_1P2V_SEL    0
36630 #define V_MDIO_1P2V_SEL(x) ((x) << S_MDIO_1P2V_SEL)
36631 #define F_MDIO_1P2V_SEL    V_MDIO_1P2V_SEL(1U)
36632 
36633 #define A_MI_ADDR 0x19104
36634 
36635 #define S_PHYADDR    5
36636 #define M_PHYADDR    0x1fU
36637 #define V_PHYADDR(x) ((x) << S_PHYADDR)
36638 #define G_PHYADDR(x) (((x) >> S_PHYADDR) & M_PHYADDR)
36639 
36640 #define S_REGADDR    0
36641 #define M_REGADDR    0x1fU
36642 #define V_REGADDR(x) ((x) << S_REGADDR)
36643 #define G_REGADDR(x) (((x) >> S_REGADDR) & M_REGADDR)
36644 
36645 #define A_MI_DATA 0x19108
36646 
36647 #define S_MDIDATA    0
36648 #define M_MDIDATA    0xffffU
36649 #define V_MDIDATA(x) ((x) << S_MDIDATA)
36650 #define G_MDIDATA(x) (((x) >> S_MDIDATA) & M_MDIDATA)
36651 
36652 #define A_MI_OP 0x1910c
36653 
36654 #define S_INC    2
36655 #define V_INC(x) ((x) << S_INC)
36656 #define F_INC    V_INC(1U)
36657 
36658 #define S_MDIOP    0
36659 #define M_MDIOP    0x3U
36660 #define V_MDIOP(x) ((x) << S_MDIOP)
36661 #define G_MDIOP(x) (((x) >> S_MDIOP) & M_MDIOP)
36662 
36663 /* registers for module UART */
36664 #define UART_BASE_ADDR 0x19110
36665 
36666 #define A_UART_CONFIG 0x19110
36667 
36668 #define S_STOPBITS    22
36669 #define M_STOPBITS    0x3U
36670 #define V_STOPBITS(x) ((x) << S_STOPBITS)
36671 #define G_STOPBITS(x) (((x) >> S_STOPBITS) & M_STOPBITS)
36672 
36673 #define S_PARITY    20
36674 #define M_PARITY    0x3U
36675 #define V_PARITY(x) ((x) << S_PARITY)
36676 #define G_PARITY(x) (((x) >> S_PARITY) & M_PARITY)
36677 
36678 #define S_DATABITS    16
36679 #define M_DATABITS    0xfU
36680 #define V_DATABITS(x) ((x) << S_DATABITS)
36681 #define G_DATABITS(x) (((x) >> S_DATABITS) & M_DATABITS)
36682 
36683 #define S_UART_CLKDIV    0
36684 #define M_UART_CLKDIV    0xfffU
36685 #define V_UART_CLKDIV(x) ((x) << S_UART_CLKDIV)
36686 #define G_UART_CLKDIV(x) (((x) >> S_UART_CLKDIV) & M_UART_CLKDIV)
36687 
36688 /* registers for module PMU */
36689 #define PMU_BASE_ADDR 0x19120
36690 
36691 #define A_PMU_PART_CG_PWRMODE 0x19120
36692 
36693 #define S_TPPARTCGEN    14
36694 #define V_TPPARTCGEN(x) ((x) << S_TPPARTCGEN)
36695 #define F_TPPARTCGEN    V_TPPARTCGEN(1U)
36696 
36697 #define S_PDPPARTCGEN    13
36698 #define V_PDPPARTCGEN(x) ((x) << S_PDPPARTCGEN)
36699 #define F_PDPPARTCGEN    V_PDPPARTCGEN(1U)
36700 
36701 #define S_PCIEPARTCGEN    12
36702 #define V_PCIEPARTCGEN(x) ((x) << S_PCIEPARTCGEN)
36703 #define F_PCIEPARTCGEN    V_PCIEPARTCGEN(1U)
36704 
36705 #define S_EDC1PARTCGEN    11
36706 #define V_EDC1PARTCGEN(x) ((x) << S_EDC1PARTCGEN)
36707 #define F_EDC1PARTCGEN    V_EDC1PARTCGEN(1U)
36708 
36709 #define S_MCPARTCGEN    10
36710 #define V_MCPARTCGEN(x) ((x) << S_MCPARTCGEN)
36711 #define F_MCPARTCGEN    V_MCPARTCGEN(1U)
36712 
36713 #define S_EDC0PARTCGEN    9
36714 #define V_EDC0PARTCGEN(x) ((x) << S_EDC0PARTCGEN)
36715 #define F_EDC0PARTCGEN    V_EDC0PARTCGEN(1U)
36716 
36717 #define S_LEPARTCGEN    8
36718 #define V_LEPARTCGEN(x) ((x) << S_LEPARTCGEN)
36719 #define F_LEPARTCGEN    V_LEPARTCGEN(1U)
36720 
36721 #define S_INITPOWERMODE    0
36722 #define M_INITPOWERMODE    0x3U
36723 #define V_INITPOWERMODE(x) ((x) << S_INITPOWERMODE)
36724 #define G_INITPOWERMODE(x) (((x) >> S_INITPOWERMODE) & M_INITPOWERMODE)
36725 
36726 #define S_SGE_PART_CGEN    19
36727 #define V_SGE_PART_CGEN(x) ((x) << S_SGE_PART_CGEN)
36728 #define F_SGE_PART_CGEN    V_SGE_PART_CGEN(1U)
36729 
36730 #define S_PDP_PART_CGEN    18
36731 #define V_PDP_PART_CGEN(x) ((x) << S_PDP_PART_CGEN)
36732 #define F_PDP_PART_CGEN    V_PDP_PART_CGEN(1U)
36733 
36734 #define S_TP_PART_CGEN    17
36735 #define V_TP_PART_CGEN(x) ((x) << S_TP_PART_CGEN)
36736 #define F_TP_PART_CGEN    V_TP_PART_CGEN(1U)
36737 
36738 #define S_EDC0_PART_CGEN    16
36739 #define V_EDC0_PART_CGEN(x) ((x) << S_EDC0_PART_CGEN)
36740 #define F_EDC0_PART_CGEN    V_EDC0_PART_CGEN(1U)
36741 
36742 #define S_EDC1_PART_CGEN    15
36743 #define V_EDC1_PART_CGEN(x) ((x) << S_EDC1_PART_CGEN)
36744 #define F_EDC1_PART_CGEN    V_EDC1_PART_CGEN(1U)
36745 
36746 #define S_LE_PART_CGEN    14
36747 #define V_LE_PART_CGEN(x) ((x) << S_LE_PART_CGEN)
36748 #define F_LE_PART_CGEN    V_LE_PART_CGEN(1U)
36749 
36750 #define S_MA_PART_CGEN    13
36751 #define V_MA_PART_CGEN(x) ((x) << S_MA_PART_CGEN)
36752 #define F_MA_PART_CGEN    V_MA_PART_CGEN(1U)
36753 
36754 #define S_MC0_PART_CGEN    12
36755 #define V_MC0_PART_CGEN(x) ((x) << S_MC0_PART_CGEN)
36756 #define F_MC0_PART_CGEN    V_MC0_PART_CGEN(1U)
36757 
36758 #define S_MC1_PART_CGEN    11
36759 #define V_MC1_PART_CGEN(x) ((x) << S_MC1_PART_CGEN)
36760 #define F_MC1_PART_CGEN    V_MC1_PART_CGEN(1U)
36761 
36762 #define S_PCIE_PART_CGEN    10
36763 #define V_PCIE_PART_CGEN(x) ((x) << S_PCIE_PART_CGEN)
36764 #define F_PCIE_PART_CGEN    V_PCIE_PART_CGEN(1U)
36765 
36766 #define S_PL_DIS_PRTY_CHK    20
36767 #define V_PL_DIS_PRTY_CHK(x) ((x) << S_PL_DIS_PRTY_CHK)
36768 #define F_PL_DIS_PRTY_CHK    V_PL_DIS_PRTY_CHK(1U)
36769 
36770 #define A_PMU_SLEEPMODE_WAKEUP 0x19124
36771 
36772 #define S_HWWAKEUPEN    5
36773 #define V_HWWAKEUPEN(x) ((x) << S_HWWAKEUPEN)
36774 #define F_HWWAKEUPEN    V_HWWAKEUPEN(1U)
36775 
36776 #define S_PORT3SLEEPMODE    4
36777 #define V_PORT3SLEEPMODE(x) ((x) << S_PORT3SLEEPMODE)
36778 #define F_PORT3SLEEPMODE    V_PORT3SLEEPMODE(1U)
36779 
36780 #define S_PORT2SLEEPMODE    3
36781 #define V_PORT2SLEEPMODE(x) ((x) << S_PORT2SLEEPMODE)
36782 #define F_PORT2SLEEPMODE    V_PORT2SLEEPMODE(1U)
36783 
36784 #define S_PORT1SLEEPMODE    2
36785 #define V_PORT1SLEEPMODE(x) ((x) << S_PORT1SLEEPMODE)
36786 #define F_PORT1SLEEPMODE    V_PORT1SLEEPMODE(1U)
36787 
36788 #define S_PORT0SLEEPMODE    1
36789 #define V_PORT0SLEEPMODE(x) ((x) << S_PORT0SLEEPMODE)
36790 #define F_PORT0SLEEPMODE    V_PORT0SLEEPMODE(1U)
36791 
36792 #define S_WAKEUP    0
36793 #define V_WAKEUP(x) ((x) << S_WAKEUP)
36794 #define F_WAKEUP    V_WAKEUP(1U)
36795 
36796 #define S_GLOBALDEEPSLEEPEN    6
36797 #define V_GLOBALDEEPSLEEPEN(x) ((x) << S_GLOBALDEEPSLEEPEN)
36798 #define F_GLOBALDEEPSLEEPEN    V_GLOBALDEEPSLEEPEN(1U)
36799 
36800 /* registers for module ULP_RX */
36801 #define ULP_RX_BASE_ADDR 0x19150
36802 
36803 #define A_ULP_RX_CTL 0x19150
36804 
36805 #define S_PCMD1THRESHOLD    24
36806 #define M_PCMD1THRESHOLD    0xffU
36807 #define V_PCMD1THRESHOLD(x) ((x) << S_PCMD1THRESHOLD)
36808 #define G_PCMD1THRESHOLD(x) (((x) >> S_PCMD1THRESHOLD) & M_PCMD1THRESHOLD)
36809 
36810 #define S_PCMD0THRESHOLD    16
36811 #define M_PCMD0THRESHOLD    0xffU
36812 #define V_PCMD0THRESHOLD(x) ((x) << S_PCMD0THRESHOLD)
36813 #define G_PCMD0THRESHOLD(x) (((x) >> S_PCMD0THRESHOLD) & M_PCMD0THRESHOLD)
36814 
36815 #define S_DISABLE_0B_STAG_ERR    14
36816 #define V_DISABLE_0B_STAG_ERR(x) ((x) << S_DISABLE_0B_STAG_ERR)
36817 #define F_DISABLE_0B_STAG_ERR    V_DISABLE_0B_STAG_ERR(1U)
36818 
36819 #define S_RDMA_0B_WR_OPCODE    10
36820 #define M_RDMA_0B_WR_OPCODE    0xfU
36821 #define V_RDMA_0B_WR_OPCODE(x) ((x) << S_RDMA_0B_WR_OPCODE)
36822 #define G_RDMA_0B_WR_OPCODE(x) (((x) >> S_RDMA_0B_WR_OPCODE) & M_RDMA_0B_WR_OPCODE)
36823 
36824 #define S_RDMA_0B_WR_PASS    9
36825 #define V_RDMA_0B_WR_PASS(x) ((x) << S_RDMA_0B_WR_PASS)
36826 #define F_RDMA_0B_WR_PASS    V_RDMA_0B_WR_PASS(1U)
36827 
36828 #define S_STAG_RQE    8
36829 #define V_STAG_RQE(x) ((x) << S_STAG_RQE)
36830 #define F_STAG_RQE    V_STAG_RQE(1U)
36831 
36832 #define S_RDMA_STATE_EN    7
36833 #define V_RDMA_STATE_EN(x) ((x) << S_RDMA_STATE_EN)
36834 #define F_RDMA_STATE_EN    V_RDMA_STATE_EN(1U)
36835 
36836 #define S_CRC1_EN    6
36837 #define V_CRC1_EN(x) ((x) << S_CRC1_EN)
36838 #define F_CRC1_EN    V_CRC1_EN(1U)
36839 
36840 #define S_RDMA_0B_WR_CQE    5
36841 #define V_RDMA_0B_WR_CQE(x) ((x) << S_RDMA_0B_WR_CQE)
36842 #define F_RDMA_0B_WR_CQE    V_RDMA_0B_WR_CQE(1U)
36843 
36844 #define S_PCIE_ATRB_EN    4
36845 #define V_PCIE_ATRB_EN(x) ((x) << S_PCIE_ATRB_EN)
36846 #define F_PCIE_ATRB_EN    V_PCIE_ATRB_EN(1U)
36847 
36848 #define S_RDMA_PERMISSIVE_MODE    3
36849 #define V_RDMA_PERMISSIVE_MODE(x) ((x) << S_RDMA_PERMISSIVE_MODE)
36850 #define F_RDMA_PERMISSIVE_MODE    V_RDMA_PERMISSIVE_MODE(1U)
36851 
36852 #define S_PAGEPODME    2
36853 #define V_PAGEPODME(x) ((x) << S_PAGEPODME)
36854 #define F_PAGEPODME    V_PAGEPODME(1U)
36855 
36856 #define S_ISCSITAGTCB    1
36857 #define V_ISCSITAGTCB(x) ((x) << S_ISCSITAGTCB)
36858 #define F_ISCSITAGTCB    V_ISCSITAGTCB(1U)
36859 
36860 #define S_TDDPTAGTCB    0
36861 #define V_TDDPTAGTCB(x) ((x) << S_TDDPTAGTCB)
36862 #define F_TDDPTAGTCB    V_TDDPTAGTCB(1U)
36863 
36864 #define A_ULP_RX_INT_ENABLE 0x19154
36865 
36866 #define S_ENABLE_CTX_1    24
36867 #define V_ENABLE_CTX_1(x) ((x) << S_ENABLE_CTX_1)
36868 #define F_ENABLE_CTX_1    V_ENABLE_CTX_1(1U)
36869 
36870 #define S_ENABLE_CTX_0    23
36871 #define V_ENABLE_CTX_0(x) ((x) << S_ENABLE_CTX_0)
36872 #define F_ENABLE_CTX_0    V_ENABLE_CTX_0(1U)
36873 
36874 #define S_ENABLE_FF    22
36875 #define V_ENABLE_FF(x) ((x) << S_ENABLE_FF)
36876 #define F_ENABLE_FF    V_ENABLE_FF(1U)
36877 
36878 #define S_ENABLE_APF_1    21
36879 #define V_ENABLE_APF_1(x) ((x) << S_ENABLE_APF_1)
36880 #define F_ENABLE_APF_1    V_ENABLE_APF_1(1U)
36881 
36882 #define S_ENABLE_APF_0    20
36883 #define V_ENABLE_APF_0(x) ((x) << S_ENABLE_APF_0)
36884 #define F_ENABLE_APF_0    V_ENABLE_APF_0(1U)
36885 
36886 #define S_ENABLE_AF_1    19
36887 #define V_ENABLE_AF_1(x) ((x) << S_ENABLE_AF_1)
36888 #define F_ENABLE_AF_1    V_ENABLE_AF_1(1U)
36889 
36890 #define S_ENABLE_AF_0    18
36891 #define V_ENABLE_AF_0(x) ((x) << S_ENABLE_AF_0)
36892 #define F_ENABLE_AF_0    V_ENABLE_AF_0(1U)
36893 
36894 #define S_ENABLE_DDPDF_1    17
36895 #define V_ENABLE_DDPDF_1(x) ((x) << S_ENABLE_DDPDF_1)
36896 #define F_ENABLE_DDPDF_1    V_ENABLE_DDPDF_1(1U)
36897 
36898 #define S_ENABLE_DDPMF_1    16
36899 #define V_ENABLE_DDPMF_1(x) ((x) << S_ENABLE_DDPMF_1)
36900 #define F_ENABLE_DDPMF_1    V_ENABLE_DDPMF_1(1U)
36901 
36902 #define S_ENABLE_MEMRF_1    15
36903 #define V_ENABLE_MEMRF_1(x) ((x) << S_ENABLE_MEMRF_1)
36904 #define F_ENABLE_MEMRF_1    V_ENABLE_MEMRF_1(1U)
36905 
36906 #define S_ENABLE_PRSDF_1    14
36907 #define V_ENABLE_PRSDF_1(x) ((x) << S_ENABLE_PRSDF_1)
36908 #define F_ENABLE_PRSDF_1    V_ENABLE_PRSDF_1(1U)
36909 
36910 #define S_ENABLE_DDPDF_0    13
36911 #define V_ENABLE_DDPDF_0(x) ((x) << S_ENABLE_DDPDF_0)
36912 #define F_ENABLE_DDPDF_0    V_ENABLE_DDPDF_0(1U)
36913 
36914 #define S_ENABLE_DDPMF_0    12
36915 #define V_ENABLE_DDPMF_0(x) ((x) << S_ENABLE_DDPMF_0)
36916 #define F_ENABLE_DDPMF_0    V_ENABLE_DDPMF_0(1U)
36917 
36918 #define S_ENABLE_MEMRF_0    11
36919 #define V_ENABLE_MEMRF_0(x) ((x) << S_ENABLE_MEMRF_0)
36920 #define F_ENABLE_MEMRF_0    V_ENABLE_MEMRF_0(1U)
36921 
36922 #define S_ENABLE_PRSDF_0    10
36923 #define V_ENABLE_PRSDF_0(x) ((x) << S_ENABLE_PRSDF_0)
36924 #define F_ENABLE_PRSDF_0    V_ENABLE_PRSDF_0(1U)
36925 
36926 #define S_ENABLE_PCMDF_1    9
36927 #define V_ENABLE_PCMDF_1(x) ((x) << S_ENABLE_PCMDF_1)
36928 #define F_ENABLE_PCMDF_1    V_ENABLE_PCMDF_1(1U)
36929 
36930 #define S_ENABLE_TPTCF_1    8
36931 #define V_ENABLE_TPTCF_1(x) ((x) << S_ENABLE_TPTCF_1)
36932 #define F_ENABLE_TPTCF_1    V_ENABLE_TPTCF_1(1U)
36933 
36934 #define S_ENABLE_DDPCF_1    7
36935 #define V_ENABLE_DDPCF_1(x) ((x) << S_ENABLE_DDPCF_1)
36936 #define F_ENABLE_DDPCF_1    V_ENABLE_DDPCF_1(1U)
36937 
36938 #define S_ENABLE_MPARF_1    6
36939 #define V_ENABLE_MPARF_1(x) ((x) << S_ENABLE_MPARF_1)
36940 #define F_ENABLE_MPARF_1    V_ENABLE_MPARF_1(1U)
36941 
36942 #define S_ENABLE_MPARC_1    5
36943 #define V_ENABLE_MPARC_1(x) ((x) << S_ENABLE_MPARC_1)
36944 #define F_ENABLE_MPARC_1    V_ENABLE_MPARC_1(1U)
36945 
36946 #define S_ENABLE_PCMDF_0    4
36947 #define V_ENABLE_PCMDF_0(x) ((x) << S_ENABLE_PCMDF_0)
36948 #define F_ENABLE_PCMDF_0    V_ENABLE_PCMDF_0(1U)
36949 
36950 #define S_ENABLE_TPTCF_0    3
36951 #define V_ENABLE_TPTCF_0(x) ((x) << S_ENABLE_TPTCF_0)
36952 #define F_ENABLE_TPTCF_0    V_ENABLE_TPTCF_0(1U)
36953 
36954 #define S_ENABLE_DDPCF_0    2
36955 #define V_ENABLE_DDPCF_0(x) ((x) << S_ENABLE_DDPCF_0)
36956 #define F_ENABLE_DDPCF_0    V_ENABLE_DDPCF_0(1U)
36957 
36958 #define S_ENABLE_MPARF_0    1
36959 #define V_ENABLE_MPARF_0(x) ((x) << S_ENABLE_MPARF_0)
36960 #define F_ENABLE_MPARF_0    V_ENABLE_MPARF_0(1U)
36961 
36962 #define S_ENABLE_MPARC_0    0
36963 #define V_ENABLE_MPARC_0(x) ((x) << S_ENABLE_MPARC_0)
36964 #define F_ENABLE_MPARC_0    V_ENABLE_MPARC_0(1U)
36965 
36966 #define S_SE_CNT_MISMATCH_1    26
36967 #define V_SE_CNT_MISMATCH_1(x) ((x) << S_SE_CNT_MISMATCH_1)
36968 #define F_SE_CNT_MISMATCH_1    V_SE_CNT_MISMATCH_1(1U)
36969 
36970 #define S_SE_CNT_MISMATCH_0    25
36971 #define V_SE_CNT_MISMATCH_0(x) ((x) << S_SE_CNT_MISMATCH_0)
36972 #define F_SE_CNT_MISMATCH_0    V_SE_CNT_MISMATCH_0(1U)
36973 
36974 #define A_ULP_RX_INT_CAUSE 0x19158
36975 
36976 #define S_CAUSE_CTX_1    24
36977 #define V_CAUSE_CTX_1(x) ((x) << S_CAUSE_CTX_1)
36978 #define F_CAUSE_CTX_1    V_CAUSE_CTX_1(1U)
36979 
36980 #define S_CAUSE_CTX_0    23
36981 #define V_CAUSE_CTX_0(x) ((x) << S_CAUSE_CTX_0)
36982 #define F_CAUSE_CTX_0    V_CAUSE_CTX_0(1U)
36983 
36984 #define S_CAUSE_FF    22
36985 #define V_CAUSE_FF(x) ((x) << S_CAUSE_FF)
36986 #define F_CAUSE_FF    V_CAUSE_FF(1U)
36987 
36988 #define S_CAUSE_APF_1    21
36989 #define V_CAUSE_APF_1(x) ((x) << S_CAUSE_APF_1)
36990 #define F_CAUSE_APF_1    V_CAUSE_APF_1(1U)
36991 
36992 #define S_CAUSE_APF_0    20
36993 #define V_CAUSE_APF_0(x) ((x) << S_CAUSE_APF_0)
36994 #define F_CAUSE_APF_0    V_CAUSE_APF_0(1U)
36995 
36996 #define S_CAUSE_AF_1    19
36997 #define V_CAUSE_AF_1(x) ((x) << S_CAUSE_AF_1)
36998 #define F_CAUSE_AF_1    V_CAUSE_AF_1(1U)
36999 
37000 #define S_CAUSE_AF_0    18
37001 #define V_CAUSE_AF_0(x) ((x) << S_CAUSE_AF_0)
37002 #define F_CAUSE_AF_0    V_CAUSE_AF_0(1U)
37003 
37004 #define S_CAUSE_DDPDF_1    17
37005 #define V_CAUSE_DDPDF_1(x) ((x) << S_CAUSE_DDPDF_1)
37006 #define F_CAUSE_DDPDF_1    V_CAUSE_DDPDF_1(1U)
37007 
37008 #define S_CAUSE_DDPMF_1    16
37009 #define V_CAUSE_DDPMF_1(x) ((x) << S_CAUSE_DDPMF_1)
37010 #define F_CAUSE_DDPMF_1    V_CAUSE_DDPMF_1(1U)
37011 
37012 #define S_CAUSE_MEMRF_1    15
37013 #define V_CAUSE_MEMRF_1(x) ((x) << S_CAUSE_MEMRF_1)
37014 #define F_CAUSE_MEMRF_1    V_CAUSE_MEMRF_1(1U)
37015 
37016 #define S_CAUSE_PRSDF_1    14
37017 #define V_CAUSE_PRSDF_1(x) ((x) << S_CAUSE_PRSDF_1)
37018 #define F_CAUSE_PRSDF_1    V_CAUSE_PRSDF_1(1U)
37019 
37020 #define S_CAUSE_DDPDF_0    13
37021 #define V_CAUSE_DDPDF_0(x) ((x) << S_CAUSE_DDPDF_0)
37022 #define F_CAUSE_DDPDF_0    V_CAUSE_DDPDF_0(1U)
37023 
37024 #define S_CAUSE_DDPMF_0    12
37025 #define V_CAUSE_DDPMF_0(x) ((x) << S_CAUSE_DDPMF_0)
37026 #define F_CAUSE_DDPMF_0    V_CAUSE_DDPMF_0(1U)
37027 
37028 #define S_CAUSE_MEMRF_0    11
37029 #define V_CAUSE_MEMRF_0(x) ((x) << S_CAUSE_MEMRF_0)
37030 #define F_CAUSE_MEMRF_0    V_CAUSE_MEMRF_0(1U)
37031 
37032 #define S_CAUSE_PRSDF_0    10
37033 #define V_CAUSE_PRSDF_0(x) ((x) << S_CAUSE_PRSDF_0)
37034 #define F_CAUSE_PRSDF_0    V_CAUSE_PRSDF_0(1U)
37035 
37036 #define S_CAUSE_PCMDF_1    9
37037 #define V_CAUSE_PCMDF_1(x) ((x) << S_CAUSE_PCMDF_1)
37038 #define F_CAUSE_PCMDF_1    V_CAUSE_PCMDF_1(1U)
37039 
37040 #define S_CAUSE_TPTCF_1    8
37041 #define V_CAUSE_TPTCF_1(x) ((x) << S_CAUSE_TPTCF_1)
37042 #define F_CAUSE_TPTCF_1    V_CAUSE_TPTCF_1(1U)
37043 
37044 #define S_CAUSE_DDPCF_1    7
37045 #define V_CAUSE_DDPCF_1(x) ((x) << S_CAUSE_DDPCF_1)
37046 #define F_CAUSE_DDPCF_1    V_CAUSE_DDPCF_1(1U)
37047 
37048 #define S_CAUSE_MPARF_1    6
37049 #define V_CAUSE_MPARF_1(x) ((x) << S_CAUSE_MPARF_1)
37050 #define F_CAUSE_MPARF_1    V_CAUSE_MPARF_1(1U)
37051 
37052 #define S_CAUSE_MPARC_1    5
37053 #define V_CAUSE_MPARC_1(x) ((x) << S_CAUSE_MPARC_1)
37054 #define F_CAUSE_MPARC_1    V_CAUSE_MPARC_1(1U)
37055 
37056 #define S_CAUSE_PCMDF_0    4
37057 #define V_CAUSE_PCMDF_0(x) ((x) << S_CAUSE_PCMDF_0)
37058 #define F_CAUSE_PCMDF_0    V_CAUSE_PCMDF_0(1U)
37059 
37060 #define S_CAUSE_TPTCF_0    3
37061 #define V_CAUSE_TPTCF_0(x) ((x) << S_CAUSE_TPTCF_0)
37062 #define F_CAUSE_TPTCF_0    V_CAUSE_TPTCF_0(1U)
37063 
37064 #define S_CAUSE_DDPCF_0    2
37065 #define V_CAUSE_DDPCF_0(x) ((x) << S_CAUSE_DDPCF_0)
37066 #define F_CAUSE_DDPCF_0    V_CAUSE_DDPCF_0(1U)
37067 
37068 #define S_CAUSE_MPARF_0    1
37069 #define V_CAUSE_MPARF_0(x) ((x) << S_CAUSE_MPARF_0)
37070 #define F_CAUSE_MPARF_0    V_CAUSE_MPARF_0(1U)
37071 
37072 #define S_CAUSE_MPARC_0    0
37073 #define V_CAUSE_MPARC_0(x) ((x) << S_CAUSE_MPARC_0)
37074 #define F_CAUSE_MPARC_0    V_CAUSE_MPARC_0(1U)
37075 
37076 #define A_ULP_RX_ISCSI_LLIMIT 0x1915c
37077 
37078 #define S_ISCSILLIMIT    6
37079 #define M_ISCSILLIMIT    0x3ffffffU
37080 #define V_ISCSILLIMIT(x) ((x) << S_ISCSILLIMIT)
37081 #define G_ISCSILLIMIT(x) (((x) >> S_ISCSILLIMIT) & M_ISCSILLIMIT)
37082 
37083 #define A_ULP_RX_ISCSI_ULIMIT 0x19160
37084 
37085 #define S_ISCSIULIMIT    6
37086 #define M_ISCSIULIMIT    0x3ffffffU
37087 #define V_ISCSIULIMIT(x) ((x) << S_ISCSIULIMIT)
37088 #define G_ISCSIULIMIT(x) (((x) >> S_ISCSIULIMIT) & M_ISCSIULIMIT)
37089 
37090 #define A_ULP_RX_ISCSI_TAGMASK 0x19164
37091 
37092 #define S_ISCSITAGMASK    6
37093 #define M_ISCSITAGMASK    0x3ffffffU
37094 #define V_ISCSITAGMASK(x) ((x) << S_ISCSITAGMASK)
37095 #define G_ISCSITAGMASK(x) (((x) >> S_ISCSITAGMASK) & M_ISCSITAGMASK)
37096 
37097 #define A_ULP_RX_ISCSI_PSZ 0x19168
37098 
37099 #define S_HPZ3    24
37100 #define M_HPZ3    0xfU
37101 #define V_HPZ3(x) ((x) << S_HPZ3)
37102 #define G_HPZ3(x) (((x) >> S_HPZ3) & M_HPZ3)
37103 
37104 #define S_HPZ2    16
37105 #define M_HPZ2    0xfU
37106 #define V_HPZ2(x) ((x) << S_HPZ2)
37107 #define G_HPZ2(x) (((x) >> S_HPZ2) & M_HPZ2)
37108 
37109 #define S_HPZ1    8
37110 #define M_HPZ1    0xfU
37111 #define V_HPZ1(x) ((x) << S_HPZ1)
37112 #define G_HPZ1(x) (((x) >> S_HPZ1) & M_HPZ1)
37113 
37114 #define S_HPZ0    0
37115 #define M_HPZ0    0xfU
37116 #define V_HPZ0(x) ((x) << S_HPZ0)
37117 #define G_HPZ0(x) (((x) >> S_HPZ0) & M_HPZ0)
37118 
37119 #define A_ULP_RX_TDDP_LLIMIT 0x1916c
37120 
37121 #define S_TDDPLLIMIT    6
37122 #define M_TDDPLLIMIT    0x3ffffffU
37123 #define V_TDDPLLIMIT(x) ((x) << S_TDDPLLIMIT)
37124 #define G_TDDPLLIMIT(x) (((x) >> S_TDDPLLIMIT) & M_TDDPLLIMIT)
37125 
37126 #define A_ULP_RX_TDDP_ULIMIT 0x19170
37127 
37128 #define S_TDDPULIMIT    6
37129 #define M_TDDPULIMIT    0x3ffffffU
37130 #define V_TDDPULIMIT(x) ((x) << S_TDDPULIMIT)
37131 #define G_TDDPULIMIT(x) (((x) >> S_TDDPULIMIT) & M_TDDPULIMIT)
37132 
37133 #define A_ULP_RX_TDDP_TAGMASK 0x19174
37134 
37135 #define S_TDDPTAGMASK    6
37136 #define M_TDDPTAGMASK    0x3ffffffU
37137 #define V_TDDPTAGMASK(x) ((x) << S_TDDPTAGMASK)
37138 #define G_TDDPTAGMASK(x) (((x) >> S_TDDPTAGMASK) & M_TDDPTAGMASK)
37139 
37140 #define A_ULP_RX_TDDP_PSZ 0x19178
37141 #define A_ULP_RX_STAG_LLIMIT 0x1917c
37142 #define A_ULP_RX_STAG_ULIMIT 0x19180
37143 #define A_ULP_RX_RQ_LLIMIT 0x19184
37144 #define A_ULP_RX_RQ_ULIMIT 0x19188
37145 #define A_ULP_RX_PBL_LLIMIT 0x1918c
37146 #define A_ULP_RX_PBL_ULIMIT 0x19190
37147 #define A_ULP_RX_CTX_BASE 0x19194
37148 #define A_ULP_RX_PERR_ENABLE 0x1919c
37149 
37150 #define S_PERR_ENABLE_FF    22
37151 #define V_PERR_ENABLE_FF(x) ((x) << S_PERR_ENABLE_FF)
37152 #define F_PERR_ENABLE_FF    V_PERR_ENABLE_FF(1U)
37153 
37154 #define S_PERR_ENABLE_APF_1    21
37155 #define V_PERR_ENABLE_APF_1(x) ((x) << S_PERR_ENABLE_APF_1)
37156 #define F_PERR_ENABLE_APF_1    V_PERR_ENABLE_APF_1(1U)
37157 
37158 #define S_PERR_ENABLE_APF_0    20
37159 #define V_PERR_ENABLE_APF_0(x) ((x) << S_PERR_ENABLE_APF_0)
37160 #define F_PERR_ENABLE_APF_0    V_PERR_ENABLE_APF_0(1U)
37161 
37162 #define S_PERR_ENABLE_AF_1    19
37163 #define V_PERR_ENABLE_AF_1(x) ((x) << S_PERR_ENABLE_AF_1)
37164 #define F_PERR_ENABLE_AF_1    V_PERR_ENABLE_AF_1(1U)
37165 
37166 #define S_PERR_ENABLE_AF_0    18
37167 #define V_PERR_ENABLE_AF_0(x) ((x) << S_PERR_ENABLE_AF_0)
37168 #define F_PERR_ENABLE_AF_0    V_PERR_ENABLE_AF_0(1U)
37169 
37170 #define S_PERR_ENABLE_DDPDF_1    17
37171 #define V_PERR_ENABLE_DDPDF_1(x) ((x) << S_PERR_ENABLE_DDPDF_1)
37172 #define F_PERR_ENABLE_DDPDF_1    V_PERR_ENABLE_DDPDF_1(1U)
37173 
37174 #define S_PERR_ENABLE_DDPMF_1    16
37175 #define V_PERR_ENABLE_DDPMF_1(x) ((x) << S_PERR_ENABLE_DDPMF_1)
37176 #define F_PERR_ENABLE_DDPMF_1    V_PERR_ENABLE_DDPMF_1(1U)
37177 
37178 #define S_PERR_ENABLE_MEMRF_1    15
37179 #define V_PERR_ENABLE_MEMRF_1(x) ((x) << S_PERR_ENABLE_MEMRF_1)
37180 #define F_PERR_ENABLE_MEMRF_1    V_PERR_ENABLE_MEMRF_1(1U)
37181 
37182 #define S_PERR_ENABLE_PRSDF_1    14
37183 #define V_PERR_ENABLE_PRSDF_1(x) ((x) << S_PERR_ENABLE_PRSDF_1)
37184 #define F_PERR_ENABLE_PRSDF_1    V_PERR_ENABLE_PRSDF_1(1U)
37185 
37186 #define S_PERR_ENABLE_DDPDF_0    13
37187 #define V_PERR_ENABLE_DDPDF_0(x) ((x) << S_PERR_ENABLE_DDPDF_0)
37188 #define F_PERR_ENABLE_DDPDF_0    V_PERR_ENABLE_DDPDF_0(1U)
37189 
37190 #define S_PERR_ENABLE_DDPMF_0    12
37191 #define V_PERR_ENABLE_DDPMF_0(x) ((x) << S_PERR_ENABLE_DDPMF_0)
37192 #define F_PERR_ENABLE_DDPMF_0    V_PERR_ENABLE_DDPMF_0(1U)
37193 
37194 #define S_PERR_ENABLE_MEMRF_0    11
37195 #define V_PERR_ENABLE_MEMRF_0(x) ((x) << S_PERR_ENABLE_MEMRF_0)
37196 #define F_PERR_ENABLE_MEMRF_0    V_PERR_ENABLE_MEMRF_0(1U)
37197 
37198 #define S_PERR_ENABLE_PRSDF_0    10
37199 #define V_PERR_ENABLE_PRSDF_0(x) ((x) << S_PERR_ENABLE_PRSDF_0)
37200 #define F_PERR_ENABLE_PRSDF_0    V_PERR_ENABLE_PRSDF_0(1U)
37201 
37202 #define S_PERR_ENABLE_PCMDF_1    9
37203 #define V_PERR_ENABLE_PCMDF_1(x) ((x) << S_PERR_ENABLE_PCMDF_1)
37204 #define F_PERR_ENABLE_PCMDF_1    V_PERR_ENABLE_PCMDF_1(1U)
37205 
37206 #define S_PERR_ENABLE_TPTCF_1    8
37207 #define V_PERR_ENABLE_TPTCF_1(x) ((x) << S_PERR_ENABLE_TPTCF_1)
37208 #define F_PERR_ENABLE_TPTCF_1    V_PERR_ENABLE_TPTCF_1(1U)
37209 
37210 #define S_PERR_ENABLE_DDPCF_1    7
37211 #define V_PERR_ENABLE_DDPCF_1(x) ((x) << S_PERR_ENABLE_DDPCF_1)
37212 #define F_PERR_ENABLE_DDPCF_1    V_PERR_ENABLE_DDPCF_1(1U)
37213 
37214 #define S_PERR_ENABLE_MPARF_1    6
37215 #define V_PERR_ENABLE_MPARF_1(x) ((x) << S_PERR_ENABLE_MPARF_1)
37216 #define F_PERR_ENABLE_MPARF_1    V_PERR_ENABLE_MPARF_1(1U)
37217 
37218 #define S_PERR_ENABLE_MPARC_1    5
37219 #define V_PERR_ENABLE_MPARC_1(x) ((x) << S_PERR_ENABLE_MPARC_1)
37220 #define F_PERR_ENABLE_MPARC_1    V_PERR_ENABLE_MPARC_1(1U)
37221 
37222 #define S_PERR_ENABLE_PCMDF_0    4
37223 #define V_PERR_ENABLE_PCMDF_0(x) ((x) << S_PERR_ENABLE_PCMDF_0)
37224 #define F_PERR_ENABLE_PCMDF_0    V_PERR_ENABLE_PCMDF_0(1U)
37225 
37226 #define S_PERR_ENABLE_TPTCF_0    3
37227 #define V_PERR_ENABLE_TPTCF_0(x) ((x) << S_PERR_ENABLE_TPTCF_0)
37228 #define F_PERR_ENABLE_TPTCF_0    V_PERR_ENABLE_TPTCF_0(1U)
37229 
37230 #define S_PERR_ENABLE_DDPCF_0    2
37231 #define V_PERR_ENABLE_DDPCF_0(x) ((x) << S_PERR_ENABLE_DDPCF_0)
37232 #define F_PERR_ENABLE_DDPCF_0    V_PERR_ENABLE_DDPCF_0(1U)
37233 
37234 #define S_PERR_ENABLE_MPARF_0    1
37235 #define V_PERR_ENABLE_MPARF_0(x) ((x) << S_PERR_ENABLE_MPARF_0)
37236 #define F_PERR_ENABLE_MPARF_0    V_PERR_ENABLE_MPARF_0(1U)
37237 
37238 #define S_PERR_ENABLE_MPARC_0    0
37239 #define V_PERR_ENABLE_MPARC_0(x) ((x) << S_PERR_ENABLE_MPARC_0)
37240 #define F_PERR_ENABLE_MPARC_0    V_PERR_ENABLE_MPARC_0(1U)
37241 
37242 #define S_PERR_SE_CNT_MISMATCH_1    26
37243 #define V_PERR_SE_CNT_MISMATCH_1(x) ((x) << S_PERR_SE_CNT_MISMATCH_1)
37244 #define F_PERR_SE_CNT_MISMATCH_1    V_PERR_SE_CNT_MISMATCH_1(1U)
37245 
37246 #define S_PERR_SE_CNT_MISMATCH_0    25
37247 #define V_PERR_SE_CNT_MISMATCH_0(x) ((x) << S_PERR_SE_CNT_MISMATCH_0)
37248 #define F_PERR_SE_CNT_MISMATCH_0    V_PERR_SE_CNT_MISMATCH_0(1U)
37249 
37250 #define S_PERR_RSVD0    24
37251 #define V_PERR_RSVD0(x) ((x) << S_PERR_RSVD0)
37252 #define F_PERR_RSVD0    V_PERR_RSVD0(1U)
37253 
37254 #define S_PERR_RSVD1    23
37255 #define V_PERR_RSVD1(x) ((x) << S_PERR_RSVD1)
37256 #define F_PERR_RSVD1    V_PERR_RSVD1(1U)
37257 
37258 #define S_PERR_ENABLE_CTX_1    24
37259 #define V_PERR_ENABLE_CTX_1(x) ((x) << S_PERR_ENABLE_CTX_1)
37260 #define F_PERR_ENABLE_CTX_1    V_PERR_ENABLE_CTX_1(1U)
37261 
37262 #define S_PERR_ENABLE_CTX_0    23
37263 #define V_PERR_ENABLE_CTX_0(x) ((x) << S_PERR_ENABLE_CTX_0)
37264 #define F_PERR_ENABLE_CTX_0    V_PERR_ENABLE_CTX_0(1U)
37265 
37266 #define A_ULP_RX_PERR_INJECT 0x191a0
37267 #define A_ULP_RX_RQUDP_LLIMIT 0x191a4
37268 #define A_ULP_RX_RQUDP_ULIMIT 0x191a8
37269 #define A_ULP_RX_CTX_ACC_CH0 0x191ac
37270 
37271 #define S_REQ    21
37272 #define V_REQ(x) ((x) << S_REQ)
37273 #define F_REQ    V_REQ(1U)
37274 
37275 #define S_WB    20
37276 #define V_WB(x) ((x) << S_WB)
37277 #define F_WB    V_WB(1U)
37278 
37279 #define S_ULPRX_TID    0
37280 #define M_ULPRX_TID    0xfffffU
37281 #define V_ULPRX_TID(x) ((x) << S_ULPRX_TID)
37282 #define G_ULPRX_TID(x) (((x) >> S_ULPRX_TID) & M_ULPRX_TID)
37283 
37284 #define A_ULP_RX_CTX_ACC_CH1 0x191b0
37285 #define A_ULP_RX_SE_CNT_ERR 0x191d0
37286 #define A_ULP_RX_SE_CNT_CLR 0x191d4
37287 
37288 #define S_CLRCHAN0    4
37289 #define M_CLRCHAN0    0xfU
37290 #define V_CLRCHAN0(x) ((x) << S_CLRCHAN0)
37291 #define G_CLRCHAN0(x) (((x) >> S_CLRCHAN0) & M_CLRCHAN0)
37292 
37293 #define S_CLRCHAN1    0
37294 #define M_CLRCHAN1    0xfU
37295 #define V_CLRCHAN1(x) ((x) << S_CLRCHAN1)
37296 #define G_CLRCHAN1(x) (((x) >> S_CLRCHAN1) & M_CLRCHAN1)
37297 
37298 #define A_ULP_RX_SE_CNT_CH0 0x191d8
37299 
37300 #define S_SOP_CNT_OUT0    28
37301 #define M_SOP_CNT_OUT0    0xfU
37302 #define V_SOP_CNT_OUT0(x) ((x) << S_SOP_CNT_OUT0)
37303 #define G_SOP_CNT_OUT0(x) (((x) >> S_SOP_CNT_OUT0) & M_SOP_CNT_OUT0)
37304 
37305 #define S_EOP_CNT_OUT0    24
37306 #define M_EOP_CNT_OUT0    0xfU
37307 #define V_EOP_CNT_OUT0(x) ((x) << S_EOP_CNT_OUT0)
37308 #define G_EOP_CNT_OUT0(x) (((x) >> S_EOP_CNT_OUT0) & M_EOP_CNT_OUT0)
37309 
37310 #define S_SOP_CNT_AL0    20
37311 #define M_SOP_CNT_AL0    0xfU
37312 #define V_SOP_CNT_AL0(x) ((x) << S_SOP_CNT_AL0)
37313 #define G_SOP_CNT_AL0(x) (((x) >> S_SOP_CNT_AL0) & M_SOP_CNT_AL0)
37314 
37315 #define S_EOP_CNT_AL0    16
37316 #define M_EOP_CNT_AL0    0xfU
37317 #define V_EOP_CNT_AL0(x) ((x) << S_EOP_CNT_AL0)
37318 #define G_EOP_CNT_AL0(x) (((x) >> S_EOP_CNT_AL0) & M_EOP_CNT_AL0)
37319 
37320 #define S_SOP_CNT_MR0    12
37321 #define M_SOP_CNT_MR0    0xfU
37322 #define V_SOP_CNT_MR0(x) ((x) << S_SOP_CNT_MR0)
37323 #define G_SOP_CNT_MR0(x) (((x) >> S_SOP_CNT_MR0) & M_SOP_CNT_MR0)
37324 
37325 #define S_EOP_CNT_MR0    8
37326 #define M_EOP_CNT_MR0    0xfU
37327 #define V_EOP_CNT_MR0(x) ((x) << S_EOP_CNT_MR0)
37328 #define G_EOP_CNT_MR0(x) (((x) >> S_EOP_CNT_MR0) & M_EOP_CNT_MR0)
37329 
37330 #define S_SOP_CNT_IN0    4
37331 #define M_SOP_CNT_IN0    0xfU
37332 #define V_SOP_CNT_IN0(x) ((x) << S_SOP_CNT_IN0)
37333 #define G_SOP_CNT_IN0(x) (((x) >> S_SOP_CNT_IN0) & M_SOP_CNT_IN0)
37334 
37335 #define S_EOP_CNT_IN0    0
37336 #define M_EOP_CNT_IN0    0xfU
37337 #define V_EOP_CNT_IN0(x) ((x) << S_EOP_CNT_IN0)
37338 #define G_EOP_CNT_IN0(x) (((x) >> S_EOP_CNT_IN0) & M_EOP_CNT_IN0)
37339 
37340 #define A_ULP_RX_SE_CNT_CH1 0x191dc
37341 
37342 #define S_SOP_CNT_OUT1    28
37343 #define M_SOP_CNT_OUT1    0xfU
37344 #define V_SOP_CNT_OUT1(x) ((x) << S_SOP_CNT_OUT1)
37345 #define G_SOP_CNT_OUT1(x) (((x) >> S_SOP_CNT_OUT1) & M_SOP_CNT_OUT1)
37346 
37347 #define S_EOP_CNT_OUT1    24
37348 #define M_EOP_CNT_OUT1    0xfU
37349 #define V_EOP_CNT_OUT1(x) ((x) << S_EOP_CNT_OUT1)
37350 #define G_EOP_CNT_OUT1(x) (((x) >> S_EOP_CNT_OUT1) & M_EOP_CNT_OUT1)
37351 
37352 #define S_SOP_CNT_AL1    20
37353 #define M_SOP_CNT_AL1    0xfU
37354 #define V_SOP_CNT_AL1(x) ((x) << S_SOP_CNT_AL1)
37355 #define G_SOP_CNT_AL1(x) (((x) >> S_SOP_CNT_AL1) & M_SOP_CNT_AL1)
37356 
37357 #define S_EOP_CNT_AL1    16
37358 #define M_EOP_CNT_AL1    0xfU
37359 #define V_EOP_CNT_AL1(x) ((x) << S_EOP_CNT_AL1)
37360 #define G_EOP_CNT_AL1(x) (((x) >> S_EOP_CNT_AL1) & M_EOP_CNT_AL1)
37361 
37362 #define S_SOP_CNT_MR1    12
37363 #define M_SOP_CNT_MR1    0xfU
37364 #define V_SOP_CNT_MR1(x) ((x) << S_SOP_CNT_MR1)
37365 #define G_SOP_CNT_MR1(x) (((x) >> S_SOP_CNT_MR1) & M_SOP_CNT_MR1)
37366 
37367 #define S_EOP_CNT_MR1    8
37368 #define M_EOP_CNT_MR1    0xfU
37369 #define V_EOP_CNT_MR1(x) ((x) << S_EOP_CNT_MR1)
37370 #define G_EOP_CNT_MR1(x) (((x) >> S_EOP_CNT_MR1) & M_EOP_CNT_MR1)
37371 
37372 #define S_SOP_CNT_IN1    4
37373 #define M_SOP_CNT_IN1    0xfU
37374 #define V_SOP_CNT_IN1(x) ((x) << S_SOP_CNT_IN1)
37375 #define G_SOP_CNT_IN1(x) (((x) >> S_SOP_CNT_IN1) & M_SOP_CNT_IN1)
37376 
37377 #define S_EOP_CNT_IN1    0
37378 #define M_EOP_CNT_IN1    0xfU
37379 #define V_EOP_CNT_IN1(x) ((x) << S_EOP_CNT_IN1)
37380 #define G_EOP_CNT_IN1(x) (((x) >> S_EOP_CNT_IN1) & M_EOP_CNT_IN1)
37381 
37382 #define A_ULP_RX_DBG_CTL 0x191e0
37383 
37384 #define S_EN_DBG_H    17
37385 #define V_EN_DBG_H(x) ((x) << S_EN_DBG_H)
37386 #define F_EN_DBG_H    V_EN_DBG_H(1U)
37387 
37388 #define S_EN_DBG_L    16
37389 #define V_EN_DBG_L(x) ((x) << S_EN_DBG_L)
37390 #define F_EN_DBG_L    V_EN_DBG_L(1U)
37391 
37392 #define S_SEL_H    8
37393 #define M_SEL_H    0xffU
37394 #define V_SEL_H(x) ((x) << S_SEL_H)
37395 #define G_SEL_H(x) (((x) >> S_SEL_H) & M_SEL_H)
37396 
37397 #define S_SEL_L    0
37398 #define M_SEL_L    0xffU
37399 #define V_SEL_L(x) ((x) << S_SEL_L)
37400 #define G_SEL_L(x) (((x) >> S_SEL_L) & M_SEL_L)
37401 
37402 #define A_ULP_RX_DBG_DATAH 0x191e4
37403 #define A_ULP_RX_DBG_DATAL 0x191e8
37404 #define A_ULP_RX_LA_CHNL 0x19238
37405 
37406 #define S_CHNL_SEL    0
37407 #define V_CHNL_SEL(x) ((x) << S_CHNL_SEL)
37408 #define F_CHNL_SEL    V_CHNL_SEL(1U)
37409 
37410 #define A_ULP_RX_LA_CTL 0x1923c
37411 
37412 #define S_TRC_SEL    0
37413 #define V_TRC_SEL(x) ((x) << S_TRC_SEL)
37414 #define F_TRC_SEL    V_TRC_SEL(1U)
37415 
37416 #define A_ULP_RX_LA_RDPTR 0x19240
37417 
37418 #define S_RD_PTR    0
37419 #define M_RD_PTR    0x1ffU
37420 #define V_RD_PTR(x) ((x) << S_RD_PTR)
37421 #define G_RD_PTR(x) (((x) >> S_RD_PTR) & M_RD_PTR)
37422 
37423 #define A_ULP_RX_LA_RDDATA 0x19244
37424 #define A_ULP_RX_LA_WRPTR 0x19248
37425 
37426 #define S_WR_PTR    0
37427 #define M_WR_PTR    0x1ffU
37428 #define V_WR_PTR(x) ((x) << S_WR_PTR)
37429 #define G_WR_PTR(x) (((x) >> S_WR_PTR) & M_WR_PTR)
37430 
37431 #define A_ULP_RX_LA_RESERVED 0x1924c
37432 #define A_ULP_RX_CQE_GEN_EN 0x19250
37433 
37434 #define S_TERMIMATE_MSG    1
37435 #define V_TERMIMATE_MSG(x) ((x) << S_TERMIMATE_MSG)
37436 #define F_TERMIMATE_MSG    V_TERMIMATE_MSG(1U)
37437 
37438 #define S_TERMINATE_WITH_ERR    0
37439 #define V_TERMINATE_WITH_ERR(x) ((x) << S_TERMINATE_WITH_ERR)
37440 #define F_TERMINATE_WITH_ERR    V_TERMINATE_WITH_ERR(1U)
37441 
37442 #define A_ULP_RX_ATOMIC_OPCODES 0x19254
37443 
37444 #define S_ATOMIC_REQ_QNO    22
37445 #define M_ATOMIC_REQ_QNO    0x3U
37446 #define V_ATOMIC_REQ_QNO(x) ((x) << S_ATOMIC_REQ_QNO)
37447 #define G_ATOMIC_REQ_QNO(x) (((x) >> S_ATOMIC_REQ_QNO) & M_ATOMIC_REQ_QNO)
37448 
37449 #define S_ATOMIC_RSP_QNO    20
37450 #define M_ATOMIC_RSP_QNO    0x3U
37451 #define V_ATOMIC_RSP_QNO(x) ((x) << S_ATOMIC_RSP_QNO)
37452 #define G_ATOMIC_RSP_QNO(x) (((x) >> S_ATOMIC_RSP_QNO) & M_ATOMIC_RSP_QNO)
37453 
37454 #define S_IMMEDIATE_QNO    18
37455 #define M_IMMEDIATE_QNO    0x3U
37456 #define V_IMMEDIATE_QNO(x) ((x) << S_IMMEDIATE_QNO)
37457 #define G_IMMEDIATE_QNO(x) (((x) >> S_IMMEDIATE_QNO) & M_IMMEDIATE_QNO)
37458 
37459 #define S_IMMEDIATE_WITH_SE_QNO    16
37460 #define M_IMMEDIATE_WITH_SE_QNO    0x3U
37461 #define V_IMMEDIATE_WITH_SE_QNO(x) ((x) << S_IMMEDIATE_WITH_SE_QNO)
37462 #define G_IMMEDIATE_WITH_SE_QNO(x) (((x) >> S_IMMEDIATE_WITH_SE_QNO) & M_IMMEDIATE_WITH_SE_QNO)
37463 
37464 #define S_ATOMIC_WR_OPCODE    12
37465 #define M_ATOMIC_WR_OPCODE    0xfU
37466 #define V_ATOMIC_WR_OPCODE(x) ((x) << S_ATOMIC_WR_OPCODE)
37467 #define G_ATOMIC_WR_OPCODE(x) (((x) >> S_ATOMIC_WR_OPCODE) & M_ATOMIC_WR_OPCODE)
37468 
37469 #define S_ATOMIC_RD_OPCODE    8
37470 #define M_ATOMIC_RD_OPCODE    0xfU
37471 #define V_ATOMIC_RD_OPCODE(x) ((x) << S_ATOMIC_RD_OPCODE)
37472 #define G_ATOMIC_RD_OPCODE(x) (((x) >> S_ATOMIC_RD_OPCODE) & M_ATOMIC_RD_OPCODE)
37473 
37474 #define S_IMMEDIATE_OPCODE    4
37475 #define M_IMMEDIATE_OPCODE    0xfU
37476 #define V_IMMEDIATE_OPCODE(x) ((x) << S_IMMEDIATE_OPCODE)
37477 #define G_IMMEDIATE_OPCODE(x) (((x) >> S_IMMEDIATE_OPCODE) & M_IMMEDIATE_OPCODE)
37478 
37479 #define S_IMMEDIATE_WITH_SE_OPCODE    0
37480 #define M_IMMEDIATE_WITH_SE_OPCODE    0xfU
37481 #define V_IMMEDIATE_WITH_SE_OPCODE(x) ((x) << S_IMMEDIATE_WITH_SE_OPCODE)
37482 #define G_IMMEDIATE_WITH_SE_OPCODE(x) (((x) >> S_IMMEDIATE_WITH_SE_OPCODE) & M_IMMEDIATE_WITH_SE_OPCODE)
37483 
37484 #define A_ULP_RX_T10_CRC_ENDIAN_SWITCHING 0x19258
37485 
37486 #define S_EN_ORIG_DATA    0
37487 #define V_EN_ORIG_DATA(x) ((x) << S_EN_ORIG_DATA)
37488 #define F_EN_ORIG_DATA    V_EN_ORIG_DATA(1U)
37489 
37490 #define A_ULP_RX_MISC_FEATURE_ENABLE 0x1925c
37491 
37492 #define S_TERMINATE_STATUS_EN    4
37493 #define V_TERMINATE_STATUS_EN(x) ((x) << S_TERMINATE_STATUS_EN)
37494 #define F_TERMINATE_STATUS_EN    V_TERMINATE_STATUS_EN(1U)
37495 
37496 #define S_MULTIPLE_PREF_ENABLE    3
37497 #define V_MULTIPLE_PREF_ENABLE(x) ((x) << S_MULTIPLE_PREF_ENABLE)
37498 #define F_MULTIPLE_PREF_ENABLE    V_MULTIPLE_PREF_ENABLE(1U)
37499 
37500 #define S_UMUDP_PBL_PREF_ENABLE    2
37501 #define V_UMUDP_PBL_PREF_ENABLE(x) ((x) << S_UMUDP_PBL_PREF_ENABLE)
37502 #define F_UMUDP_PBL_PREF_ENABLE    V_UMUDP_PBL_PREF_ENABLE(1U)
37503 
37504 #define S_RDMA_PBL_PREF_EN    1
37505 #define V_RDMA_PBL_PREF_EN(x) ((x) << S_RDMA_PBL_PREF_EN)
37506 #define F_RDMA_PBL_PREF_EN    V_RDMA_PBL_PREF_EN(1U)
37507 
37508 #define S_SDC_CRC_PROT_EN    0
37509 #define V_SDC_CRC_PROT_EN(x) ((x) << S_SDC_CRC_PROT_EN)
37510 #define F_SDC_CRC_PROT_EN    V_SDC_CRC_PROT_EN(1U)
37511 
37512 #define S_ISCSI_DCRC_ERROR_CMP_EN    25
37513 #define V_ISCSI_DCRC_ERROR_CMP_EN(x) ((x) << S_ISCSI_DCRC_ERROR_CMP_EN)
37514 #define F_ISCSI_DCRC_ERROR_CMP_EN    V_ISCSI_DCRC_ERROR_CMP_EN(1U)
37515 
37516 #define S_ISCSITAGPI    24
37517 #define V_ISCSITAGPI(x) ((x) << S_ISCSITAGPI)
37518 #define F_ISCSITAGPI    V_ISCSITAGPI(1U)
37519 
37520 #define S_DDP_VERSION_1    22
37521 #define M_DDP_VERSION_1    0x3U
37522 #define V_DDP_VERSION_1(x) ((x) << S_DDP_VERSION_1)
37523 #define G_DDP_VERSION_1(x) (((x) >> S_DDP_VERSION_1) & M_DDP_VERSION_1)
37524 
37525 #define S_DDP_VERSION_0    20
37526 #define M_DDP_VERSION_0    0x3U
37527 #define V_DDP_VERSION_0(x) ((x) << S_DDP_VERSION_0)
37528 #define G_DDP_VERSION_0(x) (((x) >> S_DDP_VERSION_0) & M_DDP_VERSION_0)
37529 
37530 #define S_RDMA_VERSION_1    18
37531 #define M_RDMA_VERSION_1    0x3U
37532 #define V_RDMA_VERSION_1(x) ((x) << S_RDMA_VERSION_1)
37533 #define G_RDMA_VERSION_1(x) (((x) >> S_RDMA_VERSION_1) & M_RDMA_VERSION_1)
37534 
37535 #define S_RDMA_VERSION_0    16
37536 #define M_RDMA_VERSION_0    0x3U
37537 #define V_RDMA_VERSION_0(x) ((x) << S_RDMA_VERSION_0)
37538 #define G_RDMA_VERSION_0(x) (((x) >> S_RDMA_VERSION_0) & M_RDMA_VERSION_0)
37539 
37540 #define S_PBL_BOUND_CHECK_W_PGLEN    15
37541 #define V_PBL_BOUND_CHECK_W_PGLEN(x) ((x) << S_PBL_BOUND_CHECK_W_PGLEN)
37542 #define F_PBL_BOUND_CHECK_W_PGLEN    V_PBL_BOUND_CHECK_W_PGLEN(1U)
37543 
37544 #define S_ZBYTE_FIX_DISABLE    14
37545 #define V_ZBYTE_FIX_DISABLE(x) ((x) << S_ZBYTE_FIX_DISABLE)
37546 #define F_ZBYTE_FIX_DISABLE    V_ZBYTE_FIX_DISABLE(1U)
37547 
37548 #define S_T10_OFFSET_UPDATE_EN    13
37549 #define V_T10_OFFSET_UPDATE_EN(x) ((x) << S_T10_OFFSET_UPDATE_EN)
37550 #define F_T10_OFFSET_UPDATE_EN    V_T10_OFFSET_UPDATE_EN(1U)
37551 
37552 #define S_ULP_INSERT_PI    12
37553 #define V_ULP_INSERT_PI(x) ((x) << S_ULP_INSERT_PI)
37554 #define F_ULP_INSERT_PI    V_ULP_INSERT_PI(1U)
37555 
37556 #define S_PDU_DPI    11
37557 #define V_PDU_DPI(x) ((x) << S_PDU_DPI)
37558 #define F_PDU_DPI    V_PDU_DPI(1U)
37559 
37560 #define S_ISCSI_EFF_OFFSET_EN    10
37561 #define V_ISCSI_EFF_OFFSET_EN(x) ((x) << S_ISCSI_EFF_OFFSET_EN)
37562 #define F_ISCSI_EFF_OFFSET_EN    V_ISCSI_EFF_OFFSET_EN(1U)
37563 
37564 #define S_ISCSI_ALL_CMP_MODE    9
37565 #define V_ISCSI_ALL_CMP_MODE(x) ((x) << S_ISCSI_ALL_CMP_MODE)
37566 #define F_ISCSI_ALL_CMP_MODE    V_ISCSI_ALL_CMP_MODE(1U)
37567 
37568 #define S_ISCSI_ENABLE_HDR_CMD    8
37569 #define V_ISCSI_ENABLE_HDR_CMD(x) ((x) << S_ISCSI_ENABLE_HDR_CMD)
37570 #define F_ISCSI_ENABLE_HDR_CMD    V_ISCSI_ENABLE_HDR_CMD(1U)
37571 
37572 #define S_ISCSI_FORCE_CMP_MODE    7
37573 #define V_ISCSI_FORCE_CMP_MODE(x) ((x) << S_ISCSI_FORCE_CMP_MODE)
37574 #define F_ISCSI_FORCE_CMP_MODE    V_ISCSI_FORCE_CMP_MODE(1U)
37575 
37576 #define S_ISCSI_ENABLE_CMP_MODE    6
37577 #define V_ISCSI_ENABLE_CMP_MODE(x) ((x) << S_ISCSI_ENABLE_CMP_MODE)
37578 #define F_ISCSI_ENABLE_CMP_MODE    V_ISCSI_ENABLE_CMP_MODE(1U)
37579 
37580 #define S_PIO_RDMA_SEND_RQE    5
37581 #define V_PIO_RDMA_SEND_RQE(x) ((x) << S_PIO_RDMA_SEND_RQE)
37582 #define F_PIO_RDMA_SEND_RQE    V_PIO_RDMA_SEND_RQE(1U)
37583 
37584 #define A_ULP_RX_CH0_CGEN 0x19260
37585 
37586 #define S_BYPASS_CGEN    7
37587 #define V_BYPASS_CGEN(x) ((x) << S_BYPASS_CGEN)
37588 #define F_BYPASS_CGEN    V_BYPASS_CGEN(1U)
37589 
37590 #define S_TDDP_CGEN    6
37591 #define V_TDDP_CGEN(x) ((x) << S_TDDP_CGEN)
37592 #define F_TDDP_CGEN    V_TDDP_CGEN(1U)
37593 
37594 #define S_ISCSI_CGEN    5
37595 #define V_ISCSI_CGEN(x) ((x) << S_ISCSI_CGEN)
37596 #define F_ISCSI_CGEN    V_ISCSI_CGEN(1U)
37597 
37598 #define S_RDMA_CGEN    4
37599 #define V_RDMA_CGEN(x) ((x) << S_RDMA_CGEN)
37600 #define F_RDMA_CGEN    V_RDMA_CGEN(1U)
37601 
37602 #define S_CHANNEL_CGEN    3
37603 #define V_CHANNEL_CGEN(x) ((x) << S_CHANNEL_CGEN)
37604 #define F_CHANNEL_CGEN    V_CHANNEL_CGEN(1U)
37605 
37606 #define S_ALL_DATAPATH_CGEN    2
37607 #define V_ALL_DATAPATH_CGEN(x) ((x) << S_ALL_DATAPATH_CGEN)
37608 #define F_ALL_DATAPATH_CGEN    V_ALL_DATAPATH_CGEN(1U)
37609 
37610 #define S_T10DIFF_DATAPATH_CGEN    1
37611 #define V_T10DIFF_DATAPATH_CGEN(x) ((x) << S_T10DIFF_DATAPATH_CGEN)
37612 #define F_T10DIFF_DATAPATH_CGEN    V_T10DIFF_DATAPATH_CGEN(1U)
37613 
37614 #define S_RDMA_DATAPATH_CGEN    0
37615 #define V_RDMA_DATAPATH_CGEN(x) ((x) << S_RDMA_DATAPATH_CGEN)
37616 #define F_RDMA_DATAPATH_CGEN    V_RDMA_DATAPATH_CGEN(1U)
37617 
37618 #define A_ULP_RX_CH1_CGEN 0x19264
37619 #define A_ULP_RX_RFE_DISABLE 0x19268
37620 
37621 #define S_RQE_LIM_CHECK_RFE_DISABLE    0
37622 #define V_RQE_LIM_CHECK_RFE_DISABLE(x) ((x) << S_RQE_LIM_CHECK_RFE_DISABLE)
37623 #define F_RQE_LIM_CHECK_RFE_DISABLE    V_RQE_LIM_CHECK_RFE_DISABLE(1U)
37624 
37625 #define A_ULP_RX_INT_ENABLE_2 0x1926c
37626 
37627 #define S_ULPRX2MA_INTFPERR    8
37628 #define V_ULPRX2MA_INTFPERR(x) ((x) << S_ULPRX2MA_INTFPERR)
37629 #define F_ULPRX2MA_INTFPERR    V_ULPRX2MA_INTFPERR(1U)
37630 
37631 #define S_ALN_SDC_ERR_1    7
37632 #define V_ALN_SDC_ERR_1(x) ((x) << S_ALN_SDC_ERR_1)
37633 #define F_ALN_SDC_ERR_1    V_ALN_SDC_ERR_1(1U)
37634 
37635 #define S_ALN_SDC_ERR_0    6
37636 #define V_ALN_SDC_ERR_0(x) ((x) << S_ALN_SDC_ERR_0)
37637 #define F_ALN_SDC_ERR_0    V_ALN_SDC_ERR_0(1U)
37638 
37639 #define S_PF_UNTAGGED_TPT_1    5
37640 #define V_PF_UNTAGGED_TPT_1(x) ((x) << S_PF_UNTAGGED_TPT_1)
37641 #define F_PF_UNTAGGED_TPT_1    V_PF_UNTAGGED_TPT_1(1U)
37642 
37643 #define S_PF_UNTAGGED_TPT_0    4
37644 #define V_PF_UNTAGGED_TPT_0(x) ((x) << S_PF_UNTAGGED_TPT_0)
37645 #define F_PF_UNTAGGED_TPT_0    V_PF_UNTAGGED_TPT_0(1U)
37646 
37647 #define S_PF_PBL_1    3
37648 #define V_PF_PBL_1(x) ((x) << S_PF_PBL_1)
37649 #define F_PF_PBL_1    V_PF_PBL_1(1U)
37650 
37651 #define S_PF_PBL_0    2
37652 #define V_PF_PBL_0(x) ((x) << S_PF_PBL_0)
37653 #define F_PF_PBL_0    V_PF_PBL_0(1U)
37654 
37655 #define S_DDP_HINT_1    1
37656 #define V_DDP_HINT_1(x) ((x) << S_DDP_HINT_1)
37657 #define F_DDP_HINT_1    V_DDP_HINT_1(1U)
37658 
37659 #define S_DDP_HINT_0    0
37660 #define V_DDP_HINT_0(x) ((x) << S_DDP_HINT_0)
37661 #define F_DDP_HINT_0    V_DDP_HINT_0(1U)
37662 
37663 #define A_ULP_RX_INT_CAUSE_2 0x19270
37664 #define A_ULP_RX_PERR_ENABLE_2 0x19274
37665 
37666 #define S_ENABLE_ULPRX2MA_INTFPERR    8
37667 #define V_ENABLE_ULPRX2MA_INTFPERR(x) ((x) << S_ENABLE_ULPRX2MA_INTFPERR)
37668 #define F_ENABLE_ULPRX2MA_INTFPERR    V_ENABLE_ULPRX2MA_INTFPERR(1U)
37669 
37670 #define S_ENABLE_ALN_SDC_ERR_1    7
37671 #define V_ENABLE_ALN_SDC_ERR_1(x) ((x) << S_ENABLE_ALN_SDC_ERR_1)
37672 #define F_ENABLE_ALN_SDC_ERR_1    V_ENABLE_ALN_SDC_ERR_1(1U)
37673 
37674 #define S_ENABLE_ALN_SDC_ERR_0    6
37675 #define V_ENABLE_ALN_SDC_ERR_0(x) ((x) << S_ENABLE_ALN_SDC_ERR_0)
37676 #define F_ENABLE_ALN_SDC_ERR_0    V_ENABLE_ALN_SDC_ERR_0(1U)
37677 
37678 #define S_ENABLE_PF_UNTAGGED_TPT_1    5
37679 #define V_ENABLE_PF_UNTAGGED_TPT_1(x) ((x) << S_ENABLE_PF_UNTAGGED_TPT_1)
37680 #define F_ENABLE_PF_UNTAGGED_TPT_1    V_ENABLE_PF_UNTAGGED_TPT_1(1U)
37681 
37682 #define S_ENABLE_PF_UNTAGGED_TPT_0    4
37683 #define V_ENABLE_PF_UNTAGGED_TPT_0(x) ((x) << S_ENABLE_PF_UNTAGGED_TPT_0)
37684 #define F_ENABLE_PF_UNTAGGED_TPT_0    V_ENABLE_PF_UNTAGGED_TPT_0(1U)
37685 
37686 #define S_ENABLE_PF_PBL_1    3
37687 #define V_ENABLE_PF_PBL_1(x) ((x) << S_ENABLE_PF_PBL_1)
37688 #define F_ENABLE_PF_PBL_1    V_ENABLE_PF_PBL_1(1U)
37689 
37690 #define S_ENABLE_PF_PBL_0    2
37691 #define V_ENABLE_PF_PBL_0(x) ((x) << S_ENABLE_PF_PBL_0)
37692 #define F_ENABLE_PF_PBL_0    V_ENABLE_PF_PBL_0(1U)
37693 
37694 #define S_ENABLE_DDP_HINT_1    1
37695 #define V_ENABLE_DDP_HINT_1(x) ((x) << S_ENABLE_DDP_HINT_1)
37696 #define F_ENABLE_DDP_HINT_1    V_ENABLE_DDP_HINT_1(1U)
37697 
37698 #define S_ENABLE_DDP_HINT_0    0
37699 #define V_ENABLE_DDP_HINT_0(x) ((x) << S_ENABLE_DDP_HINT_0)
37700 #define F_ENABLE_DDP_HINT_0    V_ENABLE_DDP_HINT_0(1U)
37701 
37702 #define A_ULP_RX_RQE_PBL_MULTIPLE_OUTSTANDING_CNT 0x19278
37703 
37704 #define S_PIO_RQE_PBL_MULTIPLE_CNT    0
37705 #define M_PIO_RQE_PBL_MULTIPLE_CNT    0xfU
37706 #define V_PIO_RQE_PBL_MULTIPLE_CNT(x) ((x) << S_PIO_RQE_PBL_MULTIPLE_CNT)
37707 #define G_PIO_RQE_PBL_MULTIPLE_CNT(x) (((x) >> S_PIO_RQE_PBL_MULTIPLE_CNT) & M_PIO_RQE_PBL_MULTIPLE_CNT)
37708 
37709 #define A_ULP_RX_ATOMIC_LEN 0x1927c
37710 
37711 #define S_ATOMIC_RPL_LEN    16
37712 #define M_ATOMIC_RPL_LEN    0xffU
37713 #define V_ATOMIC_RPL_LEN(x) ((x) << S_ATOMIC_RPL_LEN)
37714 #define G_ATOMIC_RPL_LEN(x) (((x) >> S_ATOMIC_RPL_LEN) & M_ATOMIC_RPL_LEN)
37715 
37716 #define S_ATOMIC_REQ_LEN    8
37717 #define M_ATOMIC_REQ_LEN    0xffU
37718 #define V_ATOMIC_REQ_LEN(x) ((x) << S_ATOMIC_REQ_LEN)
37719 #define G_ATOMIC_REQ_LEN(x) (((x) >> S_ATOMIC_REQ_LEN) & M_ATOMIC_REQ_LEN)
37720 
37721 #define S_ATOMIC_IMMEDIATE_LEN    0
37722 #define M_ATOMIC_IMMEDIATE_LEN    0xffU
37723 #define V_ATOMIC_IMMEDIATE_LEN(x) ((x) << S_ATOMIC_IMMEDIATE_LEN)
37724 #define G_ATOMIC_IMMEDIATE_LEN(x) (((x) >> S_ATOMIC_IMMEDIATE_LEN) & M_ATOMIC_IMMEDIATE_LEN)
37725 
37726 #define A_ULP_RX_CGEN_GLOBAL 0x19280
37727 #define A_ULP_RX_CTX_SKIP_MA_REQ 0x19284
37728 
37729 #define S_CLEAR_CTX_ERR_CNT1    3
37730 #define V_CLEAR_CTX_ERR_CNT1(x) ((x) << S_CLEAR_CTX_ERR_CNT1)
37731 #define F_CLEAR_CTX_ERR_CNT1    V_CLEAR_CTX_ERR_CNT1(1U)
37732 
37733 #define S_CLEAR_CTX_ERR_CNT0    2
37734 #define V_CLEAR_CTX_ERR_CNT0(x) ((x) << S_CLEAR_CTX_ERR_CNT0)
37735 #define F_CLEAR_CTX_ERR_CNT0    V_CLEAR_CTX_ERR_CNT0(1U)
37736 
37737 #define S_SKIP_MA_REQ_EN1    1
37738 #define V_SKIP_MA_REQ_EN1(x) ((x) << S_SKIP_MA_REQ_EN1)
37739 #define F_SKIP_MA_REQ_EN1    V_SKIP_MA_REQ_EN1(1U)
37740 
37741 #define S_SKIP_MA_REQ_EN0    0
37742 #define V_SKIP_MA_REQ_EN0(x) ((x) << S_SKIP_MA_REQ_EN0)
37743 #define F_SKIP_MA_REQ_EN0    V_SKIP_MA_REQ_EN0(1U)
37744 
37745 #define A_ULP_RX_CHNL0_CTX_ERROR_COUNT_PER_TID 0x19288
37746 #define A_ULP_RX_CHNL1_CTX_ERROR_COUNT_PER_TID 0x1928c
37747 #define A_ULP_RX_MSN_CHECK_ENABLE 0x19290
37748 
37749 #define S_RD_OR_TERM_MSN_CHECK_ENABLE    2
37750 #define V_RD_OR_TERM_MSN_CHECK_ENABLE(x) ((x) << S_RD_OR_TERM_MSN_CHECK_ENABLE)
37751 #define F_RD_OR_TERM_MSN_CHECK_ENABLE    V_RD_OR_TERM_MSN_CHECK_ENABLE(1U)
37752 
37753 #define S_ATOMIC_OP_MSN_CHECK_ENABLE    1
37754 #define V_ATOMIC_OP_MSN_CHECK_ENABLE(x) ((x) << S_ATOMIC_OP_MSN_CHECK_ENABLE)
37755 #define F_ATOMIC_OP_MSN_CHECK_ENABLE    V_ATOMIC_OP_MSN_CHECK_ENABLE(1U)
37756 
37757 #define S_SEND_MSN_CHECK_ENABLE    0
37758 #define V_SEND_MSN_CHECK_ENABLE(x) ((x) << S_SEND_MSN_CHECK_ENABLE)
37759 #define F_SEND_MSN_CHECK_ENABLE    V_SEND_MSN_CHECK_ENABLE(1U)
37760 
37761 #define A_ULP_RX_TLS_PP_LLIMIT 0x192a4
37762 
37763 #define S_TLSPPLLIMIT    6
37764 #define M_TLSPPLLIMIT    0x3ffffffU
37765 #define V_TLSPPLLIMIT(x) ((x) << S_TLSPPLLIMIT)
37766 #define G_TLSPPLLIMIT(x) (((x) >> S_TLSPPLLIMIT) & M_TLSPPLLIMIT)
37767 
37768 #define A_ULP_RX_TLS_PP_ULIMIT 0x192a8
37769 
37770 #define S_TLSPPULIMIT    6
37771 #define M_TLSPPULIMIT    0x3ffffffU
37772 #define V_TLSPPULIMIT(x) ((x) << S_TLSPPULIMIT)
37773 #define G_TLSPPULIMIT(x) (((x) >> S_TLSPPULIMIT) & M_TLSPPULIMIT)
37774 
37775 #define A_ULP_RX_TLS_KEY_LLIMIT 0x192ac
37776 
37777 #define S_TLSKEYLLIMIT    8
37778 #define M_TLSKEYLLIMIT    0xffffffU
37779 #define V_TLSKEYLLIMIT(x) ((x) << S_TLSKEYLLIMIT)
37780 #define G_TLSKEYLLIMIT(x) (((x) >> S_TLSKEYLLIMIT) & M_TLSKEYLLIMIT)
37781 
37782 #define A_ULP_RX_TLS_KEY_ULIMIT 0x192b0
37783 
37784 #define S_TLSKEYULIMIT    8
37785 #define M_TLSKEYULIMIT    0xffffffU
37786 #define V_TLSKEYULIMIT(x) ((x) << S_TLSKEYULIMIT)
37787 #define G_TLSKEYULIMIT(x) (((x) >> S_TLSKEYULIMIT) & M_TLSKEYULIMIT)
37788 
37789 #define A_ULP_RX_TLS_CTL 0x192bc
37790 #define A_ULP_RX_TLS_IND_CMD 0x19348
37791 
37792 #define S_TLS_RX_REG_OFF_ADDR    0
37793 #define M_TLS_RX_REG_OFF_ADDR    0x3ffU
37794 #define V_TLS_RX_REG_OFF_ADDR(x) ((x) << S_TLS_RX_REG_OFF_ADDR)
37795 #define G_TLS_RX_REG_OFF_ADDR(x) (((x) >> S_TLS_RX_REG_OFF_ADDR) & M_TLS_RX_REG_OFF_ADDR)
37796 
37797 #define A_ULP_RX_TLS_IND_DATA 0x1934c
37798 
37799 /* registers for module SF */
37800 #define SF_BASE_ADDR 0x193f8
37801 
37802 #define A_SF_DATA 0x193f8
37803 #define A_SF_OP 0x193fc
37804 
37805 #define S_SF_LOCK    4
37806 #define V_SF_LOCK(x) ((x) << S_SF_LOCK)
37807 #define F_SF_LOCK    V_SF_LOCK(1U)
37808 
37809 #define S_CONT    3
37810 #define V_CONT(x) ((x) << S_CONT)
37811 #define F_CONT    V_CONT(1U)
37812 
37813 #define S_BYTECNT    1
37814 #define M_BYTECNT    0x3U
37815 #define V_BYTECNT(x) ((x) << S_BYTECNT)
37816 #define G_BYTECNT(x) (((x) >> S_BYTECNT) & M_BYTECNT)
37817 
37818 /* registers for module PL */
37819 #define PL_BASE_ADDR 0x19400
37820 
37821 #define A_PL_VF_WHOAMI 0x0
37822 
37823 #define S_PORTXMAP    24
37824 #define M_PORTXMAP    0x7U
37825 #define V_PORTXMAP(x) ((x) << S_PORTXMAP)
37826 #define G_PORTXMAP(x) (((x) >> S_PORTXMAP) & M_PORTXMAP)
37827 
37828 #define S_SOURCEBUS    16
37829 #define M_SOURCEBUS    0x3U
37830 #define V_SOURCEBUS(x) ((x) << S_SOURCEBUS)
37831 #define G_SOURCEBUS(x) (((x) >> S_SOURCEBUS) & M_SOURCEBUS)
37832 
37833 #define S_SOURCEPF    8
37834 #define M_SOURCEPF    0x7U
37835 #define V_SOURCEPF(x) ((x) << S_SOURCEPF)
37836 #define G_SOURCEPF(x) (((x) >> S_SOURCEPF) & M_SOURCEPF)
37837 
37838 #define S_ISVF    7
37839 #define V_ISVF(x) ((x) << S_ISVF)
37840 #define F_ISVF    V_ISVF(1U)
37841 
37842 #define S_VFID    0
37843 #define M_VFID    0x7fU
37844 #define V_VFID(x) ((x) << S_VFID)
37845 #define G_VFID(x) (((x) >> S_VFID) & M_VFID)
37846 
37847 #define S_T6_SOURCEPF    9
37848 #define M_T6_SOURCEPF    0x7U
37849 #define V_T6_SOURCEPF(x) ((x) << S_T6_SOURCEPF)
37850 #define G_T6_SOURCEPF(x) (((x) >> S_T6_SOURCEPF) & M_T6_SOURCEPF)
37851 
37852 #define S_T6_ISVF    8
37853 #define V_T6_ISVF(x) ((x) << S_T6_ISVF)
37854 #define F_T6_ISVF    V_T6_ISVF(1U)
37855 
37856 #define S_T6_VFID    0
37857 #define M_T6_VFID    0xffU
37858 #define V_T6_VFID(x) ((x) << S_T6_VFID)
37859 #define G_T6_VFID(x) (((x) >> S_T6_VFID) & M_T6_VFID)
37860 
37861 #define A_PL_VF_REV 0x4
37862 
37863 #define S_CHIPID    4
37864 #define M_CHIPID    0xfU
37865 #define V_CHIPID(x) ((x) << S_CHIPID)
37866 #define G_CHIPID(x) (((x) >> S_CHIPID) & M_CHIPID)
37867 
37868 #define A_PL_VF_REVISION 0x8
37869 #define A_PL_PF_INT_CAUSE 0x3c0
37870 
37871 #define S_PFSW    3
37872 #define V_PFSW(x) ((x) << S_PFSW)
37873 #define F_PFSW    V_PFSW(1U)
37874 
37875 #define S_PFSGE    2
37876 #define V_PFSGE(x) ((x) << S_PFSGE)
37877 #define F_PFSGE    V_PFSGE(1U)
37878 
37879 #define S_PFCIM    1
37880 #define V_PFCIM(x) ((x) << S_PFCIM)
37881 #define F_PFCIM    V_PFCIM(1U)
37882 
37883 #define S_PFMPS    0
37884 #define V_PFMPS(x) ((x) << S_PFMPS)
37885 #define F_PFMPS    V_PFMPS(1U)
37886 
37887 #define A_PL_PF_INT_ENABLE 0x3c4
37888 #define A_PL_PF_CTL 0x3c8
37889 
37890 #define S_SWINT    0
37891 #define V_SWINT(x) ((x) << S_SWINT)
37892 #define F_SWINT    V_SWINT(1U)
37893 
37894 #define A_PL_WHOAMI 0x19400
37895 
37896 #define S_T6_SOURCEPF    9
37897 #define M_T6_SOURCEPF    0x7U
37898 #define V_T6_SOURCEPF(x) ((x) << S_T6_SOURCEPF)
37899 #define G_T6_SOURCEPF(x) (((x) >> S_T6_SOURCEPF) & M_T6_SOURCEPF)
37900 
37901 #define S_T6_ISVF    8
37902 #define V_T6_ISVF(x) ((x) << S_T6_ISVF)
37903 #define F_T6_ISVF    V_T6_ISVF(1U)
37904 
37905 #define S_T6_VFID    0
37906 #define M_T6_VFID    0xffU
37907 #define V_T6_VFID(x) ((x) << S_T6_VFID)
37908 #define G_T6_VFID(x) (((x) >> S_T6_VFID) & M_T6_VFID)
37909 
37910 #define A_PL_PERR_CAUSE 0x19404
37911 
37912 #define S_UART    28
37913 #define V_UART(x) ((x) << S_UART)
37914 #define F_UART    V_UART(1U)
37915 
37916 #define S_ULP_TX    27
37917 #define V_ULP_TX(x) ((x) << S_ULP_TX)
37918 #define F_ULP_TX    V_ULP_TX(1U)
37919 
37920 #define S_SGE    26
37921 #define V_SGE(x) ((x) << S_SGE)
37922 #define F_SGE    V_SGE(1U)
37923 
37924 #define S_HMA    25
37925 #define V_HMA(x) ((x) << S_HMA)
37926 #define F_HMA    V_HMA(1U)
37927 
37928 #define S_CPL_SWITCH    24
37929 #define V_CPL_SWITCH(x) ((x) << S_CPL_SWITCH)
37930 #define F_CPL_SWITCH    V_CPL_SWITCH(1U)
37931 
37932 #define S_ULP_RX    23
37933 #define V_ULP_RX(x) ((x) << S_ULP_RX)
37934 #define F_ULP_RX    V_ULP_RX(1U)
37935 
37936 #define S_PM_RX    22
37937 #define V_PM_RX(x) ((x) << S_PM_RX)
37938 #define F_PM_RX    V_PM_RX(1U)
37939 
37940 #define S_PM_TX    21
37941 #define V_PM_TX(x) ((x) << S_PM_TX)
37942 #define F_PM_TX    V_PM_TX(1U)
37943 
37944 #define S_MA    20
37945 #define V_MA(x) ((x) << S_MA)
37946 #define F_MA    V_MA(1U)
37947 
37948 #define S_TP    19
37949 #define V_TP(x) ((x) << S_TP)
37950 #define F_TP    V_TP(1U)
37951 
37952 #define S_LE    18
37953 #define V_LE(x) ((x) << S_LE)
37954 #define F_LE    V_LE(1U)
37955 
37956 #define S_EDC1    17
37957 #define V_EDC1(x) ((x) << S_EDC1)
37958 #define F_EDC1    V_EDC1(1U)
37959 
37960 #define S_EDC0    16
37961 #define V_EDC0(x) ((x) << S_EDC0)
37962 #define F_EDC0    V_EDC0(1U)
37963 
37964 #define S_MC    15
37965 #define V_MC(x) ((x) << S_MC)
37966 #define F_MC    V_MC(1U)
37967 
37968 #define S_PCIE    14
37969 #define V_PCIE(x) ((x) << S_PCIE)
37970 #define F_PCIE    V_PCIE(1U)
37971 
37972 #define S_PMU    13
37973 #define V_PMU(x) ((x) << S_PMU)
37974 #define F_PMU    V_PMU(1U)
37975 
37976 #define S_XGMAC_KR1    12
37977 #define V_XGMAC_KR1(x) ((x) << S_XGMAC_KR1)
37978 #define F_XGMAC_KR1    V_XGMAC_KR1(1U)
37979 
37980 #define S_XGMAC_KR0    11
37981 #define V_XGMAC_KR0(x) ((x) << S_XGMAC_KR0)
37982 #define F_XGMAC_KR0    V_XGMAC_KR0(1U)
37983 
37984 #define S_XGMAC1    10
37985 #define V_XGMAC1(x) ((x) << S_XGMAC1)
37986 #define F_XGMAC1    V_XGMAC1(1U)
37987 
37988 #define S_XGMAC0    9
37989 #define V_XGMAC0(x) ((x) << S_XGMAC0)
37990 #define F_XGMAC0    V_XGMAC0(1U)
37991 
37992 #define S_SMB    8
37993 #define V_SMB(x) ((x) << S_SMB)
37994 #define F_SMB    V_SMB(1U)
37995 
37996 #define S_SF    7
37997 #define V_SF(x) ((x) << S_SF)
37998 #define F_SF    V_SF(1U)
37999 
38000 #define S_PL    6
38001 #define V_PL(x) ((x) << S_PL)
38002 #define F_PL    V_PL(1U)
38003 
38004 #define S_NCSI    5
38005 #define V_NCSI(x) ((x) << S_NCSI)
38006 #define F_NCSI    V_NCSI(1U)
38007 
38008 #define S_MPS    4
38009 #define V_MPS(x) ((x) << S_MPS)
38010 #define F_MPS    V_MPS(1U)
38011 
38012 #define S_MI    3
38013 #define V_MI(x) ((x) << S_MI)
38014 #define F_MI    V_MI(1U)
38015 
38016 #define S_DBG    2
38017 #define V_DBG(x) ((x) << S_DBG)
38018 #define F_DBG    V_DBG(1U)
38019 
38020 #define S_I2CM    1
38021 #define V_I2CM(x) ((x) << S_I2CM)
38022 #define F_I2CM    V_I2CM(1U)
38023 
38024 #define S_CIM    0
38025 #define V_CIM(x) ((x) << S_CIM)
38026 #define F_CIM    V_CIM(1U)
38027 
38028 #define S_MC1    31
38029 #define V_MC1(x) ((x) << S_MC1)
38030 #define F_MC1    V_MC1(1U)
38031 
38032 #define S_MC0    15
38033 #define V_MC0(x) ((x) << S_MC0)
38034 #define F_MC0    V_MC0(1U)
38035 
38036 #define S_ANYMAC    9
38037 #define V_ANYMAC(x) ((x) << S_ANYMAC)
38038 #define F_ANYMAC    V_ANYMAC(1U)
38039 
38040 #define A_PL_PERR_ENABLE 0x19408
38041 #define A_PL_INT_CAUSE 0x1940c
38042 
38043 #define S_FLR    30
38044 #define V_FLR(x) ((x) << S_FLR)
38045 #define F_FLR    V_FLR(1U)
38046 
38047 #define S_SW_CIM    29
38048 #define V_SW_CIM(x) ((x) << S_SW_CIM)
38049 #define F_SW_CIM    V_SW_CIM(1U)
38050 
38051 #define S_MAC3    12
38052 #define V_MAC3(x) ((x) << S_MAC3)
38053 #define F_MAC3    V_MAC3(1U)
38054 
38055 #define S_MAC2    11
38056 #define V_MAC2(x) ((x) << S_MAC2)
38057 #define F_MAC2    V_MAC2(1U)
38058 
38059 #define S_MAC1    10
38060 #define V_MAC1(x) ((x) << S_MAC1)
38061 #define F_MAC1    V_MAC1(1U)
38062 
38063 #define S_MAC0    9
38064 #define V_MAC0(x) ((x) << S_MAC0)
38065 #define F_MAC0    V_MAC0(1U)
38066 
38067 #define A_PL_INT_ENABLE 0x19410
38068 #define A_PL_INT_MAP0 0x19414
38069 
38070 #define S_MAPNCSI    16
38071 #define M_MAPNCSI    0x1ffU
38072 #define V_MAPNCSI(x) ((x) << S_MAPNCSI)
38073 #define G_MAPNCSI(x) (((x) >> S_MAPNCSI) & M_MAPNCSI)
38074 
38075 #define S_MAPDEFAULT    0
38076 #define M_MAPDEFAULT    0x1ffU
38077 #define V_MAPDEFAULT(x) ((x) << S_MAPDEFAULT)
38078 #define G_MAPDEFAULT(x) (((x) >> S_MAPDEFAULT) & M_MAPDEFAULT)
38079 
38080 #define A_PL_INT_MAP1 0x19418
38081 
38082 #define S_MAPXGMAC1    16
38083 #define M_MAPXGMAC1    0x1ffU
38084 #define V_MAPXGMAC1(x) ((x) << S_MAPXGMAC1)
38085 #define G_MAPXGMAC1(x) (((x) >> S_MAPXGMAC1) & M_MAPXGMAC1)
38086 
38087 #define S_MAPXGMAC0    0
38088 #define M_MAPXGMAC0    0x1ffU
38089 #define V_MAPXGMAC0(x) ((x) << S_MAPXGMAC0)
38090 #define G_MAPXGMAC0(x) (((x) >> S_MAPXGMAC0) & M_MAPXGMAC0)
38091 
38092 #define S_MAPMAC1    16
38093 #define M_MAPMAC1    0x1ffU
38094 #define V_MAPMAC1(x) ((x) << S_MAPMAC1)
38095 #define G_MAPMAC1(x) (((x) >> S_MAPMAC1) & M_MAPMAC1)
38096 
38097 #define S_MAPMAC0    0
38098 #define M_MAPMAC0    0x1ffU
38099 #define V_MAPMAC0(x) ((x) << S_MAPMAC0)
38100 #define G_MAPMAC0(x) (((x) >> S_MAPMAC0) & M_MAPMAC0)
38101 
38102 #define A_PL_INT_MAP2 0x1941c
38103 
38104 #define S_MAPXGMAC_KR1    16
38105 #define M_MAPXGMAC_KR1    0x1ffU
38106 #define V_MAPXGMAC_KR1(x) ((x) << S_MAPXGMAC_KR1)
38107 #define G_MAPXGMAC_KR1(x) (((x) >> S_MAPXGMAC_KR1) & M_MAPXGMAC_KR1)
38108 
38109 #define S_MAPXGMAC_KR0    0
38110 #define M_MAPXGMAC_KR0    0x1ffU
38111 #define V_MAPXGMAC_KR0(x) ((x) << S_MAPXGMAC_KR0)
38112 #define G_MAPXGMAC_KR0(x) (((x) >> S_MAPXGMAC_KR0) & M_MAPXGMAC_KR0)
38113 
38114 #define S_MAPMAC3    16
38115 #define M_MAPMAC3    0x1ffU
38116 #define V_MAPMAC3(x) ((x) << S_MAPMAC3)
38117 #define G_MAPMAC3(x) (((x) >> S_MAPMAC3) & M_MAPMAC3)
38118 
38119 #define S_MAPMAC2    0
38120 #define M_MAPMAC2    0x1ffU
38121 #define V_MAPMAC2(x) ((x) << S_MAPMAC2)
38122 #define G_MAPMAC2(x) (((x) >> S_MAPMAC2) & M_MAPMAC2)
38123 
38124 #define A_PL_INT_MAP3 0x19420
38125 
38126 #define S_MAPMI    16
38127 #define M_MAPMI    0x1ffU
38128 #define V_MAPMI(x) ((x) << S_MAPMI)
38129 #define G_MAPMI(x) (((x) >> S_MAPMI) & M_MAPMI)
38130 
38131 #define S_MAPSMB    0
38132 #define M_MAPSMB    0x1ffU
38133 #define V_MAPSMB(x) ((x) << S_MAPSMB)
38134 #define G_MAPSMB(x) (((x) >> S_MAPSMB) & M_MAPSMB)
38135 
38136 #define A_PL_INT_MAP4 0x19424
38137 
38138 #define S_MAPDBG    16
38139 #define M_MAPDBG    0x1ffU
38140 #define V_MAPDBG(x) ((x) << S_MAPDBG)
38141 #define G_MAPDBG(x) (((x) >> S_MAPDBG) & M_MAPDBG)
38142 
38143 #define S_MAPI2CM    0
38144 #define M_MAPI2CM    0x1ffU
38145 #define V_MAPI2CM(x) ((x) << S_MAPI2CM)
38146 #define G_MAPI2CM(x) (((x) >> S_MAPI2CM) & M_MAPI2CM)
38147 
38148 #define A_PL_RST 0x19428
38149 
38150 #define S_FATALPERREN    3
38151 #define V_FATALPERREN(x) ((x) << S_FATALPERREN)
38152 #define F_FATALPERREN    V_FATALPERREN(1U)
38153 
38154 #define S_SWINTCIM    2
38155 #define V_SWINTCIM(x) ((x) << S_SWINTCIM)
38156 #define F_SWINTCIM    V_SWINTCIM(1U)
38157 
38158 #define S_PIORST    1
38159 #define V_PIORST(x) ((x) << S_PIORST)
38160 #define F_PIORST    V_PIORST(1U)
38161 
38162 #define S_PIORSTMODE    0
38163 #define V_PIORSTMODE(x) ((x) << S_PIORSTMODE)
38164 #define F_PIORSTMODE    V_PIORSTMODE(1U)
38165 
38166 #define S_AUTOPCIEPAUSE    4
38167 #define V_AUTOPCIEPAUSE(x) ((x) << S_AUTOPCIEPAUSE)
38168 #define F_AUTOPCIEPAUSE    V_AUTOPCIEPAUSE(1U)
38169 
38170 #define A_PL_PL_PERR_INJECT 0x1942c
38171 
38172 #define S_PL_MEMSEL    1
38173 #define V_PL_MEMSEL(x) ((x) << S_PL_MEMSEL)
38174 #define F_PL_MEMSEL    V_PL_MEMSEL(1U)
38175 
38176 #define A_PL_PL_INT_CAUSE 0x19430
38177 
38178 #define S_PF_ENABLEERR    5
38179 #define V_PF_ENABLEERR(x) ((x) << S_PF_ENABLEERR)
38180 #define F_PF_ENABLEERR    V_PF_ENABLEERR(1U)
38181 
38182 #define S_FATALPERR    4
38183 #define V_FATALPERR(x) ((x) << S_FATALPERR)
38184 #define F_FATALPERR    V_FATALPERR(1U)
38185 
38186 #define S_INVALIDACCESS    3
38187 #define V_INVALIDACCESS(x) ((x) << S_INVALIDACCESS)
38188 #define F_INVALIDACCESS    V_INVALIDACCESS(1U)
38189 
38190 #define S_TIMEOUT    2
38191 #define V_TIMEOUT(x) ((x) << S_TIMEOUT)
38192 #define F_TIMEOUT    V_TIMEOUT(1U)
38193 
38194 #define S_PLERR    1
38195 #define V_PLERR(x) ((x) << S_PLERR)
38196 #define F_PLERR    V_PLERR(1U)
38197 
38198 #define S_PERRVFID    0
38199 #define V_PERRVFID(x) ((x) << S_PERRVFID)
38200 #define F_PERRVFID    V_PERRVFID(1U)
38201 
38202 #define S_PL_BUSPERR    6
38203 #define V_PL_BUSPERR(x) ((x) << S_PL_BUSPERR)
38204 #define F_PL_BUSPERR    V_PL_BUSPERR(1U)
38205 
38206 #define A_PL_PL_INT_ENABLE 0x19434
38207 #define A_PL_PL_PERR_ENABLE 0x19438
38208 #define A_PL_REV 0x1943c
38209 
38210 #define S_REV    0
38211 #define M_REV    0xfU
38212 #define V_REV(x) ((x) << S_REV)
38213 #define G_REV(x) (((x) >> S_REV) & M_REV)
38214 
38215 #define A_PL_PCIE_LINK 0x19440
38216 
38217 #define S_LN0_AESTAT    26
38218 #define M_LN0_AESTAT    0x7U
38219 #define V_LN0_AESTAT(x) ((x) << S_LN0_AESTAT)
38220 #define G_LN0_AESTAT(x) (((x) >> S_LN0_AESTAT) & M_LN0_AESTAT)
38221 
38222 #define S_LN0_AECMD    23
38223 #define M_LN0_AECMD    0x7U
38224 #define V_LN0_AECMD(x) ((x) << S_LN0_AECMD)
38225 #define G_LN0_AECMD(x) (((x) >> S_LN0_AECMD) & M_LN0_AECMD)
38226 
38227 #define S_T5_STATECFGINITF    16
38228 #define M_T5_STATECFGINITF    0x7fU
38229 #define V_T5_STATECFGINITF(x) ((x) << S_T5_STATECFGINITF)
38230 #define G_T5_STATECFGINITF(x) (((x) >> S_T5_STATECFGINITF) & M_T5_STATECFGINITF)
38231 
38232 #define S_T5_STATECFGINIT    12
38233 #define M_T5_STATECFGINIT    0xfU
38234 #define V_T5_STATECFGINIT(x) ((x) << S_T5_STATECFGINIT)
38235 #define G_T5_STATECFGINIT(x) (((x) >> S_T5_STATECFGINIT) & M_T5_STATECFGINIT)
38236 
38237 #define S_PCIE_SPEED    8
38238 #define M_PCIE_SPEED    0x3U
38239 #define V_PCIE_SPEED(x) ((x) << S_PCIE_SPEED)
38240 #define G_PCIE_SPEED(x) (((x) >> S_PCIE_SPEED) & M_PCIE_SPEED)
38241 
38242 #define S_T5_PERSTTIMEOUT    7
38243 #define V_T5_PERSTTIMEOUT(x) ((x) << S_T5_PERSTTIMEOUT)
38244 #define F_T5_PERSTTIMEOUT    V_T5_PERSTTIMEOUT(1U)
38245 
38246 #define S_T5_LTSSMENABLE    6
38247 #define V_T5_LTSSMENABLE(x) ((x) << S_T5_LTSSMENABLE)
38248 #define F_T5_LTSSMENABLE    V_T5_LTSSMENABLE(1U)
38249 
38250 #define S_LTSSM    0
38251 #define M_LTSSM    0x3fU
38252 #define V_LTSSM(x) ((x) << S_LTSSM)
38253 #define G_LTSSM(x) (((x) >> S_LTSSM) & M_LTSSM)
38254 
38255 #define S_T6_LN0_AESTAT    27
38256 #define M_T6_LN0_AESTAT    0x7U
38257 #define V_T6_LN0_AESTAT(x) ((x) << S_T6_LN0_AESTAT)
38258 #define G_T6_LN0_AESTAT(x) (((x) >> S_T6_LN0_AESTAT) & M_T6_LN0_AESTAT)
38259 
38260 #define S_T6_LN0_AECMD    24
38261 #define M_T6_LN0_AECMD    0x7U
38262 #define V_T6_LN0_AECMD(x) ((x) << S_T6_LN0_AECMD)
38263 #define G_T6_LN0_AECMD(x) (((x) >> S_T6_LN0_AECMD) & M_T6_LN0_AECMD)
38264 
38265 #define S_T6_STATECFGINITF    16
38266 #define M_T6_STATECFGINITF    0xffU
38267 #define V_T6_STATECFGINITF(x) ((x) << S_T6_STATECFGINITF)
38268 #define G_T6_STATECFGINITF(x) (((x) >> S_T6_STATECFGINITF) & M_T6_STATECFGINITF)
38269 
38270 #define S_T6_STATECFGINIT    12
38271 #define M_T6_STATECFGINIT    0xfU
38272 #define V_T6_STATECFGINIT(x) ((x) << S_T6_STATECFGINIT)
38273 #define G_T6_STATECFGINIT(x) (((x) >> S_T6_STATECFGINIT) & M_T6_STATECFGINIT)
38274 
38275 #define S_PHY_STATUS    10
38276 #define V_PHY_STATUS(x) ((x) << S_PHY_STATUS)
38277 #define F_PHY_STATUS    V_PHY_STATUS(1U)
38278 
38279 #define S_SPEED_PL    8
38280 #define M_SPEED_PL    0x3U
38281 #define V_SPEED_PL(x) ((x) << S_SPEED_PL)
38282 #define G_SPEED_PL(x) (((x) >> S_SPEED_PL) & M_SPEED_PL)
38283 
38284 #define S_PERSTTIMEOUT_PL    7
38285 #define V_PERSTTIMEOUT_PL(x) ((x) << S_PERSTTIMEOUT_PL)
38286 #define F_PERSTTIMEOUT_PL    V_PERSTTIMEOUT_PL(1U)
38287 
38288 #define S_T6_LTSSMENABLE    6
38289 #define V_T6_LTSSMENABLE(x) ((x) << S_T6_LTSSMENABLE)
38290 #define F_T6_LTSSMENABLE    V_T6_LTSSMENABLE(1U)
38291 
38292 #define A_PL_PCIE_CTL_STAT 0x19444
38293 
38294 #define S_PCIE_STATUS    16
38295 #define M_PCIE_STATUS    0xffffU
38296 #define V_PCIE_STATUS(x) ((x) << S_PCIE_STATUS)
38297 #define G_PCIE_STATUS(x) (((x) >> S_PCIE_STATUS) & M_PCIE_STATUS)
38298 
38299 #define S_PCIE_CONTROL    0
38300 #define M_PCIE_CONTROL    0xffffU
38301 #define V_PCIE_CONTROL(x) ((x) << S_PCIE_CONTROL)
38302 #define G_PCIE_CONTROL(x) (((x) >> S_PCIE_CONTROL) & M_PCIE_CONTROL)
38303 
38304 #define A_PL_SEMAPHORE_CTL 0x1944c
38305 
38306 #define S_LOCKSTATUS    16
38307 #define M_LOCKSTATUS    0xffU
38308 #define V_LOCKSTATUS(x) ((x) << S_LOCKSTATUS)
38309 #define G_LOCKSTATUS(x) (((x) >> S_LOCKSTATUS) & M_LOCKSTATUS)
38310 
38311 #define S_OWNEROVERRIDE    8
38312 #define V_OWNEROVERRIDE(x) ((x) << S_OWNEROVERRIDE)
38313 #define F_OWNEROVERRIDE    V_OWNEROVERRIDE(1U)
38314 
38315 #define S_ENABLEPF    0
38316 #define M_ENABLEPF    0xffU
38317 #define V_ENABLEPF(x) ((x) << S_ENABLEPF)
38318 #define G_ENABLEPF(x) (((x) >> S_ENABLEPF) & M_ENABLEPF)
38319 
38320 #define A_PL_SEMAPHORE_LOCK 0x19450
38321 
38322 #define S_SEMLOCK    31
38323 #define V_SEMLOCK(x) ((x) << S_SEMLOCK)
38324 #define F_SEMLOCK    V_SEMLOCK(1U)
38325 
38326 #define S_SEMSRCBUS    3
38327 #define M_SEMSRCBUS    0x3U
38328 #define V_SEMSRCBUS(x) ((x) << S_SEMSRCBUS)
38329 #define G_SEMSRCBUS(x) (((x) >> S_SEMSRCBUS) & M_SEMSRCBUS)
38330 
38331 #define S_SEMSRCPF    0
38332 #define M_SEMSRCPF    0x7U
38333 #define V_SEMSRCPF(x) ((x) << S_SEMSRCPF)
38334 #define G_SEMSRCPF(x) (((x) >> S_SEMSRCPF) & M_SEMSRCPF)
38335 
38336 #define A_PL_PF_ENABLE 0x19470
38337 
38338 #define S_PF_ENABLE    0
38339 #define M_PF_ENABLE    0xffU
38340 #define V_PF_ENABLE(x) ((x) << S_PF_ENABLE)
38341 #define G_PF_ENABLE(x) (((x) >> S_PF_ENABLE) & M_PF_ENABLE)
38342 
38343 #define A_PL_PORTX_MAP 0x19474
38344 
38345 #define S_MAP7    28
38346 #define M_MAP7    0x7U
38347 #define V_MAP7(x) ((x) << S_MAP7)
38348 #define G_MAP7(x) (((x) >> S_MAP7) & M_MAP7)
38349 
38350 #define S_MAP6    24
38351 #define M_MAP6    0x7U
38352 #define V_MAP6(x) ((x) << S_MAP6)
38353 #define G_MAP6(x) (((x) >> S_MAP6) & M_MAP6)
38354 
38355 #define S_MAP5    20
38356 #define M_MAP5    0x7U
38357 #define V_MAP5(x) ((x) << S_MAP5)
38358 #define G_MAP5(x) (((x) >> S_MAP5) & M_MAP5)
38359 
38360 #define S_MAP4    16
38361 #define M_MAP4    0x7U
38362 #define V_MAP4(x) ((x) << S_MAP4)
38363 #define G_MAP4(x) (((x) >> S_MAP4) & M_MAP4)
38364 
38365 #define S_MAP3    12
38366 #define M_MAP3    0x7U
38367 #define V_MAP3(x) ((x) << S_MAP3)
38368 #define G_MAP3(x) (((x) >> S_MAP3) & M_MAP3)
38369 
38370 #define S_MAP2    8
38371 #define M_MAP2    0x7U
38372 #define V_MAP2(x) ((x) << S_MAP2)
38373 #define G_MAP2(x) (((x) >> S_MAP2) & M_MAP2)
38374 
38375 #define S_MAP1    4
38376 #define M_MAP1    0x7U
38377 #define V_MAP1(x) ((x) << S_MAP1)
38378 #define G_MAP1(x) (((x) >> S_MAP1) & M_MAP1)
38379 
38380 #define S_MAP0    0
38381 #define M_MAP0    0x7U
38382 #define V_MAP0(x) ((x) << S_MAP0)
38383 #define G_MAP0(x) (((x) >> S_MAP0) & M_MAP0)
38384 
38385 #define A_PL_VF_SLICE_L 0x19490
38386 
38387 #define S_LIMITADDR    16
38388 #define M_LIMITADDR    0x3ffU
38389 #define V_LIMITADDR(x) ((x) << S_LIMITADDR)
38390 #define G_LIMITADDR(x) (((x) >> S_LIMITADDR) & M_LIMITADDR)
38391 
38392 #define S_SLICEBASEADDR    0
38393 #define M_SLICEBASEADDR    0x3ffU
38394 #define V_SLICEBASEADDR(x) ((x) << S_SLICEBASEADDR)
38395 #define G_SLICEBASEADDR(x) (((x) >> S_SLICEBASEADDR) & M_SLICEBASEADDR)
38396 
38397 #define A_PL_VF_SLICE_H 0x19494
38398 
38399 #define S_MODINDX    16
38400 #define M_MODINDX    0x7U
38401 #define V_MODINDX(x) ((x) << S_MODINDX)
38402 #define G_MODINDX(x) (((x) >> S_MODINDX) & M_MODINDX)
38403 
38404 #define S_MODOFFSET    0
38405 #define M_MODOFFSET    0x3ffU
38406 #define V_MODOFFSET(x) ((x) << S_MODOFFSET)
38407 #define G_MODOFFSET(x) (((x) >> S_MODOFFSET) & M_MODOFFSET)
38408 
38409 #define A_PL_FLR_VF_STATUS 0x194d0
38410 #define A_PL_FLR_PF_STATUS 0x194e0
38411 
38412 #define S_FLR_PF    0
38413 #define M_FLR_PF    0xffU
38414 #define V_FLR_PF(x) ((x) << S_FLR_PF)
38415 #define G_FLR_PF(x) (((x) >> S_FLR_PF) & M_FLR_PF)
38416 
38417 #define A_PL_TIMEOUT_CTL 0x194f0
38418 
38419 #define S_PL_TIMEOUT    0
38420 #define M_PL_TIMEOUT    0xffffU
38421 #define V_PL_TIMEOUT(x) ((x) << S_PL_TIMEOUT)
38422 #define G_PL_TIMEOUT(x) (((x) >> S_PL_TIMEOUT) & M_PL_TIMEOUT)
38423 
38424 #define S_PERRCAPTURE    16
38425 #define V_PERRCAPTURE(x) ((x) << S_PERRCAPTURE)
38426 #define F_PERRCAPTURE    V_PERRCAPTURE(1U)
38427 
38428 #define A_PL_TIMEOUT_STATUS0 0x194f4
38429 
38430 #define S_PL_TOADDR    2
38431 #define M_PL_TOADDR    0xfffffffU
38432 #define V_PL_TOADDR(x) ((x) << S_PL_TOADDR)
38433 #define G_PL_TOADDR(x) (((x) >> S_PL_TOADDR) & M_PL_TOADDR)
38434 
38435 #define A_PL_TIMEOUT_STATUS1 0x194f8
38436 
38437 #define S_PL_TOVALID    31
38438 #define V_PL_TOVALID(x) ((x) << S_PL_TOVALID)
38439 #define F_PL_TOVALID    V_PL_TOVALID(1U)
38440 
38441 #define S_WRITE    22
38442 #define V_WRITE(x) ((x) << S_WRITE)
38443 #define F_WRITE    V_WRITE(1U)
38444 
38445 #define S_PL_TOBUS    20
38446 #define M_PL_TOBUS    0x3U
38447 #define V_PL_TOBUS(x) ((x) << S_PL_TOBUS)
38448 #define G_PL_TOBUS(x) (((x) >> S_PL_TOBUS) & M_PL_TOBUS)
38449 
38450 #define S_RGN    19
38451 #define V_RGN(x) ((x) << S_RGN)
38452 #define F_RGN    V_RGN(1U)
38453 
38454 #define S_PL_TOPF    16
38455 #define M_PL_TOPF    0x7U
38456 #define V_PL_TOPF(x) ((x) << S_PL_TOPF)
38457 #define G_PL_TOPF(x) (((x) >> S_PL_TOPF) & M_PL_TOPF)
38458 
38459 #define S_PL_TORID    0
38460 #define M_PL_TORID    0xffffU
38461 #define V_PL_TORID(x) ((x) << S_PL_TORID)
38462 #define G_PL_TORID(x) (((x) >> S_PL_TORID) & M_PL_TORID)
38463 
38464 #define S_VALIDPERR    30
38465 #define V_VALIDPERR(x) ((x) << S_VALIDPERR)
38466 #define F_VALIDPERR    V_VALIDPERR(1U)
38467 
38468 #define S_PL_TOVFID    0
38469 #define M_PL_TOVFID    0xffU
38470 #define V_PL_TOVFID(x) ((x) << S_PL_TOVFID)
38471 #define G_PL_TOVFID(x) (((x) >> S_PL_TOVFID) & M_PL_TOVFID)
38472 
38473 #define S_T6_PL_TOVFID    0
38474 #define M_T6_PL_TOVFID    0x1ffU
38475 #define V_T6_PL_TOVFID(x) ((x) << S_T6_PL_TOVFID)
38476 #define G_T6_PL_TOVFID(x) (((x) >> S_T6_PL_TOVFID) & M_T6_PL_TOVFID)
38477 
38478 #define A_PL_VFID_MAP 0x19800
38479 
38480 #define S_VFID_VLD    7
38481 #define V_VFID_VLD(x) ((x) << S_VFID_VLD)
38482 #define F_VFID_VLD    V_VFID_VLD(1U)
38483 
38484 /* registers for module LE */
38485 #define LE_BASE_ADDR 0x19c00
38486 
38487 #define A_LE_BUF_CONFIG 0x19c00
38488 #define A_LE_DB_ID 0x19c00
38489 #define A_LE_DB_CONFIG 0x19c04
38490 
38491 #define S_TCAMCMDOVLAPEN    21
38492 #define V_TCAMCMDOVLAPEN(x) ((x) << S_TCAMCMDOVLAPEN)
38493 #define F_TCAMCMDOVLAPEN    V_TCAMCMDOVLAPEN(1U)
38494 
38495 #define S_HASHEN    20
38496 #define V_HASHEN(x) ((x) << S_HASHEN)
38497 #define F_HASHEN    V_HASHEN(1U)
38498 
38499 #define S_ASBOTHSRCHEN    18
38500 #define V_ASBOTHSRCHEN(x) ((x) << S_ASBOTHSRCHEN)
38501 #define F_ASBOTHSRCHEN    V_ASBOTHSRCHEN(1U)
38502 
38503 #define S_ASLIPCOMPEN    17
38504 #define V_ASLIPCOMPEN(x) ((x) << S_ASLIPCOMPEN)
38505 #define F_ASLIPCOMPEN    V_ASLIPCOMPEN(1U)
38506 
38507 #define S_BUILD    16
38508 #define V_BUILD(x) ((x) << S_BUILD)
38509 #define F_BUILD    V_BUILD(1U)
38510 
38511 #define S_FILTEREN    11
38512 #define V_FILTEREN(x) ((x) << S_FILTEREN)
38513 #define F_FILTEREN    V_FILTEREN(1U)
38514 
38515 #define S_SYNMODE    7
38516 #define M_SYNMODE    0x3U
38517 #define V_SYNMODE(x) ((x) << S_SYNMODE)
38518 #define G_SYNMODE(x) (((x) >> S_SYNMODE) & M_SYNMODE)
38519 
38520 #define S_LEBUSEN    5
38521 #define V_LEBUSEN(x) ((x) << S_LEBUSEN)
38522 #define F_LEBUSEN    V_LEBUSEN(1U)
38523 
38524 #define S_ELOOKDUMEN    4
38525 #define V_ELOOKDUMEN(x) ((x) << S_ELOOKDUMEN)
38526 #define F_ELOOKDUMEN    V_ELOOKDUMEN(1U)
38527 
38528 #define S_IPV4ONLYEN    3
38529 #define V_IPV4ONLYEN(x) ((x) << S_IPV4ONLYEN)
38530 #define F_IPV4ONLYEN    V_IPV4ONLYEN(1U)
38531 
38532 #define S_MOSTCMDOEN    2
38533 #define V_MOSTCMDOEN(x) ((x) << S_MOSTCMDOEN)
38534 #define F_MOSTCMDOEN    V_MOSTCMDOEN(1U)
38535 
38536 #define S_DELACTSYNOEN    1
38537 #define V_DELACTSYNOEN(x) ((x) << S_DELACTSYNOEN)
38538 #define F_DELACTSYNOEN    V_DELACTSYNOEN(1U)
38539 
38540 #define S_CMDOVERLAPDIS    0
38541 #define V_CMDOVERLAPDIS(x) ((x) << S_CMDOVERLAPDIS)
38542 #define F_CMDOVERLAPDIS    V_CMDOVERLAPDIS(1U)
38543 
38544 #define S_MASKCMDOLAPDIS    26
38545 #define V_MASKCMDOLAPDIS(x) ((x) << S_MASKCMDOLAPDIS)
38546 #define F_MASKCMDOLAPDIS    V_MASKCMDOLAPDIS(1U)
38547 
38548 #define S_IPV4HASHSIZEEN    25
38549 #define V_IPV4HASHSIZEEN(x) ((x) << S_IPV4HASHSIZEEN)
38550 #define F_IPV4HASHSIZEEN    V_IPV4HASHSIZEEN(1U)
38551 
38552 #define S_PROTOCOLMASKEN    24
38553 #define V_PROTOCOLMASKEN(x) ((x) << S_PROTOCOLMASKEN)
38554 #define F_PROTOCOLMASKEN    V_PROTOCOLMASKEN(1U)
38555 
38556 #define S_TUPLESIZEEN    23
38557 #define V_TUPLESIZEEN(x) ((x) << S_TUPLESIZEEN)
38558 #define F_TUPLESIZEEN    V_TUPLESIZEEN(1U)
38559 
38560 #define S_SRVRSRAMEN    22
38561 #define V_SRVRSRAMEN(x) ((x) << S_SRVRSRAMEN)
38562 #define F_SRVRSRAMEN    V_SRVRSRAMEN(1U)
38563 
38564 #define S_ASBOTHSRCHENPR    19
38565 #define V_ASBOTHSRCHENPR(x) ((x) << S_ASBOTHSRCHENPR)
38566 #define F_ASBOTHSRCHENPR    V_ASBOTHSRCHENPR(1U)
38567 
38568 #define S_POCLIPTID0    15
38569 #define V_POCLIPTID0(x) ((x) << S_POCLIPTID0)
38570 #define F_POCLIPTID0    V_POCLIPTID0(1U)
38571 
38572 #define S_TCAMARBOFF    14
38573 #define V_TCAMARBOFF(x) ((x) << S_TCAMARBOFF)
38574 #define F_TCAMARBOFF    V_TCAMARBOFF(1U)
38575 
38576 #define S_ACCNTFULLEN    13
38577 #define V_ACCNTFULLEN(x) ((x) << S_ACCNTFULLEN)
38578 #define F_ACCNTFULLEN    V_ACCNTFULLEN(1U)
38579 
38580 #define S_FILTERRWNOCLIP    12
38581 #define V_FILTERRWNOCLIP(x) ((x) << S_FILTERRWNOCLIP)
38582 #define F_FILTERRWNOCLIP    V_FILTERRWNOCLIP(1U)
38583 
38584 #define S_CRCHASH    10
38585 #define V_CRCHASH(x) ((x) << S_CRCHASH)
38586 #define F_CRCHASH    V_CRCHASH(1U)
38587 
38588 #define S_COMPTID    9
38589 #define V_COMPTID(x) ((x) << S_COMPTID)
38590 #define F_COMPTID    V_COMPTID(1U)
38591 
38592 #define S_SINGLETHREAD    6
38593 #define V_SINGLETHREAD(x) ((x) << S_SINGLETHREAD)
38594 #define F_SINGLETHREAD    V_SINGLETHREAD(1U)
38595 
38596 #define S_CHK_FUL_TUP_ZERO    27
38597 #define V_CHK_FUL_TUP_ZERO(x) ((x) << S_CHK_FUL_TUP_ZERO)
38598 #define F_CHK_FUL_TUP_ZERO    V_CHK_FUL_TUP_ZERO(1U)
38599 
38600 #define S_PRI_HASH    26
38601 #define V_PRI_HASH(x) ((x) << S_PRI_HASH)
38602 #define F_PRI_HASH    V_PRI_HASH(1U)
38603 
38604 #define S_EXTN_HASH_IPV4    25
38605 #define V_EXTN_HASH_IPV4(x) ((x) << S_EXTN_HASH_IPV4)
38606 #define F_EXTN_HASH_IPV4    V_EXTN_HASH_IPV4(1U)
38607 
38608 #define S_ASLIPCOMPEN_IPV4    18
38609 #define V_ASLIPCOMPEN_IPV4(x) ((x) << S_ASLIPCOMPEN_IPV4)
38610 #define F_ASLIPCOMPEN_IPV4    V_ASLIPCOMPEN_IPV4(1U)
38611 
38612 #define S_IGNR_TUP_ZERO    9
38613 #define V_IGNR_TUP_ZERO(x) ((x) << S_IGNR_TUP_ZERO)
38614 #define F_IGNR_TUP_ZERO    V_IGNR_TUP_ZERO(1U)
38615 
38616 #define S_IGNR_LIP_ZERO    8
38617 #define V_IGNR_LIP_ZERO(x) ((x) << S_IGNR_LIP_ZERO)
38618 #define F_IGNR_LIP_ZERO    V_IGNR_LIP_ZERO(1U)
38619 
38620 #define S_CLCAM_INIT_BUSY    7
38621 #define V_CLCAM_INIT_BUSY(x) ((x) << S_CLCAM_INIT_BUSY)
38622 #define F_CLCAM_INIT_BUSY    V_CLCAM_INIT_BUSY(1U)
38623 
38624 #define S_CLCAM_INIT    6
38625 #define V_CLCAM_INIT(x) ((x) << S_CLCAM_INIT)
38626 #define F_CLCAM_INIT    V_CLCAM_INIT(1U)
38627 
38628 #define S_MTCAM_INIT_BUSY    5
38629 #define V_MTCAM_INIT_BUSY(x) ((x) << S_MTCAM_INIT_BUSY)
38630 #define F_MTCAM_INIT_BUSY    V_MTCAM_INIT_BUSY(1U)
38631 
38632 #define S_MTCAM_INIT    4
38633 #define V_MTCAM_INIT(x) ((x) << S_MTCAM_INIT)
38634 #define F_MTCAM_INIT    V_MTCAM_INIT(1U)
38635 
38636 #define S_REGION_EN    0
38637 #define M_REGION_EN    0xfU
38638 #define V_REGION_EN(x) ((x) << S_REGION_EN)
38639 #define G_REGION_EN(x) (((x) >> S_REGION_EN) & M_REGION_EN)
38640 
38641 #define A_LE_MISC 0x19c08
38642 
38643 #define S_CMPUNVAIL    0
38644 #define M_CMPUNVAIL    0xfU
38645 #define V_CMPUNVAIL(x) ((x) << S_CMPUNVAIL)
38646 #define G_CMPUNVAIL(x) (((x) >> S_CMPUNVAIL) & M_CMPUNVAIL)
38647 
38648 #define S_SRAMDEEPSLEEP_STAT    11
38649 #define V_SRAMDEEPSLEEP_STAT(x) ((x) << S_SRAMDEEPSLEEP_STAT)
38650 #define F_SRAMDEEPSLEEP_STAT    V_SRAMDEEPSLEEP_STAT(1U)
38651 
38652 #define S_TCAMDEEPSLEEP1_STAT    10
38653 #define V_TCAMDEEPSLEEP1_STAT(x) ((x) << S_TCAMDEEPSLEEP1_STAT)
38654 #define F_TCAMDEEPSLEEP1_STAT    V_TCAMDEEPSLEEP1_STAT(1U)
38655 
38656 #define S_TCAMDEEPSLEEP0_STAT    9
38657 #define V_TCAMDEEPSLEEP0_STAT(x) ((x) << S_TCAMDEEPSLEEP0_STAT)
38658 #define F_TCAMDEEPSLEEP0_STAT    V_TCAMDEEPSLEEP0_STAT(1U)
38659 
38660 #define S_SRAMDEEPSLEEP    8
38661 #define V_SRAMDEEPSLEEP(x) ((x) << S_SRAMDEEPSLEEP)
38662 #define F_SRAMDEEPSLEEP    V_SRAMDEEPSLEEP(1U)
38663 
38664 #define S_TCAMDEEPSLEEP1    7
38665 #define V_TCAMDEEPSLEEP1(x) ((x) << S_TCAMDEEPSLEEP1)
38666 #define F_TCAMDEEPSLEEP1    V_TCAMDEEPSLEEP1(1U)
38667 
38668 #define S_TCAMDEEPSLEEP0    6
38669 #define V_TCAMDEEPSLEEP0(x) ((x) << S_TCAMDEEPSLEEP0)
38670 #define F_TCAMDEEPSLEEP0    V_TCAMDEEPSLEEP0(1U)
38671 
38672 #define S_SRVRAMCLKOFF    5
38673 #define V_SRVRAMCLKOFF(x) ((x) << S_SRVRAMCLKOFF)
38674 #define F_SRVRAMCLKOFF    V_SRVRAMCLKOFF(1U)
38675 
38676 #define S_HASHCLKOFF    4
38677 #define V_HASHCLKOFF(x) ((x) << S_HASHCLKOFF)
38678 #define F_HASHCLKOFF    V_HASHCLKOFF(1U)
38679 
38680 #define A_LE_DB_EXEC_CTRL 0x19c08
38681 
38682 #define S_TPDB_IF_PAUSE_ACK    10
38683 #define V_TPDB_IF_PAUSE_ACK(x) ((x) << S_TPDB_IF_PAUSE_ACK)
38684 #define F_TPDB_IF_PAUSE_ACK    V_TPDB_IF_PAUSE_ACK(1U)
38685 
38686 #define S_TPDB_IF_PAUSE_REQ    9
38687 #define V_TPDB_IF_PAUSE_REQ(x) ((x) << S_TPDB_IF_PAUSE_REQ)
38688 #define F_TPDB_IF_PAUSE_REQ    V_TPDB_IF_PAUSE_REQ(1U)
38689 
38690 #define S_ERRSTOP_EN    8
38691 #define V_ERRSTOP_EN(x) ((x) << S_ERRSTOP_EN)
38692 #define F_ERRSTOP_EN    V_ERRSTOP_EN(1U)
38693 
38694 #define S_CMDLIMIT    0
38695 #define M_CMDLIMIT    0xffU
38696 #define V_CMDLIMIT(x) ((x) << S_CMDLIMIT)
38697 #define G_CMDLIMIT(x) (((x) >> S_CMDLIMIT) & M_CMDLIMIT)
38698 
38699 #define A_LE_DB_PS_CTRL 0x19c0c
38700 
38701 #define S_CLTCAMDEEPSLEEP_STAT    10
38702 #define V_CLTCAMDEEPSLEEP_STAT(x) ((x) << S_CLTCAMDEEPSLEEP_STAT)
38703 #define F_CLTCAMDEEPSLEEP_STAT    V_CLTCAMDEEPSLEEP_STAT(1U)
38704 
38705 #define S_TCAMDEEPSLEEP_STAT    9
38706 #define V_TCAMDEEPSLEEP_STAT(x) ((x) << S_TCAMDEEPSLEEP_STAT)
38707 #define F_TCAMDEEPSLEEP_STAT    V_TCAMDEEPSLEEP_STAT(1U)
38708 
38709 #define S_CLTCAMDEEPSLEEP    7
38710 #define V_CLTCAMDEEPSLEEP(x) ((x) << S_CLTCAMDEEPSLEEP)
38711 #define F_CLTCAMDEEPSLEEP    V_CLTCAMDEEPSLEEP(1U)
38712 
38713 #define S_TCAMDEEPSLEEP    6
38714 #define V_TCAMDEEPSLEEP(x) ((x) << S_TCAMDEEPSLEEP)
38715 #define F_TCAMDEEPSLEEP    V_TCAMDEEPSLEEP(1U)
38716 
38717 #define A_LE_DB_ROUTING_TABLE_INDEX 0x19c10
38718 
38719 #define S_RTINDX    7
38720 #define M_RTINDX    0x3fU
38721 #define V_RTINDX(x) ((x) << S_RTINDX)
38722 #define G_RTINDX(x) (((x) >> S_RTINDX) & M_RTINDX)
38723 
38724 #define A_LE_DB_ACTIVE_TABLE_START_INDEX 0x19c10
38725 
38726 #define S_ATINDX    0
38727 #define M_ATINDX    0xfffffU
38728 #define V_ATINDX(x) ((x) << S_ATINDX)
38729 #define G_ATINDX(x) (((x) >> S_ATINDX) & M_ATINDX)
38730 
38731 #define A_LE_DB_FILTER_TABLE_INDEX 0x19c14
38732 
38733 #define S_FTINDX    7
38734 #define M_FTINDX    0x3fU
38735 #define V_FTINDX(x) ((x) << S_FTINDX)
38736 #define G_FTINDX(x) (((x) >> S_FTINDX) & M_FTINDX)
38737 
38738 #define A_LE_DB_NORM_FILT_TABLE_START_INDEX 0x19c14
38739 
38740 #define S_NFTINDX    0
38741 #define M_NFTINDX    0xfffffU
38742 #define V_NFTINDX(x) ((x) << S_NFTINDX)
38743 #define G_NFTINDX(x) (((x) >> S_NFTINDX) & M_NFTINDX)
38744 
38745 #define A_LE_DB_SERVER_INDEX 0x19c18
38746 
38747 #define S_SRINDX    7
38748 #define M_SRINDX    0x3fU
38749 #define V_SRINDX(x) ((x) << S_SRINDX)
38750 #define G_SRINDX(x) (((x) >> S_SRINDX) & M_SRINDX)
38751 
38752 #define A_LE_DB_SRVR_START_INDEX 0x19c18
38753 
38754 #define S_T6_SRINDX    0
38755 #define M_T6_SRINDX    0xfffffU
38756 #define V_T6_SRINDX(x) ((x) << S_T6_SRINDX)
38757 #define G_T6_SRINDX(x) (((x) >> S_T6_SRINDX) & M_T6_SRINDX)
38758 
38759 #define A_LE_DB_CLIP_TABLE_INDEX 0x19c1c
38760 
38761 #define S_CLIPTINDX    7
38762 #define M_CLIPTINDX    0x3fU
38763 #define V_CLIPTINDX(x) ((x) << S_CLIPTINDX)
38764 #define G_CLIPTINDX(x) (((x) >> S_CLIPTINDX) & M_CLIPTINDX)
38765 
38766 #define A_LE_DB_HPRI_FILT_TABLE_START_INDEX 0x19c1c
38767 
38768 #define S_HFTINDX    0
38769 #define M_HFTINDX    0xfffffU
38770 #define V_HFTINDX(x) ((x) << S_HFTINDX)
38771 #define G_HFTINDX(x) (((x) >> S_HFTINDX) & M_HFTINDX)
38772 
38773 #define A_LE_DB_ACT_CNT_IPV4 0x19c20
38774 
38775 #define S_ACTCNTIPV4    0
38776 #define M_ACTCNTIPV4    0xfffffU
38777 #define V_ACTCNTIPV4(x) ((x) << S_ACTCNTIPV4)
38778 #define G_ACTCNTIPV4(x) (((x) >> S_ACTCNTIPV4) & M_ACTCNTIPV4)
38779 
38780 #define A_LE_DB_ACT_CNT_IPV6 0x19c24
38781 
38782 #define S_ACTCNTIPV6    0
38783 #define M_ACTCNTIPV6    0xfffffU
38784 #define V_ACTCNTIPV6(x) ((x) << S_ACTCNTIPV6)
38785 #define G_ACTCNTIPV6(x) (((x) >> S_ACTCNTIPV6) & M_ACTCNTIPV6)
38786 
38787 #define A_LE_DB_HASH_CONFIG 0x19c28
38788 
38789 #define S_HASHTIDSIZE    16
38790 #define M_HASHTIDSIZE    0x3fU
38791 #define V_HASHTIDSIZE(x) ((x) << S_HASHTIDSIZE)
38792 #define G_HASHTIDSIZE(x) (((x) >> S_HASHTIDSIZE) & M_HASHTIDSIZE)
38793 
38794 #define S_HASHSIZE    0
38795 #define M_HASHSIZE    0x3fU
38796 #define V_HASHSIZE(x) ((x) << S_HASHSIZE)
38797 #define G_HASHSIZE(x) (((x) >> S_HASHSIZE) & M_HASHSIZE)
38798 
38799 #define S_NUMHASHBKT    20
38800 #define M_NUMHASHBKT    0x1fU
38801 #define V_NUMHASHBKT(x) ((x) << S_NUMHASHBKT)
38802 #define G_NUMHASHBKT(x) (((x) >> S_NUMHASHBKT) & M_NUMHASHBKT)
38803 
38804 #define S_HASHTBLSIZE    3
38805 #define M_HASHTBLSIZE    0x1ffffU
38806 #define V_HASHTBLSIZE(x) ((x) << S_HASHTBLSIZE)
38807 #define G_HASHTBLSIZE(x) (((x) >> S_HASHTBLSIZE) & M_HASHTBLSIZE)
38808 
38809 #define A_LE_DB_HASH_TABLE_BASE 0x19c2c
38810 #define A_LE_DB_MIN_NUM_ACTV_TCAM_ENTRIES 0x19c2c
38811 
38812 #define S_MIN_ATCAM_ENTS    0
38813 #define M_MIN_ATCAM_ENTS    0xfffffU
38814 #define V_MIN_ATCAM_ENTS(x) ((x) << S_MIN_ATCAM_ENTS)
38815 #define G_MIN_ATCAM_ENTS(x) (((x) >> S_MIN_ATCAM_ENTS) & M_MIN_ATCAM_ENTS)
38816 
38817 #define A_LE_DB_HASH_TID_BASE 0x19c30
38818 #define A_LE_DB_HASH_TBL_BASE_ADDR 0x19c30
38819 
38820 #define S_HASHTBLADDR    4
38821 #define M_HASHTBLADDR    0xfffffffU
38822 #define V_HASHTBLADDR(x) ((x) << S_HASHTBLADDR)
38823 #define G_HASHTBLADDR(x) (((x) >> S_HASHTBLADDR) & M_HASHTBLADDR)
38824 
38825 #define A_LE_DB_SIZE 0x19c34
38826 #define A_LE_TCAM_SIZE 0x19c34
38827 
38828 #define S_TCAM_SIZE    0
38829 #define M_TCAM_SIZE    0x3U
38830 #define V_TCAM_SIZE(x) ((x) << S_TCAM_SIZE)
38831 #define G_TCAM_SIZE(x) (((x) >> S_TCAM_SIZE) & M_TCAM_SIZE)
38832 
38833 #define A_LE_DB_INT_ENABLE 0x19c38
38834 
38835 #define S_MSGSEL    27
38836 #define M_MSGSEL    0x1fU
38837 #define V_MSGSEL(x) ((x) << S_MSGSEL)
38838 #define G_MSGSEL(x) (((x) >> S_MSGSEL) & M_MSGSEL)
38839 
38840 #define S_REQQPARERR    16
38841 #define V_REQQPARERR(x) ((x) << S_REQQPARERR)
38842 #define F_REQQPARERR    V_REQQPARERR(1U)
38843 
38844 #define S_UNKNOWNCMD    15
38845 #define V_UNKNOWNCMD(x) ((x) << S_UNKNOWNCMD)
38846 #define F_UNKNOWNCMD    V_UNKNOWNCMD(1U)
38847 
38848 #define S_DROPFILTERHIT    13
38849 #define V_DROPFILTERHIT(x) ((x) << S_DROPFILTERHIT)
38850 #define F_DROPFILTERHIT    V_DROPFILTERHIT(1U)
38851 
38852 #define S_FILTERHIT    12
38853 #define V_FILTERHIT(x) ((x) << S_FILTERHIT)
38854 #define F_FILTERHIT    V_FILTERHIT(1U)
38855 
38856 #define S_SYNCOOKIEOFF    11
38857 #define V_SYNCOOKIEOFF(x) ((x) << S_SYNCOOKIEOFF)
38858 #define F_SYNCOOKIEOFF    V_SYNCOOKIEOFF(1U)
38859 
38860 #define S_SYNCOOKIEBAD    10
38861 #define V_SYNCOOKIEBAD(x) ((x) << S_SYNCOOKIEBAD)
38862 #define F_SYNCOOKIEBAD    V_SYNCOOKIEBAD(1U)
38863 
38864 #define S_SYNCOOKIE    9
38865 #define V_SYNCOOKIE(x) ((x) << S_SYNCOOKIE)
38866 #define F_SYNCOOKIE    V_SYNCOOKIE(1U)
38867 
38868 #define S_NFASRCHFAIL    8
38869 #define V_NFASRCHFAIL(x) ((x) << S_NFASRCHFAIL)
38870 #define F_NFASRCHFAIL    V_NFASRCHFAIL(1U)
38871 
38872 #define S_ACTRGNFULL    7
38873 #define V_ACTRGNFULL(x) ((x) << S_ACTRGNFULL)
38874 #define F_ACTRGNFULL    V_ACTRGNFULL(1U)
38875 
38876 #define S_PARITYERR    6
38877 #define V_PARITYERR(x) ((x) << S_PARITYERR)
38878 #define F_PARITYERR    V_PARITYERR(1U)
38879 
38880 #define S_LIPMISS    5
38881 #define V_LIPMISS(x) ((x) << S_LIPMISS)
38882 #define F_LIPMISS    V_LIPMISS(1U)
38883 
38884 #define S_LIP0    4
38885 #define V_LIP0(x) ((x) << S_LIP0)
38886 #define F_LIP0    V_LIP0(1U)
38887 
38888 #define S_MISS    3
38889 #define V_MISS(x) ((x) << S_MISS)
38890 #define F_MISS    V_MISS(1U)
38891 
38892 #define S_ROUTINGHIT    2
38893 #define V_ROUTINGHIT(x) ((x) << S_ROUTINGHIT)
38894 #define F_ROUTINGHIT    V_ROUTINGHIT(1U)
38895 
38896 #define S_ACTIVEHIT    1
38897 #define V_ACTIVEHIT(x) ((x) << S_ACTIVEHIT)
38898 #define F_ACTIVEHIT    V_ACTIVEHIT(1U)
38899 
38900 #define S_SERVERHIT    0
38901 #define V_SERVERHIT(x) ((x) << S_SERVERHIT)
38902 #define F_SERVERHIT    V_SERVERHIT(1U)
38903 
38904 #define S_ACTCNTIPV6TZERO    21
38905 #define V_ACTCNTIPV6TZERO(x) ((x) << S_ACTCNTIPV6TZERO)
38906 #define F_ACTCNTIPV6TZERO    V_ACTCNTIPV6TZERO(1U)
38907 
38908 #define S_ACTCNTIPV4TZERO    20
38909 #define V_ACTCNTIPV4TZERO(x) ((x) << S_ACTCNTIPV4TZERO)
38910 #define F_ACTCNTIPV4TZERO    V_ACTCNTIPV4TZERO(1U)
38911 
38912 #define S_ACTCNTIPV6ZERO    19
38913 #define V_ACTCNTIPV6ZERO(x) ((x) << S_ACTCNTIPV6ZERO)
38914 #define F_ACTCNTIPV6ZERO    V_ACTCNTIPV6ZERO(1U)
38915 
38916 #define S_ACTCNTIPV4ZERO    18
38917 #define V_ACTCNTIPV4ZERO(x) ((x) << S_ACTCNTIPV4ZERO)
38918 #define F_ACTCNTIPV4ZERO    V_ACTCNTIPV4ZERO(1U)
38919 
38920 #define S_MARSPPARERR    17
38921 #define V_MARSPPARERR(x) ((x) << S_MARSPPARERR)
38922 #define F_MARSPPARERR    V_MARSPPARERR(1U)
38923 
38924 #define S_VFPARERR    14
38925 #define V_VFPARERR(x) ((x) << S_VFPARERR)
38926 #define F_VFPARERR    V_VFPARERR(1U)
38927 
38928 #define S_CLIPSUBERR    29
38929 #define V_CLIPSUBERR(x) ((x) << S_CLIPSUBERR)
38930 #define F_CLIPSUBERR    V_CLIPSUBERR(1U)
38931 
38932 #define S_CLCAMFIFOERR    28
38933 #define V_CLCAMFIFOERR(x) ((x) << S_CLCAMFIFOERR)
38934 #define F_CLCAMFIFOERR    V_CLCAMFIFOERR(1U)
38935 
38936 #define S_HASHTBLMEMCRCERR    27
38937 #define V_HASHTBLMEMCRCERR(x) ((x) << S_HASHTBLMEMCRCERR)
38938 #define F_HASHTBLMEMCRCERR    V_HASHTBLMEMCRCERR(1U)
38939 
38940 #define S_CTCAMINVLDENT    26
38941 #define V_CTCAMINVLDENT(x) ((x) << S_CTCAMINVLDENT)
38942 #define F_CTCAMINVLDENT    V_CTCAMINVLDENT(1U)
38943 
38944 #define S_TCAMINVLDENT    25
38945 #define V_TCAMINVLDENT(x) ((x) << S_TCAMINVLDENT)
38946 #define F_TCAMINVLDENT    V_TCAMINVLDENT(1U)
38947 
38948 #define S_TOTCNTERR    24
38949 #define V_TOTCNTERR(x) ((x) << S_TOTCNTERR)
38950 #define F_TOTCNTERR    V_TOTCNTERR(1U)
38951 
38952 #define S_CMDPRSRINTERR    23
38953 #define V_CMDPRSRINTERR(x) ((x) << S_CMDPRSRINTERR)
38954 #define F_CMDPRSRINTERR    V_CMDPRSRINTERR(1U)
38955 
38956 #define S_CMDTIDERR    22
38957 #define V_CMDTIDERR(x) ((x) << S_CMDTIDERR)
38958 #define F_CMDTIDERR    V_CMDTIDERR(1U)
38959 
38960 #define S_T6_ACTRGNFULL    21
38961 #define V_T6_ACTRGNFULL(x) ((x) << S_T6_ACTRGNFULL)
38962 #define F_T6_ACTRGNFULL    V_T6_ACTRGNFULL(1U)
38963 
38964 #define S_T6_ACTCNTIPV6TZERO    20
38965 #define V_T6_ACTCNTIPV6TZERO(x) ((x) << S_T6_ACTCNTIPV6TZERO)
38966 #define F_T6_ACTCNTIPV6TZERO    V_T6_ACTCNTIPV6TZERO(1U)
38967 
38968 #define S_T6_ACTCNTIPV4TZERO    19
38969 #define V_T6_ACTCNTIPV4TZERO(x) ((x) << S_T6_ACTCNTIPV4TZERO)
38970 #define F_T6_ACTCNTIPV4TZERO    V_T6_ACTCNTIPV4TZERO(1U)
38971 
38972 #define S_T6_ACTCNTIPV6ZERO    18
38973 #define V_T6_ACTCNTIPV6ZERO(x) ((x) << S_T6_ACTCNTIPV6ZERO)
38974 #define F_T6_ACTCNTIPV6ZERO    V_T6_ACTCNTIPV6ZERO(1U)
38975 
38976 #define S_T6_ACTCNTIPV4ZERO    17
38977 #define V_T6_ACTCNTIPV4ZERO(x) ((x) << S_T6_ACTCNTIPV4ZERO)
38978 #define F_T6_ACTCNTIPV4ZERO    V_T6_ACTCNTIPV4ZERO(1U)
38979 
38980 #define S_MAIFWRINTPERR    16
38981 #define V_MAIFWRINTPERR(x) ((x) << S_MAIFWRINTPERR)
38982 #define F_MAIFWRINTPERR    V_MAIFWRINTPERR(1U)
38983 
38984 #define S_HASHTBLMEMACCERR    15
38985 #define V_HASHTBLMEMACCERR(x) ((x) << S_HASHTBLMEMACCERR)
38986 #define F_HASHTBLMEMACCERR    V_HASHTBLMEMACCERR(1U)
38987 
38988 #define S_TCAMCRCERR    14
38989 #define V_TCAMCRCERR(x) ((x) << S_TCAMCRCERR)
38990 #define F_TCAMCRCERR    V_TCAMCRCERR(1U)
38991 
38992 #define S_TCAMINTPERR    13
38993 #define V_TCAMINTPERR(x) ((x) << S_TCAMINTPERR)
38994 #define F_TCAMINTPERR    V_TCAMINTPERR(1U)
38995 
38996 #define S_VFSRAMPERR    12
38997 #define V_VFSRAMPERR(x) ((x) << S_VFSRAMPERR)
38998 #define F_VFSRAMPERR    V_VFSRAMPERR(1U)
38999 
39000 #define S_SRVSRAMPERR    11
39001 #define V_SRVSRAMPERR(x) ((x) << S_SRVSRAMPERR)
39002 #define F_SRVSRAMPERR    V_SRVSRAMPERR(1U)
39003 
39004 #define S_SSRAMINTPERR    10
39005 #define V_SSRAMINTPERR(x) ((x) << S_SSRAMINTPERR)
39006 #define F_SSRAMINTPERR    V_SSRAMINTPERR(1U)
39007 
39008 #define S_CLCAMINTPERR    9
39009 #define V_CLCAMINTPERR(x) ((x) << S_CLCAMINTPERR)
39010 #define F_CLCAMINTPERR    V_CLCAMINTPERR(1U)
39011 
39012 #define S_CLCAMCRCPARERR    8
39013 #define V_CLCAMCRCPARERR(x) ((x) << S_CLCAMCRCPARERR)
39014 #define F_CLCAMCRCPARERR    V_CLCAMCRCPARERR(1U)
39015 
39016 #define S_HASHTBLACCFAIL    7
39017 #define V_HASHTBLACCFAIL(x) ((x) << S_HASHTBLACCFAIL)
39018 #define F_HASHTBLACCFAIL    V_HASHTBLACCFAIL(1U)
39019 
39020 #define S_TCAMACCFAIL    6
39021 #define V_TCAMACCFAIL(x) ((x) << S_TCAMACCFAIL)
39022 #define F_TCAMACCFAIL    V_TCAMACCFAIL(1U)
39023 
39024 #define S_SRVSRAMACCFAIL    5
39025 #define V_SRVSRAMACCFAIL(x) ((x) << S_SRVSRAMACCFAIL)
39026 #define F_SRVSRAMACCFAIL    V_SRVSRAMACCFAIL(1U)
39027 
39028 #define S_CLIPTCAMACCFAIL    4
39029 #define V_CLIPTCAMACCFAIL(x) ((x) << S_CLIPTCAMACCFAIL)
39030 #define F_CLIPTCAMACCFAIL    V_CLIPTCAMACCFAIL(1U)
39031 
39032 #define S_T6_UNKNOWNCMD    3
39033 #define V_T6_UNKNOWNCMD(x) ((x) << S_T6_UNKNOWNCMD)
39034 #define F_T6_UNKNOWNCMD    V_T6_UNKNOWNCMD(1U)
39035 
39036 #define S_T6_LIP0    2
39037 #define V_T6_LIP0(x) ((x) << S_T6_LIP0)
39038 #define F_T6_LIP0    V_T6_LIP0(1U)
39039 
39040 #define S_T6_LIPMISS    1
39041 #define V_T6_LIPMISS(x) ((x) << S_T6_LIPMISS)
39042 #define F_T6_LIPMISS    V_T6_LIPMISS(1U)
39043 
39044 #define S_PIPELINEERR    0
39045 #define V_PIPELINEERR(x) ((x) << S_PIPELINEERR)
39046 #define F_PIPELINEERR    V_PIPELINEERR(1U)
39047 
39048 #define A_LE_DB_INT_CAUSE 0x19c3c
39049 
39050 #define S_T6_ACTRGNFULL    21
39051 #define V_T6_ACTRGNFULL(x) ((x) << S_T6_ACTRGNFULL)
39052 #define F_T6_ACTRGNFULL    V_T6_ACTRGNFULL(1U)
39053 
39054 #define S_T6_ACTCNTIPV6TZERO    20
39055 #define V_T6_ACTCNTIPV6TZERO(x) ((x) << S_T6_ACTCNTIPV6TZERO)
39056 #define F_T6_ACTCNTIPV6TZERO    V_T6_ACTCNTIPV6TZERO(1U)
39057 
39058 #define S_T6_ACTCNTIPV4TZERO    19
39059 #define V_T6_ACTCNTIPV4TZERO(x) ((x) << S_T6_ACTCNTIPV4TZERO)
39060 #define F_T6_ACTCNTIPV4TZERO    V_T6_ACTCNTIPV4TZERO(1U)
39061 
39062 #define S_T6_ACTCNTIPV6ZERO    18
39063 #define V_T6_ACTCNTIPV6ZERO(x) ((x) << S_T6_ACTCNTIPV6ZERO)
39064 #define F_T6_ACTCNTIPV6ZERO    V_T6_ACTCNTIPV6ZERO(1U)
39065 
39066 #define S_T6_ACTCNTIPV4ZERO    17
39067 #define V_T6_ACTCNTIPV4ZERO(x) ((x) << S_T6_ACTCNTIPV4ZERO)
39068 #define F_T6_ACTCNTIPV4ZERO    V_T6_ACTCNTIPV4ZERO(1U)
39069 
39070 #define S_T6_UNKNOWNCMD    3
39071 #define V_T6_UNKNOWNCMD(x) ((x) << S_T6_UNKNOWNCMD)
39072 #define F_T6_UNKNOWNCMD    V_T6_UNKNOWNCMD(1U)
39073 
39074 #define S_T6_LIP0    2
39075 #define V_T6_LIP0(x) ((x) << S_T6_LIP0)
39076 #define F_T6_LIP0    V_T6_LIP0(1U)
39077 
39078 #define S_T6_LIPMISS    1
39079 #define V_T6_LIPMISS(x) ((x) << S_T6_LIPMISS)
39080 #define F_T6_LIPMISS    V_T6_LIPMISS(1U)
39081 
39082 #define A_LE_DB_INT_TID 0x19c40
39083 
39084 #define S_INTTID    0
39085 #define M_INTTID    0xfffffU
39086 #define V_INTTID(x) ((x) << S_INTTID)
39087 #define G_INTTID(x) (((x) >> S_INTTID) & M_INTTID)
39088 
39089 #define A_LE_DB_DBG_MATCH_CMD_IDX_MASK 0x19c40
39090 
39091 #define S_CMD_CMP_MASK    20
39092 #define M_CMD_CMP_MASK    0x1fU
39093 #define V_CMD_CMP_MASK(x) ((x) << S_CMD_CMP_MASK)
39094 #define G_CMD_CMP_MASK(x) (((x) >> S_CMD_CMP_MASK) & M_CMD_CMP_MASK)
39095 
39096 #define S_TID_CMP_MASK    0
39097 #define M_TID_CMP_MASK    0xfffffU
39098 #define V_TID_CMP_MASK(x) ((x) << S_TID_CMP_MASK)
39099 #define G_TID_CMP_MASK(x) (((x) >> S_TID_CMP_MASK) & M_TID_CMP_MASK)
39100 
39101 #define A_LE_DB_INT_PTID 0x19c44
39102 
39103 #define S_INTPTID    0
39104 #define M_INTPTID    0xfffffU
39105 #define V_INTPTID(x) ((x) << S_INTPTID)
39106 #define G_INTPTID(x) (((x) >> S_INTPTID) & M_INTPTID)
39107 
39108 #define A_LE_DB_DBG_MATCH_CMD_IDX_DATA 0x19c44
39109 
39110 #define S_CMD_CMP    20
39111 #define M_CMD_CMP    0x1fU
39112 #define V_CMD_CMP(x) ((x) << S_CMD_CMP)
39113 #define G_CMD_CMP(x) (((x) >> S_CMD_CMP) & M_CMD_CMP)
39114 
39115 #define S_TID_CMP    0
39116 #define M_TID_CMP    0xfffffU
39117 #define V_TID_CMP(x) ((x) << S_TID_CMP)
39118 #define G_TID_CMP(x) (((x) >> S_TID_CMP) & M_TID_CMP)
39119 
39120 #define A_LE_DB_INT_INDEX 0x19c48
39121 
39122 #define S_INTINDEX    0
39123 #define M_INTINDEX    0xfffffU
39124 #define V_INTINDEX(x) ((x) << S_INTINDEX)
39125 #define G_INTINDEX(x) (((x) >> S_INTINDEX) & M_INTINDEX)
39126 
39127 #define A_LE_DB_ERR_CMD_TID 0x19c48
39128 
39129 #define S_ERR_CID    22
39130 #define M_ERR_CID    0xffU
39131 #define V_ERR_CID(x) ((x) << S_ERR_CID)
39132 #define G_ERR_CID(x) (((x) >> S_ERR_CID) & M_ERR_CID)
39133 
39134 #define S_ERR_PROT    20
39135 #define M_ERR_PROT    0x3U
39136 #define V_ERR_PROT(x) ((x) << S_ERR_PROT)
39137 #define G_ERR_PROT(x) (((x) >> S_ERR_PROT) & M_ERR_PROT)
39138 
39139 #define S_ERR_TID    0
39140 #define M_ERR_TID    0xfffffU
39141 #define V_ERR_TID(x) ((x) << S_ERR_TID)
39142 #define G_ERR_TID(x) (((x) >> S_ERR_TID) & M_ERR_TID)
39143 
39144 #define A_LE_DB_INT_CMD 0x19c4c
39145 
39146 #define S_INTCMD    0
39147 #define M_INTCMD    0xfU
39148 #define V_INTCMD(x) ((x) << S_INTCMD)
39149 #define G_INTCMD(x) (((x) >> S_INTCMD) & M_INTCMD)
39150 
39151 #define A_LE_DB_MASK_IPV4 0x19c50
39152 #define A_LE_T5_DB_MASK_IPV4 0x19c50
39153 #define A_LE_DB_DBG_MATCH_DATA_MASK 0x19c50
39154 #define A_LE_DB_MAX_NUM_HASH_ENTRIES 0x19c70
39155 
39156 #define S_MAX_HASH_ENTS    0
39157 #define M_MAX_HASH_ENTS    0xfffffU
39158 #define V_MAX_HASH_ENTS(x) ((x) << S_MAX_HASH_ENTS)
39159 #define G_MAX_HASH_ENTS(x) (((x) >> S_MAX_HASH_ENTS) & M_MAX_HASH_ENTS)
39160 
39161 #define A_LE_DB_RSP_CODE_0 0x19c74
39162 
39163 #define S_SUCCESS    25
39164 #define M_SUCCESS    0x1fU
39165 #define V_SUCCESS(x) ((x) << S_SUCCESS)
39166 #define G_SUCCESS(x) (((x) >> S_SUCCESS) & M_SUCCESS)
39167 
39168 #define S_TCAM_ACTV_SUCC    20
39169 #define M_TCAM_ACTV_SUCC    0x1fU
39170 #define V_TCAM_ACTV_SUCC(x) ((x) << S_TCAM_ACTV_SUCC)
39171 #define G_TCAM_ACTV_SUCC(x) (((x) >> S_TCAM_ACTV_SUCC) & M_TCAM_ACTV_SUCC)
39172 
39173 #define S_HASH_ACTV_SUCC    15
39174 #define M_HASH_ACTV_SUCC    0x1fU
39175 #define V_HASH_ACTV_SUCC(x) ((x) << S_HASH_ACTV_SUCC)
39176 #define G_HASH_ACTV_SUCC(x) (((x) >> S_HASH_ACTV_SUCC) & M_HASH_ACTV_SUCC)
39177 
39178 #define S_TCAM_SRVR_HIT    10
39179 #define M_TCAM_SRVR_HIT    0x1fU
39180 #define V_TCAM_SRVR_HIT(x) ((x) << S_TCAM_SRVR_HIT)
39181 #define G_TCAM_SRVR_HIT(x) (((x) >> S_TCAM_SRVR_HIT) & M_TCAM_SRVR_HIT)
39182 
39183 #define S_SRAM_SRVR_HIT    5
39184 #define M_SRAM_SRVR_HIT    0x1fU
39185 #define V_SRAM_SRVR_HIT(x) ((x) << S_SRAM_SRVR_HIT)
39186 #define G_SRAM_SRVR_HIT(x) (((x) >> S_SRAM_SRVR_HIT) & M_SRAM_SRVR_HIT)
39187 
39188 #define S_TCAM_ACTV_HIT    0
39189 #define M_TCAM_ACTV_HIT    0x1fU
39190 #define V_TCAM_ACTV_HIT(x) ((x) << S_TCAM_ACTV_HIT)
39191 #define G_TCAM_ACTV_HIT(x) (((x) >> S_TCAM_ACTV_HIT) & M_TCAM_ACTV_HIT)
39192 
39193 #define A_LE_DB_RSP_CODE_1 0x19c78
39194 
39195 #define S_HASH_ACTV_HIT    25
39196 #define M_HASH_ACTV_HIT    0x1fU
39197 #define V_HASH_ACTV_HIT(x) ((x) << S_HASH_ACTV_HIT)
39198 #define G_HASH_ACTV_HIT(x) (((x) >> S_HASH_ACTV_HIT) & M_HASH_ACTV_HIT)
39199 
39200 #define S_T6_MISS    20
39201 #define M_T6_MISS    0x1fU
39202 #define V_T6_MISS(x) ((x) << S_T6_MISS)
39203 #define G_T6_MISS(x) (((x) >> S_T6_MISS) & M_T6_MISS)
39204 
39205 #define S_NORM_FILT_HIT    15
39206 #define M_NORM_FILT_HIT    0x1fU
39207 #define V_NORM_FILT_HIT(x) ((x) << S_NORM_FILT_HIT)
39208 #define G_NORM_FILT_HIT(x) (((x) >> S_NORM_FILT_HIT) & M_NORM_FILT_HIT)
39209 
39210 #define S_HPRI_FILT_HIT    10
39211 #define M_HPRI_FILT_HIT    0x1fU
39212 #define V_HPRI_FILT_HIT(x) ((x) << S_HPRI_FILT_HIT)
39213 #define G_HPRI_FILT_HIT(x) (((x) >> S_HPRI_FILT_HIT) & M_HPRI_FILT_HIT)
39214 
39215 #define S_ACTV_OPEN_ERR    5
39216 #define M_ACTV_OPEN_ERR    0x1fU
39217 #define V_ACTV_OPEN_ERR(x) ((x) << S_ACTV_OPEN_ERR)
39218 #define G_ACTV_OPEN_ERR(x) (((x) >> S_ACTV_OPEN_ERR) & M_ACTV_OPEN_ERR)
39219 
39220 #define S_ACTV_FULL_ERR    0
39221 #define M_ACTV_FULL_ERR    0x1fU
39222 #define V_ACTV_FULL_ERR(x) ((x) << S_ACTV_FULL_ERR)
39223 #define G_ACTV_FULL_ERR(x) (((x) >> S_ACTV_FULL_ERR) & M_ACTV_FULL_ERR)
39224 
39225 #define A_LE_DB_RSP_CODE_2 0x19c7c
39226 
39227 #define S_SRCH_RGN_HIT    25
39228 #define M_SRCH_RGN_HIT    0x1fU
39229 #define V_SRCH_RGN_HIT(x) ((x) << S_SRCH_RGN_HIT)
39230 #define G_SRCH_RGN_HIT(x) (((x) >> S_SRCH_RGN_HIT) & M_SRCH_RGN_HIT)
39231 
39232 #define S_CLIP_FAIL    20
39233 #define M_CLIP_FAIL    0x1fU
39234 #define V_CLIP_FAIL(x) ((x) << S_CLIP_FAIL)
39235 #define G_CLIP_FAIL(x) (((x) >> S_CLIP_FAIL) & M_CLIP_FAIL)
39236 
39237 #define S_LIP_ZERO_ERR    15
39238 #define M_LIP_ZERO_ERR    0x1fU
39239 #define V_LIP_ZERO_ERR(x) ((x) << S_LIP_ZERO_ERR)
39240 #define G_LIP_ZERO_ERR(x) (((x) >> S_LIP_ZERO_ERR) & M_LIP_ZERO_ERR)
39241 
39242 #define S_UNKNOWN_CMD    10
39243 #define M_UNKNOWN_CMD    0x1fU
39244 #define V_UNKNOWN_CMD(x) ((x) << S_UNKNOWN_CMD)
39245 #define G_UNKNOWN_CMD(x) (((x) >> S_UNKNOWN_CMD) & M_UNKNOWN_CMD)
39246 
39247 #define S_CMD_TID_ERR    5
39248 #define M_CMD_TID_ERR    0x1fU
39249 #define V_CMD_TID_ERR(x) ((x) << S_CMD_TID_ERR)
39250 #define G_CMD_TID_ERR(x) (((x) >> S_CMD_TID_ERR) & M_CMD_TID_ERR)
39251 
39252 #define S_INTERNAL_ERR    0
39253 #define M_INTERNAL_ERR    0x1fU
39254 #define V_INTERNAL_ERR(x) ((x) << S_INTERNAL_ERR)
39255 #define G_INTERNAL_ERR(x) (((x) >> S_INTERNAL_ERR) & M_INTERNAL_ERR)
39256 
39257 #define A_LE_DB_RSP_CODE_3 0x19c80
39258 
39259 #define S_SRAM_SRVR_HIT_ACTF    25
39260 #define M_SRAM_SRVR_HIT_ACTF    0x1fU
39261 #define V_SRAM_SRVR_HIT_ACTF(x) ((x) << S_SRAM_SRVR_HIT_ACTF)
39262 #define G_SRAM_SRVR_HIT_ACTF(x) (((x) >> S_SRAM_SRVR_HIT_ACTF) & M_SRAM_SRVR_HIT_ACTF)
39263 
39264 #define S_TCAM_SRVR_HIT_ACTF    20
39265 #define M_TCAM_SRVR_HIT_ACTF    0x1fU
39266 #define V_TCAM_SRVR_HIT_ACTF(x) ((x) << S_TCAM_SRVR_HIT_ACTF)
39267 #define G_TCAM_SRVR_HIT_ACTF(x) (((x) >> S_TCAM_SRVR_HIT_ACTF) & M_TCAM_SRVR_HIT_ACTF)
39268 
39269 #define S_INVLDRD    15
39270 #define M_INVLDRD    0x1fU
39271 #define V_INVLDRD(x) ((x) << S_INVLDRD)
39272 #define G_INVLDRD(x) (((x) >> S_INVLDRD) & M_INVLDRD)
39273 
39274 #define S_TUPLZERO    10
39275 #define M_TUPLZERO    0x1fU
39276 #define V_TUPLZERO(x) ((x) << S_TUPLZERO)
39277 #define G_TUPLZERO(x) (((x) >> S_TUPLZERO) & M_TUPLZERO)
39278 
39279 #define A_LE_DB_ACT_CNT_IPV4_TCAM 0x19c94
39280 #define A_LE_DB_ACT_CNT_IPV6_TCAM 0x19c98
39281 #define A_LE_ACT_CNT_THRSH 0x19c9c
39282 
39283 #define S_ACT_CNT_THRSH    0
39284 #define M_ACT_CNT_THRSH    0x1fffffU
39285 #define V_ACT_CNT_THRSH(x) ((x) << S_ACT_CNT_THRSH)
39286 #define G_ACT_CNT_THRSH(x) (((x) >> S_ACT_CNT_THRSH) & M_ACT_CNT_THRSH)
39287 
39288 #define A_LE_DB_MASK_IPV6 0x19ca0
39289 #define A_LE_DB_DBG_MATCH_DATA 0x19ca0
39290 #define A_LE_DB_REQ_RSP_CNT 0x19ce4
39291 
39292 #define S_T4_RSPCNT    16
39293 #define M_T4_RSPCNT    0xffffU
39294 #define V_T4_RSPCNT(x) ((x) << S_T4_RSPCNT)
39295 #define G_T4_RSPCNT(x) (((x) >> S_T4_RSPCNT) & M_T4_RSPCNT)
39296 
39297 #define S_T4_REQCNT    0
39298 #define M_T4_REQCNT    0xffffU
39299 #define V_T4_REQCNT(x) ((x) << S_T4_REQCNT)
39300 #define G_T4_REQCNT(x) (((x) >> S_T4_REQCNT) & M_T4_REQCNT)
39301 
39302 #define S_RSPCNTLE    16
39303 #define M_RSPCNTLE    0xffffU
39304 #define V_RSPCNTLE(x) ((x) << S_RSPCNTLE)
39305 #define G_RSPCNTLE(x) (((x) >> S_RSPCNTLE) & M_RSPCNTLE)
39306 
39307 #define S_REQCNTLE    0
39308 #define M_REQCNTLE    0xffffU
39309 #define V_REQCNTLE(x) ((x) << S_REQCNTLE)
39310 #define G_REQCNTLE(x) (((x) >> S_REQCNTLE) & M_REQCNTLE)
39311 
39312 #define A_LE_DB_DBGI_CONFIG 0x19cf0
39313 
39314 #define S_DBGICMDPERR    31
39315 #define V_DBGICMDPERR(x) ((x) << S_DBGICMDPERR)
39316 #define F_DBGICMDPERR    V_DBGICMDPERR(1U)
39317 
39318 #define S_DBGICMDRANGE    22
39319 #define M_DBGICMDRANGE    0x7U
39320 #define V_DBGICMDRANGE(x) ((x) << S_DBGICMDRANGE)
39321 #define G_DBGICMDRANGE(x) (((x) >> S_DBGICMDRANGE) & M_DBGICMDRANGE)
39322 
39323 #define S_DBGICMDMSKTYPE    21
39324 #define V_DBGICMDMSKTYPE(x) ((x) << S_DBGICMDMSKTYPE)
39325 #define F_DBGICMDMSKTYPE    V_DBGICMDMSKTYPE(1U)
39326 
39327 #define S_DBGICMDSEARCH    20
39328 #define V_DBGICMDSEARCH(x) ((x) << S_DBGICMDSEARCH)
39329 #define F_DBGICMDSEARCH    V_DBGICMDSEARCH(1U)
39330 
39331 #define S_DBGICMDREAD    19
39332 #define V_DBGICMDREAD(x) ((x) << S_DBGICMDREAD)
39333 #define F_DBGICMDREAD    V_DBGICMDREAD(1U)
39334 
39335 #define S_DBGICMDLEARN    18
39336 #define V_DBGICMDLEARN(x) ((x) << S_DBGICMDLEARN)
39337 #define F_DBGICMDLEARN    V_DBGICMDLEARN(1U)
39338 
39339 #define S_DBGICMDERASE    17
39340 #define V_DBGICMDERASE(x) ((x) << S_DBGICMDERASE)
39341 #define F_DBGICMDERASE    V_DBGICMDERASE(1U)
39342 
39343 #define S_DBGICMDIPV6    16
39344 #define V_DBGICMDIPV6(x) ((x) << S_DBGICMDIPV6)
39345 #define F_DBGICMDIPV6    V_DBGICMDIPV6(1U)
39346 
39347 #define S_DBGICMDTYPE    13
39348 #define M_DBGICMDTYPE    0x7U
39349 #define V_DBGICMDTYPE(x) ((x) << S_DBGICMDTYPE)
39350 #define G_DBGICMDTYPE(x) (((x) >> S_DBGICMDTYPE) & M_DBGICMDTYPE)
39351 
39352 #define S_DBGICMDACKERR    12
39353 #define V_DBGICMDACKERR(x) ((x) << S_DBGICMDACKERR)
39354 #define F_DBGICMDACKERR    V_DBGICMDACKERR(1U)
39355 
39356 #define S_DBGICMDBUSY    3
39357 #define V_DBGICMDBUSY(x) ((x) << S_DBGICMDBUSY)
39358 #define F_DBGICMDBUSY    V_DBGICMDBUSY(1U)
39359 
39360 #define S_DBGICMDSTRT    2
39361 #define V_DBGICMDSTRT(x) ((x) << S_DBGICMDSTRT)
39362 #define F_DBGICMDSTRT    V_DBGICMDSTRT(1U)
39363 
39364 #define S_DBGICMDMODE    0
39365 #define M_DBGICMDMODE    0x3U
39366 #define V_DBGICMDMODE(x) ((x) << S_DBGICMDMODE)
39367 #define G_DBGICMDMODE(x) (((x) >> S_DBGICMDMODE) & M_DBGICMDMODE)
39368 
39369 #define S_DBGICMDMSKREAD    21
39370 #define V_DBGICMDMSKREAD(x) ((x) << S_DBGICMDMSKREAD)
39371 #define F_DBGICMDMSKREAD    V_DBGICMDMSKREAD(1U)
39372 
39373 #define S_DBGICMDWRITE    17
39374 #define V_DBGICMDWRITE(x) ((x) << S_DBGICMDWRITE)
39375 #define F_DBGICMDWRITE    V_DBGICMDWRITE(1U)
39376 
39377 #define A_LE_DB_DBGI_REQ_TCAM_CMD 0x19cf4
39378 
39379 #define S_DBGICMD    20
39380 #define M_DBGICMD    0xfU
39381 #define V_DBGICMD(x) ((x) << S_DBGICMD)
39382 #define G_DBGICMD(x) (((x) >> S_DBGICMD) & M_DBGICMD)
39383 
39384 #define S_DBGITINDEX    0
39385 #define M_DBGITINDEX    0xfffffU
39386 #define V_DBGITINDEX(x) ((x) << S_DBGITINDEX)
39387 #define G_DBGITINDEX(x) (((x) >> S_DBGITINDEX) & M_DBGITINDEX)
39388 
39389 #define A_LE_DB_DBGI_REQ_CMD 0x19cf4
39390 
39391 #define S_DBGITID    0
39392 #define M_DBGITID    0xfffffU
39393 #define V_DBGITID(x) ((x) << S_DBGITID)
39394 #define G_DBGITID(x) (((x) >> S_DBGITID) & M_DBGITID)
39395 
39396 #define A_LE_PERR_ENABLE 0x19cf8
39397 
39398 #define S_REQQUEUE    1
39399 #define V_REQQUEUE(x) ((x) << S_REQQUEUE)
39400 #define F_REQQUEUE    V_REQQUEUE(1U)
39401 
39402 #define S_TCAM    0
39403 #define V_TCAM(x) ((x) << S_TCAM)
39404 #define F_TCAM    V_TCAM(1U)
39405 
39406 #define S_MARSPPARERRLE    17
39407 #define V_MARSPPARERRLE(x) ((x) << S_MARSPPARERRLE)
39408 #define F_MARSPPARERRLE    V_MARSPPARERRLE(1U)
39409 
39410 #define S_REQQUEUELE    16
39411 #define V_REQQUEUELE(x) ((x) << S_REQQUEUELE)
39412 #define F_REQQUEUELE    V_REQQUEUELE(1U)
39413 
39414 #define S_VFPARERRLE    14
39415 #define V_VFPARERRLE(x) ((x) << S_VFPARERRLE)
39416 #define F_VFPARERRLE    V_VFPARERRLE(1U)
39417 
39418 #define S_TCAMLE    6
39419 #define V_TCAMLE(x) ((x) << S_TCAMLE)
39420 #define F_TCAMLE    V_TCAMLE(1U)
39421 
39422 #define S_BKCHKPERIOD    22
39423 #define M_BKCHKPERIOD    0x3ffU
39424 #define V_BKCHKPERIOD(x) ((x) << S_BKCHKPERIOD)
39425 #define G_BKCHKPERIOD(x) (((x) >> S_BKCHKPERIOD) & M_BKCHKPERIOD)
39426 
39427 #define S_TCAMBKCHKEN    21
39428 #define V_TCAMBKCHKEN(x) ((x) << S_TCAMBKCHKEN)
39429 #define F_TCAMBKCHKEN    V_TCAMBKCHKEN(1U)
39430 
39431 #define S_T6_CLCAMFIFOERR    2
39432 #define V_T6_CLCAMFIFOERR(x) ((x) << S_T6_CLCAMFIFOERR)
39433 #define F_T6_CLCAMFIFOERR    V_T6_CLCAMFIFOERR(1U)
39434 
39435 #define S_T6_HASHTBLMEMCRCERR    1
39436 #define V_T6_HASHTBLMEMCRCERR(x) ((x) << S_T6_HASHTBLMEMCRCERR)
39437 #define F_T6_HASHTBLMEMCRCERR    V_T6_HASHTBLMEMCRCERR(1U)
39438 
39439 #define A_LE_SPARE 0x19cfc
39440 #define A_LE_DB_DBGI_REQ_DATA 0x19d00
39441 #define A_LE_DB_DBGI_REQ_MASK 0x19d50
39442 #define A_LE_DB_DBGI_RSP_STATUS 0x19d94
39443 
39444 #define S_DBGIRSPINDEX    12
39445 #define M_DBGIRSPINDEX    0xfffffU
39446 #define V_DBGIRSPINDEX(x) ((x) << S_DBGIRSPINDEX)
39447 #define G_DBGIRSPINDEX(x) (((x) >> S_DBGIRSPINDEX) & M_DBGIRSPINDEX)
39448 
39449 #define S_DBGIRSPMSG    8
39450 #define M_DBGIRSPMSG    0xfU
39451 #define V_DBGIRSPMSG(x) ((x) << S_DBGIRSPMSG)
39452 #define G_DBGIRSPMSG(x) (((x) >> S_DBGIRSPMSG) & M_DBGIRSPMSG)
39453 
39454 #define S_DBGIRSPMSGVLD    7
39455 #define V_DBGIRSPMSGVLD(x) ((x) << S_DBGIRSPMSGVLD)
39456 #define F_DBGIRSPMSGVLD    V_DBGIRSPMSGVLD(1U)
39457 
39458 #define S_DBGIRSPMHIT    2
39459 #define V_DBGIRSPMHIT(x) ((x) << S_DBGIRSPMHIT)
39460 #define F_DBGIRSPMHIT    V_DBGIRSPMHIT(1U)
39461 
39462 #define S_DBGIRSPHIT    1
39463 #define V_DBGIRSPHIT(x) ((x) << S_DBGIRSPHIT)
39464 #define F_DBGIRSPHIT    V_DBGIRSPHIT(1U)
39465 
39466 #define S_DBGIRSPVALID    0
39467 #define V_DBGIRSPVALID(x) ((x) << S_DBGIRSPVALID)
39468 #define F_DBGIRSPVALID    V_DBGIRSPVALID(1U)
39469 
39470 #define S_DBGIRSPTID    12
39471 #define M_DBGIRSPTID    0xfffffU
39472 #define V_DBGIRSPTID(x) ((x) << S_DBGIRSPTID)
39473 #define G_DBGIRSPTID(x) (((x) >> S_DBGIRSPTID) & M_DBGIRSPTID)
39474 
39475 #define S_DBGIRSPLEARN    2
39476 #define V_DBGIRSPLEARN(x) ((x) << S_DBGIRSPLEARN)
39477 #define F_DBGIRSPLEARN    V_DBGIRSPLEARN(1U)
39478 
39479 #define A_LE_DBG_SEL 0x19d98
39480 #define A_LE_DB_DBGI_RSP_DATA 0x19da0
39481 #define A_LE_DB_DBGI_RSP_LAST_CMD 0x19de4
39482 
39483 #define S_LASTCMDB    16
39484 #define M_LASTCMDB    0x7ffU
39485 #define V_LASTCMDB(x) ((x) << S_LASTCMDB)
39486 #define G_LASTCMDB(x) (((x) >> S_LASTCMDB) & M_LASTCMDB)
39487 
39488 #define S_LASTCMDA    0
39489 #define M_LASTCMDA    0x7ffU
39490 #define V_LASTCMDA(x) ((x) << S_LASTCMDA)
39491 #define G_LASTCMDA(x) (((x) >> S_LASTCMDA) & M_LASTCMDA)
39492 
39493 #define A_LE_DB_DROP_FILTER_ENTRY 0x19de8
39494 
39495 #define S_DROPFILTEREN    31
39496 #define V_DROPFILTEREN(x) ((x) << S_DROPFILTEREN)
39497 #define F_DROPFILTEREN    V_DROPFILTEREN(1U)
39498 
39499 #define S_DROPFILTERCLEAR    17
39500 #define V_DROPFILTERCLEAR(x) ((x) << S_DROPFILTERCLEAR)
39501 #define F_DROPFILTERCLEAR    V_DROPFILTERCLEAR(1U)
39502 
39503 #define S_DROPFILTERSET    16
39504 #define V_DROPFILTERSET(x) ((x) << S_DROPFILTERSET)
39505 #define F_DROPFILTERSET    V_DROPFILTERSET(1U)
39506 
39507 #define S_DROPFILTERFIDX    0
39508 #define M_DROPFILTERFIDX    0x1fffU
39509 #define V_DROPFILTERFIDX(x) ((x) << S_DROPFILTERFIDX)
39510 #define G_DROPFILTERFIDX(x) (((x) >> S_DROPFILTERFIDX) & M_DROPFILTERFIDX)
39511 
39512 #define A_LE_DB_PTID_SVRBASE 0x19df0
39513 
39514 #define S_SVRBASE_ADDR    2
39515 #define M_SVRBASE_ADDR    0x3ffffU
39516 #define V_SVRBASE_ADDR(x) ((x) << S_SVRBASE_ADDR)
39517 #define G_SVRBASE_ADDR(x) (((x) >> S_SVRBASE_ADDR) & M_SVRBASE_ADDR)
39518 
39519 #define A_LE_DB_TCAM_TID_BASE 0x19df0
39520 
39521 #define S_TCAM_TID_BASE    0
39522 #define M_TCAM_TID_BASE    0xfffffU
39523 #define V_TCAM_TID_BASE(x) ((x) << S_TCAM_TID_BASE)
39524 #define G_TCAM_TID_BASE(x) (((x) >> S_TCAM_TID_BASE) & M_TCAM_TID_BASE)
39525 
39526 #define A_LE_DB_FTID_FLTRBASE 0x19df4
39527 
39528 #define S_FLTRBASE_ADDR    2
39529 #define M_FLTRBASE_ADDR    0x3ffffU
39530 #define V_FLTRBASE_ADDR(x) ((x) << S_FLTRBASE_ADDR)
39531 #define G_FLTRBASE_ADDR(x) (((x) >> S_FLTRBASE_ADDR) & M_FLTRBASE_ADDR)
39532 
39533 #define A_LE_DB_CLCAM_TID_BASE 0x19df4
39534 
39535 #define S_CLCAM_TID_BASE    0
39536 #define M_CLCAM_TID_BASE    0xfffffU
39537 #define V_CLCAM_TID_BASE(x) ((x) << S_CLCAM_TID_BASE)
39538 #define G_CLCAM_TID_BASE(x) (((x) >> S_CLCAM_TID_BASE) & M_CLCAM_TID_BASE)
39539 
39540 #define A_LE_DB_TID_HASHBASE 0x19df8
39541 
39542 #define S_HASHBASE_ADDR    2
39543 #define M_HASHBASE_ADDR    0xfffffU
39544 #define V_HASHBASE_ADDR(x) ((x) << S_HASHBASE_ADDR)
39545 #define G_HASHBASE_ADDR(x) (((x) >> S_HASHBASE_ADDR) & M_HASHBASE_ADDR)
39546 
39547 #define A_T6_LE_DB_HASH_TID_BASE 0x19df8
39548 
39549 #define S_HASH_TID_BASE    0
39550 #define M_HASH_TID_BASE    0xfffffU
39551 #define V_HASH_TID_BASE(x) ((x) << S_HASH_TID_BASE)
39552 #define G_HASH_TID_BASE(x) (((x) >> S_HASH_TID_BASE) & M_HASH_TID_BASE)
39553 
39554 #define A_LE_PERR_INJECT 0x19dfc
39555 
39556 #define S_LEMEMSEL    1
39557 #define M_LEMEMSEL    0x7U
39558 #define V_LEMEMSEL(x) ((x) << S_LEMEMSEL)
39559 #define G_LEMEMSEL(x) (((x) >> S_LEMEMSEL) & M_LEMEMSEL)
39560 
39561 #define A_LE_DB_SSRAM_TID_BASE 0x19dfc
39562 
39563 #define S_SSRAM_TID_BASE    0
39564 #define M_SSRAM_TID_BASE    0xfffffU
39565 #define V_SSRAM_TID_BASE(x) ((x) << S_SSRAM_TID_BASE)
39566 #define G_SSRAM_TID_BASE(x) (((x) >> S_SSRAM_TID_BASE) & M_SSRAM_TID_BASE)
39567 
39568 #define A_LE_DB_ACTIVE_MASK_IPV4 0x19e00
39569 #define A_LE_T5_DB_ACTIVE_MASK_IPV4 0x19e00
39570 #define A_LE_DB_ACTIVE_MASK_IPV6 0x19e50
39571 #define A_LE_HASH_MASK_GEN_IPV4 0x19ea0
39572 #define A_LE_HASH_MASK_GEN_IPV4T5 0x19ea0
39573 #define A_LE_HASH_MASK_GEN_IPV6 0x19eb0
39574 #define A_LE_HASH_MASK_GEN_IPV6T5 0x19eb4
39575 #define A_T6_LE_HASH_MASK_GEN_IPV6T5 0x19ec4
39576 #define A_LE_HASH_MASK_CMP_IPV4 0x19ee0
39577 #define A_LE_HASH_MASK_CMP_IPV4T5 0x19ee4
39578 #define A_LE_DB_PSV_FILTER_MASK_TUP_IPV4 0x19ee4
39579 #define A_LE_HASH_MASK_CMP_IPV6 0x19ef0
39580 #define A_LE_DB_PSV_FILTER_MASK_FLT_IPV4 0x19ef0
39581 #define A_LE_HASH_MASK_CMP_IPV6T5 0x19ef8
39582 #define A_LE_DB_PSV_FILTER_MASK_TUP_IPV6 0x19f04
39583 #define A_LE_DEBUG_LA_CONFIG 0x19f20
39584 #define A_LE_REQ_DEBUG_LA_DATA 0x19f24
39585 #define A_LE_REQ_DEBUG_LA_WRPTR 0x19f28
39586 #define A_LE_DB_PSV_FILTER_MASK_FLT_IPV6 0x19f28
39587 #define A_LE_RSP_DEBUG_LA_DATA 0x19f2c
39588 #define A_LE_RSP_DEBUG_LA_WRPTR 0x19f30
39589 #define A_LE_DEBUG_LA_SELECTOR 0x19f34
39590 #define A_LE_SRVR_SRAM_INIT 0x19f34
39591 
39592 #define S_SRVRSRAMBASE    2
39593 #define M_SRVRSRAMBASE    0xfffffU
39594 #define V_SRVRSRAMBASE(x) ((x) << S_SRVRSRAMBASE)
39595 #define G_SRVRSRAMBASE(x) (((x) >> S_SRVRSRAMBASE) & M_SRVRSRAMBASE)
39596 
39597 #define S_SRVRINITBUSY    1
39598 #define V_SRVRINITBUSY(x) ((x) << S_SRVRINITBUSY)
39599 #define F_SRVRINITBUSY    V_SRVRINITBUSY(1U)
39600 
39601 #define S_SRVRINIT    0
39602 #define V_SRVRINIT(x) ((x) << S_SRVRINIT)
39603 #define F_SRVRINIT    V_SRVRINIT(1U)
39604 
39605 #define A_LE_DB_SRVR_SRAM_CONFIG 0x19f34
39606 
39607 #define S_PRI_HFILT    4
39608 #define V_PRI_HFILT(x) ((x) << S_PRI_HFILT)
39609 #define F_PRI_HFILT    V_PRI_HFILT(1U)
39610 
39611 #define S_PRI_SRVR    3
39612 #define V_PRI_SRVR(x) ((x) << S_PRI_SRVR)
39613 #define F_PRI_SRVR    V_PRI_SRVR(1U)
39614 
39615 #define S_PRI_FILT    2
39616 #define V_PRI_FILT(x) ((x) << S_PRI_FILT)
39617 #define F_PRI_FILT    V_PRI_FILT(1U)
39618 
39619 #define A_LE_DEBUG_LA_CAPTURED_DATA 0x19f38
39620 #define A_LE_SRVR_VF_SRCH_TABLE 0x19f38
39621 
39622 #define S_RDWR    21
39623 #define V_RDWR(x) ((x) << S_RDWR)
39624 #define F_RDWR    V_RDWR(1U)
39625 
39626 #define S_VFINDEX    14
39627 #define M_VFINDEX    0x7fU
39628 #define V_VFINDEX(x) ((x) << S_VFINDEX)
39629 #define G_VFINDEX(x) (((x) >> S_VFINDEX) & M_VFINDEX)
39630 
39631 #define S_SRCHHADDR    7
39632 #define M_SRCHHADDR    0x7fU
39633 #define V_SRCHHADDR(x) ((x) << S_SRCHHADDR)
39634 #define G_SRCHHADDR(x) (((x) >> S_SRCHHADDR) & M_SRCHHADDR)
39635 
39636 #define S_SRCHLADDR    0
39637 #define M_SRCHLADDR    0x7fU
39638 #define V_SRCHLADDR(x) ((x) << S_SRCHLADDR)
39639 #define G_SRCHLADDR(x) (((x) >> S_SRCHLADDR) & M_SRCHLADDR)
39640 
39641 #define A_LE_DB_SRVR_VF_SRCH_TABLE_CTRL 0x19f38
39642 
39643 #define S_VFLUTBUSY    10
39644 #define V_VFLUTBUSY(x) ((x) << S_VFLUTBUSY)
39645 #define F_VFLUTBUSY    V_VFLUTBUSY(1U)
39646 
39647 #define S_VFLUTSTART    9
39648 #define V_VFLUTSTART(x) ((x) << S_VFLUTSTART)
39649 #define F_VFLUTSTART    V_VFLUTSTART(1U)
39650 
39651 #define S_T6_RDWR    8
39652 #define V_T6_RDWR(x) ((x) << S_T6_RDWR)
39653 #define F_T6_RDWR    V_T6_RDWR(1U)
39654 
39655 #define S_T6_VFINDEX    0
39656 #define M_T6_VFINDEX    0xffU
39657 #define V_T6_VFINDEX(x) ((x) << S_T6_VFINDEX)
39658 #define G_T6_VFINDEX(x) (((x) >> S_T6_VFINDEX) & M_T6_VFINDEX)
39659 
39660 #define A_LE_MA_DEBUG_LA_DATA 0x19f3c
39661 #define A_LE_DB_SRVR_VF_SRCH_TABLE_DATA 0x19f3c
39662 
39663 #define S_T6_SRCHHADDR    12
39664 #define M_T6_SRCHHADDR    0xfffU
39665 #define V_T6_SRCHHADDR(x) ((x) << S_T6_SRCHHADDR)
39666 #define G_T6_SRCHHADDR(x) (((x) >> S_T6_SRCHHADDR) & M_T6_SRCHHADDR)
39667 
39668 #define S_T6_SRCHLADDR    0
39669 #define M_T6_SRCHLADDR    0xfffU
39670 #define V_T6_SRCHLADDR(x) ((x) << S_T6_SRCHLADDR)
39671 #define G_T6_SRCHLADDR(x) (((x) >> S_T6_SRCHLADDR) & M_T6_SRCHLADDR)
39672 
39673 #define A_LE_RSP_DEBUG_LA_HASH_WRPTR 0x19f40
39674 #define A_LE_DB_SECOND_ACTIVE_MASK_IPV4 0x19f40
39675 #define A_LE_HASH_DEBUG_LA_DATA 0x19f44
39676 #define A_LE_RSP_DEBUG_LA_TCAM_WRPTR 0x19f48
39677 #define A_LE_TCAM_DEBUG_LA_DATA 0x19f4c
39678 #define A_LE_DB_SECOND_GEN_HASH_MASK_IPV4 0x19f90
39679 #define A_LE_DB_SECOND_CMP_HASH_MASK_IPV4 0x19fa4
39680 #define A_LE_HASH_COLLISION 0x19fc4
39681 #define A_LE_GLOBAL_COLLISION 0x19fc8
39682 #define A_LE_FULL_CNT_COLLISION 0x19fcc
39683 #define A_LE_DEBUG_LA_CONFIGT5 0x19fd0
39684 #define A_LE_REQ_DEBUG_LA_DATAT5 0x19fd4
39685 #define A_LE_REQ_DEBUG_LA_WRPTRT5 0x19fd8
39686 #define A_LE_RSP_DEBUG_LA_DATAT5 0x19fdc
39687 #define A_LE_RSP_DEBUG_LA_WRPTRT5 0x19fe0
39688 #define A_LE_DEBUG_LA_SEL_DATA 0x19fe4
39689 
39690 /* registers for module NCSI */
39691 #define NCSI_BASE_ADDR 0x1a000
39692 
39693 #define A_NCSI_PORT_CFGREG 0x1a000
39694 
39695 #define S_WIREEN    28
39696 #define M_WIREEN    0xfU
39697 #define V_WIREEN(x) ((x) << S_WIREEN)
39698 #define G_WIREEN(x) (((x) >> S_WIREEN) & M_WIREEN)
39699 
39700 #define S_STRP_CRC    24
39701 #define M_STRP_CRC    0xfU
39702 #define V_STRP_CRC(x) ((x) << S_STRP_CRC)
39703 #define G_STRP_CRC(x) (((x) >> S_STRP_CRC) & M_STRP_CRC)
39704 
39705 #define S_RX_HALT    22
39706 #define V_RX_HALT(x) ((x) << S_RX_HALT)
39707 #define F_RX_HALT    V_RX_HALT(1U)
39708 
39709 #define S_FLUSH_RX_FIFO    21
39710 #define V_FLUSH_RX_FIFO(x) ((x) << S_FLUSH_RX_FIFO)
39711 #define F_FLUSH_RX_FIFO    V_FLUSH_RX_FIFO(1U)
39712 
39713 #define S_HW_ARB_EN    20
39714 #define V_HW_ARB_EN(x) ((x) << S_HW_ARB_EN)
39715 #define F_HW_ARB_EN    V_HW_ARB_EN(1U)
39716 
39717 #define S_SOFT_PKG_SEL    19
39718 #define V_SOFT_PKG_SEL(x) ((x) << S_SOFT_PKG_SEL)
39719 #define F_SOFT_PKG_SEL    V_SOFT_PKG_SEL(1U)
39720 
39721 #define S_ERR_DISCARD_EN    18
39722 #define V_ERR_DISCARD_EN(x) ((x) << S_ERR_DISCARD_EN)
39723 #define F_ERR_DISCARD_EN    V_ERR_DISCARD_EN(1U)
39724 
39725 #define S_MAX_PKT_SIZE    4
39726 #define M_MAX_PKT_SIZE    0x3fffU
39727 #define V_MAX_PKT_SIZE(x) ((x) << S_MAX_PKT_SIZE)
39728 #define G_MAX_PKT_SIZE(x) (((x) >> S_MAX_PKT_SIZE) & M_MAX_PKT_SIZE)
39729 
39730 #define S_RX_BYTE_SWAP    3
39731 #define V_RX_BYTE_SWAP(x) ((x) << S_RX_BYTE_SWAP)
39732 #define F_RX_BYTE_SWAP    V_RX_BYTE_SWAP(1U)
39733 
39734 #define S_TX_BYTE_SWAP    2
39735 #define V_TX_BYTE_SWAP(x) ((x) << S_TX_BYTE_SWAP)
39736 #define F_TX_BYTE_SWAP    V_TX_BYTE_SWAP(1U)
39737 
39738 #define A_NCSI_RST_CTRL 0x1a004
39739 
39740 #define S_MAC_REF_RST    2
39741 #define V_MAC_REF_RST(x) ((x) << S_MAC_REF_RST)
39742 #define F_MAC_REF_RST    V_MAC_REF_RST(1U)
39743 
39744 #define S_MAC_RX_RST    1
39745 #define V_MAC_RX_RST(x) ((x) << S_MAC_RX_RST)
39746 #define F_MAC_RX_RST    V_MAC_RX_RST(1U)
39747 
39748 #define S_MAC_TX_RST    0
39749 #define V_MAC_TX_RST(x) ((x) << S_MAC_TX_RST)
39750 #define F_MAC_TX_RST    V_MAC_TX_RST(1U)
39751 
39752 #define A_NCSI_CH0_SADDR_LOW 0x1a010
39753 #define A_NCSI_CH0_SADDR_HIGH 0x1a014
39754 
39755 #define S_CHO_SADDR_EN    31
39756 #define V_CHO_SADDR_EN(x) ((x) << S_CHO_SADDR_EN)
39757 #define F_CHO_SADDR_EN    V_CHO_SADDR_EN(1U)
39758 
39759 #define S_CH0_SADDR_HIGH    0
39760 #define M_CH0_SADDR_HIGH    0xffffU
39761 #define V_CH0_SADDR_HIGH(x) ((x) << S_CH0_SADDR_HIGH)
39762 #define G_CH0_SADDR_HIGH(x) (((x) >> S_CH0_SADDR_HIGH) & M_CH0_SADDR_HIGH)
39763 
39764 #define A_NCSI_CH1_SADDR_LOW 0x1a018
39765 #define A_NCSI_CH1_SADDR_HIGH 0x1a01c
39766 
39767 #define S_CH1_SADDR_EN    31
39768 #define V_CH1_SADDR_EN(x) ((x) << S_CH1_SADDR_EN)
39769 #define F_CH1_SADDR_EN    V_CH1_SADDR_EN(1U)
39770 
39771 #define S_CH1_SADDR_HIGH    0
39772 #define M_CH1_SADDR_HIGH    0xffffU
39773 #define V_CH1_SADDR_HIGH(x) ((x) << S_CH1_SADDR_HIGH)
39774 #define G_CH1_SADDR_HIGH(x) (((x) >> S_CH1_SADDR_HIGH) & M_CH1_SADDR_HIGH)
39775 
39776 #define A_NCSI_CH2_SADDR_LOW 0x1a020
39777 #define A_NCSI_CH2_SADDR_HIGH 0x1a024
39778 
39779 #define S_CH2_SADDR_EN    31
39780 #define V_CH2_SADDR_EN(x) ((x) << S_CH2_SADDR_EN)
39781 #define F_CH2_SADDR_EN    V_CH2_SADDR_EN(1U)
39782 
39783 #define S_CH2_SADDR_HIGH    0
39784 #define M_CH2_SADDR_HIGH    0xffffU
39785 #define V_CH2_SADDR_HIGH(x) ((x) << S_CH2_SADDR_HIGH)
39786 #define G_CH2_SADDR_HIGH(x) (((x) >> S_CH2_SADDR_HIGH) & M_CH2_SADDR_HIGH)
39787 
39788 #define A_NCSI_CH3_SADDR_LOW 0x1a028
39789 #define A_NCSI_CH3_SADDR_HIGH 0x1a02c
39790 
39791 #define S_CH3_SADDR_EN    31
39792 #define V_CH3_SADDR_EN(x) ((x) << S_CH3_SADDR_EN)
39793 #define F_CH3_SADDR_EN    V_CH3_SADDR_EN(1U)
39794 
39795 #define S_CH3_SADDR_HIGH    0
39796 #define M_CH3_SADDR_HIGH    0xffffU
39797 #define V_CH3_SADDR_HIGH(x) ((x) << S_CH3_SADDR_HIGH)
39798 #define G_CH3_SADDR_HIGH(x) (((x) >> S_CH3_SADDR_HIGH) & M_CH3_SADDR_HIGH)
39799 
39800 #define A_NCSI_WORK_REQHDR_0 0x1a030
39801 #define A_NCSI_WORK_REQHDR_1 0x1a034
39802 #define A_NCSI_WORK_REQHDR_2 0x1a038
39803 #define A_NCSI_WORK_REQHDR_3 0x1a03c
39804 #define A_NCSI_MPS_HDR_LO 0x1a040
39805 #define A_NCSI_MPS_HDR_HI 0x1a044
39806 #define A_NCSI_CTL 0x1a048
39807 
39808 #define S_STRIP_OVLAN    3
39809 #define V_STRIP_OVLAN(x) ((x) << S_STRIP_OVLAN)
39810 #define F_STRIP_OVLAN    V_STRIP_OVLAN(1U)
39811 
39812 #define S_BMC_DROP_NON_BC    2
39813 #define V_BMC_DROP_NON_BC(x) ((x) << S_BMC_DROP_NON_BC)
39814 #define F_BMC_DROP_NON_BC    V_BMC_DROP_NON_BC(1U)
39815 
39816 #define S_BMC_RX_FWD_ALL    1
39817 #define V_BMC_RX_FWD_ALL(x) ((x) << S_BMC_RX_FWD_ALL)
39818 #define F_BMC_RX_FWD_ALL    V_BMC_RX_FWD_ALL(1U)
39819 
39820 #define S_FWD_BMC    0
39821 #define V_FWD_BMC(x) ((x) << S_FWD_BMC)
39822 #define F_FWD_BMC    V_FWD_BMC(1U)
39823 
39824 #define A_NCSI_NCSI_ETYPE 0x1a04c
39825 
39826 #define S_NCSI_ETHERTYPE    0
39827 #define M_NCSI_ETHERTYPE    0xffffU
39828 #define V_NCSI_ETHERTYPE(x) ((x) << S_NCSI_ETHERTYPE)
39829 #define G_NCSI_ETHERTYPE(x) (((x) >> S_NCSI_ETHERTYPE) & M_NCSI_ETHERTYPE)
39830 
39831 #define A_NCSI_RX_FIFO_CNT 0x1a050
39832 
39833 #define S_NCSI_RXFIFO_CNT    0
39834 #define M_NCSI_RXFIFO_CNT    0x7ffU
39835 #define V_NCSI_RXFIFO_CNT(x) ((x) << S_NCSI_RXFIFO_CNT)
39836 #define G_NCSI_RXFIFO_CNT(x) (((x) >> S_NCSI_RXFIFO_CNT) & M_NCSI_RXFIFO_CNT)
39837 
39838 #define A_NCSI_RX_ERR_CNT 0x1a054
39839 #define A_NCSI_RX_OF_CNT 0x1a058
39840 #define A_NCSI_RX_MS_CNT 0x1a05c
39841 #define A_NCSI_RX_IE_CNT 0x1a060
39842 #define A_NCSI_MPS_DEMUX_CNT 0x1a064
39843 
39844 #define S_MPS2CIM_CNT    16
39845 #define M_MPS2CIM_CNT    0x1ffU
39846 #define V_MPS2CIM_CNT(x) ((x) << S_MPS2CIM_CNT)
39847 #define G_MPS2CIM_CNT(x) (((x) >> S_MPS2CIM_CNT) & M_MPS2CIM_CNT)
39848 
39849 #define S_MPS2BMC_CNT    0
39850 #define M_MPS2BMC_CNT    0x1ffU
39851 #define V_MPS2BMC_CNT(x) ((x) << S_MPS2BMC_CNT)
39852 #define G_MPS2BMC_CNT(x) (((x) >> S_MPS2BMC_CNT) & M_MPS2BMC_CNT)
39853 
39854 #define A_NCSI_CIM_DEMUX_CNT 0x1a068
39855 
39856 #define S_CIM2MPS_CNT    16
39857 #define M_CIM2MPS_CNT    0x1ffU
39858 #define V_CIM2MPS_CNT(x) ((x) << S_CIM2MPS_CNT)
39859 #define G_CIM2MPS_CNT(x) (((x) >> S_CIM2MPS_CNT) & M_CIM2MPS_CNT)
39860 
39861 #define S_CIM2BMC_CNT    0
39862 #define M_CIM2BMC_CNT    0x1ffU
39863 #define V_CIM2BMC_CNT(x) ((x) << S_CIM2BMC_CNT)
39864 #define G_CIM2BMC_CNT(x) (((x) >> S_CIM2BMC_CNT) & M_CIM2BMC_CNT)
39865 
39866 #define A_NCSI_TX_FIFO_CNT 0x1a06c
39867 
39868 #define S_TX_FIFO_CNT    0
39869 #define M_TX_FIFO_CNT    0x3ffU
39870 #define V_TX_FIFO_CNT(x) ((x) << S_TX_FIFO_CNT)
39871 #define G_TX_FIFO_CNT(x) (((x) >> S_TX_FIFO_CNT) & M_TX_FIFO_CNT)
39872 
39873 #define A_NCSI_SE_CNT_CTL 0x1a0b0
39874 
39875 #define S_SE_CNT_CLR    0
39876 #define M_SE_CNT_CLR    0xfU
39877 #define V_SE_CNT_CLR(x) ((x) << S_SE_CNT_CLR)
39878 #define G_SE_CNT_CLR(x) (((x) >> S_SE_CNT_CLR) & M_SE_CNT_CLR)
39879 
39880 #define A_NCSI_SE_CNT_MPS 0x1a0b4
39881 
39882 #define S_NC2MPS_SOP_CNT    24
39883 #define M_NC2MPS_SOP_CNT    0xffU
39884 #define V_NC2MPS_SOP_CNT(x) ((x) << S_NC2MPS_SOP_CNT)
39885 #define G_NC2MPS_SOP_CNT(x) (((x) >> S_NC2MPS_SOP_CNT) & M_NC2MPS_SOP_CNT)
39886 
39887 #define S_NC2MPS_EOP_CNT    16
39888 #define M_NC2MPS_EOP_CNT    0x3fU
39889 #define V_NC2MPS_EOP_CNT(x) ((x) << S_NC2MPS_EOP_CNT)
39890 #define G_NC2MPS_EOP_CNT(x) (((x) >> S_NC2MPS_EOP_CNT) & M_NC2MPS_EOP_CNT)
39891 
39892 #define S_MPS2NC_SOP_CNT    8
39893 #define M_MPS2NC_SOP_CNT    0xffU
39894 #define V_MPS2NC_SOP_CNT(x) ((x) << S_MPS2NC_SOP_CNT)
39895 #define G_MPS2NC_SOP_CNT(x) (((x) >> S_MPS2NC_SOP_CNT) & M_MPS2NC_SOP_CNT)
39896 
39897 #define S_MPS2NC_EOP_CNT    0
39898 #define M_MPS2NC_EOP_CNT    0xffU
39899 #define V_MPS2NC_EOP_CNT(x) ((x) << S_MPS2NC_EOP_CNT)
39900 #define G_MPS2NC_EOP_CNT(x) (((x) >> S_MPS2NC_EOP_CNT) & M_MPS2NC_EOP_CNT)
39901 
39902 #define A_NCSI_SE_CNT_CIM 0x1a0b8
39903 
39904 #define S_NC2CIM_SOP_CNT    24
39905 #define M_NC2CIM_SOP_CNT    0xffU
39906 #define V_NC2CIM_SOP_CNT(x) ((x) << S_NC2CIM_SOP_CNT)
39907 #define G_NC2CIM_SOP_CNT(x) (((x) >> S_NC2CIM_SOP_CNT) & M_NC2CIM_SOP_CNT)
39908 
39909 #define S_NC2CIM_EOP_CNT    16
39910 #define M_NC2CIM_EOP_CNT    0x3fU
39911 #define V_NC2CIM_EOP_CNT(x) ((x) << S_NC2CIM_EOP_CNT)
39912 #define G_NC2CIM_EOP_CNT(x) (((x) >> S_NC2CIM_EOP_CNT) & M_NC2CIM_EOP_CNT)
39913 
39914 #define S_CIM2NC_SOP_CNT    8
39915 #define M_CIM2NC_SOP_CNT    0xffU
39916 #define V_CIM2NC_SOP_CNT(x) ((x) << S_CIM2NC_SOP_CNT)
39917 #define G_CIM2NC_SOP_CNT(x) (((x) >> S_CIM2NC_SOP_CNT) & M_CIM2NC_SOP_CNT)
39918 
39919 #define S_CIM2NC_EOP_CNT    0
39920 #define M_CIM2NC_EOP_CNT    0xffU
39921 #define V_CIM2NC_EOP_CNT(x) ((x) << S_CIM2NC_EOP_CNT)
39922 #define G_CIM2NC_EOP_CNT(x) (((x) >> S_CIM2NC_EOP_CNT) & M_CIM2NC_EOP_CNT)
39923 
39924 #define A_NCSI_BUS_DEBUG 0x1a0bc
39925 
39926 #define S_SOP_CNT_ERR    12
39927 #define M_SOP_CNT_ERR    0xfU
39928 #define V_SOP_CNT_ERR(x) ((x) << S_SOP_CNT_ERR)
39929 #define G_SOP_CNT_ERR(x) (((x) >> S_SOP_CNT_ERR) & M_SOP_CNT_ERR)
39930 
39931 #define S_BUS_STATE_MPS_OUT    6
39932 #define M_BUS_STATE_MPS_OUT    0x3U
39933 #define V_BUS_STATE_MPS_OUT(x) ((x) << S_BUS_STATE_MPS_OUT)
39934 #define G_BUS_STATE_MPS_OUT(x) (((x) >> S_BUS_STATE_MPS_OUT) & M_BUS_STATE_MPS_OUT)
39935 
39936 #define S_BUS_STATE_MPS_IN    4
39937 #define M_BUS_STATE_MPS_IN    0x3U
39938 #define V_BUS_STATE_MPS_IN(x) ((x) << S_BUS_STATE_MPS_IN)
39939 #define G_BUS_STATE_MPS_IN(x) (((x) >> S_BUS_STATE_MPS_IN) & M_BUS_STATE_MPS_IN)
39940 
39941 #define S_BUS_STATE_CIM_OUT    2
39942 #define M_BUS_STATE_CIM_OUT    0x3U
39943 #define V_BUS_STATE_CIM_OUT(x) ((x) << S_BUS_STATE_CIM_OUT)
39944 #define G_BUS_STATE_CIM_OUT(x) (((x) >> S_BUS_STATE_CIM_OUT) & M_BUS_STATE_CIM_OUT)
39945 
39946 #define S_BUS_STATE_CIM_IN    0
39947 #define M_BUS_STATE_CIM_IN    0x3U
39948 #define V_BUS_STATE_CIM_IN(x) ((x) << S_BUS_STATE_CIM_IN)
39949 #define G_BUS_STATE_CIM_IN(x) (((x) >> S_BUS_STATE_CIM_IN) & M_BUS_STATE_CIM_IN)
39950 
39951 #define A_NCSI_LA_RDPTR 0x1a0c0
39952 #define A_NCSI_LA_RDDATA 0x1a0c4
39953 #define A_NCSI_LA_WRPTR 0x1a0c8
39954 #define A_NCSI_LA_RESERVED 0x1a0cc
39955 #define A_NCSI_LA_CTL 0x1a0d0
39956 #define A_NCSI_INT_ENABLE 0x1a0d4
39957 
39958 #define S_CIM_DM_PRTY_ERR    8
39959 #define V_CIM_DM_PRTY_ERR(x) ((x) << S_CIM_DM_PRTY_ERR)
39960 #define F_CIM_DM_PRTY_ERR    V_CIM_DM_PRTY_ERR(1U)
39961 
39962 #define S_MPS_DM_PRTY_ERR    7
39963 #define V_MPS_DM_PRTY_ERR(x) ((x) << S_MPS_DM_PRTY_ERR)
39964 #define F_MPS_DM_PRTY_ERR    V_MPS_DM_PRTY_ERR(1U)
39965 
39966 #define S_TOKEN    6
39967 #define V_TOKEN(x) ((x) << S_TOKEN)
39968 #define F_TOKEN    V_TOKEN(1U)
39969 
39970 #define S_ARB_DONE    5
39971 #define V_ARB_DONE(x) ((x) << S_ARB_DONE)
39972 #define F_ARB_DONE    V_ARB_DONE(1U)
39973 
39974 #define S_ARB_STARTED    4
39975 #define V_ARB_STARTED(x) ((x) << S_ARB_STARTED)
39976 #define F_ARB_STARTED    V_ARB_STARTED(1U)
39977 
39978 #define S_WOL    3
39979 #define V_WOL(x) ((x) << S_WOL)
39980 #define F_WOL    V_WOL(1U)
39981 
39982 #define S_MACINT    2
39983 #define V_MACINT(x) ((x) << S_MACINT)
39984 #define F_MACINT    V_MACINT(1U)
39985 
39986 #define S_TXFIFO_PRTY_ERR    1
39987 #define V_TXFIFO_PRTY_ERR(x) ((x) << S_TXFIFO_PRTY_ERR)
39988 #define F_TXFIFO_PRTY_ERR    V_TXFIFO_PRTY_ERR(1U)
39989 
39990 #define S_RXFIFO_PRTY_ERR    0
39991 #define V_RXFIFO_PRTY_ERR(x) ((x) << S_RXFIFO_PRTY_ERR)
39992 #define F_RXFIFO_PRTY_ERR    V_RXFIFO_PRTY_ERR(1U)
39993 
39994 #define A_NCSI_INT_CAUSE 0x1a0d8
39995 #define A_NCSI_STATUS 0x1a0dc
39996 
39997 #define S_MASTER    1
39998 #define V_MASTER(x) ((x) << S_MASTER)
39999 #define F_MASTER    V_MASTER(1U)
40000 
40001 #define S_ARB_STATUS    0
40002 #define V_ARB_STATUS(x) ((x) << S_ARB_STATUS)
40003 #define F_ARB_STATUS    V_ARB_STATUS(1U)
40004 
40005 #define A_NCSI_PAUSE_CTRL 0x1a0e0
40006 
40007 #define S_FORCEPAUSE    0
40008 #define V_FORCEPAUSE(x) ((x) << S_FORCEPAUSE)
40009 #define F_FORCEPAUSE    V_FORCEPAUSE(1U)
40010 
40011 #define A_NCSI_PAUSE_TIMEOUT 0x1a0e4
40012 #define A_NCSI_PAUSE_WM 0x1a0ec
40013 
40014 #define S_PAUSEHWM    16
40015 #define M_PAUSEHWM    0x7ffU
40016 #define V_PAUSEHWM(x) ((x) << S_PAUSEHWM)
40017 #define G_PAUSEHWM(x) (((x) >> S_PAUSEHWM) & M_PAUSEHWM)
40018 
40019 #define S_PAUSELWM    0
40020 #define M_PAUSELWM    0x7ffU
40021 #define V_PAUSELWM(x) ((x) << S_PAUSELWM)
40022 #define G_PAUSELWM(x) (((x) >> S_PAUSELWM) & M_PAUSELWM)
40023 
40024 #define A_NCSI_DEBUG 0x1a0f0
40025 
40026 #define S_DEBUGSEL    0
40027 #define M_DEBUGSEL    0x3fU
40028 #define V_DEBUGSEL(x) ((x) << S_DEBUGSEL)
40029 #define G_DEBUGSEL(x) (((x) >> S_DEBUGSEL) & M_DEBUGSEL)
40030 
40031 #define S_TXFIFO_EMPTY    4
40032 #define V_TXFIFO_EMPTY(x) ((x) << S_TXFIFO_EMPTY)
40033 #define F_TXFIFO_EMPTY    V_TXFIFO_EMPTY(1U)
40034 
40035 #define S_TXFIFO_FULL    3
40036 #define V_TXFIFO_FULL(x) ((x) << S_TXFIFO_FULL)
40037 #define F_TXFIFO_FULL    V_TXFIFO_FULL(1U)
40038 
40039 #define S_PKG_ID    0
40040 #define M_PKG_ID    0x7U
40041 #define V_PKG_ID(x) ((x) << S_PKG_ID)
40042 #define G_PKG_ID(x) (((x) >> S_PKG_ID) & M_PKG_ID)
40043 
40044 #define A_NCSI_PERR_INJECT 0x1a0f4
40045 
40046 #define S_MCSIMELSEL    1
40047 #define V_MCSIMELSEL(x) ((x) << S_MCSIMELSEL)
40048 #define F_MCSIMELSEL    V_MCSIMELSEL(1U)
40049 
40050 #define A_NCSI_PERR_ENABLE 0x1a0f8
40051 #define A_NCSI_MACB_NETWORK_CTRL 0x1a100
40052 
40053 #define S_TXSNDZEROPAUSE    12
40054 #define V_TXSNDZEROPAUSE(x) ((x) << S_TXSNDZEROPAUSE)
40055 #define F_TXSNDZEROPAUSE    V_TXSNDZEROPAUSE(1U)
40056 
40057 #define S_TXSNDPAUSE    11
40058 #define V_TXSNDPAUSE(x) ((x) << S_TXSNDPAUSE)
40059 #define F_TXSNDPAUSE    V_TXSNDPAUSE(1U)
40060 
40061 #define S_TXSTOP    10
40062 #define V_TXSTOP(x) ((x) << S_TXSTOP)
40063 #define F_TXSTOP    V_TXSTOP(1U)
40064 
40065 #define S_TXSTART    9
40066 #define V_TXSTART(x) ((x) << S_TXSTART)
40067 #define F_TXSTART    V_TXSTART(1U)
40068 
40069 #define S_BACKPRESS    8
40070 #define V_BACKPRESS(x) ((x) << S_BACKPRESS)
40071 #define F_BACKPRESS    V_BACKPRESS(1U)
40072 
40073 #define S_STATWREN    7
40074 #define V_STATWREN(x) ((x) << S_STATWREN)
40075 #define F_STATWREN    V_STATWREN(1U)
40076 
40077 #define S_INCRSTAT    6
40078 #define V_INCRSTAT(x) ((x) << S_INCRSTAT)
40079 #define F_INCRSTAT    V_INCRSTAT(1U)
40080 
40081 #define S_CLEARSTAT    5
40082 #define V_CLEARSTAT(x) ((x) << S_CLEARSTAT)
40083 #define F_CLEARSTAT    V_CLEARSTAT(1U)
40084 
40085 #define S_ENMGMTPORT    4
40086 #define V_ENMGMTPORT(x) ((x) << S_ENMGMTPORT)
40087 #define F_ENMGMTPORT    V_ENMGMTPORT(1U)
40088 
40089 #define S_NCSITXEN    3
40090 #define V_NCSITXEN(x) ((x) << S_NCSITXEN)
40091 #define F_NCSITXEN    V_NCSITXEN(1U)
40092 
40093 #define S_NCSIRXEN    2
40094 #define V_NCSIRXEN(x) ((x) << S_NCSIRXEN)
40095 #define F_NCSIRXEN    V_NCSIRXEN(1U)
40096 
40097 #define S_LOOPLOCAL    1
40098 #define V_LOOPLOCAL(x) ((x) << S_LOOPLOCAL)
40099 #define F_LOOPLOCAL    V_LOOPLOCAL(1U)
40100 
40101 #define S_LOOPPHY    0
40102 #define V_LOOPPHY(x) ((x) << S_LOOPPHY)
40103 #define F_LOOPPHY    V_LOOPPHY(1U)
40104 
40105 #define A_NCSI_MACB_NETWORK_CFG 0x1a104
40106 
40107 #define S_PCLKDIV128    22
40108 #define V_PCLKDIV128(x) ((x) << S_PCLKDIV128)
40109 #define F_PCLKDIV128    V_PCLKDIV128(1U)
40110 
40111 #define S_COPYPAUSE    21
40112 #define V_COPYPAUSE(x) ((x) << S_COPYPAUSE)
40113 #define F_COPYPAUSE    V_COPYPAUSE(1U)
40114 
40115 #define S_NONSTDPREOK    20
40116 #define V_NONSTDPREOK(x) ((x) << S_NONSTDPREOK)
40117 #define F_NONSTDPREOK    V_NONSTDPREOK(1U)
40118 
40119 #define S_NOFCS    19
40120 #define V_NOFCS(x) ((x) << S_NOFCS)
40121 #define F_NOFCS    V_NOFCS(1U)
40122 
40123 #define S_RXENHALFDUP    18
40124 #define V_RXENHALFDUP(x) ((x) << S_RXENHALFDUP)
40125 #define F_RXENHALFDUP    V_RXENHALFDUP(1U)
40126 
40127 #define S_NOCOPYFCS    17
40128 #define V_NOCOPYFCS(x) ((x) << S_NOCOPYFCS)
40129 #define F_NOCOPYFCS    V_NOCOPYFCS(1U)
40130 
40131 #define S_LENCHKEN    16
40132 #define V_LENCHKEN(x) ((x) << S_LENCHKEN)
40133 #define F_LENCHKEN    V_LENCHKEN(1U)
40134 
40135 #define S_RXBUFOFFSET    14
40136 #define M_RXBUFOFFSET    0x3U
40137 #define V_RXBUFOFFSET(x) ((x) << S_RXBUFOFFSET)
40138 #define G_RXBUFOFFSET(x) (((x) >> S_RXBUFOFFSET) & M_RXBUFOFFSET)
40139 
40140 #define S_PAUSEEN    13
40141 #define V_PAUSEEN(x) ((x) << S_PAUSEEN)
40142 #define F_PAUSEEN    V_PAUSEEN(1U)
40143 
40144 #define S_RETRYTEST    12
40145 #define V_RETRYTEST(x) ((x) << S_RETRYTEST)
40146 #define F_RETRYTEST    V_RETRYTEST(1U)
40147 
40148 #define S_PCLKDIV    10
40149 #define M_PCLKDIV    0x3U
40150 #define V_PCLKDIV(x) ((x) << S_PCLKDIV)
40151 #define G_PCLKDIV(x) (((x) >> S_PCLKDIV) & M_PCLKDIV)
40152 
40153 #define S_EXTCLASS    9
40154 #define V_EXTCLASS(x) ((x) << S_EXTCLASS)
40155 #define F_EXTCLASS    V_EXTCLASS(1U)
40156 
40157 #define S_EN1536FRAME    8
40158 #define V_EN1536FRAME(x) ((x) << S_EN1536FRAME)
40159 #define F_EN1536FRAME    V_EN1536FRAME(1U)
40160 
40161 #define S_UCASTHASHEN    7
40162 #define V_UCASTHASHEN(x) ((x) << S_UCASTHASHEN)
40163 #define F_UCASTHASHEN    V_UCASTHASHEN(1U)
40164 
40165 #define S_MCASTHASHEN    6
40166 #define V_MCASTHASHEN(x) ((x) << S_MCASTHASHEN)
40167 #define F_MCASTHASHEN    V_MCASTHASHEN(1U)
40168 
40169 #define S_RXBCASTDIS    5
40170 #define V_RXBCASTDIS(x) ((x) << S_RXBCASTDIS)
40171 #define F_RXBCASTDIS    V_RXBCASTDIS(1U)
40172 
40173 #define S_NCSICOPYALLFRAMES    4
40174 #define V_NCSICOPYALLFRAMES(x) ((x) << S_NCSICOPYALLFRAMES)
40175 #define F_NCSICOPYALLFRAMES    V_NCSICOPYALLFRAMES(1U)
40176 
40177 #define S_JUMBOEN    3
40178 #define V_JUMBOEN(x) ((x) << S_JUMBOEN)
40179 #define F_JUMBOEN    V_JUMBOEN(1U)
40180 
40181 #define S_SEREN    2
40182 #define V_SEREN(x) ((x) << S_SEREN)
40183 #define F_SEREN    V_SEREN(1U)
40184 
40185 #define S_FULLDUPLEX    1
40186 #define V_FULLDUPLEX(x) ((x) << S_FULLDUPLEX)
40187 #define F_FULLDUPLEX    V_FULLDUPLEX(1U)
40188 
40189 #define S_SPEED    0
40190 #define V_SPEED(x) ((x) << S_SPEED)
40191 #define F_SPEED    V_SPEED(1U)
40192 
40193 #define A_NCSI_MACB_NETWORK_STATUS 0x1a108
40194 
40195 #define S_PHYMGMTSTATUS    2
40196 #define V_PHYMGMTSTATUS(x) ((x) << S_PHYMGMTSTATUS)
40197 #define F_PHYMGMTSTATUS    V_PHYMGMTSTATUS(1U)
40198 
40199 #define S_MDISTATUS    1
40200 #define V_MDISTATUS(x) ((x) << S_MDISTATUS)
40201 #define F_MDISTATUS    V_MDISTATUS(1U)
40202 
40203 #define S_LINKSTATUS    0
40204 #define V_LINKSTATUS(x) ((x) << S_LINKSTATUS)
40205 #define F_LINKSTATUS    V_LINKSTATUS(1U)
40206 
40207 #define A_NCSI_MACB_TX_STATUS 0x1a114
40208 
40209 #define S_UNDERRUNERR    6
40210 #define V_UNDERRUNERR(x) ((x) << S_UNDERRUNERR)
40211 #define F_UNDERRUNERR    V_UNDERRUNERR(1U)
40212 
40213 #define S_TXCOMPLETE    5
40214 #define V_TXCOMPLETE(x) ((x) << S_TXCOMPLETE)
40215 #define F_TXCOMPLETE    V_TXCOMPLETE(1U)
40216 
40217 #define S_BUFFEREXHAUSTED    4
40218 #define V_BUFFEREXHAUSTED(x) ((x) << S_BUFFEREXHAUSTED)
40219 #define F_BUFFEREXHAUSTED    V_BUFFEREXHAUSTED(1U)
40220 
40221 #define S_TXPROGRESS    3
40222 #define V_TXPROGRESS(x) ((x) << S_TXPROGRESS)
40223 #define F_TXPROGRESS    V_TXPROGRESS(1U)
40224 
40225 #define S_RETRYLIMIT    2
40226 #define V_RETRYLIMIT(x) ((x) << S_RETRYLIMIT)
40227 #define F_RETRYLIMIT    V_RETRYLIMIT(1U)
40228 
40229 #define S_COLEVENT    1
40230 #define V_COLEVENT(x) ((x) << S_COLEVENT)
40231 #define F_COLEVENT    V_COLEVENT(1U)
40232 
40233 #define S_USEDBITREAD    0
40234 #define V_USEDBITREAD(x) ((x) << S_USEDBITREAD)
40235 #define F_USEDBITREAD    V_USEDBITREAD(1U)
40236 
40237 #define A_NCSI_MACB_RX_BUF_QPTR 0x1a118
40238 
40239 #define S_RXBUFQPTR    2
40240 #define M_RXBUFQPTR    0x3fffffffU
40241 #define V_RXBUFQPTR(x) ((x) << S_RXBUFQPTR)
40242 #define G_RXBUFQPTR(x) (((x) >> S_RXBUFQPTR) & M_RXBUFQPTR)
40243 
40244 #define A_NCSI_MACB_TX_BUF_QPTR 0x1a11c
40245 
40246 #define S_TXBUFQPTR    2
40247 #define M_TXBUFQPTR    0x3fffffffU
40248 #define V_TXBUFQPTR(x) ((x) << S_TXBUFQPTR)
40249 #define G_TXBUFQPTR(x) (((x) >> S_TXBUFQPTR) & M_TXBUFQPTR)
40250 
40251 #define A_NCSI_MACB_RX_STATUS 0x1a120
40252 
40253 #define S_RXOVERRUNERR    2
40254 #define V_RXOVERRUNERR(x) ((x) << S_RXOVERRUNERR)
40255 #define F_RXOVERRUNERR    V_RXOVERRUNERR(1U)
40256 
40257 #define S_MACB_FRAMERCVD    1
40258 #define V_MACB_FRAMERCVD(x) ((x) << S_MACB_FRAMERCVD)
40259 #define F_MACB_FRAMERCVD    V_MACB_FRAMERCVD(1U)
40260 
40261 #define S_NORXBUF    0
40262 #define V_NORXBUF(x) ((x) << S_NORXBUF)
40263 #define F_NORXBUF    V_NORXBUF(1U)
40264 
40265 #define A_NCSI_MACB_INT_STATUS 0x1a124
40266 
40267 #define S_PAUSETIMEZERO    13
40268 #define V_PAUSETIMEZERO(x) ((x) << S_PAUSETIMEZERO)
40269 #define F_PAUSETIMEZERO    V_PAUSETIMEZERO(1U)
40270 
40271 #define S_PAUSERCVD    12
40272 #define V_PAUSERCVD(x) ((x) << S_PAUSERCVD)
40273 #define F_PAUSERCVD    V_PAUSERCVD(1U)
40274 
40275 #define S_HRESPNOTOK    11
40276 #define V_HRESPNOTOK(x) ((x) << S_HRESPNOTOK)
40277 #define F_HRESPNOTOK    V_HRESPNOTOK(1U)
40278 
40279 #define S_RXOVERRUN    10
40280 #define V_RXOVERRUN(x) ((x) << S_RXOVERRUN)
40281 #define F_RXOVERRUN    V_RXOVERRUN(1U)
40282 
40283 #define S_LINKCHANGE    9
40284 #define V_LINKCHANGE(x) ((x) << S_LINKCHANGE)
40285 #define F_LINKCHANGE    V_LINKCHANGE(1U)
40286 
40287 #define S_INT_TXCOMPLETE    7
40288 #define V_INT_TXCOMPLETE(x) ((x) << S_INT_TXCOMPLETE)
40289 #define F_INT_TXCOMPLETE    V_INT_TXCOMPLETE(1U)
40290 
40291 #define S_TXBUFERR    6
40292 #define V_TXBUFERR(x) ((x) << S_TXBUFERR)
40293 #define F_TXBUFERR    V_TXBUFERR(1U)
40294 
40295 #define S_RETRYLIMITERR    5
40296 #define V_RETRYLIMITERR(x) ((x) << S_RETRYLIMITERR)
40297 #define F_RETRYLIMITERR    V_RETRYLIMITERR(1U)
40298 
40299 #define S_TXBUFUNDERRUN    4
40300 #define V_TXBUFUNDERRUN(x) ((x) << S_TXBUFUNDERRUN)
40301 #define F_TXBUFUNDERRUN    V_TXBUFUNDERRUN(1U)
40302 
40303 #define S_TXUSEDBITREAD    3
40304 #define V_TXUSEDBITREAD(x) ((x) << S_TXUSEDBITREAD)
40305 #define F_TXUSEDBITREAD    V_TXUSEDBITREAD(1U)
40306 
40307 #define S_RXUSEDBITREAD    2
40308 #define V_RXUSEDBITREAD(x) ((x) << S_RXUSEDBITREAD)
40309 #define F_RXUSEDBITREAD    V_RXUSEDBITREAD(1U)
40310 
40311 #define S_RXCOMPLETE    1
40312 #define V_RXCOMPLETE(x) ((x) << S_RXCOMPLETE)
40313 #define F_RXCOMPLETE    V_RXCOMPLETE(1U)
40314 
40315 #define S_MGMTFRAMESENT    0
40316 #define V_MGMTFRAMESENT(x) ((x) << S_MGMTFRAMESENT)
40317 #define F_MGMTFRAMESENT    V_MGMTFRAMESENT(1U)
40318 
40319 #define A_NCSI_MACB_INT_EN 0x1a128
40320 #define A_NCSI_MACB_INT_DIS 0x1a12c
40321 #define A_NCSI_MACB_INT_MASK 0x1a130
40322 #define A_NCSI_MACB_PAUSE_TIME 0x1a138
40323 
40324 #define S_PAUSETIME    0
40325 #define M_PAUSETIME    0xffffU
40326 #define V_PAUSETIME(x) ((x) << S_PAUSETIME)
40327 #define G_PAUSETIME(x) (((x) >> S_PAUSETIME) & M_PAUSETIME)
40328 
40329 #define A_NCSI_MACB_PAUSE_FRAMES_RCVD 0x1a13c
40330 
40331 #define S_PAUSEFRRCVD    0
40332 #define M_PAUSEFRRCVD    0xffffU
40333 #define V_PAUSEFRRCVD(x) ((x) << S_PAUSEFRRCVD)
40334 #define G_PAUSEFRRCVD(x) (((x) >> S_PAUSEFRRCVD) & M_PAUSEFRRCVD)
40335 
40336 #define A_NCSI_MACB_TX_FRAMES_OK 0x1a140
40337 
40338 #define S_TXFRAMESOK    0
40339 #define M_TXFRAMESOK    0xffffffU
40340 #define V_TXFRAMESOK(x) ((x) << S_TXFRAMESOK)
40341 #define G_TXFRAMESOK(x) (((x) >> S_TXFRAMESOK) & M_TXFRAMESOK)
40342 
40343 #define A_NCSI_MACB_SINGLE_COL_FRAMES 0x1a144
40344 
40345 #define S_SINGLECOLTXFRAMES    0
40346 #define M_SINGLECOLTXFRAMES    0xffffU
40347 #define V_SINGLECOLTXFRAMES(x) ((x) << S_SINGLECOLTXFRAMES)
40348 #define G_SINGLECOLTXFRAMES(x) (((x) >> S_SINGLECOLTXFRAMES) & M_SINGLECOLTXFRAMES)
40349 
40350 #define A_NCSI_MACB_MUL_COL_FRAMES 0x1a148
40351 
40352 #define S_MULCOLTXFRAMES    0
40353 #define M_MULCOLTXFRAMES    0xffffU
40354 #define V_MULCOLTXFRAMES(x) ((x) << S_MULCOLTXFRAMES)
40355 #define G_MULCOLTXFRAMES(x) (((x) >> S_MULCOLTXFRAMES) & M_MULCOLTXFRAMES)
40356 
40357 #define A_NCSI_MACB_RX_FRAMES_OK 0x1a14c
40358 
40359 #define S_RXFRAMESOK    0
40360 #define M_RXFRAMESOK    0xffffffU
40361 #define V_RXFRAMESOK(x) ((x) << S_RXFRAMESOK)
40362 #define G_RXFRAMESOK(x) (((x) >> S_RXFRAMESOK) & M_RXFRAMESOK)
40363 
40364 #define A_NCSI_MACB_FCS_ERR 0x1a150
40365 
40366 #define S_RXFCSERR    0
40367 #define M_RXFCSERR    0xffU
40368 #define V_RXFCSERR(x) ((x) << S_RXFCSERR)
40369 #define G_RXFCSERR(x) (((x) >> S_RXFCSERR) & M_RXFCSERR)
40370 
40371 #define A_NCSI_MACB_ALIGN_ERR 0x1a154
40372 
40373 #define S_RXALIGNERR    0
40374 #define M_RXALIGNERR    0xffU
40375 #define V_RXALIGNERR(x) ((x) << S_RXALIGNERR)
40376 #define G_RXALIGNERR(x) (((x) >> S_RXALIGNERR) & M_RXALIGNERR)
40377 
40378 #define A_NCSI_MACB_DEF_TX_FRAMES 0x1a158
40379 
40380 #define S_TXDEFERREDFRAMES    0
40381 #define M_TXDEFERREDFRAMES    0xffffU
40382 #define V_TXDEFERREDFRAMES(x) ((x) << S_TXDEFERREDFRAMES)
40383 #define G_TXDEFERREDFRAMES(x) (((x) >> S_TXDEFERREDFRAMES) & M_TXDEFERREDFRAMES)
40384 
40385 #define A_NCSI_MACB_LATE_COL 0x1a15c
40386 
40387 #define S_LATECOLLISIONS    0
40388 #define M_LATECOLLISIONS    0xffffU
40389 #define V_LATECOLLISIONS(x) ((x) << S_LATECOLLISIONS)
40390 #define G_LATECOLLISIONS(x) (((x) >> S_LATECOLLISIONS) & M_LATECOLLISIONS)
40391 
40392 #define A_NCSI_MACB_EXCESSIVE_COL 0x1a160
40393 
40394 #define S_EXCESSIVECOLLISIONS    0
40395 #define M_EXCESSIVECOLLISIONS    0xffU
40396 #define V_EXCESSIVECOLLISIONS(x) ((x) << S_EXCESSIVECOLLISIONS)
40397 #define G_EXCESSIVECOLLISIONS(x) (((x) >> S_EXCESSIVECOLLISIONS) & M_EXCESSIVECOLLISIONS)
40398 
40399 #define A_NCSI_MACB_TX_UNDERRUN_ERR 0x1a164
40400 
40401 #define S_TXUNDERRUNERR    0
40402 #define M_TXUNDERRUNERR    0xffU
40403 #define V_TXUNDERRUNERR(x) ((x) << S_TXUNDERRUNERR)
40404 #define G_TXUNDERRUNERR(x) (((x) >> S_TXUNDERRUNERR) & M_TXUNDERRUNERR)
40405 
40406 #define A_NCSI_MACB_CARRIER_SENSE_ERR 0x1a168
40407 
40408 #define S_CARRIERSENSEERRS    0
40409 #define M_CARRIERSENSEERRS    0xffU
40410 #define V_CARRIERSENSEERRS(x) ((x) << S_CARRIERSENSEERRS)
40411 #define G_CARRIERSENSEERRS(x) (((x) >> S_CARRIERSENSEERRS) & M_CARRIERSENSEERRS)
40412 
40413 #define A_NCSI_MACB_RX_RESOURCE_ERR 0x1a16c
40414 
40415 #define S_RXRESOURCEERR    0
40416 #define M_RXRESOURCEERR    0xffffU
40417 #define V_RXRESOURCEERR(x) ((x) << S_RXRESOURCEERR)
40418 #define G_RXRESOURCEERR(x) (((x) >> S_RXRESOURCEERR) & M_RXRESOURCEERR)
40419 
40420 #define A_NCSI_MACB_RX_OVERRUN_ERR 0x1a170
40421 
40422 #define S_RXOVERRUNERRCNT    0
40423 #define M_RXOVERRUNERRCNT    0xffU
40424 #define V_RXOVERRUNERRCNT(x) ((x) << S_RXOVERRUNERRCNT)
40425 #define G_RXOVERRUNERRCNT(x) (((x) >> S_RXOVERRUNERRCNT) & M_RXOVERRUNERRCNT)
40426 
40427 #define A_NCSI_MACB_RX_SYMBOL_ERR 0x1a174
40428 
40429 #define S_RXSYMBOLERR    0
40430 #define M_RXSYMBOLERR    0xffU
40431 #define V_RXSYMBOLERR(x) ((x) << S_RXSYMBOLERR)
40432 #define G_RXSYMBOLERR(x) (((x) >> S_RXSYMBOLERR) & M_RXSYMBOLERR)
40433 
40434 #define A_NCSI_MACB_RX_OVERSIZE_FRAME 0x1a178
40435 
40436 #define S_RXOVERSIZEERR    0
40437 #define M_RXOVERSIZEERR    0xffU
40438 #define V_RXOVERSIZEERR(x) ((x) << S_RXOVERSIZEERR)
40439 #define G_RXOVERSIZEERR(x) (((x) >> S_RXOVERSIZEERR) & M_RXOVERSIZEERR)
40440 
40441 #define A_NCSI_MACB_RX_JABBER_ERR 0x1a17c
40442 
40443 #define S_RXJABBERERR    0
40444 #define M_RXJABBERERR    0xffU
40445 #define V_RXJABBERERR(x) ((x) << S_RXJABBERERR)
40446 #define G_RXJABBERERR(x) (((x) >> S_RXJABBERERR) & M_RXJABBERERR)
40447 
40448 #define A_NCSI_MACB_RX_UNDERSIZE_FRAME 0x1a180
40449 
40450 #define S_RXUNDERSIZEFR    0
40451 #define M_RXUNDERSIZEFR    0xffU
40452 #define V_RXUNDERSIZEFR(x) ((x) << S_RXUNDERSIZEFR)
40453 #define G_RXUNDERSIZEFR(x) (((x) >> S_RXUNDERSIZEFR) & M_RXUNDERSIZEFR)
40454 
40455 #define A_NCSI_MACB_SQE_TEST_ERR 0x1a184
40456 
40457 #define S_SQETESTERR    0
40458 #define M_SQETESTERR    0xffU
40459 #define V_SQETESTERR(x) ((x) << S_SQETESTERR)
40460 #define G_SQETESTERR(x) (((x) >> S_SQETESTERR) & M_SQETESTERR)
40461 
40462 #define A_NCSI_MACB_LENGTH_ERR 0x1a188
40463 
40464 #define S_LENGTHERR    0
40465 #define M_LENGTHERR    0xffU
40466 #define V_LENGTHERR(x) ((x) << S_LENGTHERR)
40467 #define G_LENGTHERR(x) (((x) >> S_LENGTHERR) & M_LENGTHERR)
40468 
40469 #define A_NCSI_MACB_TX_PAUSE_FRAMES 0x1a18c
40470 
40471 #define S_TXPAUSEFRAMES    0
40472 #define M_TXPAUSEFRAMES    0xffffU
40473 #define V_TXPAUSEFRAMES(x) ((x) << S_TXPAUSEFRAMES)
40474 #define G_TXPAUSEFRAMES(x) (((x) >> S_TXPAUSEFRAMES) & M_TXPAUSEFRAMES)
40475 
40476 #define A_NCSI_MACB_HASH_LOW 0x1a190
40477 #define A_NCSI_MACB_HASH_HIGH 0x1a194
40478 #define A_NCSI_MACB_SPECIFIC_1_LOW 0x1a198
40479 #define A_NCSI_MACB_SPECIFIC_1_HIGH 0x1a19c
40480 
40481 #define S_MATCHHIGH    0
40482 #define M_MATCHHIGH    0xffffU
40483 #define V_MATCHHIGH(x) ((x) << S_MATCHHIGH)
40484 #define G_MATCHHIGH(x) (((x) >> S_MATCHHIGH) & M_MATCHHIGH)
40485 
40486 #define A_NCSI_MACB_SPECIFIC_2_LOW 0x1a1a0
40487 #define A_NCSI_MACB_SPECIFIC_2_HIGH 0x1a1a4
40488 #define A_NCSI_MACB_SPECIFIC_3_LOW 0x1a1a8
40489 #define A_NCSI_MACB_SPECIFIC_3_HIGH 0x1a1ac
40490 #define A_NCSI_MACB_SPECIFIC_4_LOW 0x1a1b0
40491 #define A_NCSI_MACB_SPECIFIC_4_HIGH 0x1a1b4
40492 #define A_NCSI_MACB_TYPE_ID 0x1a1b8
40493 
40494 #define S_TYPEID    0
40495 #define M_TYPEID    0xffffU
40496 #define V_TYPEID(x) ((x) << S_TYPEID)
40497 #define G_TYPEID(x) (((x) >> S_TYPEID) & M_TYPEID)
40498 
40499 #define A_NCSI_MACB_TX_PAUSE_QUANTUM 0x1a1bc
40500 
40501 #define S_TXPAUSEQUANTUM    0
40502 #define M_TXPAUSEQUANTUM    0xffffU
40503 #define V_TXPAUSEQUANTUM(x) ((x) << S_TXPAUSEQUANTUM)
40504 #define G_TXPAUSEQUANTUM(x) (((x) >> S_TXPAUSEQUANTUM) & M_TXPAUSEQUANTUM)
40505 
40506 #define A_NCSI_MACB_USER_IO 0x1a1c0
40507 
40508 #define S_USERPROGINPUT    16
40509 #define M_USERPROGINPUT    0xffffU
40510 #define V_USERPROGINPUT(x) ((x) << S_USERPROGINPUT)
40511 #define G_USERPROGINPUT(x) (((x) >> S_USERPROGINPUT) & M_USERPROGINPUT)
40512 
40513 #define S_USERPROGOUTPUT    0
40514 #define M_USERPROGOUTPUT    0xffffU
40515 #define V_USERPROGOUTPUT(x) ((x) << S_USERPROGOUTPUT)
40516 #define G_USERPROGOUTPUT(x) (((x) >> S_USERPROGOUTPUT) & M_USERPROGOUTPUT)
40517 
40518 #define A_NCSI_MACB_WOL_CFG 0x1a1c4
40519 
40520 #define S_MCHASHEN    19
40521 #define V_MCHASHEN(x) ((x) << S_MCHASHEN)
40522 #define F_MCHASHEN    V_MCHASHEN(1U)
40523 
40524 #define S_SPECIFIC1EN    18
40525 #define V_SPECIFIC1EN(x) ((x) << S_SPECIFIC1EN)
40526 #define F_SPECIFIC1EN    V_SPECIFIC1EN(1U)
40527 
40528 #define S_ARPEN    17
40529 #define V_ARPEN(x) ((x) << S_ARPEN)
40530 #define F_ARPEN    V_ARPEN(1U)
40531 
40532 #define S_MAGICPKTEN    16
40533 #define V_MAGICPKTEN(x) ((x) << S_MAGICPKTEN)
40534 #define F_MAGICPKTEN    V_MAGICPKTEN(1U)
40535 
40536 #define S_ARPIPADDR    0
40537 #define M_ARPIPADDR    0xffffU
40538 #define V_ARPIPADDR(x) ((x) << S_ARPIPADDR)
40539 #define G_ARPIPADDR(x) (((x) >> S_ARPIPADDR) & M_ARPIPADDR)
40540 
40541 #define A_NCSI_MACB_REV_STATUS 0x1a1fc
40542 
40543 #define S_PARTREF    16
40544 #define M_PARTREF    0xffffU
40545 #define V_PARTREF(x) ((x) << S_PARTREF)
40546 #define G_PARTREF(x) (((x) >> S_PARTREF) & M_PARTREF)
40547 
40548 #define S_DESREV    0
40549 #define M_DESREV    0xffffU
40550 #define V_DESREV(x) ((x) << S_DESREV)
40551 #define G_DESREV(x) (((x) >> S_DESREV) & M_DESREV)
40552 
40553 /* registers for module XGMAC */
40554 #define XGMAC_BASE_ADDR 0x0
40555 
40556 #define A_XGMAC_PORT_CFG 0x1000
40557 
40558 #define S_XGMII_CLK_SEL    29
40559 #define M_XGMII_CLK_SEL    0x7U
40560 #define V_XGMII_CLK_SEL(x) ((x) << S_XGMII_CLK_SEL)
40561 #define G_XGMII_CLK_SEL(x) (((x) >> S_XGMII_CLK_SEL) & M_XGMII_CLK_SEL)
40562 
40563 #define S_SINKTX    27
40564 #define V_SINKTX(x) ((x) << S_SINKTX)
40565 #define F_SINKTX    V_SINKTX(1U)
40566 
40567 #define S_SINKTXONLINKDOWN    26
40568 #define V_SINKTXONLINKDOWN(x) ((x) << S_SINKTXONLINKDOWN)
40569 #define F_SINKTXONLINKDOWN    V_SINKTXONLINKDOWN(1U)
40570 
40571 #define S_XG2G_SPEED_MODE    25
40572 #define V_XG2G_SPEED_MODE(x) ((x) << S_XG2G_SPEED_MODE)
40573 #define F_XG2G_SPEED_MODE    V_XG2G_SPEED_MODE(1U)
40574 
40575 #define S_LOOPNOFWD    24
40576 #define V_LOOPNOFWD(x) ((x) << S_LOOPNOFWD)
40577 #define F_LOOPNOFWD    V_LOOPNOFWD(1U)
40578 
40579 #define S_XGM_TX_PAUSE_SIZE    23
40580 #define V_XGM_TX_PAUSE_SIZE(x) ((x) << S_XGM_TX_PAUSE_SIZE)
40581 #define F_XGM_TX_PAUSE_SIZE    V_XGM_TX_PAUSE_SIZE(1U)
40582 
40583 #define S_XGM_TX_PAUSE_FRAME    22
40584 #define V_XGM_TX_PAUSE_FRAME(x) ((x) << S_XGM_TX_PAUSE_FRAME)
40585 #define F_XGM_TX_PAUSE_FRAME    V_XGM_TX_PAUSE_FRAME(1U)
40586 
40587 #define S_XGM_TX_DISABLE_PRE    21
40588 #define V_XGM_TX_DISABLE_PRE(x) ((x) << S_XGM_TX_DISABLE_PRE)
40589 #define F_XGM_TX_DISABLE_PRE    V_XGM_TX_DISABLE_PRE(1U)
40590 
40591 #define S_XGM_TX_DISABLE_CRC    20
40592 #define V_XGM_TX_DISABLE_CRC(x) ((x) << S_XGM_TX_DISABLE_CRC)
40593 #define F_XGM_TX_DISABLE_CRC    V_XGM_TX_DISABLE_CRC(1U)
40594 
40595 #define S_SMUX_RX_LOOP    19
40596 #define V_SMUX_RX_LOOP(x) ((x) << S_SMUX_RX_LOOP)
40597 #define F_SMUX_RX_LOOP    V_SMUX_RX_LOOP(1U)
40598 
40599 #define S_RX_LANE_SWAP    18
40600 #define V_RX_LANE_SWAP(x) ((x) << S_RX_LANE_SWAP)
40601 #define F_RX_LANE_SWAP    V_RX_LANE_SWAP(1U)
40602 
40603 #define S_TX_LANE_SWAP    17
40604 #define V_TX_LANE_SWAP(x) ((x) << S_TX_LANE_SWAP)
40605 #define F_TX_LANE_SWAP    V_TX_LANE_SWAP(1U)
40606 
40607 #define S_SIGNAL_DET    14
40608 #define V_SIGNAL_DET(x) ((x) << S_SIGNAL_DET)
40609 #define F_SIGNAL_DET    V_SIGNAL_DET(1U)
40610 
40611 #define S_PMUX_RX_LOOP    13
40612 #define V_PMUX_RX_LOOP(x) ((x) << S_PMUX_RX_LOOP)
40613 #define F_PMUX_RX_LOOP    V_PMUX_RX_LOOP(1U)
40614 
40615 #define S_PMUX_TX_LOOP    12
40616 #define V_PMUX_TX_LOOP(x) ((x) << S_PMUX_TX_LOOP)
40617 #define F_PMUX_TX_LOOP    V_PMUX_TX_LOOP(1U)
40618 
40619 #define S_XGM_RX_SEL    10
40620 #define M_XGM_RX_SEL    0x3U
40621 #define V_XGM_RX_SEL(x) ((x) << S_XGM_RX_SEL)
40622 #define G_XGM_RX_SEL(x) (((x) >> S_XGM_RX_SEL) & M_XGM_RX_SEL)
40623 
40624 #define S_PCS_TX_SEL    8
40625 #define M_PCS_TX_SEL    0x3U
40626 #define V_PCS_TX_SEL(x) ((x) << S_PCS_TX_SEL)
40627 #define G_PCS_TX_SEL(x) (((x) >> S_PCS_TX_SEL) & M_PCS_TX_SEL)
40628 
40629 #define S_XAUI20_REM_PRE    5
40630 #define V_XAUI20_REM_PRE(x) ((x) << S_XAUI20_REM_PRE)
40631 #define F_XAUI20_REM_PRE    V_XAUI20_REM_PRE(1U)
40632 
40633 #define S_XAUI20_XGMII_SEL    4
40634 #define V_XAUI20_XGMII_SEL(x) ((x) << S_XAUI20_XGMII_SEL)
40635 #define F_XAUI20_XGMII_SEL    V_XAUI20_XGMII_SEL(1U)
40636 
40637 #define S_PORT_SEL    0
40638 #define V_PORT_SEL(x) ((x) << S_PORT_SEL)
40639 #define F_PORT_SEL    V_PORT_SEL(1U)
40640 
40641 #define A_XGMAC_PORT_RESET_CTRL 0x1004
40642 
40643 #define S_AUXEXT_RESET    10
40644 #define V_AUXEXT_RESET(x) ((x) << S_AUXEXT_RESET)
40645 #define F_AUXEXT_RESET    V_AUXEXT_RESET(1U)
40646 
40647 #define S_TXFIFO_RESET    9
40648 #define V_TXFIFO_RESET(x) ((x) << S_TXFIFO_RESET)
40649 #define F_TXFIFO_RESET    V_TXFIFO_RESET(1U)
40650 
40651 #define S_RXFIFO_RESET    8
40652 #define V_RXFIFO_RESET(x) ((x) << S_RXFIFO_RESET)
40653 #define F_RXFIFO_RESET    V_RXFIFO_RESET(1U)
40654 
40655 #define S_BEAN_RESET    7
40656 #define V_BEAN_RESET(x) ((x) << S_BEAN_RESET)
40657 #define F_BEAN_RESET    V_BEAN_RESET(1U)
40658 
40659 #define S_XAUI_RESET    6
40660 #define V_XAUI_RESET(x) ((x) << S_XAUI_RESET)
40661 #define F_XAUI_RESET    V_XAUI_RESET(1U)
40662 
40663 #define S_AE_RESET    5
40664 #define V_AE_RESET(x) ((x) << S_AE_RESET)
40665 #define F_AE_RESET    V_AE_RESET(1U)
40666 
40667 #define S_XGM_RESET    4
40668 #define V_XGM_RESET(x) ((x) << S_XGM_RESET)
40669 #define F_XGM_RESET    V_XGM_RESET(1U)
40670 
40671 #define S_XG2G_RESET    3
40672 #define V_XG2G_RESET(x) ((x) << S_XG2G_RESET)
40673 #define F_XG2G_RESET    V_XG2G_RESET(1U)
40674 
40675 #define S_WOL_RESET    2
40676 #define V_WOL_RESET(x) ((x) << S_WOL_RESET)
40677 #define F_WOL_RESET    V_WOL_RESET(1U)
40678 
40679 #define S_XFI_PCS_RESET    1
40680 #define V_XFI_PCS_RESET(x) ((x) << S_XFI_PCS_RESET)
40681 #define F_XFI_PCS_RESET    V_XFI_PCS_RESET(1U)
40682 
40683 #define S_HSS_RESET    0
40684 #define V_HSS_RESET(x) ((x) << S_HSS_RESET)
40685 #define F_HSS_RESET    V_HSS_RESET(1U)
40686 
40687 #define A_XGMAC_PORT_LED_CFG 0x1008
40688 
40689 #define S_LED1_CFG    5
40690 #define M_LED1_CFG    0x7U
40691 #define V_LED1_CFG(x) ((x) << S_LED1_CFG)
40692 #define G_LED1_CFG(x) (((x) >> S_LED1_CFG) & M_LED1_CFG)
40693 
40694 #define S_LED1_POLARITY_INV    4
40695 #define V_LED1_POLARITY_INV(x) ((x) << S_LED1_POLARITY_INV)
40696 #define F_LED1_POLARITY_INV    V_LED1_POLARITY_INV(1U)
40697 
40698 #define S_LED0_CFG    1
40699 #define M_LED0_CFG    0x7U
40700 #define V_LED0_CFG(x) ((x) << S_LED0_CFG)
40701 #define G_LED0_CFG(x) (((x) >> S_LED0_CFG) & M_LED0_CFG)
40702 
40703 #define S_LED0_POLARITY_INV    0
40704 #define V_LED0_POLARITY_INV(x) ((x) << S_LED0_POLARITY_INV)
40705 #define F_LED0_POLARITY_INV    V_LED0_POLARITY_INV(1U)
40706 
40707 #define A_XGMAC_PORT_LED_COUNTHI 0x100c
40708 
40709 #define S_LED_COUNT_HI    0
40710 #define M_LED_COUNT_HI    0x1ffffffU
40711 #define V_LED_COUNT_HI(x) ((x) << S_LED_COUNT_HI)
40712 #define G_LED_COUNT_HI(x) (((x) >> S_LED_COUNT_HI) & M_LED_COUNT_HI)
40713 
40714 #define A_XGMAC_PORT_LED_COUNTLO 0x1010
40715 
40716 #define S_LED_COUNT_LO    0
40717 #define M_LED_COUNT_LO    0x1ffffffU
40718 #define V_LED_COUNT_LO(x) ((x) << S_LED_COUNT_LO)
40719 #define G_LED_COUNT_LO(x) (((x) >> S_LED_COUNT_LO) & M_LED_COUNT_LO)
40720 
40721 #define A_XGMAC_PORT_DEBUG_CFG 0x1014
40722 
40723 #define S_TESTCLK_SEL    0
40724 #define M_TESTCLK_SEL    0xfU
40725 #define V_TESTCLK_SEL(x) ((x) << S_TESTCLK_SEL)
40726 #define G_TESTCLK_SEL(x) (((x) >> S_TESTCLK_SEL) & M_TESTCLK_SEL)
40727 
40728 #define A_XGMAC_PORT_CFG2 0x1018
40729 
40730 #define S_RX_POLARITY_INV    28
40731 #define M_RX_POLARITY_INV    0xfU
40732 #define V_RX_POLARITY_INV(x) ((x) << S_RX_POLARITY_INV)
40733 #define G_RX_POLARITY_INV(x) (((x) >> S_RX_POLARITY_INV) & M_RX_POLARITY_INV)
40734 
40735 #define S_TX_POLARITY_INV    24
40736 #define M_TX_POLARITY_INV    0xfU
40737 #define V_TX_POLARITY_INV(x) ((x) << S_TX_POLARITY_INV)
40738 #define G_TX_POLARITY_INV(x) (((x) >> S_TX_POLARITY_INV) & M_TX_POLARITY_INV)
40739 
40740 #define S_INSTANCENUM    22
40741 #define M_INSTANCENUM    0x3U
40742 #define V_INSTANCENUM(x) ((x) << S_INSTANCENUM)
40743 #define G_INSTANCENUM(x) (((x) >> S_INSTANCENUM) & M_INSTANCENUM)
40744 
40745 #define S_STOPONPERR    21
40746 #define V_STOPONPERR(x) ((x) << S_STOPONPERR)
40747 #define F_STOPONPERR    V_STOPONPERR(1U)
40748 
40749 #define S_MACTXEN    20
40750 #define V_MACTXEN(x) ((x) << S_MACTXEN)
40751 #define F_MACTXEN    V_MACTXEN(1U)
40752 
40753 #define S_MACRXEN    19
40754 #define V_MACRXEN(x) ((x) << S_MACRXEN)
40755 #define F_MACRXEN    V_MACRXEN(1U)
40756 
40757 #define S_PATEN    18
40758 #define V_PATEN(x) ((x) << S_PATEN)
40759 #define F_PATEN    V_PATEN(1U)
40760 
40761 #define S_MAGICEN    17
40762 #define V_MAGICEN(x) ((x) << S_MAGICEN)
40763 #define F_MAGICEN    V_MAGICEN(1U)
40764 
40765 #define S_TX_IPG    4
40766 #define M_TX_IPG    0x1fffU
40767 #define V_TX_IPG(x) ((x) << S_TX_IPG)
40768 #define G_TX_IPG(x) (((x) >> S_TX_IPG) & M_TX_IPG)
40769 
40770 #define S_AEC_PMA_TX_READY    1
40771 #define V_AEC_PMA_TX_READY(x) ((x) << S_AEC_PMA_TX_READY)
40772 #define F_AEC_PMA_TX_READY    V_AEC_PMA_TX_READY(1U)
40773 
40774 #define S_AEC_PMA_RX_READY    0
40775 #define V_AEC_PMA_RX_READY(x) ((x) << S_AEC_PMA_RX_READY)
40776 #define F_AEC_PMA_RX_READY    V_AEC_PMA_RX_READY(1U)
40777 
40778 #define A_XGMAC_PORT_PKT_COUNT 0x101c
40779 
40780 #define S_TX_SOP_COUNT    24
40781 #define M_TX_SOP_COUNT    0xffU
40782 #define V_TX_SOP_COUNT(x) ((x) << S_TX_SOP_COUNT)
40783 #define G_TX_SOP_COUNT(x) (((x) >> S_TX_SOP_COUNT) & M_TX_SOP_COUNT)
40784 
40785 #define S_TX_EOP_COUNT    16
40786 #define M_TX_EOP_COUNT    0xffU
40787 #define V_TX_EOP_COUNT(x) ((x) << S_TX_EOP_COUNT)
40788 #define G_TX_EOP_COUNT(x) (((x) >> S_TX_EOP_COUNT) & M_TX_EOP_COUNT)
40789 
40790 #define S_RX_SOP_COUNT    8
40791 #define M_RX_SOP_COUNT    0xffU
40792 #define V_RX_SOP_COUNT(x) ((x) << S_RX_SOP_COUNT)
40793 #define G_RX_SOP_COUNT(x) (((x) >> S_RX_SOP_COUNT) & M_RX_SOP_COUNT)
40794 
40795 #define S_RX_EOP_COUNT    0
40796 #define M_RX_EOP_COUNT    0xffU
40797 #define V_RX_EOP_COUNT(x) ((x) << S_RX_EOP_COUNT)
40798 #define G_RX_EOP_COUNT(x) (((x) >> S_RX_EOP_COUNT) & M_RX_EOP_COUNT)
40799 
40800 #define A_XGMAC_PORT_PERR_INJECT 0x1020
40801 
40802 #define S_XGMMEMSEL    1
40803 #define V_XGMMEMSEL(x) ((x) << S_XGMMEMSEL)
40804 #define F_XGMMEMSEL    V_XGMMEMSEL(1U)
40805 
40806 #define A_XGMAC_PORT_MAGIC_MACID_LO 0x1024
40807 #define A_XGMAC_PORT_MAGIC_MACID_HI 0x1028
40808 
40809 #define S_MAC_WOL_DA    0
40810 #define M_MAC_WOL_DA    0xffffU
40811 #define V_MAC_WOL_DA(x) ((x) << S_MAC_WOL_DA)
40812 #define G_MAC_WOL_DA(x) (((x) >> S_MAC_WOL_DA) & M_MAC_WOL_DA)
40813 
40814 #define A_XGMAC_PORT_BUILD_REVISION 0x102c
40815 #define A_XGMAC_PORT_XGMII_SE_COUNT 0x1030
40816 
40817 #define S_TXSOP    24
40818 #define M_TXSOP    0xffU
40819 #define V_TXSOP(x) ((x) << S_TXSOP)
40820 #define G_TXSOP(x) (((x) >> S_TXSOP) & M_TXSOP)
40821 
40822 #define S_TXEOP    16
40823 #define M_TXEOP    0xffU
40824 #define V_TXEOP(x) ((x) << S_TXEOP)
40825 #define G_TXEOP(x) (((x) >> S_TXEOP) & M_TXEOP)
40826 
40827 #define S_RXSOP    8
40828 #define M_RXSOP    0xffU
40829 #define V_RXSOP(x) ((x) << S_RXSOP)
40830 #define G_RXSOP(x) (((x) >> S_RXSOP) & M_RXSOP)
40831 
40832 #define S_T4_RXEOP    0
40833 #define M_T4_RXEOP    0xffU
40834 #define V_T4_RXEOP(x) ((x) << S_T4_RXEOP)
40835 #define G_T4_RXEOP(x) (((x) >> S_T4_RXEOP) & M_T4_RXEOP)
40836 
40837 #define A_XGMAC_PORT_LINK_STATUS 0x1034
40838 
40839 #define S_REMFLT    3
40840 #define V_REMFLT(x) ((x) << S_REMFLT)
40841 #define F_REMFLT    V_REMFLT(1U)
40842 
40843 #define S_LOCFLT    2
40844 #define V_LOCFLT(x) ((x) << S_LOCFLT)
40845 #define F_LOCFLT    V_LOCFLT(1U)
40846 
40847 #define S_LINKUP    1
40848 #define V_LINKUP(x) ((x) << S_LINKUP)
40849 #define F_LINKUP    V_LINKUP(1U)
40850 
40851 #define S_LINKDN    0
40852 #define V_LINKDN(x) ((x) << S_LINKDN)
40853 #define F_LINKDN    V_LINKDN(1U)
40854 
40855 #define A_XGMAC_PORT_CHECKIN 0x1038
40856 
40857 #define S_PREAMBLE    1
40858 #define V_PREAMBLE(x) ((x) << S_PREAMBLE)
40859 #define F_PREAMBLE    V_PREAMBLE(1U)
40860 
40861 #define S_CHECKIN    0
40862 #define V_CHECKIN(x) ((x) << S_CHECKIN)
40863 #define F_CHECKIN    V_CHECKIN(1U)
40864 
40865 #define A_XGMAC_PORT_FAULT_TEST 0x103c
40866 
40867 #define S_FLTTYPE    1
40868 #define V_FLTTYPE(x) ((x) << S_FLTTYPE)
40869 #define F_FLTTYPE    V_FLTTYPE(1U)
40870 
40871 #define S_FLTCTRL    0
40872 #define V_FLTCTRL(x) ((x) << S_FLTCTRL)
40873 #define F_FLTCTRL    V_FLTCTRL(1U)
40874 
40875 #define A_XGMAC_PORT_SPARE 0x1040
40876 #define A_XGMAC_PORT_HSS_SIGDET_STATUS 0x1044
40877 
40878 #define S_SIGNALDETECT    0
40879 #define M_SIGNALDETECT    0xfU
40880 #define V_SIGNALDETECT(x) ((x) << S_SIGNALDETECT)
40881 #define G_SIGNALDETECT(x) (((x) >> S_SIGNALDETECT) & M_SIGNALDETECT)
40882 
40883 #define A_XGMAC_PORT_EXT_LOS_STATUS 0x1048
40884 #define A_XGMAC_PORT_EXT_LOS_CTRL 0x104c
40885 
40886 #define S_CTRL    0
40887 #define M_CTRL    0xfU
40888 #define V_CTRL(x) ((x) << S_CTRL)
40889 #define G_CTRL(x) (((x) >> S_CTRL) & M_CTRL)
40890 
40891 #define A_XGMAC_PORT_FPGA_PAUSE_CTL 0x1050
40892 
40893 #define S_CTL    31
40894 #define V_CTL(x) ((x) << S_CTL)
40895 #define F_CTL    V_CTL(1U)
40896 
40897 #define S_HWM    13
40898 #define M_HWM    0x1fffU
40899 #define V_HWM(x) ((x) << S_HWM)
40900 #define G_HWM(x) (((x) >> S_HWM) & M_HWM)
40901 
40902 #define S_LWM    0
40903 #define M_LWM    0x1fffU
40904 #define V_LWM(x) ((x) << S_LWM)
40905 #define G_LWM(x) (((x) >> S_LWM) & M_LWM)
40906 
40907 #define A_XGMAC_PORT_FPGA_ERRPKT_CNT 0x1054
40908 #define A_XGMAC_PORT_LA_TX_0 0x1058
40909 #define A_XGMAC_PORT_LA_RX_0 0x105c
40910 #define A_XGMAC_PORT_FPGA_LA_CTL 0x1060
40911 
40912 #define S_RXRST    5
40913 #define V_RXRST(x) ((x) << S_RXRST)
40914 #define F_RXRST    V_RXRST(1U)
40915 
40916 #define S_TXRST    4
40917 #define V_TXRST(x) ((x) << S_TXRST)
40918 #define F_TXRST    V_TXRST(1U)
40919 
40920 #define S_XGMII    3
40921 #define V_XGMII(x) ((x) << S_XGMII)
40922 #define F_XGMII    V_XGMII(1U)
40923 
40924 #define S_LAPAUSE    2
40925 #define V_LAPAUSE(x) ((x) << S_LAPAUSE)
40926 #define F_LAPAUSE    V_LAPAUSE(1U)
40927 
40928 #define S_STOPERR    1
40929 #define V_STOPERR(x) ((x) << S_STOPERR)
40930 #define F_STOPERR    V_STOPERR(1U)
40931 
40932 #define S_LASTOP    0
40933 #define V_LASTOP(x) ((x) << S_LASTOP)
40934 #define F_LASTOP    V_LASTOP(1U)
40935 
40936 #define A_XGMAC_PORT_EPIO_DATA0 0x10c0
40937 #define A_XGMAC_PORT_EPIO_DATA1 0x10c4
40938 #define A_XGMAC_PORT_EPIO_DATA2 0x10c8
40939 #define A_XGMAC_PORT_EPIO_DATA3 0x10cc
40940 #define A_XGMAC_PORT_EPIO_OP 0x10d0
40941 
40942 #define S_EPIOWR    8
40943 #define V_EPIOWR(x) ((x) << S_EPIOWR)
40944 #define F_EPIOWR    V_EPIOWR(1U)
40945 
40946 #define S_ADDRESS    0
40947 #define M_ADDRESS    0xffU
40948 #define V_ADDRESS(x) ((x) << S_ADDRESS)
40949 #define G_ADDRESS(x) (((x) >> S_ADDRESS) & M_ADDRESS)
40950 
40951 #define A_XGMAC_PORT_WOL_STATUS 0x10d4
40952 
40953 #define S_MAGICDETECTED    31
40954 #define V_MAGICDETECTED(x) ((x) << S_MAGICDETECTED)
40955 #define F_MAGICDETECTED    V_MAGICDETECTED(1U)
40956 
40957 #define S_PATDETECTED    30
40958 #define V_PATDETECTED(x) ((x) << S_PATDETECTED)
40959 #define F_PATDETECTED    V_PATDETECTED(1U)
40960 
40961 #define S_CLEARMAGIC    4
40962 #define V_CLEARMAGIC(x) ((x) << S_CLEARMAGIC)
40963 #define F_CLEARMAGIC    V_CLEARMAGIC(1U)
40964 
40965 #define S_CLEARMATCH    3
40966 #define V_CLEARMATCH(x) ((x) << S_CLEARMATCH)
40967 #define F_CLEARMATCH    V_CLEARMATCH(1U)
40968 
40969 #define S_MATCHEDFILTER    0
40970 #define M_MATCHEDFILTER    0x7U
40971 #define V_MATCHEDFILTER(x) ((x) << S_MATCHEDFILTER)
40972 #define G_MATCHEDFILTER(x) (((x) >> S_MATCHEDFILTER) & M_MATCHEDFILTER)
40973 
40974 #define A_XGMAC_PORT_INT_EN 0x10d8
40975 
40976 #define S_EXT_LOS    28
40977 #define V_EXT_LOS(x) ((x) << S_EXT_LOS)
40978 #define F_EXT_LOS    V_EXT_LOS(1U)
40979 
40980 #define S_INCMPTBL_LINK    27
40981 #define V_INCMPTBL_LINK(x) ((x) << S_INCMPTBL_LINK)
40982 #define F_INCMPTBL_LINK    V_INCMPTBL_LINK(1U)
40983 
40984 #define S_PATDETWAKE    26
40985 #define V_PATDETWAKE(x) ((x) << S_PATDETWAKE)
40986 #define F_PATDETWAKE    V_PATDETWAKE(1U)
40987 
40988 #define S_MAGICWAKE    25
40989 #define V_MAGICWAKE(x) ((x) << S_MAGICWAKE)
40990 #define F_MAGICWAKE    V_MAGICWAKE(1U)
40991 
40992 #define S_SIGDETCHG    24
40993 #define V_SIGDETCHG(x) ((x) << S_SIGDETCHG)
40994 #define F_SIGDETCHG    V_SIGDETCHG(1U)
40995 
40996 #define S_PCSR_FEC_CORR    23
40997 #define V_PCSR_FEC_CORR(x) ((x) << S_PCSR_FEC_CORR)
40998 #define F_PCSR_FEC_CORR    V_PCSR_FEC_CORR(1U)
40999 
41000 #define S_AE_TRAIN_LOCAL    22
41001 #define V_AE_TRAIN_LOCAL(x) ((x) << S_AE_TRAIN_LOCAL)
41002 #define F_AE_TRAIN_LOCAL    V_AE_TRAIN_LOCAL(1U)
41003 
41004 #define S_HSSPLL_LOCK    21
41005 #define V_HSSPLL_LOCK(x) ((x) << S_HSSPLL_LOCK)
41006 #define F_HSSPLL_LOCK    V_HSSPLL_LOCK(1U)
41007 
41008 #define S_HSSPRT_READY    20
41009 #define V_HSSPRT_READY(x) ((x) << S_HSSPRT_READY)
41010 #define F_HSSPRT_READY    V_HSSPRT_READY(1U)
41011 
41012 #define S_AUTONEG_DONE    19
41013 #define V_AUTONEG_DONE(x) ((x) << S_AUTONEG_DONE)
41014 #define F_AUTONEG_DONE    V_AUTONEG_DONE(1U)
41015 
41016 #define S_PCSR_HI_BER    18
41017 #define V_PCSR_HI_BER(x) ((x) << S_PCSR_HI_BER)
41018 #define F_PCSR_HI_BER    V_PCSR_HI_BER(1U)
41019 
41020 #define S_PCSR_FEC_ERROR    17
41021 #define V_PCSR_FEC_ERROR(x) ((x) << S_PCSR_FEC_ERROR)
41022 #define F_PCSR_FEC_ERROR    V_PCSR_FEC_ERROR(1U)
41023 
41024 #define S_PCSR_LINK_FAIL    16
41025 #define V_PCSR_LINK_FAIL(x) ((x) << S_PCSR_LINK_FAIL)
41026 #define F_PCSR_LINK_FAIL    V_PCSR_LINK_FAIL(1U)
41027 
41028 #define S_XAUI_DEC_ERROR    15
41029 #define V_XAUI_DEC_ERROR(x) ((x) << S_XAUI_DEC_ERROR)
41030 #define F_XAUI_DEC_ERROR    V_XAUI_DEC_ERROR(1U)
41031 
41032 #define S_XAUI_LINK_FAIL    14
41033 #define V_XAUI_LINK_FAIL(x) ((x) << S_XAUI_LINK_FAIL)
41034 #define F_XAUI_LINK_FAIL    V_XAUI_LINK_FAIL(1U)
41035 
41036 #define S_PCS_CTC_ERROR    13
41037 #define V_PCS_CTC_ERROR(x) ((x) << S_PCS_CTC_ERROR)
41038 #define F_PCS_CTC_ERROR    V_PCS_CTC_ERROR(1U)
41039 
41040 #define S_PCS_LINK_GOOD    12
41041 #define V_PCS_LINK_GOOD(x) ((x) << S_PCS_LINK_GOOD)
41042 #define F_PCS_LINK_GOOD    V_PCS_LINK_GOOD(1U)
41043 
41044 #define S_PCS_LINK_FAIL    11
41045 #define V_PCS_LINK_FAIL(x) ((x) << S_PCS_LINK_FAIL)
41046 #define F_PCS_LINK_FAIL    V_PCS_LINK_FAIL(1U)
41047 
41048 #define S_RXFIFOOVERFLOW    10
41049 #define V_RXFIFOOVERFLOW(x) ((x) << S_RXFIFOOVERFLOW)
41050 #define F_RXFIFOOVERFLOW    V_RXFIFOOVERFLOW(1U)
41051 
41052 #define S_HSSPRBSERR    9
41053 #define V_HSSPRBSERR(x) ((x) << S_HSSPRBSERR)
41054 #define F_HSSPRBSERR    V_HSSPRBSERR(1U)
41055 
41056 #define S_HSSEYEQUAL    8
41057 #define V_HSSEYEQUAL(x) ((x) << S_HSSEYEQUAL)
41058 #define F_HSSEYEQUAL    V_HSSEYEQUAL(1U)
41059 
41060 #define S_REMOTEFAULT    7
41061 #define V_REMOTEFAULT(x) ((x) << S_REMOTEFAULT)
41062 #define F_REMOTEFAULT    V_REMOTEFAULT(1U)
41063 
41064 #define S_LOCALFAULT    6
41065 #define V_LOCALFAULT(x) ((x) << S_LOCALFAULT)
41066 #define F_LOCALFAULT    V_LOCALFAULT(1U)
41067 
41068 #define S_MAC_LINK_DOWN    5
41069 #define V_MAC_LINK_DOWN(x) ((x) << S_MAC_LINK_DOWN)
41070 #define F_MAC_LINK_DOWN    V_MAC_LINK_DOWN(1U)
41071 
41072 #define S_MAC_LINK_UP    4
41073 #define V_MAC_LINK_UP(x) ((x) << S_MAC_LINK_UP)
41074 #define F_MAC_LINK_UP    V_MAC_LINK_UP(1U)
41075 
41076 #define S_BEAN_INT    3
41077 #define V_BEAN_INT(x) ((x) << S_BEAN_INT)
41078 #define F_BEAN_INT    V_BEAN_INT(1U)
41079 
41080 #define S_XGM_INT    2
41081 #define V_XGM_INT(x) ((x) << S_XGM_INT)
41082 #define F_XGM_INT    V_XGM_INT(1U)
41083 
41084 #define A_XGMAC_PORT_INT_CAUSE 0x10dc
41085 #define A_XGMAC_PORT_HSS_CFG0 0x10e0
41086 
41087 #define S_TXDTS    31
41088 #define V_TXDTS(x) ((x) << S_TXDTS)
41089 #define F_TXDTS    V_TXDTS(1U)
41090 
41091 #define S_TXCTS    30
41092 #define V_TXCTS(x) ((x) << S_TXCTS)
41093 #define F_TXCTS    V_TXCTS(1U)
41094 
41095 #define S_TXBTS    29
41096 #define V_TXBTS(x) ((x) << S_TXBTS)
41097 #define F_TXBTS    V_TXBTS(1U)
41098 
41099 #define S_TXATS    28
41100 #define V_TXATS(x) ((x) << S_TXATS)
41101 #define F_TXATS    V_TXATS(1U)
41102 
41103 #define S_TXDOBS    27
41104 #define V_TXDOBS(x) ((x) << S_TXDOBS)
41105 #define F_TXDOBS    V_TXDOBS(1U)
41106 
41107 #define S_TXCOBS    26
41108 #define V_TXCOBS(x) ((x) << S_TXCOBS)
41109 #define F_TXCOBS    V_TXCOBS(1U)
41110 
41111 #define S_TXBOBS    25
41112 #define V_TXBOBS(x) ((x) << S_TXBOBS)
41113 #define F_TXBOBS    V_TXBOBS(1U)
41114 
41115 #define S_TXAOBS    24
41116 #define V_TXAOBS(x) ((x) << S_TXAOBS)
41117 #define F_TXAOBS    V_TXAOBS(1U)
41118 
41119 #define S_HSSREFCLKSEL    20
41120 #define V_HSSREFCLKSEL(x) ((x) << S_HSSREFCLKSEL)
41121 #define F_HSSREFCLKSEL    V_HSSREFCLKSEL(1U)
41122 
41123 #define S_HSSAVDHI    17
41124 #define V_HSSAVDHI(x) ((x) << S_HSSAVDHI)
41125 #define F_HSSAVDHI    V_HSSAVDHI(1U)
41126 
41127 #define S_HSSRXTS    16
41128 #define V_HSSRXTS(x) ((x) << S_HSSRXTS)
41129 #define F_HSSRXTS    V_HSSRXTS(1U)
41130 
41131 #define S_HSSTXACMODE    15
41132 #define V_HSSTXACMODE(x) ((x) << S_HSSTXACMODE)
41133 #define F_HSSTXACMODE    V_HSSTXACMODE(1U)
41134 
41135 #define S_HSSRXACMODE    14
41136 #define V_HSSRXACMODE(x) ((x) << S_HSSRXACMODE)
41137 #define F_HSSRXACMODE    V_HSSRXACMODE(1U)
41138 
41139 #define S_HSSRESYNC    13
41140 #define V_HSSRESYNC(x) ((x) << S_HSSRESYNC)
41141 #define F_HSSRESYNC    V_HSSRESYNC(1U)
41142 
41143 #define S_HSSRECCAL    12
41144 #define V_HSSRECCAL(x) ((x) << S_HSSRECCAL)
41145 #define F_HSSRECCAL    V_HSSRECCAL(1U)
41146 
41147 #define S_HSSPDWNPLL    11
41148 #define V_HSSPDWNPLL(x) ((x) << S_HSSPDWNPLL)
41149 #define F_HSSPDWNPLL    V_HSSPDWNPLL(1U)
41150 
41151 #define S_HSSDIVSEL    9
41152 #define M_HSSDIVSEL    0x3U
41153 #define V_HSSDIVSEL(x) ((x) << S_HSSDIVSEL)
41154 #define G_HSSDIVSEL(x) (((x) >> S_HSSDIVSEL) & M_HSSDIVSEL)
41155 
41156 #define S_HSSREFDIV    8
41157 #define V_HSSREFDIV(x) ((x) << S_HSSREFDIV)
41158 #define F_HSSREFDIV    V_HSSREFDIV(1U)
41159 
41160 #define S_HSSPLLBYP    7
41161 #define V_HSSPLLBYP(x) ((x) << S_HSSPLLBYP)
41162 #define F_HSSPLLBYP    V_HSSPLLBYP(1U)
41163 
41164 #define S_HSSLOFREQPLL    6
41165 #define V_HSSLOFREQPLL(x) ((x) << S_HSSLOFREQPLL)
41166 #define F_HSSLOFREQPLL    V_HSSLOFREQPLL(1U)
41167 
41168 #define S_HSSLOFREQ2PLL    5
41169 #define V_HSSLOFREQ2PLL(x) ((x) << S_HSSLOFREQ2PLL)
41170 #define F_HSSLOFREQ2PLL    V_HSSLOFREQ2PLL(1U)
41171 
41172 #define S_HSSEXTC16SEL    4
41173 #define V_HSSEXTC16SEL(x) ((x) << S_HSSEXTC16SEL)
41174 #define F_HSSEXTC16SEL    V_HSSEXTC16SEL(1U)
41175 
41176 #define S_HSSRSTCONFIG    1
41177 #define M_HSSRSTCONFIG    0x7U
41178 #define V_HSSRSTCONFIG(x) ((x) << S_HSSRSTCONFIG)
41179 #define G_HSSRSTCONFIG(x) (((x) >> S_HSSRSTCONFIG) & M_HSSRSTCONFIG)
41180 
41181 #define S_HSSPRBSEN    0
41182 #define V_HSSPRBSEN(x) ((x) << S_HSSPRBSEN)
41183 #define F_HSSPRBSEN    V_HSSPRBSEN(1U)
41184 
41185 #define A_XGMAC_PORT_HSS_CFG1 0x10e4
41186 
41187 #define S_RXDPRBSRST    28
41188 #define V_RXDPRBSRST(x) ((x) << S_RXDPRBSRST)
41189 #define F_RXDPRBSRST    V_RXDPRBSRST(1U)
41190 
41191 #define S_RXDPRBSEN    27
41192 #define V_RXDPRBSEN(x) ((x) << S_RXDPRBSEN)
41193 #define F_RXDPRBSEN    V_RXDPRBSEN(1U)
41194 
41195 #define S_RXDPRBSFRCERR    26
41196 #define V_RXDPRBSFRCERR(x) ((x) << S_RXDPRBSFRCERR)
41197 #define F_RXDPRBSFRCERR    V_RXDPRBSFRCERR(1U)
41198 
41199 #define S_TXDPRBSRST    25
41200 #define V_TXDPRBSRST(x) ((x) << S_TXDPRBSRST)
41201 #define F_TXDPRBSRST    V_TXDPRBSRST(1U)
41202 
41203 #define S_TXDPRBSEN    24
41204 #define V_TXDPRBSEN(x) ((x) << S_TXDPRBSEN)
41205 #define F_TXDPRBSEN    V_TXDPRBSEN(1U)
41206 
41207 #define S_RXCPRBSRST    20
41208 #define V_RXCPRBSRST(x) ((x) << S_RXCPRBSRST)
41209 #define F_RXCPRBSRST    V_RXCPRBSRST(1U)
41210 
41211 #define S_RXCPRBSEN    19
41212 #define V_RXCPRBSEN(x) ((x) << S_RXCPRBSEN)
41213 #define F_RXCPRBSEN    V_RXCPRBSEN(1U)
41214 
41215 #define S_RXCPRBSFRCERR    18
41216 #define V_RXCPRBSFRCERR(x) ((x) << S_RXCPRBSFRCERR)
41217 #define F_RXCPRBSFRCERR    V_RXCPRBSFRCERR(1U)
41218 
41219 #define S_TXCPRBSRST    17
41220 #define V_TXCPRBSRST(x) ((x) << S_TXCPRBSRST)
41221 #define F_TXCPRBSRST    V_TXCPRBSRST(1U)
41222 
41223 #define S_TXCPRBSEN    16
41224 #define V_TXCPRBSEN(x) ((x) << S_TXCPRBSEN)
41225 #define F_TXCPRBSEN    V_TXCPRBSEN(1U)
41226 
41227 #define S_RXBPRBSRST    12
41228 #define V_RXBPRBSRST(x) ((x) << S_RXBPRBSRST)
41229 #define F_RXBPRBSRST    V_RXBPRBSRST(1U)
41230 
41231 #define S_RXBPRBSEN    11
41232 #define V_RXBPRBSEN(x) ((x) << S_RXBPRBSEN)
41233 #define F_RXBPRBSEN    V_RXBPRBSEN(1U)
41234 
41235 #define S_RXBPRBSFRCERR    10
41236 #define V_RXBPRBSFRCERR(x) ((x) << S_RXBPRBSFRCERR)
41237 #define F_RXBPRBSFRCERR    V_RXBPRBSFRCERR(1U)
41238 
41239 #define S_TXBPRBSRST    9
41240 #define V_TXBPRBSRST(x) ((x) << S_TXBPRBSRST)
41241 #define F_TXBPRBSRST    V_TXBPRBSRST(1U)
41242 
41243 #define S_TXBPRBSEN    8
41244 #define V_TXBPRBSEN(x) ((x) << S_TXBPRBSEN)
41245 #define F_TXBPRBSEN    V_TXBPRBSEN(1U)
41246 
41247 #define S_RXAPRBSRST    4
41248 #define V_RXAPRBSRST(x) ((x) << S_RXAPRBSRST)
41249 #define F_RXAPRBSRST    V_RXAPRBSRST(1U)
41250 
41251 #define S_RXAPRBSEN    3
41252 #define V_RXAPRBSEN(x) ((x) << S_RXAPRBSEN)
41253 #define F_RXAPRBSEN    V_RXAPRBSEN(1U)
41254 
41255 #define S_RXAPRBSFRCERR    2
41256 #define V_RXAPRBSFRCERR(x) ((x) << S_RXAPRBSFRCERR)
41257 #define F_RXAPRBSFRCERR    V_RXAPRBSFRCERR(1U)
41258 
41259 #define S_TXAPRBSRST    1
41260 #define V_TXAPRBSRST(x) ((x) << S_TXAPRBSRST)
41261 #define F_TXAPRBSRST    V_TXAPRBSRST(1U)
41262 
41263 #define S_TXAPRBSEN    0
41264 #define V_TXAPRBSEN(x) ((x) << S_TXAPRBSEN)
41265 #define F_TXAPRBSEN    V_TXAPRBSEN(1U)
41266 
41267 #define A_XGMAC_PORT_HSS_CFG2 0x10e8
41268 
41269 #define S_RXDDATASYNC    23
41270 #define V_RXDDATASYNC(x) ((x) << S_RXDDATASYNC)
41271 #define F_RXDDATASYNC    V_RXDDATASYNC(1U)
41272 
41273 #define S_RXCDATASYNC    22
41274 #define V_RXCDATASYNC(x) ((x) << S_RXCDATASYNC)
41275 #define F_RXCDATASYNC    V_RXCDATASYNC(1U)
41276 
41277 #define S_RXBDATASYNC    21
41278 #define V_RXBDATASYNC(x) ((x) << S_RXBDATASYNC)
41279 #define F_RXBDATASYNC    V_RXBDATASYNC(1U)
41280 
41281 #define S_RXADATASYNC    20
41282 #define V_RXADATASYNC(x) ((x) << S_RXADATASYNC)
41283 #define F_RXADATASYNC    V_RXADATASYNC(1U)
41284 
41285 #define S_RXDEARLYIN    19
41286 #define V_RXDEARLYIN(x) ((x) << S_RXDEARLYIN)
41287 #define F_RXDEARLYIN    V_RXDEARLYIN(1U)
41288 
41289 #define S_RXDLATEIN    18
41290 #define V_RXDLATEIN(x) ((x) << S_RXDLATEIN)
41291 #define F_RXDLATEIN    V_RXDLATEIN(1U)
41292 
41293 #define S_RXDPHSLOCK    17
41294 #define V_RXDPHSLOCK(x) ((x) << S_RXDPHSLOCK)
41295 #define F_RXDPHSLOCK    V_RXDPHSLOCK(1U)
41296 
41297 #define S_RXDPHSDNIN    16
41298 #define V_RXDPHSDNIN(x) ((x) << S_RXDPHSDNIN)
41299 #define F_RXDPHSDNIN    V_RXDPHSDNIN(1U)
41300 
41301 #define S_RXDPHSUPIN    15
41302 #define V_RXDPHSUPIN(x) ((x) << S_RXDPHSUPIN)
41303 #define F_RXDPHSUPIN    V_RXDPHSUPIN(1U)
41304 
41305 #define S_RXCEARLYIN    14
41306 #define V_RXCEARLYIN(x) ((x) << S_RXCEARLYIN)
41307 #define F_RXCEARLYIN    V_RXCEARLYIN(1U)
41308 
41309 #define S_RXCLATEIN    13
41310 #define V_RXCLATEIN(x) ((x) << S_RXCLATEIN)
41311 #define F_RXCLATEIN    V_RXCLATEIN(1U)
41312 
41313 #define S_RXCPHSLOCK    12
41314 #define V_RXCPHSLOCK(x) ((x) << S_RXCPHSLOCK)
41315 #define F_RXCPHSLOCK    V_RXCPHSLOCK(1U)
41316 
41317 #define S_RXCPHSDNIN    11
41318 #define V_RXCPHSDNIN(x) ((x) << S_RXCPHSDNIN)
41319 #define F_RXCPHSDNIN    V_RXCPHSDNIN(1U)
41320 
41321 #define S_RXCPHSUPIN    10
41322 #define V_RXCPHSUPIN(x) ((x) << S_RXCPHSUPIN)
41323 #define F_RXCPHSUPIN    V_RXCPHSUPIN(1U)
41324 
41325 #define S_RXBEARLYIN    9
41326 #define V_RXBEARLYIN(x) ((x) << S_RXBEARLYIN)
41327 #define F_RXBEARLYIN    V_RXBEARLYIN(1U)
41328 
41329 #define S_RXBLATEIN    8
41330 #define V_RXBLATEIN(x) ((x) << S_RXBLATEIN)
41331 #define F_RXBLATEIN    V_RXBLATEIN(1U)
41332 
41333 #define S_RXBPHSLOCK    7
41334 #define V_RXBPHSLOCK(x) ((x) << S_RXBPHSLOCK)
41335 #define F_RXBPHSLOCK    V_RXBPHSLOCK(1U)
41336 
41337 #define S_RXBPHSDNIN    6
41338 #define V_RXBPHSDNIN(x) ((x) << S_RXBPHSDNIN)
41339 #define F_RXBPHSDNIN    V_RXBPHSDNIN(1U)
41340 
41341 #define S_RXBPHSUPIN    5
41342 #define V_RXBPHSUPIN(x) ((x) << S_RXBPHSUPIN)
41343 #define F_RXBPHSUPIN    V_RXBPHSUPIN(1U)
41344 
41345 #define S_RXAEARLYIN    4
41346 #define V_RXAEARLYIN(x) ((x) << S_RXAEARLYIN)
41347 #define F_RXAEARLYIN    V_RXAEARLYIN(1U)
41348 
41349 #define S_RXALATEIN    3
41350 #define V_RXALATEIN(x) ((x) << S_RXALATEIN)
41351 #define F_RXALATEIN    V_RXALATEIN(1U)
41352 
41353 #define S_RXAPHSLOCK    2
41354 #define V_RXAPHSLOCK(x) ((x) << S_RXAPHSLOCK)
41355 #define F_RXAPHSLOCK    V_RXAPHSLOCK(1U)
41356 
41357 #define S_RXAPHSDNIN    1
41358 #define V_RXAPHSDNIN(x) ((x) << S_RXAPHSDNIN)
41359 #define F_RXAPHSDNIN    V_RXAPHSDNIN(1U)
41360 
41361 #define S_RXAPHSUPIN    0
41362 #define V_RXAPHSUPIN(x) ((x) << S_RXAPHSUPIN)
41363 #define F_RXAPHSUPIN    V_RXAPHSUPIN(1U)
41364 
41365 #define A_XGMAC_PORT_HSS_STATUS 0x10ec
41366 
41367 #define S_RXDPRBSSYNC    15
41368 #define V_RXDPRBSSYNC(x) ((x) << S_RXDPRBSSYNC)
41369 #define F_RXDPRBSSYNC    V_RXDPRBSSYNC(1U)
41370 
41371 #define S_RXCPRBSSYNC    14
41372 #define V_RXCPRBSSYNC(x) ((x) << S_RXCPRBSSYNC)
41373 #define F_RXCPRBSSYNC    V_RXCPRBSSYNC(1U)
41374 
41375 #define S_RXBPRBSSYNC    13
41376 #define V_RXBPRBSSYNC(x) ((x) << S_RXBPRBSSYNC)
41377 #define F_RXBPRBSSYNC    V_RXBPRBSSYNC(1U)
41378 
41379 #define S_RXAPRBSSYNC    12
41380 #define V_RXAPRBSSYNC(x) ((x) << S_RXAPRBSSYNC)
41381 #define F_RXAPRBSSYNC    V_RXAPRBSSYNC(1U)
41382 
41383 #define S_RXDPRBSERR    11
41384 #define V_RXDPRBSERR(x) ((x) << S_RXDPRBSERR)
41385 #define F_RXDPRBSERR    V_RXDPRBSERR(1U)
41386 
41387 #define S_RXCPRBSERR    10
41388 #define V_RXCPRBSERR(x) ((x) << S_RXCPRBSERR)
41389 #define F_RXCPRBSERR    V_RXCPRBSERR(1U)
41390 
41391 #define S_RXBPRBSERR    9
41392 #define V_RXBPRBSERR(x) ((x) << S_RXBPRBSERR)
41393 #define F_RXBPRBSERR    V_RXBPRBSERR(1U)
41394 
41395 #define S_RXAPRBSERR    8
41396 #define V_RXAPRBSERR(x) ((x) << S_RXAPRBSERR)
41397 #define F_RXAPRBSERR    V_RXAPRBSERR(1U)
41398 
41399 #define S_RXDSIGDET    7
41400 #define V_RXDSIGDET(x) ((x) << S_RXDSIGDET)
41401 #define F_RXDSIGDET    V_RXDSIGDET(1U)
41402 
41403 #define S_RXCSIGDET    6
41404 #define V_RXCSIGDET(x) ((x) << S_RXCSIGDET)
41405 #define F_RXCSIGDET    V_RXCSIGDET(1U)
41406 
41407 #define S_RXBSIGDET    5
41408 #define V_RXBSIGDET(x) ((x) << S_RXBSIGDET)
41409 #define F_RXBSIGDET    V_RXBSIGDET(1U)
41410 
41411 #define S_RXASIGDET    4
41412 #define V_RXASIGDET(x) ((x) << S_RXASIGDET)
41413 #define F_RXASIGDET    V_RXASIGDET(1U)
41414 
41415 #define S_HSSPLLLOCK    1
41416 #define V_HSSPLLLOCK(x) ((x) << S_HSSPLLLOCK)
41417 #define F_HSSPLLLOCK    V_HSSPLLLOCK(1U)
41418 
41419 #define S_HSSPRTREADY    0
41420 #define V_HSSPRTREADY(x) ((x) << S_HSSPRTREADY)
41421 #define F_HSSPRTREADY    V_HSSPRTREADY(1U)
41422 
41423 #define A_XGMAC_PORT_XGM_TX_CTRL 0x1200
41424 
41425 #define S_SENDPAUSE    2
41426 #define V_SENDPAUSE(x) ((x) << S_SENDPAUSE)
41427 #define F_SENDPAUSE    V_SENDPAUSE(1U)
41428 
41429 #define S_SENDZEROPAUSE    1
41430 #define V_SENDZEROPAUSE(x) ((x) << S_SENDZEROPAUSE)
41431 #define F_SENDZEROPAUSE    V_SENDZEROPAUSE(1U)
41432 
41433 #define S_XGM_TXEN    0
41434 #define V_XGM_TXEN(x) ((x) << S_XGM_TXEN)
41435 #define F_XGM_TXEN    V_XGM_TXEN(1U)
41436 
41437 #define A_XGMAC_PORT_XGM_TX_CFG 0x1204
41438 
41439 #define S_CRCCAL    8
41440 #define M_CRCCAL    0x3U
41441 #define V_CRCCAL(x) ((x) << S_CRCCAL)
41442 #define G_CRCCAL(x) (((x) >> S_CRCCAL) & M_CRCCAL)
41443 
41444 #define S_DISDEFIDLECNT    7
41445 #define V_DISDEFIDLECNT(x) ((x) << S_DISDEFIDLECNT)
41446 #define F_DISDEFIDLECNT    V_DISDEFIDLECNT(1U)
41447 
41448 #define S_DECAVGTXIPG    6
41449 #define V_DECAVGTXIPG(x) ((x) << S_DECAVGTXIPG)
41450 #define F_DECAVGTXIPG    V_DECAVGTXIPG(1U)
41451 
41452 #define S_UNIDIRTXEN    5
41453 #define V_UNIDIRTXEN(x) ((x) << S_UNIDIRTXEN)
41454 #define F_UNIDIRTXEN    V_UNIDIRTXEN(1U)
41455 
41456 #define S_CFGCLKSPEED    2
41457 #define M_CFGCLKSPEED    0x7U
41458 #define V_CFGCLKSPEED(x) ((x) << S_CFGCLKSPEED)
41459 #define G_CFGCLKSPEED(x) (((x) >> S_CFGCLKSPEED) & M_CFGCLKSPEED)
41460 
41461 #define S_STRETCHMODE    1
41462 #define V_STRETCHMODE(x) ((x) << S_STRETCHMODE)
41463 #define F_STRETCHMODE    V_STRETCHMODE(1U)
41464 
41465 #define S_TXPAUSEEN    0
41466 #define V_TXPAUSEEN(x) ((x) << S_TXPAUSEEN)
41467 #define F_TXPAUSEEN    V_TXPAUSEEN(1U)
41468 
41469 #define A_XGMAC_PORT_XGM_TX_PAUSE_QUANTA 0x1208
41470 
41471 #define S_TXPAUSEQUANTA    0
41472 #define M_TXPAUSEQUANTA    0xffffU
41473 #define V_TXPAUSEQUANTA(x) ((x) << S_TXPAUSEQUANTA)
41474 #define G_TXPAUSEQUANTA(x) (((x) >> S_TXPAUSEQUANTA) & M_TXPAUSEQUANTA)
41475 
41476 #define A_XGMAC_PORT_XGM_RX_CTRL 0x120c
41477 #define A_XGMAC_PORT_XGM_RX_CFG 0x1210
41478 
41479 #define S_RXCRCCAL    16
41480 #define M_RXCRCCAL    0x3U
41481 #define V_RXCRCCAL(x) ((x) << S_RXCRCCAL)
41482 #define G_RXCRCCAL(x) (((x) >> S_RXCRCCAL) & M_RXCRCCAL)
41483 
41484 #define S_STATLOCALFAULT    15
41485 #define V_STATLOCALFAULT(x) ((x) << S_STATLOCALFAULT)
41486 #define F_STATLOCALFAULT    V_STATLOCALFAULT(1U)
41487 
41488 #define S_STATREMOTEFAULT    14
41489 #define V_STATREMOTEFAULT(x) ((x) << S_STATREMOTEFAULT)
41490 #define F_STATREMOTEFAULT    V_STATREMOTEFAULT(1U)
41491 
41492 #define S_LENERRFRAMEDIS    13
41493 #define V_LENERRFRAMEDIS(x) ((x) << S_LENERRFRAMEDIS)
41494 #define F_LENERRFRAMEDIS    V_LENERRFRAMEDIS(1U)
41495 
41496 #define S_CON802_3PREAMBLE    12
41497 #define V_CON802_3PREAMBLE(x) ((x) << S_CON802_3PREAMBLE)
41498 #define F_CON802_3PREAMBLE    V_CON802_3PREAMBLE(1U)
41499 
41500 #define S_ENNON802_3PREAMBLE    11
41501 #define V_ENNON802_3PREAMBLE(x) ((x) << S_ENNON802_3PREAMBLE)
41502 #define F_ENNON802_3PREAMBLE    V_ENNON802_3PREAMBLE(1U)
41503 
41504 #define S_COPYPREAMBLE    10
41505 #define V_COPYPREAMBLE(x) ((x) << S_COPYPREAMBLE)
41506 #define F_COPYPREAMBLE    V_COPYPREAMBLE(1U)
41507 
41508 #define S_DISPAUSEFRAMES    9
41509 #define V_DISPAUSEFRAMES(x) ((x) << S_DISPAUSEFRAMES)
41510 #define F_DISPAUSEFRAMES    V_DISPAUSEFRAMES(1U)
41511 
41512 #define S_EN1536BFRAMES    8
41513 #define V_EN1536BFRAMES(x) ((x) << S_EN1536BFRAMES)
41514 #define F_EN1536BFRAMES    V_EN1536BFRAMES(1U)
41515 
41516 #define S_ENJUMBO    7
41517 #define V_ENJUMBO(x) ((x) << S_ENJUMBO)
41518 #define F_ENJUMBO    V_ENJUMBO(1U)
41519 
41520 #define S_RMFCS    6
41521 #define V_RMFCS(x) ((x) << S_RMFCS)
41522 #define F_RMFCS    V_RMFCS(1U)
41523 
41524 #define S_DISNONVLAN    5
41525 #define V_DISNONVLAN(x) ((x) << S_DISNONVLAN)
41526 #define F_DISNONVLAN    V_DISNONVLAN(1U)
41527 
41528 #define S_ENEXTMATCH    4
41529 #define V_ENEXTMATCH(x) ((x) << S_ENEXTMATCH)
41530 #define F_ENEXTMATCH    V_ENEXTMATCH(1U)
41531 
41532 #define S_ENHASHUCAST    3
41533 #define V_ENHASHUCAST(x) ((x) << S_ENHASHUCAST)
41534 #define F_ENHASHUCAST    V_ENHASHUCAST(1U)
41535 
41536 #define S_ENHASHMCAST    2
41537 #define V_ENHASHMCAST(x) ((x) << S_ENHASHMCAST)
41538 #define F_ENHASHMCAST    V_ENHASHMCAST(1U)
41539 
41540 #define S_DISBCAST    1
41541 #define V_DISBCAST(x) ((x) << S_DISBCAST)
41542 #define F_DISBCAST    V_DISBCAST(1U)
41543 
41544 #define S_COPYALLFRAMES    0
41545 #define V_COPYALLFRAMES(x) ((x) << S_COPYALLFRAMES)
41546 #define F_COPYALLFRAMES    V_COPYALLFRAMES(1U)
41547 
41548 #define A_XGMAC_PORT_XGM_RX_HASH_LOW 0x1214
41549 #define A_XGMAC_PORT_XGM_RX_HASH_HIGH 0x1218
41550 #define A_XGMAC_PORT_XGM_RX_EXACT_MATCH_LOW_1 0x121c
41551 #define A_XGMAC_PORT_XGM_RX_EXACT_MATCH_HIGH_1 0x1220
41552 
41553 #define S_ADDRESS_HIGH    0
41554 #define M_ADDRESS_HIGH    0xffffU
41555 #define V_ADDRESS_HIGH(x) ((x) << S_ADDRESS_HIGH)
41556 #define G_ADDRESS_HIGH(x) (((x) >> S_ADDRESS_HIGH) & M_ADDRESS_HIGH)
41557 
41558 #define A_XGMAC_PORT_XGM_RX_EXACT_MATCH_LOW_2 0x1224
41559 #define A_XGMAC_PORT_XGM_RX_EXACT_MATCH_HIGH_2 0x1228
41560 #define A_XGMAC_PORT_XGM_RX_EXACT_MATCH_LOW_3 0x122c
41561 #define A_XGMAC_PORT_XGM_RX_EXACT_MATCH_HIGH_3 0x1230
41562 #define A_XGMAC_PORT_XGM_RX_EXACT_MATCH_LOW_4 0x1234
41563 #define A_XGMAC_PORT_XGM_RX_EXACT_MATCH_HIGH_4 0x1238
41564 #define A_XGMAC_PORT_XGM_RX_EXACT_MATCH_LOW_5 0x123c
41565 #define A_XGMAC_PORT_XGM_RX_EXACT_MATCH_HIGH_5 0x1240
41566 #define A_XGMAC_PORT_XGM_RX_EXACT_MATCH_LOW_6 0x1244
41567 #define A_XGMAC_PORT_XGM_RX_EXACT_MATCH_HIGH_6 0x1248
41568 #define A_XGMAC_PORT_XGM_RX_EXACT_MATCH_LOW_7 0x124c
41569 #define A_XGMAC_PORT_XGM_RX_EXACT_MATCH_HIGH_7 0x1250
41570 #define A_XGMAC_PORT_XGM_RX_EXACT_MATCH_LOW_8 0x1254
41571 #define A_XGMAC_PORT_XGM_RX_EXACT_MATCH_HIGH_8 0x1258
41572 #define A_XGMAC_PORT_XGM_RX_TYPE_MATCH_1 0x125c
41573 
41574 #define S_ENTYPEMATCH    31
41575 #define V_ENTYPEMATCH(x) ((x) << S_ENTYPEMATCH)
41576 #define F_ENTYPEMATCH    V_ENTYPEMATCH(1U)
41577 
41578 #define S_TYPE    0
41579 #define M_TYPE    0xffffU
41580 #define V_TYPE(x) ((x) << S_TYPE)
41581 #define G_TYPE(x) (((x) >> S_TYPE) & M_TYPE)
41582 
41583 #define A_XGMAC_PORT_XGM_RX_TYPE_MATCH_2 0x1260
41584 #define A_XGMAC_PORT_XGM_RX_TYPE_MATCH_3 0x1264
41585 #define A_XGMAC_PORT_XGM_RX_TYPE_MATCH_4 0x1268
41586 #define A_XGMAC_PORT_XGM_INT_STATUS 0x126c
41587 
41588 #define S_XGMIIEXTINT    10
41589 #define V_XGMIIEXTINT(x) ((x) << S_XGMIIEXTINT)
41590 #define F_XGMIIEXTINT    V_XGMIIEXTINT(1U)
41591 
41592 #define S_LINKFAULTCHANGE    9
41593 #define V_LINKFAULTCHANGE(x) ((x) << S_LINKFAULTCHANGE)
41594 #define F_LINKFAULTCHANGE    V_LINKFAULTCHANGE(1U)
41595 
41596 #define S_PHYFRAMECOMPLETE    8
41597 #define V_PHYFRAMECOMPLETE(x) ((x) << S_PHYFRAMECOMPLETE)
41598 #define F_PHYFRAMECOMPLETE    V_PHYFRAMECOMPLETE(1U)
41599 
41600 #define S_PAUSEFRAMETXMT    7
41601 #define V_PAUSEFRAMETXMT(x) ((x) << S_PAUSEFRAMETXMT)
41602 #define F_PAUSEFRAMETXMT    V_PAUSEFRAMETXMT(1U)
41603 
41604 #define S_PAUSECNTRTIMEOUT    6
41605 #define V_PAUSECNTRTIMEOUT(x) ((x) << S_PAUSECNTRTIMEOUT)
41606 #define F_PAUSECNTRTIMEOUT    V_PAUSECNTRTIMEOUT(1U)
41607 
41608 #define S_NON0PAUSERCVD    5
41609 #define V_NON0PAUSERCVD(x) ((x) << S_NON0PAUSERCVD)
41610 #define F_NON0PAUSERCVD    V_NON0PAUSERCVD(1U)
41611 
41612 #define S_STATOFLOW    4
41613 #define V_STATOFLOW(x) ((x) << S_STATOFLOW)
41614 #define F_STATOFLOW    V_STATOFLOW(1U)
41615 
41616 #define S_TXERRFIFO    3
41617 #define V_TXERRFIFO(x) ((x) << S_TXERRFIFO)
41618 #define F_TXERRFIFO    V_TXERRFIFO(1U)
41619 
41620 #define S_TXUFLOW    2
41621 #define V_TXUFLOW(x) ((x) << S_TXUFLOW)
41622 #define F_TXUFLOW    V_TXUFLOW(1U)
41623 
41624 #define S_FRAMETXMT    1
41625 #define V_FRAMETXMT(x) ((x) << S_FRAMETXMT)
41626 #define F_FRAMETXMT    V_FRAMETXMT(1U)
41627 
41628 #define S_FRAMERCVD    0
41629 #define V_FRAMERCVD(x) ((x) << S_FRAMERCVD)
41630 #define F_FRAMERCVD    V_FRAMERCVD(1U)
41631 
41632 #define A_XGMAC_PORT_XGM_INT_MASK 0x1270
41633 #define A_XGMAC_PORT_XGM_INT_EN 0x1274
41634 #define A_XGMAC_PORT_XGM_INT_DISABLE 0x1278
41635 #define A_XGMAC_PORT_XGM_TX_PAUSE_TIMER 0x127c
41636 
41637 #define S_CURPAUSETIMER    0
41638 #define M_CURPAUSETIMER    0xffffU
41639 #define V_CURPAUSETIMER(x) ((x) << S_CURPAUSETIMER)
41640 #define G_CURPAUSETIMER(x) (((x) >> S_CURPAUSETIMER) & M_CURPAUSETIMER)
41641 
41642 #define A_XGMAC_PORT_XGM_STAT_CTRL 0x1280
41643 
41644 #define S_READSNPSHOT    4
41645 #define V_READSNPSHOT(x) ((x) << S_READSNPSHOT)
41646 #define F_READSNPSHOT    V_READSNPSHOT(1U)
41647 
41648 #define S_TAKESNPSHOT    3
41649 #define V_TAKESNPSHOT(x) ((x) << S_TAKESNPSHOT)
41650 #define F_TAKESNPSHOT    V_TAKESNPSHOT(1U)
41651 
41652 #define S_CLRSTATS    2
41653 #define V_CLRSTATS(x) ((x) << S_CLRSTATS)
41654 #define F_CLRSTATS    V_CLRSTATS(1U)
41655 
41656 #define S_INCRSTATS    1
41657 #define V_INCRSTATS(x) ((x) << S_INCRSTATS)
41658 #define F_INCRSTATS    V_INCRSTATS(1U)
41659 
41660 #define S_ENTESTMODEWR    0
41661 #define V_ENTESTMODEWR(x) ((x) << S_ENTESTMODEWR)
41662 #define F_ENTESTMODEWR    V_ENTESTMODEWR(1U)
41663 
41664 #define A_XGMAC_PORT_XGM_MDIO_CTRL 0x1284
41665 
41666 #define S_FRAMETYPE    30
41667 #define M_FRAMETYPE    0x3U
41668 #define V_FRAMETYPE(x) ((x) << S_FRAMETYPE)
41669 #define G_FRAMETYPE(x) (((x) >> S_FRAMETYPE) & M_FRAMETYPE)
41670 
41671 #define S_OPERATION    28
41672 #define M_OPERATION    0x3U
41673 #define V_OPERATION(x) ((x) << S_OPERATION)
41674 #define G_OPERATION(x) (((x) >> S_OPERATION) & M_OPERATION)
41675 
41676 #define S_PORTADDR    23
41677 #define M_PORTADDR    0x1fU
41678 #define V_PORTADDR(x) ((x) << S_PORTADDR)
41679 #define G_PORTADDR(x) (((x) >> S_PORTADDR) & M_PORTADDR)
41680 
41681 #define S_DEVADDR    18
41682 #define M_DEVADDR    0x1fU
41683 #define V_DEVADDR(x) ((x) << S_DEVADDR)
41684 #define G_DEVADDR(x) (((x) >> S_DEVADDR) & M_DEVADDR)
41685 
41686 #define S_RESRV    16
41687 #define M_RESRV    0x3U
41688 #define V_RESRV(x) ((x) << S_RESRV)
41689 #define G_RESRV(x) (((x) >> S_RESRV) & M_RESRV)
41690 
41691 #define S_DATA    0
41692 #define M_DATA    0xffffU
41693 #define V_DATA(x) ((x) << S_DATA)
41694 #define G_DATA(x) (((x) >> S_DATA) & M_DATA)
41695 
41696 #define A_XGMAC_PORT_XGM_MODULE_ID 0x12fc
41697 
41698 #define S_MODULEID    16
41699 #define M_MODULEID    0xffffU
41700 #define V_MODULEID(x) ((x) << S_MODULEID)
41701 #define G_MODULEID(x) (((x) >> S_MODULEID) & M_MODULEID)
41702 
41703 #define S_MODULEREV    0
41704 #define M_MODULEREV    0xffffU
41705 #define V_MODULEREV(x) ((x) << S_MODULEREV)
41706 #define G_MODULEREV(x) (((x) >> S_MODULEREV) & M_MODULEREV)
41707 
41708 #define A_XGMAC_PORT_XGM_STAT_TX_BYTE_LOW 0x1300
41709 #define A_XGMAC_PORT_XGM_STAT_TX_BYTE_HIGH 0x1304
41710 
41711 #define S_TXBYTES_HIGH    0
41712 #define M_TXBYTES_HIGH    0x1fffU
41713 #define V_TXBYTES_HIGH(x) ((x) << S_TXBYTES_HIGH)
41714 #define G_TXBYTES_HIGH(x) (((x) >> S_TXBYTES_HIGH) & M_TXBYTES_HIGH)
41715 
41716 #define A_XGMAC_PORT_XGM_STAT_TX_FRAME_LOW 0x1308
41717 #define A_XGMAC_PORT_XGM_STAT_TX_FRAME_HIGH 0x130c
41718 
41719 #define S_TXFRAMES_HIGH    0
41720 #define M_TXFRAMES_HIGH    0xfU
41721 #define V_TXFRAMES_HIGH(x) ((x) << S_TXFRAMES_HIGH)
41722 #define G_TXFRAMES_HIGH(x) (((x) >> S_TXFRAMES_HIGH) & M_TXFRAMES_HIGH)
41723 
41724 #define A_XGMAC_PORT_XGM_STAT_TX_BCAST 0x1310
41725 #define A_XGMAC_PORT_XGM_STAT_TX_MCAST 0x1314
41726 #define A_XGMAC_PORT_XGM_STAT_TX_PAUSE 0x1318
41727 #define A_XGMAC_PORT_XGM_STAT_TX_64B_FRAMES 0x131c
41728 #define A_XGMAC_PORT_XGM_STAT_TX_65_127B_FRAMES 0x1320
41729 #define A_XGMAC_PORT_XGM_STAT_TX_128_255B_FRAMES 0x1324
41730 #define A_XGMAC_PORT_XGM_STAT_TX_256_511B_FRAMES 0x1328
41731 #define A_XGMAC_PORT_XGM_STAT_TX_512_1023B_FRAMES 0x132c
41732 #define A_XGMAC_PORT_XGM_STAT_TX_1024_1518B_FRAMES 0x1330
41733 #define A_XGMAC_PORT_XGM_STAT_TX_1519_MAXB_FRAMES 0x1334
41734 #define A_XGMAC_PORT_XGM_STAT_TX_ERR_FRAMES 0x1338
41735 #define A_XGMAC_PORT_XGM_STAT_RX_BYTES_LOW 0x133c
41736 #define A_XGMAC_PORT_XGM_STAT_RX_BYTES_HIGH 0x1340
41737 
41738 #define S_RXBYTES_HIGH    0
41739 #define M_RXBYTES_HIGH    0x1fffU
41740 #define V_RXBYTES_HIGH(x) ((x) << S_RXBYTES_HIGH)
41741 #define G_RXBYTES_HIGH(x) (((x) >> S_RXBYTES_HIGH) & M_RXBYTES_HIGH)
41742 
41743 #define A_XGMAC_PORT_XGM_STAT_RX_FRAMES_LOW 0x1344
41744 #define A_XGMAC_PORT_XGM_STAT_RX_FRAMES_HIGH 0x1348
41745 
41746 #define S_RXFRAMES_HIGH    0
41747 #define M_RXFRAMES_HIGH    0xfU
41748 #define V_RXFRAMES_HIGH(x) ((x) << S_RXFRAMES_HIGH)
41749 #define G_RXFRAMES_HIGH(x) (((x) >> S_RXFRAMES_HIGH) & M_RXFRAMES_HIGH)
41750 
41751 #define A_XGMAC_PORT_XGM_STAT_RX_BCAST_FRAMES 0x134c
41752 #define A_XGMAC_PORT_XGM_STAT_RX_MCAST_FRAMES 0x1350
41753 #define A_XGMAC_PORT_XGM_STAT_RX_PAUSE_FRAMES 0x1354
41754 
41755 #define S_RXPAUSEFRAMES    0
41756 #define M_RXPAUSEFRAMES    0xffffU
41757 #define V_RXPAUSEFRAMES(x) ((x) << S_RXPAUSEFRAMES)
41758 #define G_RXPAUSEFRAMES(x) (((x) >> S_RXPAUSEFRAMES) & M_RXPAUSEFRAMES)
41759 
41760 #define A_XGMAC_PORT_XGM_STAT_RX_64B_FRAMES 0x1358
41761 #define A_XGMAC_PORT_XGM_STAT_RX_65_127B_FRAMES 0x135c
41762 #define A_XGMAC_PORT_XGM_STAT_RX_128_255B_FRAMES 0x1360
41763 #define A_XGMAC_PORT_XGM_STAT_RX_256_511B_FRAMES 0x1364
41764 #define A_XGMAC_PORT_XGM_STAT_RX_512_1023B_FRAMES 0x1368
41765 #define A_XGMAC_PORT_XGM_STAT_RX_1024_1518B_FRAMES 0x136c
41766 #define A_XGMAC_PORT_XGM_STAT_RX_1519_MAXB_FRAMES 0x1370
41767 #define A_XGMAC_PORT_XGM_STAT_RX_SHORT_FRAMES 0x1374
41768 
41769 #define S_RXSHORTFRAMES    0
41770 #define M_RXSHORTFRAMES    0xffffU
41771 #define V_RXSHORTFRAMES(x) ((x) << S_RXSHORTFRAMES)
41772 #define G_RXSHORTFRAMES(x) (((x) >> S_RXSHORTFRAMES) & M_RXSHORTFRAMES)
41773 
41774 #define A_XGMAC_PORT_XGM_STAT_RX_OVERSIZE_FRAMES 0x1378
41775 
41776 #define S_RXOVERSIZEFRAMES    0
41777 #define M_RXOVERSIZEFRAMES    0xffffU
41778 #define V_RXOVERSIZEFRAMES(x) ((x) << S_RXOVERSIZEFRAMES)
41779 #define G_RXOVERSIZEFRAMES(x) (((x) >> S_RXOVERSIZEFRAMES) & M_RXOVERSIZEFRAMES)
41780 
41781 #define A_XGMAC_PORT_XGM_STAT_RX_JABBER_FRAMES 0x137c
41782 
41783 #define S_RXJABBERFRAMES    0
41784 #define M_RXJABBERFRAMES    0xffffU
41785 #define V_RXJABBERFRAMES(x) ((x) << S_RXJABBERFRAMES)
41786 #define G_RXJABBERFRAMES(x) (((x) >> S_RXJABBERFRAMES) & M_RXJABBERFRAMES)
41787 
41788 #define A_XGMAC_PORT_XGM_STAT_RX_CRC_ERR_FRAMES 0x1380
41789 
41790 #define S_RXCRCERRFRAMES    0
41791 #define M_RXCRCERRFRAMES    0xffffU
41792 #define V_RXCRCERRFRAMES(x) ((x) << S_RXCRCERRFRAMES)
41793 #define G_RXCRCERRFRAMES(x) (((x) >> S_RXCRCERRFRAMES) & M_RXCRCERRFRAMES)
41794 
41795 #define A_XGMAC_PORT_XGM_STAT_RX_LENGTH_ERR_FRAMES 0x1384
41796 
41797 #define S_RXLENGTHERRFRAMES    0
41798 #define M_RXLENGTHERRFRAMES    0xffffU
41799 #define V_RXLENGTHERRFRAMES(x) ((x) << S_RXLENGTHERRFRAMES)
41800 #define G_RXLENGTHERRFRAMES(x) (((x) >> S_RXLENGTHERRFRAMES) & M_RXLENGTHERRFRAMES)
41801 
41802 #define A_XGMAC_PORT_XGM_STAT_RX_SYM_CODE_ERR_FRAMES 0x1388
41803 
41804 #define S_RXSYMCODEERRFRAMES    0
41805 #define M_RXSYMCODEERRFRAMES    0xffffU
41806 #define V_RXSYMCODEERRFRAMES(x) ((x) << S_RXSYMCODEERRFRAMES)
41807 #define G_RXSYMCODEERRFRAMES(x) (((x) >> S_RXSYMCODEERRFRAMES) & M_RXSYMCODEERRFRAMES)
41808 
41809 #define A_XGMAC_PORT_XAUI_CTRL 0x1400
41810 
41811 #define S_POLARITY_INV_RX    8
41812 #define M_POLARITY_INV_RX    0xfU
41813 #define V_POLARITY_INV_RX(x) ((x) << S_POLARITY_INV_RX)
41814 #define G_POLARITY_INV_RX(x) (((x) >> S_POLARITY_INV_RX) & M_POLARITY_INV_RX)
41815 
41816 #define S_POLARITY_INV_TX    4
41817 #define M_POLARITY_INV_TX    0xfU
41818 #define V_POLARITY_INV_TX(x) ((x) << S_POLARITY_INV_TX)
41819 #define G_POLARITY_INV_TX(x) (((x) >> S_POLARITY_INV_TX) & M_POLARITY_INV_TX)
41820 
41821 #define S_TEST_SEL    2
41822 #define M_TEST_SEL    0x3U
41823 #define V_TEST_SEL(x) ((x) << S_TEST_SEL)
41824 #define G_TEST_SEL(x) (((x) >> S_TEST_SEL) & M_TEST_SEL)
41825 
41826 #define S_TEST_EN    0
41827 #define V_TEST_EN(x) ((x) << S_TEST_EN)
41828 #define F_TEST_EN    V_TEST_EN(1U)
41829 
41830 #define A_XGMAC_PORT_XAUI_STATUS 0x1404
41831 
41832 #define S_DECODE_ERROR    12
41833 #define M_DECODE_ERROR    0xffU
41834 #define V_DECODE_ERROR(x) ((x) << S_DECODE_ERROR)
41835 #define G_DECODE_ERROR(x) (((x) >> S_DECODE_ERROR) & M_DECODE_ERROR)
41836 
41837 #define S_LANE3_CTC_STATUS    11
41838 #define V_LANE3_CTC_STATUS(x) ((x) << S_LANE3_CTC_STATUS)
41839 #define F_LANE3_CTC_STATUS    V_LANE3_CTC_STATUS(1U)
41840 
41841 #define S_LANE2_CTC_STATUS    10
41842 #define V_LANE2_CTC_STATUS(x) ((x) << S_LANE2_CTC_STATUS)
41843 #define F_LANE2_CTC_STATUS    V_LANE2_CTC_STATUS(1U)
41844 
41845 #define S_LANE1_CTC_STATUS    9
41846 #define V_LANE1_CTC_STATUS(x) ((x) << S_LANE1_CTC_STATUS)
41847 #define F_LANE1_CTC_STATUS    V_LANE1_CTC_STATUS(1U)
41848 
41849 #define S_LANE0_CTC_STATUS    8
41850 #define V_LANE0_CTC_STATUS(x) ((x) << S_LANE0_CTC_STATUS)
41851 #define F_LANE0_CTC_STATUS    V_LANE0_CTC_STATUS(1U)
41852 
41853 #define S_ALIGN_STATUS    4
41854 #define V_ALIGN_STATUS(x) ((x) << S_ALIGN_STATUS)
41855 #define F_ALIGN_STATUS    V_ALIGN_STATUS(1U)
41856 
41857 #define S_LANE3_SYNC_STATUS    3
41858 #define V_LANE3_SYNC_STATUS(x) ((x) << S_LANE3_SYNC_STATUS)
41859 #define F_LANE3_SYNC_STATUS    V_LANE3_SYNC_STATUS(1U)
41860 
41861 #define S_LANE2_SYNC_STATUS    2
41862 #define V_LANE2_SYNC_STATUS(x) ((x) << S_LANE2_SYNC_STATUS)
41863 #define F_LANE2_SYNC_STATUS    V_LANE2_SYNC_STATUS(1U)
41864 
41865 #define S_LANE1_SYNC_STATUS    1
41866 #define V_LANE1_SYNC_STATUS(x) ((x) << S_LANE1_SYNC_STATUS)
41867 #define F_LANE1_SYNC_STATUS    V_LANE1_SYNC_STATUS(1U)
41868 
41869 #define S_LANE0_SYNC_STATUS    0
41870 #define V_LANE0_SYNC_STATUS(x) ((x) << S_LANE0_SYNC_STATUS)
41871 #define F_LANE0_SYNC_STATUS    V_LANE0_SYNC_STATUS(1U)
41872 
41873 #define A_XGMAC_PORT_PCSR_CTRL 0x1500
41874 
41875 #define S_RX_CLK_SPEED    7
41876 #define V_RX_CLK_SPEED(x) ((x) << S_RX_CLK_SPEED)
41877 #define F_RX_CLK_SPEED    V_RX_CLK_SPEED(1U)
41878 
41879 #define S_SCRBYPASS    6
41880 #define V_SCRBYPASS(x) ((x) << S_SCRBYPASS)
41881 #define F_SCRBYPASS    V_SCRBYPASS(1U)
41882 
41883 #define S_FECERRINDEN    5
41884 #define V_FECERRINDEN(x) ((x) << S_FECERRINDEN)
41885 #define F_FECERRINDEN    V_FECERRINDEN(1U)
41886 
41887 #define S_FECEN    4
41888 #define V_FECEN(x) ((x) << S_FECEN)
41889 #define F_FECEN    V_FECEN(1U)
41890 
41891 #define S_TESTSEL    2
41892 #define M_TESTSEL    0x3U
41893 #define V_TESTSEL(x) ((x) << S_TESTSEL)
41894 #define G_TESTSEL(x) (((x) >> S_TESTSEL) & M_TESTSEL)
41895 
41896 #define S_SCRLOOPEN    1
41897 #define V_SCRLOOPEN(x) ((x) << S_SCRLOOPEN)
41898 #define F_SCRLOOPEN    V_SCRLOOPEN(1U)
41899 
41900 #define S_XGMIILOOPEN    0
41901 #define V_XGMIILOOPEN(x) ((x) << S_XGMIILOOPEN)
41902 #define F_XGMIILOOPEN    V_XGMIILOOPEN(1U)
41903 
41904 #define A_XGMAC_PORT_PCSR_TXTEST_CTRL 0x1510
41905 
41906 #define S_TX_PRBS9_EN    4
41907 #define V_TX_PRBS9_EN(x) ((x) << S_TX_PRBS9_EN)
41908 #define F_TX_PRBS9_EN    V_TX_PRBS9_EN(1U)
41909 
41910 #define S_TX_PRBS31_EN    3
41911 #define V_TX_PRBS31_EN(x) ((x) << S_TX_PRBS31_EN)
41912 #define F_TX_PRBS31_EN    V_TX_PRBS31_EN(1U)
41913 
41914 #define S_TX_TST_DAT_SEL    2
41915 #define V_TX_TST_DAT_SEL(x) ((x) << S_TX_TST_DAT_SEL)
41916 #define F_TX_TST_DAT_SEL    V_TX_TST_DAT_SEL(1U)
41917 
41918 #define S_TX_TST_SEL    1
41919 #define V_TX_TST_SEL(x) ((x) << S_TX_TST_SEL)
41920 #define F_TX_TST_SEL    V_TX_TST_SEL(1U)
41921 
41922 #define S_TX_TST_EN    0
41923 #define V_TX_TST_EN(x) ((x) << S_TX_TST_EN)
41924 #define F_TX_TST_EN    V_TX_TST_EN(1U)
41925 
41926 #define A_XGMAC_PORT_PCSR_TXTEST_SEEDA_LOWER 0x1514
41927 #define A_XGMAC_PORT_PCSR_TXTEST_SEEDA_UPPER 0x1518
41928 
41929 #define S_SEEDA_UPPER    0
41930 #define M_SEEDA_UPPER    0x3ffffffU
41931 #define V_SEEDA_UPPER(x) ((x) << S_SEEDA_UPPER)
41932 #define G_SEEDA_UPPER(x) (((x) >> S_SEEDA_UPPER) & M_SEEDA_UPPER)
41933 
41934 #define A_XGMAC_PORT_PCSR_TXTEST_SEEDB_LOWER 0x152c
41935 #define A_XGMAC_PORT_PCSR_TXTEST_SEEDB_UPPER 0x1530
41936 
41937 #define S_SEEDB_UPPER    0
41938 #define M_SEEDB_UPPER    0x3ffffffU
41939 #define V_SEEDB_UPPER(x) ((x) << S_SEEDB_UPPER)
41940 #define G_SEEDB_UPPER(x) (((x) >> S_SEEDB_UPPER) & M_SEEDB_UPPER)
41941 
41942 #define A_XGMAC_PORT_PCSR_RXTEST_CTRL 0x153c
41943 
41944 #define S_TPTER_CNT_RST    7
41945 #define V_TPTER_CNT_RST(x) ((x) << S_TPTER_CNT_RST)
41946 #define F_TPTER_CNT_RST    V_TPTER_CNT_RST(1U)
41947 
41948 #define S_TEST_CNT_125US    6
41949 #define V_TEST_CNT_125US(x) ((x) << S_TEST_CNT_125US)
41950 #define F_TEST_CNT_125US    V_TEST_CNT_125US(1U)
41951 
41952 #define S_TEST_CNT_PRE    5
41953 #define V_TEST_CNT_PRE(x) ((x) << S_TEST_CNT_PRE)
41954 #define F_TEST_CNT_PRE    V_TEST_CNT_PRE(1U)
41955 
41956 #define S_BER_CNT_RST    4
41957 #define V_BER_CNT_RST(x) ((x) << S_BER_CNT_RST)
41958 #define F_BER_CNT_RST    V_BER_CNT_RST(1U)
41959 
41960 #define S_ERR_BLK_CNT_RST    3
41961 #define V_ERR_BLK_CNT_RST(x) ((x) << S_ERR_BLK_CNT_RST)
41962 #define F_ERR_BLK_CNT_RST    V_ERR_BLK_CNT_RST(1U)
41963 
41964 #define S_RX_PRBS31_EN    2
41965 #define V_RX_PRBS31_EN(x) ((x) << S_RX_PRBS31_EN)
41966 #define F_RX_PRBS31_EN    V_RX_PRBS31_EN(1U)
41967 
41968 #define S_RX_TST_DAT_SEL    1
41969 #define V_RX_TST_DAT_SEL(x) ((x) << S_RX_TST_DAT_SEL)
41970 #define F_RX_TST_DAT_SEL    V_RX_TST_DAT_SEL(1U)
41971 
41972 #define S_RX_TST_EN    0
41973 #define V_RX_TST_EN(x) ((x) << S_RX_TST_EN)
41974 #define F_RX_TST_EN    V_RX_TST_EN(1U)
41975 
41976 #define A_XGMAC_PORT_PCSR_STATUS 0x1550
41977 
41978 #define S_ERR_BLK_CNT    16
41979 #define M_ERR_BLK_CNT    0xffU
41980 #define V_ERR_BLK_CNT(x) ((x) << S_ERR_BLK_CNT)
41981 #define G_ERR_BLK_CNT(x) (((x) >> S_ERR_BLK_CNT) & M_ERR_BLK_CNT)
41982 
41983 #define S_BER_COUNT    8
41984 #define M_BER_COUNT    0x3fU
41985 #define V_BER_COUNT(x) ((x) << S_BER_COUNT)
41986 #define G_BER_COUNT(x) (((x) >> S_BER_COUNT) & M_BER_COUNT)
41987 
41988 #define S_HI_BER    2
41989 #define V_HI_BER(x) ((x) << S_HI_BER)
41990 #define F_HI_BER    V_HI_BER(1U)
41991 
41992 #define S_RX_FAULT    1
41993 #define V_RX_FAULT(x) ((x) << S_RX_FAULT)
41994 #define F_RX_FAULT    V_RX_FAULT(1U)
41995 
41996 #define S_TX_FAULT    0
41997 #define V_TX_FAULT(x) ((x) << S_TX_FAULT)
41998 #define F_TX_FAULT    V_TX_FAULT(1U)
41999 
42000 #define A_XGMAC_PORT_PCSR_TEST_STATUS 0x1554
42001 
42002 #define S_TPT_ERR_CNT    0
42003 #define M_TPT_ERR_CNT    0xffffU
42004 #define V_TPT_ERR_CNT(x) ((x) << S_TPT_ERR_CNT)
42005 #define G_TPT_ERR_CNT(x) (((x) >> S_TPT_ERR_CNT) & M_TPT_ERR_CNT)
42006 
42007 #define A_XGMAC_PORT_AN_CONTROL 0x1600
42008 
42009 #define S_SOFT_RESET    15
42010 #define V_SOFT_RESET(x) ((x) << S_SOFT_RESET)
42011 #define F_SOFT_RESET    V_SOFT_RESET(1U)
42012 
42013 #define S_AN_ENABLE    12
42014 #define V_AN_ENABLE(x) ((x) << S_AN_ENABLE)
42015 #define F_AN_ENABLE    V_AN_ENABLE(1U)
42016 
42017 #define S_RESTART_AN    9
42018 #define V_RESTART_AN(x) ((x) << S_RESTART_AN)
42019 #define F_RESTART_AN    V_RESTART_AN(1U)
42020 
42021 #define A_XGMAC_PORT_AN_STATUS 0x1604
42022 
42023 #define S_NONCER_MATCH    31
42024 #define V_NONCER_MATCH(x) ((x) << S_NONCER_MATCH)
42025 #define F_NONCER_MATCH    V_NONCER_MATCH(1U)
42026 
42027 #define S_PARALLEL_DET_FAULT    9
42028 #define V_PARALLEL_DET_FAULT(x) ((x) << S_PARALLEL_DET_FAULT)
42029 #define F_PARALLEL_DET_FAULT    V_PARALLEL_DET_FAULT(1U)
42030 
42031 #define S_PAGE_RECEIVED    6
42032 #define V_PAGE_RECEIVED(x) ((x) << S_PAGE_RECEIVED)
42033 #define F_PAGE_RECEIVED    V_PAGE_RECEIVED(1U)
42034 
42035 #define S_AN_COMPLETE    5
42036 #define V_AN_COMPLETE(x) ((x) << S_AN_COMPLETE)
42037 #define F_AN_COMPLETE    V_AN_COMPLETE(1U)
42038 
42039 #define S_STAT_REMFAULT    4
42040 #define V_STAT_REMFAULT(x) ((x) << S_STAT_REMFAULT)
42041 #define F_STAT_REMFAULT    V_STAT_REMFAULT(1U)
42042 
42043 #define S_AN_ABILITY    3
42044 #define V_AN_ABILITY(x) ((x) << S_AN_ABILITY)
42045 #define F_AN_ABILITY    V_AN_ABILITY(1U)
42046 
42047 #define S_LINK_STATUS    2
42048 #define V_LINK_STATUS(x) ((x) << S_LINK_STATUS)
42049 #define F_LINK_STATUS    V_LINK_STATUS(1U)
42050 
42051 #define S_PARTNER_AN_ABILITY    0
42052 #define V_PARTNER_AN_ABILITY(x) ((x) << S_PARTNER_AN_ABILITY)
42053 #define F_PARTNER_AN_ABILITY    V_PARTNER_AN_ABILITY(1U)
42054 
42055 #define A_XGMAC_PORT_AN_ADVERTISEMENT 0x1608
42056 
42057 #define S_FEC_ENABLE    31
42058 #define V_FEC_ENABLE(x) ((x) << S_FEC_ENABLE)
42059 #define F_FEC_ENABLE    V_FEC_ENABLE(1U)
42060 
42061 #define S_FEC_ABILITY    30
42062 #define V_FEC_ABILITY(x) ((x) << S_FEC_ABILITY)
42063 #define F_FEC_ABILITY    V_FEC_ABILITY(1U)
42064 
42065 #define S_10GBASE_KR_CAPABLE    23
42066 #define V_10GBASE_KR_CAPABLE(x) ((x) << S_10GBASE_KR_CAPABLE)
42067 #define F_10GBASE_KR_CAPABLE    V_10GBASE_KR_CAPABLE(1U)
42068 
42069 #define S_10GBASE_KX4_CAPABLE    22
42070 #define V_10GBASE_KX4_CAPABLE(x) ((x) << S_10GBASE_KX4_CAPABLE)
42071 #define F_10GBASE_KX4_CAPABLE    V_10GBASE_KX4_CAPABLE(1U)
42072 
42073 #define S_1000BASE_KX_CAPABLE    21
42074 #define V_1000BASE_KX_CAPABLE(x) ((x) << S_1000BASE_KX_CAPABLE)
42075 #define F_1000BASE_KX_CAPABLE    V_1000BASE_KX_CAPABLE(1U)
42076 
42077 #define S_TRANSMITTED_NONCE    16
42078 #define M_TRANSMITTED_NONCE    0x1fU
42079 #define V_TRANSMITTED_NONCE(x) ((x) << S_TRANSMITTED_NONCE)
42080 #define G_TRANSMITTED_NONCE(x) (((x) >> S_TRANSMITTED_NONCE) & M_TRANSMITTED_NONCE)
42081 
42082 #define S_NP    15
42083 #define V_NP(x) ((x) << S_NP)
42084 #define F_NP    V_NP(1U)
42085 
42086 #define S_ACK    14
42087 #define V_ACK(x) ((x) << S_ACK)
42088 #define F_ACK    V_ACK(1U)
42089 
42090 #define S_REMOTE_FAULT    13
42091 #define V_REMOTE_FAULT(x) ((x) << S_REMOTE_FAULT)
42092 #define F_REMOTE_FAULT    V_REMOTE_FAULT(1U)
42093 
42094 #define S_ASM_DIR    11
42095 #define V_ASM_DIR(x) ((x) << S_ASM_DIR)
42096 #define F_ASM_DIR    V_ASM_DIR(1U)
42097 
42098 #define S_PAUSE    10
42099 #define V_PAUSE(x) ((x) << S_PAUSE)
42100 #define F_PAUSE    V_PAUSE(1U)
42101 
42102 #define S_ECHOED_NONCE    5
42103 #define M_ECHOED_NONCE    0x1fU
42104 #define V_ECHOED_NONCE(x) ((x) << S_ECHOED_NONCE)
42105 #define G_ECHOED_NONCE(x) (((x) >> S_ECHOED_NONCE) & M_ECHOED_NONCE)
42106 
42107 #define A_XGMAC_PORT_AN_LINK_PARTNER_ABILITY 0x160c
42108 
42109 #define S_SELECTOR_FIELD    0
42110 #define M_SELECTOR_FIELD    0x1fU
42111 #define V_SELECTOR_FIELD(x) ((x) << S_SELECTOR_FIELD)
42112 #define G_SELECTOR_FIELD(x) (((x) >> S_SELECTOR_FIELD) & M_SELECTOR_FIELD)
42113 
42114 #define A_XGMAC_PORT_AN_NP_LOWER_TRANSMIT 0x1610
42115 
42116 #define S_NP_INFO    16
42117 #define M_NP_INFO    0xffffU
42118 #define V_NP_INFO(x) ((x) << S_NP_INFO)
42119 #define G_NP_INFO(x) (((x) >> S_NP_INFO) & M_NP_INFO)
42120 
42121 #define S_NP_INDICATION    15
42122 #define V_NP_INDICATION(x) ((x) << S_NP_INDICATION)
42123 #define F_NP_INDICATION    V_NP_INDICATION(1U)
42124 
42125 #define S_MESSAGE_PAGE    13
42126 #define V_MESSAGE_PAGE(x) ((x) << S_MESSAGE_PAGE)
42127 #define F_MESSAGE_PAGE    V_MESSAGE_PAGE(1U)
42128 
42129 #define S_ACK_2    12
42130 #define V_ACK_2(x) ((x) << S_ACK_2)
42131 #define F_ACK_2    V_ACK_2(1U)
42132 
42133 #define S_TOGGLE    11
42134 #define V_TOGGLE(x) ((x) << S_TOGGLE)
42135 #define F_TOGGLE    V_TOGGLE(1U)
42136 
42137 #define A_XGMAC_PORT_AN_NP_UPPER_TRANSMIT 0x1614
42138 
42139 #define S_NP_INFO_HI    0
42140 #define M_NP_INFO_HI    0xffffU
42141 #define V_NP_INFO_HI(x) ((x) << S_NP_INFO_HI)
42142 #define G_NP_INFO_HI(x) (((x) >> S_NP_INFO_HI) & M_NP_INFO_HI)
42143 
42144 #define A_XGMAC_PORT_AN_LP_NP_LOWER 0x1618
42145 #define A_XGMAC_PORT_AN_LP_NP_UPPER 0x161c
42146 #define A_XGMAC_PORT_AN_BACKPLANE_ETHERNET_STATUS 0x1624
42147 
42148 #define S_TX_PAUSE_OKAY    6
42149 #define V_TX_PAUSE_OKAY(x) ((x) << S_TX_PAUSE_OKAY)
42150 #define F_TX_PAUSE_OKAY    V_TX_PAUSE_OKAY(1U)
42151 
42152 #define S_RX_PAUSE_OKAY    5
42153 #define V_RX_PAUSE_OKAY(x) ((x) << S_RX_PAUSE_OKAY)
42154 #define F_RX_PAUSE_OKAY    V_RX_PAUSE_OKAY(1U)
42155 
42156 #define S_10GBASE_KR_FEC_NEG    4
42157 #define V_10GBASE_KR_FEC_NEG(x) ((x) << S_10GBASE_KR_FEC_NEG)
42158 #define F_10GBASE_KR_FEC_NEG    V_10GBASE_KR_FEC_NEG(1U)
42159 
42160 #define S_10GBASE_KR_NEG    3
42161 #define V_10GBASE_KR_NEG(x) ((x) << S_10GBASE_KR_NEG)
42162 #define F_10GBASE_KR_NEG    V_10GBASE_KR_NEG(1U)
42163 
42164 #define S_10GBASE_KX4_NEG    2
42165 #define V_10GBASE_KX4_NEG(x) ((x) << S_10GBASE_KX4_NEG)
42166 #define F_10GBASE_KX4_NEG    V_10GBASE_KX4_NEG(1U)
42167 
42168 #define S_1000BASE_KX_NEG    1
42169 #define V_1000BASE_KX_NEG(x) ((x) << S_1000BASE_KX_NEG)
42170 #define F_1000BASE_KX_NEG    V_1000BASE_KX_NEG(1U)
42171 
42172 #define S_BP_AN_ABILITY    0
42173 #define V_BP_AN_ABILITY(x) ((x) << S_BP_AN_ABILITY)
42174 #define F_BP_AN_ABILITY    V_BP_AN_ABILITY(1U)
42175 
42176 #define A_XGMAC_PORT_AN_TX_NONCE_CONTROL 0x1628
42177 
42178 #define S_BYPASS_LFSR    15
42179 #define V_BYPASS_LFSR(x) ((x) << S_BYPASS_LFSR)
42180 #define F_BYPASS_LFSR    V_BYPASS_LFSR(1U)
42181 
42182 #define S_LFSR_INIT    0
42183 #define M_LFSR_INIT    0x7fffU
42184 #define V_LFSR_INIT(x) ((x) << S_LFSR_INIT)
42185 #define G_LFSR_INIT(x) (((x) >> S_LFSR_INIT) & M_LFSR_INIT)
42186 
42187 #define A_XGMAC_PORT_AN_INTERRUPT_STATUS 0x162c
42188 
42189 #define S_NP_FROM_LP    3
42190 #define V_NP_FROM_LP(x) ((x) << S_NP_FROM_LP)
42191 #define F_NP_FROM_LP    V_NP_FROM_LP(1U)
42192 
42193 #define S_PARALLELDETFAULTINT    2
42194 #define V_PARALLELDETFAULTINT(x) ((x) << S_PARALLELDETFAULTINT)
42195 #define F_PARALLELDETFAULTINT    V_PARALLELDETFAULTINT(1U)
42196 
42197 #define S_BP_FROM_LP    1
42198 #define V_BP_FROM_LP(x) ((x) << S_BP_FROM_LP)
42199 #define F_BP_FROM_LP    V_BP_FROM_LP(1U)
42200 
42201 #define S_PCS_AN_COMPLETE    0
42202 #define V_PCS_AN_COMPLETE(x) ((x) << S_PCS_AN_COMPLETE)
42203 #define F_PCS_AN_COMPLETE    V_PCS_AN_COMPLETE(1U)
42204 
42205 #define A_XGMAC_PORT_AN_GENERIC_TIMER_TIMEOUT 0x1630
42206 
42207 #define S_GENERIC_TIMEOUT    0
42208 #define M_GENERIC_TIMEOUT    0x7fffffU
42209 #define V_GENERIC_TIMEOUT(x) ((x) << S_GENERIC_TIMEOUT)
42210 #define G_GENERIC_TIMEOUT(x) (((x) >> S_GENERIC_TIMEOUT) & M_GENERIC_TIMEOUT)
42211 
42212 #define A_XGMAC_PORT_AN_BREAK_LINK_TIMEOUT 0x1634
42213 
42214 #define S_BREAK_LINK_TIMEOUT    0
42215 #define M_BREAK_LINK_TIMEOUT    0xffffffU
42216 #define V_BREAK_LINK_TIMEOUT(x) ((x) << S_BREAK_LINK_TIMEOUT)
42217 #define G_BREAK_LINK_TIMEOUT(x) (((x) >> S_BREAK_LINK_TIMEOUT) & M_BREAK_LINK_TIMEOUT)
42218 
42219 #define A_XGMAC_PORT_AN_MODULE_ID 0x163c
42220 
42221 #define S_MODULE_ID    16
42222 #define M_MODULE_ID    0xffffU
42223 #define V_MODULE_ID(x) ((x) << S_MODULE_ID)
42224 #define G_MODULE_ID(x) (((x) >> S_MODULE_ID) & M_MODULE_ID)
42225 
42226 #define S_MODULE_REVISION    0
42227 #define M_MODULE_REVISION    0xffffU
42228 #define V_MODULE_REVISION(x) ((x) << S_MODULE_REVISION)
42229 #define G_MODULE_REVISION(x) (((x) >> S_MODULE_REVISION) & M_MODULE_REVISION)
42230 
42231 #define A_XGMAC_PORT_AE_RX_COEF_REQ 0x1700
42232 
42233 #define S_RXREQ_CPRE    13
42234 #define V_RXREQ_CPRE(x) ((x) << S_RXREQ_CPRE)
42235 #define F_RXREQ_CPRE    V_RXREQ_CPRE(1U)
42236 
42237 #define S_RXREQ_CINIT    12
42238 #define V_RXREQ_CINIT(x) ((x) << S_RXREQ_CINIT)
42239 #define F_RXREQ_CINIT    V_RXREQ_CINIT(1U)
42240 
42241 #define S_RXREQ_C0    4
42242 #define M_RXREQ_C0    0x3U
42243 #define V_RXREQ_C0(x) ((x) << S_RXREQ_C0)
42244 #define G_RXREQ_C0(x) (((x) >> S_RXREQ_C0) & M_RXREQ_C0)
42245 
42246 #define S_RXREQ_C1    2
42247 #define M_RXREQ_C1    0x3U
42248 #define V_RXREQ_C1(x) ((x) << S_RXREQ_C1)
42249 #define G_RXREQ_C1(x) (((x) >> S_RXREQ_C1) & M_RXREQ_C1)
42250 
42251 #define S_RXREQ_C2    0
42252 #define M_RXREQ_C2    0x3U
42253 #define V_RXREQ_C2(x) ((x) << S_RXREQ_C2)
42254 #define G_RXREQ_C2(x) (((x) >> S_RXREQ_C2) & M_RXREQ_C2)
42255 
42256 #define A_XGMAC_PORT_AE_RX_COEF_STAT 0x1704
42257 
42258 #define S_RXSTAT_RDY    15
42259 #define V_RXSTAT_RDY(x) ((x) << S_RXSTAT_RDY)
42260 #define F_RXSTAT_RDY    V_RXSTAT_RDY(1U)
42261 
42262 #define S_RXSTAT_C0    4
42263 #define M_RXSTAT_C0    0x3U
42264 #define V_RXSTAT_C0(x) ((x) << S_RXSTAT_C0)
42265 #define G_RXSTAT_C0(x) (((x) >> S_RXSTAT_C0) & M_RXSTAT_C0)
42266 
42267 #define S_RXSTAT_C1    2
42268 #define M_RXSTAT_C1    0x3U
42269 #define V_RXSTAT_C1(x) ((x) << S_RXSTAT_C1)
42270 #define G_RXSTAT_C1(x) (((x) >> S_RXSTAT_C1) & M_RXSTAT_C1)
42271 
42272 #define S_RXSTAT_C2    0
42273 #define M_RXSTAT_C2    0x3U
42274 #define V_RXSTAT_C2(x) ((x) << S_RXSTAT_C2)
42275 #define G_RXSTAT_C2(x) (((x) >> S_RXSTAT_C2) & M_RXSTAT_C2)
42276 
42277 #define A_XGMAC_PORT_AE_TX_COEF_REQ 0x1708
42278 
42279 #define S_TXREQ_CPRE    13
42280 #define V_TXREQ_CPRE(x) ((x) << S_TXREQ_CPRE)
42281 #define F_TXREQ_CPRE    V_TXREQ_CPRE(1U)
42282 
42283 #define S_TXREQ_CINIT    12
42284 #define V_TXREQ_CINIT(x) ((x) << S_TXREQ_CINIT)
42285 #define F_TXREQ_CINIT    V_TXREQ_CINIT(1U)
42286 
42287 #define S_TXREQ_C0    4
42288 #define M_TXREQ_C0    0x3U
42289 #define V_TXREQ_C0(x) ((x) << S_TXREQ_C0)
42290 #define G_TXREQ_C0(x) (((x) >> S_TXREQ_C0) & M_TXREQ_C0)
42291 
42292 #define S_TXREQ_C1    2
42293 #define M_TXREQ_C1    0x3U
42294 #define V_TXREQ_C1(x) ((x) << S_TXREQ_C1)
42295 #define G_TXREQ_C1(x) (((x) >> S_TXREQ_C1) & M_TXREQ_C1)
42296 
42297 #define S_TXREQ_C2    0
42298 #define M_TXREQ_C2    0x3U
42299 #define V_TXREQ_C2(x) ((x) << S_TXREQ_C2)
42300 #define G_TXREQ_C2(x) (((x) >> S_TXREQ_C2) & M_TXREQ_C2)
42301 
42302 #define A_XGMAC_PORT_AE_TX_COEF_STAT 0x170c
42303 
42304 #define S_TXSTAT_RDY    15
42305 #define V_TXSTAT_RDY(x) ((x) << S_TXSTAT_RDY)
42306 #define F_TXSTAT_RDY    V_TXSTAT_RDY(1U)
42307 
42308 #define S_TXSTAT_C0    4
42309 #define M_TXSTAT_C0    0x3U
42310 #define V_TXSTAT_C0(x) ((x) << S_TXSTAT_C0)
42311 #define G_TXSTAT_C0(x) (((x) >> S_TXSTAT_C0) & M_TXSTAT_C0)
42312 
42313 #define S_TXSTAT_C1    2
42314 #define M_TXSTAT_C1    0x3U
42315 #define V_TXSTAT_C1(x) ((x) << S_TXSTAT_C1)
42316 #define G_TXSTAT_C1(x) (((x) >> S_TXSTAT_C1) & M_TXSTAT_C1)
42317 
42318 #define S_TXSTAT_C2    0
42319 #define M_TXSTAT_C2    0x3U
42320 #define V_TXSTAT_C2(x) ((x) << S_TXSTAT_C2)
42321 #define G_TXSTAT_C2(x) (((x) >> S_TXSTAT_C2) & M_TXSTAT_C2)
42322 
42323 #define A_XGMAC_PORT_AE_REG_MODE 0x1710
42324 
42325 #define S_MAN_DEC    4
42326 #define M_MAN_DEC    0x3U
42327 #define V_MAN_DEC(x) ((x) << S_MAN_DEC)
42328 #define G_MAN_DEC(x) (((x) >> S_MAN_DEC) & M_MAN_DEC)
42329 
42330 #define S_MANUAL_RDY    3
42331 #define V_MANUAL_RDY(x) ((x) << S_MANUAL_RDY)
42332 #define F_MANUAL_RDY    V_MANUAL_RDY(1U)
42333 
42334 #define S_MWT_DISABLE    2
42335 #define V_MWT_DISABLE(x) ((x) << S_MWT_DISABLE)
42336 #define F_MWT_DISABLE    V_MWT_DISABLE(1U)
42337 
42338 #define S_MDIO_OVR    1
42339 #define V_MDIO_OVR(x) ((x) << S_MDIO_OVR)
42340 #define F_MDIO_OVR    V_MDIO_OVR(1U)
42341 
42342 #define S_STICKY_MODE    0
42343 #define V_STICKY_MODE(x) ((x) << S_STICKY_MODE)
42344 #define F_STICKY_MODE    V_STICKY_MODE(1U)
42345 
42346 #define A_XGMAC_PORT_AE_PRBS_CTL 0x1714
42347 
42348 #define S_PRBS_CHK_ERRCNT    8
42349 #define M_PRBS_CHK_ERRCNT    0xffU
42350 #define V_PRBS_CHK_ERRCNT(x) ((x) << S_PRBS_CHK_ERRCNT)
42351 #define G_PRBS_CHK_ERRCNT(x) (((x) >> S_PRBS_CHK_ERRCNT) & M_PRBS_CHK_ERRCNT)
42352 
42353 #define S_PRBS_SYNCCNT    5
42354 #define M_PRBS_SYNCCNT    0x7U
42355 #define V_PRBS_SYNCCNT(x) ((x) << S_PRBS_SYNCCNT)
42356 #define G_PRBS_SYNCCNT(x) (((x) >> S_PRBS_SYNCCNT) & M_PRBS_SYNCCNT)
42357 
42358 #define S_PRBS_CHK_SYNC    4
42359 #define V_PRBS_CHK_SYNC(x) ((x) << S_PRBS_CHK_SYNC)
42360 #define F_PRBS_CHK_SYNC    V_PRBS_CHK_SYNC(1U)
42361 
42362 #define S_PRBS_CHK_RST    3
42363 #define V_PRBS_CHK_RST(x) ((x) << S_PRBS_CHK_RST)
42364 #define F_PRBS_CHK_RST    V_PRBS_CHK_RST(1U)
42365 
42366 #define S_PRBS_CHK_OFF    2
42367 #define V_PRBS_CHK_OFF(x) ((x) << S_PRBS_CHK_OFF)
42368 #define F_PRBS_CHK_OFF    V_PRBS_CHK_OFF(1U)
42369 
42370 #define S_PRBS_GEN_FRCERR    1
42371 #define V_PRBS_GEN_FRCERR(x) ((x) << S_PRBS_GEN_FRCERR)
42372 #define F_PRBS_GEN_FRCERR    V_PRBS_GEN_FRCERR(1U)
42373 
42374 #define S_PRBS_GEN_OFF    0
42375 #define V_PRBS_GEN_OFF(x) ((x) << S_PRBS_GEN_OFF)
42376 #define F_PRBS_GEN_OFF    V_PRBS_GEN_OFF(1U)
42377 
42378 #define A_XGMAC_PORT_AE_FSM_CTL 0x1718
42379 
42380 #define S_FSM_TR_LCL    14
42381 #define V_FSM_TR_LCL(x) ((x) << S_FSM_TR_LCL)
42382 #define F_FSM_TR_LCL    V_FSM_TR_LCL(1U)
42383 
42384 #define S_FSM_GDMRK    11
42385 #define M_FSM_GDMRK    0x7U
42386 #define V_FSM_GDMRK(x) ((x) << S_FSM_GDMRK)
42387 #define G_FSM_GDMRK(x) (((x) >> S_FSM_GDMRK) & M_FSM_GDMRK)
42388 
42389 #define S_FSM_BADMRK    8
42390 #define M_FSM_BADMRK    0x7U
42391 #define V_FSM_BADMRK(x) ((x) << S_FSM_BADMRK)
42392 #define G_FSM_BADMRK(x) (((x) >> S_FSM_BADMRK) & M_FSM_BADMRK)
42393 
42394 #define S_FSM_TR_FAIL    7
42395 #define V_FSM_TR_FAIL(x) ((x) << S_FSM_TR_FAIL)
42396 #define F_FSM_TR_FAIL    V_FSM_TR_FAIL(1U)
42397 
42398 #define S_FSM_TR_ACT    6
42399 #define V_FSM_TR_ACT(x) ((x) << S_FSM_TR_ACT)
42400 #define F_FSM_TR_ACT    V_FSM_TR_ACT(1U)
42401 
42402 #define S_FSM_FRM_LCK    5
42403 #define V_FSM_FRM_LCK(x) ((x) << S_FSM_FRM_LCK)
42404 #define F_FSM_FRM_LCK    V_FSM_FRM_LCK(1U)
42405 
42406 #define S_FSM_TR_COMP    4
42407 #define V_FSM_TR_COMP(x) ((x) << S_FSM_TR_COMP)
42408 #define F_FSM_TR_COMP    V_FSM_TR_COMP(1U)
42409 
42410 #define S_MC_RX_RDY    3
42411 #define V_MC_RX_RDY(x) ((x) << S_MC_RX_RDY)
42412 #define F_MC_RX_RDY    V_MC_RX_RDY(1U)
42413 
42414 #define S_FSM_CU_DIS    2
42415 #define V_FSM_CU_DIS(x) ((x) << S_FSM_CU_DIS)
42416 #define F_FSM_CU_DIS    V_FSM_CU_DIS(1U)
42417 
42418 #define S_FSM_TR_RST    1
42419 #define V_FSM_TR_RST(x) ((x) << S_FSM_TR_RST)
42420 #define F_FSM_TR_RST    V_FSM_TR_RST(1U)
42421 
42422 #define S_FSM_TR_EN    0
42423 #define V_FSM_TR_EN(x) ((x) << S_FSM_TR_EN)
42424 #define F_FSM_TR_EN    V_FSM_TR_EN(1U)
42425 
42426 #define A_XGMAC_PORT_AE_FSM_STATE 0x171c
42427 
42428 #define S_CC2FSM_STATE    13
42429 #define M_CC2FSM_STATE    0x7U
42430 #define V_CC2FSM_STATE(x) ((x) << S_CC2FSM_STATE)
42431 #define G_CC2FSM_STATE(x) (((x) >> S_CC2FSM_STATE) & M_CC2FSM_STATE)
42432 
42433 #define S_CC1FSM_STATE    10
42434 #define M_CC1FSM_STATE    0x7U
42435 #define V_CC1FSM_STATE(x) ((x) << S_CC1FSM_STATE)
42436 #define G_CC1FSM_STATE(x) (((x) >> S_CC1FSM_STATE) & M_CC1FSM_STATE)
42437 
42438 #define S_CC0FSM_STATE    7
42439 #define M_CC0FSM_STATE    0x7U
42440 #define V_CC0FSM_STATE(x) ((x) << S_CC0FSM_STATE)
42441 #define G_CC0FSM_STATE(x) (((x) >> S_CC0FSM_STATE) & M_CC0FSM_STATE)
42442 
42443 #define S_FLFSM_STATE    4
42444 #define M_FLFSM_STATE    0x7U
42445 #define V_FLFSM_STATE(x) ((x) << S_FLFSM_STATE)
42446 #define G_FLFSM_STATE(x) (((x) >> S_FLFSM_STATE) & M_FLFSM_STATE)
42447 
42448 #define S_TFSM_STATE    0
42449 #define M_TFSM_STATE    0x7U
42450 #define V_TFSM_STATE(x) ((x) << S_TFSM_STATE)
42451 #define G_TFSM_STATE(x) (((x) >> S_TFSM_STATE) & M_TFSM_STATE)
42452 
42453 #define A_XGMAC_PORT_AE_TX_DIS 0x1780
42454 
42455 #define S_PMD_TX_DIS    0
42456 #define V_PMD_TX_DIS(x) ((x) << S_PMD_TX_DIS)
42457 #define F_PMD_TX_DIS    V_PMD_TX_DIS(1U)
42458 
42459 #define A_XGMAC_PORT_AE_KR_CTRL 0x1784
42460 
42461 #define S_TRAINING_ENABLE    1
42462 #define V_TRAINING_ENABLE(x) ((x) << S_TRAINING_ENABLE)
42463 #define F_TRAINING_ENABLE    V_TRAINING_ENABLE(1U)
42464 
42465 #define S_RESTART_TRAINING    0
42466 #define V_RESTART_TRAINING(x) ((x) << S_RESTART_TRAINING)
42467 #define F_RESTART_TRAINING    V_RESTART_TRAINING(1U)
42468 
42469 #define A_XGMAC_PORT_AE_RX_SIGDET 0x1788
42470 
42471 #define S_PMD_SIGDET    0
42472 #define V_PMD_SIGDET(x) ((x) << S_PMD_SIGDET)
42473 #define F_PMD_SIGDET    V_PMD_SIGDET(1U)
42474 
42475 #define A_XGMAC_PORT_AE_KR_STATUS 0x178c
42476 
42477 #define S_TRAINING_FAILURE    3
42478 #define V_TRAINING_FAILURE(x) ((x) << S_TRAINING_FAILURE)
42479 #define F_TRAINING_FAILURE    V_TRAINING_FAILURE(1U)
42480 
42481 #define S_TRAINING    2
42482 #define V_TRAINING(x) ((x) << S_TRAINING)
42483 #define F_TRAINING    V_TRAINING(1U)
42484 
42485 #define S_FRAME_LOCK    1
42486 #define V_FRAME_LOCK(x) ((x) << S_FRAME_LOCK)
42487 #define F_FRAME_LOCK    V_FRAME_LOCK(1U)
42488 
42489 #define S_RX_TRAINED    0
42490 #define V_RX_TRAINED(x) ((x) << S_RX_TRAINED)
42491 #define F_RX_TRAINED    V_RX_TRAINED(1U)
42492 
42493 #define A_XGMAC_PORT_HSS_TXA_MODE_CFG 0x1800
42494 
42495 #define S_BWSEL    2
42496 #define M_BWSEL    0x3U
42497 #define V_BWSEL(x) ((x) << S_BWSEL)
42498 #define G_BWSEL(x) (((x) >> S_BWSEL) & M_BWSEL)
42499 
42500 #define S_RTSEL    0
42501 #define M_RTSEL    0x3U
42502 #define V_RTSEL(x) ((x) << S_RTSEL)
42503 #define G_RTSEL(x) (((x) >> S_RTSEL) & M_RTSEL)
42504 
42505 #define A_XGMAC_PORT_HSS_TXA_TEST_CTRL 0x1804
42506 
42507 #define S_TWDP    5
42508 #define V_TWDP(x) ((x) << S_TWDP)
42509 #define F_TWDP    V_TWDP(1U)
42510 
42511 #define S_TPGRST    4
42512 #define V_TPGRST(x) ((x) << S_TPGRST)
42513 #define F_TPGRST    V_TPGRST(1U)
42514 
42515 #define S_TPGEN    3
42516 #define V_TPGEN(x) ((x) << S_TPGEN)
42517 #define F_TPGEN    V_TPGEN(1U)
42518 
42519 #define S_TPSEL    0
42520 #define M_TPSEL    0x7U
42521 #define V_TPSEL(x) ((x) << S_TPSEL)
42522 #define G_TPSEL(x) (((x) >> S_TPSEL) & M_TPSEL)
42523 
42524 #define A_XGMAC_PORT_HSS_TXA_COEFF_CTRL 0x1808
42525 
42526 #define S_AEINVPOL    6
42527 #define V_AEINVPOL(x) ((x) << S_AEINVPOL)
42528 #define F_AEINVPOL    V_AEINVPOL(1U)
42529 
42530 #define S_AESOURCE    5
42531 #define V_AESOURCE(x) ((x) << S_AESOURCE)
42532 #define F_AESOURCE    V_AESOURCE(1U)
42533 
42534 #define S_EQMODE    4
42535 #define V_EQMODE(x) ((x) << S_EQMODE)
42536 #define F_EQMODE    V_EQMODE(1U)
42537 
42538 #define S_OCOEF    3
42539 #define V_OCOEF(x) ((x) << S_OCOEF)
42540 #define F_OCOEF    V_OCOEF(1U)
42541 
42542 #define S_COEFRST    2
42543 #define V_COEFRST(x) ((x) << S_COEFRST)
42544 #define F_COEFRST    V_COEFRST(1U)
42545 
42546 #define S_SPEN    1
42547 #define V_SPEN(x) ((x) << S_SPEN)
42548 #define F_SPEN    V_SPEN(1U)
42549 
42550 #define S_ALOAD    0
42551 #define V_ALOAD(x) ((x) << S_ALOAD)
42552 #define F_ALOAD    V_ALOAD(1U)
42553 
42554 #define A_XGMAC_PORT_HSS_TXA_DRIVER_MODE 0x180c
42555 
42556 #define S_DRVOFFT    5
42557 #define V_DRVOFFT(x) ((x) << S_DRVOFFT)
42558 #define F_DRVOFFT    V_DRVOFFT(1U)
42559 
42560 #define S_SLEW    2
42561 #define M_SLEW    0x7U
42562 #define V_SLEW(x) ((x) << S_SLEW)
42563 #define G_SLEW(x) (((x) >> S_SLEW) & M_SLEW)
42564 
42565 #define S_FFE    0
42566 #define M_FFE    0x3U
42567 #define V_FFE(x) ((x) << S_FFE)
42568 #define G_FFE(x) (((x) >> S_FFE) & M_FFE)
42569 
42570 #define A_XGMAC_PORT_HSS_TXA_DRIVER_OVR_CTRL 0x1810
42571 
42572 #define S_VLINC    7
42573 #define V_VLINC(x) ((x) << S_VLINC)
42574 #define F_VLINC    V_VLINC(1U)
42575 
42576 #define S_VLDEC    6
42577 #define V_VLDEC(x) ((x) << S_VLDEC)
42578 #define F_VLDEC    V_VLDEC(1U)
42579 
42580 #define S_LOPWR    5
42581 #define V_LOPWR(x) ((x) << S_LOPWR)
42582 #define F_LOPWR    V_LOPWR(1U)
42583 
42584 #define S_TDMEN    4
42585 #define V_TDMEN(x) ((x) << S_TDMEN)
42586 #define F_TDMEN    V_TDMEN(1U)
42587 
42588 #define S_DCCEN    3
42589 #define V_DCCEN(x) ((x) << S_DCCEN)
42590 #define F_DCCEN    V_DCCEN(1U)
42591 
42592 #define S_VHSEL    2
42593 #define V_VHSEL(x) ((x) << S_VHSEL)
42594 #define F_VHSEL    V_VHSEL(1U)
42595 
42596 #define S_IDAC    0
42597 #define M_IDAC    0x3U
42598 #define V_IDAC(x) ((x) << S_IDAC)
42599 #define G_IDAC(x) (((x) >> S_IDAC) & M_IDAC)
42600 
42601 #define A_XGMAC_PORT_HSS_TXA_TDM_BIASGEN_STANDBY_TIMER 0x1814
42602 
42603 #define S_STBY    0
42604 #define M_STBY    0xffffU
42605 #define V_STBY(x) ((x) << S_STBY)
42606 #define G_STBY(x) (((x) >> S_STBY) & M_STBY)
42607 
42608 #define A_XGMAC_PORT_HSS_TXA_TDM_BIASGEN_PWRON_TIMER 0x1818
42609 
42610 #define S_PON    0
42611 #define M_PON    0xffffU
42612 #define V_PON(x) ((x) << S_PON)
42613 #define G_PON(x) (((x) >> S_PON) & M_PON)
42614 
42615 #define A_XGMAC_PORT_HSS_TXA_TAP0_COEFF 0x1820
42616 
42617 #define S_NXTT0    0
42618 #define M_NXTT0    0xfU
42619 #define V_NXTT0(x) ((x) << S_NXTT0)
42620 #define G_NXTT0(x) (((x) >> S_NXTT0) & M_NXTT0)
42621 
42622 #define A_XGMAC_PORT_HSS_TXA_TAP1_COEFF 0x1824
42623 
42624 #define S_NXTT1    0
42625 #define M_NXTT1    0x3fU
42626 #define V_NXTT1(x) ((x) << S_NXTT1)
42627 #define G_NXTT1(x) (((x) >> S_NXTT1) & M_NXTT1)
42628 
42629 #define A_XGMAC_PORT_HSS_TXA_TAP2_COEFF 0x1828
42630 
42631 #define S_NXTT2    0
42632 #define M_NXTT2    0x1fU
42633 #define V_NXTT2(x) ((x) << S_NXTT2)
42634 #define G_NXTT2(x) (((x) >> S_NXTT2) & M_NXTT2)
42635 
42636 #define A_XGMAC_PORT_HSS_TXA_PWR 0x1830
42637 
42638 #define S_TXPWR    0
42639 #define M_TXPWR    0x7fU
42640 #define V_TXPWR(x) ((x) << S_TXPWR)
42641 #define G_TXPWR(x) (((x) >> S_TXPWR) & M_TXPWR)
42642 
42643 #define A_XGMAC_PORT_HSS_TXA_POLARITY 0x1834
42644 
42645 #define S_TXPOL    4
42646 #define M_TXPOL    0x7U
42647 #define V_TXPOL(x) ((x) << S_TXPOL)
42648 #define G_TXPOL(x) (((x) >> S_TXPOL) & M_TXPOL)
42649 
42650 #define S_NTXPOL    0
42651 #define M_NTXPOL    0x7U
42652 #define V_NTXPOL(x) ((x) << S_NTXPOL)
42653 #define G_NTXPOL(x) (((x) >> S_NTXPOL) & M_NTXPOL)
42654 
42655 #define A_XGMAC_PORT_HSS_TXA_8023AP_AE_CMD 0x1838
42656 
42657 #define S_CXPRESET    13
42658 #define V_CXPRESET(x) ((x) << S_CXPRESET)
42659 #define F_CXPRESET    V_CXPRESET(1U)
42660 
42661 #define S_CXINIT    12
42662 #define V_CXINIT(x) ((x) << S_CXINIT)
42663 #define F_CXINIT    V_CXINIT(1U)
42664 
42665 #define S_C2UPDT    4
42666 #define M_C2UPDT    0x3U
42667 #define V_C2UPDT(x) ((x) << S_C2UPDT)
42668 #define G_C2UPDT(x) (((x) >> S_C2UPDT) & M_C2UPDT)
42669 
42670 #define S_C1UPDT    2
42671 #define M_C1UPDT    0x3U
42672 #define V_C1UPDT(x) ((x) << S_C1UPDT)
42673 #define G_C1UPDT(x) (((x) >> S_C1UPDT) & M_C1UPDT)
42674 
42675 #define S_C0UPDT    0
42676 #define M_C0UPDT    0x3U
42677 #define V_C0UPDT(x) ((x) << S_C0UPDT)
42678 #define G_C0UPDT(x) (((x) >> S_C0UPDT) & M_C0UPDT)
42679 
42680 #define A_XGMAC_PORT_HSS_TXA_8023AP_AE_STATUS 0x183c
42681 
42682 #define S_C2STAT    4
42683 #define M_C2STAT    0x3U
42684 #define V_C2STAT(x) ((x) << S_C2STAT)
42685 #define G_C2STAT(x) (((x) >> S_C2STAT) & M_C2STAT)
42686 
42687 #define S_C1STAT    2
42688 #define M_C1STAT    0x3U
42689 #define V_C1STAT(x) ((x) << S_C1STAT)
42690 #define G_C1STAT(x) (((x) >> S_C1STAT) & M_C1STAT)
42691 
42692 #define S_C0STAT    0
42693 #define M_C0STAT    0x3U
42694 #define V_C0STAT(x) ((x) << S_C0STAT)
42695 #define G_C0STAT(x) (((x) >> S_C0STAT) & M_C0STAT)
42696 
42697 #define A_XGMAC_PORT_HSS_TXA_TAP0_IDAC_OVR 0x1840
42698 
42699 #define S_NIDAC0    0
42700 #define M_NIDAC0    0x1fU
42701 #define V_NIDAC0(x) ((x) << S_NIDAC0)
42702 #define G_NIDAC0(x) (((x) >> S_NIDAC0) & M_NIDAC0)
42703 
42704 #define A_XGMAC_PORT_HSS_TXA_TAP1_IDAC_OVR 0x1844
42705 
42706 #define S_NIDAC1    0
42707 #define M_NIDAC1    0x7fU
42708 #define V_NIDAC1(x) ((x) << S_NIDAC1)
42709 #define G_NIDAC1(x) (((x) >> S_NIDAC1) & M_NIDAC1)
42710 
42711 #define A_XGMAC_PORT_HSS_TXA_TAP2_IDAC_OVR 0x1848
42712 
42713 #define S_NIDAC2    0
42714 #define M_NIDAC2    0x3fU
42715 #define V_NIDAC2(x) ((x) << S_NIDAC2)
42716 #define G_NIDAC2(x) (((x) >> S_NIDAC2) & M_NIDAC2)
42717 
42718 #define A_XGMAC_PORT_HSS_TXA_PWR_DAC_OVR 0x1850
42719 
42720 #define S_OPEN    7
42721 #define V_OPEN(x) ((x) << S_OPEN)
42722 #define F_OPEN    V_OPEN(1U)
42723 
42724 #define S_OPVAL    0
42725 #define M_OPVAL    0x1fU
42726 #define V_OPVAL(x) ((x) << S_OPVAL)
42727 #define G_OPVAL(x) (((x) >> S_OPVAL) & M_OPVAL)
42728 
42729 #define A_XGMAC_PORT_HSS_TXA_PWR_DAC 0x1854
42730 
42731 #define S_PDAC    0
42732 #define M_PDAC    0x1fU
42733 #define V_PDAC(x) ((x) << S_PDAC)
42734 #define G_PDAC(x) (((x) >> S_PDAC) & M_PDAC)
42735 
42736 #define A_XGMAC_PORT_HSS_TXA_TAP0_IDAC_APP 0x1860
42737 
42738 #define S_AIDAC0    0
42739 #define M_AIDAC0    0x1fU
42740 #define V_AIDAC0(x) ((x) << S_AIDAC0)
42741 #define G_AIDAC0(x) (((x) >> S_AIDAC0) & M_AIDAC0)
42742 
42743 #define A_XGMAC_PORT_HSS_TXA_TAP1_IDAC_APP 0x1864
42744 
42745 #define S_AIDAC1    0
42746 #define M_AIDAC1    0x1fU
42747 #define V_AIDAC1(x) ((x) << S_AIDAC1)
42748 #define G_AIDAC1(x) (((x) >> S_AIDAC1) & M_AIDAC1)
42749 
42750 #define A_XGMAC_PORT_HSS_TXA_TAP2_IDAC_APP 0x1868
42751 
42752 #define S_TXA_AIDAC2    0
42753 #define M_TXA_AIDAC2    0x1fU
42754 #define V_TXA_AIDAC2(x) ((x) << S_TXA_AIDAC2)
42755 #define G_TXA_AIDAC2(x) (((x) >> S_TXA_AIDAC2) & M_TXA_AIDAC2)
42756 
42757 #define A_XGMAC_PORT_HSS_TXA_SEG_DIS_APP 0x1870
42758 
42759 #define S_CURSD    0
42760 #define M_CURSD    0x7fU
42761 #define V_CURSD(x) ((x) << S_CURSD)
42762 #define G_CURSD(x) (((x) >> S_CURSD) & M_CURSD)
42763 
42764 #define A_XGMAC_PORT_HSS_TXA_EXT_ADDR_DATA 0x1878
42765 
42766 #define S_XDATA    0
42767 #define M_XDATA    0xffffU
42768 #define V_XDATA(x) ((x) << S_XDATA)
42769 #define G_XDATA(x) (((x) >> S_XDATA) & M_XDATA)
42770 
42771 #define A_XGMAC_PORT_HSS_TXA_EXT_ADDR 0x187c
42772 
42773 #define S_EXTADDR    1
42774 #define M_EXTADDR    0x1fU
42775 #define V_EXTADDR(x) ((x) << S_EXTADDR)
42776 #define G_EXTADDR(x) (((x) >> S_EXTADDR) & M_EXTADDR)
42777 
42778 #define S_XWR    0
42779 #define V_XWR(x) ((x) << S_XWR)
42780 #define F_XWR    V_XWR(1U)
42781 
42782 #define A_XGMAC_PORT_HSS_TXB_MODE_CFG 0x1880
42783 #define A_XGMAC_PORT_HSS_TXB_TEST_CTRL 0x1884
42784 #define A_XGMAC_PORT_HSS_TXB_COEFF_CTRL 0x1888
42785 #define A_XGMAC_PORT_HSS_TXB_DRIVER_MODE 0x188c
42786 #define A_XGMAC_PORT_HSS_TXB_DRIVER_OVR_CTRL 0x1890
42787 #define A_XGMAC_PORT_HSS_TXB_TDM_BIASGEN_STANDBY_TIMER 0x1894
42788 #define A_XGMAC_PORT_HSS_TXB_TDM_BIASGEN_PWRON_TIMER 0x1898
42789 #define A_XGMAC_PORT_HSS_TXB_TAP0_COEFF 0x18a0
42790 #define A_XGMAC_PORT_HSS_TXB_TAP1_COEFF 0x18a4
42791 #define A_XGMAC_PORT_HSS_TXB_TAP2_COEFF 0x18a8
42792 #define A_XGMAC_PORT_HSS_TXB_PWR 0x18b0
42793 #define A_XGMAC_PORT_HSS_TXB_POLARITY 0x18b4
42794 #define A_XGMAC_PORT_HSS_TXB_8023AP_AE_CMD 0x18b8
42795 #define A_XGMAC_PORT_HSS_TXB_8023AP_AE_STATUS 0x18bc
42796 #define A_XGMAC_PORT_HSS_TXB_TAP0_IDAC_OVR 0x18c0
42797 #define A_XGMAC_PORT_HSS_TXB_TAP1_IDAC_OVR 0x18c4
42798 #define A_XGMAC_PORT_HSS_TXB_TAP2_IDAC_OVR 0x18c8
42799 #define A_XGMAC_PORT_HSS_TXB_PWR_DAC_OVR 0x18d0
42800 #define A_XGMAC_PORT_HSS_TXB_PWR_DAC 0x18d4
42801 #define A_XGMAC_PORT_HSS_TXB_TAP0_IDAC_APP 0x18e0
42802 #define A_XGMAC_PORT_HSS_TXB_TAP1_IDAC_APP 0x18e4
42803 #define A_XGMAC_PORT_HSS_TXB_TAP2_IDAC_APP 0x18e8
42804 
42805 #define S_AIDAC2    0
42806 #define M_AIDAC2    0x3fU
42807 #define V_AIDAC2(x) ((x) << S_AIDAC2)
42808 #define G_AIDAC2(x) (((x) >> S_AIDAC2) & M_AIDAC2)
42809 
42810 #define A_XGMAC_PORT_HSS_TXB_SEG_DIS_APP 0x18f0
42811 #define A_XGMAC_PORT_HSS_TXB_EXT_ADDR_DATA 0x18f8
42812 #define A_XGMAC_PORT_HSS_TXB_EXT_ADDR 0x18fc
42813 
42814 #define S_XADDR    2
42815 #define M_XADDR    0xfU
42816 #define V_XADDR(x) ((x) << S_XADDR)
42817 #define G_XADDR(x) (((x) >> S_XADDR) & M_XADDR)
42818 
42819 #define A_XGMAC_PORT_HSS_RXA_CFG_MODE 0x1900
42820 
42821 #define S_BW810    8
42822 #define V_BW810(x) ((x) << S_BW810)
42823 #define F_BW810    V_BW810(1U)
42824 
42825 #define S_AUXCLK    7
42826 #define V_AUXCLK(x) ((x) << S_AUXCLK)
42827 #define F_AUXCLK    V_AUXCLK(1U)
42828 
42829 #define S_DMSEL    4
42830 #define M_DMSEL    0x7U
42831 #define V_DMSEL(x) ((x) << S_DMSEL)
42832 #define G_DMSEL(x) (((x) >> S_DMSEL) & M_DMSEL)
42833 
42834 #define A_XGMAC_PORT_HSS_RXA_TEST_CTRL 0x1904
42835 
42836 #define S_RCLKEN    15
42837 #define V_RCLKEN(x) ((x) << S_RCLKEN)
42838 #define F_RCLKEN    V_RCLKEN(1U)
42839 
42840 #define S_RRATE    13
42841 #define M_RRATE    0x3U
42842 #define V_RRATE(x) ((x) << S_RRATE)
42843 #define G_RRATE(x) (((x) >> S_RRATE) & M_RRATE)
42844 
42845 #define S_LBFRCERROR    10
42846 #define V_LBFRCERROR(x) ((x) << S_LBFRCERROR)
42847 #define F_LBFRCERROR    V_LBFRCERROR(1U)
42848 
42849 #define S_LBERROR    9
42850 #define V_LBERROR(x) ((x) << S_LBERROR)
42851 #define F_LBERROR    V_LBERROR(1U)
42852 
42853 #define S_LBSYNC    8
42854 #define V_LBSYNC(x) ((x) << S_LBSYNC)
42855 #define F_LBSYNC    V_LBSYNC(1U)
42856 
42857 #define S_FDWRAPCLK    7
42858 #define V_FDWRAPCLK(x) ((x) << S_FDWRAPCLK)
42859 #define F_FDWRAPCLK    V_FDWRAPCLK(1U)
42860 
42861 #define S_FDWRAP    6
42862 #define V_FDWRAP(x) ((x) << S_FDWRAP)
42863 #define F_FDWRAP    V_FDWRAP(1U)
42864 
42865 #define S_PRST    4
42866 #define V_PRST(x) ((x) << S_PRST)
42867 #define F_PRST    V_PRST(1U)
42868 
42869 #define S_PCHKEN    3
42870 #define V_PCHKEN(x) ((x) << S_PCHKEN)
42871 #define F_PCHKEN    V_PCHKEN(1U)
42872 
42873 #define S_PRBSSEL    0
42874 #define M_PRBSSEL    0x7U
42875 #define V_PRBSSEL(x) ((x) << S_PRBSSEL)
42876 #define G_PRBSSEL(x) (((x) >> S_PRBSSEL) & M_PRBSSEL)
42877 
42878 #define A_XGMAC_PORT_HSS_RXA_PH_ROTATOR_CTRL 0x1908
42879 
42880 #define S_FTHROT    12
42881 #define M_FTHROT    0xfU
42882 #define V_FTHROT(x) ((x) << S_FTHROT)
42883 #define G_FTHROT(x) (((x) >> S_FTHROT) & M_FTHROT)
42884 
42885 #define S_RTHROT    11
42886 #define V_RTHROT(x) ((x) << S_RTHROT)
42887 #define F_RTHROT    V_RTHROT(1U)
42888 
42889 #define S_FILTCTL    7
42890 #define M_FILTCTL    0xfU
42891 #define V_FILTCTL(x) ((x) << S_FILTCTL)
42892 #define G_FILTCTL(x) (((x) >> S_FILTCTL) & M_FILTCTL)
42893 
42894 #define S_RSRVO    5
42895 #define M_RSRVO    0x3U
42896 #define V_RSRVO(x) ((x) << S_RSRVO)
42897 #define G_RSRVO(x) (((x) >> S_RSRVO) & M_RSRVO)
42898 
42899 #define S_EXTEL    4
42900 #define V_EXTEL(x) ((x) << S_EXTEL)
42901 #define F_EXTEL    V_EXTEL(1U)
42902 
42903 #define S_RSTONSTUCK    3
42904 #define V_RSTONSTUCK(x) ((x) << S_RSTONSTUCK)
42905 #define F_RSTONSTUCK    V_RSTONSTUCK(1U)
42906 
42907 #define S_FREEZEFW    2
42908 #define V_FREEZEFW(x) ((x) << S_FREEZEFW)
42909 #define F_FREEZEFW    V_FREEZEFW(1U)
42910 
42911 #define S_RESETFW    1
42912 #define V_RESETFW(x) ((x) << S_RESETFW)
42913 #define F_RESETFW    V_RESETFW(1U)
42914 
42915 #define S_SSCENABLE    0
42916 #define V_SSCENABLE(x) ((x) << S_SSCENABLE)
42917 #define F_SSCENABLE    V_SSCENABLE(1U)
42918 
42919 #define A_XGMAC_PORT_HSS_RXA_PH_ROTATOR_OFFSET_CTRL 0x190c
42920 
42921 #define S_RSNP    11
42922 #define V_RSNP(x) ((x) << S_RSNP)
42923 #define F_RSNP    V_RSNP(1U)
42924 
42925 #define S_TSOEN    10
42926 #define V_TSOEN(x) ((x) << S_TSOEN)
42927 #define F_TSOEN    V_TSOEN(1U)
42928 
42929 #define S_OFFEN    9
42930 #define V_OFFEN(x) ((x) << S_OFFEN)
42931 #define F_OFFEN    V_OFFEN(1U)
42932 
42933 #define S_TMSCAL    7
42934 #define M_TMSCAL    0x3U
42935 #define V_TMSCAL(x) ((x) << S_TMSCAL)
42936 #define G_TMSCAL(x) (((x) >> S_TMSCAL) & M_TMSCAL)
42937 
42938 #define S_APADJ    6
42939 #define V_APADJ(x) ((x) << S_APADJ)
42940 #define F_APADJ    V_APADJ(1U)
42941 
42942 #define S_RSEL    5
42943 #define V_RSEL(x) ((x) << S_RSEL)
42944 #define F_RSEL    V_RSEL(1U)
42945 
42946 #define S_PHOFFS    0
42947 #define M_PHOFFS    0x1fU
42948 #define V_PHOFFS(x) ((x) << S_PHOFFS)
42949 #define G_PHOFFS(x) (((x) >> S_PHOFFS) & M_PHOFFS)
42950 
42951 #define A_XGMAC_PORT_HSS_RXA_PH_ROTATOR_POSITION1 0x1910
42952 
42953 #define S_ROT0A    8
42954 #define M_ROT0A    0x3fU
42955 #define V_ROT0A(x) ((x) << S_ROT0A)
42956 #define G_ROT0A(x) (((x) >> S_ROT0A) & M_ROT0A)
42957 
42958 #define S_RTSEL_SNAPSHOT    0
42959 #define M_RTSEL_SNAPSHOT    0x3fU
42960 #define V_RTSEL_SNAPSHOT(x) ((x) << S_RTSEL_SNAPSHOT)
42961 #define G_RTSEL_SNAPSHOT(x) (((x) >> S_RTSEL_SNAPSHOT) & M_RTSEL_SNAPSHOT)
42962 
42963 #define A_XGMAC_PORT_HSS_RXA_PH_ROTATOR_POSITION2 0x1914
42964 
42965 #define S_ROT90    0
42966 #define M_ROT90    0x3fU
42967 #define V_ROT90(x) ((x) << S_ROT90)
42968 #define G_ROT90(x) (((x) >> S_ROT90) & M_ROT90)
42969 
42970 #define A_XGMAC_PORT_HSS_RXA_PH_ROTATOR_STATIC_PH_OFFSET 0x1918
42971 
42972 #define S_RCALER    15
42973 #define V_RCALER(x) ((x) << S_RCALER)
42974 #define F_RCALER    V_RCALER(1U)
42975 
42976 #define S_RAOOFF    10
42977 #define M_RAOOFF    0x1fU
42978 #define V_RAOOFF(x) ((x) << S_RAOOFF)
42979 #define G_RAOOFF(x) (((x) >> S_RAOOFF) & M_RAOOFF)
42980 
42981 #define S_RAEOFF    5
42982 #define M_RAEOFF    0x1fU
42983 #define V_RAEOFF(x) ((x) << S_RAEOFF)
42984 #define G_RAEOFF(x) (((x) >> S_RAEOFF) & M_RAEOFF)
42985 
42986 #define S_RDOFF    0
42987 #define M_RDOFF    0x1fU
42988 #define V_RDOFF(x) ((x) << S_RDOFF)
42989 #define G_RDOFF(x) (((x) >> S_RDOFF) & M_RDOFF)
42990 
42991 #define A_XGMAC_PORT_HSS_RXA_SIGDET_CTRL 0x191c
42992 
42993 #define S_SIGNSD    13
42994 #define M_SIGNSD    0x3U
42995 #define V_SIGNSD(x) ((x) << S_SIGNSD)
42996 #define G_SIGNSD(x) (((x) >> S_SIGNSD) & M_SIGNSD)
42997 
42998 #define S_DACSD    8
42999 #define M_DACSD    0x1fU
43000 #define V_DACSD(x) ((x) << S_DACSD)
43001 #define G_DACSD(x) (((x) >> S_DACSD) & M_DACSD)
43002 
43003 #define S_SDPDN    6
43004 #define V_SDPDN(x) ((x) << S_SDPDN)
43005 #define F_SDPDN    V_SDPDN(1U)
43006 
43007 #define S_SIGDET    5
43008 #define V_SIGDET(x) ((x) << S_SIGDET)
43009 #define F_SIGDET    V_SIGDET(1U)
43010 
43011 #define S_SDLVL    0
43012 #define M_SDLVL    0x1fU
43013 #define V_SDLVL(x) ((x) << S_SDLVL)
43014 #define G_SDLVL(x) (((x) >> S_SDLVL) & M_SDLVL)
43015 
43016 #define A_XGMAC_PORT_HSS_RXA_DFE_CTRL 0x1920
43017 
43018 #define S_REQCMP    15
43019 #define V_REQCMP(x) ((x) << S_REQCMP)
43020 #define F_REQCMP    V_REQCMP(1U)
43021 
43022 #define S_DFEREQ    14
43023 #define V_DFEREQ(x) ((x) << S_DFEREQ)
43024 #define F_DFEREQ    V_DFEREQ(1U)
43025 
43026 #define S_SPCEN    13
43027 #define V_SPCEN(x) ((x) << S_SPCEN)
43028 #define F_SPCEN    V_SPCEN(1U)
43029 
43030 #define S_GATEEN    12
43031 #define V_GATEEN(x) ((x) << S_GATEEN)
43032 #define F_GATEEN    V_GATEEN(1U)
43033 
43034 #define S_SPIFMT    9
43035 #define M_SPIFMT    0x7U
43036 #define V_SPIFMT(x) ((x) << S_SPIFMT)
43037 #define G_SPIFMT(x) (((x) >> S_SPIFMT) & M_SPIFMT)
43038 
43039 #define S_DFEPWR    6
43040 #define M_DFEPWR    0x7U
43041 #define V_DFEPWR(x) ((x) << S_DFEPWR)
43042 #define G_DFEPWR(x) (((x) >> S_DFEPWR) & M_DFEPWR)
43043 
43044 #define S_STNDBY    5
43045 #define V_STNDBY(x) ((x) << S_STNDBY)
43046 #define F_STNDBY    V_STNDBY(1U)
43047 
43048 #define S_FRCH    4
43049 #define V_FRCH(x) ((x) << S_FRCH)
43050 #define F_FRCH    V_FRCH(1U)
43051 
43052 #define S_NONRND    3
43053 #define V_NONRND(x) ((x) << S_NONRND)
43054 #define F_NONRND    V_NONRND(1U)
43055 
43056 #define S_NONRNF    2
43057 #define V_NONRNF(x) ((x) << S_NONRNF)
43058 #define F_NONRNF    V_NONRNF(1U)
43059 
43060 #define S_FSTLCK    1
43061 #define V_FSTLCK(x) ((x) << S_FSTLCK)
43062 #define F_FSTLCK    V_FSTLCK(1U)
43063 
43064 #define S_DFERST    0
43065 #define V_DFERST(x) ((x) << S_DFERST)
43066 #define F_DFERST    V_DFERST(1U)
43067 
43068 #define A_XGMAC_PORT_HSS_RXA_DFE_DATA_EDGE_SAMPLE 0x1924
43069 
43070 #define S_ESAMP    8
43071 #define M_ESAMP    0xffU
43072 #define V_ESAMP(x) ((x) << S_ESAMP)
43073 #define G_ESAMP(x) (((x) >> S_ESAMP) & M_ESAMP)
43074 
43075 #define S_DSAMP    0
43076 #define M_DSAMP    0xffU
43077 #define V_DSAMP(x) ((x) << S_DSAMP)
43078 #define G_DSAMP(x) (((x) >> S_DSAMP) & M_DSAMP)
43079 
43080 #define A_XGMAC_PORT_HSS_RXA_DFE_AMP_SAMPLE 0x1928
43081 
43082 #define S_SMODE    8
43083 #define M_SMODE    0xfU
43084 #define V_SMODE(x) ((x) << S_SMODE)
43085 #define G_SMODE(x) (((x) >> S_SMODE) & M_SMODE)
43086 
43087 #define S_ADCORR    7
43088 #define V_ADCORR(x) ((x) << S_ADCORR)
43089 #define F_ADCORR    V_ADCORR(1U)
43090 
43091 #define S_TRAINEN    6
43092 #define V_TRAINEN(x) ((x) << S_TRAINEN)
43093 #define F_TRAINEN    V_TRAINEN(1U)
43094 
43095 #define S_ASAMPQ    3
43096 #define M_ASAMPQ    0x7U
43097 #define V_ASAMPQ(x) ((x) << S_ASAMPQ)
43098 #define G_ASAMPQ(x) (((x) >> S_ASAMPQ) & M_ASAMPQ)
43099 
43100 #define S_ASAMP    0
43101 #define M_ASAMP    0x7U
43102 #define V_ASAMP(x) ((x) << S_ASAMP)
43103 #define G_ASAMP(x) (((x) >> S_ASAMP) & M_ASAMP)
43104 
43105 #define A_XGMAC_PORT_HSS_RXA_VGA_CTRL1 0x192c
43106 
43107 #define S_POLE    12
43108 #define M_POLE    0x3U
43109 #define V_POLE(x) ((x) << S_POLE)
43110 #define G_POLE(x) (((x) >> S_POLE) & M_POLE)
43111 
43112 #define S_PEAK    8
43113 #define M_PEAK    0x7U
43114 #define V_PEAK(x) ((x) << S_PEAK)
43115 #define G_PEAK(x) (((x) >> S_PEAK) & M_PEAK)
43116 
43117 #define S_VOFFSN    6
43118 #define M_VOFFSN    0x3U
43119 #define V_VOFFSN(x) ((x) << S_VOFFSN)
43120 #define G_VOFFSN(x) (((x) >> S_VOFFSN) & M_VOFFSN)
43121 
43122 #define S_VOFFA    0
43123 #define M_VOFFA    0x3fU
43124 #define V_VOFFA(x) ((x) << S_VOFFA)
43125 #define G_VOFFA(x) (((x) >> S_VOFFA) & M_VOFFA)
43126 
43127 #define A_XGMAC_PORT_HSS_RXA_VGA_CTRL2 0x1930
43128 
43129 #define S_SHORTV    10
43130 #define V_SHORTV(x) ((x) << S_SHORTV)
43131 #define F_SHORTV    V_SHORTV(1U)
43132 
43133 #define S_VGAIN    0
43134 #define M_VGAIN    0xfU
43135 #define V_VGAIN(x) ((x) << S_VGAIN)
43136 #define G_VGAIN(x) (((x) >> S_VGAIN) & M_VGAIN)
43137 
43138 #define A_XGMAC_PORT_HSS_RXA_VGA_CTRL3 0x1934
43139 
43140 #define S_HBND1    10
43141 #define V_HBND1(x) ((x) << S_HBND1)
43142 #define F_HBND1    V_HBND1(1U)
43143 
43144 #define S_HBND0    9
43145 #define V_HBND0(x) ((x) << S_HBND0)
43146 #define F_HBND0    V_HBND0(1U)
43147 
43148 #define S_VLCKD    8
43149 #define V_VLCKD(x) ((x) << S_VLCKD)
43150 #define F_VLCKD    V_VLCKD(1U)
43151 
43152 #define S_VLCKDF    7
43153 #define V_VLCKDF(x) ((x) << S_VLCKDF)
43154 #define F_VLCKDF    V_VLCKDF(1U)
43155 
43156 #define S_AMAXT    0
43157 #define M_AMAXT    0x7fU
43158 #define V_AMAXT(x) ((x) << S_AMAXT)
43159 #define G_AMAXT(x) (((x) >> S_AMAXT) & M_AMAXT)
43160 
43161 #define A_XGMAC_PORT_HSS_RXA_DFE_D00_D01_OFFSET 0x1938
43162 
43163 #define S_D01SN    13
43164 #define M_D01SN    0x3U
43165 #define V_D01SN(x) ((x) << S_D01SN)
43166 #define G_D01SN(x) (((x) >> S_D01SN) & M_D01SN)
43167 
43168 #define S_D01AMP    8
43169 #define M_D01AMP    0x1fU
43170 #define V_D01AMP(x) ((x) << S_D01AMP)
43171 #define G_D01AMP(x) (((x) >> S_D01AMP) & M_D01AMP)
43172 
43173 #define S_D00SN    5
43174 #define M_D00SN    0x3U
43175 #define V_D00SN(x) ((x) << S_D00SN)
43176 #define G_D00SN(x) (((x) >> S_D00SN) & M_D00SN)
43177 
43178 #define S_D00AMP    0
43179 #define M_D00AMP    0x1fU
43180 #define V_D00AMP(x) ((x) << S_D00AMP)
43181 #define G_D00AMP(x) (((x) >> S_D00AMP) & M_D00AMP)
43182 
43183 #define A_XGMAC_PORT_HSS_RXA_DFE_D10_D11_OFFSET 0x193c
43184 
43185 #define S_D11SN    13
43186 #define M_D11SN    0x3U
43187 #define V_D11SN(x) ((x) << S_D11SN)
43188 #define G_D11SN(x) (((x) >> S_D11SN) & M_D11SN)
43189 
43190 #define S_D11AMP    8
43191 #define M_D11AMP    0x1fU
43192 #define V_D11AMP(x) ((x) << S_D11AMP)
43193 #define G_D11AMP(x) (((x) >> S_D11AMP) & M_D11AMP)
43194 
43195 #define S_D10SN    5
43196 #define M_D10SN    0x3U
43197 #define V_D10SN(x) ((x) << S_D10SN)
43198 #define G_D10SN(x) (((x) >> S_D10SN) & M_D10SN)
43199 
43200 #define S_D10AMP    0
43201 #define M_D10AMP    0x1fU
43202 #define V_D10AMP(x) ((x) << S_D10AMP)
43203 #define G_D10AMP(x) (((x) >> S_D10AMP) & M_D10AMP)
43204 
43205 #define A_XGMAC_PORT_HSS_RXA_DFE_E0_E1_OFFSET 0x1940
43206 
43207 #define S_E1SN    13
43208 #define M_E1SN    0x3U
43209 #define V_E1SN(x) ((x) << S_E1SN)
43210 #define G_E1SN(x) (((x) >> S_E1SN) & M_E1SN)
43211 
43212 #define S_E1AMP    8
43213 #define M_E1AMP    0x1fU
43214 #define V_E1AMP(x) ((x) << S_E1AMP)
43215 #define G_E1AMP(x) (((x) >> S_E1AMP) & M_E1AMP)
43216 
43217 #define S_E0SN    5
43218 #define M_E0SN    0x3U
43219 #define V_E0SN(x) ((x) << S_E0SN)
43220 #define G_E0SN(x) (((x) >> S_E0SN) & M_E0SN)
43221 
43222 #define S_E0AMP    0
43223 #define M_E0AMP    0x1fU
43224 #define V_E0AMP(x) ((x) << S_E0AMP)
43225 #define G_E0AMP(x) (((x) >> S_E0AMP) & M_E0AMP)
43226 
43227 #define A_XGMAC_PORT_HSS_RXA_DACA_OFFSET 0x1944
43228 
43229 #define S_AOFFO    8
43230 #define M_AOFFO    0x3fU
43231 #define V_AOFFO(x) ((x) << S_AOFFO)
43232 #define G_AOFFO(x) (((x) >> S_AOFFO) & M_AOFFO)
43233 
43234 #define S_AOFFE    0
43235 #define M_AOFFE    0x3fU
43236 #define V_AOFFE(x) ((x) << S_AOFFE)
43237 #define G_AOFFE(x) (((x) >> S_AOFFE) & M_AOFFE)
43238 
43239 #define A_XGMAC_PORT_HSS_RXA_DACAP_DAC_AN_OFFSET 0x1948
43240 
43241 #define S_DACAN    8
43242 #define M_DACAN    0xffU
43243 #define V_DACAN(x) ((x) << S_DACAN)
43244 #define G_DACAN(x) (((x) >> S_DACAN) & M_DACAN)
43245 
43246 #define S_DACAP    0
43247 #define M_DACAP    0xffU
43248 #define V_DACAP(x) ((x) << S_DACAP)
43249 #define G_DACAP(x) (((x) >> S_DACAP) & M_DACAP)
43250 
43251 #define A_XGMAC_PORT_HSS_RXA_DACA_MIN 0x194c
43252 
43253 #define S_DACAZ    8
43254 #define M_DACAZ    0xffU
43255 #define V_DACAZ(x) ((x) << S_DACAZ)
43256 #define G_DACAZ(x) (((x) >> S_DACAZ) & M_DACAZ)
43257 
43258 #define S_DACAM    0
43259 #define M_DACAM    0xffU
43260 #define V_DACAM(x) ((x) << S_DACAM)
43261 #define G_DACAM(x) (((x) >> S_DACAM) & M_DACAM)
43262 
43263 #define A_XGMAC_PORT_HSS_RXA_ADAC_CTRL 0x1950
43264 
43265 #define S_ADSN    7
43266 #define M_ADSN    0x3U
43267 #define V_ADSN(x) ((x) << S_ADSN)
43268 #define G_ADSN(x) (((x) >> S_ADSN) & M_ADSN)
43269 
43270 #define S_ADMAG    0
43271 #define M_ADMAG    0x7fU
43272 #define V_ADMAG(x) ((x) << S_ADMAG)
43273 #define G_ADMAG(x) (((x) >> S_ADMAG) & M_ADMAG)
43274 
43275 #define A_XGMAC_PORT_HSS_RXA_DIGITAL_EYE_CTRL 0x1954
43276 
43277 #define S_BLKAZ    15
43278 #define V_BLKAZ(x) ((x) << S_BLKAZ)
43279 #define F_BLKAZ    V_BLKAZ(1U)
43280 
43281 #define S_WIDTH    10
43282 #define M_WIDTH    0x1fU
43283 #define V_WIDTH(x) ((x) << S_WIDTH)
43284 #define G_WIDTH(x) (((x) >> S_WIDTH) & M_WIDTH)
43285 
43286 #define S_MINWIDTH    5
43287 #define M_MINWIDTH    0x1fU
43288 #define V_MINWIDTH(x) ((x) << S_MINWIDTH)
43289 #define G_MINWIDTH(x) (((x) >> S_MINWIDTH) & M_MINWIDTH)
43290 
43291 #define S_MINAMP    0
43292 #define M_MINAMP    0x1fU
43293 #define V_MINAMP(x) ((x) << S_MINAMP)
43294 #define G_MINAMP(x) (((x) >> S_MINAMP) & M_MINAMP)
43295 
43296 #define A_XGMAC_PORT_HSS_RXA_DIGITAL_EYE_METRICS 0x1958
43297 
43298 #define S_EMBRDY    10
43299 #define V_EMBRDY(x) ((x) << S_EMBRDY)
43300 #define F_EMBRDY    V_EMBRDY(1U)
43301 
43302 #define S_EMBUMP    7
43303 #define V_EMBUMP(x) ((x) << S_EMBUMP)
43304 #define F_EMBUMP    V_EMBUMP(1U)
43305 
43306 #define S_EMMD    5
43307 #define M_EMMD    0x3U
43308 #define V_EMMD(x) ((x) << S_EMMD)
43309 #define G_EMMD(x) (((x) >> S_EMMD) & M_EMMD)
43310 
43311 #define S_EMPAT    1
43312 #define V_EMPAT(x) ((x) << S_EMPAT)
43313 #define F_EMPAT    V_EMPAT(1U)
43314 
43315 #define S_EMEN    0
43316 #define V_EMEN(x) ((x) << S_EMEN)
43317 #define F_EMEN    V_EMEN(1U)
43318 
43319 #define A_XGMAC_PORT_HSS_RXA_DFE_H1 0x195c
43320 
43321 #define S_H1OSN    14
43322 #define M_H1OSN    0x3U
43323 #define V_H1OSN(x) ((x) << S_H1OSN)
43324 #define G_H1OSN(x) (((x) >> S_H1OSN) & M_H1OSN)
43325 
43326 #define S_H1OMAG    8
43327 #define M_H1OMAG    0x3fU
43328 #define V_H1OMAG(x) ((x) << S_H1OMAG)
43329 #define G_H1OMAG(x) (((x) >> S_H1OMAG) & M_H1OMAG)
43330 
43331 #define S_H1ESN    6
43332 #define M_H1ESN    0x3U
43333 #define V_H1ESN(x) ((x) << S_H1ESN)
43334 #define G_H1ESN(x) (((x) >> S_H1ESN) & M_H1ESN)
43335 
43336 #define S_H1EMAG    0
43337 #define M_H1EMAG    0x3fU
43338 #define V_H1EMAG(x) ((x) << S_H1EMAG)
43339 #define G_H1EMAG(x) (((x) >> S_H1EMAG) & M_H1EMAG)
43340 
43341 #define A_XGMAC_PORT_HSS_RXA_DFE_H2 0x1960
43342 
43343 #define S_H2OSN    13
43344 #define M_H2OSN    0x3U
43345 #define V_H2OSN(x) ((x) << S_H2OSN)
43346 #define G_H2OSN(x) (((x) >> S_H2OSN) & M_H2OSN)
43347 
43348 #define S_H2OMAG    8
43349 #define M_H2OMAG    0x1fU
43350 #define V_H2OMAG(x) ((x) << S_H2OMAG)
43351 #define G_H2OMAG(x) (((x) >> S_H2OMAG) & M_H2OMAG)
43352 
43353 #define S_H2ESN    5
43354 #define M_H2ESN    0x3U
43355 #define V_H2ESN(x) ((x) << S_H2ESN)
43356 #define G_H2ESN(x) (((x) >> S_H2ESN) & M_H2ESN)
43357 
43358 #define S_H2EMAG    0
43359 #define M_H2EMAG    0x1fU
43360 #define V_H2EMAG(x) ((x) << S_H2EMAG)
43361 #define G_H2EMAG(x) (((x) >> S_H2EMAG) & M_H2EMAG)
43362 
43363 #define A_XGMAC_PORT_HSS_RXA_DFE_H3 0x1964
43364 
43365 #define S_H3OSN    12
43366 #define M_H3OSN    0x3U
43367 #define V_H3OSN(x) ((x) << S_H3OSN)
43368 #define G_H3OSN(x) (((x) >> S_H3OSN) & M_H3OSN)
43369 
43370 #define S_H3OMAG    8
43371 #define M_H3OMAG    0xfU
43372 #define V_H3OMAG(x) ((x) << S_H3OMAG)
43373 #define G_H3OMAG(x) (((x) >> S_H3OMAG) & M_H3OMAG)
43374 
43375 #define S_H3ESN    4
43376 #define M_H3ESN    0x3U
43377 #define V_H3ESN(x) ((x) << S_H3ESN)
43378 #define G_H3ESN(x) (((x) >> S_H3ESN) & M_H3ESN)
43379 
43380 #define S_H3EMAG    0
43381 #define M_H3EMAG    0xfU
43382 #define V_H3EMAG(x) ((x) << S_H3EMAG)
43383 #define G_H3EMAG(x) (((x) >> S_H3EMAG) & M_H3EMAG)
43384 
43385 #define A_XGMAC_PORT_HSS_RXA_DFE_H4 0x1968
43386 
43387 #define S_H4OSN    12
43388 #define M_H4OSN    0x3U
43389 #define V_H4OSN(x) ((x) << S_H4OSN)
43390 #define G_H4OSN(x) (((x) >> S_H4OSN) & M_H4OSN)
43391 
43392 #define S_H4OMAG    8
43393 #define M_H4OMAG    0xfU
43394 #define V_H4OMAG(x) ((x) << S_H4OMAG)
43395 #define G_H4OMAG(x) (((x) >> S_H4OMAG) & M_H4OMAG)
43396 
43397 #define S_H4ESN    4
43398 #define M_H4ESN    0x3U
43399 #define V_H4ESN(x) ((x) << S_H4ESN)
43400 #define G_H4ESN(x) (((x) >> S_H4ESN) & M_H4ESN)
43401 
43402 #define S_H4EMAG    0
43403 #define M_H4EMAG    0xfU
43404 #define V_H4EMAG(x) ((x) << S_H4EMAG)
43405 #define G_H4EMAG(x) (((x) >> S_H4EMAG) & M_H4EMAG)
43406 
43407 #define A_XGMAC_PORT_HSS_RXA_DFE_H5 0x196c
43408 
43409 #define S_H5OSN    12
43410 #define M_H5OSN    0x3U
43411 #define V_H5OSN(x) ((x) << S_H5OSN)
43412 #define G_H5OSN(x) (((x) >> S_H5OSN) & M_H5OSN)
43413 
43414 #define S_H5OMAG    8
43415 #define M_H5OMAG    0xfU
43416 #define V_H5OMAG(x) ((x) << S_H5OMAG)
43417 #define G_H5OMAG(x) (((x) >> S_H5OMAG) & M_H5OMAG)
43418 
43419 #define S_H5ESN    4
43420 #define M_H5ESN    0x3U
43421 #define V_H5ESN(x) ((x) << S_H5ESN)
43422 #define G_H5ESN(x) (((x) >> S_H5ESN) & M_H5ESN)
43423 
43424 #define S_H5EMAG    0
43425 #define M_H5EMAG    0xfU
43426 #define V_H5EMAG(x) ((x) << S_H5EMAG)
43427 #define G_H5EMAG(x) (((x) >> S_H5EMAG) & M_H5EMAG)
43428 
43429 #define A_XGMAC_PORT_HSS_RXA_DAC_DPC 0x1970
43430 
43431 #define S_DPCCVG    13
43432 #define V_DPCCVG(x) ((x) << S_DPCCVG)
43433 #define F_DPCCVG    V_DPCCVG(1U)
43434 
43435 #define S_DACCVG    12
43436 #define V_DACCVG(x) ((x) << S_DACCVG)
43437 #define F_DACCVG    V_DACCVG(1U)
43438 
43439 #define S_DPCTGT    9
43440 #define M_DPCTGT    0x7U
43441 #define V_DPCTGT(x) ((x) << S_DPCTGT)
43442 #define G_DPCTGT(x) (((x) >> S_DPCTGT) & M_DPCTGT)
43443 
43444 #define S_BLKH1T    8
43445 #define V_BLKH1T(x) ((x) << S_BLKH1T)
43446 #define F_BLKH1T    V_BLKH1T(1U)
43447 
43448 #define S_BLKOAE    7
43449 #define V_BLKOAE(x) ((x) << S_BLKOAE)
43450 #define F_BLKOAE    V_BLKOAE(1U)
43451 
43452 #define S_H1TGT    4
43453 #define M_H1TGT    0x7U
43454 #define V_H1TGT(x) ((x) << S_H1TGT)
43455 #define G_H1TGT(x) (((x) >> S_H1TGT) & M_H1TGT)
43456 
43457 #define S_OAE    0
43458 #define M_OAE    0xfU
43459 #define V_OAE(x) ((x) << S_OAE)
43460 #define G_OAE(x) (((x) >> S_OAE) & M_OAE)
43461 
43462 #define A_XGMAC_PORT_HSS_RXA_DDC 0x1974
43463 
43464 #define S_OLS    11
43465 #define M_OLS    0x1fU
43466 #define V_OLS(x) ((x) << S_OLS)
43467 #define G_OLS(x) (((x) >> S_OLS) & M_OLS)
43468 
43469 #define S_OES    6
43470 #define M_OES    0x1fU
43471 #define V_OES(x) ((x) << S_OES)
43472 #define G_OES(x) (((x) >> S_OES) & M_OES)
43473 
43474 #define S_BLKODEC    5
43475 #define V_BLKODEC(x) ((x) << S_BLKODEC)
43476 #define F_BLKODEC    V_BLKODEC(1U)
43477 
43478 #define S_ODEC    0
43479 #define M_ODEC    0x1fU
43480 #define V_ODEC(x) ((x) << S_ODEC)
43481 #define G_ODEC(x) (((x) >> S_ODEC) & M_ODEC)
43482 
43483 #define A_XGMAC_PORT_HSS_RXA_INTERNAL_STATUS 0x1978
43484 
43485 #define S_BER6    15
43486 #define V_BER6(x) ((x) << S_BER6)
43487 #define F_BER6    V_BER6(1U)
43488 
43489 #define S_BER6VAL    14
43490 #define V_BER6VAL(x) ((x) << S_BER6VAL)
43491 #define F_BER6VAL    V_BER6VAL(1U)
43492 
43493 #define S_BER3VAL    13
43494 #define V_BER3VAL(x) ((x) << S_BER3VAL)
43495 #define F_BER3VAL    V_BER3VAL(1U)
43496 
43497 #define S_DPCCMP    9
43498 #define V_DPCCMP(x) ((x) << S_DPCCMP)
43499 #define F_DPCCMP    V_DPCCMP(1U)
43500 
43501 #define S_DACCMP    8
43502 #define V_DACCMP(x) ((x) << S_DACCMP)
43503 #define F_DACCMP    V_DACCMP(1U)
43504 
43505 #define S_DDCCMP    7
43506 #define V_DDCCMP(x) ((x) << S_DDCCMP)
43507 #define F_DDCCMP    V_DDCCMP(1U)
43508 
43509 #define S_AERRFLG    6
43510 #define V_AERRFLG(x) ((x) << S_AERRFLG)
43511 #define F_AERRFLG    V_AERRFLG(1U)
43512 
43513 #define S_WERRFLG    5
43514 #define V_WERRFLG(x) ((x) << S_WERRFLG)
43515 #define F_WERRFLG    V_WERRFLG(1U)
43516 
43517 #define S_TRCMP    4
43518 #define V_TRCMP(x) ((x) << S_TRCMP)
43519 #define F_TRCMP    V_TRCMP(1U)
43520 
43521 #define S_VLCKF    3
43522 #define V_VLCKF(x) ((x) << S_VLCKF)
43523 #define F_VLCKF    V_VLCKF(1U)
43524 
43525 #define S_ROCADJ    2
43526 #define V_ROCADJ(x) ((x) << S_ROCADJ)
43527 #define F_ROCADJ    V_ROCADJ(1U)
43528 
43529 #define S_ROCCMP    1
43530 #define V_ROCCMP(x) ((x) << S_ROCCMP)
43531 #define F_ROCCMP    V_ROCCMP(1U)
43532 
43533 #define S_OCCMP    0
43534 #define V_OCCMP(x) ((x) << S_OCCMP)
43535 #define F_OCCMP    V_OCCMP(1U)
43536 
43537 #define A_XGMAC_PORT_HSS_RXA_DFE_FUNC_CTRL 0x197c
43538 
43539 #define S_FDPC    15
43540 #define V_FDPC(x) ((x) << S_FDPC)
43541 #define F_FDPC    V_FDPC(1U)
43542 
43543 #define S_FDAC    14
43544 #define V_FDAC(x) ((x) << S_FDAC)
43545 #define F_FDAC    V_FDAC(1U)
43546 
43547 #define S_FDDC    13
43548 #define V_FDDC(x) ((x) << S_FDDC)
43549 #define F_FDDC    V_FDDC(1U)
43550 
43551 #define S_FNRND    12
43552 #define V_FNRND(x) ((x) << S_FNRND)
43553 #define F_FNRND    V_FNRND(1U)
43554 
43555 #define S_FVGAIN    11
43556 #define V_FVGAIN(x) ((x) << S_FVGAIN)
43557 #define F_FVGAIN    V_FVGAIN(1U)
43558 
43559 #define S_FVOFF    10
43560 #define V_FVOFF(x) ((x) << S_FVOFF)
43561 #define F_FVOFF    V_FVOFF(1U)
43562 
43563 #define S_FSDET    9
43564 #define V_FSDET(x) ((x) << S_FSDET)
43565 #define F_FSDET    V_FSDET(1U)
43566 
43567 #define S_FBER6    8
43568 #define V_FBER6(x) ((x) << S_FBER6)
43569 #define F_FBER6    V_FBER6(1U)
43570 
43571 #define S_FROTO    7
43572 #define V_FROTO(x) ((x) << S_FROTO)
43573 #define F_FROTO    V_FROTO(1U)
43574 
43575 #define S_FH4H5    6
43576 #define V_FH4H5(x) ((x) << S_FH4H5)
43577 #define F_FH4H5    V_FH4H5(1U)
43578 
43579 #define S_FH2H3    5
43580 #define V_FH2H3(x) ((x) << S_FH2H3)
43581 #define F_FH2H3    V_FH2H3(1U)
43582 
43583 #define S_FH1    4
43584 #define V_FH1(x) ((x) << S_FH1)
43585 #define F_FH1    V_FH1(1U)
43586 
43587 #define S_FH1SN    3
43588 #define V_FH1SN(x) ((x) << S_FH1SN)
43589 #define F_FH1SN    V_FH1SN(1U)
43590 
43591 #define S_FNRDF    2
43592 #define V_FNRDF(x) ((x) << S_FNRDF)
43593 #define F_FNRDF    V_FNRDF(1U)
43594 
43595 #define S_FADAC    0
43596 #define V_FADAC(x) ((x) << S_FADAC)
43597 #define F_FADAC    V_FADAC(1U)
43598 
43599 #define A_XGMAC_PORT_HSS_RXB_CFG_MODE 0x1980
43600 #define A_XGMAC_PORT_HSS_RXB_TEST_CTRL 0x1984
43601 #define A_XGMAC_PORT_HSS_RXB_PH_ROTATOR_CTRL 0x1988
43602 #define A_XGMAC_PORT_HSS_RXB_PH_ROTATOR_OFFSET_CTRL 0x198c
43603 #define A_XGMAC_PORT_HSS_RXB_PH_ROTATOR_POSITION1 0x1990
43604 #define A_XGMAC_PORT_HSS_RXB_PH_ROTATOR_POSITION2 0x1994
43605 #define A_XGMAC_PORT_HSS_RXB_PH_ROTATOR_STATIC_PH_OFFSET 0x1998
43606 #define A_XGMAC_PORT_HSS_RXB_SIGDET_CTRL 0x199c
43607 #define A_XGMAC_PORT_HSS_RXB_DFE_CTRL 0x19a0
43608 #define A_XGMAC_PORT_HSS_RXB_DFE_DATA_EDGE_SAMPLE 0x19a4
43609 #define A_XGMAC_PORT_HSS_RXB_DFE_AMP_SAMPLE 0x19a8
43610 #define A_XGMAC_PORT_HSS_RXB_VGA_CTRL1 0x19ac
43611 #define A_XGMAC_PORT_HSS_RXB_VGA_CTRL2 0x19b0
43612 #define A_XGMAC_PORT_HSS_RXB_VGA_CTRL3 0x19b4
43613 #define A_XGMAC_PORT_HSS_RXB_DFE_D00_D01_OFFSET 0x19b8
43614 #define A_XGMAC_PORT_HSS_RXB_DFE_D10_D11_OFFSET 0x19bc
43615 #define A_XGMAC_PORT_HSS_RXB_DFE_E0_E1_OFFSET 0x19c0
43616 #define A_XGMAC_PORT_HSS_RXB_DACA_OFFSET 0x19c4
43617 #define A_XGMAC_PORT_HSS_RXB_DACAP_DAC_AN_OFFSET 0x19c8
43618 #define A_XGMAC_PORT_HSS_RXB_DACA_MIN 0x19cc
43619 #define A_XGMAC_PORT_HSS_RXB_ADAC_CTRL 0x19d0
43620 #define A_XGMAC_PORT_HSS_RXB_DIGITAL_EYE_CTRL 0x19d4
43621 #define A_XGMAC_PORT_HSS_RXB_DIGITAL_EYE_METRICS 0x19d8
43622 #define A_XGMAC_PORT_HSS_RXB_DFE_H1 0x19dc
43623 #define A_XGMAC_PORT_HSS_RXB_DFE_H2 0x19e0
43624 #define A_XGMAC_PORT_HSS_RXB_DFE_H3 0x19e4
43625 #define A_XGMAC_PORT_HSS_RXB_DFE_H4 0x19e8
43626 #define A_XGMAC_PORT_HSS_RXB_DFE_H5 0x19ec
43627 #define A_XGMAC_PORT_HSS_RXB_DAC_DPC 0x19f0
43628 #define A_XGMAC_PORT_HSS_RXB_DDC 0x19f4
43629 #define A_XGMAC_PORT_HSS_RXB_INTERNAL_STATUS 0x19f8
43630 #define A_XGMAC_PORT_HSS_RXB_DFE_FUNC_CTRL 0x19fc
43631 #define A_XGMAC_PORT_HSS_TXC_MODE_CFG 0x1a00
43632 #define A_XGMAC_PORT_HSS_TXC_TEST_CTRL 0x1a04
43633 #define A_XGMAC_PORT_HSS_TXC_COEFF_CTRL 0x1a08
43634 #define A_XGMAC_PORT_HSS_TXC_DRIVER_MODE 0x1a0c
43635 #define A_XGMAC_PORT_HSS_TXC_DRIVER_OVR_CTRL 0x1a10
43636 #define A_XGMAC_PORT_HSS_TXC_TDM_BIASGEN_STANDBY_TIMER 0x1a14
43637 #define A_XGMAC_PORT_HSS_TXC_TDM_BIASGEN_PWRON_TIMER 0x1a18
43638 #define A_XGMAC_PORT_HSS_TXC_TAP0_COEFF 0x1a20
43639 #define A_XGMAC_PORT_HSS_TXC_TAP1_COEFF 0x1a24
43640 #define A_XGMAC_PORT_HSS_TXC_TAP2_COEFF 0x1a28
43641 #define A_XGMAC_PORT_HSS_TXC_PWR 0x1a30
43642 #define A_XGMAC_PORT_HSS_TXC_POLARITY 0x1a34
43643 #define A_XGMAC_PORT_HSS_TXC_8023AP_AE_CMD 0x1a38
43644 #define A_XGMAC_PORT_HSS_TXC_8023AP_AE_STATUS 0x1a3c
43645 #define A_XGMAC_PORT_HSS_TXC_TAP0_IDAC_OVR 0x1a40
43646 #define A_XGMAC_PORT_HSS_TXC_TAP1_IDAC_OVR 0x1a44
43647 #define A_XGMAC_PORT_HSS_TXC_TAP2_IDAC_OVR 0x1a48
43648 #define A_XGMAC_PORT_HSS_TXC_PWR_DAC_OVR 0x1a50
43649 #define A_XGMAC_PORT_HSS_TXC_PWR_DAC 0x1a54
43650 #define A_XGMAC_PORT_HSS_TXC_TAP0_IDAC_APP 0x1a60
43651 #define A_XGMAC_PORT_HSS_TXC_TAP1_IDAC_APP 0x1a64
43652 #define A_XGMAC_PORT_HSS_TXC_TAP2_IDAC_APP 0x1a68
43653 #define A_XGMAC_PORT_HSS_TXC_SEG_DIS_APP 0x1a70
43654 #define A_XGMAC_PORT_HSS_TXC_EXT_ADDR_DATA 0x1a78
43655 #define A_XGMAC_PORT_HSS_TXC_EXT_ADDR 0x1a7c
43656 #define A_XGMAC_PORT_HSS_TXD_MODE_CFG 0x1a80
43657 #define A_XGMAC_PORT_HSS_TXD_TEST_CTRL 0x1a84
43658 #define A_XGMAC_PORT_HSS_TXD_COEFF_CTRL 0x1a88
43659 #define A_XGMAC_PORT_HSS_TXD_DRIVER_MODE 0x1a8c
43660 #define A_XGMAC_PORT_HSS_TXD_DRIVER_OVR_CTRL 0x1a90
43661 #define A_XGMAC_PORT_HSS_TXD_TDM_BIASGEN_STANDBY_TIMER 0x1a94
43662 #define A_XGMAC_PORT_HSS_TXD_TDM_BIASGEN_PWRON_TIMER 0x1a98
43663 #define A_XGMAC_PORT_HSS_TXD_TAP0_COEFF 0x1aa0
43664 #define A_XGMAC_PORT_HSS_TXD_TAP1_COEFF 0x1aa4
43665 #define A_XGMAC_PORT_HSS_TXD_TAP2_COEFF 0x1aa8
43666 #define A_XGMAC_PORT_HSS_TXD_PWR 0x1ab0
43667 #define A_XGMAC_PORT_HSS_TXD_POLARITY 0x1ab4
43668 #define A_XGMAC_PORT_HSS_TXD_8023AP_AE_CMD 0x1ab8
43669 #define A_XGMAC_PORT_HSS_TXD_8023AP_AE_STATUS 0x1abc
43670 #define A_XGMAC_PORT_HSS_TXD_TAP0_IDAC_OVR 0x1ac0
43671 #define A_XGMAC_PORT_HSS_TXD_TAP1_IDAC_OVR 0x1ac4
43672 #define A_XGMAC_PORT_HSS_TXD_TAP2_IDAC_OVR 0x1ac8
43673 #define A_XGMAC_PORT_HSS_TXD_PWR_DAC_OVR 0x1ad0
43674 #define A_XGMAC_PORT_HSS_TXD_PWR_DAC 0x1ad4
43675 #define A_XGMAC_PORT_HSS_TXD_TAP0_IDAC_APP 0x1ae0
43676 #define A_XGMAC_PORT_HSS_TXD_TAP1_IDAC_APP 0x1ae4
43677 #define A_XGMAC_PORT_HSS_TXD_TAP2_IDAC_APP 0x1ae8
43678 #define A_XGMAC_PORT_HSS_TXD_SEG_DIS_APP 0x1af0
43679 #define A_XGMAC_PORT_HSS_TXD_EXT_ADDR_DATA 0x1af8
43680 #define A_XGMAC_PORT_HSS_TXD_EXT_ADDR 0x1afc
43681 #define A_XGMAC_PORT_HSS_RXC_CFG_MODE 0x1b00
43682 #define A_XGMAC_PORT_HSS_RXC_TEST_CTRL 0x1b04
43683 #define A_XGMAC_PORT_HSS_RXC_PH_ROTATOR_CTRL 0x1b08
43684 #define A_XGMAC_PORT_HSS_RXC_PH_ROTATOR_OFFSET_CTRL 0x1b0c
43685 #define A_XGMAC_PORT_HSS_RXC_PH_ROTATOR_POSITION1 0x1b10
43686 #define A_XGMAC_PORT_HSS_RXC_PH_ROTATOR_POSITION2 0x1b14
43687 #define A_XGMAC_PORT_HSS_RXC_PH_ROTATOR_STATIC_PH_OFFSET 0x1b18
43688 #define A_XGMAC_PORT_HSS_RXC_SIGDET_CTRL 0x1b1c
43689 #define A_XGMAC_PORT_HSS_RXC_DFE_CTRL 0x1b20
43690 #define A_XGMAC_PORT_HSS_RXC_DFE_DATA_EDGE_SAMPLE 0x1b24
43691 #define A_XGMAC_PORT_HSS_RXC_DFE_AMP_SAMPLE 0x1b28
43692 #define A_XGMAC_PORT_HSS_RXC_VGA_CTRL1 0x1b2c
43693 #define A_XGMAC_PORT_HSS_RXC_VGA_CTRL2 0x1b30
43694 #define A_XGMAC_PORT_HSS_RXC_VGA_CTRL3 0x1b34
43695 #define A_XGMAC_PORT_HSS_RXC_DFE_D00_D01_OFFSET 0x1b38
43696 #define A_XGMAC_PORT_HSS_RXC_DFE_D10_D11_OFFSET 0x1b3c
43697 #define A_XGMAC_PORT_HSS_RXC_DFE_E0_E1_OFFSET 0x1b40
43698 #define A_XGMAC_PORT_HSS_RXC_DACA_OFFSET 0x1b44
43699 #define A_XGMAC_PORT_HSS_RXC_DACAP_DAC_AN_OFFSET 0x1b48
43700 #define A_XGMAC_PORT_HSS_RXC_DACA_MIN 0x1b4c
43701 #define A_XGMAC_PORT_HSS_RXC_ADAC_CTRL 0x1b50
43702 #define A_XGMAC_PORT_HSS_RXC_DIGITAL_EYE_CTRL 0x1b54
43703 #define A_XGMAC_PORT_HSS_RXC_DIGITAL_EYE_METRICS 0x1b58
43704 #define A_XGMAC_PORT_HSS_RXC_DFE_H1 0x1b5c
43705 #define A_XGMAC_PORT_HSS_RXC_DFE_H2 0x1b60
43706 #define A_XGMAC_PORT_HSS_RXC_DFE_H3 0x1b64
43707 #define A_XGMAC_PORT_HSS_RXC_DFE_H4 0x1b68
43708 #define A_XGMAC_PORT_HSS_RXC_DFE_H5 0x1b6c
43709 #define A_XGMAC_PORT_HSS_RXC_DAC_DPC 0x1b70
43710 #define A_XGMAC_PORT_HSS_RXC_DDC 0x1b74
43711 #define A_XGMAC_PORT_HSS_RXC_INTERNAL_STATUS 0x1b78
43712 #define A_XGMAC_PORT_HSS_RXC_DFE_FUNC_CTRL 0x1b7c
43713 #define A_XGMAC_PORT_HSS_RXD_CFG_MODE 0x1b80
43714 #define A_XGMAC_PORT_HSS_RXD_TEST_CTRL 0x1b84
43715 #define A_XGMAC_PORT_HSS_RXD_PH_ROTATOR_CTRL 0x1b88
43716 #define A_XGMAC_PORT_HSS_RXD_PH_ROTATOR_OFFSET_CTRL 0x1b8c
43717 #define A_XGMAC_PORT_HSS_RXD_PH_ROTATOR_POSITION1 0x1b90
43718 #define A_XGMAC_PORT_HSS_RXD_PH_ROTATOR_POSITION2 0x1b94
43719 #define A_XGMAC_PORT_HSS_RXD_PH_ROTATOR_STATIC_PH_OFFSET 0x1b98
43720 #define A_XGMAC_PORT_HSS_RXD_SIGDET_CTRL 0x1b9c
43721 #define A_XGMAC_PORT_HSS_RXD_DFE_CTRL 0x1ba0
43722 #define A_XGMAC_PORT_HSS_RXD_DFE_DATA_EDGE_SAMPLE 0x1ba4
43723 #define A_XGMAC_PORT_HSS_RXD_DFE_AMP_SAMPLE 0x1ba8
43724 #define A_XGMAC_PORT_HSS_RXD_VGA_CTRL1 0x1bac
43725 #define A_XGMAC_PORT_HSS_RXD_VGA_CTRL2 0x1bb0
43726 #define A_XGMAC_PORT_HSS_RXD_VGA_CTRL3 0x1bb4
43727 #define A_XGMAC_PORT_HSS_RXD_DFE_D00_D01_OFFSET 0x1bb8
43728 #define A_XGMAC_PORT_HSS_RXD_DFE_D10_D11_OFFSET 0x1bbc
43729 #define A_XGMAC_PORT_HSS_RXD_DFE_E0_E1_OFFSET 0x1bc0
43730 #define A_XGMAC_PORT_HSS_RXD_DACA_OFFSET 0x1bc4
43731 #define A_XGMAC_PORT_HSS_RXD_DACAP_DAC_AN_OFFSET 0x1bc8
43732 #define A_XGMAC_PORT_HSS_RXD_DACA_MIN 0x1bcc
43733 #define A_XGMAC_PORT_HSS_RXD_ADAC_CTRL 0x1bd0
43734 #define A_XGMAC_PORT_HSS_RXD_DIGITAL_EYE_CTRL 0x1bd4
43735 #define A_XGMAC_PORT_HSS_RXD_DIGITAL_EYE_METRICS 0x1bd8
43736 #define A_XGMAC_PORT_HSS_RXD_DFE_H1 0x1bdc
43737 #define A_XGMAC_PORT_HSS_RXD_DFE_H2 0x1be0
43738 #define A_XGMAC_PORT_HSS_RXD_DFE_H3 0x1be4
43739 #define A_XGMAC_PORT_HSS_RXD_DFE_H4 0x1be8
43740 #define A_XGMAC_PORT_HSS_RXD_DFE_H5 0x1bec
43741 #define A_XGMAC_PORT_HSS_RXD_DAC_DPC 0x1bf0
43742 #define A_XGMAC_PORT_HSS_RXD_DDC 0x1bf4
43743 #define A_XGMAC_PORT_HSS_RXD_INTERNAL_STATUS 0x1bf8
43744 #define A_XGMAC_PORT_HSS_RXD_DFE_FUNC_CTRL 0x1bfc
43745 #define A_XGMAC_PORT_HSS_VCO_COARSE_CALIBRATION_0 0x1c00
43746 
43747 #define S_BSELO    0
43748 #define M_BSELO    0xfU
43749 #define V_BSELO(x) ((x) << S_BSELO)
43750 #define G_BSELO(x) (((x) >> S_BSELO) & M_BSELO)
43751 
43752 #define A_XGMAC_PORT_HSS_VCO_COARSE_CALIBRATION_1 0x1c04
43753 
43754 #define S_LDET    4
43755 #define V_LDET(x) ((x) << S_LDET)
43756 #define F_LDET    V_LDET(1U)
43757 
43758 #define S_CCERR    3
43759 #define V_CCERR(x) ((x) << S_CCERR)
43760 #define F_CCERR    V_CCERR(1U)
43761 
43762 #define S_CCCMP    2
43763 #define V_CCCMP(x) ((x) << S_CCCMP)
43764 #define F_CCCMP    V_CCCMP(1U)
43765 
43766 #define A_XGMAC_PORT_HSS_VCO_COARSE_CALIBRATION_2 0x1c08
43767 
43768 #define S_BSELI    0
43769 #define M_BSELI    0xfU
43770 #define V_BSELI(x) ((x) << S_BSELI)
43771 #define G_BSELI(x) (((x) >> S_BSELI) & M_BSELI)
43772 
43773 #define A_XGMAC_PORT_HSS_VCO_COARSE_CALIBRATION_3 0x1c0c
43774 
43775 #define S_VISEL    4
43776 #define V_VISEL(x) ((x) << S_VISEL)
43777 #define F_VISEL    V_VISEL(1U)
43778 
43779 #define S_FMIN    3
43780 #define V_FMIN(x) ((x) << S_FMIN)
43781 #define F_FMIN    V_FMIN(1U)
43782 
43783 #define S_FMAX    2
43784 #define V_FMAX(x) ((x) << S_FMAX)
43785 #define F_FMAX    V_FMAX(1U)
43786 
43787 #define S_CVHOLD    1
43788 #define V_CVHOLD(x) ((x) << S_CVHOLD)
43789 #define F_CVHOLD    V_CVHOLD(1U)
43790 
43791 #define S_TCDIS    0
43792 #define V_TCDIS(x) ((x) << S_TCDIS)
43793 #define F_TCDIS    V_TCDIS(1U)
43794 
43795 #define A_XGMAC_PORT_HSS_VCO_COARSE_CALIBRATION_4 0x1c10
43796 
43797 #define S_CMETH    2
43798 #define V_CMETH(x) ((x) << S_CMETH)
43799 #define F_CMETH    V_CMETH(1U)
43800 
43801 #define S_RECAL    1
43802 #define V_RECAL(x) ((x) << S_RECAL)
43803 #define F_RECAL    V_RECAL(1U)
43804 
43805 #define S_CCLD    0
43806 #define V_CCLD(x) ((x) << S_CCLD)
43807 #define F_CCLD    V_CCLD(1U)
43808 
43809 #define A_XGMAC_PORT_HSS_ANALOG_TEST_MUX 0x1c14
43810 
43811 #define S_ATST    0
43812 #define M_ATST    0x1fU
43813 #define V_ATST(x) ((x) << S_ATST)
43814 #define G_ATST(x) (((x) >> S_ATST) & M_ATST)
43815 
43816 #define A_XGMAC_PORT_HSS_PORT_EN_0 0x1c18
43817 
43818 #define S_RXDEN    7
43819 #define V_RXDEN(x) ((x) << S_RXDEN)
43820 #define F_RXDEN    V_RXDEN(1U)
43821 
43822 #define S_RXCEN    6
43823 #define V_RXCEN(x) ((x) << S_RXCEN)
43824 #define F_RXCEN    V_RXCEN(1U)
43825 
43826 #define S_TXDEN    5
43827 #define V_TXDEN(x) ((x) << S_TXDEN)
43828 #define F_TXDEN    V_TXDEN(1U)
43829 
43830 #define S_TXCEN    4
43831 #define V_TXCEN(x) ((x) << S_TXCEN)
43832 #define F_TXCEN    V_TXCEN(1U)
43833 
43834 #define S_RXBEN    3
43835 #define V_RXBEN(x) ((x) << S_RXBEN)
43836 #define F_RXBEN    V_RXBEN(1U)
43837 
43838 #define S_RXAEN    2
43839 #define V_RXAEN(x) ((x) << S_RXAEN)
43840 #define F_RXAEN    V_RXAEN(1U)
43841 
43842 #define S_TXBEN    1
43843 #define V_TXBEN(x) ((x) << S_TXBEN)
43844 #define F_TXBEN    V_TXBEN(1U)
43845 
43846 #define S_TXAEN    0
43847 #define V_TXAEN(x) ((x) << S_TXAEN)
43848 #define F_TXAEN    V_TXAEN(1U)
43849 
43850 #define A_XGMAC_PORT_HSS_PORT_RESET_0 0x1c20
43851 
43852 #define S_RXDRST    7
43853 #define V_RXDRST(x) ((x) << S_RXDRST)
43854 #define F_RXDRST    V_RXDRST(1U)
43855 
43856 #define S_RXCRST    6
43857 #define V_RXCRST(x) ((x) << S_RXCRST)
43858 #define F_RXCRST    V_RXCRST(1U)
43859 
43860 #define S_TXDRST    5
43861 #define V_TXDRST(x) ((x) << S_TXDRST)
43862 #define F_TXDRST    V_TXDRST(1U)
43863 
43864 #define S_TXCRST    4
43865 #define V_TXCRST(x) ((x) << S_TXCRST)
43866 #define F_TXCRST    V_TXCRST(1U)
43867 
43868 #define S_RXBRST    3
43869 #define V_RXBRST(x) ((x) << S_RXBRST)
43870 #define F_RXBRST    V_RXBRST(1U)
43871 
43872 #define S_RXARST    2
43873 #define V_RXARST(x) ((x) << S_RXARST)
43874 #define F_RXARST    V_RXARST(1U)
43875 
43876 #define S_TXBRST    1
43877 #define V_TXBRST(x) ((x) << S_TXBRST)
43878 #define F_TXBRST    V_TXBRST(1U)
43879 
43880 #define S_TXARST    0
43881 #define V_TXARST(x) ((x) << S_TXARST)
43882 #define F_TXARST    V_TXARST(1U)
43883 
43884 #define A_XGMAC_PORT_HSS_CHARGE_PUMP_CTRL 0x1c28
43885 
43886 #define S_ENCPIS    2
43887 #define V_ENCPIS(x) ((x) << S_ENCPIS)
43888 #define F_ENCPIS    V_ENCPIS(1U)
43889 
43890 #define S_CPISEL    0
43891 #define M_CPISEL    0x3U
43892 #define V_CPISEL(x) ((x) << S_CPISEL)
43893 #define G_CPISEL(x) (((x) >> S_CPISEL) & M_CPISEL)
43894 
43895 #define A_XGMAC_PORT_HSS_BAND_GAP_CTRL 0x1c2c
43896 
43897 #define S_BGCTL    0
43898 #define M_BGCTL    0x1fU
43899 #define V_BGCTL(x) ((x) << S_BGCTL)
43900 #define G_BGCTL(x) (((x) >> S_BGCTL) & M_BGCTL)
43901 
43902 #define A_XGMAC_PORT_HSS_LOFREQ_OVR 0x1c30
43903 
43904 #define S_LFREQ2    3
43905 #define V_LFREQ2(x) ((x) << S_LFREQ2)
43906 #define F_LFREQ2    V_LFREQ2(1U)
43907 
43908 #define S_LFREQ1    2
43909 #define V_LFREQ1(x) ((x) << S_LFREQ1)
43910 #define F_LFREQ1    V_LFREQ1(1U)
43911 
43912 #define S_LFREQO    1
43913 #define V_LFREQO(x) ((x) << S_LFREQO)
43914 #define F_LFREQO    V_LFREQO(1U)
43915 
43916 #define S_LFSEL    0
43917 #define V_LFSEL(x) ((x) << S_LFSEL)
43918 #define F_LFSEL    V_LFSEL(1U)
43919 
43920 #define A_XGMAC_PORT_HSS_VOLTAGE_BOOST_CTRL 0x1c38
43921 
43922 #define S_PFVAL    2
43923 #define V_PFVAL(x) ((x) << S_PFVAL)
43924 #define F_PFVAL    V_PFVAL(1U)
43925 
43926 #define S_PFEN    1
43927 #define V_PFEN(x) ((x) << S_PFEN)
43928 #define F_PFEN    V_PFEN(1U)
43929 
43930 #define S_VBADJ    0
43931 #define V_VBADJ(x) ((x) << S_VBADJ)
43932 #define F_VBADJ    V_VBADJ(1U)
43933 
43934 #define A_XGMAC_PORT_HSS_TX_MODE_CFG 0x1c80
43935 #define A_XGMAC_PORT_HSS_TXTEST_CTRL 0x1c84
43936 #define A_XGMAC_PORT_HSS_TX_COEFF_CTRL 0x1c88
43937 #define A_XGMAC_PORT_HSS_TX_DRIVER_MODE 0x1c8c
43938 #define A_XGMAC_PORT_HSS_TX_DRIVER_OVR_CTRL 0x1c90
43939 #define A_XGMAC_PORT_HSS_TX_TDM_BIASGEN_STANDBY_TIMER 0x1c94
43940 #define A_XGMAC_PORT_HSS_TX_TDM_BIASGEN_PWRON_TIMER 0x1c98
43941 #define A_XGMAC_PORT_HSS_TX_TAP0_COEFF 0x1ca0
43942 #define A_XGMAC_PORT_HSS_TX_TAP1_COEFF 0x1ca4
43943 #define A_XGMAC_PORT_HSS_TX_TAP2_COEFF 0x1ca8
43944 #define A_XGMAC_PORT_HSS_TX_PWR 0x1cb0
43945 #define A_XGMAC_PORT_HSS_TX_POLARITY 0x1cb4
43946 #define A_XGMAC_PORT_HSS_TX_8023AP_AE_CMD 0x1cb8
43947 #define A_XGMAC_PORT_HSS_TX_8023AP_AE_STATUS 0x1cbc
43948 #define A_XGMAC_PORT_HSS_TX_TAP0_IDAC_OVR 0x1cc0
43949 #define A_XGMAC_PORT_HSS_TX_TAP1_IDAC_OVR 0x1cc4
43950 #define A_XGMAC_PORT_HSS_TX_TAP2_IDAC_OVR 0x1cc8
43951 #define A_XGMAC_PORT_HSS_TX_PWR_DAC_OVR 0x1cd0
43952 #define A_XGMAC_PORT_HSS_TX_PWR_DAC 0x1cd4
43953 #define A_XGMAC_PORT_HSS_TX_TAP0_IDAC_APP 0x1ce0
43954 #define A_XGMAC_PORT_HSS_TX_TAP1_IDAC_APP 0x1ce4
43955 #define A_XGMAC_PORT_HSS_TX_TAP2_IDAC_APP 0x1ce8
43956 #define A_XGMAC_PORT_HSS_TX_SEG_DIS_APP 0x1cf0
43957 #define A_XGMAC_PORT_HSS_TX_EXT_ADDR_DATA 0x1cf8
43958 #define A_XGMAC_PORT_HSS_TX_EXT_ADDR 0x1cfc
43959 #define A_XGMAC_PORT_HSS_RX_CFG_MODE 0x1d00
43960 #define A_XGMAC_PORT_HSS_RXTEST_CTRL 0x1d04
43961 #define A_XGMAC_PORT_HSS_RX_PH_ROTATOR_CTRL 0x1d08
43962 #define A_XGMAC_PORT_HSS_RX_PH_ROTATOR_OFFSET_CTRL 0x1d0c
43963 #define A_XGMAC_PORT_HSS_RX_PH_ROTATOR_POSITION1 0x1d10
43964 #define A_XGMAC_PORT_HSS_RX_PH_ROTATOR_POSITION2 0x1d14
43965 #define A_XGMAC_PORT_HSS_RX_PH_ROTATOR_STATIC_PH_OFFSET 0x1d18
43966 #define A_XGMAC_PORT_HSS_RX_SIGDET_CTRL 0x1d1c
43967 #define A_XGMAC_PORT_HSS_RX_DFE_CTRL 0x1d20
43968 #define A_XGMAC_PORT_HSS_RX_DFE_DATA_EDGE_SAMPLE 0x1d24
43969 #define A_XGMAC_PORT_HSS_RX_DFE_AMP_SAMPLE 0x1d28
43970 #define A_XGMAC_PORT_HSS_RX_VGA_CTRL1 0x1d2c
43971 #define A_XGMAC_PORT_HSS_RX_VGA_CTRL2 0x1d30
43972 #define A_XGMAC_PORT_HSS_RX_VGA_CTRL3 0x1d34
43973 #define A_XGMAC_PORT_HSS_RX_DFE_D00_D01_OFFSET 0x1d38
43974 #define A_XGMAC_PORT_HSS_RX_DFE_D10_D11_OFFSET 0x1d3c
43975 #define A_XGMAC_PORT_HSS_RX_DFE_E0_E1_OFFSET 0x1d40
43976 #define A_XGMAC_PORT_HSS_RX_DACA_OFFSET 0x1d44
43977 #define A_XGMAC_PORT_HSS_RX_DACAP_DAC_AN_OFFSET 0x1d48
43978 #define A_XGMAC_PORT_HSS_RX_DACA_MIN 0x1d4c
43979 #define A_XGMAC_PORT_HSS_RX_ADAC_CTRL 0x1d50
43980 #define A_XGMAC_PORT_HSS_RX_DIGITAL_EYE_CTRL 0x1d54
43981 #define A_XGMAC_PORT_HSS_RX_DIGITAL_EYE_METRICS 0x1d58
43982 #define A_XGMAC_PORT_HSS_RX_DFE_H1 0x1d5c
43983 #define A_XGMAC_PORT_HSS_RX_DFE_H2 0x1d60
43984 #define A_XGMAC_PORT_HSS_RX_DFE_H3 0x1d64
43985 #define A_XGMAC_PORT_HSS_RX_DFE_H4 0x1d68
43986 #define A_XGMAC_PORT_HSS_RX_DFE_H5 0x1d6c
43987 #define A_XGMAC_PORT_HSS_RX_DAC_DPC 0x1d70
43988 #define A_XGMAC_PORT_HSS_RX_DDC 0x1d74
43989 #define A_XGMAC_PORT_HSS_RX_INTERNAL_STATUS 0x1d78
43990 #define A_XGMAC_PORT_HSS_RX_DFE_FUNC_CTRL 0x1d7c
43991 #define A_XGMAC_PORT_HSS_TXRX_CFG_MODE 0x1e00
43992 #define A_XGMAC_PORT_HSS_TXRXTEST_CTRL 0x1e04
43993 
43994 /* registers for module UP */
43995 #define UP_BASE_ADDR 0x0
43996 
43997 #define A_UP_IBQ_CONFIG 0x0
43998 
43999 #define S_IBQGEN2    2
44000 #define M_IBQGEN2    0x3fffffffU
44001 #define V_IBQGEN2(x) ((x) << S_IBQGEN2)
44002 #define G_IBQGEN2(x) (((x) >> S_IBQGEN2) & M_IBQGEN2)
44003 
44004 #define S_IBQBUSY    1
44005 #define V_IBQBUSY(x) ((x) << S_IBQBUSY)
44006 #define F_IBQBUSY    V_IBQBUSY(1U)
44007 
44008 #define S_IBQEN    0
44009 #define V_IBQEN(x) ((x) << S_IBQEN)
44010 #define F_IBQEN    V_IBQEN(1U)
44011 
44012 #define A_UP_OBQ_CONFIG 0x4
44013 
44014 #define S_OBQGEN2    2
44015 #define M_OBQGEN2    0x3fffffffU
44016 #define V_OBQGEN2(x) ((x) << S_OBQGEN2)
44017 #define G_OBQGEN2(x) (((x) >> S_OBQGEN2) & M_OBQGEN2)
44018 
44019 #define S_OBQBUSY    1
44020 #define V_OBQBUSY(x) ((x) << S_OBQBUSY)
44021 #define F_OBQBUSY    V_OBQBUSY(1U)
44022 
44023 #define S_OBQEN    0
44024 #define V_OBQEN(x) ((x) << S_OBQEN)
44025 #define F_OBQEN    V_OBQEN(1U)
44026 
44027 #define A_UP_IBQ_GEN 0x8
44028 
44029 #define S_IBQGEN0    22
44030 #define M_IBQGEN0    0x3ffU
44031 #define V_IBQGEN0(x) ((x) << S_IBQGEN0)
44032 #define G_IBQGEN0(x) (((x) >> S_IBQGEN0) & M_IBQGEN0)
44033 
44034 #define S_IBQTSCHCHNLRDY    18
44035 #define M_IBQTSCHCHNLRDY    0xfU
44036 #define V_IBQTSCHCHNLRDY(x) ((x) << S_IBQTSCHCHNLRDY)
44037 #define G_IBQTSCHCHNLRDY(x) (((x) >> S_IBQTSCHCHNLRDY) & M_IBQTSCHCHNLRDY)
44038 
44039 #define S_IBQMBVFSTATUS    17
44040 #define V_IBQMBVFSTATUS(x) ((x) << S_IBQMBVFSTATUS)
44041 #define F_IBQMBVFSTATUS    V_IBQMBVFSTATUS(1U)
44042 
44043 #define S_IBQMBSTATUS    16
44044 #define V_IBQMBSTATUS(x) ((x) << S_IBQMBSTATUS)
44045 #define F_IBQMBSTATUS    V_IBQMBSTATUS(1U)
44046 
44047 #define S_IBQGEN1    6
44048 #define M_IBQGEN1    0x3ffU
44049 #define V_IBQGEN1(x) ((x) << S_IBQGEN1)
44050 #define G_IBQGEN1(x) (((x) >> S_IBQGEN1) & M_IBQGEN1)
44051 
44052 #define S_IBQEMPTY    0
44053 #define M_IBQEMPTY    0x3fU
44054 #define V_IBQEMPTY(x) ((x) << S_IBQEMPTY)
44055 #define G_IBQEMPTY(x) (((x) >> S_IBQEMPTY) & M_IBQEMPTY)
44056 
44057 #define A_UP_OBQ_GEN 0xc
44058 
44059 #define S_OBQGEN    6
44060 #define M_OBQGEN    0x3ffffffU
44061 #define V_OBQGEN(x) ((x) << S_OBQGEN)
44062 #define G_OBQGEN(x) (((x) >> S_OBQGEN) & M_OBQGEN)
44063 
44064 #define S_OBQFULL    0
44065 #define M_OBQFULL    0x3fU
44066 #define V_OBQFULL(x) ((x) << S_OBQFULL)
44067 #define G_OBQFULL(x) (((x) >> S_OBQFULL) & M_OBQFULL)
44068 
44069 #define S_T5_OBQGEN    8
44070 #define M_T5_OBQGEN    0xffffffU
44071 #define V_T5_OBQGEN(x) ((x) << S_T5_OBQGEN)
44072 #define G_T5_OBQGEN(x) (((x) >> S_T5_OBQGEN) & M_T5_OBQGEN)
44073 
44074 #define S_T5_OBQFULL    0
44075 #define M_T5_OBQFULL    0xffU
44076 #define V_T5_OBQFULL(x) ((x) << S_T5_OBQFULL)
44077 #define G_T5_OBQFULL(x) (((x) >> S_T5_OBQFULL) & M_T5_OBQFULL)
44078 
44079 #define A_UP_IBQ_0_RDADDR 0x10
44080 
44081 #define S_QUEID    13
44082 #define M_QUEID    0x7ffffU
44083 #define V_QUEID(x) ((x) << S_QUEID)
44084 #define G_QUEID(x) (((x) >> S_QUEID) & M_QUEID)
44085 
44086 #define S_IBQRDADDR    0
44087 #define M_IBQRDADDR    0x1fffU
44088 #define V_IBQRDADDR(x) ((x) << S_IBQRDADDR)
44089 #define G_IBQRDADDR(x) (((x) >> S_IBQRDADDR) & M_IBQRDADDR)
44090 
44091 #define A_UP_IBQ_0_WRADDR 0x14
44092 
44093 #define S_IBQWRADDR    0
44094 #define M_IBQWRADDR    0x1fffU
44095 #define V_IBQWRADDR(x) ((x) << S_IBQWRADDR)
44096 #define G_IBQWRADDR(x) (((x) >> S_IBQWRADDR) & M_IBQWRADDR)
44097 
44098 #define A_UP_IBQ_0_STATUS 0x18
44099 
44100 #define S_QUEERRFRAME    31
44101 #define V_QUEERRFRAME(x) ((x) << S_QUEERRFRAME)
44102 #define F_QUEERRFRAME    V_QUEERRFRAME(1U)
44103 
44104 #define S_QUEREMFLITS    0
44105 #define M_QUEREMFLITS    0x7ffU
44106 #define V_QUEREMFLITS(x) ((x) << S_QUEREMFLITS)
44107 #define G_QUEREMFLITS(x) (((x) >> S_QUEREMFLITS) & M_QUEREMFLITS)
44108 
44109 #define A_UP_IBQ_0_PKTCNT 0x1c
44110 
44111 #define S_QUEEOPCNT    16
44112 #define M_QUEEOPCNT    0xfffU
44113 #define V_QUEEOPCNT(x) ((x) << S_QUEEOPCNT)
44114 #define G_QUEEOPCNT(x) (((x) >> S_QUEEOPCNT) & M_QUEEOPCNT)
44115 
44116 #define S_QUESOPCNT    0
44117 #define M_QUESOPCNT    0xfffU
44118 #define V_QUESOPCNT(x) ((x) << S_QUESOPCNT)
44119 #define G_QUESOPCNT(x) (((x) >> S_QUESOPCNT) & M_QUESOPCNT)
44120 
44121 #define A_UP_IBQ_1_RDADDR 0x20
44122 #define A_UP_IBQ_1_WRADDR 0x24
44123 #define A_UP_IBQ_1_STATUS 0x28
44124 #define A_UP_IBQ_1_PKTCNT 0x2c
44125 #define A_UP_IBQ_2_RDADDR 0x30
44126 #define A_UP_IBQ_2_WRADDR 0x34
44127 #define A_UP_IBQ_2_STATUS 0x38
44128 #define A_UP_IBQ_2_PKTCNT 0x3c
44129 #define A_UP_IBQ_3_RDADDR 0x40
44130 #define A_UP_IBQ_3_WRADDR 0x44
44131 #define A_UP_IBQ_3_STATUS 0x48
44132 #define A_UP_IBQ_3_PKTCNT 0x4c
44133 #define A_UP_IBQ_4_RDADDR 0x50
44134 #define A_UP_IBQ_4_WRADDR 0x54
44135 #define A_UP_IBQ_4_STATUS 0x58
44136 #define A_UP_IBQ_4_PKTCNT 0x5c
44137 #define A_UP_IBQ_5_RDADDR 0x60
44138 #define A_UP_IBQ_5_WRADDR 0x64
44139 #define A_UP_IBQ_5_STATUS 0x68
44140 #define A_UP_IBQ_5_PKTCNT 0x6c
44141 #define A_UP_OBQ_0_RDADDR 0x70
44142 
44143 #define S_OBQID    15
44144 #define M_OBQID    0x1ffffU
44145 #define V_OBQID(x) ((x) << S_OBQID)
44146 #define G_OBQID(x) (((x) >> S_OBQID) & M_OBQID)
44147 
44148 #define S_QUERDADDR    0
44149 #define M_QUERDADDR    0x7fffU
44150 #define V_QUERDADDR(x) ((x) << S_QUERDADDR)
44151 #define G_QUERDADDR(x) (((x) >> S_QUERDADDR) & M_QUERDADDR)
44152 
44153 #define A_UP_OBQ_0_WRADDR 0x74
44154 
44155 #define S_QUEWRADDR    0
44156 #define M_QUEWRADDR    0x7fffU
44157 #define V_QUEWRADDR(x) ((x) << S_QUEWRADDR)
44158 #define G_QUEWRADDR(x) (((x) >> S_QUEWRADDR) & M_QUEWRADDR)
44159 
44160 #define A_UP_OBQ_0_STATUS 0x78
44161 #define A_UP_OBQ_0_PKTCNT 0x7c
44162 #define A_UP_OBQ_1_RDADDR 0x80
44163 #define A_UP_OBQ_1_WRADDR 0x84
44164 #define A_UP_OBQ_1_STATUS 0x88
44165 #define A_UP_OBQ_1_PKTCNT 0x8c
44166 #define A_UP_OBQ_2_RDADDR 0x90
44167 #define A_UP_OBQ_2_WRADDR 0x94
44168 #define A_UP_OBQ_2_STATUS 0x98
44169 #define A_UP_OBQ_2_PKTCNT 0x9c
44170 #define A_UP_OBQ_3_RDADDR 0xa0
44171 #define A_UP_OBQ_3_WRADDR 0xa4
44172 #define A_UP_OBQ_3_STATUS 0xa8
44173 #define A_UP_OBQ_3_PKTCNT 0xac
44174 #define A_UP_OBQ_4_RDADDR 0xb0
44175 #define A_UP_OBQ_4_WRADDR 0xb4
44176 #define A_UP_OBQ_4_STATUS 0xb8
44177 #define A_UP_OBQ_4_PKTCNT 0xbc
44178 #define A_UP_OBQ_5_RDADDR 0xc0
44179 #define A_UP_OBQ_5_WRADDR 0xc4
44180 #define A_UP_OBQ_5_STATUS 0xc8
44181 #define A_UP_OBQ_5_PKTCNT 0xcc
44182 #define A_UP_IBQ_0_CONFIG 0xd0
44183 
44184 #define S_QUESIZE    26
44185 #define M_QUESIZE    0x3fU
44186 #define V_QUESIZE(x) ((x) << S_QUESIZE)
44187 #define G_QUESIZE(x) (((x) >> S_QUESIZE) & M_QUESIZE)
44188 
44189 #define S_QUEBASE    8
44190 #define M_QUEBASE    0x3fU
44191 #define V_QUEBASE(x) ((x) << S_QUEBASE)
44192 #define G_QUEBASE(x) (((x) >> S_QUEBASE) & M_QUEBASE)
44193 
44194 #define S_QUEDBG8BEN    7
44195 #define V_QUEDBG8BEN(x) ((x) << S_QUEDBG8BEN)
44196 #define F_QUEDBG8BEN    V_QUEDBG8BEN(1U)
44197 
44198 #define S_QUEBAREADDR    0
44199 #define V_QUEBAREADDR(x) ((x) << S_QUEBAREADDR)
44200 #define F_QUEBAREADDR    V_QUEBAREADDR(1U)
44201 
44202 #define S_QUE1KEN    6
44203 #define V_QUE1KEN(x) ((x) << S_QUE1KEN)
44204 #define F_QUE1KEN    V_QUE1KEN(1U)
44205 
44206 #define A_UP_IBQ_0_REALADDR 0xd4
44207 
44208 #define S_QUERDADDRWRAP    31
44209 #define V_QUERDADDRWRAP(x) ((x) << S_QUERDADDRWRAP)
44210 #define F_QUERDADDRWRAP    V_QUERDADDRWRAP(1U)
44211 
44212 #define S_QUEWRADDRWRAP    30
44213 #define V_QUEWRADDRWRAP(x) ((x) << S_QUEWRADDRWRAP)
44214 #define F_QUEWRADDRWRAP    V_QUEWRADDRWRAP(1U)
44215 
44216 #define S_QUEMEMADDR    3
44217 #define M_QUEMEMADDR    0x7ffU
44218 #define V_QUEMEMADDR(x) ((x) << S_QUEMEMADDR)
44219 #define G_QUEMEMADDR(x) (((x) >> S_QUEMEMADDR) & M_QUEMEMADDR)
44220 
44221 #define A_UP_IBQ_1_CONFIG 0xd8
44222 #define A_UP_IBQ_1_REALADDR 0xdc
44223 #define A_UP_IBQ_2_CONFIG 0xe0
44224 #define A_UP_IBQ_2_REALADDR 0xe4
44225 #define A_UP_IBQ_3_CONFIG 0xe8
44226 #define A_UP_IBQ_3_REALADDR 0xec
44227 #define A_UP_IBQ_4_CONFIG 0xf0
44228 #define A_UP_IBQ_4_REALADDR 0xf4
44229 #define A_UP_IBQ_5_CONFIG 0xf8
44230 #define A_UP_IBQ_5_REALADDR 0xfc
44231 #define A_UP_OBQ_0_CONFIG 0x100
44232 #define A_UP_OBQ_0_REALADDR 0x104
44233 #define A_UP_OBQ_1_CONFIG 0x108
44234 #define A_UP_OBQ_1_REALADDR 0x10c
44235 #define A_UP_OBQ_2_CONFIG 0x110
44236 #define A_UP_OBQ_2_REALADDR 0x114
44237 #define A_UP_OBQ_3_CONFIG 0x118
44238 #define A_UP_OBQ_3_REALADDR 0x11c
44239 #define A_UP_OBQ_4_CONFIG 0x120
44240 #define A_UP_OBQ_4_REALADDR 0x124
44241 #define A_UP_OBQ_5_CONFIG 0x128
44242 #define A_UP_OBQ_5_REALADDR 0x12c
44243 #define A_UP_MAILBOX_STATUS 0x130
44244 
44245 #define S_MBGEN0    20
44246 #define M_MBGEN0    0xfffU
44247 #define V_MBGEN0(x) ((x) << S_MBGEN0)
44248 #define G_MBGEN0(x) (((x) >> S_MBGEN0) & M_MBGEN0)
44249 
44250 #define S_GENTIMERTRIGGER    16
44251 #define M_GENTIMERTRIGGER    0xfU
44252 #define V_GENTIMERTRIGGER(x) ((x) << S_GENTIMERTRIGGER)
44253 #define G_GENTIMERTRIGGER(x) (((x) >> S_GENTIMERTRIGGER) & M_GENTIMERTRIGGER)
44254 
44255 #define S_MBGEN1    8
44256 #define M_MBGEN1    0xffU
44257 #define V_MBGEN1(x) ((x) << S_MBGEN1)
44258 #define G_MBGEN1(x) (((x) >> S_MBGEN1) & M_MBGEN1)
44259 
44260 #define S_MBPFINT    0
44261 #define M_MBPFINT    0xffU
44262 #define V_MBPFINT(x) ((x) << S_MBPFINT)
44263 #define G_MBPFINT(x) (((x) >> S_MBPFINT) & M_MBPFINT)
44264 
44265 #define A_UP_UP_DBG_LA_CFG 0x140
44266 
44267 #define S_UPDBGLACAPTBUB    31
44268 #define V_UPDBGLACAPTBUB(x) ((x) << S_UPDBGLACAPTBUB)
44269 #define F_UPDBGLACAPTBUB    V_UPDBGLACAPTBUB(1U)
44270 
44271 #define S_UPDBGLACAPTPCONLY    30
44272 #define V_UPDBGLACAPTPCONLY(x) ((x) << S_UPDBGLACAPTPCONLY)
44273 #define F_UPDBGLACAPTPCONLY    V_UPDBGLACAPTPCONLY(1U)
44274 
44275 #define S_UPDBGLAMASKSTOP    29
44276 #define V_UPDBGLAMASKSTOP(x) ((x) << S_UPDBGLAMASKSTOP)
44277 #define F_UPDBGLAMASKSTOP    V_UPDBGLAMASKSTOP(1U)
44278 
44279 #define S_UPDBGLAMASKTRIG    28
44280 #define V_UPDBGLAMASKTRIG(x) ((x) << S_UPDBGLAMASKTRIG)
44281 #define F_UPDBGLAMASKTRIG    V_UPDBGLAMASKTRIG(1U)
44282 
44283 #define S_UPDBGLAWRPTR    16
44284 #define M_UPDBGLAWRPTR    0xfffU
44285 #define V_UPDBGLAWRPTR(x) ((x) << S_UPDBGLAWRPTR)
44286 #define G_UPDBGLAWRPTR(x) (((x) >> S_UPDBGLAWRPTR) & M_UPDBGLAWRPTR)
44287 
44288 #define S_UPDBGLARDPTR    2
44289 #define M_UPDBGLARDPTR    0xfffU
44290 #define V_UPDBGLARDPTR(x) ((x) << S_UPDBGLARDPTR)
44291 #define G_UPDBGLARDPTR(x) (((x) >> S_UPDBGLARDPTR) & M_UPDBGLARDPTR)
44292 
44293 #define S_UPDBGLARDEN    1
44294 #define V_UPDBGLARDEN(x) ((x) << S_UPDBGLARDEN)
44295 #define F_UPDBGLARDEN    V_UPDBGLARDEN(1U)
44296 
44297 #define S_UPDBGLAEN    0
44298 #define V_UPDBGLAEN(x) ((x) << S_UPDBGLAEN)
44299 #define F_UPDBGLAEN    V_UPDBGLAEN(1U)
44300 
44301 #define S_UPDBGLABUSY    14
44302 #define V_UPDBGLABUSY(x) ((x) << S_UPDBGLABUSY)
44303 #define F_UPDBGLABUSY    V_UPDBGLABUSY(1U)
44304 
44305 #define A_UP_UP_DBG_LA_DATA 0x144
44306 #define A_UP_PIO_MST_CONFIG 0x148
44307 
44308 #define S_FLSRC    24
44309 #define M_FLSRC    0x7U
44310 #define V_FLSRC(x) ((x) << S_FLSRC)
44311 #define G_FLSRC(x) (((x) >> S_FLSRC) & M_FLSRC)
44312 
44313 #define S_SEPROT    23
44314 #define V_SEPROT(x) ((x) << S_SEPROT)
44315 #define F_SEPROT    V_SEPROT(1U)
44316 
44317 #define S_SESRC    20
44318 #define M_SESRC    0x7U
44319 #define V_SESRC(x) ((x) << S_SESRC)
44320 #define G_SESRC(x) (((x) >> S_SESRC) & M_SESRC)
44321 
44322 #define S_UPRGN    19
44323 #define V_UPRGN(x) ((x) << S_UPRGN)
44324 #define F_UPRGN    V_UPRGN(1U)
44325 
44326 #define S_UPPF    16
44327 #define M_UPPF    0x7U
44328 #define V_UPPF(x) ((x) << S_UPPF)
44329 #define G_UPPF(x) (((x) >> S_UPPF) & M_UPPF)
44330 
44331 #define S_UPRID    0
44332 #define M_UPRID    0xffffU
44333 #define V_UPRID(x) ((x) << S_UPRID)
44334 #define G_UPRID(x) (((x) >> S_UPRID) & M_UPRID)
44335 
44336 #define S_REQVFVLD    27
44337 #define V_REQVFVLD(x) ((x) << S_REQVFVLD)
44338 #define F_REQVFVLD    V_REQVFVLD(1U)
44339 
44340 #define S_T5_UPRID    0
44341 #define M_T5_UPRID    0xffU
44342 #define V_T5_UPRID(x) ((x) << S_T5_UPRID)
44343 #define G_T5_UPRID(x) (((x) >> S_T5_UPRID) & M_T5_UPRID)
44344 
44345 #define S_T6_UPRID    0
44346 #define M_T6_UPRID    0x1ffU
44347 #define V_T6_UPRID(x) ((x) << S_T6_UPRID)
44348 #define G_T6_UPRID(x) (((x) >> S_T6_UPRID) & M_T6_UPRID)
44349 
44350 #define A_UP_UP_SELF_CONTROL 0x14c
44351 
44352 #define S_UPSELFRESET    0
44353 #define V_UPSELFRESET(x) ((x) << S_UPSELFRESET)
44354 #define F_UPSELFRESET    V_UPSELFRESET(1U)
44355 
44356 #define A_UP_MAILBOX_PF0_CTL 0x180
44357 #define A_UP_MAILBOX_PF1_CTL 0x190
44358 #define A_UP_MAILBOX_PF2_CTL 0x1a0
44359 #define A_UP_MAILBOX_PF3_CTL 0x1b0
44360 #define A_UP_MAILBOX_PF4_CTL 0x1c0
44361 #define A_UP_MAILBOX_PF5_CTL 0x1d0
44362 #define A_UP_MAILBOX_PF6_CTL 0x1e0
44363 #define A_UP_MAILBOX_PF7_CTL 0x1f0
44364 #define A_UP_TSCH_CHNLN_CLASS_RDY 0x200
44365 
44366 #define S_ECO_15444_SGE_DB_BUSY    31
44367 #define V_ECO_15444_SGE_DB_BUSY(x) ((x) << S_ECO_15444_SGE_DB_BUSY)
44368 #define F_ECO_15444_SGE_DB_BUSY    V_ECO_15444_SGE_DB_BUSY(1U)
44369 
44370 #define S_ECO_15444_PL_INTF_BUSY    30
44371 #define V_ECO_15444_PL_INTF_BUSY(x) ((x) << S_ECO_15444_PL_INTF_BUSY)
44372 #define F_ECO_15444_PL_INTF_BUSY    V_ECO_15444_PL_INTF_BUSY(1U)
44373 
44374 #define S_TSCHCHNLCRDY    0
44375 #define M_TSCHCHNLCRDY    0x3fffffffU
44376 #define V_TSCHCHNLCRDY(x) ((x) << S_TSCHCHNLCRDY)
44377 #define G_TSCHCHNLCRDY(x) (((x) >> S_TSCHCHNLCRDY) & M_TSCHCHNLCRDY)
44378 
44379 #define A_UP_TSCH_CHNLN_CLASS_WATCH_RDY 0x204
44380 
44381 #define S_TSCHWRRLIMIT    16
44382 #define M_TSCHWRRLIMIT    0xffffU
44383 #define V_TSCHWRRLIMIT(x) ((x) << S_TSCHWRRLIMIT)
44384 #define G_TSCHWRRLIMIT(x) (((x) >> S_TSCHWRRLIMIT) & M_TSCHWRRLIMIT)
44385 
44386 #define S_TSCHCHNLCWRDY    0
44387 #define M_TSCHCHNLCWRDY    0xffffU
44388 #define V_TSCHCHNLCWRDY(x) ((x) << S_TSCHCHNLCWRDY)
44389 #define G_TSCHCHNLCWRDY(x) (((x) >> S_TSCHCHNLCWRDY) & M_TSCHCHNLCWRDY)
44390 
44391 #define A_UP_TSCH_CHNLN_CLASS_WATCH_LIST 0x208
44392 
44393 #define S_TSCHWRRRELOAD    16
44394 #define M_TSCHWRRRELOAD    0xffffU
44395 #define V_TSCHWRRRELOAD(x) ((x) << S_TSCHWRRRELOAD)
44396 #define G_TSCHWRRRELOAD(x) (((x) >> S_TSCHWRRRELOAD) & M_TSCHWRRRELOAD)
44397 
44398 #define S_TSCHCHNLCWATCH    0
44399 #define M_TSCHCHNLCWATCH    0xffffU
44400 #define V_TSCHCHNLCWATCH(x) ((x) << S_TSCHCHNLCWATCH)
44401 #define G_TSCHCHNLCWATCH(x) (((x) >> S_TSCHCHNLCWATCH) & M_TSCHCHNLCWATCH)
44402 
44403 #define A_UP_TSCH_CHNLN_CLASS_TAKE 0x20c
44404 
44405 #define S_TSCHCHNLCNUM    24
44406 #define M_TSCHCHNLCNUM    0x1fU
44407 #define V_TSCHCHNLCNUM(x) ((x) << S_TSCHCHNLCNUM)
44408 #define G_TSCHCHNLCNUM(x) (((x) >> S_TSCHCHNLCNUM) & M_TSCHCHNLCNUM)
44409 
44410 #define S_TSCHCHNLCCNT    0
44411 #define M_TSCHCHNLCCNT    0xffffffU
44412 #define V_TSCHCHNLCCNT(x) ((x) << S_TSCHCHNLCCNT)
44413 #define G_TSCHCHNLCCNT(x) (((x) >> S_TSCHCHNLCCNT) & M_TSCHCHNLCCNT)
44414 
44415 #define S_TSCHCHNLCHDIS    31
44416 #define V_TSCHCHNLCHDIS(x) ((x) << S_TSCHCHNLCHDIS)
44417 #define F_TSCHCHNLCHDIS    V_TSCHCHNLCHDIS(1U)
44418 
44419 #define S_TSCHCHNLWDIS    30
44420 #define V_TSCHCHNLWDIS(x) ((x) << S_TSCHCHNLWDIS)
44421 #define F_TSCHCHNLWDIS    V_TSCHCHNLWDIS(1U)
44422 
44423 #define S_TSCHCHNLCLDIS    29
44424 #define V_TSCHCHNLCLDIS(x) ((x) << S_TSCHCHNLCLDIS)
44425 #define F_TSCHCHNLCLDIS    V_TSCHCHNLCLDIS(1U)
44426 
44427 #define A_UP_UPLADBGPCCHKDATA_0 0x240
44428 #define A_UP_UPLADBGPCCHKMASK_0 0x244
44429 #define A_UP_UPLADBGPCCHKDATA_1 0x250
44430 #define A_UP_UPLADBGPCCHKMASK_1 0x254
44431 #define A_UP_UPLADBGPCCHKDATA_2 0x260
44432 #define A_UP_UPLADBGPCCHKMASK_2 0x264
44433 #define A_UP_UPLADBGPCCHKDATA_3 0x270
44434 #define A_UP_UPLADBGPCCHKMASK_3 0x274
44435 #define A_UP_IBQ_0_SHADOW_RDADDR 0x280
44436 #define A_UP_IBQ_0_SHADOW_WRADDR 0x284
44437 #define A_UP_IBQ_0_SHADOW_STATUS 0x288
44438 #define A_UP_IBQ_0_SHADOW_PKTCNT 0x28c
44439 #define A_UP_IBQ_1_SHADOW_RDADDR 0x290
44440 #define A_UP_IBQ_1_SHADOW_WRADDR 0x294
44441 #define A_UP_IBQ_1_SHADOW_STATUS 0x298
44442 #define A_UP_IBQ_1_SHADOW_PKTCNT 0x29c
44443 #define A_UP_IBQ_2_SHADOW_RDADDR 0x2a0
44444 #define A_UP_IBQ_2_SHADOW_WRADDR 0x2a4
44445 #define A_UP_IBQ_2_SHADOW_STATUS 0x2a8
44446 #define A_UP_IBQ_2_SHADOW_PKTCNT 0x2ac
44447 #define A_UP_IBQ_3_SHADOW_RDADDR 0x2b0
44448 #define A_UP_IBQ_3_SHADOW_WRADDR 0x2b4
44449 #define A_UP_IBQ_3_SHADOW_STATUS 0x2b8
44450 #define A_UP_IBQ_3_SHADOW_PKTCNT 0x2bc
44451 #define A_UP_IBQ_4_SHADOW_RDADDR 0x2c0
44452 #define A_UP_IBQ_4_SHADOW_WRADDR 0x2c4
44453 #define A_UP_IBQ_4_SHADOW_STATUS 0x2c8
44454 #define A_UP_IBQ_4_SHADOW_PKTCNT 0x2cc
44455 #define A_UP_IBQ_5_SHADOW_RDADDR 0x2d0
44456 #define A_UP_IBQ_5_SHADOW_WRADDR 0x2d4
44457 #define A_UP_IBQ_5_SHADOW_STATUS 0x2d8
44458 #define A_UP_IBQ_5_SHADOW_PKTCNT 0x2dc
44459 #define A_UP_OBQ_0_SHADOW_RDADDR 0x2e0
44460 #define A_UP_OBQ_0_SHADOW_WRADDR 0x2e4
44461 #define A_UP_OBQ_0_SHADOW_STATUS 0x2e8
44462 #define A_UP_OBQ_0_SHADOW_PKTCNT 0x2ec
44463 #define A_UP_OBQ_1_SHADOW_RDADDR 0x2f0
44464 #define A_UP_OBQ_1_SHADOW_WRADDR 0x2f4
44465 #define A_UP_OBQ_1_SHADOW_STATUS 0x2f8
44466 #define A_UP_OBQ_1_SHADOW_PKTCNT 0x2fc
44467 #define A_UP_OBQ_2_SHADOW_RDADDR 0x300
44468 #define A_UP_OBQ_2_SHADOW_WRADDR 0x304
44469 #define A_UP_OBQ_2_SHADOW_STATUS 0x308
44470 #define A_UP_OBQ_2_SHADOW_PKTCNT 0x30c
44471 #define A_UP_OBQ_3_SHADOW_RDADDR 0x310
44472 #define A_UP_OBQ_3_SHADOW_WRADDR 0x314
44473 #define A_UP_OBQ_3_SHADOW_STATUS 0x318
44474 #define A_UP_OBQ_3_SHADOW_PKTCNT 0x31c
44475 #define A_UP_OBQ_4_SHADOW_RDADDR 0x320
44476 #define A_UP_OBQ_4_SHADOW_WRADDR 0x324
44477 #define A_UP_OBQ_4_SHADOW_STATUS 0x328
44478 #define A_UP_OBQ_4_SHADOW_PKTCNT 0x32c
44479 #define A_UP_OBQ_5_SHADOW_RDADDR 0x330
44480 #define A_UP_OBQ_5_SHADOW_WRADDR 0x334
44481 #define A_UP_OBQ_5_SHADOW_STATUS 0x338
44482 #define A_UP_OBQ_5_SHADOW_PKTCNT 0x33c
44483 #define A_UP_OBQ_6_SHADOW_RDADDR 0x340
44484 #define A_UP_OBQ_6_SHADOW_WRADDR 0x344
44485 #define A_UP_OBQ_6_SHADOW_STATUS 0x348
44486 #define A_UP_OBQ_6_SHADOW_PKTCNT 0x34c
44487 #define A_UP_OBQ_7_SHADOW_RDADDR 0x350
44488 #define A_UP_OBQ_7_SHADOW_WRADDR 0x354
44489 #define A_UP_OBQ_7_SHADOW_STATUS 0x358
44490 #define A_UP_OBQ_7_SHADOW_PKTCNT 0x35c
44491 #define A_UP_IBQ_0_SHADOW_CONFIG 0x360
44492 #define A_UP_IBQ_0_SHADOW_REALADDR 0x364
44493 #define A_UP_IBQ_1_SHADOW_CONFIG 0x368
44494 #define A_UP_IBQ_1_SHADOW_REALADDR 0x36c
44495 #define A_UP_IBQ_2_SHADOW_CONFIG 0x370
44496 #define A_UP_IBQ_2_SHADOW_REALADDR 0x374
44497 #define A_UP_IBQ_3_SHADOW_CONFIG 0x378
44498 #define A_UP_IBQ_3_SHADOW_REALADDR 0x37c
44499 #define A_UP_IBQ_4_SHADOW_CONFIG 0x380
44500 #define A_UP_IBQ_4_SHADOW_REALADDR 0x384
44501 #define A_UP_IBQ_5_SHADOW_CONFIG 0x388
44502 #define A_UP_IBQ_5_SHADOW_REALADDR 0x38c
44503 #define A_UP_OBQ_0_SHADOW_CONFIG 0x390
44504 #define A_UP_OBQ_0_SHADOW_REALADDR 0x394
44505 #define A_UP_OBQ_1_SHADOW_CONFIG 0x398
44506 #define A_UP_OBQ_1_SHADOW_REALADDR 0x39c
44507 #define A_UP_OBQ_2_SHADOW_CONFIG 0x3a0
44508 #define A_UP_OBQ_2_SHADOW_REALADDR 0x3a4
44509 #define A_UP_OBQ_3_SHADOW_CONFIG 0x3a8
44510 #define A_UP_OBQ_3_SHADOW_REALADDR 0x3ac
44511 #define A_UP_OBQ_4_SHADOW_CONFIG 0x3b0
44512 #define A_UP_OBQ_4_SHADOW_REALADDR 0x3b4
44513 #define A_UP_OBQ_5_SHADOW_CONFIG 0x3b8
44514 #define A_UP_OBQ_5_SHADOW_REALADDR 0x3bc
44515 #define A_UP_OBQ_6_SHADOW_CONFIG 0x3c0
44516 #define A_UP_OBQ_6_SHADOW_REALADDR 0x3c4
44517 #define A_UP_OBQ_7_SHADOW_CONFIG 0x3c8
44518 #define A_UP_OBQ_7_SHADOW_REALADDR 0x3cc
44519 
44520 /* registers for module CIM_CTL */
44521 #define CIM_CTL_BASE_ADDR 0x0
44522 
44523 #define A_CIM_CTL_CONFIG 0x0
44524 
44525 #define S_AUTOPREFLOC    17
44526 #define M_AUTOPREFLOC    0x1fU
44527 #define V_AUTOPREFLOC(x) ((x) << S_AUTOPREFLOC)
44528 #define G_AUTOPREFLOC(x) (((x) >> S_AUTOPREFLOC) & M_AUTOPREFLOC)
44529 
44530 #define S_AUTOPREFEN    16
44531 #define V_AUTOPREFEN(x) ((x) << S_AUTOPREFEN)
44532 #define F_AUTOPREFEN    V_AUTOPREFEN(1U)
44533 
44534 #define S_DISMATIMEOUT    15
44535 #define V_DISMATIMEOUT(x) ((x) << S_DISMATIMEOUT)
44536 #define F_DISMATIMEOUT    V_DISMATIMEOUT(1U)
44537 
44538 #define S_PIFMULTICMD    8
44539 #define V_PIFMULTICMD(x) ((x) << S_PIFMULTICMD)
44540 #define F_PIFMULTICMD    V_PIFMULTICMD(1U)
44541 
44542 #define S_UPSELFRESETTOUT    7
44543 #define V_UPSELFRESETTOUT(x) ((x) << S_UPSELFRESETTOUT)
44544 #define F_UPSELFRESETTOUT    V_UPSELFRESETTOUT(1U)
44545 
44546 #define S_PLSWAPDISWR    6
44547 #define V_PLSWAPDISWR(x) ((x) << S_PLSWAPDISWR)
44548 #define F_PLSWAPDISWR    V_PLSWAPDISWR(1U)
44549 
44550 #define S_PLSWAPDISRD    5
44551 #define V_PLSWAPDISRD(x) ((x) << S_PLSWAPDISRD)
44552 #define F_PLSWAPDISRD    V_PLSWAPDISRD(1U)
44553 
44554 #define S_PREFEN    0
44555 #define V_PREFEN(x) ((x) << S_PREFEN)
44556 #define F_PREFEN    V_PREFEN(1U)
44557 
44558 #define S_DISSLOWTIMEOUT    14
44559 #define V_DISSLOWTIMEOUT(x) ((x) << S_DISSLOWTIMEOUT)
44560 #define F_DISSLOWTIMEOUT    V_DISSLOWTIMEOUT(1U)
44561 
44562 #define S_INTLRSPEN    9
44563 #define V_INTLRSPEN(x) ((x) << S_INTLRSPEN)
44564 #define F_INTLRSPEN    V_INTLRSPEN(1U)
44565 
44566 #define A_CIM_CTL_PREFADDR 0x4
44567 #define A_CIM_CTL_ALLOCADDR 0x8
44568 #define A_CIM_CTL_INVLDTADDR 0xc
44569 #define A_CIM_CTL_STATIC_PREFADDR0 0x10
44570 #define A_CIM_CTL_STATIC_PREFADDR1 0x14
44571 #define A_CIM_CTL_STATIC_PREFADDR2 0x18
44572 #define A_CIM_CTL_STATIC_PREFADDR3 0x1c
44573 #define A_CIM_CTL_STATIC_PREFADDR4 0x20
44574 #define A_CIM_CTL_STATIC_PREFADDR5 0x24
44575 #define A_CIM_CTL_STATIC_PREFADDR6 0x28
44576 #define A_CIM_CTL_STATIC_PREFADDR7 0x2c
44577 #define A_CIM_CTL_STATIC_PREFADDR8 0x30
44578 #define A_CIM_CTL_STATIC_PREFADDR9 0x34
44579 #define A_CIM_CTL_STATIC_PREFADDR10 0x38
44580 #define A_CIM_CTL_STATIC_PREFADDR11 0x3c
44581 #define A_CIM_CTL_STATIC_PREFADDR12 0x40
44582 #define A_CIM_CTL_STATIC_PREFADDR13 0x44
44583 #define A_CIM_CTL_STATIC_PREFADDR14 0x48
44584 #define A_CIM_CTL_STATIC_PREFADDR15 0x4c
44585 #define A_CIM_CTL_STATIC_ALLOCADDR0 0x50
44586 #define A_CIM_CTL_STATIC_ALLOCADDR1 0x54
44587 #define A_CIM_CTL_STATIC_ALLOCADDR2 0x58
44588 #define A_CIM_CTL_STATIC_ALLOCADDR3 0x5c
44589 #define A_CIM_CTL_STATIC_ALLOCADDR4 0x60
44590 #define A_CIM_CTL_STATIC_ALLOCADDR5 0x64
44591 #define A_CIM_CTL_STATIC_ALLOCADDR6 0x68
44592 #define A_CIM_CTL_STATIC_ALLOCADDR7 0x6c
44593 #define A_CIM_CTL_STATIC_ALLOCADDR8 0x70
44594 #define A_CIM_CTL_STATIC_ALLOCADDR9 0x74
44595 #define A_CIM_CTL_STATIC_ALLOCADDR10 0x78
44596 #define A_CIM_CTL_STATIC_ALLOCADDR11 0x7c
44597 #define A_CIM_CTL_STATIC_ALLOCADDR12 0x80
44598 #define A_CIM_CTL_STATIC_ALLOCADDR13 0x84
44599 #define A_CIM_CTL_STATIC_ALLOCADDR14 0x88
44600 #define A_CIM_CTL_STATIC_ALLOCADDR15 0x8c
44601 #define A_CIM_CTL_FIFO_CNT 0x90
44602 
44603 #define S_CTLFIFOCNT    0
44604 #define M_CTLFIFOCNT    0xfU
44605 #define V_CTLFIFOCNT(x) ((x) << S_CTLFIFOCNT)
44606 #define G_CTLFIFOCNT(x) (((x) >> S_CTLFIFOCNT) & M_CTLFIFOCNT)
44607 
44608 #define A_CIM_CTL_GLB_TIMER 0x94
44609 #define A_CIM_CTL_TIMER0 0x98
44610 #define A_CIM_CTL_TIMER1 0x9c
44611 #define A_CIM_CTL_GEN0 0xa0
44612 #define A_CIM_CTL_GEN1 0xa4
44613 #define A_CIM_CTL_GEN2 0xa8
44614 #define A_CIM_CTL_GEN3 0xac
44615 #define A_CIM_CTL_GLB_TIMER_TICK 0xb0
44616 #define A_CIM_CTL_GEN_TIMER0_CTL 0xb4
44617 
44618 #define S_GENTIMERRUN    7
44619 #define V_GENTIMERRUN(x) ((x) << S_GENTIMERRUN)
44620 #define F_GENTIMERRUN    V_GENTIMERRUN(1U)
44621 
44622 #define S_GENTIMERTRIG    6
44623 #define V_GENTIMERTRIG(x) ((x) << S_GENTIMERTRIG)
44624 #define F_GENTIMERTRIG    V_GENTIMERTRIG(1U)
44625 
44626 #define S_GENTIMERACT    4
44627 #define M_GENTIMERACT    0x3U
44628 #define V_GENTIMERACT(x) ((x) << S_GENTIMERACT)
44629 #define G_GENTIMERACT(x) (((x) >> S_GENTIMERACT) & M_GENTIMERACT)
44630 
44631 #define S_GENTIMERCFG    2
44632 #define M_GENTIMERCFG    0x3U
44633 #define V_GENTIMERCFG(x) ((x) << S_GENTIMERCFG)
44634 #define G_GENTIMERCFG(x) (((x) >> S_GENTIMERCFG) & M_GENTIMERCFG)
44635 
44636 #define S_GENTIMERSTOP    1
44637 #define V_GENTIMERSTOP(x) ((x) << S_GENTIMERSTOP)
44638 #define F_GENTIMERSTOP    V_GENTIMERSTOP(1U)
44639 
44640 #define S_GENTIMERSTRT    0
44641 #define V_GENTIMERSTRT(x) ((x) << S_GENTIMERSTRT)
44642 #define F_GENTIMERSTRT    V_GENTIMERSTRT(1U)
44643 
44644 #define A_CIM_CTL_GEN_TIMER0 0xb8
44645 #define A_CIM_CTL_GEN_TIMER1_CTL 0xbc
44646 #define A_CIM_CTL_GEN_TIMER1 0xc0
44647 #define A_CIM_CTL_GEN_TIMER2_CTL 0xc4
44648 #define A_CIM_CTL_GEN_TIMER2 0xc8
44649 #define A_CIM_CTL_GEN_TIMER3_CTL 0xcc
44650 #define A_CIM_CTL_GEN_TIMER3 0xd0
44651 #define A_CIM_CTL_MAILBOX_VF_STATUS 0xe0
44652 #define A_CIM_CTL_MAILBOX_VFN_CTL 0x100
44653 #define A_CIM_CTL_TSCH_CHNLN_CTL 0x900
44654 
44655 #define S_TSCHNLEN    31
44656 #define V_TSCHNLEN(x) ((x) << S_TSCHNLEN)
44657 #define F_TSCHNLEN    V_TSCHNLEN(1U)
44658 
44659 #define S_TSCHNRESET    30
44660 #define V_TSCHNRESET(x) ((x) << S_TSCHNRESET)
44661 #define F_TSCHNRESET    V_TSCHNRESET(1U)
44662 
44663 #define S_T6_MIN_MAX_EN    29
44664 #define V_T6_MIN_MAX_EN(x) ((x) << S_T6_MIN_MAX_EN)
44665 #define F_T6_MIN_MAX_EN    V_T6_MIN_MAX_EN(1U)
44666 
44667 #define A_CIM_CTL_TSCH_CHNLN_TICK 0x904
44668 
44669 #define S_TSCHNLTICK    0
44670 #define M_TSCHNLTICK    0xffffU
44671 #define V_TSCHNLTICK(x) ((x) << S_TSCHNLTICK)
44672 #define G_TSCHNLTICK(x) (((x) >> S_TSCHNLTICK) & M_TSCHNLTICK)
44673 
44674 #define A_CIM_CTL_TSCH_CHNLN_CLASS_RATECTL 0x904
44675 
44676 #define S_TSC15RATECTL    15
44677 #define V_TSC15RATECTL(x) ((x) << S_TSC15RATECTL)
44678 #define F_TSC15RATECTL    V_TSC15RATECTL(1U)
44679 
44680 #define S_TSC14RATECTL    14
44681 #define V_TSC14RATECTL(x) ((x) << S_TSC14RATECTL)
44682 #define F_TSC14RATECTL    V_TSC14RATECTL(1U)
44683 
44684 #define S_TSC13RATECTL    13
44685 #define V_TSC13RATECTL(x) ((x) << S_TSC13RATECTL)
44686 #define F_TSC13RATECTL    V_TSC13RATECTL(1U)
44687 
44688 #define S_TSC12RATECTL    12
44689 #define V_TSC12RATECTL(x) ((x) << S_TSC12RATECTL)
44690 #define F_TSC12RATECTL    V_TSC12RATECTL(1U)
44691 
44692 #define S_TSC11RATECTL    11
44693 #define V_TSC11RATECTL(x) ((x) << S_TSC11RATECTL)
44694 #define F_TSC11RATECTL    V_TSC11RATECTL(1U)
44695 
44696 #define S_TSC10RATECTL    10
44697 #define V_TSC10RATECTL(x) ((x) << S_TSC10RATECTL)
44698 #define F_TSC10RATECTL    V_TSC10RATECTL(1U)
44699 
44700 #define S_TSC9RATECTL    9
44701 #define V_TSC9RATECTL(x) ((x) << S_TSC9RATECTL)
44702 #define F_TSC9RATECTL    V_TSC9RATECTL(1U)
44703 
44704 #define S_TSC8RATECTL    8
44705 #define V_TSC8RATECTL(x) ((x) << S_TSC8RATECTL)
44706 #define F_TSC8RATECTL    V_TSC8RATECTL(1U)
44707 
44708 #define S_TSC7RATECTL    7
44709 #define V_TSC7RATECTL(x) ((x) << S_TSC7RATECTL)
44710 #define F_TSC7RATECTL    V_TSC7RATECTL(1U)
44711 
44712 #define S_TSC6RATECTL    6
44713 #define V_TSC6RATECTL(x) ((x) << S_TSC6RATECTL)
44714 #define F_TSC6RATECTL    V_TSC6RATECTL(1U)
44715 
44716 #define S_TSC5RATECTL    5
44717 #define V_TSC5RATECTL(x) ((x) << S_TSC5RATECTL)
44718 #define F_TSC5RATECTL    V_TSC5RATECTL(1U)
44719 
44720 #define S_TSC4RATECTL    4
44721 #define V_TSC4RATECTL(x) ((x) << S_TSC4RATECTL)
44722 #define F_TSC4RATECTL    V_TSC4RATECTL(1U)
44723 
44724 #define S_TSC3RATECTL    3
44725 #define V_TSC3RATECTL(x) ((x) << S_TSC3RATECTL)
44726 #define F_TSC3RATECTL    V_TSC3RATECTL(1U)
44727 
44728 #define S_TSC2RATECTL    2
44729 #define V_TSC2RATECTL(x) ((x) << S_TSC2RATECTL)
44730 #define F_TSC2RATECTL    V_TSC2RATECTL(1U)
44731 
44732 #define S_TSC1RATECTL    1
44733 #define V_TSC1RATECTL(x) ((x) << S_TSC1RATECTL)
44734 #define F_TSC1RATECTL    V_TSC1RATECTL(1U)
44735 
44736 #define S_TSC0RATECTL    0
44737 #define V_TSC0RATECTL(x) ((x) << S_TSC0RATECTL)
44738 #define F_TSC0RATECTL    V_TSC0RATECTL(1U)
44739 
44740 #define A_CIM_CTL_TSCH_CHNLN_CLASS_ENABLE_A 0x908
44741 
44742 #define S_TSC15WRREN    31
44743 #define V_TSC15WRREN(x) ((x) << S_TSC15WRREN)
44744 #define F_TSC15WRREN    V_TSC15WRREN(1U)
44745 
44746 #define S_TSC15RATEEN    30
44747 #define V_TSC15RATEEN(x) ((x) << S_TSC15RATEEN)
44748 #define F_TSC15RATEEN    V_TSC15RATEEN(1U)
44749 
44750 #define S_TSC14WRREN    29
44751 #define V_TSC14WRREN(x) ((x) << S_TSC14WRREN)
44752 #define F_TSC14WRREN    V_TSC14WRREN(1U)
44753 
44754 #define S_TSC14RATEEN    28
44755 #define V_TSC14RATEEN(x) ((x) << S_TSC14RATEEN)
44756 #define F_TSC14RATEEN    V_TSC14RATEEN(1U)
44757 
44758 #define S_TSC13WRREN    27
44759 #define V_TSC13WRREN(x) ((x) << S_TSC13WRREN)
44760 #define F_TSC13WRREN    V_TSC13WRREN(1U)
44761 
44762 #define S_TSC13RATEEN    26
44763 #define V_TSC13RATEEN(x) ((x) << S_TSC13RATEEN)
44764 #define F_TSC13RATEEN    V_TSC13RATEEN(1U)
44765 
44766 #define S_TSC12WRREN    25
44767 #define V_TSC12WRREN(x) ((x) << S_TSC12WRREN)
44768 #define F_TSC12WRREN    V_TSC12WRREN(1U)
44769 
44770 #define S_TSC12RATEEN    24
44771 #define V_TSC12RATEEN(x) ((x) << S_TSC12RATEEN)
44772 #define F_TSC12RATEEN    V_TSC12RATEEN(1U)
44773 
44774 #define S_TSC11WRREN    23
44775 #define V_TSC11WRREN(x) ((x) << S_TSC11WRREN)
44776 #define F_TSC11WRREN    V_TSC11WRREN(1U)
44777 
44778 #define S_TSC11RATEEN    22
44779 #define V_TSC11RATEEN(x) ((x) << S_TSC11RATEEN)
44780 #define F_TSC11RATEEN    V_TSC11RATEEN(1U)
44781 
44782 #define S_TSC10WRREN    21
44783 #define V_TSC10WRREN(x) ((x) << S_TSC10WRREN)
44784 #define F_TSC10WRREN    V_TSC10WRREN(1U)
44785 
44786 #define S_TSC10RATEEN    20
44787 #define V_TSC10RATEEN(x) ((x) << S_TSC10RATEEN)
44788 #define F_TSC10RATEEN    V_TSC10RATEEN(1U)
44789 
44790 #define S_TSC9WRREN    19
44791 #define V_TSC9WRREN(x) ((x) << S_TSC9WRREN)
44792 #define F_TSC9WRREN    V_TSC9WRREN(1U)
44793 
44794 #define S_TSC9RATEEN    18
44795 #define V_TSC9RATEEN(x) ((x) << S_TSC9RATEEN)
44796 #define F_TSC9RATEEN    V_TSC9RATEEN(1U)
44797 
44798 #define S_TSC8WRREN    17
44799 #define V_TSC8WRREN(x) ((x) << S_TSC8WRREN)
44800 #define F_TSC8WRREN    V_TSC8WRREN(1U)
44801 
44802 #define S_TSC8RATEEN    16
44803 #define V_TSC8RATEEN(x) ((x) << S_TSC8RATEEN)
44804 #define F_TSC8RATEEN    V_TSC8RATEEN(1U)
44805 
44806 #define S_TSC7WRREN    15
44807 #define V_TSC7WRREN(x) ((x) << S_TSC7WRREN)
44808 #define F_TSC7WRREN    V_TSC7WRREN(1U)
44809 
44810 #define S_TSC7RATEEN    14
44811 #define V_TSC7RATEEN(x) ((x) << S_TSC7RATEEN)
44812 #define F_TSC7RATEEN    V_TSC7RATEEN(1U)
44813 
44814 #define S_TSC6WRREN    13
44815 #define V_TSC6WRREN(x) ((x) << S_TSC6WRREN)
44816 #define F_TSC6WRREN    V_TSC6WRREN(1U)
44817 
44818 #define S_TSC6RATEEN    12
44819 #define V_TSC6RATEEN(x) ((x) << S_TSC6RATEEN)
44820 #define F_TSC6RATEEN    V_TSC6RATEEN(1U)
44821 
44822 #define S_TSC5WRREN    11
44823 #define V_TSC5WRREN(x) ((x) << S_TSC5WRREN)
44824 #define F_TSC5WRREN    V_TSC5WRREN(1U)
44825 
44826 #define S_TSC5RATEEN    10
44827 #define V_TSC5RATEEN(x) ((x) << S_TSC5RATEEN)
44828 #define F_TSC5RATEEN    V_TSC5RATEEN(1U)
44829 
44830 #define S_TSC4WRREN    9
44831 #define V_TSC4WRREN(x) ((x) << S_TSC4WRREN)
44832 #define F_TSC4WRREN    V_TSC4WRREN(1U)
44833 
44834 #define S_TSC4RATEEN    8
44835 #define V_TSC4RATEEN(x) ((x) << S_TSC4RATEEN)
44836 #define F_TSC4RATEEN    V_TSC4RATEEN(1U)
44837 
44838 #define S_TSC3WRREN    7
44839 #define V_TSC3WRREN(x) ((x) << S_TSC3WRREN)
44840 #define F_TSC3WRREN    V_TSC3WRREN(1U)
44841 
44842 #define S_TSC3RATEEN    6
44843 #define V_TSC3RATEEN(x) ((x) << S_TSC3RATEEN)
44844 #define F_TSC3RATEEN    V_TSC3RATEEN(1U)
44845 
44846 #define S_TSC2WRREN    5
44847 #define V_TSC2WRREN(x) ((x) << S_TSC2WRREN)
44848 #define F_TSC2WRREN    V_TSC2WRREN(1U)
44849 
44850 #define S_TSC2RATEEN    4
44851 #define V_TSC2RATEEN(x) ((x) << S_TSC2RATEEN)
44852 #define F_TSC2RATEEN    V_TSC2RATEEN(1U)
44853 
44854 #define S_TSC1WRREN    3
44855 #define V_TSC1WRREN(x) ((x) << S_TSC1WRREN)
44856 #define F_TSC1WRREN    V_TSC1WRREN(1U)
44857 
44858 #define S_TSC1RATEEN    2
44859 #define V_TSC1RATEEN(x) ((x) << S_TSC1RATEEN)
44860 #define F_TSC1RATEEN    V_TSC1RATEEN(1U)
44861 
44862 #define S_TSC0WRREN    1
44863 #define V_TSC0WRREN(x) ((x) << S_TSC0WRREN)
44864 #define F_TSC0WRREN    V_TSC0WRREN(1U)
44865 
44866 #define S_TSC0RATEEN    0
44867 #define V_TSC0RATEEN(x) ((x) << S_TSC0RATEEN)
44868 #define F_TSC0RATEEN    V_TSC0RATEEN(1U)
44869 
44870 #define A_CIM_CTL_TSCH_MIN_MAX_EN 0x90c
44871 
44872 #define S_MIN_MAX_EN    0
44873 #define V_MIN_MAX_EN(x) ((x) << S_MIN_MAX_EN)
44874 #define F_MIN_MAX_EN    V_MIN_MAX_EN(1U)
44875 
44876 #define A_CIM_CTL_TSCH_CHNLN_RATE_LIMITER 0x910
44877 
44878 #define S_TSCHNLRATENEG    31
44879 #define V_TSCHNLRATENEG(x) ((x) << S_TSCHNLRATENEG)
44880 #define F_TSCHNLRATENEG    V_TSCHNLRATENEG(1U)
44881 
44882 #define S_TSCHNLRATEL    0
44883 #define M_TSCHNLRATEL    0x7fffffffU
44884 #define V_TSCHNLRATEL(x) ((x) << S_TSCHNLRATEL)
44885 #define G_TSCHNLRATEL(x) (((x) >> S_TSCHNLRATEL) & M_TSCHNLRATEL)
44886 
44887 #define S_TSCHNLRATEPROT    30
44888 #define V_TSCHNLRATEPROT(x) ((x) << S_TSCHNLRATEPROT)
44889 #define F_TSCHNLRATEPROT    V_TSCHNLRATEPROT(1U)
44890 
44891 #define S_T6_TSCHNLRATEL    0
44892 #define M_T6_TSCHNLRATEL    0x3fffffffU
44893 #define V_T6_TSCHNLRATEL(x) ((x) << S_T6_TSCHNLRATEL)
44894 #define G_T6_TSCHNLRATEL(x) (((x) >> S_T6_TSCHNLRATEL) & M_T6_TSCHNLRATEL)
44895 
44896 #define A_CIM_CTL_TSCH_CHNLN_RATE_PROPERTIES 0x914
44897 
44898 #define S_TSCHNLRMAX    16
44899 #define M_TSCHNLRMAX    0xffffU
44900 #define V_TSCHNLRMAX(x) ((x) << S_TSCHNLRMAX)
44901 #define G_TSCHNLRMAX(x) (((x) >> S_TSCHNLRMAX) & M_TSCHNLRMAX)
44902 
44903 #define S_TSCHNLRINCR    0
44904 #define M_TSCHNLRINCR    0xffffU
44905 #define V_TSCHNLRINCR(x) ((x) << S_TSCHNLRINCR)
44906 #define G_TSCHNLRINCR(x) (((x) >> S_TSCHNLRINCR) & M_TSCHNLRINCR)
44907 
44908 #define S_TSCHNLRTSEL    14
44909 #define M_TSCHNLRTSEL    0x3U
44910 #define V_TSCHNLRTSEL(x) ((x) << S_TSCHNLRTSEL)
44911 #define G_TSCHNLRTSEL(x) (((x) >> S_TSCHNLRTSEL) & M_TSCHNLRTSEL)
44912 
44913 #define S_T6_TSCHNLRINCR    0
44914 #define M_T6_TSCHNLRINCR    0x3fffU
44915 #define V_T6_TSCHNLRINCR(x) ((x) << S_T6_TSCHNLRINCR)
44916 #define G_T6_TSCHNLRINCR(x) (((x) >> S_T6_TSCHNLRINCR) & M_T6_TSCHNLRINCR)
44917 
44918 #define A_CIM_CTL_TSCH_CHNLN_WRR 0x918
44919 #define A_CIM_CTL_TSCH_CHNLN_WEIGHT 0x91c
44920 
44921 #define S_TSCHNLWEIGHT    0
44922 #define M_TSCHNLWEIGHT    0x3fffffU
44923 #define V_TSCHNLWEIGHT(x) ((x) << S_TSCHNLWEIGHT)
44924 #define G_TSCHNLWEIGHT(x) (((x) >> S_TSCHNLWEIGHT) & M_TSCHNLWEIGHT)
44925 
44926 #define A_CIM_CTL_TSCH_CHNLN_CLASSM_RATE_LIMITER 0x920
44927 
44928 #define S_TSCCLRATENEG    31
44929 #define V_TSCCLRATENEG(x) ((x) << S_TSCCLRATENEG)
44930 #define F_TSCCLRATENEG    V_TSCCLRATENEG(1U)
44931 
44932 #define S_TSCCLRATEL    0
44933 #define M_TSCCLRATEL    0xffffffU
44934 #define V_TSCCLRATEL(x) ((x) << S_TSCCLRATEL)
44935 #define G_TSCCLRATEL(x) (((x) >> S_TSCCLRATEL) & M_TSCCLRATEL)
44936 
44937 #define S_TSCCLRATEPROT    30
44938 #define V_TSCCLRATEPROT(x) ((x) << S_TSCCLRATEPROT)
44939 #define F_TSCCLRATEPROT    V_TSCCLRATEPROT(1U)
44940 
44941 #define A_CIM_CTL_TSCH_CHNLN_CLASSM_RATE_PROPERTIES 0x924
44942 
44943 #define S_TSCCLRMAX    16
44944 #define M_TSCCLRMAX    0xffffU
44945 #define V_TSCCLRMAX(x) ((x) << S_TSCCLRMAX)
44946 #define G_TSCCLRMAX(x) (((x) >> S_TSCCLRMAX) & M_TSCCLRMAX)
44947 
44948 #define S_TSCCLRINCR    0
44949 #define M_TSCCLRINCR    0xffffU
44950 #define V_TSCCLRINCR(x) ((x) << S_TSCCLRINCR)
44951 #define G_TSCCLRINCR(x) (((x) >> S_TSCCLRINCR) & M_TSCCLRINCR)
44952 
44953 #define S_TSCCLRTSEL    14
44954 #define M_TSCCLRTSEL    0x3U
44955 #define V_TSCCLRTSEL(x) ((x) << S_TSCCLRTSEL)
44956 #define G_TSCCLRTSEL(x) (((x) >> S_TSCCLRTSEL) & M_TSCCLRTSEL)
44957 
44958 #define S_T6_TSCCLRINCR    0
44959 #define M_T6_TSCCLRINCR    0x3fffU
44960 #define V_T6_TSCCLRINCR(x) ((x) << S_T6_TSCCLRINCR)
44961 #define G_T6_TSCCLRINCR(x) (((x) >> S_T6_TSCCLRINCR) & M_T6_TSCCLRINCR)
44962 
44963 #define A_CIM_CTL_TSCH_CHNLN_CLASSM_WRR 0x928
44964 
44965 #define S_TSCCLWRRNEG    31
44966 #define V_TSCCLWRRNEG(x) ((x) << S_TSCCLWRRNEG)
44967 #define F_TSCCLWRRNEG    V_TSCCLWRRNEG(1U)
44968 
44969 #define S_TSCCLWRR    0
44970 #define M_TSCCLWRR    0x3ffffffU
44971 #define V_TSCCLWRR(x) ((x) << S_TSCCLWRR)
44972 #define G_TSCCLWRR(x) (((x) >> S_TSCCLWRR) & M_TSCCLWRR)
44973 
44974 #define S_TSCCLWRRPROT    30
44975 #define V_TSCCLWRRPROT(x) ((x) << S_TSCCLWRRPROT)
44976 #define F_TSCCLWRRPROT    V_TSCCLWRRPROT(1U)
44977 
44978 #define A_CIM_CTL_TSCH_CHNLN_CLASSM_WEIGHT 0x92c
44979 
44980 #define S_TSCCLWEIGHT    0
44981 #define M_TSCCLWEIGHT    0xffffU
44982 #define V_TSCCLWEIGHT(x) ((x) << S_TSCCLWEIGHT)
44983 #define G_TSCCLWEIGHT(x) (((x) >> S_TSCCLWEIGHT) & M_TSCCLWEIGHT)
44984 
44985 #define S_PAUSEVECSEL    28
44986 #define M_PAUSEVECSEL    0x3U
44987 #define V_PAUSEVECSEL(x) ((x) << S_PAUSEVECSEL)
44988 #define G_PAUSEVECSEL(x) (((x) >> S_PAUSEVECSEL) & M_PAUSEVECSEL)
44989 
44990 #define S_MPSPAUSEMASK    20
44991 #define M_MPSPAUSEMASK    0xffU
44992 #define V_MPSPAUSEMASK(x) ((x) << S_MPSPAUSEMASK)
44993 #define G_MPSPAUSEMASK(x) (((x) >> S_MPSPAUSEMASK) & M_MPSPAUSEMASK)
44994 
44995 #define A_CIM_CTL_TSCH_TICK0 0xd80
44996 #define A_CIM_CTL_MAILBOX_PF0_CTL 0xd84
44997 #define A_CIM_CTL_TSCH_TICK1 0xd84
44998 #define A_CIM_CTL_MAILBOX_PF1_CTL 0xd88
44999 #define A_CIM_CTL_TSCH_TICK2 0xd88
45000 #define A_CIM_CTL_MAILBOX_PF2_CTL 0xd8c
45001 #define A_CIM_CTL_TSCH_TICK3 0xd8c
45002 #define A_CIM_CTL_MAILBOX_PF3_CTL 0xd90
45003 #define A_T6_CIM_CTL_MAILBOX_PF0_CTL 0xd90
45004 #define A_CIM_CTL_MAILBOX_PF4_CTL 0xd94
45005 #define A_T6_CIM_CTL_MAILBOX_PF1_CTL 0xd94
45006 #define A_CIM_CTL_MAILBOX_PF5_CTL 0xd98
45007 #define A_T6_CIM_CTL_MAILBOX_PF2_CTL 0xd98
45008 #define A_CIM_CTL_MAILBOX_PF6_CTL 0xd9c
45009 #define A_T6_CIM_CTL_MAILBOX_PF3_CTL 0xd9c
45010 #define A_CIM_CTL_MAILBOX_PF7_CTL 0xda0
45011 #define A_T6_CIM_CTL_MAILBOX_PF4_CTL 0xda0
45012 #define A_CIM_CTL_MAILBOX_CTL_OWNER_COPY 0xda4
45013 
45014 #define S_PF7_OWNER_PL    15
45015 #define V_PF7_OWNER_PL(x) ((x) << S_PF7_OWNER_PL)
45016 #define F_PF7_OWNER_PL    V_PF7_OWNER_PL(1U)
45017 
45018 #define S_PF6_OWNER_PL    14
45019 #define V_PF6_OWNER_PL(x) ((x) << S_PF6_OWNER_PL)
45020 #define F_PF6_OWNER_PL    V_PF6_OWNER_PL(1U)
45021 
45022 #define S_PF5_OWNER_PL    13
45023 #define V_PF5_OWNER_PL(x) ((x) << S_PF5_OWNER_PL)
45024 #define F_PF5_OWNER_PL    V_PF5_OWNER_PL(1U)
45025 
45026 #define S_PF4_OWNER_PL    12
45027 #define V_PF4_OWNER_PL(x) ((x) << S_PF4_OWNER_PL)
45028 #define F_PF4_OWNER_PL    V_PF4_OWNER_PL(1U)
45029 
45030 #define S_PF3_OWNER_PL    11
45031 #define V_PF3_OWNER_PL(x) ((x) << S_PF3_OWNER_PL)
45032 #define F_PF3_OWNER_PL    V_PF3_OWNER_PL(1U)
45033 
45034 #define S_PF2_OWNER_PL    10
45035 #define V_PF2_OWNER_PL(x) ((x) << S_PF2_OWNER_PL)
45036 #define F_PF2_OWNER_PL    V_PF2_OWNER_PL(1U)
45037 
45038 #define S_PF1_OWNER_PL    9
45039 #define V_PF1_OWNER_PL(x) ((x) << S_PF1_OWNER_PL)
45040 #define F_PF1_OWNER_PL    V_PF1_OWNER_PL(1U)
45041 
45042 #define S_PF0_OWNER_PL    8
45043 #define V_PF0_OWNER_PL(x) ((x) << S_PF0_OWNER_PL)
45044 #define F_PF0_OWNER_PL    V_PF0_OWNER_PL(1U)
45045 
45046 #define S_PF7_OWNER_UP    7
45047 #define V_PF7_OWNER_UP(x) ((x) << S_PF7_OWNER_UP)
45048 #define F_PF7_OWNER_UP    V_PF7_OWNER_UP(1U)
45049 
45050 #define S_PF6_OWNER_UP    6
45051 #define V_PF6_OWNER_UP(x) ((x) << S_PF6_OWNER_UP)
45052 #define F_PF6_OWNER_UP    V_PF6_OWNER_UP(1U)
45053 
45054 #define S_PF5_OWNER_UP    5
45055 #define V_PF5_OWNER_UP(x) ((x) << S_PF5_OWNER_UP)
45056 #define F_PF5_OWNER_UP    V_PF5_OWNER_UP(1U)
45057 
45058 #define S_PF4_OWNER_UP    4
45059 #define V_PF4_OWNER_UP(x) ((x) << S_PF4_OWNER_UP)
45060 #define F_PF4_OWNER_UP    V_PF4_OWNER_UP(1U)
45061 
45062 #define S_PF3_OWNER_UP    3
45063 #define V_PF3_OWNER_UP(x) ((x) << S_PF3_OWNER_UP)
45064 #define F_PF3_OWNER_UP    V_PF3_OWNER_UP(1U)
45065 
45066 #define S_PF2_OWNER_UP    2
45067 #define V_PF2_OWNER_UP(x) ((x) << S_PF2_OWNER_UP)
45068 #define F_PF2_OWNER_UP    V_PF2_OWNER_UP(1U)
45069 
45070 #define S_PF1_OWNER_UP    1
45071 #define V_PF1_OWNER_UP(x) ((x) << S_PF1_OWNER_UP)
45072 #define F_PF1_OWNER_UP    V_PF1_OWNER_UP(1U)
45073 
45074 #define S_PF0_OWNER_UP    0
45075 #define V_PF0_OWNER_UP(x) ((x) << S_PF0_OWNER_UP)
45076 #define F_PF0_OWNER_UP    V_PF0_OWNER_UP(1U)
45077 
45078 #define A_T6_CIM_CTL_MAILBOX_PF5_CTL 0xda4
45079 #define A_CIM_CTL_PIO_MST_CONFIG 0xda8
45080 
45081 #define S_T5_CTLRID    0
45082 #define M_T5_CTLRID    0xffU
45083 #define V_T5_CTLRID(x) ((x) << S_T5_CTLRID)
45084 #define G_T5_CTLRID(x) (((x) >> S_T5_CTLRID) & M_T5_CTLRID)
45085 
45086 #define A_T6_CIM_CTL_MAILBOX_PF6_CTL 0xda8
45087 #define A_T6_CIM_CTL_MAILBOX_PF7_CTL 0xdac
45088 #define A_T6_CIM_CTL_MAILBOX_CTL_OWNER_COPY 0xdb0
45089 #define A_T6_CIM_CTL_PIO_MST_CONFIG 0xdb4
45090 
45091 #define S_T6_UPRID    0
45092 #define M_T6_UPRID    0x1ffU
45093 #define V_T6_UPRID(x) ((x) << S_T6_UPRID)
45094 #define G_T6_UPRID(x) (((x) >> S_T6_UPRID) & M_T6_UPRID)
45095 
45096 #define A_CIM_CTL_ULP_OBQ0_PAUSE_MASK 0xe00
45097 #define A_CIM_CTL_ULP_OBQ1_PAUSE_MASK 0xe04
45098 #define A_CIM_CTL_ULP_OBQ2_PAUSE_MASK 0xe08
45099 #define A_CIM_CTL_ULP_OBQ3_PAUSE_MASK 0xe0c
45100 #define A_CIM_CTL_ULP_OBQ_CONFIG 0xe10
45101 
45102 #define S_CH1_PRIO_EN    1
45103 #define V_CH1_PRIO_EN(x) ((x) << S_CH1_PRIO_EN)
45104 #define F_CH1_PRIO_EN    V_CH1_PRIO_EN(1U)
45105 
45106 #define S_CH0_PRIO_EN    0
45107 #define V_CH0_PRIO_EN(x) ((x) << S_CH0_PRIO_EN)
45108 #define F_CH0_PRIO_EN    V_CH0_PRIO_EN(1U)
45109 
45110 #define A_CIM_CTL_PIF_TIMEOUT 0xe40
45111 
45112 #define S_SLOW_TIMEOUT    16
45113 #define M_SLOW_TIMEOUT    0xffffU
45114 #define V_SLOW_TIMEOUT(x) ((x) << S_SLOW_TIMEOUT)
45115 #define G_SLOW_TIMEOUT(x) (((x) >> S_SLOW_TIMEOUT) & M_SLOW_TIMEOUT)
45116 
45117 #define S_MA_TIMEOUT    0
45118 #define M_MA_TIMEOUT    0xffffU
45119 #define V_MA_TIMEOUT(x) ((x) << S_MA_TIMEOUT)
45120 #define G_MA_TIMEOUT(x) (((x) >> S_MA_TIMEOUT) & M_MA_TIMEOUT)
45121 
45122 /* registers for module MAC */
45123 #define MAC_BASE_ADDR 0x0
45124 
45125 #define A_MAC_PORT_CFG 0x800
45126 
45127 #define S_MAC_CLK_SEL    29
45128 #define M_MAC_CLK_SEL    0x7U
45129 #define V_MAC_CLK_SEL(x) ((x) << S_MAC_CLK_SEL)
45130 #define G_MAC_CLK_SEL(x) (((x) >> S_MAC_CLK_SEL) & M_MAC_CLK_SEL)
45131 
45132 #define S_SMUXTXSEL    9
45133 #define V_SMUXTXSEL(x) ((x) << S_SMUXTXSEL)
45134 #define F_SMUXTXSEL    V_SMUXTXSEL(1U)
45135 
45136 #define S_SMUXRXSEL    8
45137 #define V_SMUXRXSEL(x) ((x) << S_SMUXRXSEL)
45138 #define F_SMUXRXSEL    V_SMUXRXSEL(1U)
45139 
45140 #define S_PORTSPEED    4
45141 #define M_PORTSPEED    0x3U
45142 #define V_PORTSPEED(x) ((x) << S_PORTSPEED)
45143 #define G_PORTSPEED(x) (((x) >> S_PORTSPEED) & M_PORTSPEED)
45144 
45145 #define S_ENA_ERR_RSP    28
45146 #define V_ENA_ERR_RSP(x) ((x) << S_ENA_ERR_RSP)
45147 #define F_ENA_ERR_RSP    V_ENA_ERR_RSP(1U)
45148 
45149 #define S_DEBUG_CLR    25
45150 #define V_DEBUG_CLR(x) ((x) << S_DEBUG_CLR)
45151 #define F_DEBUG_CLR    V_DEBUG_CLR(1U)
45152 
45153 #define S_PLL_SEL    23
45154 #define V_PLL_SEL(x) ((x) << S_PLL_SEL)
45155 #define F_PLL_SEL    V_PLL_SEL(1U)
45156 
45157 #define S_PORT_MAP    20
45158 #define M_PORT_MAP    0x7U
45159 #define V_PORT_MAP(x) ((x) << S_PORT_MAP)
45160 #define G_PORT_MAP(x) (((x) >> S_PORT_MAP) & M_PORT_MAP)
45161 
45162 #define S_AEC_PAT_DATA    15
45163 #define V_AEC_PAT_DATA(x) ((x) << S_AEC_PAT_DATA)
45164 #define F_AEC_PAT_DATA    V_AEC_PAT_DATA(1U)
45165 
45166 #define S_MACCLK_SEL    13
45167 #define V_MACCLK_SEL(x) ((x) << S_MACCLK_SEL)
45168 #define F_MACCLK_SEL    V_MACCLK_SEL(1U)
45169 
45170 #define S_XGMII_SEL    12
45171 #define V_XGMII_SEL(x) ((x) << S_XGMII_SEL)
45172 #define F_XGMII_SEL    V_XGMII_SEL(1U)
45173 
45174 #define S_DEBUG_PORT_SEL    10
45175 #define M_DEBUG_PORT_SEL    0x3U
45176 #define V_DEBUG_PORT_SEL(x) ((x) << S_DEBUG_PORT_SEL)
45177 #define G_DEBUG_PORT_SEL(x) (((x) >> S_DEBUG_PORT_SEL) & M_DEBUG_PORT_SEL)
45178 
45179 #define S_ENABLE_25G    7
45180 #define V_ENABLE_25G(x) ((x) << S_ENABLE_25G)
45181 #define F_ENABLE_25G    V_ENABLE_25G(1U)
45182 
45183 #define S_ENABLE_50G    6
45184 #define V_ENABLE_50G(x) ((x) << S_ENABLE_50G)
45185 #define F_ENABLE_50G    V_ENABLE_50G(1U)
45186 
45187 #define S_DEBUG_TX_RX_SEL    1
45188 #define V_DEBUG_TX_RX_SEL(x) ((x) << S_DEBUG_TX_RX_SEL)
45189 #define F_DEBUG_TX_RX_SEL    V_DEBUG_TX_RX_SEL(1U)
45190 
45191 #define A_MAC_PORT_RESET_CTRL 0x804
45192 
45193 #define S_TWGDSK_HSSC16B    31
45194 #define V_TWGDSK_HSSC16B(x) ((x) << S_TWGDSK_HSSC16B)
45195 #define F_TWGDSK_HSSC16B    V_TWGDSK_HSSC16B(1U)
45196 
45197 #define S_EEE_RESET    30
45198 #define V_EEE_RESET(x) ((x) << S_EEE_RESET)
45199 #define F_EEE_RESET    V_EEE_RESET(1U)
45200 
45201 #define S_PTP_TIMER    29
45202 #define V_PTP_TIMER(x) ((x) << S_PTP_TIMER)
45203 #define F_PTP_TIMER    V_PTP_TIMER(1U)
45204 
45205 #define S_MTIPREFRESET    28
45206 #define V_MTIPREFRESET(x) ((x) << S_MTIPREFRESET)
45207 #define F_MTIPREFRESET    V_MTIPREFRESET(1U)
45208 
45209 #define S_MTIPTXFFRESET    27
45210 #define V_MTIPTXFFRESET(x) ((x) << S_MTIPTXFFRESET)
45211 #define F_MTIPTXFFRESET    V_MTIPTXFFRESET(1U)
45212 
45213 #define S_MTIPRXFFRESET    26
45214 #define V_MTIPRXFFRESET(x) ((x) << S_MTIPRXFFRESET)
45215 #define F_MTIPRXFFRESET    V_MTIPRXFFRESET(1U)
45216 
45217 #define S_MTIPREGRESET    25
45218 #define V_MTIPREGRESET(x) ((x) << S_MTIPREGRESET)
45219 #define F_MTIPREGRESET    V_MTIPREGRESET(1U)
45220 
45221 #define S_AEC3RESET    23
45222 #define V_AEC3RESET(x) ((x) << S_AEC3RESET)
45223 #define F_AEC3RESET    V_AEC3RESET(1U)
45224 
45225 #define S_AEC2RESET    22
45226 #define V_AEC2RESET(x) ((x) << S_AEC2RESET)
45227 #define F_AEC2RESET    V_AEC2RESET(1U)
45228 
45229 #define S_AEC1RESET    21
45230 #define V_AEC1RESET(x) ((x) << S_AEC1RESET)
45231 #define F_AEC1RESET    V_AEC1RESET(1U)
45232 
45233 #define S_AEC0RESET    20
45234 #define V_AEC0RESET(x) ((x) << S_AEC0RESET)
45235 #define F_AEC0RESET    V_AEC0RESET(1U)
45236 
45237 #define S_AET3RESET    19
45238 #define V_AET3RESET(x) ((x) << S_AET3RESET)
45239 #define F_AET3RESET    V_AET3RESET(1U)
45240 
45241 #define S_AET2RESET    18
45242 #define V_AET2RESET(x) ((x) << S_AET2RESET)
45243 #define F_AET2RESET    V_AET2RESET(1U)
45244 
45245 #define S_AET1RESET    17
45246 #define V_AET1RESET(x) ((x) << S_AET1RESET)
45247 #define F_AET1RESET    V_AET1RESET(1U)
45248 
45249 #define S_AET0RESET    16
45250 #define V_AET0RESET(x) ((x) << S_AET0RESET)
45251 #define F_AET0RESET    V_AET0RESET(1U)
45252 
45253 #define S_TXIF_RESET    12
45254 #define V_TXIF_RESET(x) ((x) << S_TXIF_RESET)
45255 #define F_TXIF_RESET    V_TXIF_RESET(1U)
45256 
45257 #define S_RXIF_RESET    11
45258 #define V_RXIF_RESET(x) ((x) << S_RXIF_RESET)
45259 #define F_RXIF_RESET    V_RXIF_RESET(1U)
45260 
45261 #define S_MTIPSD3TXRST    9
45262 #define V_MTIPSD3TXRST(x) ((x) << S_MTIPSD3TXRST)
45263 #define F_MTIPSD3TXRST    V_MTIPSD3TXRST(1U)
45264 
45265 #define S_MTIPSD2TXRST    8
45266 #define V_MTIPSD2TXRST(x) ((x) << S_MTIPSD2TXRST)
45267 #define F_MTIPSD2TXRST    V_MTIPSD2TXRST(1U)
45268 
45269 #define S_MTIPSD1TXRST    7
45270 #define V_MTIPSD1TXRST(x) ((x) << S_MTIPSD1TXRST)
45271 #define F_MTIPSD1TXRST    V_MTIPSD1TXRST(1U)
45272 
45273 #define S_MTIPSD0TXRST    6
45274 #define V_MTIPSD0TXRST(x) ((x) << S_MTIPSD0TXRST)
45275 #define F_MTIPSD0TXRST    V_MTIPSD0TXRST(1U)
45276 
45277 #define S_MTIPSD3RXRST    5
45278 #define V_MTIPSD3RXRST(x) ((x) << S_MTIPSD3RXRST)
45279 #define F_MTIPSD3RXRST    V_MTIPSD3RXRST(1U)
45280 
45281 #define S_MTIPSD2RXRST    4
45282 #define V_MTIPSD2RXRST(x) ((x) << S_MTIPSD2RXRST)
45283 #define F_MTIPSD2RXRST    V_MTIPSD2RXRST(1U)
45284 
45285 #define S_MTIPSD1RXRST    3
45286 #define V_MTIPSD1RXRST(x) ((x) << S_MTIPSD1RXRST)
45287 #define F_MTIPSD1RXRST    V_MTIPSD1RXRST(1U)
45288 
45289 #define S_MTIPSD0RXRST    1
45290 #define V_MTIPSD0RXRST(x) ((x) << S_MTIPSD0RXRST)
45291 #define F_MTIPSD0RXRST    V_MTIPSD0RXRST(1U)
45292 
45293 #define S_MAC100G40G_RESET    27
45294 #define V_MAC100G40G_RESET(x) ((x) << S_MAC100G40G_RESET)
45295 #define F_MAC100G40G_RESET    V_MAC100G40G_RESET(1U)
45296 
45297 #define S_MAC10G1G_RESET    26
45298 #define V_MAC10G1G_RESET(x) ((x) << S_MAC10G1G_RESET)
45299 #define F_MAC10G1G_RESET    V_MAC10G1G_RESET(1U)
45300 
45301 #define S_PCS1G_RESET    24
45302 #define V_PCS1G_RESET(x) ((x) << S_PCS1G_RESET)
45303 #define F_PCS1G_RESET    V_PCS1G_RESET(1U)
45304 
45305 #define S_PCS10G_RESET    15
45306 #define V_PCS10G_RESET(x) ((x) << S_PCS10G_RESET)
45307 #define F_PCS10G_RESET    V_PCS10G_RESET(1U)
45308 
45309 #define S_PCS40G_RESET    14
45310 #define V_PCS40G_RESET(x) ((x) << S_PCS40G_RESET)
45311 #define F_PCS40G_RESET    V_PCS40G_RESET(1U)
45312 
45313 #define S_PCS100G_RESET    13
45314 #define V_PCS100G_RESET(x) ((x) << S_PCS100G_RESET)
45315 #define F_PCS100G_RESET    V_PCS100G_RESET(1U)
45316 
45317 #define A_MAC_PORT_LED_CFG 0x808
45318 
45319 #define S_LED1_CFG1    14
45320 #define M_LED1_CFG1    0x3U
45321 #define V_LED1_CFG1(x) ((x) << S_LED1_CFG1)
45322 #define G_LED1_CFG1(x) (((x) >> S_LED1_CFG1) & M_LED1_CFG1)
45323 
45324 #define S_LED0_CFG1    12
45325 #define M_LED0_CFG1    0x3U
45326 #define V_LED0_CFG1(x) ((x) << S_LED0_CFG1)
45327 #define G_LED0_CFG1(x) (((x) >> S_LED0_CFG1) & M_LED0_CFG1)
45328 
45329 #define S_LED1_TLO    11
45330 #define V_LED1_TLO(x) ((x) << S_LED1_TLO)
45331 #define F_LED1_TLO    V_LED1_TLO(1U)
45332 
45333 #define S_LED1_THI    10
45334 #define V_LED1_THI(x) ((x) << S_LED1_THI)
45335 #define F_LED1_THI    V_LED1_THI(1U)
45336 
45337 #define S_LED0_TLO    9
45338 #define V_LED0_TLO(x) ((x) << S_LED0_TLO)
45339 #define F_LED0_TLO    V_LED0_TLO(1U)
45340 
45341 #define S_LED0_THI    8
45342 #define V_LED0_THI(x) ((x) << S_LED0_THI)
45343 #define F_LED0_THI    V_LED0_THI(1U)
45344 
45345 #define A_MAC_PORT_LED_COUNTHI 0x80c
45346 #define A_MAC_PORT_LED_COUNTLO 0x810
45347 #define A_MAC_PORT_CFG3 0x814
45348 
45349 #define S_T5_FPGA_PTP_PORT    26
45350 #define M_T5_FPGA_PTP_PORT    0x3U
45351 #define V_T5_FPGA_PTP_PORT(x) ((x) << S_T5_FPGA_PTP_PORT)
45352 #define G_T5_FPGA_PTP_PORT(x) (((x) >> S_T5_FPGA_PTP_PORT) & M_T5_FPGA_PTP_PORT)
45353 
45354 #define S_FCSDISCTRL    25
45355 #define V_FCSDISCTRL(x) ((x) << S_FCSDISCTRL)
45356 #define F_FCSDISCTRL    V_FCSDISCTRL(1U)
45357 
45358 #define S_SIGDETCTRL    24
45359 #define V_SIGDETCTRL(x) ((x) << S_SIGDETCTRL)
45360 #define F_SIGDETCTRL    V_SIGDETCTRL(1U)
45361 
45362 #define S_TX_LANE    23
45363 #define V_TX_LANE(x) ((x) << S_TX_LANE)
45364 #define F_TX_LANE    V_TX_LANE(1U)
45365 
45366 #define S_RX_LANE    22
45367 #define V_RX_LANE(x) ((x) << S_RX_LANE)
45368 #define F_RX_LANE    V_RX_LANE(1U)
45369 
45370 #define S_SE_CLR    21
45371 #define V_SE_CLR(x) ((x) << S_SE_CLR)
45372 #define F_SE_CLR    V_SE_CLR(1U)
45373 
45374 #define S_AN_ENA    17
45375 #define M_AN_ENA    0xfU
45376 #define V_AN_ENA(x) ((x) << S_AN_ENA)
45377 #define G_AN_ENA(x) (((x) >> S_AN_ENA) & M_AN_ENA)
45378 
45379 #define S_SD_RX_CLK_ENA    13
45380 #define M_SD_RX_CLK_ENA    0xfU
45381 #define V_SD_RX_CLK_ENA(x) ((x) << S_SD_RX_CLK_ENA)
45382 #define G_SD_RX_CLK_ENA(x) (((x) >> S_SD_RX_CLK_ENA) & M_SD_RX_CLK_ENA)
45383 
45384 #define S_SD_TX_CLK_ENA    9
45385 #define M_SD_TX_CLK_ENA    0xfU
45386 #define V_SD_TX_CLK_ENA(x) ((x) << S_SD_TX_CLK_ENA)
45387 #define G_SD_TX_CLK_ENA(x) (((x) >> S_SD_TX_CLK_ENA) & M_SD_TX_CLK_ENA)
45388 
45389 #define S_SGMIISEL    8
45390 #define V_SGMIISEL(x) ((x) << S_SGMIISEL)
45391 #define F_SGMIISEL    V_SGMIISEL(1U)
45392 
45393 #define S_HSSPLLSEL    4
45394 #define M_HSSPLLSEL    0xfU
45395 #define V_HSSPLLSEL(x) ((x) << S_HSSPLLSEL)
45396 #define G_HSSPLLSEL(x) (((x) >> S_HSSPLLSEL) & M_HSSPLLSEL)
45397 
45398 #define S_HSSC16C20SEL    0
45399 #define M_HSSC16C20SEL    0xfU
45400 #define V_HSSC16C20SEL(x) ((x) << S_HSSC16C20SEL)
45401 #define G_HSSC16C20SEL(x) (((x) >> S_HSSC16C20SEL) & M_HSSC16C20SEL)
45402 
45403 #define S_REF_CLK_SEL    30
45404 #define M_REF_CLK_SEL    0x3U
45405 #define V_REF_CLK_SEL(x) ((x) << S_REF_CLK_SEL)
45406 #define G_REF_CLK_SEL(x) (((x) >> S_REF_CLK_SEL) & M_REF_CLK_SEL)
45407 
45408 #define S_SGMII_SD_SIG_DET    29
45409 #define V_SGMII_SD_SIG_DET(x) ((x) << S_SGMII_SD_SIG_DET)
45410 #define F_SGMII_SD_SIG_DET    V_SGMII_SD_SIG_DET(1U)
45411 
45412 #define S_SGMII_SGPCS_ENA    28
45413 #define V_SGMII_SGPCS_ENA(x) ((x) << S_SGMII_SGPCS_ENA)
45414 #define F_SGMII_SGPCS_ENA    V_SGMII_SGPCS_ENA(1U)
45415 
45416 #define S_MAC_FPGA_PTP_PORT    26
45417 #define M_MAC_FPGA_PTP_PORT    0x3U
45418 #define V_MAC_FPGA_PTP_PORT(x) ((x) << S_MAC_FPGA_PTP_PORT)
45419 #define G_MAC_FPGA_PTP_PORT(x) (((x) >> S_MAC_FPGA_PTP_PORT) & M_MAC_FPGA_PTP_PORT)
45420 
45421 #define A_MAC_PORT_CFG2 0x818
45422 
45423 #define S_T5_AEC_PMA_TX_READY    4
45424 #define M_T5_AEC_PMA_TX_READY    0xfU
45425 #define V_T5_AEC_PMA_TX_READY(x) ((x) << S_T5_AEC_PMA_TX_READY)
45426 #define G_T5_AEC_PMA_TX_READY(x) (((x) >> S_T5_AEC_PMA_TX_READY) & M_T5_AEC_PMA_TX_READY)
45427 
45428 #define S_T5_AEC_PMA_RX_READY    0
45429 #define M_T5_AEC_PMA_RX_READY    0xfU
45430 #define V_T5_AEC_PMA_RX_READY(x) ((x) << S_T5_AEC_PMA_RX_READY)
45431 #define G_T5_AEC_PMA_RX_READY(x) (((x) >> S_T5_AEC_PMA_RX_READY) & M_T5_AEC_PMA_RX_READY)
45432 
45433 #define S_AN_DATA_CTL    19
45434 #define V_AN_DATA_CTL(x) ((x) << S_AN_DATA_CTL)
45435 #define F_AN_DATA_CTL    V_AN_DATA_CTL(1U)
45436 
45437 #define A_MAC_PORT_PKT_COUNT 0x81c
45438 #define A_MAC_PORT_CFG4 0x820
45439 
45440 #define S_AEC3_RX_WIDTH    14
45441 #define M_AEC3_RX_WIDTH    0x3U
45442 #define V_AEC3_RX_WIDTH(x) ((x) << S_AEC3_RX_WIDTH)
45443 #define G_AEC3_RX_WIDTH(x) (((x) >> S_AEC3_RX_WIDTH) & M_AEC3_RX_WIDTH)
45444 
45445 #define S_AEC2_RX_WIDTH    12
45446 #define M_AEC2_RX_WIDTH    0x3U
45447 #define V_AEC2_RX_WIDTH(x) ((x) << S_AEC2_RX_WIDTH)
45448 #define G_AEC2_RX_WIDTH(x) (((x) >> S_AEC2_RX_WIDTH) & M_AEC2_RX_WIDTH)
45449 
45450 #define S_AEC1_RX_WIDTH    10
45451 #define M_AEC1_RX_WIDTH    0x3U
45452 #define V_AEC1_RX_WIDTH(x) ((x) << S_AEC1_RX_WIDTH)
45453 #define G_AEC1_RX_WIDTH(x) (((x) >> S_AEC1_RX_WIDTH) & M_AEC1_RX_WIDTH)
45454 
45455 #define S_AEC0_RX_WIDTH    8
45456 #define M_AEC0_RX_WIDTH    0x3U
45457 #define V_AEC0_RX_WIDTH(x) ((x) << S_AEC0_RX_WIDTH)
45458 #define G_AEC0_RX_WIDTH(x) (((x) >> S_AEC0_RX_WIDTH) & M_AEC0_RX_WIDTH)
45459 
45460 #define S_AEC3_TX_WIDTH    6
45461 #define M_AEC3_TX_WIDTH    0x3U
45462 #define V_AEC3_TX_WIDTH(x) ((x) << S_AEC3_TX_WIDTH)
45463 #define G_AEC3_TX_WIDTH(x) (((x) >> S_AEC3_TX_WIDTH) & M_AEC3_TX_WIDTH)
45464 
45465 #define S_AEC2_TX_WIDTH    4
45466 #define M_AEC2_TX_WIDTH    0x3U
45467 #define V_AEC2_TX_WIDTH(x) ((x) << S_AEC2_TX_WIDTH)
45468 #define G_AEC2_TX_WIDTH(x) (((x) >> S_AEC2_TX_WIDTH) & M_AEC2_TX_WIDTH)
45469 
45470 #define S_AEC1_TX_WIDTH    2
45471 #define M_AEC1_TX_WIDTH    0x3U
45472 #define V_AEC1_TX_WIDTH(x) ((x) << S_AEC1_TX_WIDTH)
45473 #define G_AEC1_TX_WIDTH(x) (((x) >> S_AEC1_TX_WIDTH) & M_AEC1_TX_WIDTH)
45474 
45475 #define S_AEC0_TX_WIDTH    0
45476 #define M_AEC0_TX_WIDTH    0x3U
45477 #define V_AEC0_TX_WIDTH(x) ((x) << S_AEC0_TX_WIDTH)
45478 #define G_AEC0_TX_WIDTH(x) (((x) >> S_AEC0_TX_WIDTH) & M_AEC0_TX_WIDTH)
45479 
45480 #define A_MAC_PORT_MAGIC_MACID_LO 0x824
45481 #define A_MAC_PORT_MAGIC_MACID_HI 0x828
45482 #define A_MAC_PORT_MTIP_RESET_CTRL 0x82c
45483 
45484 #define S_AN_RESET_SD_TX_CLK    31
45485 #define V_AN_RESET_SD_TX_CLK(x) ((x) << S_AN_RESET_SD_TX_CLK)
45486 #define F_AN_RESET_SD_TX_CLK    V_AN_RESET_SD_TX_CLK(1U)
45487 
45488 #define S_AN_RESET_SD_RX_CLK    30
45489 #define V_AN_RESET_SD_RX_CLK(x) ((x) << S_AN_RESET_SD_RX_CLK)
45490 #define F_AN_RESET_SD_RX_CLK    V_AN_RESET_SD_RX_CLK(1U)
45491 
45492 #define S_SGMII_RESET_TX_CLK    29
45493 #define V_SGMII_RESET_TX_CLK(x) ((x) << S_SGMII_RESET_TX_CLK)
45494 #define F_SGMII_RESET_TX_CLK    V_SGMII_RESET_TX_CLK(1U)
45495 
45496 #define S_SGMII_RESET_RX_CLK    28
45497 #define V_SGMII_RESET_RX_CLK(x) ((x) << S_SGMII_RESET_RX_CLK)
45498 #define F_SGMII_RESET_RX_CLK    V_SGMII_RESET_RX_CLK(1U)
45499 
45500 #define S_SGMII_RESET_REF_CLK    27
45501 #define V_SGMII_RESET_REF_CLK(x) ((x) << S_SGMII_RESET_REF_CLK)
45502 #define F_SGMII_RESET_REF_CLK    V_SGMII_RESET_REF_CLK(1U)
45503 
45504 #define S_PCS10G_RESET_XFI_RXCLK    26
45505 #define V_PCS10G_RESET_XFI_RXCLK(x) ((x) << S_PCS10G_RESET_XFI_RXCLK)
45506 #define F_PCS10G_RESET_XFI_RXCLK    V_PCS10G_RESET_XFI_RXCLK(1U)
45507 
45508 #define S_PCS10G_RESET_XFI_TXCLK    25
45509 #define V_PCS10G_RESET_XFI_TXCLK(x) ((x) << S_PCS10G_RESET_XFI_TXCLK)
45510 #define F_PCS10G_RESET_XFI_TXCLK    V_PCS10G_RESET_XFI_TXCLK(1U)
45511 
45512 #define S_PCS10G_RESET_SD_TX_CLK    24
45513 #define V_PCS10G_RESET_SD_TX_CLK(x) ((x) << S_PCS10G_RESET_SD_TX_CLK)
45514 #define F_PCS10G_RESET_SD_TX_CLK    V_PCS10G_RESET_SD_TX_CLK(1U)
45515 
45516 #define S_PCS10G_RESET_SD_RX_CLK    23
45517 #define V_PCS10G_RESET_SD_RX_CLK(x) ((x) << S_PCS10G_RESET_SD_RX_CLK)
45518 #define F_PCS10G_RESET_SD_RX_CLK    V_PCS10G_RESET_SD_RX_CLK(1U)
45519 
45520 #define S_PCS40G_RESET_RXCLK    22
45521 #define V_PCS40G_RESET_RXCLK(x) ((x) << S_PCS40G_RESET_RXCLK)
45522 #define F_PCS40G_RESET_RXCLK    V_PCS40G_RESET_RXCLK(1U)
45523 
45524 #define S_PCS40G_RESET_SD_TX_CLK    21
45525 #define V_PCS40G_RESET_SD_TX_CLK(x) ((x) << S_PCS40G_RESET_SD_TX_CLK)
45526 #define F_PCS40G_RESET_SD_TX_CLK    V_PCS40G_RESET_SD_TX_CLK(1U)
45527 
45528 #define S_PCS40G_RESET_SD0_RX_CLK    20
45529 #define V_PCS40G_RESET_SD0_RX_CLK(x) ((x) << S_PCS40G_RESET_SD0_RX_CLK)
45530 #define F_PCS40G_RESET_SD0_RX_CLK    V_PCS40G_RESET_SD0_RX_CLK(1U)
45531 
45532 #define S_PCS40G_RESET_SD1_RX_CLK    19
45533 #define V_PCS40G_RESET_SD1_RX_CLK(x) ((x) << S_PCS40G_RESET_SD1_RX_CLK)
45534 #define F_PCS40G_RESET_SD1_RX_CLK    V_PCS40G_RESET_SD1_RX_CLK(1U)
45535 
45536 #define S_PCS40G_RESET_SD2_RX_CLK    18
45537 #define V_PCS40G_RESET_SD2_RX_CLK(x) ((x) << S_PCS40G_RESET_SD2_RX_CLK)
45538 #define F_PCS40G_RESET_SD2_RX_CLK    V_PCS40G_RESET_SD2_RX_CLK(1U)
45539 
45540 #define S_PCS40G_RESET_SD3_RX_CLK    17
45541 #define V_PCS40G_RESET_SD3_RX_CLK(x) ((x) << S_PCS40G_RESET_SD3_RX_CLK)
45542 #define F_PCS40G_RESET_SD3_RX_CLK    V_PCS40G_RESET_SD3_RX_CLK(1U)
45543 
45544 #define S_PCS100G_RESET_CGMII_RXCLK    16
45545 #define V_PCS100G_RESET_CGMII_RXCLK(x) ((x) << S_PCS100G_RESET_CGMII_RXCLK)
45546 #define F_PCS100G_RESET_CGMII_RXCLK    V_PCS100G_RESET_CGMII_RXCLK(1U)
45547 
45548 #define S_PCS100G_RESET_CGMII_TXCLK    15
45549 #define V_PCS100G_RESET_CGMII_TXCLK(x) ((x) << S_PCS100G_RESET_CGMII_TXCLK)
45550 #define F_PCS100G_RESET_CGMII_TXCLK    V_PCS100G_RESET_CGMII_TXCLK(1U)
45551 
45552 #define S_PCS100G_RESET_TX_CLK    14
45553 #define V_PCS100G_RESET_TX_CLK(x) ((x) << S_PCS100G_RESET_TX_CLK)
45554 #define F_PCS100G_RESET_TX_CLK    V_PCS100G_RESET_TX_CLK(1U)
45555 
45556 #define S_PCS100G_RESET_SD0_RX_CLK    13
45557 #define V_PCS100G_RESET_SD0_RX_CLK(x) ((x) << S_PCS100G_RESET_SD0_RX_CLK)
45558 #define F_PCS100G_RESET_SD0_RX_CLK    V_PCS100G_RESET_SD0_RX_CLK(1U)
45559 
45560 #define S_PCS100G_RESET_SD1_RX_CLK    12
45561 #define V_PCS100G_RESET_SD1_RX_CLK(x) ((x) << S_PCS100G_RESET_SD1_RX_CLK)
45562 #define F_PCS100G_RESET_SD1_RX_CLK    V_PCS100G_RESET_SD1_RX_CLK(1U)
45563 
45564 #define S_PCS100G_RESET_SD2_RX_CLK    11
45565 #define V_PCS100G_RESET_SD2_RX_CLK(x) ((x) << S_PCS100G_RESET_SD2_RX_CLK)
45566 #define F_PCS100G_RESET_SD2_RX_CLK    V_PCS100G_RESET_SD2_RX_CLK(1U)
45567 
45568 #define S_PCS100G_RESET_SD3_RX_CLK    10
45569 #define V_PCS100G_RESET_SD3_RX_CLK(x) ((x) << S_PCS100G_RESET_SD3_RX_CLK)
45570 #define F_PCS100G_RESET_SD3_RX_CLK    V_PCS100G_RESET_SD3_RX_CLK(1U)
45571 
45572 #define S_MAC40G100G_RESET_TXCLK    9
45573 #define V_MAC40G100G_RESET_TXCLK(x) ((x) << S_MAC40G100G_RESET_TXCLK)
45574 #define F_MAC40G100G_RESET_TXCLK    V_MAC40G100G_RESET_TXCLK(1U)
45575 
45576 #define S_MAC40G100G_RESET_RXCLK    8
45577 #define V_MAC40G100G_RESET_RXCLK(x) ((x) << S_MAC40G100G_RESET_RXCLK)
45578 #define F_MAC40G100G_RESET_RXCLK    V_MAC40G100G_RESET_RXCLK(1U)
45579 
45580 #define S_MAC40G100G_RESET_FF_TX_CLK    7
45581 #define V_MAC40G100G_RESET_FF_TX_CLK(x) ((x) << S_MAC40G100G_RESET_FF_TX_CLK)
45582 #define F_MAC40G100G_RESET_FF_TX_CLK    V_MAC40G100G_RESET_FF_TX_CLK(1U)
45583 
45584 #define S_MAC40G100G_RESET_FF_RX_CLK    6
45585 #define V_MAC40G100G_RESET_FF_RX_CLK(x) ((x) << S_MAC40G100G_RESET_FF_RX_CLK)
45586 #define F_MAC40G100G_RESET_FF_RX_CLK    V_MAC40G100G_RESET_FF_RX_CLK(1U)
45587 
45588 #define S_MAC40G100G_RESET_TS_CLK    5
45589 #define V_MAC40G100G_RESET_TS_CLK(x) ((x) << S_MAC40G100G_RESET_TS_CLK)
45590 #define F_MAC40G100G_RESET_TS_CLK    V_MAC40G100G_RESET_TS_CLK(1U)
45591 
45592 #define S_MAC1G10G_RESET_RXCLK    4
45593 #define V_MAC1G10G_RESET_RXCLK(x) ((x) << S_MAC1G10G_RESET_RXCLK)
45594 #define F_MAC1G10G_RESET_RXCLK    V_MAC1G10G_RESET_RXCLK(1U)
45595 
45596 #define S_MAC1G10G_RESET_TXCLK    3
45597 #define V_MAC1G10G_RESET_TXCLK(x) ((x) << S_MAC1G10G_RESET_TXCLK)
45598 #define F_MAC1G10G_RESET_TXCLK    V_MAC1G10G_RESET_TXCLK(1U)
45599 
45600 #define S_MAC1G10G_RESET_FF_RX_CLK    2
45601 #define V_MAC1G10G_RESET_FF_RX_CLK(x) ((x) << S_MAC1G10G_RESET_FF_RX_CLK)
45602 #define F_MAC1G10G_RESET_FF_RX_CLK    V_MAC1G10G_RESET_FF_RX_CLK(1U)
45603 
45604 #define S_MAC1G10G_RESET_FF_TX_CLK    1
45605 #define V_MAC1G10G_RESET_FF_TX_CLK(x) ((x) << S_MAC1G10G_RESET_FF_TX_CLK)
45606 #define F_MAC1G10G_RESET_FF_TX_CLK    V_MAC1G10G_RESET_FF_TX_CLK(1U)
45607 
45608 #define S_XGMII_CLK_RESET    0
45609 #define V_XGMII_CLK_RESET(x) ((x) << S_XGMII_CLK_RESET)
45610 #define F_XGMII_CLK_RESET    V_XGMII_CLK_RESET(1U)
45611 
45612 #define A_MAC_PORT_MTIP_GATE_CTRL 0x830
45613 
45614 #define S_AN_GATE_SD_TX_CLK    31
45615 #define V_AN_GATE_SD_TX_CLK(x) ((x) << S_AN_GATE_SD_TX_CLK)
45616 #define F_AN_GATE_SD_TX_CLK    V_AN_GATE_SD_TX_CLK(1U)
45617 
45618 #define S_AN_GATE_SD_RX_CLK    30
45619 #define V_AN_GATE_SD_RX_CLK(x) ((x) << S_AN_GATE_SD_RX_CLK)
45620 #define F_AN_GATE_SD_RX_CLK    V_AN_GATE_SD_RX_CLK(1U)
45621 
45622 #define S_SGMII_GATE_TX_CLK    29
45623 #define V_SGMII_GATE_TX_CLK(x) ((x) << S_SGMII_GATE_TX_CLK)
45624 #define F_SGMII_GATE_TX_CLK    V_SGMII_GATE_TX_CLK(1U)
45625 
45626 #define S_SGMII_GATE_RX_CLK    28
45627 #define V_SGMII_GATE_RX_CLK(x) ((x) << S_SGMII_GATE_RX_CLK)
45628 #define F_SGMII_GATE_RX_CLK    V_SGMII_GATE_RX_CLK(1U)
45629 
45630 #define S_SGMII_GATE_REF_CLK    27
45631 #define V_SGMII_GATE_REF_CLK(x) ((x) << S_SGMII_GATE_REF_CLK)
45632 #define F_SGMII_GATE_REF_CLK    V_SGMII_GATE_REF_CLK(1U)
45633 
45634 #define S_PCS10G_GATE_XFI_RXCLK    26
45635 #define V_PCS10G_GATE_XFI_RXCLK(x) ((x) << S_PCS10G_GATE_XFI_RXCLK)
45636 #define F_PCS10G_GATE_XFI_RXCLK    V_PCS10G_GATE_XFI_RXCLK(1U)
45637 
45638 #define S_PCS10G_GATE_XFI_TXCLK    25
45639 #define V_PCS10G_GATE_XFI_TXCLK(x) ((x) << S_PCS10G_GATE_XFI_TXCLK)
45640 #define F_PCS10G_GATE_XFI_TXCLK    V_PCS10G_GATE_XFI_TXCLK(1U)
45641 
45642 #define S_PCS10G_GATE_SD_TX_CLK    24
45643 #define V_PCS10G_GATE_SD_TX_CLK(x) ((x) << S_PCS10G_GATE_SD_TX_CLK)
45644 #define F_PCS10G_GATE_SD_TX_CLK    V_PCS10G_GATE_SD_TX_CLK(1U)
45645 
45646 #define S_PCS10G_GATE_SD_RX_CLK    23
45647 #define V_PCS10G_GATE_SD_RX_CLK(x) ((x) << S_PCS10G_GATE_SD_RX_CLK)
45648 #define F_PCS10G_GATE_SD_RX_CLK    V_PCS10G_GATE_SD_RX_CLK(1U)
45649 
45650 #define S_PCS40G_GATE_RXCLK    22
45651 #define V_PCS40G_GATE_RXCLK(x) ((x) << S_PCS40G_GATE_RXCLK)
45652 #define F_PCS40G_GATE_RXCLK    V_PCS40G_GATE_RXCLK(1U)
45653 
45654 #define S_PCS40G_GATE_SD_TX_CLK    21
45655 #define V_PCS40G_GATE_SD_TX_CLK(x) ((x) << S_PCS40G_GATE_SD_TX_CLK)
45656 #define F_PCS40G_GATE_SD_TX_CLK    V_PCS40G_GATE_SD_TX_CLK(1U)
45657 
45658 #define S_PCS40G_GATE_SD_RX_CLK    20
45659 #define V_PCS40G_GATE_SD_RX_CLK(x) ((x) << S_PCS40G_GATE_SD_RX_CLK)
45660 #define F_PCS40G_GATE_SD_RX_CLK    V_PCS40G_GATE_SD_RX_CLK(1U)
45661 
45662 #define S_PCS100G_GATE_CGMII_RXCLK    19
45663 #define V_PCS100G_GATE_CGMII_RXCLK(x) ((x) << S_PCS100G_GATE_CGMII_RXCLK)
45664 #define F_PCS100G_GATE_CGMII_RXCLK    V_PCS100G_GATE_CGMII_RXCLK(1U)
45665 
45666 #define S_PCS100G_GATE_CGMII_TXCLK    18
45667 #define V_PCS100G_GATE_CGMII_TXCLK(x) ((x) << S_PCS100G_GATE_CGMII_TXCLK)
45668 #define F_PCS100G_GATE_CGMII_TXCLK    V_PCS100G_GATE_CGMII_TXCLK(1U)
45669 
45670 #define S_PCS100G_GATE_TX_CLK    17
45671 #define V_PCS100G_GATE_TX_CLK(x) ((x) << S_PCS100G_GATE_TX_CLK)
45672 #define F_PCS100G_GATE_TX_CLK    V_PCS100G_GATE_TX_CLK(1U)
45673 
45674 #define S_PCS100G_GATE_SD_RX_CLK    16
45675 #define V_PCS100G_GATE_SD_RX_CLK(x) ((x) << S_PCS100G_GATE_SD_RX_CLK)
45676 #define F_PCS100G_GATE_SD_RX_CLK    V_PCS100G_GATE_SD_RX_CLK(1U)
45677 
45678 #define S_MAC40G100G_GATE_TXCLK    15
45679 #define V_MAC40G100G_GATE_TXCLK(x) ((x) << S_MAC40G100G_GATE_TXCLK)
45680 #define F_MAC40G100G_GATE_TXCLK    V_MAC40G100G_GATE_TXCLK(1U)
45681 
45682 #define S_MAC40G100G_GATE_RXCLK    14
45683 #define V_MAC40G100G_GATE_RXCLK(x) ((x) << S_MAC40G100G_GATE_RXCLK)
45684 #define F_MAC40G100G_GATE_RXCLK    V_MAC40G100G_GATE_RXCLK(1U)
45685 
45686 #define S_MAC40G100G_GATE_FF_TX_CLK    13
45687 #define V_MAC40G100G_GATE_FF_TX_CLK(x) ((x) << S_MAC40G100G_GATE_FF_TX_CLK)
45688 #define F_MAC40G100G_GATE_FF_TX_CLK    V_MAC40G100G_GATE_FF_TX_CLK(1U)
45689 
45690 #define S_MAC40G100G_GATE_FF_RX_CLK    12
45691 #define V_MAC40G100G_GATE_FF_RX_CLK(x) ((x) << S_MAC40G100G_GATE_FF_RX_CLK)
45692 #define F_MAC40G100G_GATE_FF_RX_CLK    V_MAC40G100G_GATE_FF_RX_CLK(1U)
45693 
45694 #define S_MAC40G100G_TS_CLK    11
45695 #define V_MAC40G100G_TS_CLK(x) ((x) << S_MAC40G100G_TS_CLK)
45696 #define F_MAC40G100G_TS_CLK    V_MAC40G100G_TS_CLK(1U)
45697 
45698 #define S_MAC1G10G_GATE_RXCLK    10
45699 #define V_MAC1G10G_GATE_RXCLK(x) ((x) << S_MAC1G10G_GATE_RXCLK)
45700 #define F_MAC1G10G_GATE_RXCLK    V_MAC1G10G_GATE_RXCLK(1U)
45701 
45702 #define S_MAC1G10G_GATE_TXCLK    9
45703 #define V_MAC1G10G_GATE_TXCLK(x) ((x) << S_MAC1G10G_GATE_TXCLK)
45704 #define F_MAC1G10G_GATE_TXCLK    V_MAC1G10G_GATE_TXCLK(1U)
45705 
45706 #define S_MAC1G10G_GATE_FF_RX_CLK    8
45707 #define V_MAC1G10G_GATE_FF_RX_CLK(x) ((x) << S_MAC1G10G_GATE_FF_RX_CLK)
45708 #define F_MAC1G10G_GATE_FF_RX_CLK    V_MAC1G10G_GATE_FF_RX_CLK(1U)
45709 
45710 #define S_MAC1G10G_GATE_FF_TX_CLK    7
45711 #define V_MAC1G10G_GATE_FF_TX_CLK(x) ((x) << S_MAC1G10G_GATE_FF_TX_CLK)
45712 #define F_MAC1G10G_GATE_FF_TX_CLK    V_MAC1G10G_GATE_FF_TX_CLK(1U)
45713 
45714 #define S_AEC_RX    6
45715 #define V_AEC_RX(x) ((x) << S_AEC_RX)
45716 #define F_AEC_RX    V_AEC_RX(1U)
45717 
45718 #define S_AEC_TX    5
45719 #define V_AEC_TX(x) ((x) << S_AEC_TX)
45720 #define F_AEC_TX    V_AEC_TX(1U)
45721 
45722 #define S_PCS100G_CLK_ENABLE    4
45723 #define V_PCS100G_CLK_ENABLE(x) ((x) << S_PCS100G_CLK_ENABLE)
45724 #define F_PCS100G_CLK_ENABLE    V_PCS100G_CLK_ENABLE(1U)
45725 
45726 #define S_PCS40G_CLK_ENABLE    3
45727 #define V_PCS40G_CLK_ENABLE(x) ((x) << S_PCS40G_CLK_ENABLE)
45728 #define F_PCS40G_CLK_ENABLE    V_PCS40G_CLK_ENABLE(1U)
45729 
45730 #define S_PCS10G_CLK_ENABLE    2
45731 #define V_PCS10G_CLK_ENABLE(x) ((x) << S_PCS10G_CLK_ENABLE)
45732 #define F_PCS10G_CLK_ENABLE    V_PCS10G_CLK_ENABLE(1U)
45733 
45734 #define S_PCS1G_CLK_ENABLE    1
45735 #define V_PCS1G_CLK_ENABLE(x) ((x) << S_PCS1G_CLK_ENABLE)
45736 #define F_PCS1G_CLK_ENABLE    V_PCS1G_CLK_ENABLE(1U)
45737 
45738 #define S_AN_CLK_ENABLE    0
45739 #define V_AN_CLK_ENABLE(x) ((x) << S_AN_CLK_ENABLE)
45740 #define F_AN_CLK_ENABLE    V_AN_CLK_ENABLE(1U)
45741 
45742 #define A_MAC_PORT_LINK_STATUS 0x834
45743 
45744 #define S_AN_DONE    6
45745 #define V_AN_DONE(x) ((x) << S_AN_DONE)
45746 #define F_AN_DONE    V_AN_DONE(1U)
45747 
45748 #define S_ALIGN_DONE    5
45749 #define V_ALIGN_DONE(x) ((x) << S_ALIGN_DONE)
45750 #define F_ALIGN_DONE    V_ALIGN_DONE(1U)
45751 
45752 #define S_BLOCK_LOCK    4
45753 #define V_BLOCK_LOCK(x) ((x) << S_BLOCK_LOCK)
45754 #define F_BLOCK_LOCK    V_BLOCK_LOCK(1U)
45755 
45756 #define S_HI_BER_ST    7
45757 #define V_HI_BER_ST(x) ((x) << S_HI_BER_ST)
45758 #define F_HI_BER_ST    V_HI_BER_ST(1U)
45759 
45760 #define S_AN_DONE_ST    6
45761 #define V_AN_DONE_ST(x) ((x) << S_AN_DONE_ST)
45762 #define F_AN_DONE_ST    V_AN_DONE_ST(1U)
45763 
45764 #define A_MAC_PORT_AEC_ADD_CTL_STAT_0 0x838
45765 
45766 #define S_AEC_SYS_LANE_TYPE_3    11
45767 #define V_AEC_SYS_LANE_TYPE_3(x) ((x) << S_AEC_SYS_LANE_TYPE_3)
45768 #define F_AEC_SYS_LANE_TYPE_3    V_AEC_SYS_LANE_TYPE_3(1U)
45769 
45770 #define S_AEC_SYS_LANE_TYPE_2    10
45771 #define V_AEC_SYS_LANE_TYPE_2(x) ((x) << S_AEC_SYS_LANE_TYPE_2)
45772 #define F_AEC_SYS_LANE_TYPE_2    V_AEC_SYS_LANE_TYPE_2(1U)
45773 
45774 #define S_AEC_SYS_LANE_TYPE_1    9
45775 #define V_AEC_SYS_LANE_TYPE_1(x) ((x) << S_AEC_SYS_LANE_TYPE_1)
45776 #define F_AEC_SYS_LANE_TYPE_1    V_AEC_SYS_LANE_TYPE_1(1U)
45777 
45778 #define S_AEC_SYS_LANE_TYPE_0    8
45779 #define V_AEC_SYS_LANE_TYPE_0(x) ((x) << S_AEC_SYS_LANE_TYPE_0)
45780 #define F_AEC_SYS_LANE_TYPE_0    V_AEC_SYS_LANE_TYPE_0(1U)
45781 
45782 #define S_AEC_SYS_LANE_SELECT_3    6
45783 #define M_AEC_SYS_LANE_SELECT_3    0x3U
45784 #define V_AEC_SYS_LANE_SELECT_3(x) ((x) << S_AEC_SYS_LANE_SELECT_3)
45785 #define G_AEC_SYS_LANE_SELECT_3(x) (((x) >> S_AEC_SYS_LANE_SELECT_3) & M_AEC_SYS_LANE_SELECT_3)
45786 
45787 #define S_AEC_SYS_LANE_SELECT_2    4
45788 #define M_AEC_SYS_LANE_SELECT_2    0x3U
45789 #define V_AEC_SYS_LANE_SELECT_2(x) ((x) << S_AEC_SYS_LANE_SELECT_2)
45790 #define G_AEC_SYS_LANE_SELECT_2(x) (((x) >> S_AEC_SYS_LANE_SELECT_2) & M_AEC_SYS_LANE_SELECT_2)
45791 
45792 #define S_AEC_SYS_LANE_SELECT_1    2
45793 #define M_AEC_SYS_LANE_SELECT_1    0x3U
45794 #define V_AEC_SYS_LANE_SELECT_1(x) ((x) << S_AEC_SYS_LANE_SELECT_1)
45795 #define G_AEC_SYS_LANE_SELECT_1(x) (((x) >> S_AEC_SYS_LANE_SELECT_1) & M_AEC_SYS_LANE_SELECT_1)
45796 
45797 #define S_AEC_SYS_LANE_SELECT_O    0
45798 #define M_AEC_SYS_LANE_SELECT_O    0x3U
45799 #define V_AEC_SYS_LANE_SELECT_O(x) ((x) << S_AEC_SYS_LANE_SELECT_O)
45800 #define G_AEC_SYS_LANE_SELECT_O(x) (((x) >> S_AEC_SYS_LANE_SELECT_O) & M_AEC_SYS_LANE_SELECT_O)
45801 
45802 #define A_MAC_PORT_AEC_ADD_CTL_STAT_1 0x83c
45803 
45804 #define S_AEC_RX_UNKNOWN_LANE_3    11
45805 #define V_AEC_RX_UNKNOWN_LANE_3(x) ((x) << S_AEC_RX_UNKNOWN_LANE_3)
45806 #define F_AEC_RX_UNKNOWN_LANE_3    V_AEC_RX_UNKNOWN_LANE_3(1U)
45807 
45808 #define S_AEC_RX_UNKNOWN_LANE_2    10
45809 #define V_AEC_RX_UNKNOWN_LANE_2(x) ((x) << S_AEC_RX_UNKNOWN_LANE_2)
45810 #define F_AEC_RX_UNKNOWN_LANE_2    V_AEC_RX_UNKNOWN_LANE_2(1U)
45811 
45812 #define S_AEC_RX_UNKNOWN_LANE_1    9
45813 #define V_AEC_RX_UNKNOWN_LANE_1(x) ((x) << S_AEC_RX_UNKNOWN_LANE_1)
45814 #define F_AEC_RX_UNKNOWN_LANE_1    V_AEC_RX_UNKNOWN_LANE_1(1U)
45815 
45816 #define S_AEC_RX_UNKNOWN_LANE_0    8
45817 #define V_AEC_RX_UNKNOWN_LANE_0(x) ((x) << S_AEC_RX_UNKNOWN_LANE_0)
45818 #define F_AEC_RX_UNKNOWN_LANE_0    V_AEC_RX_UNKNOWN_LANE_0(1U)
45819 
45820 #define S_AEC_RX_LANE_ID_3    6
45821 #define M_AEC_RX_LANE_ID_3    0x3U
45822 #define V_AEC_RX_LANE_ID_3(x) ((x) << S_AEC_RX_LANE_ID_3)
45823 #define G_AEC_RX_LANE_ID_3(x) (((x) >> S_AEC_RX_LANE_ID_3) & M_AEC_RX_LANE_ID_3)
45824 
45825 #define S_AEC_RX_LANE_ID_2    4
45826 #define M_AEC_RX_LANE_ID_2    0x3U
45827 #define V_AEC_RX_LANE_ID_2(x) ((x) << S_AEC_RX_LANE_ID_2)
45828 #define G_AEC_RX_LANE_ID_2(x) (((x) >> S_AEC_RX_LANE_ID_2) & M_AEC_RX_LANE_ID_2)
45829 
45830 #define S_AEC_RX_LANE_ID_1    2
45831 #define M_AEC_RX_LANE_ID_1    0x3U
45832 #define V_AEC_RX_LANE_ID_1(x) ((x) << S_AEC_RX_LANE_ID_1)
45833 #define G_AEC_RX_LANE_ID_1(x) (((x) >> S_AEC_RX_LANE_ID_1) & M_AEC_RX_LANE_ID_1)
45834 
45835 #define S_AEC_RX_LANE_ID_O    0
45836 #define M_AEC_RX_LANE_ID_O    0x3U
45837 #define V_AEC_RX_LANE_ID_O(x) ((x) << S_AEC_RX_LANE_ID_O)
45838 #define G_AEC_RX_LANE_ID_O(x) (((x) >> S_AEC_RX_LANE_ID_O) & M_AEC_RX_LANE_ID_O)
45839 
45840 #define A_MAC_PORT_AEC_XGMII_TIMER_LO_40G 0x840
45841 
45842 #define S_XGMII_CLK_IN_1MS_LO_40G    0
45843 #define M_XGMII_CLK_IN_1MS_LO_40G    0xffffU
45844 #define V_XGMII_CLK_IN_1MS_LO_40G(x) ((x) << S_XGMII_CLK_IN_1MS_LO_40G)
45845 #define G_XGMII_CLK_IN_1MS_LO_40G(x) (((x) >> S_XGMII_CLK_IN_1MS_LO_40G) & M_XGMII_CLK_IN_1MS_LO_40G)
45846 
45847 #define A_MAC_PORT_AEC_XGMII_TIMER_HI_40G 0x844
45848 
45849 #define S_XGMII_CLK_IN_1MS_HI_40G    0
45850 #define M_XGMII_CLK_IN_1MS_HI_40G    0xfU
45851 #define V_XGMII_CLK_IN_1MS_HI_40G(x) ((x) << S_XGMII_CLK_IN_1MS_HI_40G)
45852 #define G_XGMII_CLK_IN_1MS_HI_40G(x) (((x) >> S_XGMII_CLK_IN_1MS_HI_40G) & M_XGMII_CLK_IN_1MS_HI_40G)
45853 
45854 #define A_MAC_PORT_AEC_XGMII_TIMER_LO_100G 0x848
45855 
45856 #define S_XGMII_CLK_IN_1MS_LO_100G    0
45857 #define M_XGMII_CLK_IN_1MS_LO_100G    0xffffU
45858 #define V_XGMII_CLK_IN_1MS_LO_100G(x) ((x) << S_XGMII_CLK_IN_1MS_LO_100G)
45859 #define G_XGMII_CLK_IN_1MS_LO_100G(x) (((x) >> S_XGMII_CLK_IN_1MS_LO_100G) & M_XGMII_CLK_IN_1MS_LO_100G)
45860 
45861 #define A_MAC_PORT_AEC_XGMII_TIMER_HI_100G 0x84c
45862 
45863 #define S_XGMII_CLK_IN_1MS_HI_100G    0
45864 #define M_XGMII_CLK_IN_1MS_HI_100G    0xfU
45865 #define V_XGMII_CLK_IN_1MS_HI_100G(x) ((x) << S_XGMII_CLK_IN_1MS_HI_100G)
45866 #define G_XGMII_CLK_IN_1MS_HI_100G(x) (((x) >> S_XGMII_CLK_IN_1MS_HI_100G) & M_XGMII_CLK_IN_1MS_HI_100G)
45867 
45868 #define A_MAC_PORT_AEC_DEBUG_LO_0 0x850
45869 
45870 #define S_CTL_FSM_CUR_STATE    28
45871 #define M_CTL_FSM_CUR_STATE    0x7U
45872 #define V_CTL_FSM_CUR_STATE(x) ((x) << S_CTL_FSM_CUR_STATE)
45873 #define G_CTL_FSM_CUR_STATE(x) (((x) >> S_CTL_FSM_CUR_STATE) & M_CTL_FSM_CUR_STATE)
45874 
45875 #define S_CIN_FSM_CUR_STATE    26
45876 #define M_CIN_FSM_CUR_STATE    0x3U
45877 #define V_CIN_FSM_CUR_STATE(x) ((x) << S_CIN_FSM_CUR_STATE)
45878 #define G_CIN_FSM_CUR_STATE(x) (((x) >> S_CIN_FSM_CUR_STATE) & M_CIN_FSM_CUR_STATE)
45879 
45880 #define S_CRI_FSM_CUR_STATE    23
45881 #define M_CRI_FSM_CUR_STATE    0x7U
45882 #define V_CRI_FSM_CUR_STATE(x) ((x) << S_CRI_FSM_CUR_STATE)
45883 #define G_CRI_FSM_CUR_STATE(x) (((x) >> S_CRI_FSM_CUR_STATE) & M_CRI_FSM_CUR_STATE)
45884 
45885 #define S_CU_C3_ACK_VALUE    21
45886 #define M_CU_C3_ACK_VALUE    0x3U
45887 #define V_CU_C3_ACK_VALUE(x) ((x) << S_CU_C3_ACK_VALUE)
45888 #define G_CU_C3_ACK_VALUE(x) (((x) >> S_CU_C3_ACK_VALUE) & M_CU_C3_ACK_VALUE)
45889 
45890 #define S_CU_C2_ACK_VALUE    19
45891 #define M_CU_C2_ACK_VALUE    0x3U
45892 #define V_CU_C2_ACK_VALUE(x) ((x) << S_CU_C2_ACK_VALUE)
45893 #define G_CU_C2_ACK_VALUE(x) (((x) >> S_CU_C2_ACK_VALUE) & M_CU_C2_ACK_VALUE)
45894 
45895 #define S_CU_C1_ACK_VALUE    17
45896 #define M_CU_C1_ACK_VALUE    0x3U
45897 #define V_CU_C1_ACK_VALUE(x) ((x) << S_CU_C1_ACK_VALUE)
45898 #define G_CU_C1_ACK_VALUE(x) (((x) >> S_CU_C1_ACK_VALUE) & M_CU_C1_ACK_VALUE)
45899 
45900 #define S_CU_C0_ACK_VALUE    15
45901 #define M_CU_C0_ACK_VALUE    0x3U
45902 #define V_CU_C0_ACK_VALUE(x) ((x) << S_CU_C0_ACK_VALUE)
45903 #define G_CU_C0_ACK_VALUE(x) (((x) >> S_CU_C0_ACK_VALUE) & M_CU_C0_ACK_VALUE)
45904 
45905 #define S_CX_INIT    13
45906 #define V_CX_INIT(x) ((x) << S_CX_INIT)
45907 #define F_CX_INIT    V_CX_INIT(1U)
45908 
45909 #define S_CX_PRESET    12
45910 #define V_CX_PRESET(x) ((x) << S_CX_PRESET)
45911 #define F_CX_PRESET    V_CX_PRESET(1U)
45912 
45913 #define S_CUF_C3_UPDATE    9
45914 #define M_CUF_C3_UPDATE    0x3U
45915 #define V_CUF_C3_UPDATE(x) ((x) << S_CUF_C3_UPDATE)
45916 #define G_CUF_C3_UPDATE(x) (((x) >> S_CUF_C3_UPDATE) & M_CUF_C3_UPDATE)
45917 
45918 #define S_CUF_C2_UPDATE    7
45919 #define M_CUF_C2_UPDATE    0x3U
45920 #define V_CUF_C2_UPDATE(x) ((x) << S_CUF_C2_UPDATE)
45921 #define G_CUF_C2_UPDATE(x) (((x) >> S_CUF_C2_UPDATE) & M_CUF_C2_UPDATE)
45922 
45923 #define S_CUF_C1_UPDATE    5
45924 #define M_CUF_C1_UPDATE    0x3U
45925 #define V_CUF_C1_UPDATE(x) ((x) << S_CUF_C1_UPDATE)
45926 #define G_CUF_C1_UPDATE(x) (((x) >> S_CUF_C1_UPDATE) & M_CUF_C1_UPDATE)
45927 
45928 #define S_CUF_C0_UPDATE    3
45929 #define M_CUF_C0_UPDATE    0x3U
45930 #define V_CUF_C0_UPDATE(x) ((x) << S_CUF_C0_UPDATE)
45931 #define G_CUF_C0_UPDATE(x) (((x) >> S_CUF_C0_UPDATE) & M_CUF_C0_UPDATE)
45932 
45933 #define S_REG_FPH_ATTR_TXUPDAT_VALID    2
45934 #define V_REG_FPH_ATTR_TXUPDAT_VALID(x) ((x) << S_REG_FPH_ATTR_TXUPDAT_VALID)
45935 #define F_REG_FPH_ATTR_TXUPDAT_VALID    V_REG_FPH_ATTR_TXUPDAT_VALID(1U)
45936 
45937 #define S_REG_FPH_ATTR_TXSTAT_VALID    1
45938 #define V_REG_FPH_ATTR_TXSTAT_VALID(x) ((x) << S_REG_FPH_ATTR_TXSTAT_VALID)
45939 #define F_REG_FPH_ATTR_TXSTAT_VALID    V_REG_FPH_ATTR_TXSTAT_VALID(1U)
45940 
45941 #define S_REG_MAN_DEC_REQ    0
45942 #define V_REG_MAN_DEC_REQ(x) ((x) << S_REG_MAN_DEC_REQ)
45943 #define F_REG_MAN_DEC_REQ    V_REG_MAN_DEC_REQ(1U)
45944 
45945 #define A_MAC_PORT_AEC_DEBUG_HI_0 0x854
45946 
45947 #define S_FC_LSNA_    12
45948 #define V_FC_LSNA_(x) ((x) << S_FC_LSNA_)
45949 #define F_FC_LSNA_    V_FC_LSNA_(1U)
45950 
45951 #define S_CUF_C0_FSM_DEBUG    9
45952 #define M_CUF_C0_FSM_DEBUG    0x7U
45953 #define V_CUF_C0_FSM_DEBUG(x) ((x) << S_CUF_C0_FSM_DEBUG)
45954 #define G_CUF_C0_FSM_DEBUG(x) (((x) >> S_CUF_C0_FSM_DEBUG) & M_CUF_C0_FSM_DEBUG)
45955 
45956 #define S_CUF_C1_FSM_DEBUG    6
45957 #define M_CUF_C1_FSM_DEBUG    0x7U
45958 #define V_CUF_C1_FSM_DEBUG(x) ((x) << S_CUF_C1_FSM_DEBUG)
45959 #define G_CUF_C1_FSM_DEBUG(x) (((x) >> S_CUF_C1_FSM_DEBUG) & M_CUF_C1_FSM_DEBUG)
45960 
45961 #define S_CUF_C2_FSM_DEBUG    3
45962 #define M_CUF_C2_FSM_DEBUG    0x7U
45963 #define V_CUF_C2_FSM_DEBUG(x) ((x) << S_CUF_C2_FSM_DEBUG)
45964 #define G_CUF_C2_FSM_DEBUG(x) (((x) >> S_CUF_C2_FSM_DEBUG) & M_CUF_C2_FSM_DEBUG)
45965 
45966 #define S_LCK_FSM_CUR_STATE    0
45967 #define M_LCK_FSM_CUR_STATE    0x7U
45968 #define V_LCK_FSM_CUR_STATE(x) ((x) << S_LCK_FSM_CUR_STATE)
45969 #define G_LCK_FSM_CUR_STATE(x) (((x) >> S_LCK_FSM_CUR_STATE) & M_LCK_FSM_CUR_STATE)
45970 
45971 #define A_MAC_PORT_AEC_DEBUG_LO_1 0x858
45972 #define A_MAC_PORT_AEC_DEBUG_HI_1 0x85c
45973 #define A_MAC_PORT_AEC_DEBUG_LO_2 0x860
45974 #define A_MAC_PORT_AEC_DEBUG_HI_2 0x864
45975 #define A_MAC_PORT_AEC_DEBUG_LO_3 0x868
45976 #define A_MAC_PORT_AEC_DEBUG_HI_3 0x86c
45977 #define A_MAC_PORT_MAC_DEBUG_RO 0x870
45978 
45979 #define S_MAC40G100G_TX_UNDERFLOW    13
45980 #define V_MAC40G100G_TX_UNDERFLOW(x) ((x) << S_MAC40G100G_TX_UNDERFLOW)
45981 #define F_MAC40G100G_TX_UNDERFLOW    V_MAC40G100G_TX_UNDERFLOW(1U)
45982 
45983 #define S_MAC1G10G_MAGIC_IND    12
45984 #define V_MAC1G10G_MAGIC_IND(x) ((x) << S_MAC1G10G_MAGIC_IND)
45985 #define F_MAC1G10G_MAGIC_IND    V_MAC1G10G_MAGIC_IND(1U)
45986 
45987 #define S_MAC1G10G_FF_RX_EMPTY    11
45988 #define V_MAC1G10G_FF_RX_EMPTY(x) ((x) << S_MAC1G10G_FF_RX_EMPTY)
45989 #define F_MAC1G10G_FF_RX_EMPTY    V_MAC1G10G_FF_RX_EMPTY(1U)
45990 
45991 #define S_MAC1G10G_FF_TX_OVR_ERR    10
45992 #define V_MAC1G10G_FF_TX_OVR_ERR(x) ((x) << S_MAC1G10G_FF_TX_OVR_ERR)
45993 #define F_MAC1G10G_FF_TX_OVR_ERR    V_MAC1G10G_FF_TX_OVR_ERR(1U)
45994 
45995 #define S_MAC1G10G_IF_MODE_ENA    8
45996 #define M_MAC1G10G_IF_MODE_ENA    0x3U
45997 #define V_MAC1G10G_IF_MODE_ENA(x) ((x) << S_MAC1G10G_IF_MODE_ENA)
45998 #define G_MAC1G10G_IF_MODE_ENA(x) (((x) >> S_MAC1G10G_IF_MODE_ENA) & M_MAC1G10G_IF_MODE_ENA)
45999 
46000 #define S_MAC1G10G_MII_ENA_10    7
46001 #define V_MAC1G10G_MII_ENA_10(x) ((x) << S_MAC1G10G_MII_ENA_10)
46002 #define F_MAC1G10G_MII_ENA_10    V_MAC1G10G_MII_ENA_10(1U)
46003 
46004 #define S_MAC1G10G_PAUSE_ON    6
46005 #define V_MAC1G10G_PAUSE_ON(x) ((x) << S_MAC1G10G_PAUSE_ON)
46006 #define F_MAC1G10G_PAUSE_ON    V_MAC1G10G_PAUSE_ON(1U)
46007 
46008 #define S_MAC1G10G_PFC_MODE    5
46009 #define V_MAC1G10G_PFC_MODE(x) ((x) << S_MAC1G10G_PFC_MODE)
46010 #define F_MAC1G10G_PFC_MODE    V_MAC1G10G_PFC_MODE(1U)
46011 
46012 #define S_MAC1G10G_RX_SFD_O    4
46013 #define V_MAC1G10G_RX_SFD_O(x) ((x) << S_MAC1G10G_RX_SFD_O)
46014 #define F_MAC1G10G_RX_SFD_O    V_MAC1G10G_RX_SFD_O(1U)
46015 
46016 #define S_MAC1G10G_TX_EMPTY    3
46017 #define V_MAC1G10G_TX_EMPTY(x) ((x) << S_MAC1G10G_TX_EMPTY)
46018 #define F_MAC1G10G_TX_EMPTY    V_MAC1G10G_TX_EMPTY(1U)
46019 
46020 #define S_MAC1G10G_TX_SFD_O    2
46021 #define V_MAC1G10G_TX_SFD_O(x) ((x) << S_MAC1G10G_TX_SFD_O)
46022 #define F_MAC1G10G_TX_SFD_O    V_MAC1G10G_TX_SFD_O(1U)
46023 
46024 #define S_MAC1G10G_TX_TS_FRM_OUT    1
46025 #define V_MAC1G10G_TX_TS_FRM_OUT(x) ((x) << S_MAC1G10G_TX_TS_FRM_OUT)
46026 #define F_MAC1G10G_TX_TS_FRM_OUT    V_MAC1G10G_TX_TS_FRM_OUT(1U)
46027 
46028 #define S_MAC1G10G_TX_UNDERFLOW    0
46029 #define V_MAC1G10G_TX_UNDERFLOW(x) ((x) << S_MAC1G10G_TX_UNDERFLOW)
46030 #define F_MAC1G10G_TX_UNDERFLOW    V_MAC1G10G_TX_UNDERFLOW(1U)
46031 
46032 #define A_MAC_PORT_MAC_CTRL_RW 0x874
46033 
46034 #define S_MAC40G100G_FF_TX_PFC_XOFF    17
46035 #define M_MAC40G100G_FF_TX_PFC_XOFF    0xffU
46036 #define V_MAC40G100G_FF_TX_PFC_XOFF(x) ((x) << S_MAC40G100G_FF_TX_PFC_XOFF)
46037 #define G_MAC40G100G_FF_TX_PFC_XOFF(x) (((x) >> S_MAC40G100G_FF_TX_PFC_XOFF) & M_MAC40G100G_FF_TX_PFC_XOFF)
46038 
46039 #define S_MAC40G100G_TX_LOC_FAULT    16
46040 #define V_MAC40G100G_TX_LOC_FAULT(x) ((x) << S_MAC40G100G_TX_LOC_FAULT)
46041 #define F_MAC40G100G_TX_LOC_FAULT    V_MAC40G100G_TX_LOC_FAULT(1U)
46042 
46043 #define S_MAC40G100G_TX_REM_FAULT    15
46044 #define V_MAC40G100G_TX_REM_FAULT(x) ((x) << S_MAC40G100G_TX_REM_FAULT)
46045 #define F_MAC40G100G_TX_REM_FAULT    V_MAC40G100G_TX_REM_FAULT(1U)
46046 
46047 #define S_MAC40G_LOOP_BCK    14
46048 #define V_MAC40G_LOOP_BCK(x) ((x) << S_MAC40G_LOOP_BCK)
46049 #define F_MAC40G_LOOP_BCK    V_MAC40G_LOOP_BCK(1U)
46050 
46051 #define S_MAC1G10G_MAGIC_ENA    13
46052 #define V_MAC1G10G_MAGIC_ENA(x) ((x) << S_MAC1G10G_MAGIC_ENA)
46053 #define F_MAC1G10G_MAGIC_ENA    V_MAC1G10G_MAGIC_ENA(1U)
46054 
46055 #define S_MAC1G10G_IF_MODE_SET    11
46056 #define M_MAC1G10G_IF_MODE_SET    0x3U
46057 #define V_MAC1G10G_IF_MODE_SET(x) ((x) << S_MAC1G10G_IF_MODE_SET)
46058 #define G_MAC1G10G_IF_MODE_SET(x) (((x) >> S_MAC1G10G_IF_MODE_SET) & M_MAC1G10G_IF_MODE_SET)
46059 
46060 #define S_MAC1G10G_TX_LOC_FAULT    10
46061 #define V_MAC1G10G_TX_LOC_FAULT(x) ((x) << S_MAC1G10G_TX_LOC_FAULT)
46062 #define F_MAC1G10G_TX_LOC_FAULT    V_MAC1G10G_TX_LOC_FAULT(1U)
46063 
46064 #define S_MAC1G10G_TX_REM_FAULT    9
46065 #define V_MAC1G10G_TX_REM_FAULT(x) ((x) << S_MAC1G10G_TX_REM_FAULT)
46066 #define F_MAC1G10G_TX_REM_FAULT    V_MAC1G10G_TX_REM_FAULT(1U)
46067 
46068 #define S_MAC1G10G_XOFF_GEN    1
46069 #define M_MAC1G10G_XOFF_GEN    0xffU
46070 #define V_MAC1G10G_XOFF_GEN(x) ((x) << S_MAC1G10G_XOFF_GEN)
46071 #define G_MAC1G10G_XOFF_GEN(x) (((x) >> S_MAC1G10G_XOFF_GEN) & M_MAC1G10G_XOFF_GEN)
46072 
46073 #define S_MAC1G_LOOP_BCK    0
46074 #define V_MAC1G_LOOP_BCK(x) ((x) << S_MAC1G_LOOP_BCK)
46075 #define F_MAC1G_LOOP_BCK    V_MAC1G_LOOP_BCK(1U)
46076 
46077 #define A_MAC_PORT_PCS_DEBUG0_RO 0x878
46078 
46079 #define S_FPGA_LOCK    26
46080 #define M_FPGA_LOCK    0xfU
46081 #define V_FPGA_LOCK(x) ((x) << S_FPGA_LOCK)
46082 #define G_FPGA_LOCK(x) (((x) >> S_FPGA_LOCK) & M_FPGA_LOCK)
46083 
46084 #define S_T6_AN_DONE    25
46085 #define V_T6_AN_DONE(x) ((x) << S_T6_AN_DONE)
46086 #define F_T6_AN_DONE    V_T6_AN_DONE(1U)
46087 
46088 #define S_AN_INT    24
46089 #define V_AN_INT(x) ((x) << S_AN_INT)
46090 #define F_AN_INT    V_AN_INT(1U)
46091 
46092 #define S_AN_PCS_RX_CLK_ENA    23
46093 #define V_AN_PCS_RX_CLK_ENA(x) ((x) << S_AN_PCS_RX_CLK_ENA)
46094 #define F_AN_PCS_RX_CLK_ENA    V_AN_PCS_RX_CLK_ENA(1U)
46095 
46096 #define S_AN_PCS_TX_CLK_ENA    22
46097 #define V_AN_PCS_TX_CLK_ENA(x) ((x) << S_AN_PCS_TX_CLK_ENA)
46098 #define F_AN_PCS_TX_CLK_ENA    V_AN_PCS_TX_CLK_ENA(1U)
46099 
46100 #define S_AN_SELECT    17
46101 #define M_AN_SELECT    0x1fU
46102 #define V_AN_SELECT(x) ((x) << S_AN_SELECT)
46103 #define G_AN_SELECT(x) (((x) >> S_AN_SELECT) & M_AN_SELECT)
46104 
46105 #define S_AN_PROG    16
46106 #define V_AN_PROG(x) ((x) << S_AN_PROG)
46107 #define F_AN_PROG    V_AN_PROG(1U)
46108 
46109 #define S_PCS40G_BLOCK_LOCK    12
46110 #define M_PCS40G_BLOCK_LOCK    0xfU
46111 #define V_PCS40G_BLOCK_LOCK(x) ((x) << S_PCS40G_BLOCK_LOCK)
46112 #define G_PCS40G_BLOCK_LOCK(x) (((x) >> S_PCS40G_BLOCK_LOCK) & M_PCS40G_BLOCK_LOCK)
46113 
46114 #define S_PCS40G_BER_TIMER_DONE    11
46115 #define V_PCS40G_BER_TIMER_DONE(x) ((x) << S_PCS40G_BER_TIMER_DONE)
46116 #define F_PCS40G_BER_TIMER_DONE    V_PCS40G_BER_TIMER_DONE(1U)
46117 
46118 #define S_PCS10G_FEC_LOCKED    10
46119 #define V_PCS10G_FEC_LOCKED(x) ((x) << S_PCS10G_FEC_LOCKED)
46120 #define F_PCS10G_FEC_LOCKED    V_PCS10G_FEC_LOCKED(1U)
46121 
46122 #define S_PCS10G_BLOCK_LOCK    9
46123 #define V_PCS10G_BLOCK_LOCK(x) ((x) << S_PCS10G_BLOCK_LOCK)
46124 #define F_PCS10G_BLOCK_LOCK    V_PCS10G_BLOCK_LOCK(1U)
46125 
46126 #define S_SGMII_GMII_COL    8
46127 #define V_SGMII_GMII_COL(x) ((x) << S_SGMII_GMII_COL)
46128 #define F_SGMII_GMII_COL    V_SGMII_GMII_COL(1U)
46129 
46130 #define S_SGMII_GMII_CRS    7
46131 #define V_SGMII_GMII_CRS(x) ((x) << S_SGMII_GMII_CRS)
46132 #define F_SGMII_GMII_CRS    V_SGMII_GMII_CRS(1U)
46133 
46134 #define S_SGMII_SD_LOOPBACK    6
46135 #define V_SGMII_SD_LOOPBACK(x) ((x) << S_SGMII_SD_LOOPBACK)
46136 #define F_SGMII_SD_LOOPBACK    V_SGMII_SD_LOOPBACK(1U)
46137 
46138 #define S_SGMII_SG_AN_DONE    5
46139 #define V_SGMII_SG_AN_DONE(x) ((x) << S_SGMII_SG_AN_DONE)
46140 #define F_SGMII_SG_AN_DONE    V_SGMII_SG_AN_DONE(1U)
46141 
46142 #define S_SGMII_SG_HD    4
46143 #define V_SGMII_SG_HD(x) ((x) << S_SGMII_SG_HD)
46144 #define F_SGMII_SG_HD    V_SGMII_SG_HD(1U)
46145 
46146 #define S_SGMII_SG_PAGE_RX    3
46147 #define V_SGMII_SG_PAGE_RX(x) ((x) << S_SGMII_SG_PAGE_RX)
46148 #define F_SGMII_SG_PAGE_RX    V_SGMII_SG_PAGE_RX(1U)
46149 
46150 #define S_SGMII_SG_RX_SYNC    2
46151 #define V_SGMII_SG_RX_SYNC(x) ((x) << S_SGMII_SG_RX_SYNC)
46152 #define F_SGMII_SG_RX_SYNC    V_SGMII_SG_RX_SYNC(1U)
46153 
46154 #define S_SGMII_SG_SPEED    0
46155 #define M_SGMII_SG_SPEED    0x3U
46156 #define V_SGMII_SG_SPEED(x) ((x) << S_SGMII_SG_SPEED)
46157 #define G_SGMII_SG_SPEED(x) (((x) >> S_SGMII_SG_SPEED) & M_SGMII_SG_SPEED)
46158 
46159 #define A_MAC_PORT_PCS_CTRL_RW 0x87c
46160 
46161 #define S_TX_LI_FAULT    31
46162 #define V_TX_LI_FAULT(x) ((x) << S_TX_LI_FAULT)
46163 #define F_TX_LI_FAULT    V_TX_LI_FAULT(1U)
46164 
46165 #define S_T6_PAD    30
46166 #define V_T6_PAD(x) ((x) << S_T6_PAD)
46167 #define F_T6_PAD    V_T6_PAD(1U)
46168 
46169 #define S_BLK_STB_VAL    22
46170 #define M_BLK_STB_VAL    0xffU
46171 #define V_BLK_STB_VAL(x) ((x) << S_BLK_STB_VAL)
46172 #define G_BLK_STB_VAL(x) (((x) >> S_BLK_STB_VAL) & M_BLK_STB_VAL)
46173 
46174 #define S_DEBUG_SEL    18
46175 #define M_DEBUG_SEL    0xfU
46176 #define V_DEBUG_SEL(x) ((x) << S_DEBUG_SEL)
46177 #define G_DEBUG_SEL(x) (((x) >> S_DEBUG_SEL) & M_DEBUG_SEL)
46178 
46179 #define S_SGMII_LOOP    15
46180 #define M_SGMII_LOOP    0x7U
46181 #define V_SGMII_LOOP(x) ((x) << S_SGMII_LOOP)
46182 #define G_SGMII_LOOP(x) (((x) >> S_SGMII_LOOP) & M_SGMII_LOOP)
46183 
46184 #define S_AN_DIS_TIMER    14
46185 #define V_AN_DIS_TIMER(x) ((x) << S_AN_DIS_TIMER)
46186 #define F_AN_DIS_TIMER    V_AN_DIS_TIMER(1U)
46187 
46188 #define S_PCS100G_BER_TIMER_SHORT    13
46189 #define V_PCS100G_BER_TIMER_SHORT(x) ((x) << S_PCS100G_BER_TIMER_SHORT)
46190 #define F_PCS100G_BER_TIMER_SHORT    V_PCS100G_BER_TIMER_SHORT(1U)
46191 
46192 #define S_PCS100G_TX_LANE_THRESH    9
46193 #define M_PCS100G_TX_LANE_THRESH    0xfU
46194 #define V_PCS100G_TX_LANE_THRESH(x) ((x) << S_PCS100G_TX_LANE_THRESH)
46195 #define G_PCS100G_TX_LANE_THRESH(x) (((x) >> S_PCS100G_TX_LANE_THRESH) & M_PCS100G_TX_LANE_THRESH)
46196 
46197 #define S_PCS100G_VL_INTVL    8
46198 #define V_PCS100G_VL_INTVL(x) ((x) << S_PCS100G_VL_INTVL)
46199 #define F_PCS100G_VL_INTVL    V_PCS100G_VL_INTVL(1U)
46200 
46201 #define S_SGMII_TX_LANE_CKMULT    4
46202 #define M_SGMII_TX_LANE_CKMULT    0x7U
46203 #define V_SGMII_TX_LANE_CKMULT(x) ((x) << S_SGMII_TX_LANE_CKMULT)
46204 #define G_SGMII_TX_LANE_CKMULT(x) (((x) >> S_SGMII_TX_LANE_CKMULT) & M_SGMII_TX_LANE_CKMULT)
46205 
46206 #define S_SGMII_TX_LANE_THRESH    0
46207 #define M_SGMII_TX_LANE_THRESH    0xfU
46208 #define V_SGMII_TX_LANE_THRESH(x) ((x) << S_SGMII_TX_LANE_THRESH)
46209 #define G_SGMII_TX_LANE_THRESH(x) (((x) >> S_SGMII_TX_LANE_THRESH) & M_SGMII_TX_LANE_THRESH)
46210 
46211 #define A_MAC_PORT_PCS_DEBUG1_RO 0x880
46212 
46213 #define S_PCS100G_ALIGN_LOCK    21
46214 #define V_PCS100G_ALIGN_LOCK(x) ((x) << S_PCS100G_ALIGN_LOCK)
46215 #define F_PCS100G_ALIGN_LOCK    V_PCS100G_ALIGN_LOCK(1U)
46216 
46217 #define S_PCS100G_BER_TIMER_DONE    20
46218 #define V_PCS100G_BER_TIMER_DONE(x) ((x) << S_PCS100G_BER_TIMER_DONE)
46219 #define F_PCS100G_BER_TIMER_DONE    V_PCS100G_BER_TIMER_DONE(1U)
46220 
46221 #define S_PCS100G_BLOCK_LOCK    0
46222 #define M_PCS100G_BLOCK_LOCK    0xfffffU
46223 #define V_PCS100G_BLOCK_LOCK(x) ((x) << S_PCS100G_BLOCK_LOCK)
46224 #define G_PCS100G_BLOCK_LOCK(x) (((x) >> S_PCS100G_BLOCK_LOCK) & M_PCS100G_BLOCK_LOCK)
46225 
46226 #define A_MAC_PORT_PERR_INT_EN_100G 0x884
46227 
46228 #define S_PERR_RX_FEC100G_DLY    29
46229 #define V_PERR_RX_FEC100G_DLY(x) ((x) << S_PERR_RX_FEC100G_DLY)
46230 #define F_PERR_RX_FEC100G_DLY    V_PERR_RX_FEC100G_DLY(1U)
46231 
46232 #define S_PERR_RX_FEC100G    28
46233 #define V_PERR_RX_FEC100G(x) ((x) << S_PERR_RX_FEC100G)
46234 #define F_PERR_RX_FEC100G    V_PERR_RX_FEC100G(1U)
46235 
46236 #define S_PERR_RX3_FEC100G_DK    27
46237 #define V_PERR_RX3_FEC100G_DK(x) ((x) << S_PERR_RX3_FEC100G_DK)
46238 #define F_PERR_RX3_FEC100G_DK    V_PERR_RX3_FEC100G_DK(1U)
46239 
46240 #define S_PERR_RX2_FEC100G_DK    26
46241 #define V_PERR_RX2_FEC100G_DK(x) ((x) << S_PERR_RX2_FEC100G_DK)
46242 #define F_PERR_RX2_FEC100G_DK    V_PERR_RX2_FEC100G_DK(1U)
46243 
46244 #define S_PERR_RX1_FEC100G_DK    25
46245 #define V_PERR_RX1_FEC100G_DK(x) ((x) << S_PERR_RX1_FEC100G_DK)
46246 #define F_PERR_RX1_FEC100G_DK    V_PERR_RX1_FEC100G_DK(1U)
46247 
46248 #define S_PERR_RX0_FEC100G_DK    24
46249 #define V_PERR_RX0_FEC100G_DK(x) ((x) << S_PERR_RX0_FEC100G_DK)
46250 #define F_PERR_RX0_FEC100G_DK    V_PERR_RX0_FEC100G_DK(1U)
46251 
46252 #define S_PERR_TX3_PCS100G    23
46253 #define V_PERR_TX3_PCS100G(x) ((x) << S_PERR_TX3_PCS100G)
46254 #define F_PERR_TX3_PCS100G    V_PERR_TX3_PCS100G(1U)
46255 
46256 #define S_PERR_TX2_PCS100G    22
46257 #define V_PERR_TX2_PCS100G(x) ((x) << S_PERR_TX2_PCS100G)
46258 #define F_PERR_TX2_PCS100G    V_PERR_TX2_PCS100G(1U)
46259 
46260 #define S_PERR_TX1_PCS100G    21
46261 #define V_PERR_TX1_PCS100G(x) ((x) << S_PERR_TX1_PCS100G)
46262 #define F_PERR_TX1_PCS100G    V_PERR_TX1_PCS100G(1U)
46263 
46264 #define S_PERR_TX0_PCS100G    20
46265 #define V_PERR_TX0_PCS100G(x) ((x) << S_PERR_TX0_PCS100G)
46266 #define F_PERR_TX0_PCS100G    V_PERR_TX0_PCS100G(1U)
46267 
46268 #define S_PERR_RX19_PCS100G    19
46269 #define V_PERR_RX19_PCS100G(x) ((x) << S_PERR_RX19_PCS100G)
46270 #define F_PERR_RX19_PCS100G    V_PERR_RX19_PCS100G(1U)
46271 
46272 #define S_PERR_RX18_PCS100G    18
46273 #define V_PERR_RX18_PCS100G(x) ((x) << S_PERR_RX18_PCS100G)
46274 #define F_PERR_RX18_PCS100G    V_PERR_RX18_PCS100G(1U)
46275 
46276 #define S_PERR_RX17_PCS100G    17
46277 #define V_PERR_RX17_PCS100G(x) ((x) << S_PERR_RX17_PCS100G)
46278 #define F_PERR_RX17_PCS100G    V_PERR_RX17_PCS100G(1U)
46279 
46280 #define S_PERR_RX16_PCS100G    16
46281 #define V_PERR_RX16_PCS100G(x) ((x) << S_PERR_RX16_PCS100G)
46282 #define F_PERR_RX16_PCS100G    V_PERR_RX16_PCS100G(1U)
46283 
46284 #define S_PERR_RX15_PCS100G    15
46285 #define V_PERR_RX15_PCS100G(x) ((x) << S_PERR_RX15_PCS100G)
46286 #define F_PERR_RX15_PCS100G    V_PERR_RX15_PCS100G(1U)
46287 
46288 #define S_PERR_RX14_PCS100G    14
46289 #define V_PERR_RX14_PCS100G(x) ((x) << S_PERR_RX14_PCS100G)
46290 #define F_PERR_RX14_PCS100G    V_PERR_RX14_PCS100G(1U)
46291 
46292 #define S_PERR_RX13_PCS100G    13
46293 #define V_PERR_RX13_PCS100G(x) ((x) << S_PERR_RX13_PCS100G)
46294 #define F_PERR_RX13_PCS100G    V_PERR_RX13_PCS100G(1U)
46295 
46296 #define S_PERR_RX12_PCS100G    12
46297 #define V_PERR_RX12_PCS100G(x) ((x) << S_PERR_RX12_PCS100G)
46298 #define F_PERR_RX12_PCS100G    V_PERR_RX12_PCS100G(1U)
46299 
46300 #define S_PERR_RX11_PCS100G    11
46301 #define V_PERR_RX11_PCS100G(x) ((x) << S_PERR_RX11_PCS100G)
46302 #define F_PERR_RX11_PCS100G    V_PERR_RX11_PCS100G(1U)
46303 
46304 #define S_PERR_RX10_PCS100G    10
46305 #define V_PERR_RX10_PCS100G(x) ((x) << S_PERR_RX10_PCS100G)
46306 #define F_PERR_RX10_PCS100G    V_PERR_RX10_PCS100G(1U)
46307 
46308 #define S_PERR_RX9_PCS100G    9
46309 #define V_PERR_RX9_PCS100G(x) ((x) << S_PERR_RX9_PCS100G)
46310 #define F_PERR_RX9_PCS100G    V_PERR_RX9_PCS100G(1U)
46311 
46312 #define S_PERR_RX8_PCS100G    8
46313 #define V_PERR_RX8_PCS100G(x) ((x) << S_PERR_RX8_PCS100G)
46314 #define F_PERR_RX8_PCS100G    V_PERR_RX8_PCS100G(1U)
46315 
46316 #define S_PERR_RX7_PCS100G    7
46317 #define V_PERR_RX7_PCS100G(x) ((x) << S_PERR_RX7_PCS100G)
46318 #define F_PERR_RX7_PCS100G    V_PERR_RX7_PCS100G(1U)
46319 
46320 #define S_PERR_RX6_PCS100G    6
46321 #define V_PERR_RX6_PCS100G(x) ((x) << S_PERR_RX6_PCS100G)
46322 #define F_PERR_RX6_PCS100G    V_PERR_RX6_PCS100G(1U)
46323 
46324 #define S_PERR_RX5_PCS100G    5
46325 #define V_PERR_RX5_PCS100G(x) ((x) << S_PERR_RX5_PCS100G)
46326 #define F_PERR_RX5_PCS100G    V_PERR_RX5_PCS100G(1U)
46327 
46328 #define S_PERR_RX4_PCS100G    4
46329 #define V_PERR_RX4_PCS100G(x) ((x) << S_PERR_RX4_PCS100G)
46330 #define F_PERR_RX4_PCS100G    V_PERR_RX4_PCS100G(1U)
46331 
46332 #define S_PERR_RX3_PCS100G    3
46333 #define V_PERR_RX3_PCS100G(x) ((x) << S_PERR_RX3_PCS100G)
46334 #define F_PERR_RX3_PCS100G    V_PERR_RX3_PCS100G(1U)
46335 
46336 #define S_PERR_RX2_PCS100G    2
46337 #define V_PERR_RX2_PCS100G(x) ((x) << S_PERR_RX2_PCS100G)
46338 #define F_PERR_RX2_PCS100G    V_PERR_RX2_PCS100G(1U)
46339 
46340 #define S_PERR_RX1_PCS100G    1
46341 #define V_PERR_RX1_PCS100G(x) ((x) << S_PERR_RX1_PCS100G)
46342 #define F_PERR_RX1_PCS100G    V_PERR_RX1_PCS100G(1U)
46343 
46344 #define S_PERR_RX0_PCS100G    0
46345 #define V_PERR_RX0_PCS100G(x) ((x) << S_PERR_RX0_PCS100G)
46346 #define F_PERR_RX0_PCS100G    V_PERR_RX0_PCS100G(1U)
46347 
46348 #define A_MAC_PORT_PERR_INT_CAUSE_100G 0x888
46349 #define A_MAC_PORT_PERR_ENABLE_100G 0x88c
46350 #define A_MAC_PORT_MAC_STAT_DEBUG 0x890
46351 #define A_MAC_PORT_MAC_25G_50G_AM0 0x894
46352 #define A_MAC_PORT_MAC_25G_50G_AM1 0x898
46353 #define A_MAC_PORT_MAC_25G_50G_AM2 0x89c
46354 #define A_MAC_PORT_MAC_25G_50G_AM3 0x8a0
46355 #define A_MAC_PORT_MAC_AN_STATE_STATUS 0x8a4
46356 #define A_MAC_PORT_EPIO_DATA0 0x8c0
46357 #define A_MAC_PORT_EPIO_DATA1 0x8c4
46358 #define A_MAC_PORT_EPIO_DATA2 0x8c8
46359 #define A_MAC_PORT_EPIO_DATA3 0x8cc
46360 #define A_MAC_PORT_EPIO_OP 0x8d0
46361 #define A_MAC_PORT_WOL_STATUS 0x8d4
46362 #define A_MAC_PORT_INT_EN 0x8d8
46363 
46364 #define S_TX_TS_AVAIL    29
46365 #define V_TX_TS_AVAIL(x) ((x) << S_TX_TS_AVAIL)
46366 #define F_TX_TS_AVAIL    V_TX_TS_AVAIL(1U)
46367 
46368 #define S_AN_PAGE_RCVD    2
46369 #define V_AN_PAGE_RCVD(x) ((x) << S_AN_PAGE_RCVD)
46370 #define F_AN_PAGE_RCVD    V_AN_PAGE_RCVD(1U)
46371 
46372 #define S_PPS    30
46373 #define V_PPS(x) ((x) << S_PPS)
46374 #define F_PPS    V_PPS(1U)
46375 
46376 #define S_SINGLE_ALARM    28
46377 #define V_SINGLE_ALARM(x) ((x) << S_SINGLE_ALARM)
46378 #define F_SINGLE_ALARM    V_SINGLE_ALARM(1U)
46379 
46380 #define S_PERIODIC_ALARM    27
46381 #define V_PERIODIC_ALARM(x) ((x) << S_PERIODIC_ALARM)
46382 #define F_PERIODIC_ALARM    V_PERIODIC_ALARM(1U)
46383 
46384 #define A_MAC_PORT_INT_CAUSE 0x8dc
46385 #define A_MAC_PORT_PERR_INT_EN 0x8e0
46386 
46387 #define S_PERR_PKT_RAM    24
46388 #define V_PERR_PKT_RAM(x) ((x) << S_PERR_PKT_RAM)
46389 #define F_PERR_PKT_RAM    V_PERR_PKT_RAM(1U)
46390 
46391 #define S_PERR_MASK_RAM    23
46392 #define V_PERR_MASK_RAM(x) ((x) << S_PERR_MASK_RAM)
46393 #define F_PERR_MASK_RAM    V_PERR_MASK_RAM(1U)
46394 
46395 #define S_PERR_CRC_RAM    22
46396 #define V_PERR_CRC_RAM(x) ((x) << S_PERR_CRC_RAM)
46397 #define F_PERR_CRC_RAM    V_PERR_CRC_RAM(1U)
46398 
46399 #define S_RX_DFF_SEG0    21
46400 #define V_RX_DFF_SEG0(x) ((x) << S_RX_DFF_SEG0)
46401 #define F_RX_DFF_SEG0    V_RX_DFF_SEG0(1U)
46402 
46403 #define S_RX_SFF_SEG0    20
46404 #define V_RX_SFF_SEG0(x) ((x) << S_RX_SFF_SEG0)
46405 #define F_RX_SFF_SEG0    V_RX_SFF_SEG0(1U)
46406 
46407 #define S_RX_DFF_MAC10    19
46408 #define V_RX_DFF_MAC10(x) ((x) << S_RX_DFF_MAC10)
46409 #define F_RX_DFF_MAC10    V_RX_DFF_MAC10(1U)
46410 
46411 #define S_RX_SFF_MAC10    18
46412 #define V_RX_SFF_MAC10(x) ((x) << S_RX_SFF_MAC10)
46413 #define F_RX_SFF_MAC10    V_RX_SFF_MAC10(1U)
46414 
46415 #define S_TX_DFF_SEG0    17
46416 #define V_TX_DFF_SEG0(x) ((x) << S_TX_DFF_SEG0)
46417 #define F_TX_DFF_SEG0    V_TX_DFF_SEG0(1U)
46418 
46419 #define S_TX_SFF_SEG0    16
46420 #define V_TX_SFF_SEG0(x) ((x) << S_TX_SFF_SEG0)
46421 #define F_TX_SFF_SEG0    V_TX_SFF_SEG0(1U)
46422 
46423 #define S_TX_DFF_MAC10    15
46424 #define V_TX_DFF_MAC10(x) ((x) << S_TX_DFF_MAC10)
46425 #define F_TX_DFF_MAC10    V_TX_DFF_MAC10(1U)
46426 
46427 #define S_TX_SFF_MAC10    14
46428 #define V_TX_SFF_MAC10(x) ((x) << S_TX_SFF_MAC10)
46429 #define F_TX_SFF_MAC10    V_TX_SFF_MAC10(1U)
46430 
46431 #define S_RX_STATS    13
46432 #define V_RX_STATS(x) ((x) << S_RX_STATS)
46433 #define F_RX_STATS    V_RX_STATS(1U)
46434 
46435 #define S_TX_STATS    12
46436 #define V_TX_STATS(x) ((x) << S_TX_STATS)
46437 #define F_TX_STATS    V_TX_STATS(1U)
46438 
46439 #define S_PERR3_RX_MIX    11
46440 #define V_PERR3_RX_MIX(x) ((x) << S_PERR3_RX_MIX)
46441 #define F_PERR3_RX_MIX    V_PERR3_RX_MIX(1U)
46442 
46443 #define S_PERR3_RX_SD    10
46444 #define V_PERR3_RX_SD(x) ((x) << S_PERR3_RX_SD)
46445 #define F_PERR3_RX_SD    V_PERR3_RX_SD(1U)
46446 
46447 #define S_PERR3_TX    9
46448 #define V_PERR3_TX(x) ((x) << S_PERR3_TX)
46449 #define F_PERR3_TX    V_PERR3_TX(1U)
46450 
46451 #define S_PERR2_RX_MIX    8
46452 #define V_PERR2_RX_MIX(x) ((x) << S_PERR2_RX_MIX)
46453 #define F_PERR2_RX_MIX    V_PERR2_RX_MIX(1U)
46454 
46455 #define S_PERR2_RX_SD    7
46456 #define V_PERR2_RX_SD(x) ((x) << S_PERR2_RX_SD)
46457 #define F_PERR2_RX_SD    V_PERR2_RX_SD(1U)
46458 
46459 #define S_PERR2_TX    6
46460 #define V_PERR2_TX(x) ((x) << S_PERR2_TX)
46461 #define F_PERR2_TX    V_PERR2_TX(1U)
46462 
46463 #define S_PERR1_RX_MIX    5
46464 #define V_PERR1_RX_MIX(x) ((x) << S_PERR1_RX_MIX)
46465 #define F_PERR1_RX_MIX    V_PERR1_RX_MIX(1U)
46466 
46467 #define S_PERR1_RX_SD    4
46468 #define V_PERR1_RX_SD(x) ((x) << S_PERR1_RX_SD)
46469 #define F_PERR1_RX_SD    V_PERR1_RX_SD(1U)
46470 
46471 #define S_PERR1_TX    3
46472 #define V_PERR1_TX(x) ((x) << S_PERR1_TX)
46473 #define F_PERR1_TX    V_PERR1_TX(1U)
46474 
46475 #define S_PERR0_RX_MIX    2
46476 #define V_PERR0_RX_MIX(x) ((x) << S_PERR0_RX_MIX)
46477 #define F_PERR0_RX_MIX    V_PERR0_RX_MIX(1U)
46478 
46479 #define S_PERR0_RX_SD    1
46480 #define V_PERR0_RX_SD(x) ((x) << S_PERR0_RX_SD)
46481 #define F_PERR0_RX_SD    V_PERR0_RX_SD(1U)
46482 
46483 #define S_PERR0_TX    0
46484 #define V_PERR0_TX(x) ((x) << S_PERR0_TX)
46485 #define F_PERR0_TX    V_PERR0_TX(1U)
46486 
46487 #define S_T6_PERR_PKT_RAM    31
46488 #define V_T6_PERR_PKT_RAM(x) ((x) << S_T6_PERR_PKT_RAM)
46489 #define F_T6_PERR_PKT_RAM    V_T6_PERR_PKT_RAM(1U)
46490 
46491 #define S_T6_PERR_MASK_RAM    30
46492 #define V_T6_PERR_MASK_RAM(x) ((x) << S_T6_PERR_MASK_RAM)
46493 #define F_T6_PERR_MASK_RAM    V_T6_PERR_MASK_RAM(1U)
46494 
46495 #define S_T6_PERR_CRC_RAM    29
46496 #define V_T6_PERR_CRC_RAM(x) ((x) << S_T6_PERR_CRC_RAM)
46497 #define F_T6_PERR_CRC_RAM    V_T6_PERR_CRC_RAM(1U)
46498 
46499 #define S_RX_MAC40G    28
46500 #define V_RX_MAC40G(x) ((x) << S_RX_MAC40G)
46501 #define F_RX_MAC40G    V_RX_MAC40G(1U)
46502 
46503 #define S_TX_MAC40G    27
46504 #define V_TX_MAC40G(x) ((x) << S_TX_MAC40G)
46505 #define F_TX_MAC40G    V_TX_MAC40G(1U)
46506 
46507 #define S_RX_ST_MAC40G    26
46508 #define V_RX_ST_MAC40G(x) ((x) << S_RX_ST_MAC40G)
46509 #define F_RX_ST_MAC40G    V_RX_ST_MAC40G(1U)
46510 
46511 #define S_TX_ST_MAC40G    25
46512 #define V_TX_ST_MAC40G(x) ((x) << S_TX_ST_MAC40G)
46513 #define F_TX_ST_MAC40G    V_TX_ST_MAC40G(1U)
46514 
46515 #define S_TX_MAC1G10G    24
46516 #define V_TX_MAC1G10G(x) ((x) << S_TX_MAC1G10G)
46517 #define F_TX_MAC1G10G    V_TX_MAC1G10G(1U)
46518 
46519 #define S_RX_MAC1G10G    23
46520 #define V_RX_MAC1G10G(x) ((x) << S_RX_MAC1G10G)
46521 #define F_RX_MAC1G10G    V_RX_MAC1G10G(1U)
46522 
46523 #define S_RX_STATUS_MAC1G10G    22
46524 #define V_RX_STATUS_MAC1G10G(x) ((x) << S_RX_STATUS_MAC1G10G)
46525 #define F_RX_STATUS_MAC1G10G    V_RX_STATUS_MAC1G10G(1U)
46526 
46527 #define S_RX_ST_MAC1G10G    21
46528 #define V_RX_ST_MAC1G10G(x) ((x) << S_RX_ST_MAC1G10G)
46529 #define F_RX_ST_MAC1G10G    V_RX_ST_MAC1G10G(1U)
46530 
46531 #define S_TX_ST_MAC1G10G    20
46532 #define V_TX_ST_MAC1G10G(x) ((x) << S_TX_ST_MAC1G10G)
46533 #define F_TX_ST_MAC1G10G    V_TX_ST_MAC1G10G(1U)
46534 
46535 #define S_PERR_TX0_PCS40G    19
46536 #define V_PERR_TX0_PCS40G(x) ((x) << S_PERR_TX0_PCS40G)
46537 #define F_PERR_TX0_PCS40G    V_PERR_TX0_PCS40G(1U)
46538 
46539 #define S_PERR_TX1_PCS40G    18
46540 #define V_PERR_TX1_PCS40G(x) ((x) << S_PERR_TX1_PCS40G)
46541 #define F_PERR_TX1_PCS40G    V_PERR_TX1_PCS40G(1U)
46542 
46543 #define S_PERR_TX2_PCS40G    17
46544 #define V_PERR_TX2_PCS40G(x) ((x) << S_PERR_TX2_PCS40G)
46545 #define F_PERR_TX2_PCS40G    V_PERR_TX2_PCS40G(1U)
46546 
46547 #define S_PERR_TX3_PCS40G    16
46548 #define V_PERR_TX3_PCS40G(x) ((x) << S_PERR_TX3_PCS40G)
46549 #define F_PERR_TX3_PCS40G    V_PERR_TX3_PCS40G(1U)
46550 
46551 #define S_PERR_TX0_FEC40G    15
46552 #define V_PERR_TX0_FEC40G(x) ((x) << S_PERR_TX0_FEC40G)
46553 #define F_PERR_TX0_FEC40G    V_PERR_TX0_FEC40G(1U)
46554 
46555 #define S_PERR_TX1_FEC40G    14
46556 #define V_PERR_TX1_FEC40G(x) ((x) << S_PERR_TX1_FEC40G)
46557 #define F_PERR_TX1_FEC40G    V_PERR_TX1_FEC40G(1U)
46558 
46559 #define S_PERR_TX2_FEC40G    13
46560 #define V_PERR_TX2_FEC40G(x) ((x) << S_PERR_TX2_FEC40G)
46561 #define F_PERR_TX2_FEC40G    V_PERR_TX2_FEC40G(1U)
46562 
46563 #define S_PERR_TX3_FEC40G    12
46564 #define V_PERR_TX3_FEC40G(x) ((x) << S_PERR_TX3_FEC40G)
46565 #define F_PERR_TX3_FEC40G    V_PERR_TX3_FEC40G(1U)
46566 
46567 #define S_PERR_RX0_PCS40G    11
46568 #define V_PERR_RX0_PCS40G(x) ((x) << S_PERR_RX0_PCS40G)
46569 #define F_PERR_RX0_PCS40G    V_PERR_RX0_PCS40G(1U)
46570 
46571 #define S_PERR_RX1_PCS40G    10
46572 #define V_PERR_RX1_PCS40G(x) ((x) << S_PERR_RX1_PCS40G)
46573 #define F_PERR_RX1_PCS40G    V_PERR_RX1_PCS40G(1U)
46574 
46575 #define S_PERR_RX2_PCS40G    9
46576 #define V_PERR_RX2_PCS40G(x) ((x) << S_PERR_RX2_PCS40G)
46577 #define F_PERR_RX2_PCS40G    V_PERR_RX2_PCS40G(1U)
46578 
46579 #define S_PERR_RX3_PCS40G    8
46580 #define V_PERR_RX3_PCS40G(x) ((x) << S_PERR_RX3_PCS40G)
46581 #define F_PERR_RX3_PCS40G    V_PERR_RX3_PCS40G(1U)
46582 
46583 #define S_PERR_RX0_FEC40G    7
46584 #define V_PERR_RX0_FEC40G(x) ((x) << S_PERR_RX0_FEC40G)
46585 #define F_PERR_RX0_FEC40G    V_PERR_RX0_FEC40G(1U)
46586 
46587 #define S_PERR_RX1_FEC40G    6
46588 #define V_PERR_RX1_FEC40G(x) ((x) << S_PERR_RX1_FEC40G)
46589 #define F_PERR_RX1_FEC40G    V_PERR_RX1_FEC40G(1U)
46590 
46591 #define S_PERR_RX2_FEC40G    5
46592 #define V_PERR_RX2_FEC40G(x) ((x) << S_PERR_RX2_FEC40G)
46593 #define F_PERR_RX2_FEC40G    V_PERR_RX2_FEC40G(1U)
46594 
46595 #define S_PERR_RX3_FEC40G    4
46596 #define V_PERR_RX3_FEC40G(x) ((x) << S_PERR_RX3_FEC40G)
46597 #define F_PERR_RX3_FEC40G    V_PERR_RX3_FEC40G(1U)
46598 
46599 #define S_PERR_RX_PCS10G_LPBK    3
46600 #define V_PERR_RX_PCS10G_LPBK(x) ((x) << S_PERR_RX_PCS10G_LPBK)
46601 #define F_PERR_RX_PCS10G_LPBK    V_PERR_RX_PCS10G_LPBK(1U)
46602 
46603 #define S_PERR_RX_PCS10G    2
46604 #define V_PERR_RX_PCS10G(x) ((x) << S_PERR_RX_PCS10G)
46605 #define F_PERR_RX_PCS10G    V_PERR_RX_PCS10G(1U)
46606 
46607 #define S_PERR_RX_PCS1G    1
46608 #define V_PERR_RX_PCS1G(x) ((x) << S_PERR_RX_PCS1G)
46609 #define F_PERR_RX_PCS1G    V_PERR_RX_PCS1G(1U)
46610 
46611 #define S_PERR_TX_PCS1G    0
46612 #define V_PERR_TX_PCS1G(x) ((x) << S_PERR_TX_PCS1G)
46613 #define F_PERR_TX_PCS1G    V_PERR_TX_PCS1G(1U)
46614 
46615 #define A_MAC_PORT_PERR_INT_CAUSE 0x8e4
46616 
46617 #define S_T6_PERR_PKT_RAM    31
46618 #define V_T6_PERR_PKT_RAM(x) ((x) << S_T6_PERR_PKT_RAM)
46619 #define F_T6_PERR_PKT_RAM    V_T6_PERR_PKT_RAM(1U)
46620 
46621 #define S_T6_PERR_MASK_RAM    30
46622 #define V_T6_PERR_MASK_RAM(x) ((x) << S_T6_PERR_MASK_RAM)
46623 #define F_T6_PERR_MASK_RAM    V_T6_PERR_MASK_RAM(1U)
46624 
46625 #define S_T6_PERR_CRC_RAM    29
46626 #define V_T6_PERR_CRC_RAM(x) ((x) << S_T6_PERR_CRC_RAM)
46627 #define F_T6_PERR_CRC_RAM    V_T6_PERR_CRC_RAM(1U)
46628 
46629 #define A_MAC_PORT_PERR_ENABLE 0x8e8
46630 
46631 #define S_T6_PERR_PKT_RAM    31
46632 #define V_T6_PERR_PKT_RAM(x) ((x) << S_T6_PERR_PKT_RAM)
46633 #define F_T6_PERR_PKT_RAM    V_T6_PERR_PKT_RAM(1U)
46634 
46635 #define S_T6_PERR_MASK_RAM    30
46636 #define V_T6_PERR_MASK_RAM(x) ((x) << S_T6_PERR_MASK_RAM)
46637 #define F_T6_PERR_MASK_RAM    V_T6_PERR_MASK_RAM(1U)
46638 
46639 #define S_T6_PERR_CRC_RAM    29
46640 #define V_T6_PERR_CRC_RAM(x) ((x) << S_T6_PERR_CRC_RAM)
46641 #define F_T6_PERR_CRC_RAM    V_T6_PERR_CRC_RAM(1U)
46642 
46643 #define A_MAC_PORT_PERR_INJECT 0x8ec
46644 
46645 #define S_MEMSEL_PERR    1
46646 #define M_MEMSEL_PERR    0x3fU
46647 #define V_MEMSEL_PERR(x) ((x) << S_MEMSEL_PERR)
46648 #define G_MEMSEL_PERR(x) (((x) >> S_MEMSEL_PERR) & M_MEMSEL_PERR)
46649 
46650 #define A_MAC_PORT_HSS_CFG0 0x8f0
46651 
46652 #define S_HSSREFCLKVALIDA    20
46653 #define V_HSSREFCLKVALIDA(x) ((x) << S_HSSREFCLKVALIDA)
46654 #define F_HSSREFCLKVALIDA    V_HSSREFCLKVALIDA(1U)
46655 
46656 #define S_HSSREFCLKVALIDB    19
46657 #define V_HSSREFCLKVALIDB(x) ((x) << S_HSSREFCLKVALIDB)
46658 #define F_HSSREFCLKVALIDB    V_HSSREFCLKVALIDB(1U)
46659 
46660 #define S_HSSRESYNCA    18
46661 #define V_HSSRESYNCA(x) ((x) << S_HSSRESYNCA)
46662 #define F_HSSRESYNCA    V_HSSRESYNCA(1U)
46663 
46664 #define S_HSSRESYNCB    16
46665 #define V_HSSRESYNCB(x) ((x) << S_HSSRESYNCB)
46666 #define F_HSSRESYNCB    V_HSSRESYNCB(1U)
46667 
46668 #define S_HSSRECCALA    15
46669 #define V_HSSRECCALA(x) ((x) << S_HSSRECCALA)
46670 #define F_HSSRECCALA    V_HSSRECCALA(1U)
46671 
46672 #define S_HSSRECCALB    13
46673 #define V_HSSRECCALB(x) ((x) << S_HSSRECCALB)
46674 #define F_HSSRECCALB    V_HSSRECCALB(1U)
46675 
46676 #define S_HSSPLLBYPA    12
46677 #define V_HSSPLLBYPA(x) ((x) << S_HSSPLLBYPA)
46678 #define F_HSSPLLBYPA    V_HSSPLLBYPA(1U)
46679 
46680 #define S_HSSPLLBYPB    11
46681 #define V_HSSPLLBYPB(x) ((x) << S_HSSPLLBYPB)
46682 #define F_HSSPLLBYPB    V_HSSPLLBYPB(1U)
46683 
46684 #define S_HSSPDWNPLLA    10
46685 #define V_HSSPDWNPLLA(x) ((x) << S_HSSPDWNPLLA)
46686 #define F_HSSPDWNPLLA    V_HSSPDWNPLLA(1U)
46687 
46688 #define S_HSSPDWNPLLB    9
46689 #define V_HSSPDWNPLLB(x) ((x) << S_HSSPDWNPLLB)
46690 #define F_HSSPDWNPLLB    V_HSSPDWNPLLB(1U)
46691 
46692 #define S_HSSVCOSELA    8
46693 #define V_HSSVCOSELA(x) ((x) << S_HSSVCOSELA)
46694 #define F_HSSVCOSELA    V_HSSVCOSELA(1U)
46695 
46696 #define S_HSSVCOSELB    7
46697 #define V_HSSVCOSELB(x) ((x) << S_HSSVCOSELB)
46698 #define F_HSSVCOSELB    V_HSSVCOSELB(1U)
46699 
46700 #define S_HSSCALCOMP    6
46701 #define V_HSSCALCOMP(x) ((x) << S_HSSCALCOMP)
46702 #define F_HSSCALCOMP    V_HSSCALCOMP(1U)
46703 
46704 #define S_HSSCALENAB    5
46705 #define V_HSSCALENAB(x) ((x) << S_HSSCALENAB)
46706 #define F_HSSCALENAB    V_HSSCALENAB(1U)
46707 
46708 #define A_MAC_PORT_HSS_CFG1 0x8f4
46709 
46710 #define S_RXACONFIGSEL    30
46711 #define M_RXACONFIGSEL    0x3U
46712 #define V_RXACONFIGSEL(x) ((x) << S_RXACONFIGSEL)
46713 #define G_RXACONFIGSEL(x) (((x) >> S_RXACONFIGSEL) & M_RXACONFIGSEL)
46714 
46715 #define S_RXAQUIET    29
46716 #define V_RXAQUIET(x) ((x) << S_RXAQUIET)
46717 #define F_RXAQUIET    V_RXAQUIET(1U)
46718 
46719 #define S_RXAREFRESH    28
46720 #define V_RXAREFRESH(x) ((x) << S_RXAREFRESH)
46721 #define F_RXAREFRESH    V_RXAREFRESH(1U)
46722 
46723 #define S_RXBCONFIGSEL    26
46724 #define M_RXBCONFIGSEL    0x3U
46725 #define V_RXBCONFIGSEL(x) ((x) << S_RXBCONFIGSEL)
46726 #define G_RXBCONFIGSEL(x) (((x) >> S_RXBCONFIGSEL) & M_RXBCONFIGSEL)
46727 
46728 #define S_RXBQUIET    25
46729 #define V_RXBQUIET(x) ((x) << S_RXBQUIET)
46730 #define F_RXBQUIET    V_RXBQUIET(1U)
46731 
46732 #define S_RXBREFRESH    24
46733 #define V_RXBREFRESH(x) ((x) << S_RXBREFRESH)
46734 #define F_RXBREFRESH    V_RXBREFRESH(1U)
46735 
46736 #define S_RXCCONFIGSEL    22
46737 #define M_RXCCONFIGSEL    0x3U
46738 #define V_RXCCONFIGSEL(x) ((x) << S_RXCCONFIGSEL)
46739 #define G_RXCCONFIGSEL(x) (((x) >> S_RXCCONFIGSEL) & M_RXCCONFIGSEL)
46740 
46741 #define S_RXCQUIET    21
46742 #define V_RXCQUIET(x) ((x) << S_RXCQUIET)
46743 #define F_RXCQUIET    V_RXCQUIET(1U)
46744 
46745 #define S_RXCREFRESH    20
46746 #define V_RXCREFRESH(x) ((x) << S_RXCREFRESH)
46747 #define F_RXCREFRESH    V_RXCREFRESH(1U)
46748 
46749 #define S_RXDCONFIGSEL    18
46750 #define M_RXDCONFIGSEL    0x3U
46751 #define V_RXDCONFIGSEL(x) ((x) << S_RXDCONFIGSEL)
46752 #define G_RXDCONFIGSEL(x) (((x) >> S_RXDCONFIGSEL) & M_RXDCONFIGSEL)
46753 
46754 #define S_RXDQUIET    17
46755 #define V_RXDQUIET(x) ((x) << S_RXDQUIET)
46756 #define F_RXDQUIET    V_RXDQUIET(1U)
46757 
46758 #define S_RXDREFRESH    16
46759 #define V_RXDREFRESH(x) ((x) << S_RXDREFRESH)
46760 #define F_RXDREFRESH    V_RXDREFRESH(1U)
46761 
46762 #define S_TXACONFIGSEL    14
46763 #define M_TXACONFIGSEL    0x3U
46764 #define V_TXACONFIGSEL(x) ((x) << S_TXACONFIGSEL)
46765 #define G_TXACONFIGSEL(x) (((x) >> S_TXACONFIGSEL) & M_TXACONFIGSEL)
46766 
46767 #define S_TXAQUIET    13
46768 #define V_TXAQUIET(x) ((x) << S_TXAQUIET)
46769 #define F_TXAQUIET    V_TXAQUIET(1U)
46770 
46771 #define S_TXAREFRESH    12
46772 #define V_TXAREFRESH(x) ((x) << S_TXAREFRESH)
46773 #define F_TXAREFRESH    V_TXAREFRESH(1U)
46774 
46775 #define S_TXBCONFIGSEL    10
46776 #define M_TXBCONFIGSEL    0x3U
46777 #define V_TXBCONFIGSEL(x) ((x) << S_TXBCONFIGSEL)
46778 #define G_TXBCONFIGSEL(x) (((x) >> S_TXBCONFIGSEL) & M_TXBCONFIGSEL)
46779 
46780 #define S_TXBQUIET    9
46781 #define V_TXBQUIET(x) ((x) << S_TXBQUIET)
46782 #define F_TXBQUIET    V_TXBQUIET(1U)
46783 
46784 #define S_TXBREFRESH    8
46785 #define V_TXBREFRESH(x) ((x) << S_TXBREFRESH)
46786 #define F_TXBREFRESH    V_TXBREFRESH(1U)
46787 
46788 #define S_TXCCONFIGSEL    6
46789 #define M_TXCCONFIGSEL    0x3U
46790 #define V_TXCCONFIGSEL(x) ((x) << S_TXCCONFIGSEL)
46791 #define G_TXCCONFIGSEL(x) (((x) >> S_TXCCONFIGSEL) & M_TXCCONFIGSEL)
46792 
46793 #define S_TXCQUIET    5
46794 #define V_TXCQUIET(x) ((x) << S_TXCQUIET)
46795 #define F_TXCQUIET    V_TXCQUIET(1U)
46796 
46797 #define S_TXCREFRESH    4
46798 #define V_TXCREFRESH(x) ((x) << S_TXCREFRESH)
46799 #define F_TXCREFRESH    V_TXCREFRESH(1U)
46800 
46801 #define S_TXDCONFIGSEL    2
46802 #define M_TXDCONFIGSEL    0x3U
46803 #define V_TXDCONFIGSEL(x) ((x) << S_TXDCONFIGSEL)
46804 #define G_TXDCONFIGSEL(x) (((x) >> S_TXDCONFIGSEL) & M_TXDCONFIGSEL)
46805 
46806 #define S_TXDQUIET    1
46807 #define V_TXDQUIET(x) ((x) << S_TXDQUIET)
46808 #define F_TXDQUIET    V_TXDQUIET(1U)
46809 
46810 #define S_TXDREFRESH    0
46811 #define V_TXDREFRESH(x) ((x) << S_TXDREFRESH)
46812 #define F_TXDREFRESH    V_TXDREFRESH(1U)
46813 
46814 #define A_MAC_PORT_HSS_CFG2 0x8f8
46815 
46816 #define S_RXAASSTCLK    31
46817 #define V_RXAASSTCLK(x) ((x) << S_RXAASSTCLK)
46818 #define F_RXAASSTCLK    V_RXAASSTCLK(1U)
46819 
46820 #define S_T5RXAPRBSRST    30
46821 #define V_T5RXAPRBSRST(x) ((x) << S_T5RXAPRBSRST)
46822 #define F_T5RXAPRBSRST    V_T5RXAPRBSRST(1U)
46823 
46824 #define S_RXBASSTCLK    29
46825 #define V_RXBASSTCLK(x) ((x) << S_RXBASSTCLK)
46826 #define F_RXBASSTCLK    V_RXBASSTCLK(1U)
46827 
46828 #define S_T5RXBPRBSRST    28
46829 #define V_T5RXBPRBSRST(x) ((x) << S_T5RXBPRBSRST)
46830 #define F_T5RXBPRBSRST    V_T5RXBPRBSRST(1U)
46831 
46832 #define S_RXCASSTCLK    27
46833 #define V_RXCASSTCLK(x) ((x) << S_RXCASSTCLK)
46834 #define F_RXCASSTCLK    V_RXCASSTCLK(1U)
46835 
46836 #define S_T5RXCPRBSRST    26
46837 #define V_T5RXCPRBSRST(x) ((x) << S_T5RXCPRBSRST)
46838 #define F_T5RXCPRBSRST    V_T5RXCPRBSRST(1U)
46839 
46840 #define S_RXDASSTCLK    25
46841 #define V_RXDASSTCLK(x) ((x) << S_RXDASSTCLK)
46842 #define F_RXDASSTCLK    V_RXDASSTCLK(1U)
46843 
46844 #define S_T5RXDPRBSRST    24
46845 #define V_T5RXDPRBSRST(x) ((x) << S_T5RXDPRBSRST)
46846 #define F_T5RXDPRBSRST    V_T5RXDPRBSRST(1U)
46847 
46848 #define A_MAC_PORT_HSS_CFG3 0x8fc
46849 
46850 #define S_HSSCALSSTN    25
46851 #define M_HSSCALSSTN    0x7U
46852 #define V_HSSCALSSTN(x) ((x) << S_HSSCALSSTN)
46853 #define G_HSSCALSSTN(x) (((x) >> S_HSSCALSSTN) & M_HSSCALSSTN)
46854 
46855 #define S_HSSCALSSTP    22
46856 #define M_HSSCALSSTP    0x7U
46857 #define V_HSSCALSSTP(x) ((x) << S_HSSCALSSTP)
46858 #define G_HSSCALSSTP(x) (((x) >> S_HSSCALSSTP) & M_HSSCALSSTP)
46859 
46860 #define S_HSSVBOOSTDIVB    19
46861 #define M_HSSVBOOSTDIVB    0x7U
46862 #define V_HSSVBOOSTDIVB(x) ((x) << S_HSSVBOOSTDIVB)
46863 #define G_HSSVBOOSTDIVB(x) (((x) >> S_HSSVBOOSTDIVB) & M_HSSVBOOSTDIVB)
46864 
46865 #define S_HSSVBOOSTDIVA    16
46866 #define M_HSSVBOOSTDIVA    0x7U
46867 #define V_HSSVBOOSTDIVA(x) ((x) << S_HSSVBOOSTDIVA)
46868 #define G_HSSVBOOSTDIVA(x) (((x) >> S_HSSVBOOSTDIVA) & M_HSSVBOOSTDIVA)
46869 
46870 #define S_HSSPLLCONFIGB    8
46871 #define M_HSSPLLCONFIGB    0xffU
46872 #define V_HSSPLLCONFIGB(x) ((x) << S_HSSPLLCONFIGB)
46873 #define G_HSSPLLCONFIGB(x) (((x) >> S_HSSPLLCONFIGB) & M_HSSPLLCONFIGB)
46874 
46875 #define S_HSSPLLCONFIGA    0
46876 #define M_HSSPLLCONFIGA    0xffU
46877 #define V_HSSPLLCONFIGA(x) ((x) << S_HSSPLLCONFIGA)
46878 #define G_HSSPLLCONFIGA(x) (((x) >> S_HSSPLLCONFIGA) & M_HSSPLLCONFIGA)
46879 
46880 #define S_T6_HSSCALSSTN    22
46881 #define M_T6_HSSCALSSTN    0x3fU
46882 #define V_T6_HSSCALSSTN(x) ((x) << S_T6_HSSCALSSTN)
46883 #define G_T6_HSSCALSSTN(x) (((x) >> S_T6_HSSCALSSTN) & M_T6_HSSCALSSTN)
46884 
46885 #define S_T6_HSSCALSSTP    16
46886 #define M_T6_HSSCALSSTP    0x3fU
46887 #define V_T6_HSSCALSSTP(x) ((x) << S_T6_HSSCALSSTP)
46888 #define G_T6_HSSCALSSTP(x) (((x) >> S_T6_HSSCALSSTP) & M_T6_HSSCALSSTP)
46889 
46890 #define A_MAC_PORT_HSS_CFG4 0x900
46891 
46892 #define S_HSSDIVSELA    9
46893 #define M_HSSDIVSELA    0x1ffU
46894 #define V_HSSDIVSELA(x) ((x) << S_HSSDIVSELA)
46895 #define G_HSSDIVSELA(x) (((x) >> S_HSSDIVSELA) & M_HSSDIVSELA)
46896 
46897 #define S_HSSDIVSELB    0
46898 #define M_HSSDIVSELB    0x1ffU
46899 #define V_HSSDIVSELB(x) ((x) << S_HSSDIVSELB)
46900 #define G_HSSDIVSELB(x) (((x) >> S_HSSDIVSELB) & M_HSSDIVSELB)
46901 
46902 #define S_HSSREFDIVA    24
46903 #define M_HSSREFDIVA    0xfU
46904 #define V_HSSREFDIVA(x) ((x) << S_HSSREFDIVA)
46905 #define G_HSSREFDIVA(x) (((x) >> S_HSSREFDIVA) & M_HSSREFDIVA)
46906 
46907 #define S_HSSREFDIVB    20
46908 #define M_HSSREFDIVB    0xfU
46909 #define V_HSSREFDIVB(x) ((x) << S_HSSREFDIVB)
46910 #define G_HSSREFDIVB(x) (((x) >> S_HSSREFDIVB) & M_HSSREFDIVB)
46911 
46912 #define S_HSSPLLDIV2B    19
46913 #define V_HSSPLLDIV2B(x) ((x) << S_HSSPLLDIV2B)
46914 #define F_HSSPLLDIV2B    V_HSSPLLDIV2B(1U)
46915 
46916 #define S_HSSPLLDIV2A    18
46917 #define V_HSSPLLDIV2A(x) ((x) << S_HSSPLLDIV2A)
46918 #define F_HSSPLLDIV2A    V_HSSPLLDIV2A(1U)
46919 
46920 #define A_MAC_PORT_HSS_STATUS 0x904
46921 
46922 #define S_HSSPLLLOCKB    3
46923 #define V_HSSPLLLOCKB(x) ((x) << S_HSSPLLLOCKB)
46924 #define F_HSSPLLLOCKB    V_HSSPLLLOCKB(1U)
46925 
46926 #define S_HSSPLLLOCKA    2
46927 #define V_HSSPLLLOCKA(x) ((x) << S_HSSPLLLOCKA)
46928 #define F_HSSPLLLOCKA    V_HSSPLLLOCKA(1U)
46929 
46930 #define S_HSSPRTREADYB    1
46931 #define V_HSSPRTREADYB(x) ((x) << S_HSSPRTREADYB)
46932 #define F_HSSPRTREADYB    V_HSSPRTREADYB(1U)
46933 
46934 #define S_HSSPRTREADYA    0
46935 #define V_HSSPRTREADYA(x) ((x) << S_HSSPRTREADYA)
46936 #define F_HSSPRTREADYA    V_HSSPRTREADYA(1U)
46937 
46938 #define S_RXDERROFLOW    19
46939 #define V_RXDERROFLOW(x) ((x) << S_RXDERROFLOW)
46940 #define F_RXDERROFLOW    V_RXDERROFLOW(1U)
46941 
46942 #define S_RXCERROFLOW    18
46943 #define V_RXCERROFLOW(x) ((x) << S_RXCERROFLOW)
46944 #define F_RXCERROFLOW    V_RXCERROFLOW(1U)
46945 
46946 #define S_RXBERROFLOW    17
46947 #define V_RXBERROFLOW(x) ((x) << S_RXBERROFLOW)
46948 #define F_RXBERROFLOW    V_RXBERROFLOW(1U)
46949 
46950 #define S_RXAERROFLOW    16
46951 #define V_RXAERROFLOW(x) ((x) << S_RXAERROFLOW)
46952 #define F_RXAERROFLOW    V_RXAERROFLOW(1U)
46953 
46954 #define A_MAC_PORT_HSS_EEE_STATUS 0x908
46955 
46956 #define S_RXAQUIET_STATUS    15
46957 #define V_RXAQUIET_STATUS(x) ((x) << S_RXAQUIET_STATUS)
46958 #define F_RXAQUIET_STATUS    V_RXAQUIET_STATUS(1U)
46959 
46960 #define S_RXAREFRESH_STATUS    14
46961 #define V_RXAREFRESH_STATUS(x) ((x) << S_RXAREFRESH_STATUS)
46962 #define F_RXAREFRESH_STATUS    V_RXAREFRESH_STATUS(1U)
46963 
46964 #define S_RXBQUIET_STATUS    13
46965 #define V_RXBQUIET_STATUS(x) ((x) << S_RXBQUIET_STATUS)
46966 #define F_RXBQUIET_STATUS    V_RXBQUIET_STATUS(1U)
46967 
46968 #define S_RXBREFRESH_STATUS    12
46969 #define V_RXBREFRESH_STATUS(x) ((x) << S_RXBREFRESH_STATUS)
46970 #define F_RXBREFRESH_STATUS    V_RXBREFRESH_STATUS(1U)
46971 
46972 #define S_RXCQUIET_STATUS    11
46973 #define V_RXCQUIET_STATUS(x) ((x) << S_RXCQUIET_STATUS)
46974 #define F_RXCQUIET_STATUS    V_RXCQUIET_STATUS(1U)
46975 
46976 #define S_RXCREFRESH_STATUS    10
46977 #define V_RXCREFRESH_STATUS(x) ((x) << S_RXCREFRESH_STATUS)
46978 #define F_RXCREFRESH_STATUS    V_RXCREFRESH_STATUS(1U)
46979 
46980 #define S_RXDQUIET_STATUS    9
46981 #define V_RXDQUIET_STATUS(x) ((x) << S_RXDQUIET_STATUS)
46982 #define F_RXDQUIET_STATUS    V_RXDQUIET_STATUS(1U)
46983 
46984 #define S_RXDREFRESH_STATUS    8
46985 #define V_RXDREFRESH_STATUS(x) ((x) << S_RXDREFRESH_STATUS)
46986 #define F_RXDREFRESH_STATUS    V_RXDREFRESH_STATUS(1U)
46987 
46988 #define S_TXAQUIET_STATUS    7
46989 #define V_TXAQUIET_STATUS(x) ((x) << S_TXAQUIET_STATUS)
46990 #define F_TXAQUIET_STATUS    V_TXAQUIET_STATUS(1U)
46991 
46992 #define S_TXAREFRESH_STATUS    6
46993 #define V_TXAREFRESH_STATUS(x) ((x) << S_TXAREFRESH_STATUS)
46994 #define F_TXAREFRESH_STATUS    V_TXAREFRESH_STATUS(1U)
46995 
46996 #define S_TXBQUIET_STATUS    5
46997 #define V_TXBQUIET_STATUS(x) ((x) << S_TXBQUIET_STATUS)
46998 #define F_TXBQUIET_STATUS    V_TXBQUIET_STATUS(1U)
46999 
47000 #define S_TXBREFRESH_STATUS    4
47001 #define V_TXBREFRESH_STATUS(x) ((x) << S_TXBREFRESH_STATUS)
47002 #define F_TXBREFRESH_STATUS    V_TXBREFRESH_STATUS(1U)
47003 
47004 #define S_TXCQUIET_STATUS    3
47005 #define V_TXCQUIET_STATUS(x) ((x) << S_TXCQUIET_STATUS)
47006 #define F_TXCQUIET_STATUS    V_TXCQUIET_STATUS(1U)
47007 
47008 #define S_TXCREFRESH_STATUS    2
47009 #define V_TXCREFRESH_STATUS(x) ((x) << S_TXCREFRESH_STATUS)
47010 #define F_TXCREFRESH_STATUS    V_TXCREFRESH_STATUS(1U)
47011 
47012 #define S_TXDQUIET_STATUS    1
47013 #define V_TXDQUIET_STATUS(x) ((x) << S_TXDQUIET_STATUS)
47014 #define F_TXDQUIET_STATUS    V_TXDQUIET_STATUS(1U)
47015 
47016 #define S_TXDREFRESH_STATUS    0
47017 #define V_TXDREFRESH_STATUS(x) ((x) << S_TXDREFRESH_STATUS)
47018 #define F_TXDREFRESH_STATUS    V_TXDREFRESH_STATUS(1U)
47019 
47020 #define A_MAC_PORT_HSS_SIGDET_STATUS 0x90c
47021 #define A_MAC_PORT_HSS_PL_CTL 0x910
47022 
47023 #define S_TOV    16
47024 #define M_TOV    0xffU
47025 #define V_TOV(x) ((x) << S_TOV)
47026 #define G_TOV(x) (((x) >> S_TOV) & M_TOV)
47027 
47028 #define S_TSU    8
47029 #define M_TSU    0xffU
47030 #define V_TSU(x) ((x) << S_TSU)
47031 #define G_TSU(x) (((x) >> S_TSU) & M_TSU)
47032 
47033 #define S_IPW    0
47034 #define M_IPW    0xffU
47035 #define V_IPW(x) ((x) << S_IPW)
47036 #define G_IPW(x) (((x) >> S_IPW) & M_IPW)
47037 
47038 #define A_MAC_PORT_RUNT_FRAME 0x914
47039 
47040 #define S_RUNTCLEAR    16
47041 #define V_RUNTCLEAR(x) ((x) << S_RUNTCLEAR)
47042 #define F_RUNTCLEAR    V_RUNTCLEAR(1U)
47043 
47044 #define S_RUNT    0
47045 #define M_RUNT    0xffffU
47046 #define V_RUNT(x) ((x) << S_RUNT)
47047 #define G_RUNT(x) (((x) >> S_RUNT) & M_RUNT)
47048 
47049 #define A_MAC_PORT_EEE_STATUS 0x918
47050 
47051 #define S_EEE_TX_10G_STATE    10
47052 #define M_EEE_TX_10G_STATE    0x3U
47053 #define V_EEE_TX_10G_STATE(x) ((x) << S_EEE_TX_10G_STATE)
47054 #define G_EEE_TX_10G_STATE(x) (((x) >> S_EEE_TX_10G_STATE) & M_EEE_TX_10G_STATE)
47055 
47056 #define S_EEE_RX_10G_STATE    8
47057 #define M_EEE_RX_10G_STATE    0x3U
47058 #define V_EEE_RX_10G_STATE(x) ((x) << S_EEE_RX_10G_STATE)
47059 #define G_EEE_RX_10G_STATE(x) (((x) >> S_EEE_RX_10G_STATE) & M_EEE_RX_10G_STATE)
47060 
47061 #define S_EEE_TX_1G_STATE    6
47062 #define M_EEE_TX_1G_STATE    0x3U
47063 #define V_EEE_TX_1G_STATE(x) ((x) << S_EEE_TX_1G_STATE)
47064 #define G_EEE_TX_1G_STATE(x) (((x) >> S_EEE_TX_1G_STATE) & M_EEE_TX_1G_STATE)
47065 
47066 #define S_EEE_RX_1G_STATE    4
47067 #define M_EEE_RX_1G_STATE    0x3U
47068 #define V_EEE_RX_1G_STATE(x) ((x) << S_EEE_RX_1G_STATE)
47069 #define G_EEE_RX_1G_STATE(x) (((x) >> S_EEE_RX_1G_STATE) & M_EEE_RX_1G_STATE)
47070 
47071 #define S_PMA_RX_REFRESH    3
47072 #define V_PMA_RX_REFRESH(x) ((x) << S_PMA_RX_REFRESH)
47073 #define F_PMA_RX_REFRESH    V_PMA_RX_REFRESH(1U)
47074 
47075 #define S_PMA_RX_QUIET    2
47076 #define V_PMA_RX_QUIET(x) ((x) << S_PMA_RX_QUIET)
47077 #define F_PMA_RX_QUIET    V_PMA_RX_QUIET(1U)
47078 
47079 #define S_PMA_TX_REFRESH    1
47080 #define V_PMA_TX_REFRESH(x) ((x) << S_PMA_TX_REFRESH)
47081 #define F_PMA_TX_REFRESH    V_PMA_TX_REFRESH(1U)
47082 
47083 #define S_PMA_TX_QUIET    0
47084 #define V_PMA_TX_QUIET(x) ((x) << S_PMA_TX_QUIET)
47085 #define F_PMA_TX_QUIET    V_PMA_TX_QUIET(1U)
47086 
47087 #define A_MAC_PORT_CGEN 0x91c
47088 
47089 #define S_CGEN    8
47090 #define V_CGEN(x) ((x) << S_CGEN)
47091 #define F_CGEN    V_CGEN(1U)
47092 
47093 #define S_SD7_CGEN    7
47094 #define V_SD7_CGEN(x) ((x) << S_SD7_CGEN)
47095 #define F_SD7_CGEN    V_SD7_CGEN(1U)
47096 
47097 #define S_SD6_CGEN    6
47098 #define V_SD6_CGEN(x) ((x) << S_SD6_CGEN)
47099 #define F_SD6_CGEN    V_SD6_CGEN(1U)
47100 
47101 #define S_SD5_CGEN    5
47102 #define V_SD5_CGEN(x) ((x) << S_SD5_CGEN)
47103 #define F_SD5_CGEN    V_SD5_CGEN(1U)
47104 
47105 #define S_SD4_CGEN    4
47106 #define V_SD4_CGEN(x) ((x) << S_SD4_CGEN)
47107 #define F_SD4_CGEN    V_SD4_CGEN(1U)
47108 
47109 #define S_SD3_CGEN    3
47110 #define V_SD3_CGEN(x) ((x) << S_SD3_CGEN)
47111 #define F_SD3_CGEN    V_SD3_CGEN(1U)
47112 
47113 #define S_SD2_CGEN    2
47114 #define V_SD2_CGEN(x) ((x) << S_SD2_CGEN)
47115 #define F_SD2_CGEN    V_SD2_CGEN(1U)
47116 
47117 #define S_SD1_CGEN    1
47118 #define V_SD1_CGEN(x) ((x) << S_SD1_CGEN)
47119 #define F_SD1_CGEN    V_SD1_CGEN(1U)
47120 
47121 #define S_SD0_CGEN    0
47122 #define V_SD0_CGEN(x) ((x) << S_SD0_CGEN)
47123 #define F_SD0_CGEN    V_SD0_CGEN(1U)
47124 
47125 #define A_MAC_PORT_CGEN_MTIP 0x920
47126 
47127 #define S_MACSEG5_CGEN    11
47128 #define V_MACSEG5_CGEN(x) ((x) << S_MACSEG5_CGEN)
47129 #define F_MACSEG5_CGEN    V_MACSEG5_CGEN(1U)
47130 
47131 #define S_PCSSEG5_CGEN    10
47132 #define V_PCSSEG5_CGEN(x) ((x) << S_PCSSEG5_CGEN)
47133 #define F_PCSSEG5_CGEN    V_PCSSEG5_CGEN(1U)
47134 
47135 #define S_MACSEG4_CGEN    9
47136 #define V_MACSEG4_CGEN(x) ((x) << S_MACSEG4_CGEN)
47137 #define F_MACSEG4_CGEN    V_MACSEG4_CGEN(1U)
47138 
47139 #define S_PCSSEG4_CGEN    8
47140 #define V_PCSSEG4_CGEN(x) ((x) << S_PCSSEG4_CGEN)
47141 #define F_PCSSEG4_CGEN    V_PCSSEG4_CGEN(1U)
47142 
47143 #define S_MACSEG3_CGEN    7
47144 #define V_MACSEG3_CGEN(x) ((x) << S_MACSEG3_CGEN)
47145 #define F_MACSEG3_CGEN    V_MACSEG3_CGEN(1U)
47146 
47147 #define S_PCSSEG3_CGEN    6
47148 #define V_PCSSEG3_CGEN(x) ((x) << S_PCSSEG3_CGEN)
47149 #define F_PCSSEG3_CGEN    V_PCSSEG3_CGEN(1U)
47150 
47151 #define S_MACSEG2_CGEN    5
47152 #define V_MACSEG2_CGEN(x) ((x) << S_MACSEG2_CGEN)
47153 #define F_MACSEG2_CGEN    V_MACSEG2_CGEN(1U)
47154 
47155 #define S_PCSSEG2_CGEN    4
47156 #define V_PCSSEG2_CGEN(x) ((x) << S_PCSSEG2_CGEN)
47157 #define F_PCSSEG2_CGEN    V_PCSSEG2_CGEN(1U)
47158 
47159 #define S_MACSEG1_CGEN    3
47160 #define V_MACSEG1_CGEN(x) ((x) << S_MACSEG1_CGEN)
47161 #define F_MACSEG1_CGEN    V_MACSEG1_CGEN(1U)
47162 
47163 #define S_PCSSEG1_CGEN    2
47164 #define V_PCSSEG1_CGEN(x) ((x) << S_PCSSEG1_CGEN)
47165 #define F_PCSSEG1_CGEN    V_PCSSEG1_CGEN(1U)
47166 
47167 #define S_MACSEG0_CGEN    1
47168 #define V_MACSEG0_CGEN(x) ((x) << S_MACSEG0_CGEN)
47169 #define F_MACSEG0_CGEN    V_MACSEG0_CGEN(1U)
47170 
47171 #define S_PCSSEG0_CGEN    0
47172 #define V_PCSSEG0_CGEN(x) ((x) << S_PCSSEG0_CGEN)
47173 #define F_PCSSEG0_CGEN    V_PCSSEG0_CGEN(1U)
47174 
47175 #define A_MAC_PORT_TX_TS_ID 0x924
47176 
47177 #define S_TS_ID    0
47178 #define M_TS_ID    0x7U
47179 #define V_TS_ID(x) ((x) << S_TS_ID)
47180 #define G_TS_ID(x) (((x) >> S_TS_ID) & M_TS_ID)
47181 
47182 #define A_MAC_PORT_TX_TS_VAL_LO 0x928
47183 #define A_MAC_PORT_TX_TS_VAL_HI 0x92c
47184 #define A_MAC_PORT_EEE_CTL 0x930
47185 
47186 #define S_EEE_CTRL    2
47187 #define M_EEE_CTRL    0x3fffffffU
47188 #define V_EEE_CTRL(x) ((x) << S_EEE_CTRL)
47189 #define G_EEE_CTRL(x) (((x) >> S_EEE_CTRL) & M_EEE_CTRL)
47190 
47191 #define S_TICK_START    1
47192 #define V_TICK_START(x) ((x) << S_TICK_START)
47193 #define F_TICK_START    V_TICK_START(1U)
47194 
47195 #define S_EEE_ENABLE    0
47196 #define V_EEE_ENABLE(x) ((x) << S_EEE_ENABLE)
47197 #define F_EEE_ENABLE    V_EEE_ENABLE(1U)
47198 
47199 #define A_MAC_PORT_EEE_TX_CTL 0x934
47200 
47201 #define S_WAKE_TIMER    16
47202 #define M_WAKE_TIMER    0xffffU
47203 #define V_WAKE_TIMER(x) ((x) << S_WAKE_TIMER)
47204 #define G_WAKE_TIMER(x) (((x) >> S_WAKE_TIMER) & M_WAKE_TIMER)
47205 
47206 #define S_HSS_TIMER    5
47207 #define M_HSS_TIMER    0xfU
47208 #define V_HSS_TIMER(x) ((x) << S_HSS_TIMER)
47209 #define G_HSS_TIMER(x) (((x) >> S_HSS_TIMER) & M_HSS_TIMER)
47210 
47211 #define S_HSS_CTL    4
47212 #define V_HSS_CTL(x) ((x) << S_HSS_CTL)
47213 #define F_HSS_CTL    V_HSS_CTL(1U)
47214 
47215 #define S_LPI_ACTIVE    3
47216 #define V_LPI_ACTIVE(x) ((x) << S_LPI_ACTIVE)
47217 #define F_LPI_ACTIVE    V_LPI_ACTIVE(1U)
47218 
47219 #define S_LPI_TXHOLD    2
47220 #define V_LPI_TXHOLD(x) ((x) << S_LPI_TXHOLD)
47221 #define F_LPI_TXHOLD    V_LPI_TXHOLD(1U)
47222 
47223 #define S_LPI_REQ    1
47224 #define V_LPI_REQ(x) ((x) << S_LPI_REQ)
47225 #define F_LPI_REQ    V_LPI_REQ(1U)
47226 
47227 #define S_EEE_TX_RESET    0
47228 #define V_EEE_TX_RESET(x) ((x) << S_EEE_TX_RESET)
47229 #define F_EEE_TX_RESET    V_EEE_TX_RESET(1U)
47230 
47231 #define A_MAC_PORT_EEE_RX_CTL 0x938
47232 
47233 #define S_LPI_IND    1
47234 #define V_LPI_IND(x) ((x) << S_LPI_IND)
47235 #define F_LPI_IND    V_LPI_IND(1U)
47236 
47237 #define S_EEE_RX_RESET    0
47238 #define V_EEE_RX_RESET(x) ((x) << S_EEE_RX_RESET)
47239 #define F_EEE_RX_RESET    V_EEE_RX_RESET(1U)
47240 
47241 #define A_MAC_PORT_EEE_TX_10G_SLEEP_TIMER 0x93c
47242 #define A_MAC_PORT_EEE_TX_10G_QUIET_TIMER 0x940
47243 #define A_MAC_PORT_EEE_TX_10G_WAKE_TIMER 0x944
47244 #define A_MAC_PORT_EEE_TX_1G_SLEEP_TIMER 0x948
47245 #define A_MAC_PORT_EEE_TX_1G_QUIET_TIMER 0x94c
47246 #define A_MAC_PORT_EEE_TX_1G_REFRESH_TIMER 0x950
47247 #define A_MAC_PORT_EEE_RX_10G_QUIET_TIMER 0x954
47248 #define A_MAC_PORT_EEE_RX_10G_WAKE_TIMER 0x958
47249 #define A_MAC_PORT_EEE_RX_10G_WF_TIMER 0x95c
47250 #define A_MAC_PORT_EEE_RX_1G_QUIET_TIMER 0x960
47251 #define A_MAC_PORT_EEE_RX_1G_WAKE_TIMER 0x964
47252 #define A_MAC_PORT_EEE_WF_COUNT 0x968
47253 
47254 #define S_WAKE_CNT_CLR    16
47255 #define V_WAKE_CNT_CLR(x) ((x) << S_WAKE_CNT_CLR)
47256 #define F_WAKE_CNT_CLR    V_WAKE_CNT_CLR(1U)
47257 
47258 #define S_WAKE_CNT    0
47259 #define M_WAKE_CNT    0xffffU
47260 #define V_WAKE_CNT(x) ((x) << S_WAKE_CNT)
47261 #define G_WAKE_CNT(x) (((x) >> S_WAKE_CNT) & M_WAKE_CNT)
47262 
47263 #define A_MAC_PORT_PTP_TIMER_RD0_LO 0x96c
47264 #define A_MAC_PORT_PTP_TIMER_RD0_HI 0x970
47265 #define A_MAC_PORT_PTP_TIMER_RD1_LO 0x974
47266 #define A_MAC_PORT_PTP_TIMER_RD1_HI 0x978
47267 #define A_MAC_PORT_PTP_TIMER_WR_LO 0x97c
47268 #define A_MAC_PORT_PTP_TIMER_WR_HI 0x980
47269 #define A_MAC_PORT_PTP_TIMER_OFFSET_0 0x984
47270 #define A_MAC_PORT_PTP_TIMER_OFFSET_1 0x988
47271 #define A_MAC_PORT_PTP_TIMER_OFFSET_2 0x98c
47272 
47273 #define S_PTP_OFFSET    0
47274 #define M_PTP_OFFSET    0xffU
47275 #define V_PTP_OFFSET(x) ((x) << S_PTP_OFFSET)
47276 #define G_PTP_OFFSET(x) (((x) >> S_PTP_OFFSET) & M_PTP_OFFSET)
47277 
47278 #define A_MAC_PORT_PTP_SUM_LO 0x990
47279 #define A_MAC_PORT_PTP_SUM_HI 0x994
47280 #define A_MAC_PORT_PTP_TIMER_INCR0 0x998
47281 
47282 #define S_Y    16
47283 #define M_Y    0xffffU
47284 #define V_Y(x) ((x) << S_Y)
47285 #define G_Y(x) (((x) >> S_Y) & M_Y)
47286 
47287 #define S_X    0
47288 #define M_X    0xffffU
47289 #define V_X(x) ((x) << S_X)
47290 #define G_X(x) (((x) >> S_X) & M_X)
47291 
47292 #define A_MAC_PORT_PTP_TIMER_INCR1 0x99c
47293 
47294 #define S_Y_TICK    16
47295 #define M_Y_TICK    0xffffU
47296 #define V_Y_TICK(x) ((x) << S_Y_TICK)
47297 #define G_Y_TICK(x) (((x) >> S_Y_TICK) & M_Y_TICK)
47298 
47299 #define S_X_TICK    0
47300 #define M_X_TICK    0xffffU
47301 #define V_X_TICK(x) ((x) << S_X_TICK)
47302 #define G_X_TICK(x) (((x) >> S_X_TICK) & M_X_TICK)
47303 
47304 #define A_MAC_PORT_PTP_DRIFT_ADJUST_COUNT 0x9a0
47305 #define A_MAC_PORT_PTP_OFFSET_ADJUST_FINE 0x9a4
47306 
47307 #define S_B    16
47308 #define CXGBE_M_B    0xffffU
47309 #define V_B(x) ((x) << S_B)
47310 #define G_B(x) (((x) >> S_B) & CXGBE_M_B)
47311 
47312 #define S_A    0
47313 #define M_A    0xffffU
47314 #define V_A(x) ((x) << S_A)
47315 #define G_A(x) (((x) >> S_A) & M_A)
47316 
47317 #define A_MAC_PORT_PTP_OFFSET_ADJUST_TOTAL 0x9a8
47318 #define A_MAC_PORT_PTP_CFG 0x9ac
47319 
47320 #define S_FRZ    18
47321 #define V_FRZ(x) ((x) << S_FRZ)
47322 #define F_FRZ    V_FRZ(1U)
47323 
47324 #define S_OFFSER_ADJUST_SIGN    17
47325 #define V_OFFSER_ADJUST_SIGN(x) ((x) << S_OFFSER_ADJUST_SIGN)
47326 #define F_OFFSER_ADJUST_SIGN    V_OFFSER_ADJUST_SIGN(1U)
47327 
47328 #define S_ADD_OFFSET    16
47329 #define V_ADD_OFFSET(x) ((x) << S_ADD_OFFSET)
47330 #define F_ADD_OFFSET    V_ADD_OFFSET(1U)
47331 
47332 #define S_CYCLE1    8
47333 #define M_CYCLE1    0xffU
47334 #define V_CYCLE1(x) ((x) << S_CYCLE1)
47335 #define G_CYCLE1(x) (((x) >> S_CYCLE1) & M_CYCLE1)
47336 
47337 #define S_Q    0
47338 #define M_Q    0xffU
47339 #define V_Q(x) ((x) << S_Q)
47340 #define G_Q(x) (((x) >> S_Q) & M_Q)
47341 
47342 #define S_ALARM_EN    21
47343 #define V_ALARM_EN(x) ((x) << S_ALARM_EN)
47344 #define F_ALARM_EN    V_ALARM_EN(1U)
47345 
47346 #define S_ALARM_START    20
47347 #define V_ALARM_START(x) ((x) << S_ALARM_START)
47348 #define F_ALARM_START    V_ALARM_START(1U)
47349 
47350 #define S_PPS_EN    19
47351 #define V_PPS_EN(x) ((x) << S_PPS_EN)
47352 #define F_PPS_EN    V_PPS_EN(1U)
47353 
47354 #define A_MAC_PORT_PTP_PPS 0x9b0
47355 #define A_MAC_PORT_PTP_SINGLE_ALARM 0x9b4
47356 #define A_MAC_PORT_PTP_PERIODIC_ALARM 0x9b8
47357 #define A_MAC_PORT_PTP_STATUS 0x9bc
47358 
47359 #define S_ALARM_DONE    0
47360 #define V_ALARM_DONE(x) ((x) << S_ALARM_DONE)
47361 #define F_ALARM_DONE    V_ALARM_DONE(1U)
47362 
47363 #define A_MAC_PORT_MTIP_REVISION 0xa00
47364 
47365 #define S_CUSTREV    16
47366 #define M_CUSTREV    0xffffU
47367 #define V_CUSTREV(x) ((x) << S_CUSTREV)
47368 #define G_CUSTREV(x) (((x) >> S_CUSTREV) & M_CUSTREV)
47369 
47370 #define S_VER    8
47371 #define M_VER    0xffU
47372 #define V_VER(x) ((x) << S_VER)
47373 #define G_VER(x) (((x) >> S_VER) & M_VER)
47374 
47375 #define S_MTIP_REV    0
47376 #define M_MTIP_REV    0xffU
47377 #define V_MTIP_REV(x) ((x) << S_MTIP_REV)
47378 #define G_MTIP_REV(x) (((x) >> S_MTIP_REV) & M_MTIP_REV)
47379 
47380 #define A_MAC_PORT_MTIP_SCRATCH 0xa04
47381 #define A_MAC_PORT_MTIP_COMMAND_CONFIG 0xa08
47382 
47383 #define S_TX_FLUSH_ENABLE    22
47384 #define V_TX_FLUSH_ENABLE(x) ((x) << S_TX_FLUSH_ENABLE)
47385 #define F_TX_FLUSH_ENABLE    V_TX_FLUSH_ENABLE(1U)
47386 
47387 #define S_RX_SFD_ANY    21
47388 #define V_RX_SFD_ANY(x) ((x) << S_RX_SFD_ANY)
47389 #define F_RX_SFD_ANY    V_RX_SFD_ANY(1U)
47390 
47391 #define S_PAUSE_PFC_COMP    20
47392 #define V_PAUSE_PFC_COMP(x) ((x) << S_PAUSE_PFC_COMP)
47393 #define F_PAUSE_PFC_COMP    V_PAUSE_PFC_COMP(1U)
47394 
47395 #define S_PFC_MODE    19
47396 #define V_PFC_MODE(x) ((x) << S_PFC_MODE)
47397 #define F_PFC_MODE    V_PFC_MODE(1U)
47398 
47399 #define S_RS_COL_CNT_EXT    18
47400 #define V_RS_COL_CNT_EXT(x) ((x) << S_RS_COL_CNT_EXT)
47401 #define F_RS_COL_CNT_EXT    V_RS_COL_CNT_EXT(1U)
47402 
47403 #define S_NO_LGTH_CHECK    17
47404 #define V_NO_LGTH_CHECK(x) ((x) << S_NO_LGTH_CHECK)
47405 #define F_NO_LGTH_CHECK    V_NO_LGTH_CHECK(1U)
47406 
47407 #define S_SEND_IDLE    16
47408 #define V_SEND_IDLE(x) ((x) << S_SEND_IDLE)
47409 #define F_SEND_IDLE    V_SEND_IDLE(1U)
47410 
47411 #define S_PHY_TXENA    15
47412 #define V_PHY_TXENA(x) ((x) << S_PHY_TXENA)
47413 #define F_PHY_TXENA    V_PHY_TXENA(1U)
47414 
47415 #define S_RX_ERR_DISC    14
47416 #define V_RX_ERR_DISC(x) ((x) << S_RX_ERR_DISC)
47417 #define F_RX_ERR_DISC    V_RX_ERR_DISC(1U)
47418 
47419 #define S_CMD_FRAME_ENA    13
47420 #define V_CMD_FRAME_ENA(x) ((x) << S_CMD_FRAME_ENA)
47421 #define F_CMD_FRAME_ENA    V_CMD_FRAME_ENA(1U)
47422 
47423 #define S_SW_RESET    12
47424 #define V_SW_RESET(x) ((x) << S_SW_RESET)
47425 #define F_SW_RESET    V_SW_RESET(1U)
47426 
47427 #define S_TX_PAD_EN    11
47428 #define V_TX_PAD_EN(x) ((x) << S_TX_PAD_EN)
47429 #define F_TX_PAD_EN    V_TX_PAD_EN(1U)
47430 
47431 #define S_PHY_LOOPBACK_EN    10
47432 #define V_PHY_LOOPBACK_EN(x) ((x) << S_PHY_LOOPBACK_EN)
47433 #define F_PHY_LOOPBACK_EN    V_PHY_LOOPBACK_EN(1U)
47434 
47435 #define S_TX_ADDR_INS    9
47436 #define V_TX_ADDR_INS(x) ((x) << S_TX_ADDR_INS)
47437 #define F_TX_ADDR_INS    V_TX_ADDR_INS(1U)
47438 
47439 #define S_PAUSE_IGNORE    8
47440 #define V_PAUSE_IGNORE(x) ((x) << S_PAUSE_IGNORE)
47441 #define F_PAUSE_IGNORE    V_PAUSE_IGNORE(1U)
47442 
47443 #define S_PAUSE_FWD    7
47444 #define V_PAUSE_FWD(x) ((x) << S_PAUSE_FWD)
47445 #define F_PAUSE_FWD    V_PAUSE_FWD(1U)
47446 
47447 #define S_CRC_FWD    6
47448 #define V_CRC_FWD(x) ((x) << S_CRC_FWD)
47449 #define F_CRC_FWD    V_CRC_FWD(1U)
47450 
47451 #define S_PAD_EN    5
47452 #define V_PAD_EN(x) ((x) << S_PAD_EN)
47453 #define F_PAD_EN    V_PAD_EN(1U)
47454 
47455 #define S_PROMIS_EN    4
47456 #define V_PROMIS_EN(x) ((x) << S_PROMIS_EN)
47457 #define F_PROMIS_EN    V_PROMIS_EN(1U)
47458 
47459 #define S_WAN_MODE    3
47460 #define V_WAN_MODE(x) ((x) << S_WAN_MODE)
47461 #define F_WAN_MODE    V_WAN_MODE(1U)
47462 
47463 #define S_RX_ENA    1
47464 #define V_RX_ENA(x) ((x) << S_RX_ENA)
47465 #define F_RX_ENA    V_RX_ENA(1U)
47466 
47467 #define S_TX_ENA    0
47468 #define V_TX_ENA(x) ((x) << S_TX_ENA)
47469 #define F_TX_ENA    V_TX_ENA(1U)
47470 
47471 #define A_MAC_PORT_MTIP_MAC_ADDR_0 0xa0c
47472 #define A_MAC_PORT_MTIP_MAC_ADDR_1 0xa10
47473 
47474 #define S_MACADDRHI    0
47475 #define M_MACADDRHI    0xffffU
47476 #define V_MACADDRHI(x) ((x) << S_MACADDRHI)
47477 #define G_MACADDRHI(x) (((x) >> S_MACADDRHI) & M_MACADDRHI)
47478 
47479 #define A_MAC_PORT_MTIP_FRM_LENGTH 0xa14
47480 
47481 #define S_LEN    0
47482 #define M_LEN    0xffffU
47483 #define V_LEN(x) ((x) << S_LEN)
47484 #define G_LEN(x) (((x) >> S_LEN) & M_LEN)
47485 
47486 #define A_MAC_PORT_MTIP_RX_FIFO_SECTIONS 0xa1c
47487 
47488 #define S_AVAIL    16
47489 #define M_AVAIL    0xffffU
47490 #define V_AVAIL(x) ((x) << S_AVAIL)
47491 #define G_AVAIL(x) (((x) >> S_AVAIL) & M_AVAIL)
47492 
47493 #define S_EMPTY    0
47494 #define M_EMPTY    0xffffU
47495 #define V_EMPTY(x) ((x) << S_EMPTY)
47496 #define G_EMPTY(x) (((x) >> S_EMPTY) & M_EMPTY)
47497 
47498 #define A_MAC_PORT_MTIP_TX_FIFO_SECTIONS 0xa20
47499 #define A_MAC_PORT_MTIP_RX_FIFO_ALMOST_F_E 0xa24
47500 
47501 #define S_ALMSTFULL    16
47502 #define M_ALMSTFULL    0xffffU
47503 #define V_ALMSTFULL(x) ((x) << S_ALMSTFULL)
47504 #define G_ALMSTFULL(x) (((x) >> S_ALMSTFULL) & M_ALMSTFULL)
47505 
47506 #define S_ALMSTEMPTY    0
47507 #define M_ALMSTEMPTY    0xffffU
47508 #define V_ALMSTEMPTY(x) ((x) << S_ALMSTEMPTY)
47509 #define G_ALMSTEMPTY(x) (((x) >> S_ALMSTEMPTY) & M_ALMSTEMPTY)
47510 
47511 #define A_MAC_PORT_MTIP_TX_FIFO_ALMOST_F_E 0xa28
47512 #define A_MAC_PORT_MTIP_HASHTABLE_LOAD 0xa2c
47513 
47514 #define S_ENABLE_MCAST_RX    8
47515 #define V_ENABLE_MCAST_RX(x) ((x) << S_ENABLE_MCAST_RX)
47516 #define F_ENABLE_MCAST_RX    V_ENABLE_MCAST_RX(1U)
47517 
47518 #define S_HASHTABLE_ADDR    0
47519 #define M_HASHTABLE_ADDR    0x3fU
47520 #define V_HASHTABLE_ADDR(x) ((x) << S_HASHTABLE_ADDR)
47521 #define G_HASHTABLE_ADDR(x) (((x) >> S_HASHTABLE_ADDR) & M_HASHTABLE_ADDR)
47522 
47523 #define A_MAC_PORT_MTIP_MAC_STATUS 0xa40
47524 
47525 #define S_TS_AVAIL    3
47526 #define V_TS_AVAIL(x) ((x) << S_TS_AVAIL)
47527 #define F_TS_AVAIL    V_TS_AVAIL(1U)
47528 
47529 #define S_PHY_LOS    2
47530 #define V_PHY_LOS(x) ((x) << S_PHY_LOS)
47531 #define F_PHY_LOS    V_PHY_LOS(1U)
47532 
47533 #define S_RX_REM_FAULT    1
47534 #define V_RX_REM_FAULT(x) ((x) << S_RX_REM_FAULT)
47535 #define F_RX_REM_FAULT    V_RX_REM_FAULT(1U)
47536 
47537 #define S_RX_LOC_FAULT    0
47538 #define V_RX_LOC_FAULT(x) ((x) << S_RX_LOC_FAULT)
47539 #define F_RX_LOC_FAULT    V_RX_LOC_FAULT(1U)
47540 
47541 #define A_MAC_PORT_MTIP_TX_IPG_LENGTH 0xa44
47542 
47543 #define S_IPG    0
47544 #define M_IPG    0x7fU
47545 #define V_IPG(x) ((x) << S_IPG)
47546 #define G_IPG(x) (((x) >> S_IPG) & M_IPG)
47547 
47548 #define A_MAC_PORT_MTIP_MAC_CREDIT_TRIGGER 0xa48
47549 
47550 #define S_RXFIFORST    0
47551 #define V_RXFIFORST(x) ((x) << S_RXFIFORST)
47552 #define F_RXFIFORST    V_RXFIFORST(1U)
47553 
47554 #define A_MAC_PORT_MTIP_INIT_CREDIT 0xa4c
47555 
47556 #define S_MACCRDRST    0
47557 #define M_MACCRDRST    0xffU
47558 #define V_MACCRDRST(x) ((x) << S_MACCRDRST)
47559 #define G_MACCRDRST(x) (((x) >> S_MACCRDRST) & M_MACCRDRST)
47560 
47561 #define A_MAC_PORT_MTIP_CURRENT_CREDIT 0xa50
47562 
47563 #define S_INITCREDIT    0
47564 #define M_INITCREDIT    0xffU
47565 #define V_INITCREDIT(x) ((x) << S_INITCREDIT)
47566 #define G_INITCREDIT(x) (((x) >> S_INITCREDIT) & M_INITCREDIT)
47567 
47568 #define A_MAC_PORT_RX_PAUSE_STATUS 0xa74
47569 
47570 #define S_STATUS    0
47571 #define M_STATUS    0xffU
47572 #define V_STATUS(x) ((x) << S_STATUS)
47573 #define G_STATUS(x) (((x) >> S_STATUS) & M_STATUS)
47574 
47575 #define A_MAC_PORT_MTIP_TS_TIMESTAMP 0xa7c
47576 #define A_MAC_PORT_AFRAMESTRANSMITTEDOK 0xa80
47577 #define A_MAC_PORT_AFRAMESTRANSMITTEDOKHI 0xa84
47578 #define A_MAC_PORT_AFRAMESRECEIVEDOK 0xa88
47579 #define A_MAC_PORT_AFRAMESRECEIVEDOKHI 0xa8c
47580 #define A_MAC_PORT_AFRAMECHECKSEQUENCEERRORS 0xa90
47581 #define A_MAC_PORT_AFRAMECHECKSEQUENCEERRORSHI 0xa94
47582 #define A_MAC_PORT_AALIGNMENTERRORS 0xa98
47583 #define A_MAC_PORT_AALIGNMENTERRORSHI 0xa9c
47584 #define A_MAC_PORT_APAUSEMACCTRLFRAMESTRANSMITTED 0xaa0
47585 #define A_MAC_PORT_APAUSEMACCTRLFRAMESTRANSMITTEDHI 0xaa4
47586 #define A_MAC_PORT_APAUSEMACCTRLFRAMESRECEIVED 0xaa8
47587 #define A_MAC_PORT_APAUSEMACCTRLFRAMESRECEIVEDHI 0xaac
47588 #define A_MAC_PORT_AFRAMETOOLONGERRORS 0xab0
47589 #define A_MAC_PORT_AFRAMETOOLONGERRORSHI 0xab4
47590 #define A_MAC_PORT_AINRANGELENGTHERRORS 0xab8
47591 #define A_MAC_PORT_AINRANGELENGTHERRORSHI 0xabc
47592 #define A_MAC_PORT_VLANTRANSMITTEDOK 0xac0
47593 #define A_MAC_PORT_VLANTRANSMITTEDOKHI 0xac4
47594 #define A_MAC_PORT_VLANRECEIVEDOK 0xac8
47595 #define A_MAC_PORT_VLANRECEIVEDOKHI 0xacc
47596 #define A_MAC_PORT_AOCTETSTRANSMITTEDOK 0xad0
47597 #define A_MAC_PORT_AOCTETSTRANSMITTEDOKHI 0xad4
47598 #define A_MAC_PORT_AOCTETSRECEIVEDOK 0xad8
47599 #define A_MAC_PORT_AOCTETSRECEIVEDOKHI 0xadc
47600 #define A_MAC_PORT_IFINUCASTPKTS 0xae0
47601 #define A_MAC_PORT_IFINUCASTPKTSHI 0xae4
47602 #define A_MAC_PORT_IFINMULTICASTPKTS 0xae8
47603 #define A_MAC_PORT_IFINMULTICASTPKTSHI 0xaec
47604 #define A_MAC_PORT_IFINBROADCASTPKTS 0xaf0
47605 #define A_MAC_PORT_IFINBROADCASTPKTSHI 0xaf4
47606 #define A_MAC_PORT_IFOUTERRORS 0xaf8
47607 #define A_MAC_PORT_IFOUTERRORSHI 0xafc
47608 #define A_MAC_PORT_IFOUTUCASTPKTS 0xb08
47609 #define A_MAC_PORT_IFOUTUCASTPKTSHI 0xb0c
47610 #define A_MAC_PORT_IFOUTMULTICASTPKTS 0xb10
47611 #define A_MAC_PORT_IFOUTMULTICASTPKTSHI 0xb14
47612 #define A_MAC_PORT_IFOUTBROADCASTPKTS 0xb18
47613 #define A_MAC_PORT_IFOUTBROADCASTPKTSHI 0xb1c
47614 #define A_MAC_PORT_ETHERSTATSDROPEVENTS 0xb20
47615 #define A_MAC_PORT_ETHERSTATSDROPEVENTSHI 0xb24
47616 #define A_MAC_PORT_ETHERSTATSOCTETS 0xb28
47617 #define A_MAC_PORT_ETHERSTATSOCTETSHI 0xb2c
47618 #define A_MAC_PORT_ETHERSTATSPKTS 0xb30
47619 #define A_MAC_PORT_ETHERSTATSPKTSHI 0xb34
47620 #define A_MAC_PORT_ETHERSTATSUNDERSIZEPKTS 0xb38
47621 #define A_MAC_PORT_ETHERSTATSUNDERSIZEPKTSHI 0xb3c
47622 #define A_MAC_PORT_ETHERSTATSPKTS64OCTETS 0xb40
47623 #define A_MAC_PORT_ETHERSTATSPKTS64OCTETSHI 0xb44
47624 #define A_MAC_PORT_ETHERSTATSPKTS65TO127OCTETS 0xb48
47625 #define A_MAC_PORT_ETHERSTATSPKTS65TO127OCTETSHI 0xb4c
47626 #define A_MAC_PORT_ETHERSTATSPKTS128TO255OCTETS 0xb50
47627 #define A_MAC_PORT_ETHERSTATSPKTS128TO255OCTETSHI 0xb54
47628 #define A_MAC_PORT_ETHERSTATSPKTS256TO511OCTETS 0xb58
47629 #define A_MAC_PORT_ETHERSTATSPKTS256TO511OCTETSHI 0xb5c
47630 #define A_MAC_PORT_ETHERSTATSPKTS512TO1023OCTETS 0xb60
47631 #define A_MAC_PORT_ETHERSTATSPKTS512TO1023OCTETSHI 0xb64
47632 #define A_MAC_PORT_ETHERSTATSPKTS1024TO1518OCTETS 0xb68
47633 #define A_MAC_PORT_ETHERSTATSPKTS1024TO1518OCTETSHI 0xb6c
47634 #define A_MAC_PORT_ETHERSTATSPKTS1519TOMAXOCTETS 0xb70
47635 #define A_MAC_PORT_ETHERSTATSPKTS1519TOMAXOCTETSHI 0xb74
47636 #define A_MAC_PORT_ETHERSTATSOVERSIZEPKTS 0xb78
47637 #define A_MAC_PORT_ETHERSTATSOVERSIZEPKTSHI 0xb7c
47638 #define A_MAC_PORT_ETHERSTATSJABBERS 0xb80
47639 #define A_MAC_PORT_ETHERSTATSJABBERSHI 0xb84
47640 #define A_MAC_PORT_ETHERSTATSFRAGMENTS 0xb88
47641 #define A_MAC_PORT_ETHERSTATSFRAGMENTSHI 0xb8c
47642 #define A_MAC_PORT_IFINERRORS 0xb90
47643 #define A_MAC_PORT_IFINERRORSHI 0xb94
47644 #define A_MAC_PORT_ACBFCPAUSEFRAMESTRANSMITTED_0 0xb98
47645 #define A_MAC_PORT_ACBFCPAUSEFRAMESTRANSMITTED_0HI 0xb9c
47646 #define A_MAC_PORT_ACBFCPAUSEFRAMESTRANSMITTED_1 0xba0
47647 #define A_MAC_PORT_ACBFCPAUSEFRAMESTRANSMITTED_1HI 0xba4
47648 #define A_MAC_PORT_ACBFCPAUSEFRAMESTRANSMITTED_2 0xba8
47649 #define A_MAC_PORT_ACBFCPAUSEFRAMESTRANSMITTED_2HI 0xbac
47650 #define A_MAC_PORT_ACBFCPAUSEFRAMESTRANSMITTED_3 0xbb0
47651 #define A_MAC_PORT_ACBFCPAUSEFRAMESTRANSMITTED_3HI 0xbb4
47652 #define A_MAC_PORT_ACBFCPAUSEFRAMESTRANSMITTED_4 0xbb8
47653 #define A_MAC_PORT_ACBFCPAUSEFRAMESTRANSMITTED_4HI 0xbbc
47654 #define A_MAC_PORT_ACBFCPAUSEFRAMESTRANSMITTED_5 0xbc0
47655 #define A_MAC_PORT_ACBFCPAUSEFRAMESTRANSMITTED_5HI 0xbc4
47656 #define A_MAC_PORT_ACBFCPAUSEFRAMESTRANSMITTED_6 0xbc8
47657 #define A_MAC_PORT_ACBFCPAUSEFRAMESTRANSMITTED_6HI 0xbcc
47658 #define A_MAC_PORT_ACBFCPAUSEFRAMESTRANSMITTED_7 0xbd0
47659 #define A_MAC_PORT_ACBFCPAUSEFRAMESTRANSMITTED_7HI 0xbd4
47660 #define A_MAC_PORT_ACBFCPAUSEFRAMESRECEIVED_0 0xbd8
47661 #define A_MAC_PORT_ACBFCPAUSEFRAMESRECEIVED_0HI 0xbdc
47662 #define A_MAC_PORT_ACBFCPAUSEFRAMESRECEIVED_1 0xbe0
47663 #define A_MAC_PORT_ACBFCPAUSEFRAMESRECEIVED_1HI 0xbe4
47664 #define A_MAC_PORT_ACBFCPAUSEFRAMESRECEIVED_2 0xbe8
47665 #define A_MAC_PORT_ACBFCPAUSEFRAMESRECEIVED_2HI 0xbec
47666 #define A_MAC_PORT_ACBFCPAUSEFRAMESRECEIVED_3 0xbf0
47667 #define A_MAC_PORT_ACBFCPAUSEFRAMESRECEIVED_3HI 0xbf4
47668 #define A_MAC_PORT_ACBFCPAUSEFRAMESRECEIVED_4 0xbf8
47669 #define A_MAC_PORT_ACBFCPAUSEFRAMESRECEIVED_4HI 0xbfc
47670 #define A_MAC_PORT_ACBFCPAUSEFRAMESRECEIVED_5 0xc00
47671 #define A_MAC_PORT_ACBFCPAUSEFRAMESRECEIVED_5HI 0xc04
47672 #define A_MAC_PORT_ACBFCPAUSEFRAMESRECEIVED_6 0xc08
47673 #define A_MAC_PORT_ACBFCPAUSEFRAMESRECEIVED_6HI 0xc0c
47674 #define A_MAC_PORT_ACBFCPAUSEFRAMESRECEIVED_7 0xc10
47675 #define A_MAC_PORT_ACBFCPAUSEFRAMESRECEIVED_7HI 0xc14
47676 #define A_MAC_PORT_AMACCONTROLFRAMESTRANSMITTED 0xc18
47677 #define A_MAC_PORT_AMACCONTROLFRAMESTRANSMITTEDHI 0xc1c
47678 #define A_MAC_PORT_AMACCONTROLFRAMESRECEIVED 0xc20
47679 #define A_MAC_PORT_AMACCONTROLFRAMESRECEIVEDHI 0xc24
47680 #define A_MAC_PORT_MTIP_SGMII_CONTROL 0xd00
47681 
47682 #define S_RESET    15
47683 #define V_RESET(x) ((x) << S_RESET)
47684 #define F_RESET    V_RESET(1U)
47685 
47686 #define S_LOOPBACK    14
47687 #define V_LOOPBACK(x) ((x) << S_LOOPBACK)
47688 #define F_LOOPBACK    V_LOOPBACK(1U)
47689 
47690 #define S_SPPEDSEL1    13
47691 #define V_SPPEDSEL1(x) ((x) << S_SPPEDSEL1)
47692 #define F_SPPEDSEL1    V_SPPEDSEL1(1U)
47693 
47694 #define S_AN_EN    12
47695 #define V_AN_EN(x) ((x) << S_AN_EN)
47696 #define F_AN_EN    V_AN_EN(1U)
47697 
47698 #define S_PWRDWN    11
47699 #define V_PWRDWN(x) ((x) << S_PWRDWN)
47700 #define F_PWRDWN    V_PWRDWN(1U)
47701 
47702 #define S_ISOLATE    10
47703 #define V_ISOLATE(x) ((x) << S_ISOLATE)
47704 #define F_ISOLATE    V_ISOLATE(1U)
47705 
47706 #define S_AN_RESTART    9
47707 #define V_AN_RESTART(x) ((x) << S_AN_RESTART)
47708 #define F_AN_RESTART    V_AN_RESTART(1U)
47709 
47710 #define S_DPLX    8
47711 #define V_DPLX(x) ((x) << S_DPLX)
47712 #define F_DPLX    V_DPLX(1U)
47713 
47714 #define S_COLLISIONTEST    7
47715 #define V_COLLISIONTEST(x) ((x) << S_COLLISIONTEST)
47716 #define F_COLLISIONTEST    V_COLLISIONTEST(1U)
47717 
47718 #define S_SPEEDSEL0    6
47719 #define V_SPEEDSEL0(x) ((x) << S_SPEEDSEL0)
47720 #define F_SPEEDSEL0    V_SPEEDSEL0(1U)
47721 
47722 #define A_MAC_PORT_MTIP_1G10G_REVISION 0xd00
47723 
47724 #define S_VER_1G10G    8
47725 #define M_VER_1G10G    0xffU
47726 #define V_VER_1G10G(x) ((x) << S_VER_1G10G)
47727 #define G_VER_1G10G(x) (((x) >> S_VER_1G10G) & M_VER_1G10G)
47728 
47729 #define S_REV_1G10G    0
47730 #define M_REV_1G10G    0xffU
47731 #define V_REV_1G10G(x) ((x) << S_REV_1G10G)
47732 #define G_REV_1G10G(x) (((x) >> S_REV_1G10G) & M_REV_1G10G)
47733 
47734 #define A_MAC_PORT_MTIP_SGMII_STATUS 0xd04
47735 
47736 #define S_100BASET4    15
47737 #define V_100BASET4(x) ((x) << S_100BASET4)
47738 #define F_100BASET4    V_100BASET4(1U)
47739 
47740 #define S_100BASEXFULLDPLX    14
47741 #define V_100BASEXFULLDPLX(x) ((x) << S_100BASEXFULLDPLX)
47742 #define F_100BASEXFULLDPLX    V_100BASEXFULLDPLX(1U)
47743 
47744 #define S_100BASEXHALFDPLX    13
47745 #define V_100BASEXHALFDPLX(x) ((x) << S_100BASEXHALFDPLX)
47746 #define F_100BASEXHALFDPLX    V_100BASEXHALFDPLX(1U)
47747 
47748 #define S_10MBPSFULLDPLX    12
47749 #define V_10MBPSFULLDPLX(x) ((x) << S_10MBPSFULLDPLX)
47750 #define F_10MBPSFULLDPLX    V_10MBPSFULLDPLX(1U)
47751 
47752 #define S_10MBPSHALFDPLX    11
47753 #define V_10MBPSHALFDPLX(x) ((x) << S_10MBPSHALFDPLX)
47754 #define F_10MBPSHALFDPLX    V_10MBPSHALFDPLX(1U)
47755 
47756 #define S_100BASET2FULLDPLX    10
47757 #define V_100BASET2FULLDPLX(x) ((x) << S_100BASET2FULLDPLX)
47758 #define F_100BASET2FULLDPLX    V_100BASET2FULLDPLX(1U)
47759 
47760 #define S_100BASET2HALFDPLX    9
47761 #define V_100BASET2HALFDPLX(x) ((x) << S_100BASET2HALFDPLX)
47762 #define F_100BASET2HALFDPLX    V_100BASET2HALFDPLX(1U)
47763 
47764 #define S_EXTDSTATUS    8
47765 #define V_EXTDSTATUS(x) ((x) << S_EXTDSTATUS)
47766 #define F_EXTDSTATUS    V_EXTDSTATUS(1U)
47767 
47768 #define S_SGMII_REM_FAULT    4
47769 #define V_SGMII_REM_FAULT(x) ((x) << S_SGMII_REM_FAULT)
47770 #define F_SGMII_REM_FAULT    V_SGMII_REM_FAULT(1U)
47771 
47772 #define S_JABBERDETECT    1
47773 #define V_JABBERDETECT(x) ((x) << S_JABBERDETECT)
47774 #define F_JABBERDETECT    V_JABBERDETECT(1U)
47775 
47776 #define S_EXTDCAPABILITY    0
47777 #define V_EXTDCAPABILITY(x) ((x) << S_EXTDCAPABILITY)
47778 #define F_EXTDCAPABILITY    V_EXTDCAPABILITY(1U)
47779 
47780 #define A_MAC_PORT_MTIP_1G10G_SCRATCH 0xd04
47781 #define A_MAC_PORT_MTIP_SGMII_PHY_IDENTIFIER_0 0xd08
47782 #define A_MAC_PORT_MTIP_1G10G_COMMAND_CONFIG 0xd08
47783 
47784 #define S_SHORT_DISCARD    25
47785 #define V_SHORT_DISCARD(x) ((x) << S_SHORT_DISCARD)
47786 #define F_SHORT_DISCARD    V_SHORT_DISCARD(1U)
47787 
47788 #define S_REG_LOWP_RXEMPTY    24
47789 #define V_REG_LOWP_RXEMPTY(x) ((x) << S_REG_LOWP_RXEMPTY)
47790 #define F_REG_LOWP_RXEMPTY    V_REG_LOWP_RXEMPTY(1U)
47791 
47792 #define S_TX_LOWP_ENA    23
47793 #define V_TX_LOWP_ENA(x) ((x) << S_TX_LOWP_ENA)
47794 #define F_TX_LOWP_ENA    V_TX_LOWP_ENA(1U)
47795 
47796 #define S_TX_FLUSH_EN    22
47797 #define V_TX_FLUSH_EN(x) ((x) << S_TX_FLUSH_EN)
47798 #define F_TX_FLUSH_EN    V_TX_FLUSH_EN(1U)
47799 
47800 #define S_SFD_ANY    21
47801 #define V_SFD_ANY(x) ((x) << S_SFD_ANY)
47802 #define F_SFD_ANY    V_SFD_ANY(1U)
47803 
47804 #define S_COL_CNT_EXT    18
47805 #define V_COL_CNT_EXT(x) ((x) << S_COL_CNT_EXT)
47806 #define F_COL_CNT_EXT    V_COL_CNT_EXT(1U)
47807 
47808 #define S_FORCE_SEND_IDLE    16
47809 #define V_FORCE_SEND_IDLE(x) ((x) << S_FORCE_SEND_IDLE)
47810 #define F_FORCE_SEND_IDLE    V_FORCE_SEND_IDLE(1U)
47811 
47812 #define S_CNTL_FRM_ENA    13
47813 #define V_CNTL_FRM_ENA(x) ((x) << S_CNTL_FRM_ENA)
47814 #define F_CNTL_FRM_ENA    V_CNTL_FRM_ENA(1U)
47815 
47816 #define S_RX_ENAMAC    1
47817 #define V_RX_ENAMAC(x) ((x) << S_RX_ENAMAC)
47818 #define F_RX_ENAMAC    V_RX_ENAMAC(1U)
47819 
47820 #define S_TX_ENAMAC    0
47821 #define V_TX_ENAMAC(x) ((x) << S_TX_ENAMAC)
47822 #define F_TX_ENAMAC    V_TX_ENAMAC(1U)
47823 
47824 #define A_MAC_PORT_MTIP_SGMII_PHY_IDENTIFIER_1 0xd0c
47825 #define A_MAC_PORT_MTIP_1G10G_MAC_ADDR_0 0xd0c
47826 #define A_MAC_PORT_MTIP_SGMII_DEV_ABILITY 0xd10
47827 
47828 #define S_RF2    13
47829 #define V_RF2(x) ((x) << S_RF2)
47830 #define F_RF2    V_RF2(1U)
47831 
47832 #define S_RF1    12
47833 #define V_RF1(x) ((x) << S_RF1)
47834 #define F_RF1    V_RF1(1U)
47835 
47836 #define S_PS2    8
47837 #define V_PS2(x) ((x) << S_PS2)
47838 #define F_PS2    V_PS2(1U)
47839 
47840 #define S_PS1    7
47841 #define V_PS1(x) ((x) << S_PS1)
47842 #define F_PS1    V_PS1(1U)
47843 
47844 #define S_HD    6
47845 #define V_HD(x) ((x) << S_HD)
47846 #define F_HD    V_HD(1U)
47847 
47848 #define S_FD    5
47849 #define V_FD(x) ((x) << S_FD)
47850 #define F_FD    V_FD(1U)
47851 
47852 #define A_MAC_PORT_MTIP_1G10G_MAC_ADDR_1 0xd10
47853 #define A_MAC_PORT_MTIP_SGMII_PARTNER_ABILITY 0xd14
47854 
47855 #define S_CULINKSTATUS    15
47856 #define V_CULINKSTATUS(x) ((x) << S_CULINKSTATUS)
47857 #define F_CULINKSTATUS    V_CULINKSTATUS(1U)
47858 
47859 #define S_CUDPLXSTATUS    12
47860 #define V_CUDPLXSTATUS(x) ((x) << S_CUDPLXSTATUS)
47861 #define F_CUDPLXSTATUS    V_CUDPLXSTATUS(1U)
47862 
47863 #define S_CUSPEED    10
47864 #define M_CUSPEED    0x3U
47865 #define V_CUSPEED(x) ((x) << S_CUSPEED)
47866 #define G_CUSPEED(x) (((x) >> S_CUSPEED) & M_CUSPEED)
47867 
47868 #define A_MAC_PORT_MTIP_1G10G_FRM_LENGTH_TX_MTU 0xd14
47869 
47870 #define S_SET_LEN    16
47871 #define M_SET_LEN    0xffffU
47872 #define V_SET_LEN(x) ((x) << S_SET_LEN)
47873 #define G_SET_LEN(x) (((x) >> S_SET_LEN) & M_SET_LEN)
47874 
47875 #define S_FRM_LEN_SET    0
47876 #define M_FRM_LEN_SET    0xffffU
47877 #define V_FRM_LEN_SET(x) ((x) << S_FRM_LEN_SET)
47878 #define G_FRM_LEN_SET(x) (((x) >> S_FRM_LEN_SET) & M_FRM_LEN_SET)
47879 
47880 #define A_MAC_PORT_MTIP_SGMII_AN_EXPANSION 0xd18
47881 
47882 #define S_PGRCVD    1
47883 #define V_PGRCVD(x) ((x) << S_PGRCVD)
47884 #define F_PGRCVD    V_PGRCVD(1U)
47885 
47886 #define S_REALTIMEPGRCVD    0
47887 #define V_REALTIMEPGRCVD(x) ((x) << S_REALTIMEPGRCVD)
47888 #define F_REALTIMEPGRCVD    V_REALTIMEPGRCVD(1U)
47889 
47890 #define A_MAC_PORT_MTIP_SGMII_DEVICE_NP 0xd1c
47891 #define A_MAC_PORT_MTIP_1G10G_RX_FIFO_SECTIONS 0xd1c
47892 
47893 #define S_RX1G10G_EMPTY    16
47894 #define M_RX1G10G_EMPTY    0xffffU
47895 #define V_RX1G10G_EMPTY(x) ((x) << S_RX1G10G_EMPTY)
47896 #define G_RX1G10G_EMPTY(x) (((x) >> S_RX1G10G_EMPTY) & M_RX1G10G_EMPTY)
47897 
47898 #define S_RX1G10G_AVAIL    0
47899 #define M_RX1G10G_AVAIL    0xffffU
47900 #define V_RX1G10G_AVAIL(x) ((x) << S_RX1G10G_AVAIL)
47901 #define G_RX1G10G_AVAIL(x) (((x) >> S_RX1G10G_AVAIL) & M_RX1G10G_AVAIL)
47902 
47903 #define A_MAC_PORT_MTIP_SGMII_PARTNER_NP 0xd20
47904 #define A_MAC_PORT_MTIP_1G10G_TX_FIFO_SECTIONS 0xd20
47905 
47906 #define S_TX1G10G_EMPTY    16
47907 #define M_TX1G10G_EMPTY    0xffffU
47908 #define V_TX1G10G_EMPTY(x) ((x) << S_TX1G10G_EMPTY)
47909 #define G_TX1G10G_EMPTY(x) (((x) >> S_TX1G10G_EMPTY) & M_TX1G10G_EMPTY)
47910 
47911 #define S_TX1G10G_AVAIL    0
47912 #define M_TX1G10G_AVAIL    0xffffU
47913 #define V_TX1G10G_AVAIL(x) ((x) << S_TX1G10G_AVAIL)
47914 #define G_TX1G10G_AVAIL(x) (((x) >> S_TX1G10G_AVAIL) & M_TX1G10G_AVAIL)
47915 
47916 #define A_MAC_PORT_MTIP_1G10G_RX_FIFO_ALMOST_F_E 0xd24
47917 
47918 #define S_ALMOSTFULL    16
47919 #define M_ALMOSTFULL    0xffffU
47920 #define V_ALMOSTFULL(x) ((x) << S_ALMOSTFULL)
47921 #define G_ALMOSTFULL(x) (((x) >> S_ALMOSTFULL) & M_ALMOSTFULL)
47922 
47923 #define S_ALMOSTEMPTY    0
47924 #define M_ALMOSTEMPTY    0xffffU
47925 #define V_ALMOSTEMPTY(x) ((x) << S_ALMOSTEMPTY)
47926 #define G_ALMOSTEMPTY(x) (((x) >> S_ALMOSTEMPTY) & M_ALMOSTEMPTY)
47927 
47928 #define A_MAC_PORT_MTIP_1G10G_TX_FIFO_ALMOST_F_E 0xd28
47929 #define A_MAC_PORT_MTIP_1G10G_HASHTABLE_LOAD 0xd2c
47930 #define A_MAC_PORT_MTIP_1G10G_MDIO_CFG_STATUS 0xd30
47931 
47932 #define S_CLK_DIVISOR    7
47933 #define M_CLK_DIVISOR    0x1ffU
47934 #define V_CLK_DIVISOR(x) ((x) << S_CLK_DIVISOR)
47935 #define G_CLK_DIVISOR(x) (((x) >> S_CLK_DIVISOR) & M_CLK_DIVISOR)
47936 
47937 #define S_ENA_CLAUSE    6
47938 #define V_ENA_CLAUSE(x) ((x) << S_ENA_CLAUSE)
47939 #define F_ENA_CLAUSE    V_ENA_CLAUSE(1U)
47940 
47941 #define S_PREAMBLE_DISABLE    5
47942 #define V_PREAMBLE_DISABLE(x) ((x) << S_PREAMBLE_DISABLE)
47943 #define F_PREAMBLE_DISABLE    V_PREAMBLE_DISABLE(1U)
47944 
47945 #define S_HOLD_TIME_SETTING    2
47946 #define M_HOLD_TIME_SETTING    0x7U
47947 #define V_HOLD_TIME_SETTING(x) ((x) << S_HOLD_TIME_SETTING)
47948 #define G_HOLD_TIME_SETTING(x) (((x) >> S_HOLD_TIME_SETTING) & M_HOLD_TIME_SETTING)
47949 
47950 #define S_MDIO_READ_ERROR    1
47951 #define V_MDIO_READ_ERROR(x) ((x) << S_MDIO_READ_ERROR)
47952 #define F_MDIO_READ_ERROR    V_MDIO_READ_ERROR(1U)
47953 
47954 #define A_MAC_PORT_MTIP_1G10G_MDIO_COMMAND 0xd34
47955 
47956 #define S_READ_MODE    15
47957 #define V_READ_MODE(x) ((x) << S_READ_MODE)
47958 #define F_READ_MODE    V_READ_MODE(1U)
47959 
47960 #define S_POST_INCR_READ    14
47961 #define V_POST_INCR_READ(x) ((x) << S_POST_INCR_READ)
47962 #define F_POST_INCR_READ    V_POST_INCR_READ(1U)
47963 
47964 #define S_PORT_PHY_ADDR    5
47965 #define M_PORT_PHY_ADDR    0x1fU
47966 #define V_PORT_PHY_ADDR(x) ((x) << S_PORT_PHY_ADDR)
47967 #define G_PORT_PHY_ADDR(x) (((x) >> S_PORT_PHY_ADDR) & M_PORT_PHY_ADDR)
47968 
47969 #define S_DEVICE_REG_ADDR    0
47970 #define M_DEVICE_REG_ADDR    0x1fU
47971 #define V_DEVICE_REG_ADDR(x) ((x) << S_DEVICE_REG_ADDR)
47972 #define G_DEVICE_REG_ADDR(x) (((x) >> S_DEVICE_REG_ADDR) & M_DEVICE_REG_ADDR)
47973 
47974 #define A_MAC_PORT_MTIP_1G10G_MDIO_DATA 0xd38
47975 
47976 #define S_MDIO_DATA    0
47977 #define M_MDIO_DATA    0xffffU
47978 #define V_MDIO_DATA(x) ((x) << S_MDIO_DATA)
47979 #define G_MDIO_DATA(x) (((x) >> S_MDIO_DATA) & M_MDIO_DATA)
47980 
47981 #define A_MAC_PORT_MTIP_SGMII_EXTENDED_STATUS 0xd3c
47982 #define A_MAC_PORT_MTIP_1G10G_MDIO_REGADDR 0xd3c
47983 #define A_MAC_PORT_MTIP_1G10G_STATUS 0xd40
47984 
47985 #define S_RX_LINT_FAULT    7
47986 #define V_RX_LINT_FAULT(x) ((x) << S_RX_LINT_FAULT)
47987 #define F_RX_LINT_FAULT    V_RX_LINT_FAULT(1U)
47988 
47989 #define S_RX_EMPTY    6
47990 #define V_RX_EMPTY(x) ((x) << S_RX_EMPTY)
47991 #define F_RX_EMPTY    V_RX_EMPTY(1U)
47992 
47993 #define S_TX_EMPTY    5
47994 #define V_TX_EMPTY(x) ((x) << S_TX_EMPTY)
47995 #define F_TX_EMPTY    V_TX_EMPTY(1U)
47996 
47997 #define S_RX_LOWP    4
47998 #define V_RX_LOWP(x) ((x) << S_RX_LOWP)
47999 #define F_RX_LOWP    V_RX_LOWP(1U)
48000 
48001 #define A_MAC_PORT_MTIP_1G10G_TX_IPG_LENGTH 0xd44
48002 #define A_MAC_PORT_MTIP_SGMII_LINK_TIMER_LO 0xd48
48003 
48004 #define S_COUNT_LO    0
48005 #define M_COUNT_LO    0xffffU
48006 #define V_COUNT_LO(x) ((x) << S_COUNT_LO)
48007 #define G_COUNT_LO(x) (((x) >> S_COUNT_LO) & M_COUNT_LO)
48008 
48009 #define A_MAC_PORT_MTIP_1G10G_CREDIT_TRIGGER 0xd48
48010 #define A_MAC_PORT_MTIP_SGMII_LINK_TIMER_HI 0xd4c
48011 
48012 #define S_COUNT_HI    0
48013 #define M_COUNT_HI    0x1fU
48014 #define V_COUNT_HI(x) ((x) << S_COUNT_HI)
48015 #define G_COUNT_HI(x) (((x) >> S_COUNT_HI) & M_COUNT_HI)
48016 
48017 #define A_MAC_PORT_MTIP_1G10G_INIT_CREDIT 0xd4c
48018 #define A_MAC_PORT_MTIP_SGMII_IF_MODE 0xd50
48019 
48020 #define S_SGMII_PCS_ENABLE    5
48021 #define V_SGMII_PCS_ENABLE(x) ((x) << S_SGMII_PCS_ENABLE)
48022 #define F_SGMII_PCS_ENABLE    V_SGMII_PCS_ENABLE(1U)
48023 
48024 #define S_SGMII_HDUPLEX    4
48025 #define V_SGMII_HDUPLEX(x) ((x) << S_SGMII_HDUPLEX)
48026 #define F_SGMII_HDUPLEX    V_SGMII_HDUPLEX(1U)
48027 
48028 #define S_SGMII_SPEED    2
48029 #define M_SGMII_SPEED    0x3U
48030 #define V_SGMII_SPEED(x) ((x) << S_SGMII_SPEED)
48031 #define G_SGMII_SPEED(x) (((x) >> S_SGMII_SPEED) & M_SGMII_SPEED)
48032 
48033 #define S_USE_SGMII_AN    1
48034 #define V_USE_SGMII_AN(x) ((x) << S_USE_SGMII_AN)
48035 #define F_USE_SGMII_AN    V_USE_SGMII_AN(1U)
48036 
48037 #define S_SGMII_ENA    0
48038 #define V_SGMII_ENA(x) ((x) << S_SGMII_ENA)
48039 #define F_SGMII_ENA    V_SGMII_ENA(1U)
48040 
48041 #define A_MAC_PORT_MTIP_1G10G_CL01_PAUSE_QUANTA 0xd54
48042 
48043 #define S_CL1_PAUSE_QUANTA    16
48044 #define M_CL1_PAUSE_QUANTA    0xffffU
48045 #define V_CL1_PAUSE_QUANTA(x) ((x) << S_CL1_PAUSE_QUANTA)
48046 #define G_CL1_PAUSE_QUANTA(x) (((x) >> S_CL1_PAUSE_QUANTA) & M_CL1_PAUSE_QUANTA)
48047 
48048 #define S_CL0_PAUSE_QUANTA    0
48049 #define M_CL0_PAUSE_QUANTA    0xffffU
48050 #define V_CL0_PAUSE_QUANTA(x) ((x) << S_CL0_PAUSE_QUANTA)
48051 #define G_CL0_PAUSE_QUANTA(x) (((x) >> S_CL0_PAUSE_QUANTA) & M_CL0_PAUSE_QUANTA)
48052 
48053 #define A_MAC_PORT_MTIP_1G10G_CL23_PAUSE_QUANTA 0xd58
48054 
48055 #define S_CL3_PAUSE_QUANTA    16
48056 #define M_CL3_PAUSE_QUANTA    0xffffU
48057 #define V_CL3_PAUSE_QUANTA(x) ((x) << S_CL3_PAUSE_QUANTA)
48058 #define G_CL3_PAUSE_QUANTA(x) (((x) >> S_CL3_PAUSE_QUANTA) & M_CL3_PAUSE_QUANTA)
48059 
48060 #define S_CL2_PAUSE_QUANTA    0
48061 #define M_CL2_PAUSE_QUANTA    0xffffU
48062 #define V_CL2_PAUSE_QUANTA(x) ((x) << S_CL2_PAUSE_QUANTA)
48063 #define G_CL2_PAUSE_QUANTA(x) (((x) >> S_CL2_PAUSE_QUANTA) & M_CL2_PAUSE_QUANTA)
48064 
48065 #define A_MAC_PORT_MTIP_1G10G_CL45_PAUSE_QUANTA 0xd5c
48066 
48067 #define S_CL5_PAUSE_QUANTA    16
48068 #define M_CL5_PAUSE_QUANTA    0xffffU
48069 #define V_CL5_PAUSE_QUANTA(x) ((x) << S_CL5_PAUSE_QUANTA)
48070 #define G_CL5_PAUSE_QUANTA(x) (((x) >> S_CL5_PAUSE_QUANTA) & M_CL5_PAUSE_QUANTA)
48071 
48072 #define S_CL4_PAUSE_QUANTA    0
48073 #define M_CL4_PAUSE_QUANTA    0xffffU
48074 #define V_CL4_PAUSE_QUANTA(x) ((x) << S_CL4_PAUSE_QUANTA)
48075 #define G_CL4_PAUSE_QUANTA(x) (((x) >> S_CL4_PAUSE_QUANTA) & M_CL4_PAUSE_QUANTA)
48076 
48077 #define A_MAC_PORT_MTIP_1G10G_CL67_PAUSE_QUANTA 0xd60
48078 
48079 #define S_CL7_PAUSE_QUANTA    16
48080 #define M_CL7_PAUSE_QUANTA    0xffffU
48081 #define V_CL7_PAUSE_QUANTA(x) ((x) << S_CL7_PAUSE_QUANTA)
48082 #define G_CL7_PAUSE_QUANTA(x) (((x) >> S_CL7_PAUSE_QUANTA) & M_CL7_PAUSE_QUANTA)
48083 
48084 #define S_CL6_PAUSE_QUANTA    0
48085 #define M_CL6_PAUSE_QUANTA    0xffffU
48086 #define V_CL6_PAUSE_QUANTA(x) ((x) << S_CL6_PAUSE_QUANTA)
48087 #define G_CL6_PAUSE_QUANTA(x) (((x) >> S_CL6_PAUSE_QUANTA) & M_CL6_PAUSE_QUANTA)
48088 
48089 #define A_MAC_PORT_MTIP_1G10G_CL01_QUANTA_THRESH 0xd64
48090 
48091 #define S_CL1_QUANTA_THRESH    16
48092 #define M_CL1_QUANTA_THRESH    0xffffU
48093 #define V_CL1_QUANTA_THRESH(x) ((x) << S_CL1_QUANTA_THRESH)
48094 #define G_CL1_QUANTA_THRESH(x) (((x) >> S_CL1_QUANTA_THRESH) & M_CL1_QUANTA_THRESH)
48095 
48096 #define S_CL0_QUANTA_THRESH    0
48097 #define M_CL0_QUANTA_THRESH    0xffffU
48098 #define V_CL0_QUANTA_THRESH(x) ((x) << S_CL0_QUANTA_THRESH)
48099 #define G_CL0_QUANTA_THRESH(x) (((x) >> S_CL0_QUANTA_THRESH) & M_CL0_QUANTA_THRESH)
48100 
48101 #define A_MAC_PORT_MTIP_1G10G_CL23_QUANTA_THRESH 0xd68
48102 
48103 #define S_CL3_QUANTA_THRESH    16
48104 #define M_CL3_QUANTA_THRESH    0xffffU
48105 #define V_CL3_QUANTA_THRESH(x) ((x) << S_CL3_QUANTA_THRESH)
48106 #define G_CL3_QUANTA_THRESH(x) (((x) >> S_CL3_QUANTA_THRESH) & M_CL3_QUANTA_THRESH)
48107 
48108 #define S_CL2_QUANTA_THRESH    0
48109 #define M_CL2_QUANTA_THRESH    0xffffU
48110 #define V_CL2_QUANTA_THRESH(x) ((x) << S_CL2_QUANTA_THRESH)
48111 #define G_CL2_QUANTA_THRESH(x) (((x) >> S_CL2_QUANTA_THRESH) & M_CL2_QUANTA_THRESH)
48112 
48113 #define A_MAC_PORT_MTIP_1G10G_CL45_QUANTA_THRESH 0xd6c
48114 
48115 #define S_CL5_QUANTA_THRESH    16
48116 #define M_CL5_QUANTA_THRESH    0xffffU
48117 #define V_CL5_QUANTA_THRESH(x) ((x) << S_CL5_QUANTA_THRESH)
48118 #define G_CL5_QUANTA_THRESH(x) (((x) >> S_CL5_QUANTA_THRESH) & M_CL5_QUANTA_THRESH)
48119 
48120 #define S_CL4_QUANTA_THRESH    0
48121 #define M_CL4_QUANTA_THRESH    0xffffU
48122 #define V_CL4_QUANTA_THRESH(x) ((x) << S_CL4_QUANTA_THRESH)
48123 #define G_CL4_QUANTA_THRESH(x) (((x) >> S_CL4_QUANTA_THRESH) & M_CL4_QUANTA_THRESH)
48124 
48125 #define A_MAC_PORT_MTIP_1G10G_CL67_QUANTA_THRESH 0xd70
48126 
48127 #define S_CL7_QUANTA_THRESH    16
48128 #define M_CL7_QUANTA_THRESH    0xffffU
48129 #define V_CL7_QUANTA_THRESH(x) ((x) << S_CL7_QUANTA_THRESH)
48130 #define G_CL7_QUANTA_THRESH(x) (((x) >> S_CL7_QUANTA_THRESH) & M_CL7_QUANTA_THRESH)
48131 
48132 #define S_CL6_QUANTA_THRESH    0
48133 #define M_CL6_QUANTA_THRESH    0xffffU
48134 #define V_CL6_QUANTA_THRESH(x) ((x) << S_CL6_QUANTA_THRESH)
48135 #define G_CL6_QUANTA_THRESH(x) (((x) >> S_CL6_QUANTA_THRESH) & M_CL6_QUANTA_THRESH)
48136 
48137 #define A_MAC_PORT_MTIP_1G10G_RX_PAUSE_STATUS 0xd74
48138 
48139 #define S_STATUS_BIT    0
48140 #define M_STATUS_BIT    0xffU
48141 #define V_STATUS_BIT(x) ((x) << S_STATUS_BIT)
48142 #define G_STATUS_BIT(x) (((x) >> S_STATUS_BIT) & M_STATUS_BIT)
48143 
48144 #define A_MAC_PORT_MTIP_1G10G_TS_TIMESTAMP 0xd7c
48145 #define A_MAC_PORT_MTIP_1G10G_STATN_CONFIG 0xde0
48146 
48147 #define S_CLEAR    2
48148 #define V_CLEAR(x) ((x) << S_CLEAR)
48149 #define F_CLEAR    V_CLEAR(1U)
48150 
48151 #define S_CLEAR_ON_READ    1
48152 #define V_CLEAR_ON_READ(x) ((x) << S_CLEAR_ON_READ)
48153 #define F_CLEAR_ON_READ    V_CLEAR_ON_READ(1U)
48154 
48155 #define S_SATURATE    0
48156 #define V_SATURATE(x) ((x) << S_SATURATE)
48157 #define F_SATURATE    V_SATURATE(1U)
48158 
48159 #define A_MAC_PORT_MTIP_1G10G_RX_ETHERSTATSOCTETS 0xe00
48160 #define A_MAC_PORT_MTIP_1G10G_RX_ETHERSTATSOCTETSHI 0xe04
48161 #define A_MAC_PORT_MTIP_1G10G_RX_OCTETSOK 0xe08
48162 #define A_MAC_PORT_MTIP_1G10G_RX_OCTETSOKHI 0xe0c
48163 #define A_MAC_PORT_MTIP_1G10G_RX_AALIGNMENTERRORS 0xe10
48164 #define A_MAC_PORT_MTIP_1G10G_RX_AALIGNMENTERRORSHI 0xe14
48165 #define A_MAC_PORT_MTIP_1G10G_RX_APAUSEMACCTRLFRAMES 0xe18
48166 #define A_MAC_PORT_MTIP_1G10G_RX_APAUSEMACCTRLFRAMESHI 0xe1c
48167 #define A_MAC_PORT_MTIP_1G10G_RX_FRAMESOK 0xe20
48168 #define A_MAC_PORT_MTIP_1G10G_RX_FRAMESOKHI 0xe24
48169 #define A_MAC_PORT_MTIP_1G10G_RX_CRCERRORS 0xe28
48170 #define A_MAC_PORT_MTIP_1G10G_RX_CRCERRORSHI 0xe2c
48171 #define A_MAC_PORT_MTIP_1G10G_RX_VLANOK 0xe30
48172 #define A_MAC_PORT_MTIP_1G10G_RX_VLANOKHI 0xe34
48173 #define A_MAC_PORT_MTIP_1G10G_RX_IFINERRORS 0xe38
48174 #define A_MAC_PORT_MTIP_1G10G_RX_IFINERRORSHI 0xe3c
48175 #define A_MAC_PORT_MTIP_1G10G_RX_IFINUCASTPKTS 0xe40
48176 #define A_MAC_PORT_MTIP_1G10G_RX_IFINUCASTPKTSHI 0xe44
48177 #define A_MAC_PORT_MTIP_1G10G_RX_IFINMULTICASTPKTS 0xe48
48178 #define A_MAC_PORT_MTIP_1G10G_RX_IFINMULTICASTPKTSHI 0xe4c
48179 #define A_MAC_PORT_MTIP_1G10G_RX_IFINBROADCASTPKTS 0xe50
48180 #define A_MAC_PORT_MTIP_1G10G_RX_IFINBROADCASTPKTSHI 0xe54
48181 #define A_MAC_PORT_MTIP_1G10G_RX_ETHERSTATSDROPEVENTS 0xe58
48182 #define A_MAC_PORT_MTIP_1G10G_RX_ETHERSTATSDROPEVENTSHI 0xe5c
48183 #define A_MAC_PORT_MTIP_1G10G_RX_ETHERSTATSPKTS 0xe60
48184 #define A_MAC_PORT_MTIP_1G10G_RX_ETHERSTATSPKTSHI 0xe64
48185 #define A_MAC_PORT_MTIP_1G10G_RX_ETHERSTATSUNDERSIZEPKTS 0xe68
48186 #define A_MAC_PORT_MTIP_1G10G_RX_ETHERSTATSUNDERSIZEPKTSHI 0xe6c
48187 #define A_MAC_PORT_MTIP_1G10G_RX_ETHERSTATSPKTS64OCTETS 0xe70
48188 #define A_MAC_PORT_MTIP_1G10G_RX_ETHERSTATSPKTS64OCTETSHI 0xe74
48189 #define A_MAC_PORT_MTIP_1G10G_RX_ETHERSTATSPKTS65TO127OCTETS 0xe78
48190 #define A_MAC_PORT_MTIP_1G10G_RX_ETHERSTATSPKTS65TO127OCTETSHI 0xe7c
48191 #define A_MAC_PORT_MTIP_1G10G_RX_ETHERSTATSPKTS128TO255OCTETS 0xe80
48192 #define A_MAC_PORT_MTIP_1G10G_RX_ETHERSTATSPKTS128TO255OCTETSHI 0xe84
48193 #define A_MAC_PORT_MTIP_1G10G_RX_ETHERSTATSPKTS256TO511OCTETS 0xe88
48194 #define A_MAC_PORT_MTIP_1G10G_RX_ETHERSTATSPKTS256TO511OCTETSHI 0xe8c
48195 #define A_MAC_PORT_MTIP_1G10G_RX_ETHERSTATSPKTS512TO1023OCTETS 0xe90
48196 #define A_MAC_PORT_MTIP_1G10G_RX_ETHERSTATSPKTS512TO1023OCTETSHI 0xe94
48197 #define A_MAC_PORT_MTIP_1G10G_RX_ETHERSTATSPKTS1024TO1518OCTETS 0xe98
48198 #define A_MAC_PORT_MTIP_1G10G_RX_ETHERSTATSPKTS1024TO1518OCTETSHI 0xe9c
48199 #define A_MAC_PORT_MTIP_1G10G_RX_ETHERSTATSPKTS1519TOMAX 0xea0
48200 #define A_MAC_PORT_MTIP_1G10G_RX_ETHERSTATSPKTS1519TOMAXHI 0xea4
48201 #define A_MAC_PORT_MTIP_1G10G_RX_ETHERSTATSOVERSIZEPKTS 0xea8
48202 #define A_MAC_PORT_MTIP_1G10G_RX_ETHERSTATSOVERSIZEPKTSHI 0xeac
48203 #define A_MAC_PORT_MTIP_1G10G_RX_ETHERSTATSJABBERS 0xeb0
48204 #define A_MAC_PORT_MTIP_1G10G_RX_ETHERSTATSJABBERSHI 0xeb4
48205 #define A_MAC_PORT_MTIP_1G10G_RX_ETHERSTATSFRAGMENTS 0xeb8
48206 #define A_MAC_PORT_MTIP_1G10G_RX_ETHERSTATSFRAGMENTSHI 0xebc
48207 #define A_MAC_PORT_MTIP_1G10G_AMACCONTROLFRAMESRECEIVED 0xec0
48208 #define A_MAC_PORT_MTIP_1G10G_AMACCONTROLFRAMESRECEIVEDHI 0xec4
48209 #define A_MAC_PORT_MTIP_1G10G_RX_AFRAMETOOLONG 0xec8
48210 #define A_MAC_PORT_MTIP_1G10G_RX_AFRAMETOOLONGHI 0xecc
48211 #define A_MAC_PORT_MTIP_1G10G_RX_AINRANGELENGTHERRORS 0xed0
48212 #define A_MAC_PORT_MTIP_1G10G_RX_AINRANGELENGTHERRORSHI 0xed4
48213 #define A_MAC_PORT_MTIP_1G10G_TX_ETHERSTATSOCTETS 0xf00
48214 #define A_MAC_PORT_MTIP_1G10G_TX_ETHERSTATSOCTETSHI 0xf04
48215 #define A_MAC_PORT_MTIP_1G10G_TX_OCTETSOK 0xf08
48216 #define A_MAC_PORT_MTIP_1G10G_TX_OCTETSOKHI 0xf0c
48217 #define A_MAC_PORT_MTIP_1G10G_TX_AALIGNMENTERRORS 0xf10
48218 #define A_MAC_PORT_MTIP_1G10G_TX_AALIGNMENTERRORSHI 0xf14
48219 #define A_MAC_PORT_MTIP_1G10G_TX_APAUSEMACCTRLFRAMES 0xf18
48220 #define A_MAC_PORT_MTIP_1G10G_TX_APAUSEMACCTRLFRAMESHI 0xf1c
48221 #define A_MAC_PORT_MTIP_1G10G_TX_FRAMESOK 0xf20
48222 #define A_MAC_PORT_MTIP_1G10G_TX_FRAMESOKHI 0xf24
48223 #define A_MAC_PORT_MTIP_1G10G_TX_CRCERRORS 0xf28
48224 #define A_MAC_PORT_MTIP_1G10G_TX_CRCERRORSHI 0xf2c
48225 #define A_MAC_PORT_MTIP_1G10G_TX_VLANOK 0xf30
48226 #define A_MAC_PORT_MTIP_1G10G_TX_VLANOKHI 0xf34
48227 #define A_MAC_PORT_MTIP_1G10G_TX_IFOUTERRORS 0xf38
48228 #define A_MAC_PORT_MTIP_1G10G_TX_IFOUTERRORSHI 0xf3c
48229 #define A_MAC_PORT_MTIP_1G10G_TX_IFUCASTPKTS 0xf40
48230 #define A_MAC_PORT_MTIP_1G10G_TX_IFUCASTPKTSHI 0xf44
48231 #define A_MAC_PORT_MTIP_1G10G_TX_IFMULTICASTPKTS 0xf48
48232 #define A_MAC_PORT_MTIP_1G10G_TX_IFMULTICASTPKTSHI 0xf4c
48233 #define A_MAC_PORT_MTIP_1G10G_TX_IFBROADCASTPKTS 0xf50
48234 #define A_MAC_PORT_MTIP_1G10G_TX_IFBROADCASTPKTSHI 0xf54
48235 #define A_MAC_PORT_MTIP_1G10G_TX_ETHERSTATSDROPEVENTS 0xf58
48236 #define A_MAC_PORT_MTIP_1G10G_TX_ETHERSTATSDROPEVENTSHI 0xf5c
48237 #define A_MAC_PORT_MTIP_1G10G_TX_ETHERSTATSPKTS 0xf60
48238 #define A_MAC_PORT_MTIP_1G10G_TX_ETHERSTATSPKTSHI 0xf64
48239 #define A_MAC_PORT_MTIP_1G10G_TX_ETHERSTATSUNDERSIZEPKTS 0xf68
48240 #define A_MAC_PORT_MTIP_1G10G_TX_ETHERSTATSUNDERSIZEPKTSHI 0xf6c
48241 #define A_MAC_PORT_MTIP_1G10G_TX_ETHERSTATSPKTS64OCTETS 0xf70
48242 #define A_MAC_PORT_MTIP_1G10G_TX_ETHERSTATSPKTS64OCTETSHI 0xf74
48243 #define A_MAC_PORT_MTIP_1G10G_TX_ETHERSTATSPKTS65TO127OCTETS 0xf78
48244 #define A_MAC_PORT_MTIP_1G10G_TX_ETHERSTATSPKTS65TO127OCTETSHI 0xf7c
48245 #define A_MAC_PORT_MTIP_1G10G_TX_ETHERSTATSPKTS128TO255OCTETS 0xf80
48246 #define A_MAC_PORT_MTIP_1G10G_TX_ETHERSTATSPKTS128TO255OCTETSHI 0xf84
48247 #define A_MAC_PORT_MTIP_1G10G_TX_ETHERSTATSPKTS256TO511OCTETS 0xf88
48248 #define A_MAC_PORT_MTIP_1G10G_TX_ETHERSTATSPKTS256TO511OCTETSHI 0xf8c
48249 #define A_MAC_PORT_MTIP_1G10G_TX_ETHERSTATSPKTS512TO1023OCTETS 0xf90
48250 #define A_MAC_PORT_MTIP_1G10G_TX_ETHERSTATSPKTS512TO1023OCTETSHI 0xf94
48251 #define A_MAC_PORT_MTIP_1G10G_TX_ETHERSTATSPKTS1024TO1518OCTETS 0xf98
48252 #define A_MAC_PORT_MTIP_1G10G_TX_ETHERSTATSPKTS1024TO1518OCTETSHI 0xf9c
48253 #define A_MAC_PORT_MTIP_1G10G_ETHERSTATSPKTS1519TOTX_MTU 0xfa0
48254 #define A_MAC_PORT_MTIP_1G10G_ETHERSTATSPKTS1519TOTX_MTUHI 0xfa4
48255 #define A_MAC_PORT_MTIP_1G10G_TX_AMACCONTROLFRAMES 0xfc0
48256 #define A_MAC_PORT_MTIP_1G10G_TX_AMACCONTROLFRAMESHI 0xfc4
48257 #define A_MAC_PORT_MTIP_1G10G_IF_MODE 0x1000
48258 
48259 #define S_MII_ENA_10    4
48260 #define V_MII_ENA_10(x) ((x) << S_MII_ENA_10)
48261 #define F_MII_ENA_10    V_MII_ENA_10(1U)
48262 
48263 #define S_IF_MODE    0
48264 #define M_IF_MODE    0x3U
48265 #define V_IF_MODE(x) ((x) << S_IF_MODE)
48266 #define G_IF_MODE(x) (((x) >> S_IF_MODE) & M_IF_MODE)
48267 
48268 #define A_MAC_PORT_MTIP_1G10G_IF_STATUS 0x1004
48269 
48270 #define S_IF_STATUS_MODE    0
48271 #define M_IF_STATUS_MODE    0x3U
48272 #define V_IF_STATUS_MODE(x) ((x) << S_IF_STATUS_MODE)
48273 #define G_IF_STATUS_MODE(x) (((x) >> S_IF_STATUS_MODE) & M_IF_STATUS_MODE)
48274 
48275 #define A_MAC_PORT_MTIP_1G10G_PFCFRAMESRECEIVED_0 0x1080
48276 #define A_MAC_PORT_MTIP_1G10G_PFCFRAMESRECEIVED_0HI 0x1084
48277 #define A_MAC_PORT_MTIP_1G10G_PFCFRAMESRECEIVED_1 0x1088
48278 #define A_MAC_PORT_MTIP_1G10G_PFCFRAMESRECEIVED_1HI 0x108c
48279 #define A_MAC_PORT_MTIP_1G10G_PFCFRAMESRECEIVED_2 0x1090
48280 #define A_MAC_PORT_MTIP_1G10G_PFCFRAMESRECEIVED_2HI 0x1094
48281 #define A_MAC_PORT_MTIP_1G10G_PFCFRAMESRECEIVED_3 0x1098
48282 #define A_MAC_PORT_MTIP_1G10G_PFCFRAMESRECEIVED_3HI 0x109c
48283 #define A_MAC_PORT_MTIP_1G10G_PFCFRAMESRECEIVED_4 0x10a0
48284 #define A_MAC_PORT_MTIP_1G10G_PFCFRAMESRECEIVED_4HI 0x10a4
48285 #define A_MAC_PORT_MTIP_1G10G_PFCFRAMESRECEIVED_5 0x10a8
48286 #define A_MAC_PORT_MTIP_1G10G_PFCFRAMESRECEIVED_5HI 0x10ac
48287 #define A_MAC_PORT_MTIP_1G10G_PFCFRAMESRECEIVED_6 0x10b0
48288 #define A_MAC_PORT_MTIP_1G10G_PFCFRAMESRECEIVED_6HI 0x10b4
48289 #define A_MAC_PORT_MTIP_1G10G_PFCFRAMESRECEIVED_7 0x10b8
48290 #define A_MAC_PORT_MTIP_1G10G_PFCFRAMESRECEIVED_7HI 0x10bc
48291 #define A_MAC_PORT_MTIP_1G10G_PFCFRAMESTRANSMITTED_0 0x10c0
48292 #define A_MAC_PORT_MTIP_1G10G_PFCFRAMESTRANSMITTED_0HI 0x10c4
48293 #define A_MAC_PORT_MTIP_1G10G_PFCFRAMESTRANSMITTED_1 0x10c8
48294 #define A_MAC_PORT_MTIP_1G10G_PFCFRAMESTRANSMITTED_1HI 0x10cc
48295 #define A_MAC_PORT_MTIP_1G10G_PFCFRAMESTRANSMITTED_2 0x10d0
48296 #define A_MAC_PORT_MTIP_1G10G_PFCFRAMESTRANSMITTED_2HI 0x10d4
48297 #define A_MAC_PORT_MTIP_1G10G_PFCFRAMESTRANSMITTED_3 0x10d8
48298 #define A_MAC_PORT_MTIP_1G10G_PFCFRAMESTRANSMITTED_3HI 0x10dc
48299 #define A_MAC_PORT_MTIP_1G10G_PFCFRAMESTRANSMITTED_4 0x10e0
48300 #define A_MAC_PORT_MTIP_1G10G_PFCFRAMESTRANSMITTED_4HI 0x10e4
48301 #define A_MAC_PORT_MTIP_1G10G_PFCFRAMESTRANSMITTED_5 0x10e8
48302 #define A_MAC_PORT_MTIP_1G10G_PFCFRAMESTRANSMITTED_5HI 0x10ec
48303 #define A_MAC_PORT_MTIP_1G10G_PFCFRAMESTRANSMITTED_6 0x10f0
48304 #define A_MAC_PORT_MTIP_1G10G_PFCFRAMESTRANSMITTED_6HI 0x10f4
48305 #define A_MAC_PORT_MTIP_1G10G_PFCFRAMESTRANSMITTED_7 0x10f8
48306 #define A_MAC_PORT_MTIP_1G10G_PFCFRAMESTRANSMITTED_7HI 0x10fc
48307 #define A_MAC_PORT_MTIP_ACT_CTL_SEG 0x1200
48308 
48309 #define S_ACTIVE    0
48310 #define M_ACTIVE    0x3fU
48311 #define V_ACTIVE(x) ((x) << S_ACTIVE)
48312 #define G_ACTIVE(x) (((x) >> S_ACTIVE) & M_ACTIVE)
48313 
48314 #define A_T6_MAC_PORT_MTIP_SGMII_CONTROL 0x1200
48315 
48316 #define S_SPEED_SEL    13
48317 #define V_SPEED_SEL(x) ((x) << S_SPEED_SEL)
48318 #define F_SPEED_SEL    V_SPEED_SEL(1U)
48319 
48320 #define S_PWR_DWN    11
48321 #define V_PWR_DWN(x) ((x) << S_PWR_DWN)
48322 #define F_PWR_DWN    V_PWR_DWN(1U)
48323 
48324 #define S_DUPLEX_MODE    8
48325 #define V_DUPLEX_MODE(x) ((x) << S_DUPLEX_MODE)
48326 #define F_DUPLEX_MODE    V_DUPLEX_MODE(1U)
48327 
48328 #define S_COLLISION_TEST    7
48329 #define V_COLLISION_TEST(x) ((x) << S_COLLISION_TEST)
48330 #define F_COLLISION_TEST    V_COLLISION_TEST(1U)
48331 
48332 #define S_T6_SPEED_SEL1    6
48333 #define V_T6_SPEED_SEL1(x) ((x) << S_T6_SPEED_SEL1)
48334 #define F_T6_SPEED_SEL1    V_T6_SPEED_SEL1(1U)
48335 
48336 #define A_MAC_PORT_MTIP_MODE_CTL_SEG 0x1204
48337 
48338 #define S_MODE_CTL    0
48339 #define M_MODE_CTL    0x3U
48340 #define V_MODE_CTL(x) ((x) << S_MODE_CTL)
48341 #define G_MODE_CTL(x) (((x) >> S_MODE_CTL) & M_MODE_CTL)
48342 
48343 #define A_T6_MAC_PORT_MTIP_SGMII_STATUS 0x1204
48344 
48345 #define S_T6_REM_FAULT    4
48346 #define V_T6_REM_FAULT(x) ((x) << S_T6_REM_FAULT)
48347 #define F_T6_REM_FAULT    V_T6_REM_FAULT(1U)
48348 
48349 #define A_MAC_PORT_MTIP_TXCLK_CTL_SEG 0x1208
48350 
48351 #define S_TXCLK_CTL    0
48352 #define M_TXCLK_CTL    0xffffU
48353 #define V_TXCLK_CTL(x) ((x) << S_TXCLK_CTL)
48354 #define G_TXCLK_CTL(x) (((x) >> S_TXCLK_CTL) & M_TXCLK_CTL)
48355 
48356 #define A_T6_MAC_PORT_MTIP_SGMII_PHY_IDENTIFIER_0 0x1208
48357 #define A_MAC_PORT_MTIP_TX_PRMBL_CTL_SEG 0x120c
48358 #define A_T6_MAC_PORT_MTIP_SGMII_PHY_IDENTIFIER_1 0x120c
48359 #define A_T6_MAC_PORT_MTIP_SGMII_DEV_ABILITY 0x1210
48360 #define A_T6_MAC_PORT_MTIP_SGMII_PARTNER_ABILITY 0x1214
48361 #define A_T6_MAC_PORT_MTIP_SGMII_AN_EXPANSION 0x1218
48362 
48363 #define S_NEXT_PAGE_ABLE    2
48364 #define V_NEXT_PAGE_ABLE(x) ((x) << S_NEXT_PAGE_ABLE)
48365 #define F_NEXT_PAGE_ABLE    V_NEXT_PAGE_ABLE(1U)
48366 
48367 #define S_PAGE_RECEIVE    1
48368 #define V_PAGE_RECEIVE(x) ((x) << S_PAGE_RECEIVE)
48369 #define F_PAGE_RECEIVE    V_PAGE_RECEIVE(1U)
48370 
48371 #define A_MAC_PORT_MTIP_SGMII_NP_TX 0x121c
48372 
48373 #define S_NP_TX    0
48374 #define M_NP_TX    0xffffU
48375 #define V_NP_TX(x) ((x) << S_NP_TX)
48376 #define G_NP_TX(x) (((x) >> S_NP_TX) & M_NP_TX)
48377 
48378 #define A_MAC_PORT_MTIP_WAN_RS_COL_CNT 0x1220
48379 
48380 #define S_COL_CNT    0
48381 #define M_COL_CNT    0xffffU
48382 #define V_COL_CNT(x) ((x) << S_COL_CNT)
48383 #define G_COL_CNT(x) (((x) >> S_COL_CNT) & M_COL_CNT)
48384 
48385 #define A_MAC_PORT_MTIP_SGMII_LP_NP_RX 0x1220
48386 
48387 #define S_LP_NP_RX    0
48388 #define M_LP_NP_RX    0xffffU
48389 #define V_LP_NP_RX(x) ((x) << S_LP_NP_RX)
48390 #define G_LP_NP_RX(x) (((x) >> S_LP_NP_RX) & M_LP_NP_RX)
48391 
48392 #define A_T6_MAC_PORT_MTIP_SGMII_EXTENDED_STATUS 0x123c
48393 
48394 #define S_EXTENDED_STATUS    0
48395 #define M_EXTENDED_STATUS    0xffffU
48396 #define V_EXTENDED_STATUS(x) ((x) << S_EXTENDED_STATUS)
48397 #define G_EXTENDED_STATUS(x) (((x) >> S_EXTENDED_STATUS) & M_EXTENDED_STATUS)
48398 
48399 #define A_MAC_PORT_MTIP_VL_INTVL 0x1240
48400 
48401 #define S_VL_INTVL    1
48402 #define V_VL_INTVL(x) ((x) << S_VL_INTVL)
48403 #define F_VL_INTVL    V_VL_INTVL(1U)
48404 
48405 #define A_MAC_PORT_MTIP_SGMII_SCRATCH 0x1240
48406 
48407 #define S_SCRATCH    0
48408 #define M_SCRATCH    0xffffU
48409 #define V_SCRATCH(x) ((x) << S_SCRATCH)
48410 #define G_SCRATCH(x) (((x) >> S_SCRATCH) & M_SCRATCH)
48411 
48412 #define A_MAC_PORT_MTIP_SGMII_REV 0x1244
48413 
48414 #define S_SGMII_VER    8
48415 #define M_SGMII_VER    0xffU
48416 #define V_SGMII_VER(x) ((x) << S_SGMII_VER)
48417 #define G_SGMII_VER(x) (((x) >> S_SGMII_VER) & M_SGMII_VER)
48418 
48419 #define S_SGMII_REV    0
48420 #define M_SGMII_REV    0xffU
48421 #define V_SGMII_REV(x) ((x) << S_SGMII_REV)
48422 #define G_SGMII_REV(x) (((x) >> S_SGMII_REV) & M_SGMII_REV)
48423 
48424 #define A_T6_MAC_PORT_MTIP_SGMII_LINK_TIMER_LO 0x1248
48425 
48426 #define S_LINK_TIMER_LO    0
48427 #define M_LINK_TIMER_LO    0xffffU
48428 #define V_LINK_TIMER_LO(x) ((x) << S_LINK_TIMER_LO)
48429 #define G_LINK_TIMER_LO(x) (((x) >> S_LINK_TIMER_LO) & M_LINK_TIMER_LO)
48430 
48431 #define A_T6_MAC_PORT_MTIP_SGMII_LINK_TIMER_HI 0x124c
48432 
48433 #define S_LINK_TIMER_HI    0
48434 #define M_LINK_TIMER_HI    0xffffU
48435 #define V_LINK_TIMER_HI(x) ((x) << S_LINK_TIMER_HI)
48436 #define G_LINK_TIMER_HI(x) (((x) >> S_LINK_TIMER_HI) & M_LINK_TIMER_HI)
48437 
48438 #define A_T6_MAC_PORT_MTIP_SGMII_IF_MODE 0x1250
48439 
48440 #define S_SGMII_DUPLEX    4
48441 #define V_SGMII_DUPLEX(x) ((x) << S_SGMII_DUPLEX)
48442 #define F_SGMII_DUPLEX    V_SGMII_DUPLEX(1U)
48443 
48444 #define A_MAC_PORT_MTIP_SGMII_DECODE_ERROR 0x1254
48445 
48446 #define S_T6_DECODE_ERROR    0
48447 #define M_T6_DECODE_ERROR    0xffffU
48448 #define V_T6_DECODE_ERROR(x) ((x) << S_T6_DECODE_ERROR)
48449 #define G_T6_DECODE_ERROR(x) (((x) >> S_T6_DECODE_ERROR) & M_T6_DECODE_ERROR)
48450 
48451 #define A_MAC_PORT_MTIP_KR_PCS_CONTROL_1 0x1300
48452 
48453 #define S_LOW_POWER    11
48454 #define V_LOW_POWER(x) ((x) << S_LOW_POWER)
48455 #define F_LOW_POWER    V_LOW_POWER(1U)
48456 
48457 #define S_T6_SPEED_SEL1    6
48458 #define V_T6_SPEED_SEL1(x) ((x) << S_T6_SPEED_SEL1)
48459 #define F_T6_SPEED_SEL1    V_T6_SPEED_SEL1(1U)
48460 
48461 #define S_SPEED_SEL2    2
48462 #define M_SPEED_SEL2    0xfU
48463 #define V_SPEED_SEL2(x) ((x) << S_SPEED_SEL2)
48464 #define G_SPEED_SEL2(x) (((x) >> S_SPEED_SEL2) & M_SPEED_SEL2)
48465 
48466 #define A_MAC_PORT_MTIP_KR_PCS_STATUS_1 0x1304
48467 
48468 #define S_TX_LPI    11
48469 #define V_TX_LPI(x) ((x) << S_TX_LPI)
48470 #define F_TX_LPI    V_TX_LPI(1U)
48471 
48472 #define S_RX_LPI    10
48473 #define V_RX_LPI(x) ((x) << S_RX_LPI)
48474 #define F_RX_LPI    V_RX_LPI(1U)
48475 
48476 #define S_TX_LPI_ACTIVE    9
48477 #define V_TX_LPI_ACTIVE(x) ((x) << S_TX_LPI_ACTIVE)
48478 #define F_TX_LPI_ACTIVE    V_TX_LPI_ACTIVE(1U)
48479 
48480 #define S_RX_LPI_ACTIVE    8
48481 #define V_RX_LPI_ACTIVE(x) ((x) << S_RX_LPI_ACTIVE)
48482 #define F_RX_LPI_ACTIVE    V_RX_LPI_ACTIVE(1U)
48483 
48484 #define S_FAULT    7
48485 #define V_FAULT(x) ((x) << S_FAULT)
48486 #define F_FAULT    V_FAULT(1U)
48487 
48488 #define S_PCS_RX_LINK_STAT    2
48489 #define V_PCS_RX_LINK_STAT(x) ((x) << S_PCS_RX_LINK_STAT)
48490 #define F_PCS_RX_LINK_STAT    V_PCS_RX_LINK_STAT(1U)
48491 
48492 #define S_LOW_POWER_ABILITY    1
48493 #define V_LOW_POWER_ABILITY(x) ((x) << S_LOW_POWER_ABILITY)
48494 #define F_LOW_POWER_ABILITY    V_LOW_POWER_ABILITY(1U)
48495 
48496 #define A_MAC_PORT_MTIP_KR_PCS_DEVICE_IDENTIFIER_1 0x1308
48497 #define A_MAC_PORT_MTIP_KR_PCS_DEVICE_IDENTIFIER_2 0x130c
48498 #define A_MAC_PORT_MTIP_KR_PCS_SPEED_ABILITY 0x1310
48499 
48500 #define S_10G_CAPABLE    0
48501 #define V_10G_CAPABLE(x) ((x) << S_10G_CAPABLE)
48502 #define F_10G_CAPABLE    V_10G_CAPABLE(1U)
48503 
48504 #define A_MAC_PORT_MTIP_KR_PCS_DEVICES_IN_PACKAGELO 0x1314
48505 
48506 #define S_AUTO_NEGOTIATION_PRESENT    7
48507 #define V_AUTO_NEGOTIATION_PRESENT(x) ((x) << S_AUTO_NEGOTIATION_PRESENT)
48508 #define F_AUTO_NEGOTIATION_PRESENT    V_AUTO_NEGOTIATION_PRESENT(1U)
48509 
48510 #define S_DTE_XS_PRESENT    5
48511 #define V_DTE_XS_PRESENT(x) ((x) << S_DTE_XS_PRESENT)
48512 #define F_DTE_XS_PRESENT    V_DTE_XS_PRESENT(1U)
48513 
48514 #define S_PHY_XS_PRESENT    4
48515 #define V_PHY_XS_PRESENT(x) ((x) << S_PHY_XS_PRESENT)
48516 #define F_PHY_XS_PRESENT    V_PHY_XS_PRESENT(1U)
48517 
48518 #define S_PCS_PRESENT    3
48519 #define V_PCS_PRESENT(x) ((x) << S_PCS_PRESENT)
48520 #define F_PCS_PRESENT    V_PCS_PRESENT(1U)
48521 
48522 #define S_WIS_PRESENT    2
48523 #define V_WIS_PRESENT(x) ((x) << S_WIS_PRESENT)
48524 #define F_WIS_PRESENT    V_WIS_PRESENT(1U)
48525 
48526 #define S_PMD_PMA_PRESENT    1
48527 #define V_PMD_PMA_PRESENT(x) ((x) << S_PMD_PMA_PRESENT)
48528 #define F_PMD_PMA_PRESENT    V_PMD_PMA_PRESENT(1U)
48529 
48530 #define S_CLAUSE_22_REG_PRESENT    0
48531 #define V_CLAUSE_22_REG_PRESENT(x) ((x) << S_CLAUSE_22_REG_PRESENT)
48532 #define F_CLAUSE_22_REG_PRESENT    V_CLAUSE_22_REG_PRESENT(1U)
48533 
48534 #define A_MAC_PORT_MTIP_KR_PCS_DEVICES_IN_PACKAGEHI 0x1318
48535 #define A_MAC_PORT_MTIP_KR_PCS_CONTROL_2 0x131c
48536 
48537 #define S_PCS_TYPE_SELECTION    0
48538 #define M_PCS_TYPE_SELECTION    0x3U
48539 #define V_PCS_TYPE_SELECTION(x) ((x) << S_PCS_TYPE_SELECTION)
48540 #define G_PCS_TYPE_SELECTION(x) (((x) >> S_PCS_TYPE_SELECTION) & M_PCS_TYPE_SELECTION)
48541 
48542 #define A_MAC_PORT_MTIP_KR_PCS_STATUS_2 0x1320
48543 
48544 #define S_DEVICE_PRESENT    14
48545 #define M_DEVICE_PRESENT    0x3U
48546 #define V_DEVICE_PRESENT(x) ((x) << S_DEVICE_PRESENT)
48547 #define G_DEVICE_PRESENT(x) (((x) >> S_DEVICE_PRESENT) & M_DEVICE_PRESENT)
48548 
48549 #define S_TRANSMIT_FAULT    11
48550 #define V_TRANSMIT_FAULT(x) ((x) << S_TRANSMIT_FAULT)
48551 #define F_TRANSMIT_FAULT    V_TRANSMIT_FAULT(1U)
48552 
48553 #define S_RECEIVE_FAULT    10
48554 #define V_RECEIVE_FAULT(x) ((x) << S_RECEIVE_FAULT)
48555 #define F_RECEIVE_FAULT    V_RECEIVE_FAULT(1U)
48556 
48557 #define S_10GBASE_W_CAPABLE    2
48558 #define V_10GBASE_W_CAPABLE(x) ((x) << S_10GBASE_W_CAPABLE)
48559 #define F_10GBASE_W_CAPABLE    V_10GBASE_W_CAPABLE(1U)
48560 
48561 #define S_10GBASE_X_CAPABLE    1
48562 #define V_10GBASE_X_CAPABLE(x) ((x) << S_10GBASE_X_CAPABLE)
48563 #define F_10GBASE_X_CAPABLE    V_10GBASE_X_CAPABLE(1U)
48564 
48565 #define S_10GBASE_R_CAPABLE    0
48566 #define V_10GBASE_R_CAPABLE(x) ((x) << S_10GBASE_R_CAPABLE)
48567 #define F_10GBASE_R_CAPABLE    V_10GBASE_R_CAPABLE(1U)
48568 
48569 #define A_MAC_PORT_MTIP_KR_10GBASE_R_PCS_PACKAGE_IDENTIFIER_LO 0x1338
48570 
48571 #define S_PCS_PACKAGE_IDENTIFIER_LO    0
48572 #define M_PCS_PACKAGE_IDENTIFIER_LO    0xffffU
48573 #define V_PCS_PACKAGE_IDENTIFIER_LO(x) ((x) << S_PCS_PACKAGE_IDENTIFIER_LO)
48574 #define G_PCS_PACKAGE_IDENTIFIER_LO(x) (((x) >> S_PCS_PACKAGE_IDENTIFIER_LO) & M_PCS_PACKAGE_IDENTIFIER_LO)
48575 
48576 #define A_MAC_PORT_MTIP_KR_10GBASE_R_PCS_PACKAGE_IDENTIFIER_HI 0x133c
48577 
48578 #define S_PCS_PACKAGE_IDENTIFIER_HI    0
48579 #define M_PCS_PACKAGE_IDENTIFIER_HI    0xffffU
48580 #define V_PCS_PACKAGE_IDENTIFIER_HI(x) ((x) << S_PCS_PACKAGE_IDENTIFIER_HI)
48581 #define G_PCS_PACKAGE_IDENTIFIER_HI(x) (((x) >> S_PCS_PACKAGE_IDENTIFIER_HI) & M_PCS_PACKAGE_IDENTIFIER_HI)
48582 
48583 #define A_MAC_PORT_MTIP_KR_10GBASE_R_PCS_STATUS_1 0x1380
48584 
48585 #define S_10GBASE_R_RX_LINK_STATUS    12
48586 #define V_10GBASE_R_RX_LINK_STATUS(x) ((x) << S_10GBASE_R_RX_LINK_STATUS)
48587 #define F_10GBASE_R_RX_LINK_STATUS    V_10GBASE_R_RX_LINK_STATUS(1U)
48588 
48589 #define S_PRBS9_PTTRN_TSTNG_ABILITY    3
48590 #define V_PRBS9_PTTRN_TSTNG_ABILITY(x) ((x) << S_PRBS9_PTTRN_TSTNG_ABILITY)
48591 #define F_PRBS9_PTTRN_TSTNG_ABILITY    V_PRBS9_PTTRN_TSTNG_ABILITY(1U)
48592 
48593 #define S_PRBS31_PTTRN_TSTNG_ABILITY    2
48594 #define V_PRBS31_PTTRN_TSTNG_ABILITY(x) ((x) << S_PRBS31_PTTRN_TSTNG_ABILITY)
48595 #define F_PRBS31_PTTRN_TSTNG_ABILITY    V_PRBS31_PTTRN_TSTNG_ABILITY(1U)
48596 
48597 #define S_10GBASE_R_PCS_HIGH_BER    1
48598 #define V_10GBASE_R_PCS_HIGH_BER(x) ((x) << S_10GBASE_R_PCS_HIGH_BER)
48599 #define F_10GBASE_R_PCS_HIGH_BER    V_10GBASE_R_PCS_HIGH_BER(1U)
48600 
48601 #define S_10GBASE_R_PCS_BLOCK_LOCK    0
48602 #define V_10GBASE_R_PCS_BLOCK_LOCK(x) ((x) << S_10GBASE_R_PCS_BLOCK_LOCK)
48603 #define F_10GBASE_R_PCS_BLOCK_LOCK    V_10GBASE_R_PCS_BLOCK_LOCK(1U)
48604 
48605 #define A_MAC_PORT_MTIP_KR_10GBASE_R_PCS_STATUS_2 0x1384
48606 
48607 #define S_LATCHED_BLOCK_LOCK    15
48608 #define V_LATCHED_BLOCK_LOCK(x) ((x) << S_LATCHED_BLOCK_LOCK)
48609 #define F_LATCHED_BLOCK_LOCK    V_LATCHED_BLOCK_LOCK(1U)
48610 
48611 #define S_LATCHED_HIGH_BER    14
48612 #define V_LATCHED_HIGH_BER(x) ((x) << S_LATCHED_HIGH_BER)
48613 #define F_LATCHED_HIGH_BER    V_LATCHED_HIGH_BER(1U)
48614 
48615 #define S_BERBER_COUNTER    8
48616 #define M_BERBER_COUNTER    0x3fU
48617 #define V_BERBER_COUNTER(x) ((x) << S_BERBER_COUNTER)
48618 #define G_BERBER_COUNTER(x) (((x) >> S_BERBER_COUNTER) & M_BERBER_COUNTER)
48619 
48620 #define A_MAC_PORT_MTIP_KR_10GBASE_R_PCS_TEST_PATTERN_SEED_A_0 0x1388
48621 
48622 #define S_TEST_PATTERN_SEED_A0    0
48623 #define M_TEST_PATTERN_SEED_A0    0xffffU
48624 #define V_TEST_PATTERN_SEED_A0(x) ((x) << S_TEST_PATTERN_SEED_A0)
48625 #define G_TEST_PATTERN_SEED_A0(x) (((x) >> S_TEST_PATTERN_SEED_A0) & M_TEST_PATTERN_SEED_A0)
48626 
48627 #define A_MAC_PORT_MTIP_KR_10GBASE_R_PCS_TEST_PATTERN_SEED_A_1 0x138c
48628 
48629 #define S_TEST_PATTERN_SEED_A1    0
48630 #define M_TEST_PATTERN_SEED_A1    0xffffU
48631 #define V_TEST_PATTERN_SEED_A1(x) ((x) << S_TEST_PATTERN_SEED_A1)
48632 #define G_TEST_PATTERN_SEED_A1(x) (((x) >> S_TEST_PATTERN_SEED_A1) & M_TEST_PATTERN_SEED_A1)
48633 
48634 #define A_MAC_PORT_MTIP_KR_10GBASE_R_PCS_TEST_PATTERN_SEED_A_2 0x1390
48635 
48636 #define S_TEST_PATTERN_SEED_A2    0
48637 #define M_TEST_PATTERN_SEED_A2    0xffffU
48638 #define V_TEST_PATTERN_SEED_A2(x) ((x) << S_TEST_PATTERN_SEED_A2)
48639 #define G_TEST_PATTERN_SEED_A2(x) (((x) >> S_TEST_PATTERN_SEED_A2) & M_TEST_PATTERN_SEED_A2)
48640 
48641 #define A_MAC_PORT_MTIP_KR_10GBASE_R_PCS_TEST_PATTERN_SEED_A_3 0x1394
48642 
48643 #define S_TEST_PATTERN_SEED_A3    0
48644 #define M_TEST_PATTERN_SEED_A3    0x3ffU
48645 #define V_TEST_PATTERN_SEED_A3(x) ((x) << S_TEST_PATTERN_SEED_A3)
48646 #define G_TEST_PATTERN_SEED_A3(x) (((x) >> S_TEST_PATTERN_SEED_A3) & M_TEST_PATTERN_SEED_A3)
48647 
48648 #define A_MAC_PORT_MTIP_KR_10GBASE_R_PCS_TEST_PATTERN_SEED_B_0 0x1398
48649 
48650 #define S_TEST_PATTERN_SEED_B0    0
48651 #define M_TEST_PATTERN_SEED_B0    0xffffU
48652 #define V_TEST_PATTERN_SEED_B0(x) ((x) << S_TEST_PATTERN_SEED_B0)
48653 #define G_TEST_PATTERN_SEED_B0(x) (((x) >> S_TEST_PATTERN_SEED_B0) & M_TEST_PATTERN_SEED_B0)
48654 
48655 #define A_MAC_PORT_MTIP_KR_10GBASE_R_PCS_TEST_PATTERN_SEED_B_1 0x139c
48656 
48657 #define S_TEST_PATTERN_SEED_B1    0
48658 #define M_TEST_PATTERN_SEED_B1    0xffffU
48659 #define V_TEST_PATTERN_SEED_B1(x) ((x) << S_TEST_PATTERN_SEED_B1)
48660 #define G_TEST_PATTERN_SEED_B1(x) (((x) >> S_TEST_PATTERN_SEED_B1) & M_TEST_PATTERN_SEED_B1)
48661 
48662 #define A_MAC_PORT_MTIP_KR_10GBASE_R_PCS_TEST_PATTERN_SEED_B_2 0x13a0
48663 
48664 #define S_TEST_PATTERN_SEED_B2    0
48665 #define M_TEST_PATTERN_SEED_B2    0xffffU
48666 #define V_TEST_PATTERN_SEED_B2(x) ((x) << S_TEST_PATTERN_SEED_B2)
48667 #define G_TEST_PATTERN_SEED_B2(x) (((x) >> S_TEST_PATTERN_SEED_B2) & M_TEST_PATTERN_SEED_B2)
48668 
48669 #define A_MAC_PORT_MTIP_KR_10GBASE_R_PCS_TEST_PATTERN_SEED_B_3 0x13a4
48670 
48671 #define S_TEST_PATTERN_SEED_B3    0
48672 #define M_TEST_PATTERN_SEED_B3    0x3ffU
48673 #define V_TEST_PATTERN_SEED_B3(x) ((x) << S_TEST_PATTERN_SEED_B3)
48674 #define G_TEST_PATTERN_SEED_B3(x) (((x) >> S_TEST_PATTERN_SEED_B3) & M_TEST_PATTERN_SEED_B3)
48675 
48676 #define A_MAC_PORT_MTIP_KR_10GBASE_R_PCS_TEST_PATTERN_CONTROL 0x13a8
48677 
48678 #define S_PRBS9_TX_TST_PTTRN_EN    6
48679 #define V_PRBS9_TX_TST_PTTRN_EN(x) ((x) << S_PRBS9_TX_TST_PTTRN_EN)
48680 #define F_PRBS9_TX_TST_PTTRN_EN    V_PRBS9_TX_TST_PTTRN_EN(1U)
48681 
48682 #define S_PRBS31_RX_TST_PTTRN_EN    5
48683 #define V_PRBS31_RX_TST_PTTRN_EN(x) ((x) << S_PRBS31_RX_TST_PTTRN_EN)
48684 #define F_PRBS31_RX_TST_PTTRN_EN    V_PRBS31_RX_TST_PTTRN_EN(1U)
48685 
48686 #define S_PRBS31_TX_TST_PTTRN_EN    4
48687 #define V_PRBS31_TX_TST_PTTRN_EN(x) ((x) << S_PRBS31_TX_TST_PTTRN_EN)
48688 #define F_PRBS31_TX_TST_PTTRN_EN    V_PRBS31_TX_TST_PTTRN_EN(1U)
48689 
48690 #define S_TX_TEST_PATTERN_EN    3
48691 #define V_TX_TEST_PATTERN_EN(x) ((x) << S_TX_TEST_PATTERN_EN)
48692 #define F_TX_TEST_PATTERN_EN    V_TX_TEST_PATTERN_EN(1U)
48693 
48694 #define S_RX_TEST_PATTERN_EN    2
48695 #define V_RX_TEST_PATTERN_EN(x) ((x) << S_RX_TEST_PATTERN_EN)
48696 #define F_RX_TEST_PATTERN_EN    V_RX_TEST_PATTERN_EN(1U)
48697 
48698 #define S_TEST_PATTERN_SELECT    1
48699 #define V_TEST_PATTERN_SELECT(x) ((x) << S_TEST_PATTERN_SELECT)
48700 #define F_TEST_PATTERN_SELECT    V_TEST_PATTERN_SELECT(1U)
48701 
48702 #define S_DATA_PATTERN_SELECT    0
48703 #define V_DATA_PATTERN_SELECT(x) ((x) << S_DATA_PATTERN_SELECT)
48704 #define F_DATA_PATTERN_SELECT    V_DATA_PATTERN_SELECT(1U)
48705 
48706 #define A_MAC_PORT_MTIP_KR_10GBASE_R_PCS_TEST_PATTERN_ERROR_COUNTER 0x13ac
48707 
48708 #define S_TEST_PATTERN_ERR_CNTR    0
48709 #define M_TEST_PATTERN_ERR_CNTR    0xffffU
48710 #define V_TEST_PATTERN_ERR_CNTR(x) ((x) << S_TEST_PATTERN_ERR_CNTR)
48711 #define G_TEST_PATTERN_ERR_CNTR(x) (((x) >> S_TEST_PATTERN_ERR_CNTR) & M_TEST_PATTERN_ERR_CNTR)
48712 
48713 #define A_MAC_PORT_MTIP_KR_VENDOR_SPECIFIC_PCS_STATUS 0x13b4
48714 
48715 #define S_TRANSMIT_FIFO_FAULT    1
48716 #define V_TRANSMIT_FIFO_FAULT(x) ((x) << S_TRANSMIT_FIFO_FAULT)
48717 #define F_TRANSMIT_FIFO_FAULT    V_TRANSMIT_FIFO_FAULT(1U)
48718 
48719 #define S_RECEIVE_FIFO_FAULT    0
48720 #define V_RECEIVE_FIFO_FAULT(x) ((x) << S_RECEIVE_FIFO_FAULT)
48721 #define F_RECEIVE_FIFO_FAULT    V_RECEIVE_FIFO_FAULT(1U)
48722 
48723 #define A_MAC_PORT_MTIP_KR4_CONTROL_1 0x1400
48724 
48725 #define S_SPEED_SELECTION    13
48726 #define V_SPEED_SELECTION(x) ((x) << S_SPEED_SELECTION)
48727 #define F_SPEED_SELECTION    V_SPEED_SELECTION(1U)
48728 
48729 #define S_SPEED_SELECTION1    6
48730 #define V_SPEED_SELECTION1(x) ((x) << S_SPEED_SELECTION1)
48731 #define F_SPEED_SELECTION1    V_SPEED_SELECTION1(1U)
48732 
48733 #define S_SPEED_SELECTION2    2
48734 #define M_SPEED_SELECTION2    0xfU
48735 #define V_SPEED_SELECTION2(x) ((x) << S_SPEED_SELECTION2)
48736 #define G_SPEED_SELECTION2(x) (((x) >> S_SPEED_SELECTION2) & M_SPEED_SELECTION2)
48737 
48738 #define A_MAC_PORT_MTIP_KR4_STATUS_1 0x1404
48739 
48740 #define S_RECEIVE_LINK_STAT    2
48741 #define V_RECEIVE_LINK_STAT(x) ((x) << S_RECEIVE_LINK_STAT)
48742 #define F_RECEIVE_LINK_STAT    V_RECEIVE_LINK_STAT(1U)
48743 
48744 #define A_MAC_PORT_MTIP_KR4_DEVICE_ID0 0x1408
48745 #define A_MAC_PORT_MTIP_KR4_DEVICE_ID1 0x140c
48746 
48747 #define S_T6_DEVICE_ID1    16
48748 #define M_T6_DEVICE_ID1    0xffffU
48749 #define V_T6_DEVICE_ID1(x) ((x) << S_T6_DEVICE_ID1)
48750 #define G_T6_DEVICE_ID1(x) (((x) >> S_T6_DEVICE_ID1) & M_T6_DEVICE_ID1)
48751 
48752 #define A_MAC_PORT_MTIP_KR4_SPEED_ABILITY 0x1410
48753 
48754 #define S_100G_CAPABLE    3
48755 #define V_100G_CAPABLE(x) ((x) << S_100G_CAPABLE)
48756 #define F_100G_CAPABLE    V_100G_CAPABLE(1U)
48757 
48758 #define S_40G_CAPABLE    2
48759 #define V_40G_CAPABLE(x) ((x) << S_40G_CAPABLE)
48760 #define F_40G_CAPABLE    V_40G_CAPABLE(1U)
48761 
48762 #define S_10PASS_TS_2BASE_TL_CAPABLE    1
48763 #define V_10PASS_TS_2BASE_TL_CAPABLE(x) ((x) << S_10PASS_TS_2BASE_TL_CAPABLE)
48764 #define F_10PASS_TS_2BASE_TL_CAPABLE    V_10PASS_TS_2BASE_TL_CAPABLE(1U)
48765 
48766 #define A_MAC_PORT_MTIP_KR4_DEVICES_IN_PKG1 0x1414
48767 
48768 #define S_CLAUSE_22_REG    0
48769 #define V_CLAUSE_22_REG(x) ((x) << S_CLAUSE_22_REG)
48770 #define F_CLAUSE_22_REG    V_CLAUSE_22_REG(1U)
48771 
48772 #define A_MAC_PORT_MTIP_KR4_DEVICES_IN_PKG2 0x1418
48773 
48774 #define S_VENDOR_SPECIFIC_DEVICE    15
48775 #define V_VENDOR_SPECIFIC_DEVICE(x) ((x) << S_VENDOR_SPECIFIC_DEVICE)
48776 #define F_VENDOR_SPECIFIC_DEVICE    V_VENDOR_SPECIFIC_DEVICE(1U)
48777 
48778 #define S_VENDOR_SPECIFIC_DEVICE1    14
48779 #define V_VENDOR_SPECIFIC_DEVICE1(x) ((x) << S_VENDOR_SPECIFIC_DEVICE1)
48780 #define F_VENDOR_SPECIFIC_DEVICE1    V_VENDOR_SPECIFIC_DEVICE1(1U)
48781 
48782 #define S_CLAUSE_22_EXT    13
48783 #define V_CLAUSE_22_EXT(x) ((x) << S_CLAUSE_22_EXT)
48784 #define F_CLAUSE_22_EXT    V_CLAUSE_22_EXT(1U)
48785 
48786 #define A_MAC_PORT_MTIP_KR4_CONTROL_2 0x141c
48787 
48788 #define S_PCS_TYPE_SEL    0
48789 #define M_PCS_TYPE_SEL    0x7U
48790 #define V_PCS_TYPE_SEL(x) ((x) << S_PCS_TYPE_SEL)
48791 #define G_PCS_TYPE_SEL(x) (((x) >> S_PCS_TYPE_SEL) & M_PCS_TYPE_SEL)
48792 
48793 #define A_MAC_PORT_MTIP_KR4_STATUS_2 0x1420
48794 
48795 #define S_100GBASE_R_CAPABLE    5
48796 #define V_100GBASE_R_CAPABLE(x) ((x) << S_100GBASE_R_CAPABLE)
48797 #define F_100GBASE_R_CAPABLE    V_100GBASE_R_CAPABLE(1U)
48798 
48799 #define S_40GBASE_R_CAPABLE    4
48800 #define V_40GBASE_R_CAPABLE(x) ((x) << S_40GBASE_R_CAPABLE)
48801 #define F_40GBASE_R_CAPABLE    V_40GBASE_R_CAPABLE(1U)
48802 
48803 #define S_10GBASE_T_CAPABLE    3
48804 #define V_10GBASE_T_CAPABLE(x) ((x) << S_10GBASE_T_CAPABLE)
48805 #define F_10GBASE_T_CAPABLE    V_10GBASE_T_CAPABLE(1U)
48806 
48807 #define A_MAC_PORT_MTIP_KR4_PKG_ID0 0x1438
48808 #define A_MAC_PORT_MTIP_KR4_PKG_ID1 0x143c
48809 #define A_MAC_PORT_MTIP_KR4_BASE_R_STATUS_1 0x1480
48810 
48811 #define S_T6_RX_LINK_STATUS    12
48812 #define V_T6_RX_LINK_STATUS(x) ((x) << S_T6_RX_LINK_STATUS)
48813 #define F_T6_RX_LINK_STATUS    V_T6_RX_LINK_STATUS(1U)
48814 
48815 #define S_HIGH_BER    1
48816 #define V_HIGH_BER(x) ((x) << S_HIGH_BER)
48817 #define F_HIGH_BER    V_HIGH_BER(1U)
48818 
48819 #define S_KR4_BLOCK_LOCK    0
48820 #define V_KR4_BLOCK_LOCK(x) ((x) << S_KR4_BLOCK_LOCK)
48821 #define F_KR4_BLOCK_LOCK    V_KR4_BLOCK_LOCK(1U)
48822 
48823 #define A_MAC_PORT_MTIP_KR4_BASE_R_STATUS_2 0x1484
48824 
48825 #define S_LATCHED_BL_LK    15
48826 #define V_LATCHED_BL_LK(x) ((x) << S_LATCHED_BL_LK)
48827 #define F_LATCHED_BL_LK    V_LATCHED_BL_LK(1U)
48828 
48829 #define S_LATCHED_HG_BR    14
48830 #define V_LATCHED_HG_BR(x) ((x) << S_LATCHED_HG_BR)
48831 #define F_LATCHED_HG_BR    V_LATCHED_HG_BR(1U)
48832 
48833 #define S_BER_CNT    8
48834 #define M_BER_CNT    0x3fU
48835 #define V_BER_CNT(x) ((x) << S_BER_CNT)
48836 #define G_BER_CNT(x) (((x) >> S_BER_CNT) & M_BER_CNT)
48837 
48838 #define S_ERR_BL_CNT    0
48839 #define M_ERR_BL_CNT    0xffU
48840 #define V_ERR_BL_CNT(x) ((x) << S_ERR_BL_CNT)
48841 #define G_ERR_BL_CNT(x) (((x) >> S_ERR_BL_CNT) & M_ERR_BL_CNT)
48842 
48843 #define A_MAC_PORT_MTIP_KR4_BASE_R_TEST_CONTROL 0x14a8
48844 
48845 #define S_TX_TP_EN    3
48846 #define V_TX_TP_EN(x) ((x) << S_TX_TP_EN)
48847 #define F_TX_TP_EN    V_TX_TP_EN(1U)
48848 
48849 #define S_RX_TP_EN    2
48850 #define V_RX_TP_EN(x) ((x) << S_RX_TP_EN)
48851 #define F_RX_TP_EN    V_RX_TP_EN(1U)
48852 
48853 #define A_MAC_PORT_MTIP_KR4_BASE_R_TEST_ERR_CNT 0x14ac
48854 
48855 #define S_TP_ERR_CNTR    0
48856 #define M_TP_ERR_CNTR    0xffffU
48857 #define V_TP_ERR_CNTR(x) ((x) << S_TP_ERR_CNTR)
48858 #define G_TP_ERR_CNTR(x) (((x) >> S_TP_ERR_CNTR) & M_TP_ERR_CNTR)
48859 
48860 #define A_MAC_PORT_MTIP_KR4_BER_HIGH_ORDER_CNT 0x14b0
48861 
48862 #define S_BER_HI_ORDER_CNT    0
48863 #define M_BER_HI_ORDER_CNT    0xffffU
48864 #define V_BER_HI_ORDER_CNT(x) ((x) << S_BER_HI_ORDER_CNT)
48865 #define G_BER_HI_ORDER_CNT(x) (((x) >> S_BER_HI_ORDER_CNT) & M_BER_HI_ORDER_CNT)
48866 
48867 #define A_MAC_PORT_MTIP_KR4_ERR_BLK_HIGH_ORDER_CNT 0x14b4
48868 
48869 #define S_HI_ORDER_CNT_EN    15
48870 #define V_HI_ORDER_CNT_EN(x) ((x) << S_HI_ORDER_CNT_EN)
48871 #define F_HI_ORDER_CNT_EN    V_HI_ORDER_CNT_EN(1U)
48872 
48873 #define S_ERR_BLK_CNTR    0
48874 #define M_ERR_BLK_CNTR    0x3fffU
48875 #define V_ERR_BLK_CNTR(x) ((x) << S_ERR_BLK_CNTR)
48876 #define G_ERR_BLK_CNTR(x) (((x) >> S_ERR_BLK_CNTR) & M_ERR_BLK_CNTR)
48877 
48878 #define A_MAC_PORT_MTIP_KR4_MULTI_LANE_ALIGN_STATUS_1 0x14c8
48879 
48880 #define S_LANE_ALIGN_STATUS    12
48881 #define V_LANE_ALIGN_STATUS(x) ((x) << S_LANE_ALIGN_STATUS)
48882 #define F_LANE_ALIGN_STATUS    V_LANE_ALIGN_STATUS(1U)
48883 
48884 #define S_LANE_3_BLK_LCK    3
48885 #define V_LANE_3_BLK_LCK(x) ((x) << S_LANE_3_BLK_LCK)
48886 #define F_LANE_3_BLK_LCK    V_LANE_3_BLK_LCK(1U)
48887 
48888 #define S_LANE_2_BLK_LC32_6431K    2
48889 #define V_LANE_2_BLK_LC32_6431K(x) ((x) << S_LANE_2_BLK_LC32_6431K)
48890 #define F_LANE_2_BLK_LC32_6431K    V_LANE_2_BLK_LC32_6431K(1U)
48891 
48892 #define S_LANE_1_BLK_LCK    1
48893 #define V_LANE_1_BLK_LCK(x) ((x) << S_LANE_1_BLK_LCK)
48894 #define F_LANE_1_BLK_LCK    V_LANE_1_BLK_LCK(1U)
48895 
48896 #define S_LANE_0_BLK_LCK    0
48897 #define V_LANE_0_BLK_LCK(x) ((x) << S_LANE_0_BLK_LCK)
48898 #define F_LANE_0_BLK_LCK    V_LANE_0_BLK_LCK(1U)
48899 
48900 #define A_MAC_PORT_MTIP_KR4_MULTI_LANE_ALIGN_STATUS_2 0x14cc
48901 #define A_MAC_PORT_MTIP_KR4_MULTI_LANE_ALIGN_STATUS_3 0x14d0
48902 
48903 #define S_LANE_3_ALIGN_MRKR_LCK    3
48904 #define V_LANE_3_ALIGN_MRKR_LCK(x) ((x) << S_LANE_3_ALIGN_MRKR_LCK)
48905 #define F_LANE_3_ALIGN_MRKR_LCK    V_LANE_3_ALIGN_MRKR_LCK(1U)
48906 
48907 #define S_LANE_2_ALIGN_MRKR_LCK    2
48908 #define V_LANE_2_ALIGN_MRKR_LCK(x) ((x) << S_LANE_2_ALIGN_MRKR_LCK)
48909 #define F_LANE_2_ALIGN_MRKR_LCK    V_LANE_2_ALIGN_MRKR_LCK(1U)
48910 
48911 #define S_LANE_1_ALIGN_MRKR_LCK    1
48912 #define V_LANE_1_ALIGN_MRKR_LCK(x) ((x) << S_LANE_1_ALIGN_MRKR_LCK)
48913 #define F_LANE_1_ALIGN_MRKR_LCK    V_LANE_1_ALIGN_MRKR_LCK(1U)
48914 
48915 #define S_LANE_0_ALIGN_MRKR_LCK    0
48916 #define V_LANE_0_ALIGN_MRKR_LCK(x) ((x) << S_LANE_0_ALIGN_MRKR_LCK)
48917 #define F_LANE_0_ALIGN_MRKR_LCK    V_LANE_0_ALIGN_MRKR_LCK(1U)
48918 
48919 #define A_MAC_PORT_MTIP_KR4_MULTI_LANE_ALIGN_STATUS_4 0x14d4
48920 #define A_MAC_PORT_MTIP_MDIO_CFG_STATUS 0x1600
48921 
48922 #define S_CLK_DIV    7
48923 #define M_CLK_DIV    0x1ffU
48924 #define V_CLK_DIV(x) ((x) << S_CLK_DIV)
48925 #define G_CLK_DIV(x) (((x) >> S_CLK_DIV) & M_CLK_DIV)
48926 
48927 #define S_CL45_EN    6
48928 #define V_CL45_EN(x) ((x) << S_CL45_EN)
48929 #define F_CL45_EN    V_CL45_EN(1U)
48930 
48931 #define S_DISABLE_PREAMBLE    5
48932 #define V_DISABLE_PREAMBLE(x) ((x) << S_DISABLE_PREAMBLE)
48933 #define F_DISABLE_PREAMBLE    V_DISABLE_PREAMBLE(1U)
48934 
48935 #define S_MDIO_HOLD_TIME    2
48936 #define M_MDIO_HOLD_TIME    0x7U
48937 #define V_MDIO_HOLD_TIME(x) ((x) << S_MDIO_HOLD_TIME)
48938 #define G_MDIO_HOLD_TIME(x) (((x) >> S_MDIO_HOLD_TIME) & M_MDIO_HOLD_TIME)
48939 
48940 #define S_MDIO_READ_ERR    1
48941 #define V_MDIO_READ_ERR(x) ((x) << S_MDIO_READ_ERR)
48942 #define F_MDIO_READ_ERR    V_MDIO_READ_ERR(1U)
48943 
48944 #define S_MDIO_BUSY    0
48945 #define V_MDIO_BUSY(x) ((x) << S_MDIO_BUSY)
48946 #define F_MDIO_BUSY    V_MDIO_BUSY(1U)
48947 
48948 #define A_MAC_PORT_MTIP_MDIO_COMMAND 0x1604
48949 
48950 #define S_MDIO_CMD_READ    15
48951 #define V_MDIO_CMD_READ(x) ((x) << S_MDIO_CMD_READ)
48952 #define F_MDIO_CMD_READ    V_MDIO_CMD_READ(1U)
48953 
48954 #define S_READ_INCR    14
48955 #define V_READ_INCR(x) ((x) << S_READ_INCR)
48956 #define F_READ_INCR    V_READ_INCR(1U)
48957 
48958 #define S_PORT_ADDR    5
48959 #define M_PORT_ADDR    0x1fU
48960 #define V_PORT_ADDR(x) ((x) << S_PORT_ADDR)
48961 #define G_PORT_ADDR(x) (((x) >> S_PORT_ADDR) & M_PORT_ADDR)
48962 
48963 #define S_DEV_ADDR    0
48964 #define M_DEV_ADDR    0x1fU
48965 #define V_DEV_ADDR(x) ((x) << S_DEV_ADDR)
48966 #define G_DEV_ADDR(x) (((x) >> S_DEV_ADDR) & M_DEV_ADDR)
48967 
48968 #define A_MAC_PORT_MTIP_MDIO_DATA 0x1608
48969 
48970 #define S_READBUSY    31
48971 #define V_READBUSY(x) ((x) << S_READBUSY)
48972 #define F_READBUSY    V_READBUSY(1U)
48973 
48974 #define S_DATA_WORD    0
48975 #define M_DATA_WORD    0xffffU
48976 #define V_DATA_WORD(x) ((x) << S_DATA_WORD)
48977 #define G_DATA_WORD(x) (((x) >> S_DATA_WORD) & M_DATA_WORD)
48978 
48979 #define A_MAC_PORT_MTIP_MDIO_REGADDR 0x160c
48980 
48981 #define S_MDIO_ADDR    0
48982 #define M_MDIO_ADDR    0xffffU
48983 #define V_MDIO_ADDR(x) ((x) << S_MDIO_ADDR)
48984 #define G_MDIO_ADDR(x) (((x) >> S_MDIO_ADDR) & M_MDIO_ADDR)
48985 
48986 #define A_MAC_PORT_MTIP_KR4_BIP_ERR_CNT_LANE_0 0x1720
48987 
48988 #define S_BIP_ERR_CNT_LANE_0    0
48989 #define M_BIP_ERR_CNT_LANE_0    0xffffU
48990 #define V_BIP_ERR_CNT_LANE_0(x) ((x) << S_BIP_ERR_CNT_LANE_0)
48991 #define G_BIP_ERR_CNT_LANE_0(x) (((x) >> S_BIP_ERR_CNT_LANE_0) & M_BIP_ERR_CNT_LANE_0)
48992 
48993 #define A_MAC_PORT_MTIP_KR4_BIP_ERR_CNT_LANE_1 0x1724
48994 
48995 #define S_BIP_ERR_CNT_LANE_1    0
48996 #define M_BIP_ERR_CNT_LANE_1    0xffffU
48997 #define V_BIP_ERR_CNT_LANE_1(x) ((x) << S_BIP_ERR_CNT_LANE_1)
48998 #define G_BIP_ERR_CNT_LANE_1(x) (((x) >> S_BIP_ERR_CNT_LANE_1) & M_BIP_ERR_CNT_LANE_1)
48999 
49000 #define A_MAC_PORT_MTIP_KR4_BIP_ERR_CNT_LANE_2 0x1728
49001 
49002 #define S_BIP_ERR_CNT_LANE_2    0
49003 #define M_BIP_ERR_CNT_LANE_2    0xffffU
49004 #define V_BIP_ERR_CNT_LANE_2(x) ((x) << S_BIP_ERR_CNT_LANE_2)
49005 #define G_BIP_ERR_CNT_LANE_2(x) (((x) >> S_BIP_ERR_CNT_LANE_2) & M_BIP_ERR_CNT_LANE_2)
49006 
49007 #define A_MAC_PORT_MTIP_KR4_BIP_ERR_CNT_LANE_3 0x172c
49008 
49009 #define S_BIP_ERR_CNT_LANE_3    0
49010 #define M_BIP_ERR_CNT_LANE_3    0xffffU
49011 #define V_BIP_ERR_CNT_LANE_3(x) ((x) << S_BIP_ERR_CNT_LANE_3)
49012 #define G_BIP_ERR_CNT_LANE_3(x) (((x) >> S_BIP_ERR_CNT_LANE_3) & M_BIP_ERR_CNT_LANE_3)
49013 
49014 #define A_MAC_PORT_MTIP_VLAN_TPID_0 0x1a00
49015 
49016 #define S_VLANTAG    0
49017 #define CXGBE_M_VLANTAG    0xffffU
49018 #define V_VLANTAG(x) ((x) << S_VLANTAG)
49019 #define G_VLANTAG(x) (((x) >> S_VLANTAG) & CXGBE_M_VLANTAG)
49020 
49021 #define A_MAC_PORT_MTIP_VLAN_TPID_1 0x1a04
49022 #define A_MAC_PORT_MTIP_VLAN_TPID_2 0x1a08
49023 #define A_MAC_PORT_MTIP_VLAN_TPID_3 0x1a0c
49024 #define A_MAC_PORT_MTIP_VLAN_TPID_4 0x1a10
49025 #define A_MAC_PORT_MTIP_VLAN_TPID_5 0x1a14
49026 #define A_MAC_PORT_MTIP_VLAN_TPID_6 0x1a18
49027 #define A_MAC_PORT_MTIP_VLAN_TPID_7 0x1a1c
49028 #define A_MAC_PORT_MTIP_KR4_LANE_0_MAPPING 0x1a40
49029 
49030 #define S_KR4_LANE_0_MAPPING    0
49031 #define M_KR4_LANE_0_MAPPING    0x3U
49032 #define V_KR4_LANE_0_MAPPING(x) ((x) << S_KR4_LANE_0_MAPPING)
49033 #define G_KR4_LANE_0_MAPPING(x) (((x) >> S_KR4_LANE_0_MAPPING) & M_KR4_LANE_0_MAPPING)
49034 
49035 #define A_MAC_PORT_MTIP_KR4_LANE_1_MAPPING 0x1a44
49036 
49037 #define S_KR4_LANE_1_MAPPING    0
49038 #define M_KR4_LANE_1_MAPPING    0x3U
49039 #define V_KR4_LANE_1_MAPPING(x) ((x) << S_KR4_LANE_1_MAPPING)
49040 #define G_KR4_LANE_1_MAPPING(x) (((x) >> S_KR4_LANE_1_MAPPING) & M_KR4_LANE_1_MAPPING)
49041 
49042 #define A_MAC_PORT_MTIP_KR4_LANE_2_MAPPING 0x1a48
49043 
49044 #define S_KR4_LANE_2_MAPPING    0
49045 #define M_KR4_LANE_2_MAPPING    0x3U
49046 #define V_KR4_LANE_2_MAPPING(x) ((x) << S_KR4_LANE_2_MAPPING)
49047 #define G_KR4_LANE_2_MAPPING(x) (((x) >> S_KR4_LANE_2_MAPPING) & M_KR4_LANE_2_MAPPING)
49048 
49049 #define A_MAC_PORT_MTIP_KR4_LANE_3_MAPPING 0x1a4c
49050 
49051 #define S_KR4_LANE_3_MAPPING    0
49052 #define M_KR4_LANE_3_MAPPING    0x3U
49053 #define V_KR4_LANE_3_MAPPING(x) ((x) << S_KR4_LANE_3_MAPPING)
49054 #define G_KR4_LANE_3_MAPPING(x) (((x) >> S_KR4_LANE_3_MAPPING) & M_KR4_LANE_3_MAPPING)
49055 
49056 #define A_MAC_PORT_MTIP_KR4_SCRATCH 0x1af0
49057 #define A_MAC_PORT_MTIP_KR4_CORE_REVISION 0x1af4
49058 #define A_MAC_PORT_MTIP_KR4_VL_INTVL 0x1af8
49059 
49060 #define S_SHRT_MRKR_CNFG    0
49061 #define V_SHRT_MRKR_CNFG(x) ((x) << S_SHRT_MRKR_CNFG)
49062 #define F_SHRT_MRKR_CNFG    V_SHRT_MRKR_CNFG(1U)
49063 
49064 #define A_MAC_PORT_MTIP_KR4_TX_LANE_THRESH 0x1afc
49065 #define A_MAC_PORT_MTIP_CR4_CONTROL_1 0x1b00
49066 #define A_MAC_PORT_MTIP_CR4_STATUS_1 0x1b04
49067 
49068 #define S_CR4_RX_LINK_STATUS    2
49069 #define V_CR4_RX_LINK_STATUS(x) ((x) << S_CR4_RX_LINK_STATUS)
49070 #define F_CR4_RX_LINK_STATUS    V_CR4_RX_LINK_STATUS(1U)
49071 
49072 #define A_MAC_PORT_MTIP_CR4_DEVICE_ID0 0x1b08
49073 
49074 #define S_CR4_DEVICE_ID0    0
49075 #define M_CR4_DEVICE_ID0    0xffffU
49076 #define V_CR4_DEVICE_ID0(x) ((x) << S_CR4_DEVICE_ID0)
49077 #define G_CR4_DEVICE_ID0(x) (((x) >> S_CR4_DEVICE_ID0) & M_CR4_DEVICE_ID0)
49078 
49079 #define A_MAC_PORT_MTIP_CR4_DEVICE_ID1 0x1b0c
49080 
49081 #define S_CR4_DEVICE_ID1    0
49082 #define M_CR4_DEVICE_ID1    0xffffU
49083 #define V_CR4_DEVICE_ID1(x) ((x) << S_CR4_DEVICE_ID1)
49084 #define G_CR4_DEVICE_ID1(x) (((x) >> S_CR4_DEVICE_ID1) & M_CR4_DEVICE_ID1)
49085 
49086 #define A_MAC_PORT_MTIP_CR4_SPEED_ABILITY 0x1b10
49087 
49088 #define S_CR4_100G_CAPABLE    8
49089 #define V_CR4_100G_CAPABLE(x) ((x) << S_CR4_100G_CAPABLE)
49090 #define F_CR4_100G_CAPABLE    V_CR4_100G_CAPABLE(1U)
49091 
49092 #define S_CR4_40G_CAPABLE    7
49093 #define V_CR4_40G_CAPABLE(x) ((x) << S_CR4_40G_CAPABLE)
49094 #define F_CR4_40G_CAPABLE    V_CR4_40G_CAPABLE(1U)
49095 
49096 #define A_MAC_PORT_MTIP_CR4_DEVICES_IN_PKG1 0x1b14
49097 
49098 #define S_CLAUSE22REG_PRESENT    0
49099 #define V_CLAUSE22REG_PRESENT(x) ((x) << S_CLAUSE22REG_PRESENT)
49100 #define F_CLAUSE22REG_PRESENT    V_CLAUSE22REG_PRESENT(1U)
49101 
49102 #define A_MAC_PORT_MTIP_CR4_DEVICES_IN_PKG2 0x1b18
49103 
49104 #define S_VSD_2_PRESENT    15
49105 #define V_VSD_2_PRESENT(x) ((x) << S_VSD_2_PRESENT)
49106 #define F_VSD_2_PRESENT    V_VSD_2_PRESENT(1U)
49107 
49108 #define S_VSD_1_PRESENT    14
49109 #define V_VSD_1_PRESENT(x) ((x) << S_VSD_1_PRESENT)
49110 #define F_VSD_1_PRESENT    V_VSD_1_PRESENT(1U)
49111 
49112 #define S_CLAUSE22_EXT_PRESENT    13
49113 #define V_CLAUSE22_EXT_PRESENT(x) ((x) << S_CLAUSE22_EXT_PRESENT)
49114 #define F_CLAUSE22_EXT_PRESENT    V_CLAUSE22_EXT_PRESENT(1U)
49115 
49116 #define A_MAC_PORT_MTIP_CR4_CONTROL_2 0x1b1c
49117 
49118 #define S_CR4_PCS_TYPE_SELECTION    0
49119 #define M_CR4_PCS_TYPE_SELECTION    0x7U
49120 #define V_CR4_PCS_TYPE_SELECTION(x) ((x) << S_CR4_PCS_TYPE_SELECTION)
49121 #define G_CR4_PCS_TYPE_SELECTION(x) (((x) >> S_CR4_PCS_TYPE_SELECTION) & M_CR4_PCS_TYPE_SELECTION)
49122 
49123 #define A_MAC_PORT_MTIP_CR4_STATUS_2 0x1b20
49124 #define A_MAC_PORT_MTIP_CR4_PKG_ID0 0x1b38
49125 #define A_MAC_PORT_MTIP_CR4_PKG_ID1 0x1b3c
49126 #define A_MAC_PORT_MTIP_CR4_BASE_R_STATUS_1 0x1b80
49127 
49128 #define S_RX_LINK_STAT    12
49129 #define V_RX_LINK_STAT(x) ((x) << S_RX_LINK_STAT)
49130 #define F_RX_LINK_STAT    V_RX_LINK_STAT(1U)
49131 
49132 #define S_BR_BLOCK_LOCK    0
49133 #define V_BR_BLOCK_LOCK(x) ((x) << S_BR_BLOCK_LOCK)
49134 #define F_BR_BLOCK_LOCK    V_BR_BLOCK_LOCK(1U)
49135 
49136 #define A_MAC_PORT_MTIP_CR4_BASE_R_STATUS_2 0x1b84
49137 
49138 #define S_BER_COUNTER    8
49139 #define M_BER_COUNTER    0x3fU
49140 #define V_BER_COUNTER(x) ((x) << S_BER_COUNTER)
49141 #define G_BER_COUNTER(x) (((x) >> S_BER_COUNTER) & M_BER_COUNTER)
49142 
49143 #define S_ERRORED_BLOCKS_CNTR    0
49144 #define M_ERRORED_BLOCKS_CNTR    0xffU
49145 #define V_ERRORED_BLOCKS_CNTR(x) ((x) << S_ERRORED_BLOCKS_CNTR)
49146 #define G_ERRORED_BLOCKS_CNTR(x) (((x) >> S_ERRORED_BLOCKS_CNTR) & M_ERRORED_BLOCKS_CNTR)
49147 
49148 #define A_MAC_PORT_MTIP_CR4_BASE_R_TEST_CONTROL 0x1ba8
49149 
49150 #define S_SCRAMBLED_ID_TP_EN    7
49151 #define V_SCRAMBLED_ID_TP_EN(x) ((x) << S_SCRAMBLED_ID_TP_EN)
49152 #define F_SCRAMBLED_ID_TP_EN    V_SCRAMBLED_ID_TP_EN(1U)
49153 
49154 #define A_MAC_PORT_MTIP_CR4_BASE_R_TEST_ERR_CNT 0x1bac
49155 
49156 #define S_BASE_R_TEST_ERR_CNT    0
49157 #define M_BASE_R_TEST_ERR_CNT    0xffffU
49158 #define V_BASE_R_TEST_ERR_CNT(x) ((x) << S_BASE_R_TEST_ERR_CNT)
49159 #define G_BASE_R_TEST_ERR_CNT(x) (((x) >> S_BASE_R_TEST_ERR_CNT) & M_BASE_R_TEST_ERR_CNT)
49160 
49161 #define A_MAC_PORT_MTIP_CR4_BER_HIGH_ORDER_CNT 0x1bb0
49162 
49163 #define S_BER_HIGH_ORDER_CNT    0
49164 #define M_BER_HIGH_ORDER_CNT    0xffffU
49165 #define V_BER_HIGH_ORDER_CNT(x) ((x) << S_BER_HIGH_ORDER_CNT)
49166 #define G_BER_HIGH_ORDER_CNT(x) (((x) >> S_BER_HIGH_ORDER_CNT) & M_BER_HIGH_ORDER_CNT)
49167 
49168 #define A_MAC_PORT_MTIP_CR4_ERR_BLK_HIGH_ORDER_CNT 0x1bb4
49169 
49170 #define S_HI_ORDER_CNT_PRESENT    15
49171 #define V_HI_ORDER_CNT_PRESENT(x) ((x) << S_HI_ORDER_CNT_PRESENT)
49172 #define F_HI_ORDER_CNT_PRESENT    V_HI_ORDER_CNT_PRESENT(1U)
49173 
49174 #define S_ERR_BLKS_CNTR    0
49175 #define M_ERR_BLKS_CNTR    0x3fffU
49176 #define V_ERR_BLKS_CNTR(x) ((x) << S_ERR_BLKS_CNTR)
49177 #define G_ERR_BLKS_CNTR(x) (((x) >> S_ERR_BLKS_CNTR) & M_ERR_BLKS_CNTR)
49178 
49179 #define A_MAC_PORT_MTIP_CR4_MULTI_LANE_ALIGN_STATUS_1 0x1bc8
49180 
49181 #define S_LANE_ALIGN_STAT    12
49182 #define V_LANE_ALIGN_STAT(x) ((x) << S_LANE_ALIGN_STAT)
49183 #define F_LANE_ALIGN_STAT    V_LANE_ALIGN_STAT(1U)
49184 
49185 #define S_LANE_7_BLCK_LCK    7
49186 #define V_LANE_7_BLCK_LCK(x) ((x) << S_LANE_7_BLCK_LCK)
49187 #define F_LANE_7_BLCK_LCK    V_LANE_7_BLCK_LCK(1U)
49188 
49189 #define S_LANE_6_BLCK_LCK    6
49190 #define V_LANE_6_BLCK_LCK(x) ((x) << S_LANE_6_BLCK_LCK)
49191 #define F_LANE_6_BLCK_LCK    V_LANE_6_BLCK_LCK(1U)
49192 
49193 #define S_LANE_5_BLCK_LCK    5
49194 #define V_LANE_5_BLCK_LCK(x) ((x) << S_LANE_5_BLCK_LCK)
49195 #define F_LANE_5_BLCK_LCK    V_LANE_5_BLCK_LCK(1U)
49196 
49197 #define S_LANE_4_BLCK_LCK    4
49198 #define V_LANE_4_BLCK_LCK(x) ((x) << S_LANE_4_BLCK_LCK)
49199 #define F_LANE_4_BLCK_LCK    V_LANE_4_BLCK_LCK(1U)
49200 
49201 #define S_LANE_3_BLCK_LCK    3
49202 #define V_LANE_3_BLCK_LCK(x) ((x) << S_LANE_3_BLCK_LCK)
49203 #define F_LANE_3_BLCK_LCK    V_LANE_3_BLCK_LCK(1U)
49204 
49205 #define S_LANE_2_BLCK_LCK    2
49206 #define V_LANE_2_BLCK_LCK(x) ((x) << S_LANE_2_BLCK_LCK)
49207 #define F_LANE_2_BLCK_LCK    V_LANE_2_BLCK_LCK(1U)
49208 
49209 #define S_LANE_1_BLCK_LCK    1
49210 #define V_LANE_1_BLCK_LCK(x) ((x) << S_LANE_1_BLCK_LCK)
49211 #define F_LANE_1_BLCK_LCK    V_LANE_1_BLCK_LCK(1U)
49212 
49213 #define S_LANE_0_BLCK_LCK    0
49214 #define V_LANE_0_BLCK_LCK(x) ((x) << S_LANE_0_BLCK_LCK)
49215 #define F_LANE_0_BLCK_LCK    V_LANE_0_BLCK_LCK(1U)
49216 
49217 #define A_MAC_PORT_MTIP_CR4_MULTI_LANE_ALIGN_STATUS_2 0x1bcc
49218 
49219 #define S_LANE_19_BLCK_LCK    11
49220 #define V_LANE_19_BLCK_LCK(x) ((x) << S_LANE_19_BLCK_LCK)
49221 #define F_LANE_19_BLCK_LCK    V_LANE_19_BLCK_LCK(1U)
49222 
49223 #define S_LANE_18_BLCK_LCK    10
49224 #define V_LANE_18_BLCK_LCK(x) ((x) << S_LANE_18_BLCK_LCK)
49225 #define F_LANE_18_BLCK_LCK    V_LANE_18_BLCK_LCK(1U)
49226 
49227 #define S_LANE_17_BLCK_LCK    9
49228 #define V_LANE_17_BLCK_LCK(x) ((x) << S_LANE_17_BLCK_LCK)
49229 #define F_LANE_17_BLCK_LCK    V_LANE_17_BLCK_LCK(1U)
49230 
49231 #define S_LANE_16_BLCK_LCK    8
49232 #define V_LANE_16_BLCK_LCK(x) ((x) << S_LANE_16_BLCK_LCK)
49233 #define F_LANE_16_BLCK_LCK    V_LANE_16_BLCK_LCK(1U)
49234 
49235 #define S_LANE_15_BLCK_LCK    7
49236 #define V_LANE_15_BLCK_LCK(x) ((x) << S_LANE_15_BLCK_LCK)
49237 #define F_LANE_15_BLCK_LCK    V_LANE_15_BLCK_LCK(1U)
49238 
49239 #define S_LANE_14_BLCK_LCK    6
49240 #define V_LANE_14_BLCK_LCK(x) ((x) << S_LANE_14_BLCK_LCK)
49241 #define F_LANE_14_BLCK_LCK    V_LANE_14_BLCK_LCK(1U)
49242 
49243 #define S_LANE_13_BLCK_LCK    5
49244 #define V_LANE_13_BLCK_LCK(x) ((x) << S_LANE_13_BLCK_LCK)
49245 #define F_LANE_13_BLCK_LCK    V_LANE_13_BLCK_LCK(1U)
49246 
49247 #define S_LANE_12_BLCK_LCK    4
49248 #define V_LANE_12_BLCK_LCK(x) ((x) << S_LANE_12_BLCK_LCK)
49249 #define F_LANE_12_BLCK_LCK    V_LANE_12_BLCK_LCK(1U)
49250 
49251 #define S_LANE_11_BLCK_LCK    3
49252 #define V_LANE_11_BLCK_LCK(x) ((x) << S_LANE_11_BLCK_LCK)
49253 #define F_LANE_11_BLCK_LCK    V_LANE_11_BLCK_LCK(1U)
49254 
49255 #define S_LANE_10_BLCK_LCK    2
49256 #define V_LANE_10_BLCK_LCK(x) ((x) << S_LANE_10_BLCK_LCK)
49257 #define F_LANE_10_BLCK_LCK    V_LANE_10_BLCK_LCK(1U)
49258 
49259 #define S_LANE_9_BLCK_LCK    1
49260 #define V_LANE_9_BLCK_LCK(x) ((x) << S_LANE_9_BLCK_LCK)
49261 #define F_LANE_9_BLCK_LCK    V_LANE_9_BLCK_LCK(1U)
49262 
49263 #define S_LANE_8_BLCK_LCK    0
49264 #define V_LANE_8_BLCK_LCK(x) ((x) << S_LANE_8_BLCK_LCK)
49265 #define F_LANE_8_BLCK_LCK    V_LANE_8_BLCK_LCK(1U)
49266 
49267 #define A_MAC_PORT_MTIP_CR4_MULTI_LANE_ALIGN_STATUS_3 0x1bd0
49268 
49269 #define S_LANE7_ALGN_MRKR_LCK    7
49270 #define V_LANE7_ALGN_MRKR_LCK(x) ((x) << S_LANE7_ALGN_MRKR_LCK)
49271 #define F_LANE7_ALGN_MRKR_LCK    V_LANE7_ALGN_MRKR_LCK(1U)
49272 
49273 #define S_LANE6_ALGN_MRKR_LCK    6
49274 #define V_LANE6_ALGN_MRKR_LCK(x) ((x) << S_LANE6_ALGN_MRKR_LCK)
49275 #define F_LANE6_ALGN_MRKR_LCK    V_LANE6_ALGN_MRKR_LCK(1U)
49276 
49277 #define S_LANE5_ALGN_MRKR_LCK    5
49278 #define V_LANE5_ALGN_MRKR_LCK(x) ((x) << S_LANE5_ALGN_MRKR_LCK)
49279 #define F_LANE5_ALGN_MRKR_LCK    V_LANE5_ALGN_MRKR_LCK(1U)
49280 
49281 #define S_LANE4_ALGN_MRKR_LCK    4
49282 #define V_LANE4_ALGN_MRKR_LCK(x) ((x) << S_LANE4_ALGN_MRKR_LCK)
49283 #define F_LANE4_ALGN_MRKR_LCK    V_LANE4_ALGN_MRKR_LCK(1U)
49284 
49285 #define S_LANE3_ALGN_MRKR_LCK    3
49286 #define V_LANE3_ALGN_MRKR_LCK(x) ((x) << S_LANE3_ALGN_MRKR_LCK)
49287 #define F_LANE3_ALGN_MRKR_LCK    V_LANE3_ALGN_MRKR_LCK(1U)
49288 
49289 #define S_LANE2_ALGN_MRKR_LCK    2
49290 #define V_LANE2_ALGN_MRKR_LCK(x) ((x) << S_LANE2_ALGN_MRKR_LCK)
49291 #define F_LANE2_ALGN_MRKR_LCK    V_LANE2_ALGN_MRKR_LCK(1U)
49292 
49293 #define S_LANE1_ALGN_MRKR_LCK    1
49294 #define V_LANE1_ALGN_MRKR_LCK(x) ((x) << S_LANE1_ALGN_MRKR_LCK)
49295 #define F_LANE1_ALGN_MRKR_LCK    V_LANE1_ALGN_MRKR_LCK(1U)
49296 
49297 #define S_LANE0_ALGN_MRKR_LCK    0
49298 #define V_LANE0_ALGN_MRKR_LCK(x) ((x) << S_LANE0_ALGN_MRKR_LCK)
49299 #define F_LANE0_ALGN_MRKR_LCK    V_LANE0_ALGN_MRKR_LCK(1U)
49300 
49301 #define A_MAC_PORT_MTIP_CR4_MULTI_LANE_ALIGN_STATUS_4 0x1bd4
49302 
49303 #define S_LANE19_ALGN_MRKR_LCK    11
49304 #define V_LANE19_ALGN_MRKR_LCK(x) ((x) << S_LANE19_ALGN_MRKR_LCK)
49305 #define F_LANE19_ALGN_MRKR_LCK    V_LANE19_ALGN_MRKR_LCK(1U)
49306 
49307 #define S_LANE18_ALGN_MRKR_LCK    10
49308 #define V_LANE18_ALGN_MRKR_LCK(x) ((x) << S_LANE18_ALGN_MRKR_LCK)
49309 #define F_LANE18_ALGN_MRKR_LCK    V_LANE18_ALGN_MRKR_LCK(1U)
49310 
49311 #define S_LANE17_ALGN_MRKR_LCK    9
49312 #define V_LANE17_ALGN_MRKR_LCK(x) ((x) << S_LANE17_ALGN_MRKR_LCK)
49313 #define F_LANE17_ALGN_MRKR_LCK    V_LANE17_ALGN_MRKR_LCK(1U)
49314 
49315 #define S_LANE16_ALGN_MRKR_LCK    8
49316 #define V_LANE16_ALGN_MRKR_LCK(x) ((x) << S_LANE16_ALGN_MRKR_LCK)
49317 #define F_LANE16_ALGN_MRKR_LCK    V_LANE16_ALGN_MRKR_LCK(1U)
49318 
49319 #define S_LANE15_ALGN_MRKR_LCK    7
49320 #define V_LANE15_ALGN_MRKR_LCK(x) ((x) << S_LANE15_ALGN_MRKR_LCK)
49321 #define F_LANE15_ALGN_MRKR_LCK    V_LANE15_ALGN_MRKR_LCK(1U)
49322 
49323 #define S_LANE14_ALGN_MRKR_LCK    6
49324 #define V_LANE14_ALGN_MRKR_LCK(x) ((x) << S_LANE14_ALGN_MRKR_LCK)
49325 #define F_LANE14_ALGN_MRKR_LCK    V_LANE14_ALGN_MRKR_LCK(1U)
49326 
49327 #define S_LANE13_ALGN_MRKR_LCK    5
49328 #define V_LANE13_ALGN_MRKR_LCK(x) ((x) << S_LANE13_ALGN_MRKR_LCK)
49329 #define F_LANE13_ALGN_MRKR_LCK    V_LANE13_ALGN_MRKR_LCK(1U)
49330 
49331 #define S_LANE12_ALGN_MRKR_LCK    4
49332 #define V_LANE12_ALGN_MRKR_LCK(x) ((x) << S_LANE12_ALGN_MRKR_LCK)
49333 #define F_LANE12_ALGN_MRKR_LCK    V_LANE12_ALGN_MRKR_LCK(1U)
49334 
49335 #define S_LANE11_ALGN_MRKR_LCK    3
49336 #define V_LANE11_ALGN_MRKR_LCK(x) ((x) << S_LANE11_ALGN_MRKR_LCK)
49337 #define F_LANE11_ALGN_MRKR_LCK    V_LANE11_ALGN_MRKR_LCK(1U)
49338 
49339 #define S_LANE10_ALGN_MRKR_LCK    2
49340 #define V_LANE10_ALGN_MRKR_LCK(x) ((x) << S_LANE10_ALGN_MRKR_LCK)
49341 #define F_LANE10_ALGN_MRKR_LCK    V_LANE10_ALGN_MRKR_LCK(1U)
49342 
49343 #define S_LANE9_ALGN_MRKR_LCK    1
49344 #define V_LANE9_ALGN_MRKR_LCK(x) ((x) << S_LANE9_ALGN_MRKR_LCK)
49345 #define F_LANE9_ALGN_MRKR_LCK    V_LANE9_ALGN_MRKR_LCK(1U)
49346 
49347 #define S_LANE8_ALGN_MRKR_LCK    0
49348 #define V_LANE8_ALGN_MRKR_LCK(x) ((x) << S_LANE8_ALGN_MRKR_LCK)
49349 #define F_LANE8_ALGN_MRKR_LCK    V_LANE8_ALGN_MRKR_LCK(1U)
49350 
49351 #define A_MAC_PORT_MTIP_PCS_CTL 0x1e00
49352 
49353 #define S_PCS_LPBK    14
49354 #define V_PCS_LPBK(x) ((x) << S_PCS_LPBK)
49355 #define F_PCS_LPBK    V_PCS_LPBK(1U)
49356 
49357 #define S_SPEED_SEL1    13
49358 #define V_SPEED_SEL1(x) ((x) << S_SPEED_SEL1)
49359 #define F_SPEED_SEL1    V_SPEED_SEL1(1U)
49360 
49361 #define S_LP_MODE    11
49362 #define V_LP_MODE(x) ((x) << S_LP_MODE)
49363 #define F_LP_MODE    V_LP_MODE(1U)
49364 
49365 #define S_SPEED_SEL0    6
49366 #define V_SPEED_SEL0(x) ((x) << S_SPEED_SEL0)
49367 #define F_SPEED_SEL0    V_SPEED_SEL0(1U)
49368 
49369 #define S_PCS_SPEED    2
49370 #define M_PCS_SPEED    0xfU
49371 #define V_PCS_SPEED(x) ((x) << S_PCS_SPEED)
49372 #define G_PCS_SPEED(x) (((x) >> S_PCS_SPEED) & M_PCS_SPEED)
49373 
49374 #define A_MAC_PORT_MTIP_PCS_STATUS1 0x1e04
49375 
49376 #define S_FAULTDET    7
49377 #define V_FAULTDET(x) ((x) << S_FAULTDET)
49378 #define F_FAULTDET    V_FAULTDET(1U)
49379 
49380 #define S_RX_LINK_STATUS    2
49381 #define V_RX_LINK_STATUS(x) ((x) << S_RX_LINK_STATUS)
49382 #define F_RX_LINK_STATUS    V_RX_LINK_STATUS(1U)
49383 
49384 #define S_LOPWRABL    1
49385 #define V_LOPWRABL(x) ((x) << S_LOPWRABL)
49386 #define F_LOPWRABL    V_LOPWRABL(1U)
49387 
49388 #define A_MAC_PORT_MTIP_PCS_DEVICE_ID0 0x1e08
49389 
49390 #define S_DEVICE_ID0    0
49391 #define M_DEVICE_ID0    0xffffU
49392 #define V_DEVICE_ID0(x) ((x) << S_DEVICE_ID0)
49393 #define G_DEVICE_ID0(x) (((x) >> S_DEVICE_ID0) & M_DEVICE_ID0)
49394 
49395 #define A_MAC_PORT_MTIP_PCS_DEVICE_ID1 0x1e0c
49396 
49397 #define S_DEVICE_ID1    0
49398 #define M_DEVICE_ID1    0xffffU
49399 #define V_DEVICE_ID1(x) ((x) << S_DEVICE_ID1)
49400 #define G_DEVICE_ID1(x) (((x) >> S_DEVICE_ID1) & M_DEVICE_ID1)
49401 
49402 #define A_MAC_PORT_MTIP_PCS_SPEED_ABILITY 0x1e10
49403 
49404 #define S_100G    8
49405 #define V_100G(x) ((x) << S_100G)
49406 #define F_100G    V_100G(1U)
49407 
49408 #define S_40G    7
49409 #define V_40G(x) ((x) << S_40G)
49410 #define F_40G    V_40G(1U)
49411 
49412 #define S_10BASE_TL    1
49413 #define V_10BASE_TL(x) ((x) << S_10BASE_TL)
49414 #define F_10BASE_TL    V_10BASE_TL(1U)
49415 
49416 #define S_10G    0
49417 #define V_10G(x) ((x) << S_10G)
49418 #define F_10G    V_10G(1U)
49419 
49420 #define A_MAC_PORT_MTIP_PCS_DEVICE_PKG1 0x1e14
49421 
49422 #define S_TC_PRESENT    6
49423 #define V_TC_PRESENT(x) ((x) << S_TC_PRESENT)
49424 #define F_TC_PRESENT    V_TC_PRESENT(1U)
49425 
49426 #define S_DTEXS    5
49427 #define V_DTEXS(x) ((x) << S_DTEXS)
49428 #define F_DTEXS    V_DTEXS(1U)
49429 
49430 #define S_PHYXS    4
49431 #define V_PHYXS(x) ((x) << S_PHYXS)
49432 #define F_PHYXS    V_PHYXS(1U)
49433 
49434 #define S_PCS    3
49435 #define V_PCS(x) ((x) << S_PCS)
49436 #define F_PCS    V_PCS(1U)
49437 
49438 #define S_WIS    2
49439 #define V_WIS(x) ((x) << S_WIS)
49440 #define F_WIS    V_WIS(1U)
49441 
49442 #define S_PMD_PMA    1
49443 #define V_PMD_PMA(x) ((x) << S_PMD_PMA)
49444 #define F_PMD_PMA    V_PMD_PMA(1U)
49445 
49446 #define S_CL22    0
49447 #define V_CL22(x) ((x) << S_CL22)
49448 #define F_CL22    V_CL22(1U)
49449 
49450 #define A_MAC_PORT_MTIP_PCS_DEVICE_PKG2 0x1e18
49451 
49452 #define S_VENDDEV2    15
49453 #define V_VENDDEV2(x) ((x) << S_VENDDEV2)
49454 #define F_VENDDEV2    V_VENDDEV2(1U)
49455 
49456 #define S_VENDDEV1    14
49457 #define V_VENDDEV1(x) ((x) << S_VENDDEV1)
49458 #define F_VENDDEV1    V_VENDDEV1(1U)
49459 
49460 #define S_CL22EXT    13
49461 #define V_CL22EXT(x) ((x) << S_CL22EXT)
49462 #define F_CL22EXT    V_CL22EXT(1U)
49463 
49464 #define A_MAC_PORT_MTIP_PCS_CTL2 0x1e1c
49465 
49466 #define S_PCSTYPE    0
49467 #define M_PCSTYPE    0x7U
49468 #define V_PCSTYPE(x) ((x) << S_PCSTYPE)
49469 #define G_PCSTYPE(x) (((x) >> S_PCSTYPE) & M_PCSTYPE)
49470 
49471 #define A_MAC_PORT_MTIP_PCS_STATUS2 0x1e20
49472 
49473 #define S_PCS_STAT2_DEVICE    15
49474 #define V_PCS_STAT2_DEVICE(x) ((x) << S_PCS_STAT2_DEVICE)
49475 #define F_PCS_STAT2_DEVICE    V_PCS_STAT2_DEVICE(1U)
49476 
49477 #define S_TXFAULT    7
49478 #define V_TXFAULT(x) ((x) << S_TXFAULT)
49479 #define F_TXFAULT    V_TXFAULT(1U)
49480 
49481 #define S_RXFAULT    6
49482 #define V_RXFAULT(x) ((x) << S_RXFAULT)
49483 #define F_RXFAULT    V_RXFAULT(1U)
49484 
49485 #define S_100BASE_R    5
49486 #define V_100BASE_R(x) ((x) << S_100BASE_R)
49487 #define F_100BASE_R    V_100BASE_R(1U)
49488 
49489 #define S_40GBASE_R    4
49490 #define V_40GBASE_R(x) ((x) << S_40GBASE_R)
49491 #define F_40GBASE_R    V_40GBASE_R(1U)
49492 
49493 #define S_10GBASE_T    3
49494 #define V_10GBASE_T(x) ((x) << S_10GBASE_T)
49495 #define F_10GBASE_T    V_10GBASE_T(1U)
49496 
49497 #define S_10GBASE_W    2
49498 #define V_10GBASE_W(x) ((x) << S_10GBASE_W)
49499 #define F_10GBASE_W    V_10GBASE_W(1U)
49500 
49501 #define S_10GBASE_X    1
49502 #define V_10GBASE_X(x) ((x) << S_10GBASE_X)
49503 #define F_10GBASE_X    V_10GBASE_X(1U)
49504 
49505 #define S_10GBASE_R    0
49506 #define V_10GBASE_R(x) ((x) << S_10GBASE_R)
49507 #define F_10GBASE_R    V_10GBASE_R(1U)
49508 
49509 #define A_MAC_PORT_MTIP_CR4_BIP_ERR_CNTLANE_0 0x1e20
49510 
49511 #define S_BIP_ERR_CNTLANE_0    0
49512 #define M_BIP_ERR_CNTLANE_0    0xffffU
49513 #define V_BIP_ERR_CNTLANE_0(x) ((x) << S_BIP_ERR_CNTLANE_0)
49514 #define G_BIP_ERR_CNTLANE_0(x) (((x) >> S_BIP_ERR_CNTLANE_0) & M_BIP_ERR_CNTLANE_0)
49515 
49516 #define A_MAC_PORT_MTIP_CR4_BIP_ERR_CNTLANE_1 0x1e24
49517 
49518 #define S_BIP_ERR_CNTLANE_1    0
49519 #define M_BIP_ERR_CNTLANE_1    0xffffU
49520 #define V_BIP_ERR_CNTLANE_1(x) ((x) << S_BIP_ERR_CNTLANE_1)
49521 #define G_BIP_ERR_CNTLANE_1(x) (((x) >> S_BIP_ERR_CNTLANE_1) & M_BIP_ERR_CNTLANE_1)
49522 
49523 #define A_MAC_PORT_MTIP_CR4_BIP_ERR_CNTLANE_2 0x1e28
49524 
49525 #define S_BIP_ERR_CNTLANE_2    0
49526 #define M_BIP_ERR_CNTLANE_2    0xffffU
49527 #define V_BIP_ERR_CNTLANE_2(x) ((x) << S_BIP_ERR_CNTLANE_2)
49528 #define G_BIP_ERR_CNTLANE_2(x) (((x) >> S_BIP_ERR_CNTLANE_2) & M_BIP_ERR_CNTLANE_2)
49529 
49530 #define A_MAC_PORT_MTIP_CR4_BIP_ERR_CNTLANE_3 0x1e2c
49531 
49532 #define S_BIP_ERR_CNTLANE_3    0
49533 #define M_BIP_ERR_CNTLANE_3    0xffffU
49534 #define V_BIP_ERR_CNTLANE_3(x) ((x) << S_BIP_ERR_CNTLANE_3)
49535 #define G_BIP_ERR_CNTLANE_3(x) (((x) >> S_BIP_ERR_CNTLANE_3) & M_BIP_ERR_CNTLANE_3)
49536 
49537 #define A_MAC_PORT_MTIP_CR4_BIP_ERR_CNTLANE_4 0x1e30
49538 
49539 #define S_BIP_ERR_CNTLANE_4    0
49540 #define M_BIP_ERR_CNTLANE_4    0xffffU
49541 #define V_BIP_ERR_CNTLANE_4(x) ((x) << S_BIP_ERR_CNTLANE_4)
49542 #define G_BIP_ERR_CNTLANE_4(x) (((x) >> S_BIP_ERR_CNTLANE_4) & M_BIP_ERR_CNTLANE_4)
49543 
49544 #define A_MAC_PORT_MTIP_CR4_BIP_ERR_CNTLANE_5 0x1e34
49545 
49546 #define S_BIP_ERR_CNTLANE_5    0
49547 #define M_BIP_ERR_CNTLANE_5    0xffffU
49548 #define V_BIP_ERR_CNTLANE_5(x) ((x) << S_BIP_ERR_CNTLANE_5)
49549 #define G_BIP_ERR_CNTLANE_5(x) (((x) >> S_BIP_ERR_CNTLANE_5) & M_BIP_ERR_CNTLANE_5)
49550 
49551 #define A_MAC_PORT_MTIP_PCS_PKG_ID0 0x1e38
49552 
49553 #define S_PKG_ID0    0
49554 #define M_PKG_ID0    0xffffU
49555 #define V_PKG_ID0(x) ((x) << S_PKG_ID0)
49556 #define G_PKG_ID0(x) (((x) >> S_PKG_ID0) & M_PKG_ID0)
49557 
49558 #define A_MAC_PORT_MTIP_CR4_BIP_ERR_CNTLANE_6 0x1e38
49559 
49560 #define S_BIP_ERR_CNTLANE_6    0
49561 #define M_BIP_ERR_CNTLANE_6    0xffffU
49562 #define V_BIP_ERR_CNTLANE_6(x) ((x) << S_BIP_ERR_CNTLANE_6)
49563 #define G_BIP_ERR_CNTLANE_6(x) (((x) >> S_BIP_ERR_CNTLANE_6) & M_BIP_ERR_CNTLANE_6)
49564 
49565 #define A_MAC_PORT_MTIP_PCS_PKG_ID1 0x1e3c
49566 
49567 #define S_PKG_ID1    0
49568 #define M_PKG_ID1    0xffffU
49569 #define V_PKG_ID1(x) ((x) << S_PKG_ID1)
49570 #define G_PKG_ID1(x) (((x) >> S_PKG_ID1) & M_PKG_ID1)
49571 
49572 #define A_MAC_PORT_MTIP_CR4_BIP_ERR_CNTLANE_7 0x1e3c
49573 
49574 #define S_BIP_ERR_CNTLANE_7    0
49575 #define M_BIP_ERR_CNTLANE_7    0xffffU
49576 #define V_BIP_ERR_CNTLANE_7(x) ((x) << S_BIP_ERR_CNTLANE_7)
49577 #define G_BIP_ERR_CNTLANE_7(x) (((x) >> S_BIP_ERR_CNTLANE_7) & M_BIP_ERR_CNTLANE_7)
49578 
49579 #define A_MAC_PORT_MTIP_CR4_BIP_ERR_CNTLANE_8 0x1e40
49580 
49581 #define S_BIP_ERR_CNTLANE_8    0
49582 #define M_BIP_ERR_CNTLANE_8    0xffffU
49583 #define V_BIP_ERR_CNTLANE_8(x) ((x) << S_BIP_ERR_CNTLANE_8)
49584 #define G_BIP_ERR_CNTLANE_8(x) (((x) >> S_BIP_ERR_CNTLANE_8) & M_BIP_ERR_CNTLANE_8)
49585 
49586 #define A_MAC_PORT_MTIP_CR4_BIP_ERR_CNTLANE_9 0x1e44
49587 
49588 #define S_BIP_ERR_CNTLANE_9    0
49589 #define M_BIP_ERR_CNTLANE_9    0xffffU
49590 #define V_BIP_ERR_CNTLANE_9(x) ((x) << S_BIP_ERR_CNTLANE_9)
49591 #define G_BIP_ERR_CNTLANE_9(x) (((x) >> S_BIP_ERR_CNTLANE_9) & M_BIP_ERR_CNTLANE_9)
49592 
49593 #define A_MAC_PORT_MTIP_CR4_BIP_ERR_CNTLANE_10 0x1e48
49594 
49595 #define S_BIP_ERR_CNTLANE_10    0
49596 #define M_BIP_ERR_CNTLANE_10    0xffffU
49597 #define V_BIP_ERR_CNTLANE_10(x) ((x) << S_BIP_ERR_CNTLANE_10)
49598 #define G_BIP_ERR_CNTLANE_10(x) (((x) >> S_BIP_ERR_CNTLANE_10) & M_BIP_ERR_CNTLANE_10)
49599 
49600 #define A_MAC_PORT_MTIP_CR4_BIP_ERR_CNTLANE_11 0x1e4c
49601 
49602 #define S_BIP_ERR_CNTLANE_11    0
49603 #define M_BIP_ERR_CNTLANE_11    0xffffU
49604 #define V_BIP_ERR_CNTLANE_11(x) ((x) << S_BIP_ERR_CNTLANE_11)
49605 #define G_BIP_ERR_CNTLANE_11(x) (((x) >> S_BIP_ERR_CNTLANE_11) & M_BIP_ERR_CNTLANE_11)
49606 
49607 #define A_MAC_PORT_MTIP_CR4_BIP_ERR_CNTLANE_12 0x1e50
49608 
49609 #define S_BIP_ERR_CNTLANE_12    0
49610 #define M_BIP_ERR_CNTLANE_12    0xffffU
49611 #define V_BIP_ERR_CNTLANE_12(x) ((x) << S_BIP_ERR_CNTLANE_12)
49612 #define G_BIP_ERR_CNTLANE_12(x) (((x) >> S_BIP_ERR_CNTLANE_12) & M_BIP_ERR_CNTLANE_12)
49613 
49614 #define A_MAC_PORT_MTIP_CR4_BIP_ERR_CNTLANE_13 0x1e54
49615 
49616 #define S_BIP_ERR_CNTLANE_13    0
49617 #define M_BIP_ERR_CNTLANE_13    0xffffU
49618 #define V_BIP_ERR_CNTLANE_13(x) ((x) << S_BIP_ERR_CNTLANE_13)
49619 #define G_BIP_ERR_CNTLANE_13(x) (((x) >> S_BIP_ERR_CNTLANE_13) & M_BIP_ERR_CNTLANE_13)
49620 
49621 #define A_MAC_PORT_MTIP_CR4_BIP_ERR_CNTLANE_14 0x1e58
49622 
49623 #define S_BIP_ERR_CNTLANE_14    0
49624 #define M_BIP_ERR_CNTLANE_14    0xffffU
49625 #define V_BIP_ERR_CNTLANE_14(x) ((x) << S_BIP_ERR_CNTLANE_14)
49626 #define G_BIP_ERR_CNTLANE_14(x) (((x) >> S_BIP_ERR_CNTLANE_14) & M_BIP_ERR_CNTLANE_14)
49627 
49628 #define A_MAC_PORT_MTIP_CR4_BIP_ERR_CNTLANE_15 0x1e5c
49629 
49630 #define S_BIP_ERR_CNTLANE_15    0
49631 #define M_BIP_ERR_CNTLANE_15    0xffffU
49632 #define V_BIP_ERR_CNTLANE_15(x) ((x) << S_BIP_ERR_CNTLANE_15)
49633 #define G_BIP_ERR_CNTLANE_15(x) (((x) >> S_BIP_ERR_CNTLANE_15) & M_BIP_ERR_CNTLANE_15)
49634 
49635 #define A_MAC_PORT_MTIP_CR4_BIP_ERR_CNTLANE_16 0x1e60
49636 
49637 #define S_BIP_ERR_CNTLANE_16    0
49638 #define M_BIP_ERR_CNTLANE_16    0xffffU
49639 #define V_BIP_ERR_CNTLANE_16(x) ((x) << S_BIP_ERR_CNTLANE_16)
49640 #define G_BIP_ERR_CNTLANE_16(x) (((x) >> S_BIP_ERR_CNTLANE_16) & M_BIP_ERR_CNTLANE_16)
49641 
49642 #define A_MAC_PORT_MTIP_CR4_BIP_ERR_CNTLANE_17 0x1e64
49643 
49644 #define S_BIP_ERR_CNTLANE_17    0
49645 #define M_BIP_ERR_CNTLANE_17    0xffffU
49646 #define V_BIP_ERR_CNTLANE_17(x) ((x) << S_BIP_ERR_CNTLANE_17)
49647 #define G_BIP_ERR_CNTLANE_17(x) (((x) >> S_BIP_ERR_CNTLANE_17) & M_BIP_ERR_CNTLANE_17)
49648 
49649 #define A_MAC_PORT_MTIP_CR4_BIP_ERR_CNTLANE_18 0x1e68
49650 
49651 #define S_BIP_ERR_CNTLANE_18    0
49652 #define M_BIP_ERR_CNTLANE_18    0xffffU
49653 #define V_BIP_ERR_CNTLANE_18(x) ((x) << S_BIP_ERR_CNTLANE_18)
49654 #define G_BIP_ERR_CNTLANE_18(x) (((x) >> S_BIP_ERR_CNTLANE_18) & M_BIP_ERR_CNTLANE_18)
49655 
49656 #define A_MAC_PORT_MTIP_CR4_BIP_ERR_CNTLANE_19 0x1e6c
49657 
49658 #define S_BIP_ERR_CNTLANE_19    0
49659 #define M_BIP_ERR_CNTLANE_19    0xffffU
49660 #define V_BIP_ERR_CNTLANE_19(x) ((x) << S_BIP_ERR_CNTLANE_19)
49661 #define G_BIP_ERR_CNTLANE_19(x) (((x) >> S_BIP_ERR_CNTLANE_19) & M_BIP_ERR_CNTLANE_19)
49662 
49663 #define A_MAC_PORT_MTIP_PCS_BASER_STATUS1 0x1e80
49664 
49665 #define S_RXLINKSTATUS    12
49666 #define V_RXLINKSTATUS(x) ((x) << S_RXLINKSTATUS)
49667 #define F_RXLINKSTATUS    V_RXLINKSTATUS(1U)
49668 
49669 #define S_RESEREVED    4
49670 #define M_RESEREVED    0xffU
49671 #define V_RESEREVED(x) ((x) << S_RESEREVED)
49672 #define G_RESEREVED(x) (((x) >> S_RESEREVED) & M_RESEREVED)
49673 
49674 #define S_10GPRBS9    3
49675 #define V_10GPRBS9(x) ((x) << S_10GPRBS9)
49676 #define F_10GPRBS9    V_10GPRBS9(1U)
49677 
49678 #define S_10GPRBS31    2
49679 #define V_10GPRBS31(x) ((x) << S_10GPRBS31)
49680 #define F_10GPRBS31    V_10GPRBS31(1U)
49681 
49682 #define S_HIBER    1
49683 #define V_HIBER(x) ((x) << S_HIBER)
49684 #define F_HIBER    V_HIBER(1U)
49685 
49686 #define S_BLOCKLOCK    0
49687 #define V_BLOCKLOCK(x) ((x) << S_BLOCKLOCK)
49688 #define F_BLOCKLOCK    V_BLOCKLOCK(1U)
49689 
49690 #define A_MAC_PORT_MTIP_PCS_BASER_STATUS2 0x1e84
49691 
49692 #define S_BLOCKLOCKLL    15
49693 #define V_BLOCKLOCKLL(x) ((x) << S_BLOCKLOCKLL)
49694 #define F_BLOCKLOCKLL    V_BLOCKLOCKLL(1U)
49695 
49696 #define S_HIBERLH    14
49697 #define V_HIBERLH(x) ((x) << S_HIBERLH)
49698 #define F_HIBERLH    V_HIBERLH(1U)
49699 
49700 #define S_HIBERCOUNT    8
49701 #define M_HIBERCOUNT    0x3fU
49702 #define V_HIBERCOUNT(x) ((x) << S_HIBERCOUNT)
49703 #define G_HIBERCOUNT(x) (((x) >> S_HIBERCOUNT) & M_HIBERCOUNT)
49704 
49705 #define S_ERRBLKCNT    0
49706 #define M_ERRBLKCNT    0xffU
49707 #define V_ERRBLKCNT(x) ((x) << S_ERRBLKCNT)
49708 #define G_ERRBLKCNT(x) (((x) >> S_ERRBLKCNT) & M_ERRBLKCNT)
49709 
49710 #define A_MAC_PORT_MTIP_10GBASER_SEED_A 0x1e88
49711 
49712 #define S_SEEDA    0
49713 #define M_SEEDA    0xffffU
49714 #define V_SEEDA(x) ((x) << S_SEEDA)
49715 #define G_SEEDA(x) (((x) >> S_SEEDA) & M_SEEDA)
49716 
49717 #define A_MAC_PORT_MTIP_10GBASER_SEED_A1 0x1e8c
49718 
49719 #define S_SEEDA1    0
49720 #define M_SEEDA1    0xffffU
49721 #define V_SEEDA1(x) ((x) << S_SEEDA1)
49722 #define G_SEEDA1(x) (((x) >> S_SEEDA1) & M_SEEDA1)
49723 
49724 #define A_MAC_PORT_MTIP_10GBASER_SEED_A2 0x1e90
49725 
49726 #define S_SEEDA2    0
49727 #define M_SEEDA2    0xffffU
49728 #define V_SEEDA2(x) ((x) << S_SEEDA2)
49729 #define G_SEEDA2(x) (((x) >> S_SEEDA2) & M_SEEDA2)
49730 
49731 #define A_MAC_PORT_MTIP_10GBASER_SEED_A3 0x1e94
49732 
49733 #define S_SEEDA3    0
49734 #define M_SEEDA3    0x3ffU
49735 #define V_SEEDA3(x) ((x) << S_SEEDA3)
49736 #define G_SEEDA3(x) (((x) >> S_SEEDA3) & M_SEEDA3)
49737 
49738 #define A_MAC_PORT_MTIP_10GBASER_SEED_B 0x1e98
49739 
49740 #define S_SEEDB    0
49741 #define M_SEEDB    0xffffU
49742 #define V_SEEDB(x) ((x) << S_SEEDB)
49743 #define G_SEEDB(x) (((x) >> S_SEEDB) & M_SEEDB)
49744 
49745 #define A_MAC_PORT_MTIP_10GBASER_SEED_B1 0x1e9c
49746 
49747 #define S_SEEDB1    0
49748 #define M_SEEDB1    0xffffU
49749 #define V_SEEDB1(x) ((x) << S_SEEDB1)
49750 #define G_SEEDB1(x) (((x) >> S_SEEDB1) & M_SEEDB1)
49751 
49752 #define A_MAC_PORT_MTIP_10GBASER_SEED_B2 0x1ea0
49753 
49754 #define S_SEEDB2    0
49755 #define M_SEEDB2    0xffffU
49756 #define V_SEEDB2(x) ((x) << S_SEEDB2)
49757 #define G_SEEDB2(x) (((x) >> S_SEEDB2) & M_SEEDB2)
49758 
49759 #define A_MAC_PORT_MTIP_10GBASER_SEED_B3 0x1ea4
49760 
49761 #define S_SEEDB3    0
49762 #define M_SEEDB3    0x3ffU
49763 #define V_SEEDB3(x) ((x) << S_SEEDB3)
49764 #define G_SEEDB3(x) (((x) >> S_SEEDB3) & M_SEEDB3)
49765 
49766 #define A_MAC_PORT_MTIP_BASER_TEST_CTRL 0x1ea8
49767 
49768 #define S_TXPRBS9    6
49769 #define V_TXPRBS9(x) ((x) << S_TXPRBS9)
49770 #define F_TXPRBS9    V_TXPRBS9(1U)
49771 
49772 #define S_RXPRBS31    5
49773 #define V_RXPRBS31(x) ((x) << S_RXPRBS31)
49774 #define F_RXPRBS31    V_RXPRBS31(1U)
49775 
49776 #define S_TXPRBS31    4
49777 #define V_TXPRBS31(x) ((x) << S_TXPRBS31)
49778 #define F_TXPRBS31    V_TXPRBS31(1U)
49779 
49780 #define S_TXTESTPATEN    3
49781 #define V_TXTESTPATEN(x) ((x) << S_TXTESTPATEN)
49782 #define F_TXTESTPATEN    V_TXTESTPATEN(1U)
49783 
49784 #define S_RXTESTPATEN    2
49785 #define V_RXTESTPATEN(x) ((x) << S_RXTESTPATEN)
49786 #define F_RXTESTPATEN    V_RXTESTPATEN(1U)
49787 
49788 #define S_TESTPATSEL    1
49789 #define V_TESTPATSEL(x) ((x) << S_TESTPATSEL)
49790 #define F_TESTPATSEL    V_TESTPATSEL(1U)
49791 
49792 #define S_DATAPATSEL    0
49793 #define V_DATAPATSEL(x) ((x) << S_DATAPATSEL)
49794 #define F_DATAPATSEL    V_DATAPATSEL(1U)
49795 
49796 #define A_MAC_PORT_MTIP_BASER_TEST_ERR_CNT 0x1eac
49797 
49798 #define S_TEST_ERR_CNT    0
49799 #define M_TEST_ERR_CNT    0xffffU
49800 #define V_TEST_ERR_CNT(x) ((x) << S_TEST_ERR_CNT)
49801 #define G_TEST_ERR_CNT(x) (((x) >> S_TEST_ERR_CNT) & M_TEST_ERR_CNT)
49802 
49803 #define A_MAC_PORT_MTIP_BER_HIGH_ORDER_CNT 0x1eb0
49804 
49805 #define S_BER_CNT_HI    0
49806 #define M_BER_CNT_HI    0xffffU
49807 #define V_BER_CNT_HI(x) ((x) << S_BER_CNT_HI)
49808 #define G_BER_CNT_HI(x) (((x) >> S_BER_CNT_HI) & M_BER_CNT_HI)
49809 
49810 #define A_MAC_PORT_MTIP_BLK_HIGH_ORDER_CNT 0x1eb4
49811 
49812 #define S_HICOUNTPRSNT    15
49813 #define V_HICOUNTPRSNT(x) ((x) << S_HICOUNTPRSNT)
49814 #define F_HICOUNTPRSNT    V_HICOUNTPRSNT(1U)
49815 
49816 #define S_BLOCK_CNT_HI    0
49817 #define M_BLOCK_CNT_HI    0x3fffU
49818 #define V_BLOCK_CNT_HI(x) ((x) << S_BLOCK_CNT_HI)
49819 #define G_BLOCK_CNT_HI(x) (((x) >> S_BLOCK_CNT_HI) & M_BLOCK_CNT_HI)
49820 
49821 #define A_MAC_PORT_MTIP_PCS_MULTI_LANE_ALIGN_STATUS1 0x1ec8
49822 
49823 #define S_ALIGNSTATUS    12
49824 #define V_ALIGNSTATUS(x) ((x) << S_ALIGNSTATUS)
49825 #define F_ALIGNSTATUS    V_ALIGNSTATUS(1U)
49826 
49827 #define S_LANE7    7
49828 #define V_LANE7(x) ((x) << S_LANE7)
49829 #define F_LANE7    V_LANE7(1U)
49830 
49831 #define S_LANE6    6
49832 #define V_LANE6(x) ((x) << S_LANE6)
49833 #define F_LANE6    V_LANE6(1U)
49834 
49835 #define S_LANE5    5
49836 #define V_LANE5(x) ((x) << S_LANE5)
49837 #define F_LANE5    V_LANE5(1U)
49838 
49839 #define S_LANE4    4
49840 #define V_LANE4(x) ((x) << S_LANE4)
49841 #define F_LANE4    V_LANE4(1U)
49842 
49843 #define S_LANE3    3
49844 #define V_LANE3(x) ((x) << S_LANE3)
49845 #define F_LANE3    V_LANE3(1U)
49846 
49847 #define S_LANE2    2
49848 #define V_LANE2(x) ((x) << S_LANE2)
49849 #define F_LANE2    V_LANE2(1U)
49850 
49851 #define S_LANE1    1
49852 #define V_LANE1(x) ((x) << S_LANE1)
49853 #define F_LANE1    V_LANE1(1U)
49854 
49855 #define S_LANE0    0
49856 #define V_LANE0(x) ((x) << S_LANE0)
49857 #define F_LANE0    V_LANE0(1U)
49858 
49859 #define A_MAC_PORT_MTIP_PCS_MULTI_LANE_ALIGN_STATUS2 0x1ecc
49860 
49861 #define S_LANE19    11
49862 #define V_LANE19(x) ((x) << S_LANE19)
49863 #define F_LANE19    V_LANE19(1U)
49864 
49865 #define S_LANE18    10
49866 #define V_LANE18(x) ((x) << S_LANE18)
49867 #define F_LANE18    V_LANE18(1U)
49868 
49869 #define S_LANE17    9
49870 #define V_LANE17(x) ((x) << S_LANE17)
49871 #define F_LANE17    V_LANE17(1U)
49872 
49873 #define S_LANE16    8
49874 #define V_LANE16(x) ((x) << S_LANE16)
49875 #define F_LANE16    V_LANE16(1U)
49876 
49877 #define S_LANE15    7
49878 #define V_LANE15(x) ((x) << S_LANE15)
49879 #define F_LANE15    V_LANE15(1U)
49880 
49881 #define S_LANE14    6
49882 #define V_LANE14(x) ((x) << S_LANE14)
49883 #define F_LANE14    V_LANE14(1U)
49884 
49885 #define S_LANE13    5
49886 #define V_LANE13(x) ((x) << S_LANE13)
49887 #define F_LANE13    V_LANE13(1U)
49888 
49889 #define S_LANE12    4
49890 #define V_LANE12(x) ((x) << S_LANE12)
49891 #define F_LANE12    V_LANE12(1U)
49892 
49893 #define S_LANE11    3
49894 #define V_LANE11(x) ((x) << S_LANE11)
49895 #define F_LANE11    V_LANE11(1U)
49896 
49897 #define S_LANE10    2
49898 #define V_LANE10(x) ((x) << S_LANE10)
49899 #define F_LANE10    V_LANE10(1U)
49900 
49901 #define S_LANE9    1
49902 #define V_LANE9(x) ((x) << S_LANE9)
49903 #define F_LANE9    V_LANE9(1U)
49904 
49905 #define S_LANE8    0
49906 #define V_LANE8(x) ((x) << S_LANE8)
49907 #define F_LANE8    V_LANE8(1U)
49908 
49909 #define A_MAC_PORT_MTIP_PCS_MULTI_LANE_ALIGN_STATUS3 0x1ed0
49910 
49911 #define S_AMLOCK7    7
49912 #define V_AMLOCK7(x) ((x) << S_AMLOCK7)
49913 #define F_AMLOCK7    V_AMLOCK7(1U)
49914 
49915 #define S_AMLOCK6    6
49916 #define V_AMLOCK6(x) ((x) << S_AMLOCK6)
49917 #define F_AMLOCK6    V_AMLOCK6(1U)
49918 
49919 #define S_AMLOCK5    5
49920 #define V_AMLOCK5(x) ((x) << S_AMLOCK5)
49921 #define F_AMLOCK5    V_AMLOCK5(1U)
49922 
49923 #define S_AMLOCK4    4
49924 #define V_AMLOCK4(x) ((x) << S_AMLOCK4)
49925 #define F_AMLOCK4    V_AMLOCK4(1U)
49926 
49927 #define S_AMLOCK3    3
49928 #define V_AMLOCK3(x) ((x) << S_AMLOCK3)
49929 #define F_AMLOCK3    V_AMLOCK3(1U)
49930 
49931 #define S_AMLOCK2    2
49932 #define V_AMLOCK2(x) ((x) << S_AMLOCK2)
49933 #define F_AMLOCK2    V_AMLOCK2(1U)
49934 
49935 #define S_AMLOCK1    1
49936 #define V_AMLOCK1(x) ((x) << S_AMLOCK1)
49937 #define F_AMLOCK1    V_AMLOCK1(1U)
49938 
49939 #define S_AMLOCK0    0
49940 #define V_AMLOCK0(x) ((x) << S_AMLOCK0)
49941 #define F_AMLOCK0    V_AMLOCK0(1U)
49942 
49943 #define A_MAC_PORT_MTIP_PCS_MULTI_LANE_ALIGN_STATUS4 0x1ed4
49944 
49945 #define S_AMLOCK19    11
49946 #define V_AMLOCK19(x) ((x) << S_AMLOCK19)
49947 #define F_AMLOCK19    V_AMLOCK19(1U)
49948 
49949 #define S_AMLOCK18    10
49950 #define V_AMLOCK18(x) ((x) << S_AMLOCK18)
49951 #define F_AMLOCK18    V_AMLOCK18(1U)
49952 
49953 #define S_AMLOCK17    9
49954 #define V_AMLOCK17(x) ((x) << S_AMLOCK17)
49955 #define F_AMLOCK17    V_AMLOCK17(1U)
49956 
49957 #define S_AMLOCK16    8
49958 #define V_AMLOCK16(x) ((x) << S_AMLOCK16)
49959 #define F_AMLOCK16    V_AMLOCK16(1U)
49960 
49961 #define S_AMLOCK15    7
49962 #define V_AMLOCK15(x) ((x) << S_AMLOCK15)
49963 #define F_AMLOCK15    V_AMLOCK15(1U)
49964 
49965 #define S_AMLOCK14    6
49966 #define V_AMLOCK14(x) ((x) << S_AMLOCK14)
49967 #define F_AMLOCK14    V_AMLOCK14(1U)
49968 
49969 #define S_AMLOCK13    5
49970 #define V_AMLOCK13(x) ((x) << S_AMLOCK13)
49971 #define F_AMLOCK13    V_AMLOCK13(1U)
49972 
49973 #define S_AMLOCK12    4
49974 #define V_AMLOCK12(x) ((x) << S_AMLOCK12)
49975 #define F_AMLOCK12    V_AMLOCK12(1U)
49976 
49977 #define S_AMLOCK11    3
49978 #define V_AMLOCK11(x) ((x) << S_AMLOCK11)
49979 #define F_AMLOCK11    V_AMLOCK11(1U)
49980 
49981 #define S_AMLOCK10    2
49982 #define V_AMLOCK10(x) ((x) << S_AMLOCK10)
49983 #define F_AMLOCK10    V_AMLOCK10(1U)
49984 
49985 #define S_AMLOCK9    1
49986 #define V_AMLOCK9(x) ((x) << S_AMLOCK9)
49987 #define F_AMLOCK9    V_AMLOCK9(1U)
49988 
49989 #define S_AMLOCK8    0
49990 #define V_AMLOCK8(x) ((x) << S_AMLOCK8)
49991 #define F_AMLOCK8    V_AMLOCK8(1U)
49992 
49993 #define A_MAC_PORT_MTIP_PCS_BIP_ERR_CNT_0 0x1f68
49994 
49995 #define S_BIPERR_CNT    0
49996 #define M_BIPERR_CNT    0xffffU
49997 #define V_BIPERR_CNT(x) ((x) << S_BIPERR_CNT)
49998 #define G_BIPERR_CNT(x) (((x) >> S_BIPERR_CNT) & M_BIPERR_CNT)
49999 
50000 #define A_MAC_PORT_MTIP_PCS_BIP_ERR_CNT_1 0x1f6c
50001 #define A_MAC_PORT_MTIP_PCS_BIP_ERR_CNT_2 0x1f70
50002 #define A_MAC_PORT_MTIP_PCS_BIP_ERR_CNT_3 0x1f74
50003 #define A_MAC_PORT_MTIP_PCS_BIP_ERR_CNT_4 0x1f78
50004 #define A_MAC_PORT_MTIP_PCS_BIP_ERR_CNT_5 0x1f7c
50005 #define A_MAC_PORT_MTIP_PCS_BIP_ERR_CNT_6 0x1f80
50006 #define A_MAC_PORT_MTIP_PCS_BIP_ERR_CNT_7 0x1f84
50007 #define A_MAC_PORT_MTIP_PCS_BIP_ERR_CNT_8 0x1f88
50008 #define A_MAC_PORT_MTIP_PCS_BIP_ERR_CNT_9 0x1f8c
50009 #define A_MAC_PORT_MTIP_PCS_BIP_ERR_CNT_10 0x1f90
50010 #define A_MAC_PORT_MTIP_PCS_BIP_ERR_CNT_11 0x1f94
50011 #define A_MAC_PORT_MTIP_PCS_BIP_ERR_CNT_12 0x1f98
50012 #define A_MAC_PORT_MTIP_PCS_BIP_ERR_CNT_13 0x1f9c
50013 #define A_MAC_PORT_MTIP_PCS_BIP_ERR_CNT_14 0x1fa0
50014 #define A_MAC_PORT_MTIP_PCS_BIP_ERR_CNT_15 0x1fa4
50015 #define A_MAC_PORT_MTIP_PCS_BIP_ERR_CNT_16 0x1fa8
50016 #define A_MAC_PORT_MTIP_PCS_BIP_ERR_CNT_17 0x1fac
50017 #define A_MAC_PORT_MTIP_PCS_BIP_ERR_CNT_18 0x1fb0
50018 #define A_MAC_PORT_MTIP_PCS_BIP_ERR_CNT_19 0x1fb4
50019 #define A_MAC_PORT_MTIP_PCS_LANE_MAP_0 0x1fb8
50020 
50021 #define S_MAP    0
50022 #define M_MAP    0x1fU
50023 #define V_MAP(x) ((x) << S_MAP)
50024 #define G_MAP(x) (((x) >> S_MAP) & M_MAP)
50025 
50026 #define A_MAC_PORT_MTIP_PCS_LANE_MAP_1 0x1fbc
50027 #define A_MAC_PORT_MTIP_PCS_LANE_MAP_2 0x1fc0
50028 #define A_MAC_PORT_MTIP_PCS_LANE_MAP_3 0x1fc4
50029 #define A_MAC_PORT_MTIP_PCS_LANE_MAP_4 0x1fc8
50030 #define A_MAC_PORT_MTIP_PCS_LANE_MAP_5 0x1fcc
50031 #define A_MAC_PORT_MTIP_PCS_LANE_MAP_6 0x1fd0
50032 #define A_MAC_PORT_MTIP_PCS_LANE_MAP_7 0x1fd4
50033 #define A_MAC_PORT_MTIP_PCS_LANE_MAP_8 0x1fd8
50034 #define A_MAC_PORT_MTIP_PCS_LANE_MAP_9 0x1fdc
50035 #define A_MAC_PORT_MTIP_PCS_LANE_MAP_10 0x1fe0
50036 #define A_MAC_PORT_MTIP_PCS_LANE_MAP_11 0x1fe4
50037 #define A_MAC_PORT_MTIP_PCS_LANE_MAP_12 0x1fe8
50038 #define A_MAC_PORT_MTIP_PCS_LANE_MAP_13 0x1fec
50039 #define A_MAC_PORT_MTIP_PCS_LANE_MAP_14 0x1ff0
50040 #define A_MAC_PORT_MTIP_PCS_LANE_MAP_15 0x1ff4
50041 #define A_MAC_PORT_MTIP_PCS_LANE_MAP_16 0x1ff8
50042 #define A_MAC_PORT_MTIP_PCS_LANE_MAP_17 0x1ffc
50043 #define A_MAC_PORT_MTIP_PCS_LANE_MAP_18 0x2000
50044 #define A_MAC_PORT_MTIP_PCS_LANE_MAP_19 0x2004
50045 #define A_MAC_PORT_MTIP_CR4_LANE_0_MAPPING 0x2140
50046 
50047 #define S_LANE_0_MAPPING    0
50048 #define M_LANE_0_MAPPING    0x3fU
50049 #define V_LANE_0_MAPPING(x) ((x) << S_LANE_0_MAPPING)
50050 #define G_LANE_0_MAPPING(x) (((x) >> S_LANE_0_MAPPING) & M_LANE_0_MAPPING)
50051 
50052 #define A_MAC_PORT_MTIP_CR4_LANE_1_MAPPING 0x2144
50053 
50054 #define S_LANE_1_MAPPING    0
50055 #define M_LANE_1_MAPPING    0x3fU
50056 #define V_LANE_1_MAPPING(x) ((x) << S_LANE_1_MAPPING)
50057 #define G_LANE_1_MAPPING(x) (((x) >> S_LANE_1_MAPPING) & M_LANE_1_MAPPING)
50058 
50059 #define A_MAC_PORT_MTIP_CR4_LANE_2_MAPPING 0x2148
50060 
50061 #define S_LANE_2_MAPPING    0
50062 #define M_LANE_2_MAPPING    0x3fU
50063 #define V_LANE_2_MAPPING(x) ((x) << S_LANE_2_MAPPING)
50064 #define G_LANE_2_MAPPING(x) (((x) >> S_LANE_2_MAPPING) & M_LANE_2_MAPPING)
50065 
50066 #define A_MAC_PORT_MTIP_CR4_LANE_3_MAPPING 0x214c
50067 
50068 #define S_LANE_3_MAPPING    0
50069 #define M_LANE_3_MAPPING    0x3fU
50070 #define V_LANE_3_MAPPING(x) ((x) << S_LANE_3_MAPPING)
50071 #define G_LANE_3_MAPPING(x) (((x) >> S_LANE_3_MAPPING) & M_LANE_3_MAPPING)
50072 
50073 #define A_MAC_PORT_MTIP_CR4_LANE_4_MAPPING 0x2150
50074 
50075 #define S_LANE_4_MAPPING    0
50076 #define M_LANE_4_MAPPING    0x3fU
50077 #define V_LANE_4_MAPPING(x) ((x) << S_LANE_4_MAPPING)
50078 #define G_LANE_4_MAPPING(x) (((x) >> S_LANE_4_MAPPING) & M_LANE_4_MAPPING)
50079 
50080 #define A_MAC_PORT_MTIP_CR4_LANE_5_MAPPING 0x2154
50081 
50082 #define S_LANE_5_MAPPING    0
50083 #define M_LANE_5_MAPPING    0x3fU
50084 #define V_LANE_5_MAPPING(x) ((x) << S_LANE_5_MAPPING)
50085 #define G_LANE_5_MAPPING(x) (((x) >> S_LANE_5_MAPPING) & M_LANE_5_MAPPING)
50086 
50087 #define A_MAC_PORT_MTIP_CR4_LANE_6_MAPPING 0x2158
50088 
50089 #define S_LANE_6_MAPPING    0
50090 #define M_LANE_6_MAPPING    0x3fU
50091 #define V_LANE_6_MAPPING(x) ((x) << S_LANE_6_MAPPING)
50092 #define G_LANE_6_MAPPING(x) (((x) >> S_LANE_6_MAPPING) & M_LANE_6_MAPPING)
50093 
50094 #define A_MAC_PORT_MTIP_CR4_LANE_7_MAPPING 0x215c
50095 
50096 #define S_LANE_7_MAPPING    0
50097 #define M_LANE_7_MAPPING    0x3fU
50098 #define V_LANE_7_MAPPING(x) ((x) << S_LANE_7_MAPPING)
50099 #define G_LANE_7_MAPPING(x) (((x) >> S_LANE_7_MAPPING) & M_LANE_7_MAPPING)
50100 
50101 #define A_MAC_PORT_MTIP_CR4_LANE_8_MAPPING 0x2160
50102 
50103 #define S_LANE_8_MAPPING    0
50104 #define M_LANE_8_MAPPING    0x3fU
50105 #define V_LANE_8_MAPPING(x) ((x) << S_LANE_8_MAPPING)
50106 #define G_LANE_8_MAPPING(x) (((x) >> S_LANE_8_MAPPING) & M_LANE_8_MAPPING)
50107 
50108 #define A_MAC_PORT_MTIP_CR4_LANE_9_MAPPING 0x2164
50109 
50110 #define S_LANE_9_MAPPING    0
50111 #define M_LANE_9_MAPPING    0x3fU
50112 #define V_LANE_9_MAPPING(x) ((x) << S_LANE_9_MAPPING)
50113 #define G_LANE_9_MAPPING(x) (((x) >> S_LANE_9_MAPPING) & M_LANE_9_MAPPING)
50114 
50115 #define A_MAC_PORT_MTIP_CR4_LANE_10_MAPPING 0x2168
50116 
50117 #define S_LANE_10_MAPPING    0
50118 #define M_LANE_10_MAPPING    0x3fU
50119 #define V_LANE_10_MAPPING(x) ((x) << S_LANE_10_MAPPING)
50120 #define G_LANE_10_MAPPING(x) (((x) >> S_LANE_10_MAPPING) & M_LANE_10_MAPPING)
50121 
50122 #define A_MAC_PORT_MTIP_CR4_LANE_11_MAPPING 0x216c
50123 
50124 #define S_LANE_11_MAPPING    0
50125 #define M_LANE_11_MAPPING    0x3fU
50126 #define V_LANE_11_MAPPING(x) ((x) << S_LANE_11_MAPPING)
50127 #define G_LANE_11_MAPPING(x) (((x) >> S_LANE_11_MAPPING) & M_LANE_11_MAPPING)
50128 
50129 #define A_MAC_PORT_MTIP_CR4_LANE_12_MAPPING 0x2170
50130 
50131 #define S_LANE_12_MAPPING    0
50132 #define M_LANE_12_MAPPING    0x3fU
50133 #define V_LANE_12_MAPPING(x) ((x) << S_LANE_12_MAPPING)
50134 #define G_LANE_12_MAPPING(x) (((x) >> S_LANE_12_MAPPING) & M_LANE_12_MAPPING)
50135 
50136 #define A_MAC_PORT_MTIP_CR4_LANE_13_MAPPING 0x2174
50137 
50138 #define S_LANE_13_MAPPING    0
50139 #define M_LANE_13_MAPPING    0x3fU
50140 #define V_LANE_13_MAPPING(x) ((x) << S_LANE_13_MAPPING)
50141 #define G_LANE_13_MAPPING(x) (((x) >> S_LANE_13_MAPPING) & M_LANE_13_MAPPING)
50142 
50143 #define A_MAC_PORT_MTIP_CR4_LANE_14_MAPPING 0x2178
50144 
50145 #define S_LANE_14_MAPPING    0
50146 #define M_LANE_14_MAPPING    0x3fU
50147 #define V_LANE_14_MAPPING(x) ((x) << S_LANE_14_MAPPING)
50148 #define G_LANE_14_MAPPING(x) (((x) >> S_LANE_14_MAPPING) & M_LANE_14_MAPPING)
50149 
50150 #define A_MAC_PORT_MTIP_CR4_LANE_15_MAPPING 0x217c
50151 
50152 #define S_LANE_15_MAPPING    0
50153 #define M_LANE_15_MAPPING    0x3fU
50154 #define V_LANE_15_MAPPING(x) ((x) << S_LANE_15_MAPPING)
50155 #define G_LANE_15_MAPPING(x) (((x) >> S_LANE_15_MAPPING) & M_LANE_15_MAPPING)
50156 
50157 #define A_MAC_PORT_MTIP_CR4_LANE_16_MAPPING 0x2180
50158 
50159 #define S_LANE_16_MAPPING    0
50160 #define M_LANE_16_MAPPING    0x3fU
50161 #define V_LANE_16_MAPPING(x) ((x) << S_LANE_16_MAPPING)
50162 #define G_LANE_16_MAPPING(x) (((x) >> S_LANE_16_MAPPING) & M_LANE_16_MAPPING)
50163 
50164 #define A_MAC_PORT_MTIP_CR4_LANE_17_MAPPING 0x2184
50165 
50166 #define S_LANE_17_MAPPING    0
50167 #define M_LANE_17_MAPPING    0x3fU
50168 #define V_LANE_17_MAPPING(x) ((x) << S_LANE_17_MAPPING)
50169 #define G_LANE_17_MAPPING(x) (((x) >> S_LANE_17_MAPPING) & M_LANE_17_MAPPING)
50170 
50171 #define A_MAC_PORT_MTIP_CR4_LANE_18_MAPPING 0x2188
50172 
50173 #define S_LANE_18_MAPPING    0
50174 #define M_LANE_18_MAPPING    0x3fU
50175 #define V_LANE_18_MAPPING(x) ((x) << S_LANE_18_MAPPING)
50176 #define G_LANE_18_MAPPING(x) (((x) >> S_LANE_18_MAPPING) & M_LANE_18_MAPPING)
50177 
50178 #define A_MAC_PORT_MTIP_CR4_LANE_19_MAPPING 0x218c
50179 
50180 #define S_LANE_19_MAPPING    0
50181 #define M_LANE_19_MAPPING    0x3fU
50182 #define V_LANE_19_MAPPING(x) ((x) << S_LANE_19_MAPPING)
50183 #define G_LANE_19_MAPPING(x) (((x) >> S_LANE_19_MAPPING) & M_LANE_19_MAPPING)
50184 
50185 #define A_MAC_PORT_MTIP_CR4_SCRATCH 0x21f0
50186 #define A_MAC_PORT_MTIP_CR4_CORE_REVISION 0x21f4
50187 
50188 #define S_CORE_REVISION    0
50189 #define M_CORE_REVISION    0xffffU
50190 #define V_CORE_REVISION(x) ((x) << S_CORE_REVISION)
50191 #define G_CORE_REVISION(x) (((x) >> S_CORE_REVISION) & M_CORE_REVISION)
50192 
50193 #define A_MAC_PORT_BEAN_CTL 0x2200
50194 
50195 #define S_AN_RESET    15
50196 #define V_AN_RESET(x) ((x) << S_AN_RESET)
50197 #define F_AN_RESET    V_AN_RESET(1U)
50198 
50199 #define S_EXT_NXP_CTRL    13
50200 #define V_EXT_NXP_CTRL(x) ((x) << S_EXT_NXP_CTRL)
50201 #define F_EXT_NXP_CTRL    V_EXT_NXP_CTRL(1U)
50202 
50203 #define S_BEAN_EN    12
50204 #define V_BEAN_EN(x) ((x) << S_BEAN_EN)
50205 #define F_BEAN_EN    V_BEAN_EN(1U)
50206 
50207 #define S_RESTART_BEAN    9
50208 #define V_RESTART_BEAN(x) ((x) << S_RESTART_BEAN)
50209 #define F_RESTART_BEAN    V_RESTART_BEAN(1U)
50210 
50211 #define A_MAC_PORT_MTIP_RS_FEC_CONTROL 0x2200
50212 
50213 #define S_RS_FEC_BYPASS_ERROR_INDICATION    1
50214 #define V_RS_FEC_BYPASS_ERROR_INDICATION(x) ((x) << S_RS_FEC_BYPASS_ERROR_INDICATION)
50215 #define F_RS_FEC_BYPASS_ERROR_INDICATION    V_RS_FEC_BYPASS_ERROR_INDICATION(1U)
50216 
50217 #define S_RS_FEC_BYPASS_CORRECTION    0
50218 #define V_RS_FEC_BYPASS_CORRECTION(x) ((x) << S_RS_FEC_BYPASS_CORRECTION)
50219 #define F_RS_FEC_BYPASS_CORRECTION    V_RS_FEC_BYPASS_CORRECTION(1U)
50220 
50221 #define A_MAC_PORT_BEAN_STATUS 0x2204
50222 
50223 #define S_PDF    9
50224 #define V_PDF(x) ((x) << S_PDF)
50225 #define F_PDF    V_PDF(1U)
50226 
50227 #define S_EXT_NXP_STATUS    7
50228 #define V_EXT_NXP_STATUS(x) ((x) << S_EXT_NXP_STATUS)
50229 #define F_EXT_NXP_STATUS    V_EXT_NXP_STATUS(1U)
50230 
50231 #define S_PAGE_RCVD    6
50232 #define V_PAGE_RCVD(x) ((x) << S_PAGE_RCVD)
50233 #define F_PAGE_RCVD    V_PAGE_RCVD(1U)
50234 
50235 #define S_BEAN_COMPLETE    5
50236 #define V_BEAN_COMPLETE(x) ((x) << S_BEAN_COMPLETE)
50237 #define F_BEAN_COMPLETE    V_BEAN_COMPLETE(1U)
50238 
50239 #define S_REM_FAULT_STATUS    4
50240 #define V_REM_FAULT_STATUS(x) ((x) << S_REM_FAULT_STATUS)
50241 #define F_REM_FAULT_STATUS    V_REM_FAULT_STATUS(1U)
50242 
50243 #define S_BEAN_ABILITY    3
50244 #define V_BEAN_ABILITY(x) ((x) << S_BEAN_ABILITY)
50245 #define F_BEAN_ABILITY    V_BEAN_ABILITY(1U)
50246 
50247 #define S_LP_BEAN_ABILITY    0
50248 #define V_LP_BEAN_ABILITY(x) ((x) << S_LP_BEAN_ABILITY)
50249 #define F_LP_BEAN_ABILITY    V_LP_BEAN_ABILITY(1U)
50250 
50251 #define A_MAC_PORT_MTIP_RS_FEC_STATUS 0x2204
50252 
50253 #define S_RS_FEC_PCS_ALIGN_STATUS    15
50254 #define V_RS_FEC_PCS_ALIGN_STATUS(x) ((x) << S_RS_FEC_PCS_ALIGN_STATUS)
50255 #define F_RS_FEC_PCS_ALIGN_STATUS    V_RS_FEC_PCS_ALIGN_STATUS(1U)
50256 
50257 #define S_FEC_ALIGN_STATUS    14
50258 #define V_FEC_ALIGN_STATUS(x) ((x) << S_FEC_ALIGN_STATUS)
50259 #define F_FEC_ALIGN_STATUS    V_FEC_ALIGN_STATUS(1U)
50260 
50261 #define S_RS_FEC_HIGH_SER    2
50262 #define V_RS_FEC_HIGH_SER(x) ((x) << S_RS_FEC_HIGH_SER)
50263 #define F_RS_FEC_HIGH_SER    V_RS_FEC_HIGH_SER(1U)
50264 
50265 #define S_RS_FEC_BYPASS_ERROR_INDICATION_ABILITY    1
50266 #define V_RS_FEC_BYPASS_ERROR_INDICATION_ABILITY(x) ((x) << S_RS_FEC_BYPASS_ERROR_INDICATION_ABILITY)
50267 #define F_RS_FEC_BYPASS_ERROR_INDICATION_ABILITY    V_RS_FEC_BYPASS_ERROR_INDICATION_ABILITY(1U)
50268 
50269 #define S_RS_FEC_BYPASS_CORRECTION_ABILITY    0
50270 #define V_RS_FEC_BYPASS_CORRECTION_ABILITY(x) ((x) << S_RS_FEC_BYPASS_CORRECTION_ABILITY)
50271 #define F_RS_FEC_BYPASS_CORRECTION_ABILITY    V_RS_FEC_BYPASS_CORRECTION_ABILITY(1U)
50272 
50273 #define A_MAC_PORT_BEAN_ABILITY_0 0x2208
50274 
50275 #define S_NXP    15
50276 #define V_NXP(x) ((x) << S_NXP)
50277 #define F_NXP    V_NXP(1U)
50278 
50279 #define S_REM_FAULT    13
50280 #define V_REM_FAULT(x) ((x) << S_REM_FAULT)
50281 #define F_REM_FAULT    V_REM_FAULT(1U)
50282 
50283 #define S_PAUSE_ABILITY    10
50284 #define M_PAUSE_ABILITY    0x7U
50285 #define V_PAUSE_ABILITY(x) ((x) << S_PAUSE_ABILITY)
50286 #define G_PAUSE_ABILITY(x) (((x) >> S_PAUSE_ABILITY) & M_PAUSE_ABILITY)
50287 
50288 #define S_ECHO_NONCE    5
50289 #define M_ECHO_NONCE    0x1fU
50290 #define V_ECHO_NONCE(x) ((x) << S_ECHO_NONCE)
50291 #define G_ECHO_NONCE(x) (((x) >> S_ECHO_NONCE) & M_ECHO_NONCE)
50292 
50293 #define S_SELECTOR    0
50294 #define M_SELECTOR    0x1fU
50295 #define V_SELECTOR(x) ((x) << S_SELECTOR)
50296 #define G_SELECTOR(x) (((x) >> S_SELECTOR) & M_SELECTOR)
50297 
50298 #define A_MAC_PORT_MTIP_RS_FEC_CCW_LO 0x2208
50299 
50300 #define S_RS_RS_FEC_CCW_LO    0
50301 #define M_RS_RS_FEC_CCW_LO    0xffffU
50302 #define V_RS_RS_FEC_CCW_LO(x) ((x) << S_RS_RS_FEC_CCW_LO)
50303 #define G_RS_RS_FEC_CCW_LO(x) (((x) >> S_RS_RS_FEC_CCW_LO) & M_RS_RS_FEC_CCW_LO)
50304 
50305 #define A_MAC_PORT_BEAN_ABILITY_1 0x220c
50306 
50307 #define S_TECH_ABILITY_1    5
50308 #define M_TECH_ABILITY_1    0x7ffU
50309 #define V_TECH_ABILITY_1(x) ((x) << S_TECH_ABILITY_1)
50310 #define G_TECH_ABILITY_1(x) (((x) >> S_TECH_ABILITY_1) & M_TECH_ABILITY_1)
50311 
50312 #define S_TX_NONCE    0
50313 #define M_TX_NONCE    0x1fU
50314 #define V_TX_NONCE(x) ((x) << S_TX_NONCE)
50315 #define G_TX_NONCE(x) (((x) >> S_TX_NONCE) & M_TX_NONCE)
50316 
50317 #define A_MAC_PORT_MTIP_RS_FEC_CCW_HI 0x220c
50318 
50319 #define S_RS_RS_FEC_CCW_HI    0
50320 #define M_RS_RS_FEC_CCW_HI    0xffffU
50321 #define V_RS_RS_FEC_CCW_HI(x) ((x) << S_RS_RS_FEC_CCW_HI)
50322 #define G_RS_RS_FEC_CCW_HI(x) (((x) >> S_RS_RS_FEC_CCW_HI) & M_RS_RS_FEC_CCW_HI)
50323 
50324 #define A_MAC_PORT_BEAN_ABILITY_2 0x2210
50325 
50326 #define S_T5_FEC_ABILITY    14
50327 #define M_T5_FEC_ABILITY    0x3U
50328 #define V_T5_FEC_ABILITY(x) ((x) << S_T5_FEC_ABILITY)
50329 #define G_T5_FEC_ABILITY(x) (((x) >> S_T5_FEC_ABILITY) & M_T5_FEC_ABILITY)
50330 
50331 #define S_TECH_ABILITY_2    0
50332 #define M_TECH_ABILITY_2    0x3fffU
50333 #define V_TECH_ABILITY_2(x) ((x) << S_TECH_ABILITY_2)
50334 #define G_TECH_ABILITY_2(x) (((x) >> S_TECH_ABILITY_2) & M_TECH_ABILITY_2)
50335 
50336 #define A_MAC_PORT_MTIP_RS_FEC_NCCW_LO 0x2210
50337 
50338 #define S_RS_RS_FEC_NCCW_LO    0
50339 #define M_RS_RS_FEC_NCCW_LO    0xffffU
50340 #define V_RS_RS_FEC_NCCW_LO(x) ((x) << S_RS_RS_FEC_NCCW_LO)
50341 #define G_RS_RS_FEC_NCCW_LO(x) (((x) >> S_RS_RS_FEC_NCCW_LO) & M_RS_RS_FEC_NCCW_LO)
50342 
50343 #define A_MAC_PORT_BEAN_REM_ABILITY_0 0x2214
50344 #define A_MAC_PORT_MTIP_RS_FEC_NCCW_HI 0x2214
50345 
50346 #define S_RS_RS_FEC_NCCW_HI    0
50347 #define M_RS_RS_FEC_NCCW_HI    0xffffU
50348 #define V_RS_RS_FEC_NCCW_HI(x) ((x) << S_RS_RS_FEC_NCCW_HI)
50349 #define G_RS_RS_FEC_NCCW_HI(x) (((x) >> S_RS_RS_FEC_NCCW_HI) & M_RS_RS_FEC_NCCW_HI)
50350 
50351 #define A_MAC_PORT_BEAN_REM_ABILITY_1 0x2218
50352 #define A_MAC_PORT_MTIP_RS_FEC_LANEMAPRS_FEC_NCCW_HI 0x2218
50353 
50354 #define S_PMA_MAPPING    0
50355 #define M_PMA_MAPPING    0xffU
50356 #define V_PMA_MAPPING(x) ((x) << S_PMA_MAPPING)
50357 #define G_PMA_MAPPING(x) (((x) >> S_PMA_MAPPING) & M_PMA_MAPPING)
50358 
50359 #define A_MAC_PORT_BEAN_REM_ABILITY_2 0x221c
50360 #define A_MAC_PORT_BEAN_MS_COUNT 0x2220
50361 
50362 #define S_MS_COUNT    0
50363 #define M_MS_COUNT    0xffffU
50364 #define V_MS_COUNT(x) ((x) << S_MS_COUNT)
50365 #define G_MS_COUNT(x) (((x) >> S_MS_COUNT) & M_MS_COUNT)
50366 
50367 #define A_MAC_PORT_BEAN_XNP_0 0x2224
50368 
50369 #define S_XNP    15
50370 #define V_XNP(x) ((x) << S_XNP)
50371 #define F_XNP    V_XNP(1U)
50372 
50373 #define S_ACKNOWLEDGE    14
50374 #define V_ACKNOWLEDGE(x) ((x) << S_ACKNOWLEDGE)
50375 #define F_ACKNOWLEDGE    V_ACKNOWLEDGE(1U)
50376 
50377 #define S_MP    13
50378 #define V_MP(x) ((x) << S_MP)
50379 #define F_MP    V_MP(1U)
50380 
50381 #define S_ACK2    12
50382 #define V_ACK2(x) ((x) << S_ACK2)
50383 #define F_ACK2    V_ACK2(1U)
50384 
50385 #define S_MU    0
50386 #define M_MU    0x7ffU
50387 #define V_MU(x) ((x) << S_MU)
50388 #define G_MU(x) (((x) >> S_MU) & M_MU)
50389 
50390 #define A_MAC_PORT_BEAN_XNP_1 0x2228
50391 
50392 #define S_UNFORMATED    0
50393 #define M_UNFORMATED    0xffffU
50394 #define V_UNFORMATED(x) ((x) << S_UNFORMATED)
50395 #define G_UNFORMATED(x) (((x) >> S_UNFORMATED) & M_UNFORMATED)
50396 
50397 #define A_MAC_PORT_MTIP_RS_FEC_SYMBLERR0_LO 0x2228
50398 
50399 #define S_RS_FEC_SYMBLERR0_LO    0
50400 #define V_RS_FEC_SYMBLERR0_LO(x) ((x) << S_RS_FEC_SYMBLERR0_LO)
50401 #define F_RS_FEC_SYMBLERR0_LO    V_RS_FEC_SYMBLERR0_LO(1U)
50402 
50403 #define A_MAC_PORT_BEAN_XNP_2 0x222c
50404 #define A_MAC_PORT_MTIP_RS_FEC_SYMBLERR0_HI 0x222c
50405 
50406 #define S_RS_FEC_SYMBLERR0_HI    0
50407 #define V_RS_FEC_SYMBLERR0_HI(x) ((x) << S_RS_FEC_SYMBLERR0_HI)
50408 #define F_RS_FEC_SYMBLERR0_HI    V_RS_FEC_SYMBLERR0_HI(1U)
50409 
50410 #define A_MAC_PORT_LP_BEAN_XNP_0 0x2230
50411 #define A_MAC_PORT_MTIP_RS_FEC_SYMBLERR1_LO 0x2230
50412 
50413 #define S_RS_FEC_SYMBLERR1_LO    0
50414 #define V_RS_FEC_SYMBLERR1_LO(x) ((x) << S_RS_FEC_SYMBLERR1_LO)
50415 #define F_RS_FEC_SYMBLERR1_LO    V_RS_FEC_SYMBLERR1_LO(1U)
50416 
50417 #define A_MAC_PORT_LP_BEAN_XNP_1 0x2234
50418 #define A_MAC_PORT_MTIP_RS_FEC_SYMBLERR1_HI 0x2234
50419 
50420 #define S_RS_FEC_SYMBLERR1_HI    0
50421 #define V_RS_FEC_SYMBLERR1_HI(x) ((x) << S_RS_FEC_SYMBLERR1_HI)
50422 #define F_RS_FEC_SYMBLERR1_HI    V_RS_FEC_SYMBLERR1_HI(1U)
50423 
50424 #define A_MAC_PORT_LP_BEAN_XNP_2 0x2238
50425 #define A_MAC_PORT_MTIP_RS_FEC_SYMBLERR2_LO 0x2238
50426 
50427 #define S_RS_FEC_SYMBLERR2_LO    0
50428 #define V_RS_FEC_SYMBLERR2_LO(x) ((x) << S_RS_FEC_SYMBLERR2_LO)
50429 #define F_RS_FEC_SYMBLERR2_LO    V_RS_FEC_SYMBLERR2_LO(1U)
50430 
50431 #define A_MAC_PORT_BEAN_ETH_STATUS 0x223c
50432 
50433 #define S_100GCR10    8
50434 #define V_100GCR10(x) ((x) << S_100GCR10)
50435 #define F_100GCR10    V_100GCR10(1U)
50436 
50437 #define S_40GCR4    6
50438 #define V_40GCR4(x) ((x) << S_40GCR4)
50439 #define F_40GCR4    V_40GCR4(1U)
50440 
50441 #define S_40GKR4    5
50442 #define V_40GKR4(x) ((x) << S_40GKR4)
50443 #define F_40GKR4    V_40GKR4(1U)
50444 
50445 #define S_FEC    4
50446 #define V_FEC(x) ((x) << S_FEC)
50447 #define F_FEC    V_FEC(1U)
50448 
50449 #define S_10GKR    3
50450 #define V_10GKR(x) ((x) << S_10GKR)
50451 #define F_10GKR    V_10GKR(1U)
50452 
50453 #define S_10GKX4    2
50454 #define V_10GKX4(x) ((x) << S_10GKX4)
50455 #define F_10GKX4    V_10GKX4(1U)
50456 
50457 #define S_1GKX    1
50458 #define V_1GKX(x) ((x) << S_1GKX)
50459 #define F_1GKX    V_1GKX(1U)
50460 
50461 #define A_MAC_PORT_MTIP_RS_FEC_SYMBLERR2_HI 0x223c
50462 
50463 #define S_RS_FEC_SYMBLERR2_HI    0
50464 #define V_RS_FEC_SYMBLERR2_HI(x) ((x) << S_RS_FEC_SYMBLERR2_HI)
50465 #define F_RS_FEC_SYMBLERR2_HI    V_RS_FEC_SYMBLERR2_HI(1U)
50466 
50467 #define A_MAC_PORT_BEAN_CTL_LANE1 0x2240
50468 #define A_MAC_PORT_MTIP_RS_FEC_SYMBLERR3_LO 0x2240
50469 
50470 #define S_RS_FEC_SYMBLERR3_LO    0
50471 #define V_RS_FEC_SYMBLERR3_LO(x) ((x) << S_RS_FEC_SYMBLERR3_LO)
50472 #define F_RS_FEC_SYMBLERR3_LO    V_RS_FEC_SYMBLERR3_LO(1U)
50473 
50474 #define A_MAC_PORT_BEAN_STATUS_LANE1 0x2244
50475 #define A_MAC_PORT_MTIP_RS_FEC_SYMBLERR3_HI 0x2244
50476 
50477 #define S_RS_FEC_SYMBLERR3_HI    0
50478 #define V_RS_FEC_SYMBLERR3_HI(x) ((x) << S_RS_FEC_SYMBLERR3_HI)
50479 #define F_RS_FEC_SYMBLERR3_HI    V_RS_FEC_SYMBLERR3_HI(1U)
50480 
50481 #define A_MAC_PORT_BEAN_ABILITY_0_LANE1 0x2248
50482 #define A_MAC_PORT_BEAN_ABILITY_1_LANE1 0x224c
50483 #define A_MAC_PORT_BEAN_ABILITY_2_LANE1 0x2250
50484 #define A_MAC_PORT_BEAN_REM_ABILITY_0_LANE1 0x2254
50485 #define A_MAC_PORT_BEAN_REM_ABILITY_1_LANE1 0x2258
50486 #define A_MAC_PORT_BEAN_REM_ABILITY_2_LANE1 0x225c
50487 #define A_MAC_PORT_BEAN_MS_COUNT_LANE1 0x2260
50488 #define A_MAC_PORT_BEAN_XNP_0_LANE1 0x2264
50489 #define A_MAC_PORT_BEAN_XNP_1_LANE1 0x2268
50490 #define A_MAC_PORT_BEAN_XNP_2_LANE1 0x226c
50491 #define A_MAC_PORT_LP_BEAN_XNP_0_LANE1 0x2270
50492 #define A_MAC_PORT_LP_BEAN_XNP_1_LANE1 0x2274
50493 #define A_MAC_PORT_LP_BEAN_XNP_2_LANE1 0x2278
50494 #define A_MAC_PORT_BEAN_ETH_STATUS_LANE1 0x227c
50495 #define A_MAC_PORT_BEAN_CTL_LANE2 0x2280
50496 #define A_MAC_PORT_BEAN_STATUS_LANE2 0x2284
50497 #define A_MAC_PORT_BEAN_ABILITY_0_LANE2 0x2288
50498 #define A_MAC_PORT_BEAN_ABILITY_1_LANE2 0x228c
50499 #define A_MAC_PORT_BEAN_ABILITY_2_LANE2 0x2290
50500 #define A_MAC_PORT_BEAN_REM_ABILITY_0_LANE2 0x2294
50501 #define A_MAC_PORT_BEAN_REM_ABILITY_1_LANE2 0x2298
50502 #define A_MAC_PORT_BEAN_REM_ABILITY_2_LANE2 0x229c
50503 #define A_MAC_PORT_BEAN_MS_COUNT_LANE2 0x22a0
50504 #define A_MAC_PORT_BEAN_XNP_0_LANE2 0x22a4
50505 #define A_MAC_PORT_BEAN_XNP_1_LANE2 0x22a8
50506 #define A_MAC_PORT_BEAN_XNP_2_LANE2 0x22ac
50507 #define A_MAC_PORT_LP_BEAN_XNP_0_LANE2 0x22b0
50508 #define A_MAC_PORT_LP_BEAN_XNP_1_LANE2 0x22b4
50509 #define A_MAC_PORT_LP_BEAN_XNP_2_LANE2 0x22b8
50510 #define A_MAC_PORT_BEAN_ETH_STATUS_LANE2 0x22bc
50511 #define A_MAC_PORT_BEAN_CTL_LANE3 0x22c0
50512 #define A_MAC_PORT_BEAN_STATUS_LANE3 0x22c4
50513 #define A_MAC_PORT_BEAN_ABILITY_0_LANE3 0x22c8
50514 #define A_MAC_PORT_BEAN_ABILITY_1_LANE3 0x22cc
50515 #define A_MAC_PORT_BEAN_ABILITY_2_LANE3 0x22d0
50516 #define A_MAC_PORT_BEAN_REM_ABILITY_0_LANE3 0x22d4
50517 #define A_MAC_PORT_BEAN_REM_ABILITY_1_LANE3 0x22d8
50518 #define A_MAC_PORT_BEAN_REM_ABILITY_2_LANE3 0x22dc
50519 #define A_MAC_PORT_BEAN_MS_COUNT_LANE3 0x22e0
50520 #define A_MAC_PORT_BEAN_XNP_0_LANE3 0x22e4
50521 #define A_MAC_PORT_BEAN_XNP_1_LANE3 0x22e8
50522 #define A_MAC_PORT_BEAN_XNP_2_LANE3 0x22ec
50523 #define A_MAC_PORT_LP_BEAN_XNP_0_LANE3 0x22f0
50524 #define A_MAC_PORT_LP_BEAN_XNP_1_LANE3 0x22f4
50525 #define A_MAC_PORT_LP_BEAN_XNP_2_LANE3 0x22f8
50526 #define A_MAC_PORT_BEAN_ETH_STATUS_LANE3 0x22fc
50527 #define A_MAC_PORT_MTIP_RS_FEC_VENDOR_CONTROL 0x2400
50528 
50529 #define S_RS_FEC_ENABLED_STATUS    15
50530 #define V_RS_FEC_ENABLED_STATUS(x) ((x) << S_RS_FEC_ENABLED_STATUS)
50531 #define F_RS_FEC_ENABLED_STATUS    V_RS_FEC_ENABLED_STATUS(1U)
50532 
50533 #define S_RS_FEC_ENABLE    2
50534 #define V_RS_FEC_ENABLE(x) ((x) << S_RS_FEC_ENABLE)
50535 #define F_RS_FEC_ENABLE    V_RS_FEC_ENABLE(1U)
50536 
50537 #define A_MAC_PORT_MTIP_RS_FEC_VENDOR_INFO_1 0x2404
50538 
50539 #define S_DESKEW_EMPTY    12
50540 #define M_DESKEW_EMPTY    0xfU
50541 #define V_DESKEW_EMPTY(x) ((x) << S_DESKEW_EMPTY)
50542 #define G_DESKEW_EMPTY(x) (((x) >> S_DESKEW_EMPTY) & M_DESKEW_EMPTY)
50543 
50544 #define S_FEC_ALIGN_STATUS_LH    10
50545 #define V_FEC_ALIGN_STATUS_LH(x) ((x) << S_FEC_ALIGN_STATUS_LH)
50546 #define F_FEC_ALIGN_STATUS_LH    V_FEC_ALIGN_STATUS_LH(1U)
50547 
50548 #define S_TX_DP_OVERFLOW    9
50549 #define V_TX_DP_OVERFLOW(x) ((x) << S_TX_DP_OVERFLOW)
50550 #define F_TX_DP_OVERFLOW    V_TX_DP_OVERFLOW(1U)
50551 
50552 #define S_RX_DP_OVERFLOW    8
50553 #define V_RX_DP_OVERFLOW(x) ((x) << S_RX_DP_OVERFLOW)
50554 #define F_RX_DP_OVERFLOW    V_RX_DP_OVERFLOW(1U)
50555 
50556 #define S_TX_DATAPATH_RESTART    7
50557 #define V_TX_DATAPATH_RESTART(x) ((x) << S_TX_DATAPATH_RESTART)
50558 #define F_TX_DATAPATH_RESTART    V_TX_DATAPATH_RESTART(1U)
50559 
50560 #define S_RX_DATAPATH_RESTART    6
50561 #define V_RX_DATAPATH_RESTART(x) ((x) << S_RX_DATAPATH_RESTART)
50562 #define F_RX_DATAPATH_RESTART    V_RX_DATAPATH_RESTART(1U)
50563 
50564 #define S_MARKER_CHECK_RESTART    5
50565 #define V_MARKER_CHECK_RESTART(x) ((x) << S_MARKER_CHECK_RESTART)
50566 #define F_MARKER_CHECK_RESTART    V_MARKER_CHECK_RESTART(1U)
50567 
50568 #define S_FEC_ALIGN_STATUS_LL    4
50569 #define V_FEC_ALIGN_STATUS_LL(x) ((x) << S_FEC_ALIGN_STATUS_LL)
50570 #define F_FEC_ALIGN_STATUS_LL    V_FEC_ALIGN_STATUS_LL(1U)
50571 
50572 #define S_AMPS_LOCK    0
50573 #define M_AMPS_LOCK    0xfU
50574 #define V_AMPS_LOCK(x) ((x) << S_AMPS_LOCK)
50575 #define G_AMPS_LOCK(x) (((x) >> S_AMPS_LOCK) & M_AMPS_LOCK)
50576 
50577 #define A_MAC_PORT_MTIP_RS_FEC_VENDOR_INFO_2 0x2408
50578 #define A_MAC_PORT_MTIP_RS_FEC_VENDOR_REVISION 0x240c
50579 
50580 #define S_RS_FEC_VENDOR_REVISION    0
50581 #define M_RS_FEC_VENDOR_REVISION    0xffffU
50582 #define V_RS_FEC_VENDOR_REVISION(x) ((x) << S_RS_FEC_VENDOR_REVISION)
50583 #define G_RS_FEC_VENDOR_REVISION(x) (((x) >> S_RS_FEC_VENDOR_REVISION) & M_RS_FEC_VENDOR_REVISION)
50584 
50585 #define A_MAC_PORT_MTIP_RS_FEC_VENDOR_TX_TEST_KEY 0x2410
50586 
50587 #define S_RS_FEC_VENDOR_TX_TEST_KEY    0
50588 #define M_RS_FEC_VENDOR_TX_TEST_KEY    0xffffU
50589 #define V_RS_FEC_VENDOR_TX_TEST_KEY(x) ((x) << S_RS_FEC_VENDOR_TX_TEST_KEY)
50590 #define G_RS_FEC_VENDOR_TX_TEST_KEY(x) (((x) >> S_RS_FEC_VENDOR_TX_TEST_KEY) & M_RS_FEC_VENDOR_TX_TEST_KEY)
50591 
50592 #define A_MAC_PORT_MTIP_RS_FEC_VENDOR_TX_TEST_SYMBOLS 0x2414
50593 
50594 #define S_RS_FEC_VENDOR_TX_TEST_SYMBOLS    0
50595 #define M_RS_FEC_VENDOR_TX_TEST_SYMBOLS    0xffffU
50596 #define V_RS_FEC_VENDOR_TX_TEST_SYMBOLS(x) ((x) << S_RS_FEC_VENDOR_TX_TEST_SYMBOLS)
50597 #define G_RS_FEC_VENDOR_TX_TEST_SYMBOLS(x) (((x) >> S_RS_FEC_VENDOR_TX_TEST_SYMBOLS) & M_RS_FEC_VENDOR_TX_TEST_SYMBOLS)
50598 
50599 #define A_MAC_PORT_MTIP_RS_FEC_VENDOR_TX_TEST_PATTERN 0x2418
50600 
50601 #define S_RS_FEC_VENDOR_TX_TEST_PATTERN    0
50602 #define M_RS_FEC_VENDOR_TX_TEST_PATTERN    0xffffU
50603 #define V_RS_FEC_VENDOR_TX_TEST_PATTERN(x) ((x) << S_RS_FEC_VENDOR_TX_TEST_PATTERN)
50604 #define G_RS_FEC_VENDOR_TX_TEST_PATTERN(x) (((x) >> S_RS_FEC_VENDOR_TX_TEST_PATTERN) & M_RS_FEC_VENDOR_TX_TEST_PATTERN)
50605 
50606 #define A_MAC_PORT_MTIP_RS_FEC_VENDOR_TX_TEST_TRIGGER 0x241c
50607 
50608 #define S_RS_FEC_VENDOR_TX_TEST_TRIGGER    0
50609 #define M_RS_FEC_VENDOR_TX_TEST_TRIGGER    0xffffU
50610 #define V_RS_FEC_VENDOR_TX_TEST_TRIGGER(x) ((x) << S_RS_FEC_VENDOR_TX_TEST_TRIGGER)
50611 #define G_RS_FEC_VENDOR_TX_TEST_TRIGGER(x) (((x) >> S_RS_FEC_VENDOR_TX_TEST_TRIGGER) & M_RS_FEC_VENDOR_TX_TEST_TRIGGER)
50612 
50613 #define A_MAC_PORT_FEC_KR_CONTROL 0x2600
50614 
50615 #define S_ENABLE_TR    1
50616 #define V_ENABLE_TR(x) ((x) << S_ENABLE_TR)
50617 #define F_ENABLE_TR    V_ENABLE_TR(1U)
50618 
50619 #define S_RESTART_TR    0
50620 #define V_RESTART_TR(x) ((x) << S_RESTART_TR)
50621 #define F_RESTART_TR    V_RESTART_TR(1U)
50622 
50623 #define A_MAC_PORT_FEC_KR_STATUS 0x2604
50624 
50625 #define S_FECKRSIGDET    15
50626 #define V_FECKRSIGDET(x) ((x) << S_FECKRSIGDET)
50627 #define F_FECKRSIGDET    V_FECKRSIGDET(1U)
50628 
50629 #define S_TRAIN_FAIL    3
50630 #define V_TRAIN_FAIL(x) ((x) << S_TRAIN_FAIL)
50631 #define F_TRAIN_FAIL    V_TRAIN_FAIL(1U)
50632 
50633 #define S_STARTUP_STATUS    2
50634 #define V_STARTUP_STATUS(x) ((x) << S_STARTUP_STATUS)
50635 #define F_STARTUP_STATUS    V_STARTUP_STATUS(1U)
50636 
50637 #define S_RX_STATUS    0
50638 #define V_RX_STATUS(x) ((x) << S_RX_STATUS)
50639 #define F_RX_STATUS    V_RX_STATUS(1U)
50640 
50641 #define A_MAC_PORT_FEC_KR_LP_COEFF 0x2608
50642 
50643 #define S_PRESET    13
50644 #define V_PRESET(x) ((x) << S_PRESET)
50645 #define F_PRESET    V_PRESET(1U)
50646 
50647 #define S_INITIALIZE    12
50648 #define V_INITIALIZE(x) ((x) << S_INITIALIZE)
50649 #define F_INITIALIZE    V_INITIALIZE(1U)
50650 
50651 #define S_CP1_UPD    4
50652 #define M_CP1_UPD    0x3U
50653 #define V_CP1_UPD(x) ((x) << S_CP1_UPD)
50654 #define G_CP1_UPD(x) (((x) >> S_CP1_UPD) & M_CP1_UPD)
50655 
50656 #define S_C0_UPD    2
50657 #define M_C0_UPD    0x3U
50658 #define V_C0_UPD(x) ((x) << S_C0_UPD)
50659 #define G_C0_UPD(x) (((x) >> S_C0_UPD) & M_C0_UPD)
50660 
50661 #define S_CN1_UPD    0
50662 #define M_CN1_UPD    0x3U
50663 #define V_CN1_UPD(x) ((x) << S_CN1_UPD)
50664 #define G_CN1_UPD(x) (((x) >> S_CN1_UPD) & M_CN1_UPD)
50665 
50666 #define A_MAC_PORT_FEC_KR_LP_STAT 0x260c
50667 
50668 #define S_RX_READY    15
50669 #define V_RX_READY(x) ((x) << S_RX_READY)
50670 #define F_RX_READY    V_RX_READY(1U)
50671 
50672 #define S_CP1_STAT    4
50673 #define M_CP1_STAT    0x3U
50674 #define V_CP1_STAT(x) ((x) << S_CP1_STAT)
50675 #define G_CP1_STAT(x) (((x) >> S_CP1_STAT) & M_CP1_STAT)
50676 
50677 #define S_C0_STAT    2
50678 #define M_C0_STAT    0x3U
50679 #define V_C0_STAT(x) ((x) << S_C0_STAT)
50680 #define G_C0_STAT(x) (((x) >> S_C0_STAT) & M_C0_STAT)
50681 
50682 #define S_CN1_STAT    0
50683 #define M_CN1_STAT    0x3U
50684 #define V_CN1_STAT(x) ((x) << S_CN1_STAT)
50685 #define G_CN1_STAT(x) (((x) >> S_CN1_STAT) & M_CN1_STAT)
50686 
50687 #define A_MAC_PORT_FEC_KR_LD_COEFF 0x2610
50688 #define A_MAC_PORT_FEC_KR_LD_STAT 0x2614
50689 #define A_MAC_PORT_FEC_ABILITY 0x2618
50690 
50691 #define S_FEC_IND_ABILITY    1
50692 #define V_FEC_IND_ABILITY(x) ((x) << S_FEC_IND_ABILITY)
50693 #define F_FEC_IND_ABILITY    V_FEC_IND_ABILITY(1U)
50694 
50695 #define S_ABILITY    0
50696 #define V_ABILITY(x) ((x) << S_ABILITY)
50697 #define F_ABILITY    V_ABILITY(1U)
50698 
50699 #define A_MAC_PORT_MTIP_FEC_ABILITY 0x2618
50700 
50701 #define S_BASE_R_FEC_ERROR_INDICATION_ABILITY    1
50702 #define V_BASE_R_FEC_ERROR_INDICATION_ABILITY(x) ((x) << S_BASE_R_FEC_ERROR_INDICATION_ABILITY)
50703 #define F_BASE_R_FEC_ERROR_INDICATION_ABILITY    V_BASE_R_FEC_ERROR_INDICATION_ABILITY(1U)
50704 
50705 #define S_BASE_R_FEC_ABILITY    0
50706 #define V_BASE_R_FEC_ABILITY(x) ((x) << S_BASE_R_FEC_ABILITY)
50707 #define F_BASE_R_FEC_ABILITY    V_BASE_R_FEC_ABILITY(1U)
50708 
50709 #define A_MAC_PORT_FEC_CONTROL 0x261c
50710 
50711 #define S_FEC_EN_ERR_IND    1
50712 #define V_FEC_EN_ERR_IND(x) ((x) << S_FEC_EN_ERR_IND)
50713 #define F_FEC_EN_ERR_IND    V_FEC_EN_ERR_IND(1U)
50714 
50715 #define S_FEC_EN    0
50716 #define V_FEC_EN(x) ((x) << S_FEC_EN)
50717 #define F_FEC_EN    V_FEC_EN(1U)
50718 
50719 #define A_MAC_PORT_FEC_STATUS 0x2620
50720 
50721 #define S_FEC_LOCKED_100    1
50722 #define V_FEC_LOCKED_100(x) ((x) << S_FEC_LOCKED_100)
50723 #define F_FEC_LOCKED_100    V_FEC_LOCKED_100(1U)
50724 
50725 #define S_FEC_LOCKED    0
50726 #define V_FEC_LOCKED(x) ((x) << S_FEC_LOCKED)
50727 #define F_FEC_LOCKED    V_FEC_LOCKED(1U)
50728 
50729 #define S_FEC_LOCKED0    1
50730 #define M_FEC_LOCKED0    0xfU
50731 #define V_FEC_LOCKED0(x) ((x) << S_FEC_LOCKED0)
50732 #define G_FEC_LOCKED0(x) (((x) >> S_FEC_LOCKED0) & M_FEC_LOCKED0)
50733 
50734 #define A_MAC_PORT_FEC_CERR_CNT_0 0x2624
50735 
50736 #define S_FEC_CERR_CNT_0    0
50737 #define M_FEC_CERR_CNT_0    0xffffU
50738 #define V_FEC_CERR_CNT_0(x) ((x) << S_FEC_CERR_CNT_0)
50739 #define G_FEC_CERR_CNT_0(x) (((x) >> S_FEC_CERR_CNT_0) & M_FEC_CERR_CNT_0)
50740 
50741 #define A_MAC_PORT_MTIP_FEC0_CERR_CNT_0 0x2624
50742 #define A_MAC_PORT_FEC_CERR_CNT_1 0x2628
50743 
50744 #define S_FEC_CERR_CNT_1    0
50745 #define M_FEC_CERR_CNT_1    0xffffU
50746 #define V_FEC_CERR_CNT_1(x) ((x) << S_FEC_CERR_CNT_1)
50747 #define G_FEC_CERR_CNT_1(x) (((x) >> S_FEC_CERR_CNT_1) & M_FEC_CERR_CNT_1)
50748 
50749 #define A_MAC_PORT_MTIP_FEC0_CERR_CNT_1 0x2628
50750 #define A_MAC_PORT_FEC_NCERR_CNT_0 0x262c
50751 
50752 #define S_FEC_NCERR_CNT_0    0
50753 #define M_FEC_NCERR_CNT_0    0xffffU
50754 #define V_FEC_NCERR_CNT_0(x) ((x) << S_FEC_NCERR_CNT_0)
50755 #define G_FEC_NCERR_CNT_0(x) (((x) >> S_FEC_NCERR_CNT_0) & M_FEC_NCERR_CNT_0)
50756 
50757 #define A_MAC_PORT_MTIP_FEC0_NCERR_CNT_0 0x262c
50758 
50759 #define S_FEC0_NCERR_CNT_0    0
50760 #define M_FEC0_NCERR_CNT_0    0xffffU
50761 #define V_FEC0_NCERR_CNT_0(x) ((x) << S_FEC0_NCERR_CNT_0)
50762 #define G_FEC0_NCERR_CNT_0(x) (((x) >> S_FEC0_NCERR_CNT_0) & M_FEC0_NCERR_CNT_0)
50763 
50764 #define A_MAC_PORT_FEC_NCERR_CNT_1 0x2630
50765 
50766 #define S_FEC_NCERR_CNT_1    0
50767 #define M_FEC_NCERR_CNT_1    0xffffU
50768 #define V_FEC_NCERR_CNT_1(x) ((x) << S_FEC_NCERR_CNT_1)
50769 #define G_FEC_NCERR_CNT_1(x) (((x) >> S_FEC_NCERR_CNT_1) & M_FEC_NCERR_CNT_1)
50770 
50771 #define A_MAC_PORT_MTIP_FEC0_NCERR_CNT_1 0x2630
50772 
50773 #define S_FEC0_NCERR_CNT_1    0
50774 #define M_FEC0_NCERR_CNT_1    0xffffU
50775 #define V_FEC0_NCERR_CNT_1(x) ((x) << S_FEC0_NCERR_CNT_1)
50776 #define G_FEC0_NCERR_CNT_1(x) (((x) >> S_FEC0_NCERR_CNT_1) & M_FEC0_NCERR_CNT_1)
50777 
50778 #define A_MAC_PORT_MTIP_FEC_STATUS1 0x2664
50779 #define A_MAC_PORT_MTIP_FEC1_CERR_CNT_0 0x2668
50780 #define A_MAC_PORT_MTIP_FEC1_CERR_CNT_1 0x266c
50781 #define A_MAC_PORT_MTIP_FEC1_NCERR_CNT_0 0x2670
50782 #define A_MAC_PORT_MTIP_FEC1_NCERR_CNT_1 0x2674
50783 #define A_MAC_PORT_MTIP_FEC_STATUS2 0x26a8
50784 #define A_MAC_PORT_MTIP_FEC2_CERR_CNT_0 0x26ac
50785 #define A_MAC_PORT_MTIP_FEC2_CERR_CNT_1 0x26b0
50786 #define A_MAC_PORT_MTIP_FEC2_NCERR_CNT_0 0x26b4
50787 #define A_MAC_PORT_MTIP_FEC2_NCERR_CNT_1 0x26b8
50788 #define A_MAC_PORT_MTIP_FEC_STATUS3 0x26ec
50789 #define A_MAC_PORT_MTIP_FEC3_CERR_CNT_0 0x26f0
50790 #define A_MAC_PORT_MTIP_FEC3_CERR_CNT_1 0x26f4
50791 #define A_MAC_PORT_MTIP_FEC3_NCERR_CNT_0 0x26f8
50792 #define A_MAC_PORT_MTIP_FEC3_NCERR_CNT_1 0x26fc
50793 #define A_MAC_PORT_AE_RX_COEF_REQ 0x2a00
50794 
50795 #define S_T5_RXREQ_C2    4
50796 #define M_T5_RXREQ_C2    0x3U
50797 #define V_T5_RXREQ_C2(x) ((x) << S_T5_RXREQ_C2)
50798 #define G_T5_RXREQ_C2(x) (((x) >> S_T5_RXREQ_C2) & M_T5_RXREQ_C2)
50799 
50800 #define S_T5_RXREQ_C1    2
50801 #define M_T5_RXREQ_C1    0x3U
50802 #define V_T5_RXREQ_C1(x) ((x) << S_T5_RXREQ_C1)
50803 #define G_T5_RXREQ_C1(x) (((x) >> S_T5_RXREQ_C1) & M_T5_RXREQ_C1)
50804 
50805 #define S_T5_RXREQ_C0    0
50806 #define M_T5_RXREQ_C0    0x3U
50807 #define V_T5_RXREQ_C0(x) ((x) << S_T5_RXREQ_C0)
50808 #define G_T5_RXREQ_C0(x) (((x) >> S_T5_RXREQ_C0) & M_T5_RXREQ_C0)
50809 
50810 #define S_T5_RXREQ_C3    6
50811 #define M_T5_RXREQ_C3    0x3U
50812 #define V_T5_RXREQ_C3(x) ((x) << S_T5_RXREQ_C3)
50813 #define G_T5_RXREQ_C3(x) (((x) >> S_T5_RXREQ_C3) & M_T5_RXREQ_C3)
50814 
50815 #define A_MAC_PORT_AE_RX_COEF_STAT 0x2a04
50816 
50817 #define S_T5_AE0_RXSTAT_RDY    15
50818 #define V_T5_AE0_RXSTAT_RDY(x) ((x) << S_T5_AE0_RXSTAT_RDY)
50819 #define F_T5_AE0_RXSTAT_RDY    V_T5_AE0_RXSTAT_RDY(1U)
50820 
50821 #define S_T5_AE0_RXSTAT_C2    4
50822 #define M_T5_AE0_RXSTAT_C2    0x3U
50823 #define V_T5_AE0_RXSTAT_C2(x) ((x) << S_T5_AE0_RXSTAT_C2)
50824 #define G_T5_AE0_RXSTAT_C2(x) (((x) >> S_T5_AE0_RXSTAT_C2) & M_T5_AE0_RXSTAT_C2)
50825 
50826 #define S_T5_AE0_RXSTAT_C1    2
50827 #define M_T5_AE0_RXSTAT_C1    0x3U
50828 #define V_T5_AE0_RXSTAT_C1(x) ((x) << S_T5_AE0_RXSTAT_C1)
50829 #define G_T5_AE0_RXSTAT_C1(x) (((x) >> S_T5_AE0_RXSTAT_C1) & M_T5_AE0_RXSTAT_C1)
50830 
50831 #define S_T5_AE0_RXSTAT_C0    0
50832 #define M_T5_AE0_RXSTAT_C0    0x3U
50833 #define V_T5_AE0_RXSTAT_C0(x) ((x) << S_T5_AE0_RXSTAT_C0)
50834 #define G_T5_AE0_RXSTAT_C0(x) (((x) >> S_T5_AE0_RXSTAT_C0) & M_T5_AE0_RXSTAT_C0)
50835 
50836 #define S_T5_AE0_RXSTAT_LSNA    14
50837 #define V_T5_AE0_RXSTAT_LSNA(x) ((x) << S_T5_AE0_RXSTAT_LSNA)
50838 #define F_T5_AE0_RXSTAT_LSNA    V_T5_AE0_RXSTAT_LSNA(1U)
50839 
50840 #define S_T5_AE0_RXSTAT_FEC    13
50841 #define V_T5_AE0_RXSTAT_FEC(x) ((x) << S_T5_AE0_RXSTAT_FEC)
50842 #define F_T5_AE0_RXSTAT_FEC    V_T5_AE0_RXSTAT_FEC(1U)
50843 
50844 #define S_T5_AE0_RXSTAT_TF    12
50845 #define V_T5_AE0_RXSTAT_TF(x) ((x) << S_T5_AE0_RXSTAT_TF)
50846 #define F_T5_AE0_RXSTAT_TF    V_T5_AE0_RXSTAT_TF(1U)
50847 
50848 #define S_T5_AE0_RXSTAT_C3    6
50849 #define M_T5_AE0_RXSTAT_C3    0x3U
50850 #define V_T5_AE0_RXSTAT_C3(x) ((x) << S_T5_AE0_RXSTAT_C3)
50851 #define G_T5_AE0_RXSTAT_C3(x) (((x) >> S_T5_AE0_RXSTAT_C3) & M_T5_AE0_RXSTAT_C3)
50852 
50853 #define A_MAC_PORT_AE_TX_COEF_REQ 0x2a08
50854 
50855 #define S_T5_TXREQ_C2    4
50856 #define M_T5_TXREQ_C2    0x3U
50857 #define V_T5_TXREQ_C2(x) ((x) << S_T5_TXREQ_C2)
50858 #define G_T5_TXREQ_C2(x) (((x) >> S_T5_TXREQ_C2) & M_T5_TXREQ_C2)
50859 
50860 #define S_T5_TXREQ_C1    2
50861 #define M_T5_TXREQ_C1    0x3U
50862 #define V_T5_TXREQ_C1(x) ((x) << S_T5_TXREQ_C1)
50863 #define G_T5_TXREQ_C1(x) (((x) >> S_T5_TXREQ_C1) & M_T5_TXREQ_C1)
50864 
50865 #define S_T5_TXREQ_C0    0
50866 #define M_T5_TXREQ_C0    0x3U
50867 #define V_T5_TXREQ_C0(x) ((x) << S_T5_TXREQ_C0)
50868 #define G_T5_TXREQ_C0(x) (((x) >> S_T5_TXREQ_C0) & M_T5_TXREQ_C0)
50869 
50870 #define S_TXREQ_FEC    11
50871 #define V_TXREQ_FEC(x) ((x) << S_TXREQ_FEC)
50872 #define F_TXREQ_FEC    V_TXREQ_FEC(1U)
50873 
50874 #define S_T5_TXREQ_C3    6
50875 #define M_T5_TXREQ_C3    0x3U
50876 #define V_T5_TXREQ_C3(x) ((x) << S_T5_TXREQ_C3)
50877 #define G_T5_TXREQ_C3(x) (((x) >> S_T5_TXREQ_C3) & M_T5_TXREQ_C3)
50878 
50879 #define A_MAC_PORT_AE_TX_COEF_STAT 0x2a0c
50880 
50881 #define S_T5_TXSTAT_C2    4
50882 #define M_T5_TXSTAT_C2    0x3U
50883 #define V_T5_TXSTAT_C2(x) ((x) << S_T5_TXSTAT_C2)
50884 #define G_T5_TXSTAT_C2(x) (((x) >> S_T5_TXSTAT_C2) & M_T5_TXSTAT_C2)
50885 
50886 #define S_T5_TXSTAT_C1    2
50887 #define M_T5_TXSTAT_C1    0x3U
50888 #define V_T5_TXSTAT_C1(x) ((x) << S_T5_TXSTAT_C1)
50889 #define G_T5_TXSTAT_C1(x) (((x) >> S_T5_TXSTAT_C1) & M_T5_TXSTAT_C1)
50890 
50891 #define S_T5_TXSTAT_C0    0
50892 #define M_T5_TXSTAT_C0    0x3U
50893 #define V_T5_TXSTAT_C0(x) ((x) << S_T5_TXSTAT_C0)
50894 #define G_T5_TXSTAT_C0(x) (((x) >> S_T5_TXSTAT_C0) & M_T5_TXSTAT_C0)
50895 
50896 #define S_T5_TXSTAT_C3    6
50897 #define M_T5_TXSTAT_C3    0x3U
50898 #define V_T5_TXSTAT_C3(x) ((x) << S_T5_TXSTAT_C3)
50899 #define G_T5_TXSTAT_C3(x) (((x) >> S_T5_TXSTAT_C3) & M_T5_TXSTAT_C3)
50900 
50901 #define A_MAC_PORT_AE_REG_MODE 0x2a10
50902 
50903 #define S_AET_RSVD    7
50904 #define V_AET_RSVD(x) ((x) << S_AET_RSVD)
50905 #define F_AET_RSVD    V_AET_RSVD(1U)
50906 
50907 #define S_AET_ENABLE    6
50908 #define V_AET_ENABLE(x) ((x) << S_AET_ENABLE)
50909 #define F_AET_ENABLE    V_AET_ENABLE(1U)
50910 
50911 #define S_SET_WAIT_TIMER    13
50912 #define M_SET_WAIT_TIMER    0x3U
50913 #define V_SET_WAIT_TIMER(x) ((x) << S_SET_WAIT_TIMER)
50914 #define G_SET_WAIT_TIMER(x) (((x) >> S_SET_WAIT_TIMER) & M_SET_WAIT_TIMER)
50915 
50916 #define S_C2_C3_STATE_SEL    12
50917 #define V_C2_C3_STATE_SEL(x) ((x) << S_C2_C3_STATE_SEL)
50918 #define F_C2_C3_STATE_SEL    V_C2_C3_STATE_SEL(1U)
50919 
50920 #define S_FFE4_EN    11
50921 #define V_FFE4_EN(x) ((x) << S_FFE4_EN)
50922 #define F_FFE4_EN    V_FFE4_EN(1U)
50923 
50924 #define S_FEC_REQUEST    10
50925 #define V_FEC_REQUEST(x) ((x) << S_FEC_REQUEST)
50926 #define F_FEC_REQUEST    V_FEC_REQUEST(1U)
50927 
50928 #define S_FEC_SUPPORTED    9
50929 #define V_FEC_SUPPORTED(x) ((x) << S_FEC_SUPPORTED)
50930 #define F_FEC_SUPPORTED    V_FEC_SUPPORTED(1U)
50931 
50932 #define S_TX_FIXED    8
50933 #define V_TX_FIXED(x) ((x) << S_TX_FIXED)
50934 #define F_TX_FIXED    V_TX_FIXED(1U)
50935 
50936 #define A_MAC_PORT_AE_PRBS_CTL 0x2a14
50937 #define A_MAC_PORT_AE_FSM_CTL 0x2a18
50938 
50939 #define S_CIN_ENABLE    15
50940 #define V_CIN_ENABLE(x) ((x) << S_CIN_ENABLE)
50941 #define F_CIN_ENABLE    V_CIN_ENABLE(1U)
50942 
50943 #define A_MAC_PORT_AE_FSM_STATE 0x2a1c
50944 #define A_MAC_PORT_AE_RX_COEF_REQ_1 0x2a20
50945 #define A_MAC_PORT_AE_RX_COEF_STAT_1 0x2a24
50946 
50947 #define S_T5_AE1_RXSTAT_RDY    15
50948 #define V_T5_AE1_RXSTAT_RDY(x) ((x) << S_T5_AE1_RXSTAT_RDY)
50949 #define F_T5_AE1_RXSTAT_RDY    V_T5_AE1_RXSTAT_RDY(1U)
50950 
50951 #define S_T5_AE1_RXSTAT_C2    4
50952 #define M_T5_AE1_RXSTAT_C2    0x3U
50953 #define V_T5_AE1_RXSTAT_C2(x) ((x) << S_T5_AE1_RXSTAT_C2)
50954 #define G_T5_AE1_RXSTAT_C2(x) (((x) >> S_T5_AE1_RXSTAT_C2) & M_T5_AE1_RXSTAT_C2)
50955 
50956 #define S_T5_AE1_RXSTAT_C1    2
50957 #define M_T5_AE1_RXSTAT_C1    0x3U
50958 #define V_T5_AE1_RXSTAT_C1(x) ((x) << S_T5_AE1_RXSTAT_C1)
50959 #define G_T5_AE1_RXSTAT_C1(x) (((x) >> S_T5_AE1_RXSTAT_C1) & M_T5_AE1_RXSTAT_C1)
50960 
50961 #define S_T5_AE1_RXSTAT_C0    0
50962 #define M_T5_AE1_RXSTAT_C0    0x3U
50963 #define V_T5_AE1_RXSTAT_C0(x) ((x) << S_T5_AE1_RXSTAT_C0)
50964 #define G_T5_AE1_RXSTAT_C0(x) (((x) >> S_T5_AE1_RXSTAT_C0) & M_T5_AE1_RXSTAT_C0)
50965 
50966 #define S_T5_AE1_RXSTAT_LSNA    14
50967 #define V_T5_AE1_RXSTAT_LSNA(x) ((x) << S_T5_AE1_RXSTAT_LSNA)
50968 #define F_T5_AE1_RXSTAT_LSNA    V_T5_AE1_RXSTAT_LSNA(1U)
50969 
50970 #define S_T5_AE1_RXSTAT_FEC    13
50971 #define V_T5_AE1_RXSTAT_FEC(x) ((x) << S_T5_AE1_RXSTAT_FEC)
50972 #define F_T5_AE1_RXSTAT_FEC    V_T5_AE1_RXSTAT_FEC(1U)
50973 
50974 #define S_T5_AE1_RXSTAT_TF    12
50975 #define V_T5_AE1_RXSTAT_TF(x) ((x) << S_T5_AE1_RXSTAT_TF)
50976 #define F_T5_AE1_RXSTAT_TF    V_T5_AE1_RXSTAT_TF(1U)
50977 
50978 #define S_T5_AE1_RXSTAT_C3    6
50979 #define M_T5_AE1_RXSTAT_C3    0x3U
50980 #define V_T5_AE1_RXSTAT_C3(x) ((x) << S_T5_AE1_RXSTAT_C3)
50981 #define G_T5_AE1_RXSTAT_C3(x) (((x) >> S_T5_AE1_RXSTAT_C3) & M_T5_AE1_RXSTAT_C3)
50982 
50983 #define A_MAC_PORT_AE_TX_COEF_REQ_1 0x2a28
50984 #define A_MAC_PORT_AE_TX_COEF_STAT_1 0x2a2c
50985 #define A_MAC_PORT_AE_REG_MODE_1 0x2a30
50986 #define A_MAC_PORT_AE_PRBS_CTL_1 0x2a34
50987 #define A_MAC_PORT_AE_FSM_CTL_1 0x2a38
50988 #define A_MAC_PORT_AE_FSM_STATE_1 0x2a3c
50989 #define A_MAC_PORT_AE_RX_COEF_REQ_2 0x2a40
50990 #define A_MAC_PORT_AE_RX_COEF_STAT_2 0x2a44
50991 
50992 #define S_T5_AE2_RXSTAT_RDY    15
50993 #define V_T5_AE2_RXSTAT_RDY(x) ((x) << S_T5_AE2_RXSTAT_RDY)
50994 #define F_T5_AE2_RXSTAT_RDY    V_T5_AE2_RXSTAT_RDY(1U)
50995 
50996 #define S_T5_AE2_RXSTAT_C2    4
50997 #define M_T5_AE2_RXSTAT_C2    0x3U
50998 #define V_T5_AE2_RXSTAT_C2(x) ((x) << S_T5_AE2_RXSTAT_C2)
50999 #define G_T5_AE2_RXSTAT_C2(x) (((x) >> S_T5_AE2_RXSTAT_C2) & M_T5_AE2_RXSTAT_C2)
51000 
51001 #define S_T5_AE2_RXSTAT_C1    2
51002 #define M_T5_AE2_RXSTAT_C1    0x3U
51003 #define V_T5_AE2_RXSTAT_C1(x) ((x) << S_T5_AE2_RXSTAT_C1)
51004 #define G_T5_AE2_RXSTAT_C1(x) (((x) >> S_T5_AE2_RXSTAT_C1) & M_T5_AE2_RXSTAT_C1)
51005 
51006 #define S_T5_AE2_RXSTAT_C0    0
51007 #define M_T5_AE2_RXSTAT_C0    0x3U
51008 #define V_T5_AE2_RXSTAT_C0(x) ((x) << S_T5_AE2_RXSTAT_C0)
51009 #define G_T5_AE2_RXSTAT_C0(x) (((x) >> S_T5_AE2_RXSTAT_C0) & M_T5_AE2_RXSTAT_C0)
51010 
51011 #define S_T5_AE2_RXSTAT_LSNA    14
51012 #define V_T5_AE2_RXSTAT_LSNA(x) ((x) << S_T5_AE2_RXSTAT_LSNA)
51013 #define F_T5_AE2_RXSTAT_LSNA    V_T5_AE2_RXSTAT_LSNA(1U)
51014 
51015 #define S_T5_AE2_RXSTAT_FEC    13
51016 #define V_T5_AE2_RXSTAT_FEC(x) ((x) << S_T5_AE2_RXSTAT_FEC)
51017 #define F_T5_AE2_RXSTAT_FEC    V_T5_AE2_RXSTAT_FEC(1U)
51018 
51019 #define S_T5_AE2_RXSTAT_TF    12
51020 #define V_T5_AE2_RXSTAT_TF(x) ((x) << S_T5_AE2_RXSTAT_TF)
51021 #define F_T5_AE2_RXSTAT_TF    V_T5_AE2_RXSTAT_TF(1U)
51022 
51023 #define S_T5_AE2_RXSTAT_C3    6
51024 #define M_T5_AE2_RXSTAT_C3    0x3U
51025 #define V_T5_AE2_RXSTAT_C3(x) ((x) << S_T5_AE2_RXSTAT_C3)
51026 #define G_T5_AE2_RXSTAT_C3(x) (((x) >> S_T5_AE2_RXSTAT_C3) & M_T5_AE2_RXSTAT_C3)
51027 
51028 #define A_MAC_PORT_AE_TX_COEF_REQ_2 0x2a48
51029 #define A_MAC_PORT_AE_TX_COEF_STAT_2 0x2a4c
51030 #define A_MAC_PORT_AE_REG_MODE_2 0x2a50
51031 #define A_MAC_PORT_AE_PRBS_CTL_2 0x2a54
51032 #define A_MAC_PORT_AE_FSM_CTL_2 0x2a58
51033 #define A_MAC_PORT_AE_FSM_STATE_2 0x2a5c
51034 #define A_MAC_PORT_AE_RX_COEF_REQ_3 0x2a60
51035 #define A_MAC_PORT_AE_RX_COEF_STAT_3 0x2a64
51036 
51037 #define S_T5_AE3_RXSTAT_RDY    15
51038 #define V_T5_AE3_RXSTAT_RDY(x) ((x) << S_T5_AE3_RXSTAT_RDY)
51039 #define F_T5_AE3_RXSTAT_RDY    V_T5_AE3_RXSTAT_RDY(1U)
51040 
51041 #define S_T5_AE3_RXSTAT_C2    4
51042 #define M_T5_AE3_RXSTAT_C2    0x3U
51043 #define V_T5_AE3_RXSTAT_C2(x) ((x) << S_T5_AE3_RXSTAT_C2)
51044 #define G_T5_AE3_RXSTAT_C2(x) (((x) >> S_T5_AE3_RXSTAT_C2) & M_T5_AE3_RXSTAT_C2)
51045 
51046 #define S_T5_AE3_RXSTAT_C1    2
51047 #define M_T5_AE3_RXSTAT_C1    0x3U
51048 #define V_T5_AE3_RXSTAT_C1(x) ((x) << S_T5_AE3_RXSTAT_C1)
51049 #define G_T5_AE3_RXSTAT_C1(x) (((x) >> S_T5_AE3_RXSTAT_C1) & M_T5_AE3_RXSTAT_C1)
51050 
51051 #define S_T5_AE3_RXSTAT_C0    0
51052 #define M_T5_AE3_RXSTAT_C0    0x3U
51053 #define V_T5_AE3_RXSTAT_C0(x) ((x) << S_T5_AE3_RXSTAT_C0)
51054 #define G_T5_AE3_RXSTAT_C0(x) (((x) >> S_T5_AE3_RXSTAT_C0) & M_T5_AE3_RXSTAT_C0)
51055 
51056 #define S_T5_AE3_RXSTAT_LSNA    14
51057 #define V_T5_AE3_RXSTAT_LSNA(x) ((x) << S_T5_AE3_RXSTAT_LSNA)
51058 #define F_T5_AE3_RXSTAT_LSNA    V_T5_AE3_RXSTAT_LSNA(1U)
51059 
51060 #define S_T5_AE3_RXSTAT_FEC    13
51061 #define V_T5_AE3_RXSTAT_FEC(x) ((x) << S_T5_AE3_RXSTAT_FEC)
51062 #define F_T5_AE3_RXSTAT_FEC    V_T5_AE3_RXSTAT_FEC(1U)
51063 
51064 #define S_T5_AE3_RXSTAT_TF    12
51065 #define V_T5_AE3_RXSTAT_TF(x) ((x) << S_T5_AE3_RXSTAT_TF)
51066 #define F_T5_AE3_RXSTAT_TF    V_T5_AE3_RXSTAT_TF(1U)
51067 
51068 #define S_T5_AE3_RXSTAT_C3    6
51069 #define M_T5_AE3_RXSTAT_C3    0x3U
51070 #define V_T5_AE3_RXSTAT_C3(x) ((x) << S_T5_AE3_RXSTAT_C3)
51071 #define G_T5_AE3_RXSTAT_C3(x) (((x) >> S_T5_AE3_RXSTAT_C3) & M_T5_AE3_RXSTAT_C3)
51072 
51073 #define A_MAC_PORT_AE_TX_COEF_REQ_3 0x2a68
51074 #define A_MAC_PORT_AE_TX_COEF_STAT_3 0x2a6c
51075 #define A_MAC_PORT_AE_REG_MODE_3 0x2a70
51076 #define A_MAC_PORT_AE_PRBS_CTL_3 0x2a74
51077 #define A_MAC_PORT_AE_FSM_CTL_3 0x2a78
51078 #define A_MAC_PORT_AE_FSM_STATE_3 0x2a7c
51079 #define A_MAC_PORT_AE_TX_DIS 0x2a80
51080 #define A_MAC_PORT_AE_KR_CTRL 0x2a84
51081 #define A_MAC_PORT_AE_RX_SIGDET 0x2a88
51082 #define A_MAC_PORT_AE_KR_STATUS 0x2a8c
51083 #define A_MAC_PORT_AE_TX_DIS_1 0x2a90
51084 #define A_MAC_PORT_AE_KR_CTRL_1 0x2a94
51085 #define A_MAC_PORT_AE_RX_SIGDET_1 0x2a98
51086 #define A_MAC_PORT_AE_KR_STATUS_1 0x2a9c
51087 #define A_MAC_PORT_AE_TX_DIS_2 0x2aa0
51088 #define A_MAC_PORT_AE_KR_CTRL_2 0x2aa4
51089 #define A_MAC_PORT_AE_RX_SIGDET_2 0x2aa8
51090 #define A_MAC_PORT_AE_KR_STATUS_2 0x2aac
51091 #define A_MAC_PORT_AE_TX_DIS_3 0x2ab0
51092 #define A_MAC_PORT_AE_KR_CTRL_3 0x2ab4
51093 #define A_MAC_PORT_AE_RX_SIGDET_3 0x2ab8
51094 #define A_MAC_PORT_AE_KR_STATUS_3 0x2abc
51095 #define A_MAC_PORT_AET_STAGE_CONFIGURATION_0 0x2b00
51096 
51097 #define S_EN_HOLD_FAIL    14
51098 #define V_EN_HOLD_FAIL(x) ((x) << S_EN_HOLD_FAIL)
51099 #define F_EN_HOLD_FAIL    V_EN_HOLD_FAIL(1U)
51100 
51101 #define S_INIT_METH    12
51102 #define M_INIT_METH    0x3U
51103 #define V_INIT_METH(x) ((x) << S_INIT_METH)
51104 #define G_INIT_METH(x) (((x) >> S_INIT_METH) & M_INIT_METH)
51105 
51106 #define S_CE_DECS    8
51107 #define M_CE_DECS    0xfU
51108 #define V_CE_DECS(x) ((x) << S_CE_DECS)
51109 #define G_CE_DECS(x) (((x) >> S_CE_DECS) & M_CE_DECS)
51110 
51111 #define S_EN_ZFE    7
51112 #define V_EN_ZFE(x) ((x) << S_EN_ZFE)
51113 #define F_EN_ZFE    V_EN_ZFE(1U)
51114 
51115 #define S_EN_GAIN_TOG    6
51116 #define V_EN_GAIN_TOG(x) ((x) << S_EN_GAIN_TOG)
51117 #define F_EN_GAIN_TOG    V_EN_GAIN_TOG(1U)
51118 
51119 #define S_EN_AI_C1    5
51120 #define V_EN_AI_C1(x) ((x) << S_EN_AI_C1)
51121 #define F_EN_AI_C1    V_EN_AI_C1(1U)
51122 
51123 #define S_EN_MAX_ST    4
51124 #define V_EN_MAX_ST(x) ((x) << S_EN_MAX_ST)
51125 #define F_EN_MAX_ST    V_EN_MAX_ST(1U)
51126 
51127 #define S_EN_H1T_EQ    3
51128 #define V_EN_H1T_EQ(x) ((x) << S_EN_H1T_EQ)
51129 #define F_EN_H1T_EQ    V_EN_H1T_EQ(1U)
51130 
51131 #define S_H1TEQ_GOAL    0
51132 #define M_H1TEQ_GOAL    0x7U
51133 #define V_H1TEQ_GOAL(x) ((x) << S_H1TEQ_GOAL)
51134 #define G_H1TEQ_GOAL(x) (((x) >> S_H1TEQ_GOAL) & M_H1TEQ_GOAL)
51135 
51136 #define S_T6_INIT_METH    12
51137 #define M_T6_INIT_METH    0xfU
51138 #define V_T6_INIT_METH(x) ((x) << S_T6_INIT_METH)
51139 #define G_T6_INIT_METH(x) (((x) >> S_T6_INIT_METH) & M_T6_INIT_METH)
51140 
51141 #define S_INIT_CNT    8
51142 #define M_INIT_CNT    0xfU
51143 #define V_INIT_CNT(x) ((x) << S_INIT_CNT)
51144 #define G_INIT_CNT(x) (((x) >> S_INIT_CNT) & M_INIT_CNT)
51145 
51146 #define S_EN_AI_N0    5
51147 #define V_EN_AI_N0(x) ((x) << S_EN_AI_N0)
51148 #define F_EN_AI_N0    V_EN_AI_N0(1U)
51149 
51150 #define A_MAC_PORT_AET_SIGNAL_LOSS_DETECTION_0 0x2b04
51151 
51152 #define S_GAIN_TH    6
51153 #define M_GAIN_TH    0x1fU
51154 #define V_GAIN_TH(x) ((x) << S_GAIN_TH)
51155 #define G_GAIN_TH(x) (((x) >> S_GAIN_TH) & M_GAIN_TH)
51156 
51157 #define S_EN_SD_TH    5
51158 #define V_EN_SD_TH(x) ((x) << S_EN_SD_TH)
51159 #define F_EN_SD_TH    V_EN_SD_TH(1U)
51160 
51161 #define S_EN_AMIN_TH    4
51162 #define V_EN_AMIN_TH(x) ((x) << S_EN_AMIN_TH)
51163 #define F_EN_AMIN_TH    V_EN_AMIN_TH(1U)
51164 
51165 #define S_AMIN_TH    0
51166 #define M_AMIN_TH    0xfU
51167 #define V_AMIN_TH(x) ((x) << S_AMIN_TH)
51168 #define G_AMIN_TH(x) (((x) >> S_AMIN_TH) & M_AMIN_TH)
51169 
51170 #define S_FEC_CNV    15
51171 #define V_FEC_CNV(x) ((x) << S_FEC_CNV)
51172 #define F_FEC_CNV    V_FEC_CNV(1U)
51173 
51174 #define S_EN_RETRY    14
51175 #define V_EN_RETRY(x) ((x) << S_EN_RETRY)
51176 #define F_EN_RETRY    V_EN_RETRY(1U)
51177 
51178 #define S_DPC_METH    12
51179 #define M_DPC_METH    0x3U
51180 #define V_DPC_METH(x) ((x) << S_DPC_METH)
51181 #define G_DPC_METH(x) (((x) >> S_DPC_METH) & M_DPC_METH)
51182 
51183 #define S_EN_P2    11
51184 #define V_EN_P2(x) ((x) << S_EN_P2)
51185 #define F_EN_P2    V_EN_P2(1U)
51186 
51187 #define A_MAC_PORT_AET_ZFE_LIMITS_0 0x2b08
51188 
51189 #define S_ACC_LIM    8
51190 #define M_ACC_LIM    0xfU
51191 #define V_ACC_LIM(x) ((x) << S_ACC_LIM)
51192 #define G_ACC_LIM(x) (((x) >> S_ACC_LIM) & M_ACC_LIM)
51193 
51194 #define S_CNV_LIM    4
51195 #define M_CNV_LIM    0xfU
51196 #define V_CNV_LIM(x) ((x) << S_CNV_LIM)
51197 #define G_CNV_LIM(x) (((x) >> S_CNV_LIM) & M_CNV_LIM)
51198 
51199 #define S_TOG_LIM    0
51200 #define M_TOG_LIM    0xfU
51201 #define V_TOG_LIM(x) ((x) << S_TOG_LIM)
51202 #define G_TOG_LIM(x) (((x) >> S_TOG_LIM) & M_TOG_LIM)
51203 
51204 #define A_MAC_PORT_AET_BOOTSTRAP_LOOKUP_TABLE_0 0x2b0c
51205 
51206 #define S_BOOT_LUT7    12
51207 #define M_BOOT_LUT7    0xfU
51208 #define V_BOOT_LUT7(x) ((x) << S_BOOT_LUT7)
51209 #define G_BOOT_LUT7(x) (((x) >> S_BOOT_LUT7) & M_BOOT_LUT7)
51210 
51211 #define S_BOOT_LUT6    8
51212 #define M_BOOT_LUT6    0xfU
51213 #define V_BOOT_LUT6(x) ((x) << S_BOOT_LUT6)
51214 #define G_BOOT_LUT6(x) (((x) >> S_BOOT_LUT6) & M_BOOT_LUT6)
51215 
51216 #define S_BOOT_LUT45    4
51217 #define M_BOOT_LUT45    0xfU
51218 #define V_BOOT_LUT45(x) ((x) << S_BOOT_LUT45)
51219 #define G_BOOT_LUT45(x) (((x) >> S_BOOT_LUT45) & M_BOOT_LUT45)
51220 
51221 #define S_BOOT_LUT0123    2
51222 #define M_BOOT_LUT0123    0x3U
51223 #define V_BOOT_LUT0123(x) ((x) << S_BOOT_LUT0123)
51224 #define G_BOOT_LUT0123(x) (((x) >> S_BOOT_LUT0123) & M_BOOT_LUT0123)
51225 
51226 #define S_BOOT_DEC_C0    1
51227 #define V_BOOT_DEC_C0(x) ((x) << S_BOOT_DEC_C0)
51228 #define F_BOOT_DEC_C0    V_BOOT_DEC_C0(1U)
51229 
51230 #define S_BOOT_LUT5    8
51231 #define M_BOOT_LUT5    0xfU
51232 #define V_BOOT_LUT5(x) ((x) << S_BOOT_LUT5)
51233 #define G_BOOT_LUT5(x) (((x) >> S_BOOT_LUT5) & M_BOOT_LUT5)
51234 
51235 #define A_MAC_PORT_AET_STATUS_0 0x2b10
51236 
51237 #define S_AET_STAT    9
51238 #define M_AET_STAT    0xfU
51239 #define V_AET_STAT(x) ((x) << S_AET_STAT)
51240 #define G_AET_STAT(x) (((x) >> S_AET_STAT) & M_AET_STAT)
51241 
51242 #define S_NEU_STATE    5
51243 #define M_NEU_STATE    0xfU
51244 #define V_NEU_STATE(x) ((x) << S_NEU_STATE)
51245 #define G_NEU_STATE(x) (((x) >> S_NEU_STATE) & M_NEU_STATE)
51246 
51247 #define S_CTRL_STATE    0
51248 #define M_CTRL_STATE    0x1fU
51249 #define V_CTRL_STATE(x) ((x) << S_CTRL_STATE)
51250 #define G_CTRL_STATE(x) (((x) >> S_CTRL_STATE) & M_CTRL_STATE)
51251 
51252 #define S_CTRL_STAT    8
51253 #define M_CTRL_STAT    0x1fU
51254 #define V_CTRL_STAT(x) ((x) << S_CTRL_STAT)
51255 #define G_CTRL_STAT(x) (((x) >> S_CTRL_STAT) & M_CTRL_STAT)
51256 
51257 #define S_T6_NEU_STATE    4
51258 #define M_T6_NEU_STATE    0xfU
51259 #define V_T6_NEU_STATE(x) ((x) << S_T6_NEU_STATE)
51260 #define G_T6_NEU_STATE(x) (((x) >> S_T6_NEU_STATE) & M_T6_NEU_STATE)
51261 
51262 #define S_T6_CTRL_STATE    0
51263 #define M_T6_CTRL_STATE    0xfU
51264 #define V_T6_CTRL_STATE(x) ((x) << S_T6_CTRL_STATE)
51265 #define G_T6_CTRL_STATE(x) (((x) >> S_T6_CTRL_STATE) & M_T6_CTRL_STATE)
51266 
51267 #define A_MAC_PORT_AET_STATUS_20 0x2b14
51268 
51269 #define S_FRAME_LOCK_CNT    0
51270 #define M_FRAME_LOCK_CNT    0x7U
51271 #define V_FRAME_LOCK_CNT(x) ((x) << S_FRAME_LOCK_CNT)
51272 #define G_FRAME_LOCK_CNT(x) (((x) >> S_FRAME_LOCK_CNT) & M_FRAME_LOCK_CNT)
51273 
51274 #define A_MAC_PORT_AET_LIMITS0 0x2b18
51275 
51276 #define S_DPC_TIME_LIM    0
51277 #define M_DPC_TIME_LIM    0x3U
51278 #define V_DPC_TIME_LIM(x) ((x) << S_DPC_TIME_LIM)
51279 #define G_DPC_TIME_LIM(x) (((x) >> S_DPC_TIME_LIM) & M_DPC_TIME_LIM)
51280 
51281 #define A_MAC_PORT_AET_STAGE_CONFIGURATION_1 0x2b20
51282 
51283 #define S_T6_INIT_METH    12
51284 #define M_T6_INIT_METH    0xfU
51285 #define V_T6_INIT_METH(x) ((x) << S_T6_INIT_METH)
51286 #define G_T6_INIT_METH(x) (((x) >> S_T6_INIT_METH) & M_T6_INIT_METH)
51287 
51288 #define A_MAC_PORT_AET_SIGNAL_LOSS_DETECTION_1 0x2b24
51289 #define A_MAC_PORT_AET_ZFE_LIMITS_1 0x2b28
51290 #define A_MAC_PORT_AET_BOOTSTRAP_LOOKUP_TABLE_1 0x2b2c
51291 #define A_MAC_PORT_AET_STATUS_1 0x2b30
51292 
51293 #define S_T6_NEU_STATE    4
51294 #define M_T6_NEU_STATE    0xfU
51295 #define V_T6_NEU_STATE(x) ((x) << S_T6_NEU_STATE)
51296 #define G_T6_NEU_STATE(x) (((x) >> S_T6_NEU_STATE) & M_T6_NEU_STATE)
51297 
51298 #define S_T6_CTRL_STATE    0
51299 #define M_T6_CTRL_STATE    0xfU
51300 #define V_T6_CTRL_STATE(x) ((x) << S_T6_CTRL_STATE)
51301 #define G_T6_CTRL_STATE(x) (((x) >> S_T6_CTRL_STATE) & M_T6_CTRL_STATE)
51302 
51303 #define A_MAC_PORT_AET_STATUS_21 0x2b34
51304 #define A_MAC_PORT_AET_LIMITS1 0x2b38
51305 #define A_MAC_PORT_AET_STAGE_CONFIGURATION_2 0x2b40
51306 
51307 #define S_T6_INIT_METH    12
51308 #define M_T6_INIT_METH    0xfU
51309 #define V_T6_INIT_METH(x) ((x) << S_T6_INIT_METH)
51310 #define G_T6_INIT_METH(x) (((x) >> S_T6_INIT_METH) & M_T6_INIT_METH)
51311 
51312 #define A_MAC_PORT_AET_SIGNAL_LOSS_DETECTION_2 0x2b44
51313 #define A_MAC_PORT_AET_ZFE_LIMITS_2 0x2b48
51314 #define A_MAC_PORT_AET_BOOTSTRAP_LOOKUP_TABLE_2 0x2b4c
51315 #define A_MAC_PORT_AET_STATUS_2 0x2b50
51316 
51317 #define S_T6_NEU_STATE    4
51318 #define M_T6_NEU_STATE    0xfU
51319 #define V_T6_NEU_STATE(x) ((x) << S_T6_NEU_STATE)
51320 #define G_T6_NEU_STATE(x) (((x) >> S_T6_NEU_STATE) & M_T6_NEU_STATE)
51321 
51322 #define S_T6_CTRL_STATE    0
51323 #define M_T6_CTRL_STATE    0xfU
51324 #define V_T6_CTRL_STATE(x) ((x) << S_T6_CTRL_STATE)
51325 #define G_T6_CTRL_STATE(x) (((x) >> S_T6_CTRL_STATE) & M_T6_CTRL_STATE)
51326 
51327 #define A_MAC_PORT_AET_STATUS_22 0x2b54
51328 #define A_MAC_PORT_AET_LIMITS2 0x2b58
51329 #define A_MAC_PORT_AET_STAGE_CONFIGURATION_3 0x2b60
51330 
51331 #define S_T6_INIT_METH    12
51332 #define M_T6_INIT_METH    0xfU
51333 #define V_T6_INIT_METH(x) ((x) << S_T6_INIT_METH)
51334 #define G_T6_INIT_METH(x) (((x) >> S_T6_INIT_METH) & M_T6_INIT_METH)
51335 
51336 #define A_MAC_PORT_AET_SIGNAL_LOSS_DETECTION_3 0x2b64
51337 #define A_MAC_PORT_AET_ZFE_LIMITS_3 0x2b68
51338 #define A_MAC_PORT_AET_BOOTSTRAP_LOOKUP_TABLE_3 0x2b6c
51339 #define A_MAC_PORT_AET_STATUS_3 0x2b70
51340 
51341 #define S_T6_NEU_STATE    4
51342 #define M_T6_NEU_STATE    0xfU
51343 #define V_T6_NEU_STATE(x) ((x) << S_T6_NEU_STATE)
51344 #define G_T6_NEU_STATE(x) (((x) >> S_T6_NEU_STATE) & M_T6_NEU_STATE)
51345 
51346 #define S_T6_CTRL_STATE    0
51347 #define M_T6_CTRL_STATE    0xfU
51348 #define V_T6_CTRL_STATE(x) ((x) << S_T6_CTRL_STATE)
51349 #define G_T6_CTRL_STATE(x) (((x) >> S_T6_CTRL_STATE) & M_T6_CTRL_STATE)
51350 
51351 #define A_MAC_PORT_AET_STATUS_23 0x2b74
51352 #define A_MAC_PORT_AET_LIMITS3 0x2b78
51353 #define A_T6_MAC_PORT_BEAN_CTL 0x2c00
51354 #define A_T6_MAC_PORT_BEAN_STATUS 0x2c04
51355 #define A_T6_MAC_PORT_BEAN_ABILITY_0 0x2c08
51356 
51357 #define S_BEAN_REM_FAULT    13
51358 #define V_BEAN_REM_FAULT(x) ((x) << S_BEAN_REM_FAULT)
51359 #define F_BEAN_REM_FAULT    V_BEAN_REM_FAULT(1U)
51360 
51361 #define A_T6_MAC_PORT_BEAN_ABILITY_1 0x2c0c
51362 #define A_T6_MAC_PORT_BEAN_ABILITY_2 0x2c10
51363 #define A_T6_MAC_PORT_BEAN_REM_ABILITY_0 0x2c14
51364 
51365 #define S_BEAN_ABL_REM_FAULT    13
51366 #define V_BEAN_ABL_REM_FAULT(x) ((x) << S_BEAN_ABL_REM_FAULT)
51367 #define F_BEAN_ABL_REM_FAULT    V_BEAN_ABL_REM_FAULT(1U)
51368 
51369 #define A_T6_MAC_PORT_BEAN_REM_ABILITY_1 0x2c18
51370 #define A_T6_MAC_PORT_BEAN_REM_ABILITY_2 0x2c1c
51371 #define A_T6_MAC_PORT_BEAN_MS_COUNT 0x2c20
51372 #define A_T6_MAC_PORT_BEAN_XNP_0 0x2c24
51373 #define A_T6_MAC_PORT_BEAN_XNP_1 0x2c28
51374 #define A_T6_MAC_PORT_BEAN_XNP_2 0x2c2c
51375 #define A_T6_MAC_PORT_LP_BEAN_XNP_0 0x2c30
51376 #define A_T6_MAC_PORT_LP_BEAN_XNP_1 0x2c34
51377 #define A_T6_MAC_PORT_LP_BEAN_XNP_2 0x2c38
51378 #define A_T6_MAC_PORT_BEAN_ETH_STATUS 0x2c3c
51379 
51380 #define S_100GCR4    11
51381 #define V_100GCR4(x) ((x) << S_100GCR4)
51382 #define F_100GCR4    V_100GCR4(1U)
51383 
51384 #define S_100GKR4    10
51385 #define V_100GKR4(x) ((x) << S_100GKR4)
51386 #define F_100GKR4    V_100GKR4(1U)
51387 
51388 #define S_100GKP4    9
51389 #define V_100GKP4(x) ((x) << S_100GKP4)
51390 #define F_100GKP4    V_100GKP4(1U)
51391 
51392 #define A_MAC_PORT_TX_LINKA_TRANSMIT_CONFIGURATION_MODE 0x3000
51393 
51394 #define S_T5_TX_LINKEN    15
51395 #define V_T5_TX_LINKEN(x) ((x) << S_T5_TX_LINKEN)
51396 #define F_T5_TX_LINKEN    V_T5_TX_LINKEN(1U)
51397 
51398 #define S_T5_TX_LINKRST    14
51399 #define V_T5_TX_LINKRST(x) ((x) << S_T5_TX_LINKRST)
51400 #define F_T5_TX_LINKRST    V_T5_TX_LINKRST(1U)
51401 
51402 #define S_T5_TX_CFGWRT    13
51403 #define V_T5_TX_CFGWRT(x) ((x) << S_T5_TX_CFGWRT)
51404 #define F_T5_TX_CFGWRT    V_T5_TX_CFGWRT(1U)
51405 
51406 #define S_T5_TX_CFGPTR    11
51407 #define M_T5_TX_CFGPTR    0x3U
51408 #define V_T5_TX_CFGPTR(x) ((x) << S_T5_TX_CFGPTR)
51409 #define G_T5_TX_CFGPTR(x) (((x) >> S_T5_TX_CFGPTR) & M_T5_TX_CFGPTR)
51410 
51411 #define S_T5_TX_CFGEXT    10
51412 #define V_T5_TX_CFGEXT(x) ((x) << S_T5_TX_CFGEXT)
51413 #define F_T5_TX_CFGEXT    V_T5_TX_CFGEXT(1U)
51414 
51415 #define S_T5_TX_CFGACT    9
51416 #define V_T5_TX_CFGACT(x) ((x) << S_T5_TX_CFGACT)
51417 #define F_T5_TX_CFGACT    V_T5_TX_CFGACT(1U)
51418 
51419 #define S_T5_TX_RSYNCC    8
51420 #define V_T5_TX_RSYNCC(x) ((x) << S_T5_TX_RSYNCC)
51421 #define F_T5_TX_RSYNCC    V_T5_TX_RSYNCC(1U)
51422 
51423 #define S_T5_TX_PLLSEL    6
51424 #define M_T5_TX_PLLSEL    0x3U
51425 #define V_T5_TX_PLLSEL(x) ((x) << S_T5_TX_PLLSEL)
51426 #define G_T5_TX_PLLSEL(x) (((x) >> S_T5_TX_PLLSEL) & M_T5_TX_PLLSEL)
51427 
51428 #define S_T5_TX_EXTC16    5
51429 #define V_T5_TX_EXTC16(x) ((x) << S_T5_TX_EXTC16)
51430 #define F_T5_TX_EXTC16    V_T5_TX_EXTC16(1U)
51431 
51432 #define S_T5_TX_DCKSEL    4
51433 #define V_T5_TX_DCKSEL(x) ((x) << S_T5_TX_DCKSEL)
51434 #define F_T5_TX_DCKSEL    V_T5_TX_DCKSEL(1U)
51435 
51436 #define S_T5_TX_RXLOOP    3
51437 #define V_T5_TX_RXLOOP(x) ((x) << S_T5_TX_RXLOOP)
51438 #define F_T5_TX_RXLOOP    V_T5_TX_RXLOOP(1U)
51439 
51440 #define S_T5_TX_BWSEL    2
51441 #define V_T5_TX_BWSEL(x) ((x) << S_T5_TX_BWSEL)
51442 #define F_T5_TX_BWSEL    V_T5_TX_BWSEL(1U)
51443 
51444 #define S_T5_TX_RTSEL    0
51445 #define M_T5_TX_RTSEL    0x3U
51446 #define V_T5_TX_RTSEL(x) ((x) << S_T5_TX_RTSEL)
51447 #define G_T5_TX_RTSEL(x) (((x) >> S_T5_TX_RTSEL) & M_T5_TX_RTSEL)
51448 
51449 #define S_T6_T5_TX_RXLOOP    5
51450 #define V_T6_T5_TX_RXLOOP(x) ((x) << S_T6_T5_TX_RXLOOP)
51451 #define F_T6_T5_TX_RXLOOP    V_T6_T5_TX_RXLOOP(1U)
51452 
51453 #define S_T5_TX_ENFFE4    4
51454 #define V_T5_TX_ENFFE4(x) ((x) << S_T5_TX_ENFFE4)
51455 #define F_T5_TX_ENFFE4    V_T5_TX_ENFFE4(1U)
51456 
51457 #define S_T6_T5_TX_BWSEL    2
51458 #define M_T6_T5_TX_BWSEL    0x3U
51459 #define V_T6_T5_TX_BWSEL(x) ((x) << S_T6_T5_TX_BWSEL)
51460 #define G_T6_T5_TX_BWSEL(x) (((x) >> S_T6_T5_TX_BWSEL) & M_T6_T5_TX_BWSEL)
51461 
51462 #define A_MAC_PORT_TX_LINKA_TRANSMIT_TEST_CONTROL 0x3004
51463 
51464 #define S_SPSEL    11
51465 #define M_SPSEL    0x7U
51466 #define V_SPSEL(x) ((x) << S_SPSEL)
51467 #define G_SPSEL(x) (((x) >> S_SPSEL) & M_SPSEL)
51468 
51469 #define S_AFDWEN    7
51470 #define V_AFDWEN(x) ((x) << S_AFDWEN)
51471 #define F_AFDWEN    V_AFDWEN(1U)
51472 
51473 #define S_TPGMD    3
51474 #define V_TPGMD(x) ((x) << S_TPGMD)
51475 #define F_TPGMD    V_TPGMD(1U)
51476 
51477 #define S_TC_FRCERR    10
51478 #define V_TC_FRCERR(x) ((x) << S_TC_FRCERR)
51479 #define F_TC_FRCERR    V_TC_FRCERR(1U)
51480 
51481 #define S_T6_ERROR    9
51482 #define V_T6_ERROR(x) ((x) << S_T6_ERROR)
51483 #define F_T6_ERROR    V_T6_ERROR(1U)
51484 
51485 #define S_SYNC    8
51486 #define V_SYNC(x) ((x) << S_SYNC)
51487 #define F_SYNC    V_SYNC(1U)
51488 
51489 #define S_P7CHK    5
51490 #define V_P7CHK(x) ((x) << S_P7CHK)
51491 #define F_P7CHK    V_P7CHK(1U)
51492 
51493 #define A_MAC_PORT_TX_LINKA_TRANSMIT_COEFFICIENT_CONTROL 0x3008
51494 
51495 #define S_ZCALOVRD    8
51496 #define V_ZCALOVRD(x) ((x) << S_ZCALOVRD)
51497 #define F_ZCALOVRD    V_ZCALOVRD(1U)
51498 
51499 #define S_AMMODE    7
51500 #define V_AMMODE(x) ((x) << S_AMMODE)
51501 #define F_AMMODE    V_AMMODE(1U)
51502 
51503 #define S_AEPOL    6
51504 #define V_AEPOL(x) ((x) << S_AEPOL)
51505 #define F_AEPOL    V_AEPOL(1U)
51506 
51507 #define S_AESRC    5
51508 #define V_AESRC(x) ((x) << S_AESRC)
51509 #define F_AESRC    V_AESRC(1U)
51510 
51511 #define S_SASMODE    7
51512 #define V_SASMODE(x) ((x) << S_SASMODE)
51513 #define F_SASMODE    V_SASMODE(1U)
51514 
51515 #define A_MAC_PORT_TX_LINKA_TRANSMIT_DRIVER_MODE_CONTROL 0x300c
51516 
51517 #define S_T5DRVHIZ    5
51518 #define V_T5DRVHIZ(x) ((x) << S_T5DRVHIZ)
51519 #define F_T5DRVHIZ    V_T5DRVHIZ(1U)
51520 
51521 #define S_T5SASIMP    4
51522 #define V_T5SASIMP(x) ((x) << S_T5SASIMP)
51523 #define F_T5SASIMP    V_T5SASIMP(1U)
51524 
51525 #define S_T5SLEW    2
51526 #define M_T5SLEW    0x3U
51527 #define V_T5SLEW(x) ((x) << S_T5SLEW)
51528 #define G_T5SLEW(x) (((x) >> S_T5SLEW) & M_T5SLEW)
51529 
51530 #define A_MAC_PORT_TX_LINKA_TRANSMIT_DRIVER_OVERRIDE_CONTROL 0x3010
51531 
51532 #define S_T5C2BUFDCEN    5
51533 #define V_T5C2BUFDCEN(x) ((x) << S_T5C2BUFDCEN)
51534 #define F_T5C2BUFDCEN    V_T5C2BUFDCEN(1U)
51535 
51536 #define S_T5DCCEN    4
51537 #define V_T5DCCEN(x) ((x) << S_T5DCCEN)
51538 #define F_T5DCCEN    V_T5DCCEN(1U)
51539 
51540 #define S_T5REGBYP    3
51541 #define V_T5REGBYP(x) ((x) << S_T5REGBYP)
51542 #define F_T5REGBYP    V_T5REGBYP(1U)
51543 
51544 #define S_T5REGAEN    2
51545 #define V_T5REGAEN(x) ((x) << S_T5REGAEN)
51546 #define F_T5REGAEN    V_T5REGAEN(1U)
51547 
51548 #define S_T5REGAMP    0
51549 #define M_T5REGAMP    0x3U
51550 #define V_T5REGAMP(x) ((x) << S_T5REGAMP)
51551 #define G_T5REGAMP(x) (((x) >> S_T5REGAMP) & M_T5REGAMP)
51552 
51553 #define A_MAC_PORT_TX_LINKA_TRANSMIT_DCLK_ROTATOR_OVERRIDE 0x3014
51554 
51555 #define S_RSTEP    15
51556 #define V_RSTEP(x) ((x) << S_RSTEP)
51557 #define F_RSTEP    V_RSTEP(1U)
51558 
51559 #define S_RLOCK    14
51560 #define V_RLOCK(x) ((x) << S_RLOCK)
51561 #define F_RLOCK    V_RLOCK(1U)
51562 
51563 #define S_RPOS    8
51564 #define M_RPOS    0x3fU
51565 #define V_RPOS(x) ((x) << S_RPOS)
51566 #define G_RPOS(x) (((x) >> S_RPOS) & M_RPOS)
51567 
51568 #define S_DCLKSAM    7
51569 #define V_DCLKSAM(x) ((x) << S_DCLKSAM)
51570 #define F_DCLKSAM    V_DCLKSAM(1U)
51571 
51572 #define A_MAC_PORT_TX_LINKA_TRANSMIT_IMPEDANCE_CALIBRATION_OVERRIDE 0x3018
51573 
51574 #define S_CALSSTN    3
51575 #define M_CALSSTN    0x7U
51576 #define V_CALSSTN(x) ((x) << S_CALSSTN)
51577 #define G_CALSSTN(x) (((x) >> S_CALSSTN) & M_CALSSTN)
51578 
51579 #define S_CALSSTP    0
51580 #define M_CALSSTP    0x7U
51581 #define V_CALSSTP(x) ((x) << S_CALSSTP)
51582 #define G_CALSSTP(x) (((x) >> S_CALSSTP) & M_CALSSTP)
51583 
51584 #define S_T6_CALSSTN    8
51585 #define M_T6_CALSSTN    0x3fU
51586 #define V_T6_CALSSTN(x) ((x) << S_T6_CALSSTN)
51587 #define G_T6_CALSSTN(x) (((x) >> S_T6_CALSSTN) & M_T6_CALSSTN)
51588 
51589 #define S_T6_CALSSTP    0
51590 #define M_T6_CALSSTP    0x3fU
51591 #define V_T6_CALSSTP(x) ((x) << S_T6_CALSSTP)
51592 #define G_T6_CALSSTP(x) (((x) >> S_T6_CALSSTP) & M_T6_CALSSTP)
51593 
51594 #define A_MAC_PORT_TX_LINKA_TRANSMIT_DCLK_DRIFT_TOLERANCE 0x301c
51595 
51596 #define S_DRTOL    0
51597 #define M_DRTOL    0x1fU
51598 #define V_DRTOL(x) ((x) << S_DRTOL)
51599 #define G_DRTOL(x) (((x) >> S_DRTOL) & M_DRTOL)
51600 
51601 #define S_T6_DRTOL    2
51602 #define M_T6_DRTOL    0x7U
51603 #define V_T6_DRTOL(x) ((x) << S_T6_DRTOL)
51604 #define G_T6_DRTOL(x) (((x) >> S_T6_DRTOL) & M_T6_DRTOL)
51605 
51606 #define A_MAC_PORT_TX_LINKA_TRANSMIT_TAP_0_COEFFICIENT 0x3020
51607 
51608 #define S_T5NXTT0    0
51609 #define M_T5NXTT0    0x1fU
51610 #define V_T5NXTT0(x) ((x) << S_T5NXTT0)
51611 #define G_T5NXTT0(x) (((x) >> S_T5NXTT0) & M_T5NXTT0)
51612 
51613 #define S_T6_NXTT0    0
51614 #define M_T6_NXTT0    0x3fU
51615 #define V_T6_NXTT0(x) ((x) << S_T6_NXTT0)
51616 #define G_T6_NXTT0(x) (((x) >> S_T6_NXTT0) & M_T6_NXTT0)
51617 
51618 #define A_MAC_PORT_TX_LINKA_TRANSMIT_TAP_1_COEFFICIENT 0x3024
51619 
51620 #define S_T5NXTT1    0
51621 #define M_T5NXTT1    0x3fU
51622 #define V_T5NXTT1(x) ((x) << S_T5NXTT1)
51623 #define G_T5NXTT1(x) (((x) >> S_T5NXTT1) & M_T5NXTT1)
51624 
51625 #define A_MAC_PORT_TX_LINKA_TRANSMIT_TAP_2_COEFFICIENT 0x3028
51626 
51627 #define S_T5NXTT2    0
51628 #define M_T5NXTT2    0x3fU
51629 #define V_T5NXTT2(x) ((x) << S_T5NXTT2)
51630 #define G_T5NXTT2(x) (((x) >> S_T5NXTT2) & M_T5NXTT2)
51631 
51632 #define S_T6_NXTT2    0
51633 #define M_T6_NXTT2    0x3fU
51634 #define V_T6_NXTT2(x) ((x) << S_T6_NXTT2)
51635 #define G_T6_NXTT2(x) (((x) >> S_T6_NXTT2) & M_T6_NXTT2)
51636 
51637 #define A_MAC_PORT_TX_LINKA_TRANSMIT_TAP_3_COEFFICIENT 0x302c
51638 
51639 #define S_NXTT3    0
51640 #define M_NXTT3    0x3fU
51641 #define V_NXTT3(x) ((x) << S_NXTT3)
51642 #define G_NXTT3(x) (((x) >> S_NXTT3) & M_NXTT3)
51643 
51644 #define A_MAC_PORT_TX_LINKA_TRANSMIT_AMPLITUDE 0x3030
51645 
51646 #define S_T5TXPWR    0
51647 #define M_T5TXPWR    0x3fU
51648 #define V_T5TXPWR(x) ((x) << S_T5TXPWR)
51649 #define G_T5TXPWR(x) (((x) >> S_T5TXPWR) & M_T5TXPWR)
51650 
51651 #define A_MAC_PORT_TX_LINKA_TRANSMIT_POLARITY 0x3034
51652 
51653 #define S_NXTPOL    0
51654 #define M_NXTPOL    0x7U
51655 #define V_NXTPOL(x) ((x) << S_NXTPOL)
51656 #define G_NXTPOL(x) (((x) >> S_NXTPOL) & M_NXTPOL)
51657 
51658 #define S_T6_NXTPOL    0
51659 #define M_T6_NXTPOL    0xfU
51660 #define V_T6_NXTPOL(x) ((x) << S_T6_NXTPOL)
51661 #define G_T6_NXTPOL(x) (((x) >> S_T6_NXTPOL) & M_T6_NXTPOL)
51662 
51663 #define A_MAC_PORT_TX_LINKA_TRANSMIT_802_3AP_ADAPTIVE_EQUALIZATION_COMMAND 0x3038
51664 
51665 #define S_CPREST    13
51666 #define V_CPREST(x) ((x) << S_CPREST)
51667 #define F_CPREST    V_CPREST(1U)
51668 
51669 #define S_CINIT    12
51670 #define V_CINIT(x) ((x) << S_CINIT)
51671 #define F_CINIT    V_CINIT(1U)
51672 
51673 #define S_SASCMD    10
51674 #define M_SASCMD    0x3U
51675 #define V_SASCMD(x) ((x) << S_SASCMD)
51676 #define G_SASCMD(x) (((x) >> S_SASCMD) & M_SASCMD)
51677 
51678 #define S_T6_C0UPDT    6
51679 #define M_T6_C0UPDT    0x3U
51680 #define V_T6_C0UPDT(x) ((x) << S_T6_C0UPDT)
51681 #define G_T6_C0UPDT(x) (((x) >> S_T6_C0UPDT) & M_T6_C0UPDT)
51682 
51683 #define S_C3UPDT    4
51684 #define M_C3UPDT    0x3U
51685 #define V_C3UPDT(x) ((x) << S_C3UPDT)
51686 #define G_C3UPDT(x) (((x) >> S_C3UPDT) & M_C3UPDT)
51687 
51688 #define S_T6_C2UPDT    2
51689 #define M_T6_C2UPDT    0x3U
51690 #define V_T6_C2UPDT(x) ((x) << S_T6_C2UPDT)
51691 #define G_T6_C2UPDT(x) (((x) >> S_T6_C2UPDT) & M_T6_C2UPDT)
51692 
51693 #define S_T6_C1UPDT    0
51694 #define M_T6_C1UPDT    0x3U
51695 #define V_T6_C1UPDT(x) ((x) << S_T6_C1UPDT)
51696 #define G_T6_C1UPDT(x) (((x) >> S_T6_C1UPDT) & M_T6_C1UPDT)
51697 
51698 #define A_MAC_PORT_TX_LINKA_TRANSMIT_802_3AP_ADAPTIVE_EQUALIZATION_STATUS 0x303c
51699 
51700 #define S_T6_C0STAT    6
51701 #define M_T6_C0STAT    0x3U
51702 #define V_T6_C0STAT(x) ((x) << S_T6_C0STAT)
51703 #define G_T6_C0STAT(x) (((x) >> S_T6_C0STAT) & M_T6_C0STAT)
51704 
51705 #define S_C3STAT    4
51706 #define M_C3STAT    0x3U
51707 #define V_C3STAT(x) ((x) << S_C3STAT)
51708 #define G_C3STAT(x) (((x) >> S_C3STAT) & M_C3STAT)
51709 
51710 #define S_T6_C2STAT    2
51711 #define M_T6_C2STAT    0x3U
51712 #define V_T6_C2STAT(x) ((x) << S_T6_C2STAT)
51713 #define G_T6_C2STAT(x) (((x) >> S_T6_C2STAT) & M_T6_C2STAT)
51714 
51715 #define S_T6_C1STAT    0
51716 #define M_T6_C1STAT    0x3U
51717 #define V_T6_C1STAT(x) ((x) << S_T6_C1STAT)
51718 #define G_T6_C1STAT(x) (((x) >> S_T6_C1STAT) & M_T6_C1STAT)
51719 
51720 #define A_MAC_PORT_TX_LINKA_TRANSMIT_TAP_0_COEFFICIENT_OVERRIDE 0x3040
51721 #define A_MAC_PORT_TX_LINKA_TRANSMIT_AE_TAP_0_COEFFICIENT_OVERRIDE 0x3040
51722 
51723 #define S_AETAP0    0
51724 #define M_AETAP0    0x7fU
51725 #define V_AETAP0(x) ((x) << S_AETAP0)
51726 #define G_AETAP0(x) (((x) >> S_AETAP0) & M_AETAP0)
51727 
51728 #define A_MAC_PORT_TX_LINKA_TRANSMIT_TAP_1_COEFFICIENT_OVERRIDE 0x3044
51729 
51730 #define S_T5NIDAC1    0
51731 #define M_T5NIDAC1    0x3fU
51732 #define V_T5NIDAC1(x) ((x) << S_T5NIDAC1)
51733 #define G_T5NIDAC1(x) (((x) >> S_T5NIDAC1) & M_T5NIDAC1)
51734 
51735 #define A_MAC_PORT_TX_LINKA_TRANSMIT_AE_TAP_1_COEFFICIENT_OVERRIDE 0x3044
51736 
51737 #define S_AETAP1    0
51738 #define M_AETAP1    0x7fU
51739 #define V_AETAP1(x) ((x) << S_AETAP1)
51740 #define G_AETAP1(x) (((x) >> S_AETAP1) & M_AETAP1)
51741 
51742 #define A_MAC_PORT_TX_LINKA_TRANSMIT_TAP_2_COEFFICIENT_OVERRIDE 0x3048
51743 
51744 #define S_T5NIDAC2    0
51745 #define M_T5NIDAC2    0x3fU
51746 #define V_T5NIDAC2(x) ((x) << S_T5NIDAC2)
51747 #define G_T5NIDAC2(x) (((x) >> S_T5NIDAC2) & M_T5NIDAC2)
51748 
51749 #define A_MAC_PORT_TX_LINKA_TRANSMIT_AE_TAP_2_COEFFICIENT_OVERRIDE 0x3048
51750 
51751 #define S_AETAP2    0
51752 #define M_AETAP2    0x7fU
51753 #define V_AETAP2(x) ((x) << S_AETAP2)
51754 #define G_AETAP2(x) (((x) >> S_AETAP2) & M_AETAP2)
51755 
51756 #define A_MAC_PORT_TX_LINKA_TRANSMIT_AE_TAP_3_COEFFICIENT_OVERRIDE 0x304c
51757 
51758 #define S_AETAP3    0
51759 #define M_AETAP3    0x7fU
51760 #define V_AETAP3(x) ((x) << S_AETAP3)
51761 #define G_AETAP3(x) (((x) >> S_AETAP3) & M_AETAP3)
51762 
51763 #define A_MAC_PORT_TX_LINKA_TRANSMIT_APPLIED_TUNE_REGISTER 0x3050
51764 
51765 #define S_ATUNEN    8
51766 #define M_ATUNEN    0xffU
51767 #define V_ATUNEN(x) ((x) << S_ATUNEN)
51768 #define G_ATUNEN(x) (((x) >> S_ATUNEN) & M_ATUNEN)
51769 
51770 #define S_ATUNEP    0
51771 #define M_ATUNEP    0xffU
51772 #define V_ATUNEP(x) ((x) << S_ATUNEP)
51773 #define G_ATUNEP(x) (((x) >> S_ATUNEP) & M_ATUNEP)
51774 
51775 #define A_MAC_PORT_TX_LINKA_TRANSMIT_ANALOG_DIAGNOSTICS_REGISTER 0x3058
51776 
51777 #define S_DCCCOMPINV    8
51778 #define V_DCCCOMPINV(x) ((x) << S_DCCCOMPINV)
51779 #define F_DCCCOMPINV    V_DCCCOMPINV(1U)
51780 
51781 #define A_MAC_PORT_TX_LINKA_TRANSMIT_TAP_0_COEFFICIENT_APPLIED 0x3060
51782 #define A_MAC_PORT_TX_LINKA_TRANSMIT_4X_SEGMENT_APPLIED 0x3060
51783 
51784 #define S_AS4X7    14
51785 #define M_AS4X7    0x3U
51786 #define V_AS4X7(x) ((x) << S_AS4X7)
51787 #define G_AS4X7(x) (((x) >> S_AS4X7) & M_AS4X7)
51788 
51789 #define S_AS4X6    12
51790 #define M_AS4X6    0x3U
51791 #define V_AS4X6(x) ((x) << S_AS4X6)
51792 #define G_AS4X6(x) (((x) >> S_AS4X6) & M_AS4X6)
51793 
51794 #define S_AS4X5    10
51795 #define M_AS4X5    0x3U
51796 #define V_AS4X5(x) ((x) << S_AS4X5)
51797 #define G_AS4X5(x) (((x) >> S_AS4X5) & M_AS4X5)
51798 
51799 #define S_AS4X4    8
51800 #define M_AS4X4    0x3U
51801 #define V_AS4X4(x) ((x) << S_AS4X4)
51802 #define G_AS4X4(x) (((x) >> S_AS4X4) & M_AS4X4)
51803 
51804 #define S_AS4X3    6
51805 #define M_AS4X3    0x3U
51806 #define V_AS4X3(x) ((x) << S_AS4X3)
51807 #define G_AS4X3(x) (((x) >> S_AS4X3) & M_AS4X3)
51808 
51809 #define S_AS4X2    4
51810 #define M_AS4X2    0x3U
51811 #define V_AS4X2(x) ((x) << S_AS4X2)
51812 #define G_AS4X2(x) (((x) >> S_AS4X2) & M_AS4X2)
51813 
51814 #define S_AS4X1    2
51815 #define M_AS4X1    0x3U
51816 #define V_AS4X1(x) ((x) << S_AS4X1)
51817 #define G_AS4X1(x) (((x) >> S_AS4X1) & M_AS4X1)
51818 
51819 #define S_AS4X0    0
51820 #define M_AS4X0    0x3U
51821 #define V_AS4X0(x) ((x) << S_AS4X0)
51822 #define G_AS4X0(x) (((x) >> S_AS4X0) & M_AS4X0)
51823 
51824 #define A_MAC_PORT_TX_LINKA_TRANSMIT_TAP_1_COEFFICIENT_APPLIED 0x3064
51825 
51826 #define S_T5AIDAC1    0
51827 #define M_T5AIDAC1    0x3fU
51828 #define V_T5AIDAC1(x) ((x) << S_T5AIDAC1)
51829 #define G_T5AIDAC1(x) (((x) >> S_T5AIDAC1) & M_T5AIDAC1)
51830 
51831 #define A_MAC_PORT_TX_LINKA_TRANSMIT_2X_SEGMENT_APPLIED 0x3064
51832 
51833 #define S_AS2X3    6
51834 #define M_AS2X3    0x3U
51835 #define V_AS2X3(x) ((x) << S_AS2X3)
51836 #define G_AS2X3(x) (((x) >> S_AS2X3) & M_AS2X3)
51837 
51838 #define S_AS2X2    4
51839 #define M_AS2X2    0x3U
51840 #define V_AS2X2(x) ((x) << S_AS2X2)
51841 #define G_AS2X2(x) (((x) >> S_AS2X2) & M_AS2X2)
51842 
51843 #define S_AS2X1    2
51844 #define M_AS2X1    0x3U
51845 #define V_AS2X1(x) ((x) << S_AS2X1)
51846 #define G_AS2X1(x) (((x) >> S_AS2X1) & M_AS2X1)
51847 
51848 #define S_AS2X0    0
51849 #define M_AS2X0    0x3U
51850 #define V_AS2X0(x) ((x) << S_AS2X0)
51851 #define G_AS2X0(x) (((x) >> S_AS2X0) & M_AS2X0)
51852 
51853 #define A_MAC_PORT_TX_LINKA_TRANSMIT_TAP_2_COEFFICIENT_APPLIED 0x3068
51854 #define A_MAC_PORT_TX_LINKA_TRANSMIT_1X_SEGMENT_APPLIED 0x3068
51855 
51856 #define S_AS1X7    14
51857 #define M_AS1X7    0x3U
51858 #define V_AS1X7(x) ((x) << S_AS1X7)
51859 #define G_AS1X7(x) (((x) >> S_AS1X7) & M_AS1X7)
51860 
51861 #define S_AS1X6    12
51862 #define M_AS1X6    0x3U
51863 #define V_AS1X6(x) ((x) << S_AS1X6)
51864 #define G_AS1X6(x) (((x) >> S_AS1X6) & M_AS1X6)
51865 
51866 #define S_AS1X5    10
51867 #define M_AS1X5    0x3U
51868 #define V_AS1X5(x) ((x) << S_AS1X5)
51869 #define G_AS1X5(x) (((x) >> S_AS1X5) & M_AS1X5)
51870 
51871 #define S_AS1X4    8
51872 #define M_AS1X4    0x3U
51873 #define V_AS1X4(x) ((x) << S_AS1X4)
51874 #define G_AS1X4(x) (((x) >> S_AS1X4) & M_AS1X4)
51875 
51876 #define S_AS1X3    6
51877 #define M_AS1X3    0x3U
51878 #define V_AS1X3(x) ((x) << S_AS1X3)
51879 #define G_AS1X3(x) (((x) >> S_AS1X3) & M_AS1X3)
51880 
51881 #define S_AS1X2    4
51882 #define M_AS1X2    0x3U
51883 #define V_AS1X2(x) ((x) << S_AS1X2)
51884 #define G_AS1X2(x) (((x) >> S_AS1X2) & M_AS1X2)
51885 
51886 #define S_AS1X1    2
51887 #define M_AS1X1    0x3U
51888 #define V_AS1X1(x) ((x) << S_AS1X1)
51889 #define G_AS1X1(x) (((x) >> S_AS1X1) & M_AS1X1)
51890 
51891 #define S_AS1X0    0
51892 #define M_AS1X0    0x3U
51893 #define V_AS1X0(x) ((x) << S_AS1X0)
51894 #define G_AS1X0(x) (((x) >> S_AS1X0) & M_AS1X0)
51895 
51896 #define A_MAC_PORT_TX_LINKA_TRANSMIT_SEGMENT_4X_TERMINATION_APPLIED 0x306c
51897 
51898 #define S_AT4X    0
51899 #define M_AT4X    0xffU
51900 #define V_AT4X(x) ((x) << S_AT4X)
51901 #define G_AT4X(x) (((x) >> S_AT4X) & M_AT4X)
51902 
51903 #define A_MAC_PORT_TX_LINKA_TRANSMIT_SEGMENT_DISABLE_APPLIED_1 0x3070
51904 
51905 #define S_MAINSC    6
51906 #define M_MAINSC    0x3fU
51907 #define V_MAINSC(x) ((x) << S_MAINSC)
51908 #define G_MAINSC(x) (((x) >> S_MAINSC) & M_MAINSC)
51909 
51910 #define S_POSTSC    0
51911 #define M_POSTSC    0x3fU
51912 #define V_POSTSC(x) ((x) << S_POSTSC)
51913 #define G_POSTSC(x) (((x) >> S_POSTSC) & M_POSTSC)
51914 
51915 #define A_MAC_PORT_TX_LINKA_TRANSMIT_SEGMENT_2X1X_TERMINATION_APPLIED 0x3070
51916 
51917 #define S_AT2X    8
51918 #define M_AT2X    0xfU
51919 #define V_AT2X(x) ((x) << S_AT2X)
51920 #define G_AT2X(x) (((x) >> S_AT2X) & M_AT2X)
51921 
51922 #define A_MAC_PORT_TX_LINKA_TRANSMIT_SEGMENT_DISABLE_APPLIED_2 0x3074
51923 
51924 #define S_PRESC    0
51925 #define M_PRESC    0x1fU
51926 #define V_PRESC(x) ((x) << S_PRESC)
51927 #define G_PRESC(x) (((x) >> S_PRESC) & M_PRESC)
51928 
51929 #define A_MAC_PORT_TX_LINKA_TRANSMIT_TAP_SIGN_APPLIED_REGISTER 0x3074
51930 
51931 #define S_ATSIGN    0
51932 #define M_ATSIGN    0xfU
51933 #define V_ATSIGN(x) ((x) << S_ATSIGN)
51934 #define G_ATSIGN(x) (((x) >> S_ATSIGN) & M_ATSIGN)
51935 
51936 #define A_MAC_PORT_TX_LINKA_TRANSMIT_EXTENDED_ADDRESS_DATA 0x3078
51937 #define A_MAC_PORT_TX_LINKA_TRANSMIT_EXTENDED_ADDRESS_ADDR 0x307c
51938 
51939 #define S_T5XADDR    1
51940 #define M_T5XADDR    0x1fU
51941 #define V_T5XADDR(x) ((x) << S_T5XADDR)
51942 #define G_T5XADDR(x) (((x) >> S_T5XADDR) & M_T5XADDR)
51943 
51944 #define S_T5XWR    0
51945 #define V_T5XWR(x) ((x) << S_T5XWR)
51946 #define F_T5XWR    V_T5XWR(1U)
51947 
51948 #define S_T6_XADDR    1
51949 #define M_T6_XADDR    0x1fU
51950 #define V_T6_XADDR(x) ((x) << S_T6_XADDR)
51951 #define G_T6_XADDR(x) (((x) >> S_T6_XADDR) & M_T6_XADDR)
51952 
51953 #define A_MAC_PORT_TX_LINKA_TRANSMIT_PATTERN_BUFFER_BYTES_1_0 0x3080
51954 
51955 #define S_XDAT10    0
51956 #define M_XDAT10    0xffffU
51957 #define V_XDAT10(x) ((x) << S_XDAT10)
51958 #define G_XDAT10(x) (((x) >> S_XDAT10) & M_XDAT10)
51959 
51960 #define A_MAC_PORT_TX_LINKA_TRANSMIT_PATTERN_BUFFER_BYTES_3_2 0x3084
51961 
51962 #define S_XDAT32    0
51963 #define M_XDAT32    0xffffU
51964 #define V_XDAT32(x) ((x) << S_XDAT32)
51965 #define G_XDAT32(x) (((x) >> S_XDAT32) & M_XDAT32)
51966 
51967 #define A_MAC_PORT_TX_LINKA_TRANSMIT_PATTERN_BUFFER_BYTE_4 0x3088
51968 
51969 #define S_XDAT4    0
51970 #define M_XDAT4    0xffU
51971 #define V_XDAT4(x) ((x) << S_XDAT4)
51972 #define G_XDAT4(x) (((x) >> S_XDAT4) & M_XDAT4)
51973 
51974 #define A_MAC_PORT_TX_LINKA_TRANSMIT_PATTERN_BUFFER_BYTES_5_4 0x3088
51975 
51976 #define S_XDAT54    0
51977 #define M_XDAT54    0xffffU
51978 #define V_XDAT54(x) ((x) << S_XDAT54)
51979 #define G_XDAT54(x) (((x) >> S_XDAT54) & M_XDAT54)
51980 
51981 #define A_MAC_PORT_TX_LINKA_TRANSMIT_DCC_CONTROL 0x308c
51982 
51983 #define S_DCCTIMEDOUT    15
51984 #define V_DCCTIMEDOUT(x) ((x) << S_DCCTIMEDOUT)
51985 #define F_DCCTIMEDOUT    V_DCCTIMEDOUT(1U)
51986 
51987 #define S_DCCTIMEEN    14
51988 #define V_DCCTIMEEN(x) ((x) << S_DCCTIMEEN)
51989 #define F_DCCTIMEEN    V_DCCTIMEEN(1U)
51990 
51991 #define S_DCCLOCK    13
51992 #define V_DCCLOCK(x) ((x) << S_DCCLOCK)
51993 #define F_DCCLOCK    V_DCCLOCK(1U)
51994 
51995 #define S_DCCOFFSET    8
51996 #define M_DCCOFFSET    0x1fU
51997 #define V_DCCOFFSET(x) ((x) << S_DCCOFFSET)
51998 #define G_DCCOFFSET(x) (((x) >> S_DCCOFFSET) & M_DCCOFFSET)
51999 
52000 #define S_DCCSTEP    6
52001 #define M_DCCSTEP    0x3U
52002 #define V_DCCSTEP(x) ((x) << S_DCCSTEP)
52003 #define G_DCCSTEP(x) (((x) >> S_DCCSTEP) & M_DCCSTEP)
52004 
52005 #define S_DCCASTEP    1
52006 #define M_DCCASTEP    0x1fU
52007 #define V_DCCASTEP(x) ((x) << S_DCCASTEP)
52008 #define G_DCCASTEP(x) (((x) >> S_DCCASTEP) & M_DCCASTEP)
52009 
52010 #define S_DCCAEN    0
52011 #define V_DCCAEN(x) ((x) << S_DCCAEN)
52012 #define F_DCCAEN    V_DCCAEN(1U)
52013 
52014 #define A_MAC_PORT_TX_LINKA_TRANSMIT_PATTERN_BUFFER_BYTES_7_6 0x308c
52015 
52016 #define S_XDAT76    0
52017 #define M_XDAT76    0xffffU
52018 #define V_XDAT76(x) ((x) << S_XDAT76)
52019 #define G_XDAT76(x) (((x) >> S_XDAT76) & M_XDAT76)
52020 
52021 #define A_MAC_PORT_TX_LINKA_TRANSMIT_DCC_OVERRIDE 0x3090
52022 
52023 #define S_DCCOUT    12
52024 #define V_DCCOUT(x) ((x) << S_DCCOUT)
52025 #define F_DCCOUT    V_DCCOUT(1U)
52026 
52027 #define S_DCCCLK    11
52028 #define V_DCCCLK(x) ((x) << S_DCCCLK)
52029 #define F_DCCCLK    V_DCCCLK(1U)
52030 
52031 #define S_DCCHOLD    10
52032 #define V_DCCHOLD(x) ((x) << S_DCCHOLD)
52033 #define F_DCCHOLD    V_DCCHOLD(1U)
52034 
52035 #define S_DCCSIGN    8
52036 #define M_DCCSIGN    0x3U
52037 #define V_DCCSIGN(x) ((x) << S_DCCSIGN)
52038 #define G_DCCSIGN(x) (((x) >> S_DCCSIGN) & M_DCCSIGN)
52039 
52040 #define S_DCCAMP    1
52041 #define M_DCCAMP    0x7fU
52042 #define V_DCCAMP(x) ((x) << S_DCCAMP)
52043 #define G_DCCAMP(x) (((x) >> S_DCCAMP) & M_DCCAMP)
52044 
52045 #define S_DCCOEN    0
52046 #define V_DCCOEN(x) ((x) << S_DCCOEN)
52047 #define F_DCCOEN    V_DCCOEN(1U)
52048 
52049 #define A_MAC_PORT_TX_LINKA_TRANSMIT_DCC_APPLIED 0x3094
52050 
52051 #define S_DCCASIGN    7
52052 #define M_DCCASIGN    0x3U
52053 #define V_DCCASIGN(x) ((x) << S_DCCASIGN)
52054 #define G_DCCASIGN(x) (((x) >> S_DCCASIGN) & M_DCCASIGN)
52055 
52056 #define S_DCCAAMP    0
52057 #define M_DCCAAMP    0x7fU
52058 #define V_DCCAAMP(x) ((x) << S_DCCAAMP)
52059 #define G_DCCAAMP(x) (((x) >> S_DCCAAMP) & M_DCCAAMP)
52060 
52061 #define A_MAC_PORT_TX_LINKA_TRANSMIT_DCC_TIME_OUT 0x3098
52062 
52063 #define S_DCCTIMEOUTVAL    0
52064 #define M_DCCTIMEOUTVAL    0xffffU
52065 #define V_DCCTIMEOUTVAL(x) ((x) << S_DCCTIMEOUTVAL)
52066 #define G_DCCTIMEOUTVAL(x) (((x) >> S_DCCTIMEOUTVAL) & M_DCCTIMEOUTVAL)
52067 
52068 #define A_MAC_PORT_TX_LINKA_TRANSMIT_802_3AZ_CONTROL 0x309c
52069 
52070 #define S_LPIDCLK    4
52071 #define V_LPIDCLK(x) ((x) << S_LPIDCLK)
52072 #define F_LPIDCLK    V_LPIDCLK(1U)
52073 
52074 #define S_LPITERM    2
52075 #define M_LPITERM    0x3U
52076 #define V_LPITERM(x) ((x) << S_LPITERM)
52077 #define G_LPITERM(x) (((x) >> S_LPITERM) & M_LPITERM)
52078 
52079 #define S_LPIPRCD    0
52080 #define M_LPIPRCD    0x3U
52081 #define V_LPIPRCD(x) ((x) << S_LPIPRCD)
52082 #define G_LPIPRCD(x) (((x) >> S_LPIPRCD) & M_LPIPRCD)
52083 
52084 #define A_T6_MAC_PORT_TX_LINKA_TRANSMIT_DCC_CONTROL 0x30a0
52085 
52086 #define S_T6_DCCTIMEEN    13
52087 #define M_T6_DCCTIMEEN    0x3U
52088 #define V_T6_DCCTIMEEN(x) ((x) << S_T6_DCCTIMEEN)
52089 #define G_T6_DCCTIMEEN(x) (((x) >> S_T6_DCCTIMEEN) & M_T6_DCCTIMEEN)
52090 
52091 #define S_T6_DCCLOCK    11
52092 #define M_T6_DCCLOCK    0x3U
52093 #define V_T6_DCCLOCK(x) ((x) << S_T6_DCCLOCK)
52094 #define G_T6_DCCLOCK(x) (((x) >> S_T6_DCCLOCK) & M_T6_DCCLOCK)
52095 
52096 #define S_T6_DCCOFFSET    8
52097 #define M_T6_DCCOFFSET    0x7U
52098 #define V_T6_DCCOFFSET(x) ((x) << S_T6_DCCOFFSET)
52099 #define G_T6_DCCOFFSET(x) (((x) >> S_T6_DCCOFFSET) & M_T6_DCCOFFSET)
52100 
52101 #define S_TX_LINKA_DCCSTEP_CTL    6
52102 #define M_TX_LINKA_DCCSTEP_CTL    0x3U
52103 #define V_TX_LINKA_DCCSTEP_CTL(x) ((x) << S_TX_LINKA_DCCSTEP_CTL)
52104 #define G_TX_LINKA_DCCSTEP_CTL(x) (((x) >> S_TX_LINKA_DCCSTEP_CTL) & M_TX_LINKA_DCCSTEP_CTL)
52105 
52106 #define A_T6_MAC_PORT_TX_LINKA_TRANSMIT_DCC_OVERRIDE 0x30a4
52107 #define A_T6_MAC_PORT_TX_LINKA_TRANSMIT_DCC_APPLIED 0x30a8
52108 #define A_T6_MAC_PORT_TX_LINKA_TRANSMIT_DCC_TIME_OUT 0x30ac
52109 #define A_MAC_PORT_TX_LINKA_TRANSMIT_TAP_SIGN_OVERRIDE 0x30c0
52110 
52111 #define S_OSIGN    0
52112 #define M_OSIGN    0xfU
52113 #define V_OSIGN(x) ((x) << S_OSIGN)
52114 #define G_OSIGN(x) (((x) >> S_OSIGN) & M_OSIGN)
52115 
52116 #define A_MAC_PORT_TX_LINKA_TRANSMIT_SEGMENT_4X_OVERRIDE 0x30c8
52117 
52118 #define S_OS4X7    14
52119 #define M_OS4X7    0x3U
52120 #define V_OS4X7(x) ((x) << S_OS4X7)
52121 #define G_OS4X7(x) (((x) >> S_OS4X7) & M_OS4X7)
52122 
52123 #define S_OS4X6    12
52124 #define M_OS4X6    0x3U
52125 #define V_OS4X6(x) ((x) << S_OS4X6)
52126 #define G_OS4X6(x) (((x) >> S_OS4X6) & M_OS4X6)
52127 
52128 #define S_OS4X5    10
52129 #define M_OS4X5    0x3U
52130 #define V_OS4X5(x) ((x) << S_OS4X5)
52131 #define G_OS4X5(x) (((x) >> S_OS4X5) & M_OS4X5)
52132 
52133 #define S_OS4X4    8
52134 #define M_OS4X4    0x3U
52135 #define V_OS4X4(x) ((x) << S_OS4X4)
52136 #define G_OS4X4(x) (((x) >> S_OS4X4) & M_OS4X4)
52137 
52138 #define S_OS4X3    6
52139 #define M_OS4X3    0x3U
52140 #define V_OS4X3(x) ((x) << S_OS4X3)
52141 #define G_OS4X3(x) (((x) >> S_OS4X3) & M_OS4X3)
52142 
52143 #define S_OS4X2    4
52144 #define M_OS4X2    0x3U
52145 #define V_OS4X2(x) ((x) << S_OS4X2)
52146 #define G_OS4X2(x) (((x) >> S_OS4X2) & M_OS4X2)
52147 
52148 #define S_OS4X1    2
52149 #define M_OS4X1    0x3U
52150 #define V_OS4X1(x) ((x) << S_OS4X1)
52151 #define G_OS4X1(x) (((x) >> S_OS4X1) & M_OS4X1)
52152 
52153 #define S_OS4X0    0
52154 #define M_OS4X0    0x3U
52155 #define V_OS4X0(x) ((x) << S_OS4X0)
52156 #define G_OS4X0(x) (((x) >> S_OS4X0) & M_OS4X0)
52157 
52158 #define A_MAC_PORT_TX_LINKA_TRANSMIT_SEGMENT_2X_OVERRIDE 0x30cc
52159 
52160 #define S_OS2X3    6
52161 #define M_OS2X3    0x3U
52162 #define V_OS2X3(x) ((x) << S_OS2X3)
52163 #define G_OS2X3(x) (((x) >> S_OS2X3) & M_OS2X3)
52164 
52165 #define S_OS2X2    4
52166 #define M_OS2X2    0x3U
52167 #define V_OS2X2(x) ((x) << S_OS2X2)
52168 #define G_OS2X2(x) (((x) >> S_OS2X2) & M_OS2X2)
52169 
52170 #define S_OS2X1    2
52171 #define M_OS2X1    0x3U
52172 #define V_OS2X1(x) ((x) << S_OS2X1)
52173 #define G_OS2X1(x) (((x) >> S_OS2X1) & M_OS2X1)
52174 
52175 #define S_OS2X0    0
52176 #define M_OS2X0    0x3U
52177 #define V_OS2X0(x) ((x) << S_OS2X0)
52178 #define G_OS2X0(x) (((x) >> S_OS2X0) & M_OS2X0)
52179 
52180 #define A_MAC_PORT_TX_LINKA_TRANSMIT_SEGMENT_1X_OVERRIDE 0x30d0
52181 
52182 #define S_OS1X7    14
52183 #define M_OS1X7    0x3U
52184 #define V_OS1X7(x) ((x) << S_OS1X7)
52185 #define G_OS1X7(x) (((x) >> S_OS1X7) & M_OS1X7)
52186 
52187 #define S_OS1X6    12
52188 #define M_OS1X6    0x3U
52189 #define V_OS1X6(x) ((x) << S_OS1X6)
52190 #define G_OS1X6(x) (((x) >> S_OS1X6) & M_OS1X6)
52191 
52192 #define S_OS1X5    10
52193 #define M_OS1X5    0x3U
52194 #define V_OS1X5(x) ((x) << S_OS1X5)
52195 #define G_OS1X5(x) (((x) >> S_OS1X5) & M_OS1X5)
52196 
52197 #define S_OS1X4    8
52198 #define M_OS1X4    0x3U
52199 #define V_OS1X4(x) ((x) << S_OS1X4)
52200 #define G_OS1X4(x) (((x) >> S_OS1X4) & M_OS1X4)
52201 
52202 #define S_OS1X3    6
52203 #define M_OS1X3    0x3U
52204 #define V_OS1X3(x) ((x) << S_OS1X3)
52205 #define G_OS1X3(x) (((x) >> S_OS1X3) & M_OS1X3)
52206 
52207 #define S_OS1X2    4
52208 #define M_OS1X2    0x3U
52209 #define V_OS1X2(x) ((x) << S_OS1X2)
52210 #define G_OS1X2(x) (((x) >> S_OS1X2) & M_OS1X2)
52211 
52212 #define S_OS1X1    2
52213 #define M_OS1X1    0x3U
52214 #define V_OS1X1(x) ((x) << S_OS1X1)
52215 #define G_OS1X1(x) (((x) >> S_OS1X1) & M_OS1X1)
52216 
52217 #define S_OS1X0    0
52218 #define M_OS1X0    0x3U
52219 #define V_OS1X0(x) ((x) << S_OS1X0)
52220 #define G_OS1X0(x) (((x) >> S_OS1X0) & M_OS1X0)
52221 
52222 #define A_MAC_PORT_TX_LINKA_TRANSMIT_TAP_SEGMENT_4X_TERMINATION_OVERRIDE 0x30d8
52223 
52224 #define S_OT4X    0
52225 #define M_OT4X    0xffU
52226 #define V_OT4X(x) ((x) << S_OT4X)
52227 #define G_OT4X(x) (((x) >> S_OT4X) & M_OT4X)
52228 
52229 #define A_MAC_PORT_TX_LINKA_TRANSMIT_TAP_SEGMENT_2X_TERMINATION_OVERRIDE 0x30dc
52230 
52231 #define S_OT2X    0
52232 #define M_OT2X    0xfU
52233 #define V_OT2X(x) ((x) << S_OT2X)
52234 #define G_OT2X(x) (((x) >> S_OT2X) & M_OT2X)
52235 
52236 #define A_MAC_PORT_TX_LINKA_TRANSMIT_TAP_SEGMENT_1X_TERMINATION_OVERRIDE 0x30e0
52237 
52238 #define S_OT1X    0
52239 #define M_OT1X    0xffU
52240 #define V_OT1X(x) ((x) << S_OT1X)
52241 #define G_OT1X(x) (((x) >> S_OT1X) & M_OT1X)
52242 
52243 #define A_MAC_PORT_TX_LINKA_TRANSMIT_MACRO_TEST_CONTROL_5 0x30ec
52244 
52245 #define S_ERRORP    15
52246 #define V_ERRORP(x) ((x) << S_ERRORP)
52247 #define F_ERRORP    V_ERRORP(1U)
52248 
52249 #define S_ERRORN    14
52250 #define V_ERRORN(x) ((x) << S_ERRORN)
52251 #define F_ERRORN    V_ERRORN(1U)
52252 
52253 #define S_TESTENA    13
52254 #define V_TESTENA(x) ((x) << S_TESTENA)
52255 #define F_TESTENA    V_TESTENA(1U)
52256 
52257 #define S_TUNEBIT    10
52258 #define M_TUNEBIT    0x7U
52259 #define V_TUNEBIT(x) ((x) << S_TUNEBIT)
52260 #define G_TUNEBIT(x) (((x) >> S_TUNEBIT) & M_TUNEBIT)
52261 
52262 #define S_DATAPOS    8
52263 #define M_DATAPOS    0x3U
52264 #define V_DATAPOS(x) ((x) << S_DATAPOS)
52265 #define G_DATAPOS(x) (((x) >> S_DATAPOS) & M_DATAPOS)
52266 
52267 #define S_SEGSEL    3
52268 #define M_SEGSEL    0x1fU
52269 #define V_SEGSEL(x) ((x) << S_SEGSEL)
52270 #define G_SEGSEL(x) (((x) >> S_SEGSEL) & M_SEGSEL)
52271 
52272 #define S_TAPSEL    1
52273 #define M_TAPSEL    0x3U
52274 #define V_TAPSEL(x) ((x) << S_TAPSEL)
52275 #define G_TAPSEL(x) (((x) >> S_TAPSEL) & M_TAPSEL)
52276 
52277 #define S_DATASIGN    0
52278 #define V_DATASIGN(x) ((x) << S_DATASIGN)
52279 #define F_DATASIGN    V_DATASIGN(1U)
52280 
52281 #define A_MAC_PORT_TX_LINKA_TRANSMIT_MACRO_TEST_CONTROL_4 0x30f0
52282 
52283 #define S_SDOVRDEN    8
52284 #define V_SDOVRDEN(x) ((x) << S_SDOVRDEN)
52285 #define F_SDOVRDEN    V_SDOVRDEN(1U)
52286 
52287 #define S_SDOVRD    0
52288 #define M_SDOVRD    0xffU
52289 #define V_SDOVRD(x) ((x) << S_SDOVRD)
52290 #define G_SDOVRD(x) (((x) >> S_SDOVRD) & M_SDOVRD)
52291 
52292 #define S_T6_SDOVRD    0
52293 #define M_T6_SDOVRD    0xffffU
52294 #define V_T6_SDOVRD(x) ((x) << S_T6_SDOVRD)
52295 #define G_T6_SDOVRD(x) (((x) >> S_T6_SDOVRD) & M_T6_SDOVRD)
52296 
52297 #define A_MAC_PORT_TX_LINKA_TRANSMIT_MACRO_TEST_CONTROL_3 0x30f4
52298 
52299 #define S_SLEWCODE    1
52300 #define M_SLEWCODE    0x3U
52301 #define V_SLEWCODE(x) ((x) << S_SLEWCODE)
52302 #define G_SLEWCODE(x) (((x) >> S_SLEWCODE) & M_SLEWCODE)
52303 
52304 #define S_ASEGEN    0
52305 #define V_ASEGEN(x) ((x) << S_ASEGEN)
52306 #define F_ASEGEN    V_ASEGEN(1U)
52307 
52308 #define S_WCNT    0
52309 #define M_WCNT    0x3ffU
52310 #define V_WCNT(x) ((x) << S_WCNT)
52311 #define G_WCNT(x) (((x) >> S_WCNT) & M_WCNT)
52312 
52313 #define A_MAC_PORT_TX_LINKA_TRANSMIT_MACRO_TEST_CONTROL_2 0x30f8
52314 
52315 #define S_AECMDVAL    14
52316 #define V_AECMDVAL(x) ((x) << S_AECMDVAL)
52317 #define F_AECMDVAL    V_AECMDVAL(1U)
52318 
52319 #define S_AECMD1312    12
52320 #define M_AECMD1312    0x3U
52321 #define V_AECMD1312(x) ((x) << S_AECMD1312)
52322 #define G_AECMD1312(x) (((x) >> S_AECMD1312) & M_AECMD1312)
52323 
52324 #define S_AECMD70    0
52325 #define M_AECMD70    0xffU
52326 #define V_AECMD70(x) ((x) << S_AECMD70)
52327 #define G_AECMD70(x) (((x) >> S_AECMD70) & M_AECMD70)
52328 
52329 #define A_MAC_PORT_TX_LINKA_TRANSMIT_MACRO_TEST_CONTROL_1 0x30fc
52330 
52331 #define S_C48DIVCTL    12
52332 #define M_C48DIVCTL    0x7U
52333 #define V_C48DIVCTL(x) ((x) << S_C48DIVCTL)
52334 #define G_C48DIVCTL(x) (((x) >> S_C48DIVCTL) & M_C48DIVCTL)
52335 
52336 #define S_RATEDIVCTL    9
52337 #define M_RATEDIVCTL    0x7U
52338 #define V_RATEDIVCTL(x) ((x) << S_RATEDIVCTL)
52339 #define G_RATEDIVCTL(x) (((x) >> S_RATEDIVCTL) & M_RATEDIVCTL)
52340 
52341 #define S_ANLGFLSH    8
52342 #define V_ANLGFLSH(x) ((x) << S_ANLGFLSH)
52343 #define F_ANLGFLSH    V_ANLGFLSH(1U)
52344 
52345 #define S_DCCTSTOUT    7
52346 #define V_DCCTSTOUT(x) ((x) << S_DCCTSTOUT)
52347 #define F_DCCTSTOUT    V_DCCTSTOUT(1U)
52348 
52349 #define S_BSOUT    6
52350 #define V_BSOUT(x) ((x) << S_BSOUT)
52351 #define F_BSOUT    V_BSOUT(1U)
52352 
52353 #define S_BSIN    5
52354 #define V_BSIN(x) ((x) << S_BSIN)
52355 #define F_BSIN    V_BSIN(1U)
52356 
52357 #define S_JTAGAMPL    3
52358 #define M_JTAGAMPL    0x3U
52359 #define V_JTAGAMPL(x) ((x) << S_JTAGAMPL)
52360 #define G_JTAGAMPL(x) (((x) >> S_JTAGAMPL) & M_JTAGAMPL)
52361 
52362 #define S_JTAGTS    2
52363 #define V_JTAGTS(x) ((x) << S_JTAGTS)
52364 #define F_JTAGTS    V_JTAGTS(1U)
52365 
52366 #define S_TS    1
52367 #define V_TS(x) ((x) << S_TS)
52368 #define F_TS    V_TS(1U)
52369 
52370 #define S_OBS    0
52371 #define V_OBS(x) ((x) << S_OBS)
52372 #define F_OBS    V_OBS(1U)
52373 
52374 #define S_T6_SDOVRDEN    15
52375 #define V_T6_SDOVRDEN(x) ((x) << S_T6_SDOVRDEN)
52376 #define F_T6_SDOVRDEN    V_T6_SDOVRDEN(1U)
52377 
52378 #define S_BSOUTN    7
52379 #define V_BSOUTN(x) ((x) << S_BSOUTN)
52380 #define F_BSOUTN    V_BSOUTN(1U)
52381 
52382 #define S_BSOUTP    6
52383 #define V_BSOUTP(x) ((x) << S_BSOUTP)
52384 #define F_BSOUTP    V_BSOUTP(1U)
52385 
52386 #define A_MAC_PORT_TX_LINKB_TRANSMIT_CONFIGURATION_MODE 0x3100
52387 
52388 #define S_T6_T5_TX_RXLOOP    5
52389 #define V_T6_T5_TX_RXLOOP(x) ((x) << S_T6_T5_TX_RXLOOP)
52390 #define F_T6_T5_TX_RXLOOP    V_T6_T5_TX_RXLOOP(1U)
52391 
52392 #define S_T6_T5_TX_BWSEL    2
52393 #define M_T6_T5_TX_BWSEL    0x3U
52394 #define V_T6_T5_TX_BWSEL(x) ((x) << S_T6_T5_TX_BWSEL)
52395 #define G_T6_T5_TX_BWSEL(x) (((x) >> S_T6_T5_TX_BWSEL) & M_T6_T5_TX_BWSEL)
52396 
52397 #define A_MAC_PORT_TX_LINKB_TRANSMIT_TEST_CONTROL 0x3104
52398 
52399 #define S_T6_ERROR    9
52400 #define V_T6_ERROR(x) ((x) << S_T6_ERROR)
52401 #define F_T6_ERROR    V_T6_ERROR(1U)
52402 
52403 #define A_MAC_PORT_TX_LINKB_TRANSMIT_COEFFICIENT_CONTROL 0x3108
52404 #define A_MAC_PORT_TX_LINKB_TRANSMIT_DRIVER_MODE_CONTROL 0x310c
52405 #define A_MAC_PORT_TX_LINKB_TRANSMIT_DRIVER_OVERRIDE_CONTROL 0x3110
52406 #define A_MAC_PORT_TX_LINKB_TRANSMIT_DCLK_ROTATOR_OVERRIDE 0x3114
52407 #define A_MAC_PORT_TX_LINKB_TRANSMIT_IMPEDANCE_CALIBRATION_OVERRIDE 0x3118
52408 
52409 #define S_T6_CALSSTN    8
52410 #define M_T6_CALSSTN    0x3fU
52411 #define V_T6_CALSSTN(x) ((x) << S_T6_CALSSTN)
52412 #define G_T6_CALSSTN(x) (((x) >> S_T6_CALSSTN) & M_T6_CALSSTN)
52413 
52414 #define S_T6_CALSSTP    0
52415 #define M_T6_CALSSTP    0x3fU
52416 #define V_T6_CALSSTP(x) ((x) << S_T6_CALSSTP)
52417 #define G_T6_CALSSTP(x) (((x) >> S_T6_CALSSTP) & M_T6_CALSSTP)
52418 
52419 #define A_MAC_PORT_TX_LINKB_TRANSMIT_DCLK_DRIFT_TOLERANCE 0x311c
52420 
52421 #define S_T6_DRTOL    2
52422 #define M_T6_DRTOL    0x7U
52423 #define V_T6_DRTOL(x) ((x) << S_T6_DRTOL)
52424 #define G_T6_DRTOL(x) (((x) >> S_T6_DRTOL) & M_T6_DRTOL)
52425 
52426 #define A_MAC_PORT_TX_LINKB_TRANSMIT_TAP_0_COEFFICIENT 0x3120
52427 
52428 #define S_T6_NXTT0    0
52429 #define M_T6_NXTT0    0x3fU
52430 #define V_T6_NXTT0(x) ((x) << S_T6_NXTT0)
52431 #define G_T6_NXTT0(x) (((x) >> S_T6_NXTT0) & M_T6_NXTT0)
52432 
52433 #define A_MAC_PORT_TX_LINKB_TRANSMIT_TAP_1_COEFFICIENT 0x3124
52434 #define A_MAC_PORT_TX_LINKB_TRANSMIT_TAP_2_COEFFICIENT 0x3128
52435 
52436 #define S_T6_NXTT2    0
52437 #define M_T6_NXTT2    0x3fU
52438 #define V_T6_NXTT2(x) ((x) << S_T6_NXTT2)
52439 #define G_T6_NXTT2(x) (((x) >> S_T6_NXTT2) & M_T6_NXTT2)
52440 
52441 #define A_MAC_PORT_TX_LINKB_TRANSMIT_TAP_3_COEFFICIENT 0x312c
52442 #define A_MAC_PORT_TX_LINKB_TRANSMIT_AMPLITUDE 0x3130
52443 #define A_MAC_PORT_TX_LINKB_TRANSMIT_POLARITY 0x3134
52444 
52445 #define S_T6_NXTPOL    0
52446 #define M_T6_NXTPOL    0xfU
52447 #define V_T6_NXTPOL(x) ((x) << S_T6_NXTPOL)
52448 #define G_T6_NXTPOL(x) (((x) >> S_T6_NXTPOL) & M_T6_NXTPOL)
52449 
52450 #define A_MAC_PORT_TX_LINKB_TRANSMIT_802_3AP_ADAPTIVE_EQUALIZATION_COMMAND 0x3138
52451 
52452 #define S_T6_C0UPDT    6
52453 #define M_T6_C0UPDT    0x3U
52454 #define V_T6_C0UPDT(x) ((x) << S_T6_C0UPDT)
52455 #define G_T6_C0UPDT(x) (((x) >> S_T6_C0UPDT) & M_T6_C0UPDT)
52456 
52457 #define S_T6_C2UPDT    2
52458 #define M_T6_C2UPDT    0x3U
52459 #define V_T6_C2UPDT(x) ((x) << S_T6_C2UPDT)
52460 #define G_T6_C2UPDT(x) (((x) >> S_T6_C2UPDT) & M_T6_C2UPDT)
52461 
52462 #define S_T6_C1UPDT    0
52463 #define M_T6_C1UPDT    0x3U
52464 #define V_T6_C1UPDT(x) ((x) << S_T6_C1UPDT)
52465 #define G_T6_C1UPDT(x) (((x) >> S_T6_C1UPDT) & M_T6_C1UPDT)
52466 
52467 #define A_MAC_PORT_TX_LINKB_TRANSMIT_802_3AP_ADAPTIVE_EQUALIZATION_STATUS 0x313c
52468 
52469 #define S_T6_C0STAT    6
52470 #define M_T6_C0STAT    0x3U
52471 #define V_T6_C0STAT(x) ((x) << S_T6_C0STAT)
52472 #define G_T6_C0STAT(x) (((x) >> S_T6_C0STAT) & M_T6_C0STAT)
52473 
52474 #define S_T6_C2STAT    2
52475 #define M_T6_C2STAT    0x3U
52476 #define V_T6_C2STAT(x) ((x) << S_T6_C2STAT)
52477 #define G_T6_C2STAT(x) (((x) >> S_T6_C2STAT) & M_T6_C2STAT)
52478 
52479 #define S_T6_C1STAT    0
52480 #define M_T6_C1STAT    0x3U
52481 #define V_T6_C1STAT(x) ((x) << S_T6_C1STAT)
52482 #define G_T6_C1STAT(x) (((x) >> S_T6_C1STAT) & M_T6_C1STAT)
52483 
52484 #define A_MAC_PORT_TX_LINKB_TRANSMIT_TAP_0_COEFFICIENT_OVERRIDE 0x3140
52485 #define A_MAC_PORT_TX_LINKB_TRANSMIT_AE_TAP_0_COEFFICIENT_OVERRIDE 0x3140
52486 #define A_MAC_PORT_TX_LINKB_TRANSMIT_TAP_1_COEFFICIENT_OVERRIDE 0x3144
52487 #define A_MAC_PORT_TX_LINKB_TRANSMIT_AE_TAP_1_COEFFICIENT_OVERRIDE 0x3144
52488 #define A_MAC_PORT_TX_LINKB_TRANSMIT_TAP_2_COEFFICIENT_OVERRIDE 0x3148
52489 #define A_MAC_PORT_TX_LINKB_TRANSMIT_AE_TAP_2_COEFFICIENT_OVERRIDE 0x3148
52490 #define A_MAC_PORT_TX_LINKB_TRANSMIT_AE_TAP_3_COEFFICIENT_OVERRIDE 0x314c
52491 #define A_MAC_PORT_TX_LINKB_TRANSMIT_APPLIED_TUNE_REGISTER 0x3150
52492 #define A_MAC_PORT_TX_LINKB_TRANSMIT_ANALOG_DIAGNOSTICS_REGISTER 0x3158
52493 #define A_MAC_PORT_TX_LINKB_TRANSMIT_TAP_0_COEFFICIENT_APPLIED 0x3160
52494 #define A_MAC_PORT_TX_LINKB_TRANSMIT_4X_SEGMENT_APPLIED 0x3160
52495 #define A_MAC_PORT_TX_LINKB_TRANSMIT_TAP_1_COEFFICIENT_APPLIED 0x3164
52496 #define A_MAC_PORT_TX_LINKB_TRANSMIT_2X_SEGMENT_APPLIED 0x3164
52497 #define A_MAC_PORT_TX_LINKB_TRANSMIT_TAP_2_COEFFICIENT_APPLIED 0x3168
52498 #define A_MAC_PORT_TX_LINKB_TRANSMIT_1X_SEGMENT_APPLIED 0x3168
52499 #define A_MAC_PORT_TX_LINKB_TRANSMIT_SEGMENT_4X_TERMINATION_APPLIED 0x316c
52500 #define A_MAC_PORT_TX_LINKB_TRANSMIT_SEGMENT_DISABLE_APPLIED_1 0x3170
52501 #define A_MAC_PORT_TX_LINKB_TRANSMIT_SEGMENT_2X1X_TERMINATION_APPLIED 0x3170
52502 #define A_MAC_PORT_TX_LINKB_TRANSMIT_SEGMENT_DISABLE_APPLIED_2 0x3174
52503 #define A_MAC_PORT_TX_LINKB_TRANSMIT_TAP_SIGN_APPLIED_REGISTER 0x3174
52504 #define A_MAC_PORT_TX_LINKB_TRANSMIT_EXTENDED_ADDRESS_DATA 0x3178
52505 #define A_MAC_PORT_TX_LINKB_TRANSMIT_EXTENDED_ADDRESS_ADDR 0x317c
52506 
52507 #define S_T6_XADDR    1
52508 #define M_T6_XADDR    0x1fU
52509 #define V_T6_XADDR(x) ((x) << S_T6_XADDR)
52510 #define G_T6_XADDR(x) (((x) >> S_T6_XADDR) & M_T6_XADDR)
52511 
52512 #define A_MAC_PORT_TX_LINKB_TRANSMIT_PATTERN_BUFFER_BYTES_1_0 0x3180
52513 #define A_MAC_PORT_TX_LINKB_TRANSMIT_PATTERN_BUFFER_BYTES_3_2 0x3184
52514 #define A_MAC_PORT_TX_LINKB_TRANSMIT_PATTERN_BUFFER_BYTE_4 0x3188
52515 #define A_MAC_PORT_TX_LINKB_TRANSMIT_PATTERN_BUFFER_BYTES_5_4 0x3188
52516 #define A_MAC_PORT_TX_LINKB_TRANSMIT_DCC_CONTROL 0x318c
52517 #define A_MAC_PORT_TX_LINKB_TRANSMIT_PATTERN_BUFFER_BYTES_7_6 0x318c
52518 #define A_MAC_PORT_TX_LINKB_TRANSMIT_DCC_OVERRIDE 0x3190
52519 #define A_MAC_PORT_TX_LINKB_TRANSMIT_DCC_APPLIED 0x3194
52520 #define A_MAC_PORT_TX_LINKB_TRANSMIT_DCC_TIME_OUT 0x3198
52521 #define A_MAC_PORT_TX_LINKB_TRANSMIT_802_3AZ_CONTROL 0x319c
52522 #define A_T6_MAC_PORT_TX_LINKB_TRANSMIT_DCC_CONTROL 0x31a0
52523 
52524 #define S_T6_DCCTIMEEN    13
52525 #define M_T6_DCCTIMEEN    0x3U
52526 #define V_T6_DCCTIMEEN(x) ((x) << S_T6_DCCTIMEEN)
52527 #define G_T6_DCCTIMEEN(x) (((x) >> S_T6_DCCTIMEEN) & M_T6_DCCTIMEEN)
52528 
52529 #define S_T6_DCCLOCK    11
52530 #define M_T6_DCCLOCK    0x3U
52531 #define V_T6_DCCLOCK(x) ((x) << S_T6_DCCLOCK)
52532 #define G_T6_DCCLOCK(x) (((x) >> S_T6_DCCLOCK) & M_T6_DCCLOCK)
52533 
52534 #define S_T6_DCCOFFSET    8
52535 #define M_T6_DCCOFFSET    0x7U
52536 #define V_T6_DCCOFFSET(x) ((x) << S_T6_DCCOFFSET)
52537 #define G_T6_DCCOFFSET(x) (((x) >> S_T6_DCCOFFSET) & M_T6_DCCOFFSET)
52538 
52539 #define S_TX_LINKB_DCCSTEP_CTL    6
52540 #define M_TX_LINKB_DCCSTEP_CTL    0x3U
52541 #define V_TX_LINKB_DCCSTEP_CTL(x) ((x) << S_TX_LINKB_DCCSTEP_CTL)
52542 #define G_TX_LINKB_DCCSTEP_CTL(x) (((x) >> S_TX_LINKB_DCCSTEP_CTL) & M_TX_LINKB_DCCSTEP_CTL)
52543 
52544 #define A_T6_MAC_PORT_TX_LINKB_TRANSMIT_DCC_OVERRIDE 0x31a4
52545 #define A_T6_MAC_PORT_TX_LINKB_TRANSMIT_DCC_APPLIED 0x31a8
52546 #define A_T6_MAC_PORT_TX_LINKB_TRANSMIT_DCC_TIME_OUT 0x31ac
52547 #define A_MAC_PORT_TX_LINKB_TRANSMIT_TAP_SIGN_OVERRIDE 0x31c0
52548 #define A_MAC_PORT_TX_LINKB_TRANSMIT_SEGMENT_4X_OVERRIDE 0x31c8
52549 #define A_MAC_PORT_TX_LINKB_TRANSMIT_SEGMENT_2X_OVERRIDE 0x31cc
52550 #define A_MAC_PORT_TX_LINKB_TRANSMIT_SEGMENT_1X_OVERRIDE 0x31d0
52551 #define A_MAC_PORT_TX_LINKB_TRANSMIT_TAP_SEGMENT_4X_TERMINATION_OVERRIDE 0x31d8
52552 #define A_MAC_PORT_TX_LINKB_TRANSMIT_TAP_SEGMENT_2X_TERMINATION_OVERRIDE 0x31dc
52553 #define A_MAC_PORT_TX_LINKB_TRANSMIT_TAP_SEGMENT_1X_TERMINATION_OVERRIDE 0x31e0
52554 #define A_MAC_PORT_TX_LINKB_TRANSMIT_MACRO_TEST_CONTROL_5 0x31ec
52555 #define A_MAC_PORT_TX_LINKB_TRANSMIT_MACRO_TEST_CONTROL_4 0x31f0
52556 
52557 #define S_T6_SDOVRD    0
52558 #define M_T6_SDOVRD    0xffffU
52559 #define V_T6_SDOVRD(x) ((x) << S_T6_SDOVRD)
52560 #define G_T6_SDOVRD(x) (((x) >> S_T6_SDOVRD) & M_T6_SDOVRD)
52561 
52562 #define A_MAC_PORT_TX_LINKB_TRANSMIT_MACRO_TEST_CONTROL_3 0x31f4
52563 #define A_MAC_PORT_TX_LINKB_TRANSMIT_MACRO_TEST_CONTROL_2 0x31f8
52564 #define A_MAC_PORT_TX_LINKB_TRANSMIT_MACRO_TEST_CONTROL_1 0x31fc
52565 
52566 #define S_T6_SDOVRDEN    15
52567 #define V_T6_SDOVRDEN(x) ((x) << S_T6_SDOVRDEN)
52568 #define F_T6_SDOVRDEN    V_T6_SDOVRDEN(1U)
52569 
52570 #define A_MAC_PORT_RX_LINKA_RECEIVER_CONFIGURATION_MODE 0x3200
52571 
52572 #define S_T5_RX_LINKEN    15
52573 #define V_T5_RX_LINKEN(x) ((x) << S_T5_RX_LINKEN)
52574 #define F_T5_RX_LINKEN    V_T5_RX_LINKEN(1U)
52575 
52576 #define S_T5_RX_LINKRST    14
52577 #define V_T5_RX_LINKRST(x) ((x) << S_T5_RX_LINKRST)
52578 #define F_T5_RX_LINKRST    V_T5_RX_LINKRST(1U)
52579 
52580 #define S_T5_RX_CFGWRT    13
52581 #define V_T5_RX_CFGWRT(x) ((x) << S_T5_RX_CFGWRT)
52582 #define F_T5_RX_CFGWRT    V_T5_RX_CFGWRT(1U)
52583 
52584 #define S_T5_RX_CFGPTR    11
52585 #define M_T5_RX_CFGPTR    0x3U
52586 #define V_T5_RX_CFGPTR(x) ((x) << S_T5_RX_CFGPTR)
52587 #define G_T5_RX_CFGPTR(x) (((x) >> S_T5_RX_CFGPTR) & M_T5_RX_CFGPTR)
52588 
52589 #define S_T5_RX_CFGEXT    10
52590 #define V_T5_RX_CFGEXT(x) ((x) << S_T5_RX_CFGEXT)
52591 #define F_T5_RX_CFGEXT    V_T5_RX_CFGEXT(1U)
52592 
52593 #define S_T5_RX_CFGACT    9
52594 #define V_T5_RX_CFGACT(x) ((x) << S_T5_RX_CFGACT)
52595 #define F_T5_RX_CFGACT    V_T5_RX_CFGACT(1U)
52596 
52597 #define S_T5_RX_AUXCLK    8
52598 #define V_T5_RX_AUXCLK(x) ((x) << S_T5_RX_AUXCLK)
52599 #define F_T5_RX_AUXCLK    V_T5_RX_AUXCLK(1U)
52600 
52601 #define S_T5_RX_PLLSEL    6
52602 #define M_T5_RX_PLLSEL    0x3U
52603 #define V_T5_RX_PLLSEL(x) ((x) << S_T5_RX_PLLSEL)
52604 #define G_T5_RX_PLLSEL(x) (((x) >> S_T5_RX_PLLSEL) & M_T5_RX_PLLSEL)
52605 
52606 #define S_T5_RX_DMSEL    4
52607 #define M_T5_RX_DMSEL    0x3U
52608 #define V_T5_RX_DMSEL(x) ((x) << S_T5_RX_DMSEL)
52609 #define G_T5_RX_DMSEL(x) (((x) >> S_T5_RX_DMSEL) & M_T5_RX_DMSEL)
52610 
52611 #define S_T5_RX_BWSEL    2
52612 #define M_T5_RX_BWSEL    0x3U
52613 #define V_T5_RX_BWSEL(x) ((x) << S_T5_RX_BWSEL)
52614 #define G_T5_RX_BWSEL(x) (((x) >> S_T5_RX_BWSEL) & M_T5_RX_BWSEL)
52615 
52616 #define S_T5_RX_RTSEL    0
52617 #define M_T5_RX_RTSEL    0x3U
52618 #define V_T5_RX_RTSEL(x) ((x) << S_T5_RX_RTSEL)
52619 #define G_T5_RX_RTSEL(x) (((x) >> S_T5_RX_RTSEL) & M_T5_RX_RTSEL)
52620 
52621 #define S_T5_RX_MODE8023AZ    8
52622 #define V_T5_RX_MODE8023AZ(x) ((x) << S_T5_RX_MODE8023AZ)
52623 #define F_T5_RX_MODE8023AZ    V_T5_RX_MODE8023AZ(1U)
52624 
52625 #define A_MAC_PORT_RX_LINKA_RECEIVER_TEST_CONTROL 0x3204
52626 
52627 #define S_FERRST    10
52628 #define V_FERRST(x) ((x) << S_FERRST)
52629 #define F_FERRST    V_FERRST(1U)
52630 
52631 #define S_ERRST    9
52632 #define V_ERRST(x) ((x) << S_ERRST)
52633 #define F_ERRST    V_ERRST(1U)
52634 
52635 #define S_SYNCST    8
52636 #define V_SYNCST(x) ((x) << S_SYNCST)
52637 #define F_SYNCST    V_SYNCST(1U)
52638 
52639 #define S_WRPSM    7
52640 #define V_WRPSM(x) ((x) << S_WRPSM)
52641 #define F_WRPSM    V_WRPSM(1U)
52642 
52643 #define S_WPLPEN    6
52644 #define V_WPLPEN(x) ((x) << S_WPLPEN)
52645 #define F_WPLPEN    V_WPLPEN(1U)
52646 
52647 #define S_WRPMD    5
52648 #define V_WRPMD(x) ((x) << S_WRPMD)
52649 #define F_WRPMD    V_WRPMD(1U)
52650 
52651 #define S_PATSEL    0
52652 #define M_PATSEL    0x7U
52653 #define V_PATSEL(x) ((x) << S_PATSEL)
52654 #define G_PATSEL(x) (((x) >> S_PATSEL) & M_PATSEL)
52655 
52656 #define S_APLYDCD    15
52657 #define V_APLYDCD(x) ((x) << S_APLYDCD)
52658 #define F_APLYDCD    V_APLYDCD(1U)
52659 
52660 #define S_PPOL    13
52661 #define M_PPOL    0x3U
52662 #define V_PPOL(x) ((x) << S_PPOL)
52663 #define G_PPOL(x) (((x) >> S_PPOL) & M_PPOL)
52664 
52665 #define S_PCLKSEL    11
52666 #define M_PCLKSEL    0x3U
52667 #define V_PCLKSEL(x) ((x) << S_PCLKSEL)
52668 #define G_PCLKSEL(x) (((x) >> S_PCLKSEL) & M_PCLKSEL)
52669 
52670 #define A_MAC_PORT_RX_LINKA_PHASE_ROTATOR_CONTROL 0x3208
52671 
52672 #define S_RSTUCK    3
52673 #define V_RSTUCK(x) ((x) << S_RSTUCK)
52674 #define F_RSTUCK    V_RSTUCK(1U)
52675 
52676 #define S_FRZFW    2
52677 #define V_FRZFW(x) ((x) << S_FRZFW)
52678 #define F_FRZFW    V_FRZFW(1U)
52679 
52680 #define S_RSTFW    1
52681 #define V_RSTFW(x) ((x) << S_RSTFW)
52682 #define F_RSTFW    V_RSTFW(1U)
52683 
52684 #define S_SSCEN    0
52685 #define V_SSCEN(x) ((x) << S_SSCEN)
52686 #define F_SSCEN    V_SSCEN(1U)
52687 
52688 #define A_MAC_PORT_RX_LINKA_PHASE_ROTATOR_OFFSET_CONTROL 0x320c
52689 
52690 #define S_H1ANOFST    12
52691 #define M_H1ANOFST    0xfU
52692 #define V_H1ANOFST(x) ((x) << S_H1ANOFST)
52693 #define G_H1ANOFST(x) (((x) >> S_H1ANOFST) & M_H1ANOFST)
52694 
52695 #define S_T6_TMSCAL    8
52696 #define M_T6_TMSCAL    0x3U
52697 #define V_T6_TMSCAL(x) ((x) << S_T6_TMSCAL)
52698 #define G_T6_TMSCAL(x) (((x) >> S_T6_TMSCAL) & M_T6_TMSCAL)
52699 
52700 #define S_T6_APADJ    7
52701 #define V_T6_APADJ(x) ((x) << S_T6_APADJ)
52702 #define F_T6_APADJ    V_T6_APADJ(1U)
52703 
52704 #define S_T6_RSEL    6
52705 #define V_T6_RSEL(x) ((x) << S_T6_RSEL)
52706 #define F_T6_RSEL    V_T6_RSEL(1U)
52707 
52708 #define S_T6_PHOFFS    0
52709 #define M_T6_PHOFFS    0x3fU
52710 #define V_T6_PHOFFS(x) ((x) << S_T6_PHOFFS)
52711 #define G_T6_PHOFFS(x) (((x) >> S_T6_PHOFFS) & M_T6_PHOFFS)
52712 
52713 #define A_MAC_PORT_RX_LINKA_PHASE_ROTATOR_POSITION_1 0x3210
52714 
52715 #define S_ROT00    0
52716 #define M_ROT00    0x3fU
52717 #define V_ROT00(x) ((x) << S_ROT00)
52718 #define G_ROT00(x) (((x) >> S_ROT00) & M_ROT00)
52719 
52720 #define S_ROTA    8
52721 #define M_ROTA    0x3fU
52722 #define V_ROTA(x) ((x) << S_ROTA)
52723 #define G_ROTA(x) (((x) >> S_ROTA) & M_ROTA)
52724 
52725 #define S_ROTD    0
52726 #define M_ROTD    0x3fU
52727 #define V_ROTD(x) ((x) << S_ROTD)
52728 #define G_ROTD(x) (((x) >> S_ROTD) & M_ROTD)
52729 
52730 #define A_MAC_PORT_RX_LINKA_PHASE_ROTATOR_POSITION_2 0x3214
52731 
52732 #define S_FREQFW    8
52733 #define M_FREQFW    0xffU
52734 #define V_FREQFW(x) ((x) << S_FREQFW)
52735 #define G_FREQFW(x) (((x) >> S_FREQFW) & M_FREQFW)
52736 
52737 #define S_FWSNAP    7
52738 #define V_FWSNAP(x) ((x) << S_FWSNAP)
52739 #define F_FWSNAP    V_FWSNAP(1U)
52740 
52741 #define S_ROTE    0
52742 #define M_ROTE    0x3fU
52743 #define V_ROTE(x) ((x) << S_ROTE)
52744 #define G_ROTE(x) (((x) >> S_ROTE) & M_ROTE)
52745 
52746 #define A_MAC_PORT_RX_LINKA_PHASE_ROTATOR_STATIC_PHASE_OFFSET_1 0x3218
52747 
52748 #define S_RAOFFF    8
52749 #define M_RAOFFF    0xfU
52750 #define V_RAOFFF(x) ((x) << S_RAOFFF)
52751 #define G_RAOFFF(x) (((x) >> S_RAOFFF) & M_RAOFFF)
52752 
52753 #define S_RAOFF    0
52754 #define M_RAOFF    0x1fU
52755 #define V_RAOFF(x) ((x) << S_RAOFF)
52756 #define G_RAOFF(x) (((x) >> S_RAOFF) & M_RAOFF)
52757 
52758 #define A_MAC_PORT_RX_LINKA_PHASE_ROTATOR_STATIC_PHASE_OFFSET_2 0x321c
52759 
52760 #define S_RBOOFF    10
52761 #define M_RBOOFF    0x1fU
52762 #define V_RBOOFF(x) ((x) << S_RBOOFF)
52763 #define G_RBOOFF(x) (((x) >> S_RBOOFF) & M_RBOOFF)
52764 
52765 #define S_RBEOFF    5
52766 #define M_RBEOFF    0x1fU
52767 #define V_RBEOFF(x) ((x) << S_RBEOFF)
52768 #define G_RBEOFF(x) (((x) >> S_RBEOFF) & M_RBEOFF)
52769 
52770 #define A_MAC_PORT_RX_LINKA_DFE_CONTROL 0x3220
52771 
52772 #define S_T6_SPIFMT    8
52773 #define M_T6_SPIFMT    0xfU
52774 #define V_T6_SPIFMT(x) ((x) << S_T6_SPIFMT)
52775 #define G_T6_SPIFMT(x) (((x) >> S_T6_SPIFMT) & M_T6_SPIFMT)
52776 
52777 #define A_MAC_PORT_RX_LINKA_DFE_SAMPLE_SNAPSHOT_1 0x3224
52778 
52779 #define S_T5BYTE1    8
52780 #define M_T5BYTE1    0xffU
52781 #define V_T5BYTE1(x) ((x) << S_T5BYTE1)
52782 #define G_T5BYTE1(x) (((x) >> S_T5BYTE1) & M_T5BYTE1)
52783 
52784 #define S_T5BYTE0    0
52785 #define M_T5BYTE0    0xffU
52786 #define V_T5BYTE0(x) ((x) << S_T5BYTE0)
52787 #define G_T5BYTE0(x) (((x) >> S_T5BYTE0) & M_T5BYTE0)
52788 
52789 #define A_MAC_PORT_RX_LINKA_DFE_SAMPLE_SNAPSHOT_2 0x3228
52790 
52791 #define S_T5_RX_SMODE    8
52792 #define M_T5_RX_SMODE    0x7U
52793 #define V_T5_RX_SMODE(x) ((x) << S_T5_RX_SMODE)
52794 #define G_T5_RX_SMODE(x) (((x) >> S_T5_RX_SMODE) & M_T5_RX_SMODE)
52795 
52796 #define S_T5_RX_ADCORR    7
52797 #define V_T5_RX_ADCORR(x) ((x) << S_T5_RX_ADCORR)
52798 #define F_T5_RX_ADCORR    V_T5_RX_ADCORR(1U)
52799 
52800 #define S_T5_RX_TRAINEN    6
52801 #define V_T5_RX_TRAINEN(x) ((x) << S_T5_RX_TRAINEN)
52802 #define F_T5_RX_TRAINEN    V_T5_RX_TRAINEN(1U)
52803 
52804 #define S_T5_RX_ASAMPQ    3
52805 #define M_T5_RX_ASAMPQ    0x7U
52806 #define V_T5_RX_ASAMPQ(x) ((x) << S_T5_RX_ASAMPQ)
52807 #define G_T5_RX_ASAMPQ(x) (((x) >> S_T5_RX_ASAMPQ) & M_T5_RX_ASAMPQ)
52808 
52809 #define S_T5_RX_ASAMP    0
52810 #define M_T5_RX_ASAMP    0x7U
52811 #define V_T5_RX_ASAMP(x) ((x) << S_T5_RX_ASAMP)
52812 #define G_T5_RX_ASAMP(x) (((x) >> S_T5_RX_ASAMP) & M_T5_RX_ASAMP)
52813 
52814 #define S_REQWOV    15
52815 #define V_REQWOV(x) ((x) << S_REQWOV)
52816 #define F_REQWOV    V_REQWOV(1U)
52817 
52818 #define S_RASEL    11
52819 #define M_RASEL    0x7U
52820 #define V_RASEL(x) ((x) << S_RASEL)
52821 #define G_RASEL(x) (((x) >> S_RASEL) & M_RASEL)
52822 
52823 #define A_MAC_PORT_RX_LINKA_RECEIVER_VGA_CONTROL_1 0x322c
52824 
52825 #define S_T6_WRAPSEL    15
52826 #define V_T6_WRAPSEL(x) ((x) << S_T6_WRAPSEL)
52827 #define F_T6_WRAPSEL    V_T6_WRAPSEL(1U)
52828 
52829 #define S_ACTL    14
52830 #define V_ACTL(x) ((x) << S_ACTL)
52831 #define F_ACTL    V_ACTL(1U)
52832 
52833 #define S_T6_PEAK    9
52834 #define M_T6_PEAK    0x1fU
52835 #define V_T6_PEAK(x) ((x) << S_T6_PEAK)
52836 #define G_T6_PEAK(x) (((x) >> S_T6_PEAK) & M_T6_PEAK)
52837 
52838 #define A_MAC_PORT_RX_LINKA_RECEIVER_VGA_CONTROL_2 0x3230
52839 
52840 #define S_T5SHORTV    10
52841 #define V_T5SHORTV(x) ((x) << S_T5SHORTV)
52842 #define F_T5SHORTV    V_T5SHORTV(1U)
52843 
52844 #define S_T5VGAIN    0
52845 #define M_T5VGAIN    0x1fU
52846 #define V_T5VGAIN(x) ((x) << S_T5VGAIN)
52847 #define G_T5VGAIN(x) (((x) >> S_T5VGAIN) & M_T5VGAIN)
52848 
52849 #define S_FVOFFSKP    15
52850 #define V_FVOFFSKP(x) ((x) << S_FVOFFSKP)
52851 #define F_FVOFFSKP    V_FVOFFSKP(1U)
52852 
52853 #define S_FGAINCHK    14
52854 #define V_FGAINCHK(x) ((x) << S_FGAINCHK)
52855 #define F_FGAINCHK    V_FGAINCHK(1U)
52856 
52857 #define S_FH1ACAL    13
52858 #define V_FH1ACAL(x) ((x) << S_FH1ACAL)
52859 #define F_FH1ACAL    V_FH1ACAL(1U)
52860 
52861 #define S_FH1AFLTR    11
52862 #define M_FH1AFLTR    0x3U
52863 #define V_FH1AFLTR(x) ((x) << S_FH1AFLTR)
52864 #define G_FH1AFLTR(x) (((x) >> S_FH1AFLTR) & M_FH1AFLTR)
52865 
52866 #define S_WGAIN    8
52867 #define M_WGAIN    0x3U
52868 #define V_WGAIN(x) ((x) << S_WGAIN)
52869 #define G_WGAIN(x) (((x) >> S_WGAIN) & M_WGAIN)
52870 
52871 #define S_GAIN_STAT    7
52872 #define V_GAIN_STAT(x) ((x) << S_GAIN_STAT)
52873 #define F_GAIN_STAT    V_GAIN_STAT(1U)
52874 
52875 #define S_T6_T5VGAIN    0
52876 #define M_T6_T5VGAIN    0x7fU
52877 #define V_T6_T5VGAIN(x) ((x) << S_T6_T5VGAIN)
52878 #define G_T6_T5VGAIN(x) (((x) >> S_T6_T5VGAIN) & M_T6_T5VGAIN)
52879 
52880 #define A_MAC_PORT_RX_LINKA_RECEIVER_VGA_CONTROL_3 0x3234
52881 #define A_MAC_PORT_RX_LINKA_RECEIVER_DQCC_CONTROL_1 0x3238
52882 
52883 #define S_IQSEP    10
52884 #define M_IQSEP    0x1fU
52885 #define V_IQSEP(x) ((x) << S_IQSEP)
52886 #define G_IQSEP(x) (((x) >> S_IQSEP) & M_IQSEP)
52887 
52888 #define S_DUTYQ    5
52889 #define M_DUTYQ    0x1fU
52890 #define V_DUTYQ(x) ((x) << S_DUTYQ)
52891 #define G_DUTYQ(x) (((x) >> S_DUTYQ) & M_DUTYQ)
52892 
52893 #define S_DUTYI    0
52894 #define M_DUTYI    0x1fU
52895 #define V_DUTYI(x) ((x) << S_DUTYI)
52896 #define G_DUTYI(x) (((x) >> S_DUTYI) & M_DUTYI)
52897 
52898 #define A_MAC_PORT_RX_LINKA_RECEIVER_POWER_MANAGEMENT_CONTROL 0x3238
52899 
52900 #define S_PMCFG    6
52901 #define M_PMCFG    0x3U
52902 #define V_PMCFG(x) ((x) << S_PMCFG)
52903 #define G_PMCFG(x) (((x) >> S_PMCFG) & M_PMCFG)
52904 
52905 #define S_PMOFFTIME    0
52906 #define M_PMOFFTIME    0x3fU
52907 #define V_PMOFFTIME(x) ((x) << S_PMOFFTIME)
52908 #define G_PMOFFTIME(x) (((x) >> S_PMOFFTIME) & M_PMOFFTIME)
52909 
52910 #define A_MAC_PORT_RX_LINKA_RECEIVER_IQAMP_CONTROL_1 0x323c
52911 
52912 #define S_SELI    9
52913 #define V_SELI(x) ((x) << S_SELI)
52914 #define F_SELI    V_SELI(1U)
52915 
52916 #define S_SERVREF    5
52917 #define M_SERVREF    0x7U
52918 #define V_SERVREF(x) ((x) << S_SERVREF)
52919 #define G_SERVREF(x) (((x) >> S_SERVREF) & M_SERVREF)
52920 
52921 #define S_IQAMP    0
52922 #define M_IQAMP    0x1fU
52923 #define V_IQAMP(x) ((x) << S_IQAMP)
52924 #define G_IQAMP(x) (((x) >> S_IQAMP) & M_IQAMP)
52925 
52926 #define A_MAC_PORT_RX_LINKA_RECEIVER_DQCC_CONTROL_3 0x3240
52927 
52928 #define S_DTHR    8
52929 #define M_DTHR    0x3fU
52930 #define V_DTHR(x) ((x) << S_DTHR)
52931 #define G_DTHR(x) (((x) >> S_DTHR) & M_DTHR)
52932 
52933 #define S_SNUL    0
52934 #define M_SNUL    0x1fU
52935 #define V_SNUL(x) ((x) << S_SNUL)
52936 #define G_SNUL(x) (((x) >> S_SNUL) & M_SNUL)
52937 
52938 #define A_MAC_PORT_RX_LINKA_RECEIVER_IQAMP_CONTROL_2 0x3240
52939 #define A_MAC_PORT_RX_LINKA_RECEIVER_DACAP_AND_DACAN_SELECTION 0x3244
52940 
52941 #define S_SAVEADAC    8
52942 #define V_SAVEADAC(x) ((x) << S_SAVEADAC)
52943 #define F_SAVEADAC    V_SAVEADAC(1U)
52944 
52945 #define S_LOAD2    7
52946 #define V_LOAD2(x) ((x) << S_LOAD2)
52947 #define F_LOAD2    V_LOAD2(1U)
52948 
52949 #define S_LOAD1    6
52950 #define V_LOAD1(x) ((x) << S_LOAD1)
52951 #define F_LOAD1    V_LOAD1(1U)
52952 
52953 #define S_WRTACC2    5
52954 #define V_WRTACC2(x) ((x) << S_WRTACC2)
52955 #define F_WRTACC2    V_WRTACC2(1U)
52956 
52957 #define S_WRTACC1    4
52958 #define V_WRTACC1(x) ((x) << S_WRTACC1)
52959 #define F_WRTACC1    V_WRTACC1(1U)
52960 
52961 #define S_SELAPAN    3
52962 #define V_SELAPAN(x) ((x) << S_SELAPAN)
52963 #define F_SELAPAN    V_SELAPAN(1U)
52964 
52965 #define S_DASEL    0
52966 #define M_DASEL    0x7U
52967 #define V_DASEL(x) ((x) << S_DASEL)
52968 #define G_DASEL(x) (((x) >> S_DASEL) & M_DASEL)
52969 
52970 #define A_MAC_PORT_RX_LINKA_RECEIVER_DACAP_AND_DACAN 0x3248
52971 #define A_MAC_PORT_RX_LINKA_RECEIVER_DACA_MIN_AND_DACAZ 0x324c
52972 #define A_MAC_PORT_RX_LINKA_RECEIVER_DACA_MIN 0x324c
52973 #define A_MAC_PORT_RX_LINKA_RECEIVER_ADAC_CONTROL 0x3250
52974 
52975 #define S_ADSN_READWRITE    8
52976 #define V_ADSN_READWRITE(x) ((x) << S_ADSN_READWRITE)
52977 #define F_ADSN_READWRITE    V_ADSN_READWRITE(1U)
52978 
52979 #define S_ADSN_READONLY    7
52980 #define V_ADSN_READONLY(x) ((x) << S_ADSN_READONLY)
52981 #define F_ADSN_READONLY    V_ADSN_READONLY(1U)
52982 
52983 #define S_ADAC2    8
52984 #define M_ADAC2    0xffU
52985 #define V_ADAC2(x) ((x) << S_ADAC2)
52986 #define G_ADAC2(x) (((x) >> S_ADAC2) & M_ADAC2)
52987 
52988 #define S_ADAC1    0
52989 #define M_ADAC1    0xffU
52990 #define V_ADAC1(x) ((x) << S_ADAC1)
52991 #define G_ADAC1(x) (((x) >> S_ADAC1) & M_ADAC1)
52992 
52993 #define A_MAC_PORT_RX_LINKA_RECEIVER_AC_COUPLING_CONTROL 0x3254
52994 
52995 #define S_FACCPLDYN    13
52996 #define V_FACCPLDYN(x) ((x) << S_FACCPLDYN)
52997 #define F_FACCPLDYN    V_FACCPLDYN(1U)
52998 
52999 #define S_ACCPLGAIN    10
53000 #define M_ACCPLGAIN    0x7U
53001 #define V_ACCPLGAIN(x) ((x) << S_ACCPLGAIN)
53002 #define G_ACCPLGAIN(x) (((x) >> S_ACCPLGAIN) & M_ACCPLGAIN)
53003 
53004 #define S_ACCPLREF    8
53005 #define M_ACCPLREF    0x3U
53006 #define V_ACCPLREF(x) ((x) << S_ACCPLREF)
53007 #define G_ACCPLREF(x) (((x) >> S_ACCPLREF) & M_ACCPLREF)
53008 
53009 #define S_ACCPLSTEP    6
53010 #define M_ACCPLSTEP    0x3U
53011 #define V_ACCPLSTEP(x) ((x) << S_ACCPLSTEP)
53012 #define G_ACCPLSTEP(x) (((x) >> S_ACCPLSTEP) & M_ACCPLSTEP)
53013 
53014 #define S_ACCPLASTEP    1
53015 #define M_ACCPLASTEP    0x1fU
53016 #define V_ACCPLASTEP(x) ((x) << S_ACCPLASTEP)
53017 #define G_ACCPLASTEP(x) (((x) >> S_ACCPLASTEP) & M_ACCPLASTEP)
53018 
53019 #define S_FACCPL    0
53020 #define V_FACCPL(x) ((x) << S_FACCPL)
53021 #define F_FACCPL    V_FACCPL(1U)
53022 
53023 #define A_MAC_PORT_RX_LINKA_RECEIVER_AC_COUPLING_VALUE 0x3258
53024 
53025 #define S_ACCPLMEANS    15
53026 #define V_ACCPLMEANS(x) ((x) << S_ACCPLMEANS)
53027 #define F_ACCPLMEANS    V_ACCPLMEANS(1U)
53028 
53029 #define S_CDROVREN    8
53030 #define V_CDROVREN(x) ((x) << S_CDROVREN)
53031 #define F_CDROVREN    V_CDROVREN(1U)
53032 
53033 #define S_ACCPLBIAS    0
53034 #define M_ACCPLBIAS    0xffU
53035 #define V_ACCPLBIAS(x) ((x) << S_ACCPLBIAS)
53036 #define G_ACCPLBIAS(x) (((x) >> S_ACCPLBIAS) & M_ACCPLBIAS)
53037 
53038 #define A_MAC_PORT_RX_LINKA_DFE_H1_LOCAL_OFFSET_ODD2_EVN2 0x325c
53039 
53040 #define S_H1O2    8
53041 #define M_H1O2    0x3fU
53042 #define V_H1O2(x) ((x) << S_H1O2)
53043 #define G_H1O2(x) (((x) >> S_H1O2) & M_H1O2)
53044 
53045 #define S_H1E2    0
53046 #define M_H1E2    0x3fU
53047 #define V_H1E2(x) ((x) << S_H1E2)
53048 #define G_H1E2(x) (((x) >> S_H1E2) & M_H1E2)
53049 
53050 #define A_MAC_PORT_RX_LINKA_DFE_H1H2H3_LOCAL_OFFSET 0x325c
53051 
53052 #define S_H123CH    0
53053 #define M_H123CH    0x3fU
53054 #define V_H123CH(x) ((x) << S_H123CH)
53055 #define G_H123CH(x) (((x) >> S_H123CH) & M_H123CH)
53056 
53057 #define A_MAC_PORT_RX_LINKA_DFE_H1_LOCAL_OFFSET_ODD3_EVN3 0x3260
53058 
53059 #define S_H1O3    8
53060 #define M_H1O3    0x3fU
53061 #define V_H1O3(x) ((x) << S_H1O3)
53062 #define G_H1O3(x) (((x) >> S_H1O3) & M_H1O3)
53063 
53064 #define S_H1E3    0
53065 #define M_H1E3    0x3fU
53066 #define V_H1E3(x) ((x) << S_H1E3)
53067 #define G_H1E3(x) (((x) >> S_H1E3) & M_H1E3)
53068 
53069 #define A_MAC_PORT_RX_LINKA_DFE_H1H2H3_LOCAL_OFFSET_VALUE 0x3260
53070 
53071 #define S_H1OX    8
53072 #define M_H1OX    0x3fU
53073 #define V_H1OX(x) ((x) << S_H1OX)
53074 #define G_H1OX(x) (((x) >> S_H1OX) & M_H1OX)
53075 
53076 #define S_H1EX    0
53077 #define M_H1EX    0x3fU
53078 #define V_H1EX(x) ((x) << S_H1EX)
53079 #define G_H1EX(x) (((x) >> S_H1EX) & M_H1EX)
53080 
53081 #define A_MAC_PORT_RX_LINKA_DFE_H1_LOCAL_OFFSET_ODD4_EVN4 0x3264
53082 
53083 #define S_H1O4    8
53084 #define M_H1O4    0x3fU
53085 #define V_H1O4(x) ((x) << S_H1O4)
53086 #define G_H1O4(x) (((x) >> S_H1O4) & M_H1O4)
53087 
53088 #define S_H1E4    0
53089 #define M_H1E4    0x3fU
53090 #define V_H1E4(x) ((x) << S_H1E4)
53091 #define G_H1E4(x) (((x) >> S_H1E4) & M_H1E4)
53092 
53093 #define A_MAC_PORT_RX_LINKA_PEAKED_INTEGRATOR 0x3264
53094 
53095 #define S_PILOCK    10
53096 #define V_PILOCK(x) ((x) << S_PILOCK)
53097 #define F_PILOCK    V_PILOCK(1U)
53098 
53099 #define S_UNPKPKA    2
53100 #define M_UNPKPKA    0x3fU
53101 #define V_UNPKPKA(x) ((x) << S_UNPKPKA)
53102 #define G_UNPKPKA(x) (((x) >> S_UNPKPKA) & M_UNPKPKA)
53103 
53104 #define S_UNPKVGA    0
53105 #define M_UNPKVGA    0x3U
53106 #define V_UNPKVGA(x) ((x) << S_UNPKVGA)
53107 #define G_UNPKVGA(x) (((x) >> S_UNPKVGA) & M_UNPKVGA)
53108 
53109 #define A_MAC_PORT_RX_LINKA_CDR_ANALOG_SWITCH 0x3268
53110 
53111 #define S_OVRAC    15
53112 #define V_OVRAC(x) ((x) << S_OVRAC)
53113 #define F_OVRAC    V_OVRAC(1U)
53114 
53115 #define S_OVRPK    14
53116 #define V_OVRPK(x) ((x) << S_OVRPK)
53117 #define F_OVRPK    V_OVRPK(1U)
53118 
53119 #define S_OVRTAILS    12
53120 #define M_OVRTAILS    0x3U
53121 #define V_OVRTAILS(x) ((x) << S_OVRTAILS)
53122 #define G_OVRTAILS(x) (((x) >> S_OVRTAILS) & M_OVRTAILS)
53123 
53124 #define S_OVRTAILV    9
53125 #define M_OVRTAILV    0x7U
53126 #define V_OVRTAILV(x) ((x) << S_OVRTAILV)
53127 #define G_OVRTAILV(x) (((x) >> S_OVRTAILV) & M_OVRTAILV)
53128 
53129 #define S_OVRCAP    8
53130 #define V_OVRCAP(x) ((x) << S_OVRCAP)
53131 #define F_OVRCAP    V_OVRCAP(1U)
53132 
53133 #define S_OVRDCDPRE    7
53134 #define V_OVRDCDPRE(x) ((x) << S_OVRDCDPRE)
53135 #define F_OVRDCDPRE    V_OVRDCDPRE(1U)
53136 
53137 #define S_OVRDCDPST    6
53138 #define V_OVRDCDPST(x) ((x) << S_OVRDCDPST)
53139 #define F_OVRDCDPST    V_OVRDCDPST(1U)
53140 
53141 #define S_DCVSCTMODE    2
53142 #define V_DCVSCTMODE(x) ((x) << S_DCVSCTMODE)
53143 #define F_DCVSCTMODE    V_DCVSCTMODE(1U)
53144 
53145 #define S_CDRANLGSW    0
53146 #define M_CDRANLGSW    0x3U
53147 #define V_CDRANLGSW(x) ((x) << S_CDRANLGSW)
53148 #define G_CDRANLGSW(x) (((x) >> S_CDRANLGSW) & M_CDRANLGSW)
53149 
53150 #define A_MAC_PORT_RX_LINKA_PEAKING_AMPLIFIER_INTIALIZATION_CONTROL 0x326c
53151 
53152 #define S_PFLAG    5
53153 #define M_PFLAG    0x3U
53154 #define V_PFLAG(x) ((x) << S_PFLAG)
53155 #define G_PFLAG(x) (((x) >> S_PFLAG) & M_PFLAG)
53156 
53157 #define A_MAC_PORT_RX_LINKA_DYNAMIC_AMPLITUDE_CENTERING_DAC_AND_DYNAMIC_PEAKING_CONTROL_DPC 0x3270
53158 
53159 #define S_DPCMD    14
53160 #define V_DPCMD(x) ((x) << S_DPCMD)
53161 #define F_DPCMD    V_DPCMD(1U)
53162 
53163 #define S_DACCLIP    15
53164 #define V_DACCLIP(x) ((x) << S_DACCLIP)
53165 #define F_DACCLIP    V_DACCLIP(1U)
53166 
53167 #define S_DPCFRZ    14
53168 #define V_DPCFRZ(x) ((x) << S_DPCFRZ)
53169 #define F_DPCFRZ    V_DPCFRZ(1U)
53170 
53171 #define S_DPCLKNQ    11
53172 #define V_DPCLKNQ(x) ((x) << S_DPCLKNQ)
53173 #define F_DPCLKNQ    V_DPCLKNQ(1U)
53174 
53175 #define S_DPCWDFE    10
53176 #define V_DPCWDFE(x) ((x) << S_DPCWDFE)
53177 #define F_DPCWDFE    V_DPCWDFE(1U)
53178 
53179 #define S_DPCWPK    9
53180 #define V_DPCWPK(x) ((x) << S_DPCWPK)
53181 #define F_DPCWPK    V_DPCWPK(1U)
53182 
53183 #define A_MAC_PORT_RX_LINKA_DYNAMIC_DATA_CENTERING_DDC 0x3274
53184 
53185 #define S_VIEWSCAN    4
53186 #define V_VIEWSCAN(x) ((x) << S_VIEWSCAN)
53187 #define F_VIEWSCAN    V_VIEWSCAN(1U)
53188 
53189 #define S_T6_ODEC    0
53190 #define M_T6_ODEC    0xfU
53191 #define V_T6_ODEC(x) ((x) << S_T6_ODEC)
53192 #define G_T6_ODEC(x) (((x) >> S_T6_ODEC) & M_T6_ODEC)
53193 
53194 #define A_MAC_PORT_RX_LINKA_RECEIVER_INTERNAL_STATUS 0x3278
53195 
53196 #define S_T5BER6VAL    15
53197 #define V_T5BER6VAL(x) ((x) << S_T5BER6VAL)
53198 #define F_T5BER6VAL    V_T5BER6VAL(1U)
53199 
53200 #define S_T5BER6    14
53201 #define V_T5BER6(x) ((x) << S_T5BER6)
53202 #define F_T5BER6    V_T5BER6(1U)
53203 
53204 #define S_T5BER3VAL    13
53205 #define V_T5BER3VAL(x) ((x) << S_T5BER3VAL)
53206 #define F_T5BER3VAL    V_T5BER3VAL(1U)
53207 
53208 #define S_T5TOOFAST    12
53209 #define V_T5TOOFAST(x) ((x) << S_T5TOOFAST)
53210 #define F_T5TOOFAST    V_T5TOOFAST(1U)
53211 
53212 #define S_T5DPCCMP    9
53213 #define V_T5DPCCMP(x) ((x) << S_T5DPCCMP)
53214 #define F_T5DPCCMP    V_T5DPCCMP(1U)
53215 
53216 #define S_T5DACCMP    8
53217 #define V_T5DACCMP(x) ((x) << S_T5DACCMP)
53218 #define F_T5DACCMP    V_T5DACCMP(1U)
53219 
53220 #define S_T5DDCCMP    7
53221 #define V_T5DDCCMP(x) ((x) << S_T5DDCCMP)
53222 #define F_T5DDCCMP    V_T5DDCCMP(1U)
53223 
53224 #define S_T5AERRFLG    6
53225 #define V_T5AERRFLG(x) ((x) << S_T5AERRFLG)
53226 #define F_T5AERRFLG    V_T5AERRFLG(1U)
53227 
53228 #define S_T5WERRFLG    5
53229 #define V_T5WERRFLG(x) ((x) << S_T5WERRFLG)
53230 #define F_T5WERRFLG    V_T5WERRFLG(1U)
53231 
53232 #define S_T5TRCMP    4
53233 #define V_T5TRCMP(x) ((x) << S_T5TRCMP)
53234 #define F_T5TRCMP    V_T5TRCMP(1U)
53235 
53236 #define S_T5VLCKF    3
53237 #define V_T5VLCKF(x) ((x) << S_T5VLCKF)
53238 #define F_T5VLCKF    V_T5VLCKF(1U)
53239 
53240 #define S_T5ROCCMP    2
53241 #define V_T5ROCCMP(x) ((x) << S_T5ROCCMP)
53242 #define F_T5ROCCMP    V_T5ROCCMP(1U)
53243 
53244 #define S_T5DQCCCMP    1
53245 #define V_T5DQCCCMP(x) ((x) << S_T5DQCCCMP)
53246 #define F_T5DQCCCMP    V_T5DQCCCMP(1U)
53247 
53248 #define S_T5OCCMP    0
53249 #define V_T5OCCMP(x) ((x) << S_T5OCCMP)
53250 #define F_T5OCCMP    V_T5OCCMP(1U)
53251 
53252 #define S_RX_LINKA_ACCCMP_RIS    11
53253 #define V_RX_LINKA_ACCCMP_RIS(x) ((x) << S_RX_LINKA_ACCCMP_RIS)
53254 #define F_RX_LINKA_ACCCMP_RIS    V_RX_LINKA_ACCCMP_RIS(1U)
53255 
53256 #define S_DCCCMP    10
53257 #define V_DCCCMP(x) ((x) << S_DCCCMP)
53258 #define F_DCCCMP    V_DCCCMP(1U)
53259 
53260 #define S_T5IQCMP    1
53261 #define V_T5IQCMP(x) ((x) << S_T5IQCMP)
53262 #define F_T5IQCMP    V_T5IQCMP(1U)
53263 
53264 #define A_MAC_PORT_RX_LINKA_DFE_FUNCTION_CONTROL_1 0x327c
53265 
53266 #define S_FLOFF    1
53267 #define V_FLOFF(x) ((x) << S_FLOFF)
53268 #define F_FLOFF    V_FLOFF(1U)
53269 
53270 #define A_MAC_PORT_RX_LINKA_DFE_FUNCTION_CONTROL_2 0x3280
53271 
53272 #define S_H25SPC    15
53273 #define V_H25SPC(x) ((x) << S_H25SPC)
53274 #define F_H25SPC    V_H25SPC(1U)
53275 
53276 #define S_FTOOFAST    8
53277 #define V_FTOOFAST(x) ((x) << S_FTOOFAST)
53278 #define F_FTOOFAST    V_FTOOFAST(1U)
53279 
53280 #define S_FINTTRIM    7
53281 #define V_FINTTRIM(x) ((x) << S_FINTTRIM)
53282 #define F_FINTTRIM    V_FINTTRIM(1U)
53283 
53284 #define S_FDINV    6
53285 #define V_FDINV(x) ((x) << S_FDINV)
53286 #define F_FDINV    V_FDINV(1U)
53287 
53288 #define S_FHGS    5
53289 #define V_FHGS(x) ((x) << S_FHGS)
53290 #define F_FHGS    V_FHGS(1U)
53291 
53292 #define S_FH6H12    4
53293 #define V_FH6H12(x) ((x) << S_FH6H12)
53294 #define F_FH6H12    V_FH6H12(1U)
53295 
53296 #define S_FH1CAL    3
53297 #define V_FH1CAL(x) ((x) << S_FH1CAL)
53298 #define F_FH1CAL    V_FH1CAL(1U)
53299 
53300 #define S_FINTCAL    2
53301 #define V_FINTCAL(x) ((x) << S_FINTCAL)
53302 #define F_FINTCAL    V_FINTCAL(1U)
53303 
53304 #define S_FDCA    1
53305 #define V_FDCA(x) ((x) << S_FDCA)
53306 #define F_FDCA    V_FDCA(1U)
53307 
53308 #define S_FDQCC    0
53309 #define V_FDQCC(x) ((x) << S_FDQCC)
53310 #define F_FDQCC    V_FDQCC(1U)
53311 
53312 #define S_FDCCAL    14
53313 #define V_FDCCAL(x) ((x) << S_FDCCAL)
53314 #define F_FDCCAL    V_FDCCAL(1U)
53315 
53316 #define S_FROTCAL    13
53317 #define V_FROTCAL(x) ((x) << S_FROTCAL)
53318 #define F_FROTCAL    V_FROTCAL(1U)
53319 
53320 #define S_FIQAMP    12
53321 #define V_FIQAMP(x) ((x) << S_FIQAMP)
53322 #define F_FIQAMP    V_FIQAMP(1U)
53323 
53324 #define S_FRPTCALF    11
53325 #define V_FRPTCALF(x) ((x) << S_FRPTCALF)
53326 #define F_FRPTCALF    V_FRPTCALF(1U)
53327 
53328 #define S_FINTCALGS    10
53329 #define V_FINTCALGS(x) ((x) << S_FINTCALGS)
53330 #define F_FINTCALGS    V_FINTCALGS(1U)
53331 
53332 #define S_FDCC    9
53333 #define V_FDCC(x) ((x) << S_FDCC)
53334 #define F_FDCC    V_FDCC(1U)
53335 
53336 #define S_FDCD    7
53337 #define V_FDCD(x) ((x) << S_FDCD)
53338 #define F_FDCD    V_FDCD(1U)
53339 
53340 #define S_FINTRCALDYN    1
53341 #define V_FINTRCALDYN(x) ((x) << S_FINTRCALDYN)
53342 #define F_FINTRCALDYN    V_FINTRCALDYN(1U)
53343 
53344 #define S_FQCC    0
53345 #define V_FQCC(x) ((x) << S_FQCC)
53346 #define F_FQCC    V_FQCC(1U)
53347 
53348 #define A_MAC_PORT_RX_LINKA_DFE_OFFSET_EVN1_EVN2 0x3284
53349 
53350 #define S_LOFE2S_READWRITE    16
53351 #define V_LOFE2S_READWRITE(x) ((x) << S_LOFE2S_READWRITE)
53352 #define F_LOFE2S_READWRITE    V_LOFE2S_READWRITE(1U)
53353 
53354 #define S_LOFE2S_READONLY    14
53355 #define M_LOFE2S_READONLY    0x3U
53356 #define V_LOFE2S_READONLY(x) ((x) << S_LOFE2S_READONLY)
53357 #define G_LOFE2S_READONLY(x) (((x) >> S_LOFE2S_READONLY) & M_LOFE2S_READONLY)
53358 
53359 #define S_LOFE2    8
53360 #define M_LOFE2    0x3fU
53361 #define V_LOFE2(x) ((x) << S_LOFE2)
53362 #define G_LOFE2(x) (((x) >> S_LOFE2) & M_LOFE2)
53363 
53364 #define S_LOFE1S_READWRITE    7
53365 #define V_LOFE1S_READWRITE(x) ((x) << S_LOFE1S_READWRITE)
53366 #define F_LOFE1S_READWRITE    V_LOFE1S_READWRITE(1U)
53367 
53368 #define S_LOFE1S_READONLY    6
53369 #define V_LOFE1S_READONLY(x) ((x) << S_LOFE1S_READONLY)
53370 #define F_LOFE1S_READONLY    V_LOFE1S_READONLY(1U)
53371 
53372 #define S_LOFE1    0
53373 #define M_LOFE1    0x3fU
53374 #define V_LOFE1(x) ((x) << S_LOFE1)
53375 #define G_LOFE1(x) (((x) >> S_LOFE1) & M_LOFE1)
53376 
53377 #define A_MAC_PORT_RX_LINKA_DFE_OFFSET_CHANNEL 0x3284
53378 
53379 #define S_QCCIND    13
53380 #define V_QCCIND(x) ((x) << S_QCCIND)
53381 #define F_QCCIND    V_QCCIND(1U)
53382 
53383 #define S_DCDIND    10
53384 #define M_DCDIND    0x7U
53385 #define V_DCDIND(x) ((x) << S_DCDIND)
53386 #define G_DCDIND(x) (((x) >> S_DCDIND) & M_DCDIND)
53387 
53388 #define S_DCCIND    8
53389 #define M_DCCIND    0x3U
53390 #define V_DCCIND(x) ((x) << S_DCCIND)
53391 #define G_DCCIND(x) (((x) >> S_DCCIND) & M_DCCIND)
53392 
53393 #define S_CFSEL    5
53394 #define V_CFSEL(x) ((x) << S_CFSEL)
53395 #define F_CFSEL    V_CFSEL(1U)
53396 
53397 #define S_LOFCH    0
53398 #define M_LOFCH    0x1fU
53399 #define V_LOFCH(x) ((x) << S_LOFCH)
53400 #define G_LOFCH(x) (((x) >> S_LOFCH) & M_LOFCH)
53401 
53402 #define A_MAC_PORT_RX_LINKA_DFE_OFFSET_ODD1_ODD2 0x3288
53403 
53404 #define S_LOFO2S_READWRITE    15
53405 #define V_LOFO2S_READWRITE(x) ((x) << S_LOFO2S_READWRITE)
53406 #define F_LOFO2S_READWRITE    V_LOFO2S_READWRITE(1U)
53407 
53408 #define S_LOFO2S_READONLY    14
53409 #define V_LOFO2S_READONLY(x) ((x) << S_LOFO2S_READONLY)
53410 #define F_LOFO2S_READONLY    V_LOFO2S_READONLY(1U)
53411 
53412 #define S_LOFO2    8
53413 #define M_LOFO2    0x3fU
53414 #define V_LOFO2(x) ((x) << S_LOFO2)
53415 #define G_LOFO2(x) (((x) >> S_LOFO2) & M_LOFO2)
53416 
53417 #define S_LOFO1S_READWRITE    7
53418 #define V_LOFO1S_READWRITE(x) ((x) << S_LOFO1S_READWRITE)
53419 #define F_LOFO1S_READWRITE    V_LOFO1S_READWRITE(1U)
53420 
53421 #define S_LOFO1S_READONLY    6
53422 #define V_LOFO1S_READONLY(x) ((x) << S_LOFO1S_READONLY)
53423 #define F_LOFO1S_READONLY    V_LOFO1S_READONLY(1U)
53424 
53425 #define S_LOFO1    0
53426 #define M_LOFO1    0x3fU
53427 #define V_LOFO1(x) ((x) << S_LOFO1)
53428 #define G_LOFO1(x) (((x) >> S_LOFO1) & M_LOFO1)
53429 
53430 #define A_MAC_PORT_RX_LINKA_DFE_OFFSET_VALUE 0x3288
53431 
53432 #define S_LOFU    8
53433 #define M_LOFU    0x7fU
53434 #define V_LOFU(x) ((x) << S_LOFU)
53435 #define G_LOFU(x) (((x) >> S_LOFU) & M_LOFU)
53436 
53437 #define S_LOFL    0
53438 #define M_LOFL    0x7fU
53439 #define V_LOFL(x) ((x) << S_LOFL)
53440 #define G_LOFL(x) (((x) >> S_LOFL) & M_LOFL)
53441 
53442 #define A_MAC_PORT_RX_LINKA_DFE_OFFSET_EVN3_EVN4 0x328c
53443 
53444 #define S_LOFE4S_READWRITE    15
53445 #define V_LOFE4S_READWRITE(x) ((x) << S_LOFE4S_READWRITE)
53446 #define F_LOFE4S_READWRITE    V_LOFE4S_READWRITE(1U)
53447 
53448 #define S_LOFE4S_READONLY    14
53449 #define V_LOFE4S_READONLY(x) ((x) << S_LOFE4S_READONLY)
53450 #define F_LOFE4S_READONLY    V_LOFE4S_READONLY(1U)
53451 
53452 #define S_LOFE    8
53453 #define M_LOFE    0x3fU
53454 #define V_LOFE(x) ((x) << S_LOFE)
53455 #define G_LOFE(x) (((x) >> S_LOFE) & M_LOFE)
53456 
53457 #define S_LOFE3S_READWRITE    7
53458 #define V_LOFE3S_READWRITE(x) ((x) << S_LOFE3S_READWRITE)
53459 #define F_LOFE3S_READWRITE    V_LOFE3S_READWRITE(1U)
53460 
53461 #define S_LOFE3S_READONLY    6
53462 #define V_LOFE3S_READONLY(x) ((x) << S_LOFE3S_READONLY)
53463 #define F_LOFE3S_READONLY    V_LOFE3S_READONLY(1U)
53464 
53465 #define S_LOFE3    0
53466 #define M_LOFE3    0x3fU
53467 #define V_LOFE3(x) ((x) << S_LOFE3)
53468 #define G_LOFE3(x) (((x) >> S_LOFE3) & M_LOFE3)
53469 
53470 #define A_MAC_PORT_RX_LINKA_H_COEFFICIENBT_BIST 0x328c
53471 
53472 #define S_HBISTMAN    12
53473 #define V_HBISTMAN(x) ((x) << S_HBISTMAN)
53474 #define F_HBISTMAN    V_HBISTMAN(1U)
53475 
53476 #define S_HBISTRES    11
53477 #define V_HBISTRES(x) ((x) << S_HBISTRES)
53478 #define F_HBISTRES    V_HBISTRES(1U)
53479 
53480 #define S_HBISTSP    8
53481 #define M_HBISTSP    0x7U
53482 #define V_HBISTSP(x) ((x) << S_HBISTSP)
53483 #define G_HBISTSP(x) (((x) >> S_HBISTSP) & M_HBISTSP)
53484 
53485 #define S_HBISTEN    7
53486 #define V_HBISTEN(x) ((x) << S_HBISTEN)
53487 #define F_HBISTEN    V_HBISTEN(1U)
53488 
53489 #define S_HBISTRST    6
53490 #define V_HBISTRST(x) ((x) << S_HBISTRST)
53491 #define F_HBISTRST    V_HBISTRST(1U)
53492 
53493 #define S_HCOMP    5
53494 #define V_HCOMP(x) ((x) << S_HCOMP)
53495 #define F_HCOMP    V_HCOMP(1U)
53496 
53497 #define S_HPASS    4
53498 #define V_HPASS(x) ((x) << S_HPASS)
53499 #define F_HPASS    V_HPASS(1U)
53500 
53501 #define S_HSEL    0
53502 #define M_HSEL    0xfU
53503 #define V_HSEL(x) ((x) << S_HSEL)
53504 #define G_HSEL(x) (((x) >> S_HSEL) & M_HSEL)
53505 
53506 #define A_MAC_PORT_RX_LINKA_DFE_OFFSET_ODD3_ODD4 0x3290
53507 
53508 #define S_LOFO4S_READWRITE    15
53509 #define V_LOFO4S_READWRITE(x) ((x) << S_LOFO4S_READWRITE)
53510 #define F_LOFO4S_READWRITE    V_LOFO4S_READWRITE(1U)
53511 
53512 #define S_LOFO4S_READONLY    14
53513 #define V_LOFO4S_READONLY(x) ((x) << S_LOFO4S_READONLY)
53514 #define F_LOFO4S_READONLY    V_LOFO4S_READONLY(1U)
53515 
53516 #define S_LOFO4    8
53517 #define M_LOFO4    0x3fU
53518 #define V_LOFO4(x) ((x) << S_LOFO4)
53519 #define G_LOFO4(x) (((x) >> S_LOFO4) & M_LOFO4)
53520 
53521 #define S_LOFO3S_READWRITE    7
53522 #define V_LOFO3S_READWRITE(x) ((x) << S_LOFO3S_READWRITE)
53523 #define F_LOFO3S_READWRITE    V_LOFO3S_READWRITE(1U)
53524 
53525 #define S_LOFO3S_READONLY    6
53526 #define V_LOFO3S_READONLY(x) ((x) << S_LOFO3S_READONLY)
53527 #define F_LOFO3S_READONLY    V_LOFO3S_READONLY(1U)
53528 
53529 #define S_LOFO3    0
53530 #define M_LOFO3    0x3fU
53531 #define V_LOFO3(x) ((x) << S_LOFO3)
53532 #define G_LOFO3(x) (((x) >> S_LOFO3) & M_LOFO3)
53533 
53534 #define A_MAC_PORT_RX_LINKA_AC_CAPACITOR_BIST 0x3290
53535 
53536 #define S_RX_LINKA_ACCCMP_BIST    13
53537 #define V_RX_LINKA_ACCCMP_BIST(x) ((x) << S_RX_LINKA_ACCCMP_BIST)
53538 #define F_RX_LINKA_ACCCMP_BIST    V_RX_LINKA_ACCCMP_BIST(1U)
53539 
53540 #define S_ACCEN    12
53541 #define V_ACCEN(x) ((x) << S_ACCEN)
53542 #define F_ACCEN    V_ACCEN(1U)
53543 
53544 #define S_ACCRST    11
53545 #define V_ACCRST(x) ((x) << S_ACCRST)
53546 #define F_ACCRST    V_ACCRST(1U)
53547 
53548 #define S_ACCIND    8
53549 #define M_ACCIND    0x7U
53550 #define V_ACCIND(x) ((x) << S_ACCIND)
53551 #define G_ACCIND(x) (((x) >> S_ACCIND) & M_ACCIND)
53552 
53553 #define S_ACCRD    0
53554 #define M_ACCRD    0xffU
53555 #define V_ACCRD(x) ((x) << S_ACCRD)
53556 #define G_ACCRD(x) (((x) >> S_ACCRD) & M_ACCRD)
53557 
53558 #define A_MAC_PORT_RX_LINKA_DFE_E0_AND_E1_OFFSET 0x3294
53559 
53560 #define S_T5E1SN_READWRITE    15
53561 #define V_T5E1SN_READWRITE(x) ((x) << S_T5E1SN_READWRITE)
53562 #define F_T5E1SN_READWRITE    V_T5E1SN_READWRITE(1U)
53563 
53564 #define S_T5E1SN_READONLY    14
53565 #define V_T5E1SN_READONLY(x) ((x) << S_T5E1SN_READONLY)
53566 #define F_T5E1SN_READONLY    V_T5E1SN_READONLY(1U)
53567 
53568 #define S_T5E1AMP    8
53569 #define M_T5E1AMP    0x3fU
53570 #define V_T5E1AMP(x) ((x) << S_T5E1AMP)
53571 #define G_T5E1AMP(x) (((x) >> S_T5E1AMP) & M_T5E1AMP)
53572 
53573 #define S_T5E0SN_READWRITE    7
53574 #define V_T5E0SN_READWRITE(x) ((x) << S_T5E0SN_READWRITE)
53575 #define F_T5E0SN_READWRITE    V_T5E0SN_READWRITE(1U)
53576 
53577 #define S_T5E0SN_READONLY    6
53578 #define V_T5E0SN_READONLY(x) ((x) << S_T5E0SN_READONLY)
53579 #define F_T5E0SN_READONLY    V_T5E0SN_READONLY(1U)
53580 
53581 #define S_T5E0AMP    0
53582 #define M_T5E0AMP    0x3fU
53583 #define V_T5E0AMP(x) ((x) << S_T5E0AMP)
53584 #define G_T5E0AMP(x) (((x) >> S_T5E0AMP) & M_T5E0AMP)
53585 
53586 #define A_MAC_PORT_RX_LINKA_RECEIVER_LOFF_CONTROL 0x3298
53587 
53588 #define S_T5LFREG    12
53589 #define V_T5LFREG(x) ((x) << S_T5LFREG)
53590 #define F_T5LFREG    V_T5LFREG(1U)
53591 
53592 #define S_T5LFRC    11
53593 #define V_T5LFRC(x) ((x) << S_T5LFRC)
53594 #define F_T5LFRC    V_T5LFRC(1U)
53595 
53596 #define S_T5LFSEL    8
53597 #define M_T5LFSEL    0x7U
53598 #define V_T5LFSEL(x) ((x) << S_T5LFSEL)
53599 #define G_T5LFSEL(x) (((x) >> S_T5LFSEL) & M_T5LFSEL)
53600 
53601 #define A_MAC_PORT_RX_LINKA_RECEIVER_LOFF_CONTROL_REGISTER 0x3298
53602 
53603 #define S_LFREG    15
53604 #define V_LFREG(x) ((x) << S_LFREG)
53605 #define F_LFREG    V_LFREG(1U)
53606 
53607 #define S_LFRC    14
53608 #define V_LFRC(x) ((x) << S_LFRC)
53609 #define F_LFRC    V_LFRC(1U)
53610 
53611 #define S_LGIDLE    13
53612 #define V_LGIDLE(x) ((x) << S_LGIDLE)
53613 #define F_LGIDLE    V_LGIDLE(1U)
53614 
53615 #define S_LFTGT    8
53616 #define M_LFTGT    0x1fU
53617 #define V_LFTGT(x) ((x) << S_LFTGT)
53618 #define G_LFTGT(x) (((x) >> S_LFTGT) & M_LFTGT)
53619 
53620 #define S_LGTGT    7
53621 #define V_LGTGT(x) ((x) << S_LGTGT)
53622 #define F_LGTGT    V_LGTGT(1U)
53623 
53624 #define S_LRDY    6
53625 #define V_LRDY(x) ((x) << S_LRDY)
53626 #define F_LRDY    V_LRDY(1U)
53627 
53628 #define S_LIDLE    5
53629 #define V_LIDLE(x) ((x) << S_LIDLE)
53630 #define F_LIDLE    V_LIDLE(1U)
53631 
53632 #define S_LCURR    0
53633 #define M_LCURR    0x1fU
53634 #define V_LCURR(x) ((x) << S_LCURR)
53635 #define G_LCURR(x) (((x) >> S_LCURR) & M_LCURR)
53636 
53637 #define A_MAC_PORT_RX_LINKA_RECEIVER_SIGDET_CONTROL 0x329c
53638 
53639 #define S_OFFSN_READWRITE    14
53640 #define V_OFFSN_READWRITE(x) ((x) << S_OFFSN_READWRITE)
53641 #define F_OFFSN_READWRITE    V_OFFSN_READWRITE(1U)
53642 
53643 #define S_OFFSN_READONLY    13
53644 #define V_OFFSN_READONLY(x) ((x) << S_OFFSN_READONLY)
53645 #define F_OFFSN_READONLY    V_OFFSN_READONLY(1U)
53646 
53647 #define S_OFFAMP    8
53648 #define M_OFFAMP    0x1fU
53649 #define V_OFFAMP(x) ((x) << S_OFFAMP)
53650 #define G_OFFAMP(x) (((x) >> S_OFFAMP) & M_OFFAMP)
53651 
53652 #define S_SDACDC    7
53653 #define V_SDACDC(x) ((x) << S_SDACDC)
53654 #define F_SDACDC    V_SDACDC(1U)
53655 
53656 #define S_OFFSN    13
53657 #define M_OFFSN    0x3U
53658 #define V_OFFSN(x) ((x) << S_OFFSN)
53659 #define G_OFFSN(x) (((x) >> S_OFFSN) & M_OFFSN)
53660 
53661 #define A_MAC_PORT_RX_LINKA_RECEIVER_ANALOG_CONTROL_SWITCH 0x32a0
53662 
53663 #define S_T5_RX_SETHDIS    7
53664 #define V_T5_RX_SETHDIS(x) ((x) << S_T5_RX_SETHDIS)
53665 #define F_T5_RX_SETHDIS    V_T5_RX_SETHDIS(1U)
53666 
53667 #define S_T5_RX_PDTERM    6
53668 #define V_T5_RX_PDTERM(x) ((x) << S_T5_RX_PDTERM)
53669 #define F_T5_RX_PDTERM    V_T5_RX_PDTERM(1U)
53670 
53671 #define S_T5_RX_BYPASS    5
53672 #define V_T5_RX_BYPASS(x) ((x) << S_T5_RX_BYPASS)
53673 #define F_T5_RX_BYPASS    V_T5_RX_BYPASS(1U)
53674 
53675 #define S_T5_RX_LPFEN    4
53676 #define V_T5_RX_LPFEN(x) ((x) << S_T5_RX_LPFEN)
53677 #define F_T5_RX_LPFEN    V_T5_RX_LPFEN(1U)
53678 
53679 #define S_T5_RX_VGABOD    3
53680 #define V_T5_RX_VGABOD(x) ((x) << S_T5_RX_VGABOD)
53681 #define F_T5_RX_VGABOD    V_T5_RX_VGABOD(1U)
53682 
53683 #define S_T5_RX_VTBYP    2
53684 #define V_T5_RX_VTBYP(x) ((x) << S_T5_RX_VTBYP)
53685 #define F_T5_RX_VTBYP    V_T5_RX_VTBYP(1U)
53686 
53687 #define S_T5_RX_VTERM    0
53688 #define M_T5_RX_VTERM    0x3U
53689 #define V_T5_RX_VTERM(x) ((x) << S_T5_RX_VTERM)
53690 #define G_T5_RX_VTERM(x) (((x) >> S_T5_RX_VTERM) & M_T5_RX_VTERM)
53691 
53692 #define S_RX_OVRSUMPD    15
53693 #define V_RX_OVRSUMPD(x) ((x) << S_RX_OVRSUMPD)
53694 #define F_RX_OVRSUMPD    V_RX_OVRSUMPD(1U)
53695 
53696 #define S_RX_OVRKBPD    14
53697 #define V_RX_OVRKBPD(x) ((x) << S_RX_OVRKBPD)
53698 #define F_RX_OVRKBPD    V_RX_OVRKBPD(1U)
53699 
53700 #define S_RX_OVRDIVPD    13
53701 #define V_RX_OVRDIVPD(x) ((x) << S_RX_OVRDIVPD)
53702 #define F_RX_OVRDIVPD    V_RX_OVRDIVPD(1U)
53703 
53704 #define S_RX_OFFVGADIS    12
53705 #define V_RX_OFFVGADIS(x) ((x) << S_RX_OFFVGADIS)
53706 #define F_RX_OFFVGADIS    V_RX_OFFVGADIS(1U)
53707 
53708 #define S_RX_OFFACDIS    11
53709 #define V_RX_OFFACDIS(x) ((x) << S_RX_OFFACDIS)
53710 #define F_RX_OFFACDIS    V_RX_OFFACDIS(1U)
53711 
53712 #define S_RX_VTERM    10
53713 #define V_RX_VTERM(x) ((x) << S_RX_VTERM)
53714 #define F_RX_VTERM    V_RX_VTERM(1U)
53715 
53716 #define S_RX_DISSPY2D    8
53717 #define V_RX_DISSPY2D(x) ((x) << S_RX_DISSPY2D)
53718 #define F_RX_DISSPY2D    V_RX_DISSPY2D(1U)
53719 
53720 #define S_RX_OBSOVEN    7
53721 #define V_RX_OBSOVEN(x) ((x) << S_RX_OBSOVEN)
53722 #define F_RX_OBSOVEN    V_RX_OBSOVEN(1U)
53723 
53724 #define S_RX_LINKANLGSW    0
53725 #define M_RX_LINKANLGSW    0x7fU
53726 #define V_RX_LINKANLGSW(x) ((x) << S_RX_LINKANLGSW)
53727 #define G_RX_LINKANLGSW(x) (((x) >> S_RX_LINKANLGSW) & M_RX_LINKANLGSW)
53728 
53729 #define A_MAC_PORT_RX_LINKA_INTEGRATOR_DAC_OFFSET 0x32a4
53730 
53731 #define S_ISTRIMS    14
53732 #define M_ISTRIMS    0x3U
53733 #define V_ISTRIMS(x) ((x) << S_ISTRIMS)
53734 #define G_ISTRIMS(x) (((x) >> S_ISTRIMS) & M_ISTRIMS)
53735 
53736 #define S_ISTRIM    8
53737 #define M_ISTRIM    0x3fU
53738 #define V_ISTRIM(x) ((x) << S_ISTRIM)
53739 #define G_ISTRIM(x) (((x) >> S_ISTRIM) & M_ISTRIM)
53740 
53741 #define S_HALF1    7
53742 #define V_HALF1(x) ((x) << S_HALF1)
53743 #define F_HALF1    V_HALF1(1U)
53744 
53745 #define S_HALF2    6
53746 #define V_HALF2(x) ((x) << S_HALF2)
53747 #define F_HALF2    V_HALF2(1U)
53748 
53749 #define S_INTDAC    0
53750 #define M_INTDAC    0x3fU
53751 #define V_INTDAC(x) ((x) << S_INTDAC)
53752 #define G_INTDAC(x) (((x) >> S_INTDAC) & M_INTDAC)
53753 
53754 #define S_INTDACEGS    13
53755 #define M_INTDACEGS    0x7U
53756 #define V_INTDACEGS(x) ((x) << S_INTDACEGS)
53757 #define G_INTDACEGS(x) (((x) >> S_INTDACEGS) & M_INTDACEGS)
53758 
53759 #define S_INTDACE    8
53760 #define M_INTDACE    0x1fU
53761 #define V_INTDACE(x) ((x) << S_INTDACE)
53762 #define G_INTDACE(x) (((x) >> S_INTDACE) & M_INTDACE)
53763 
53764 #define S_INTDACGS    6
53765 #define M_INTDACGS    0x3U
53766 #define V_INTDACGS(x) ((x) << S_INTDACGS)
53767 #define G_INTDACGS(x) (((x) >> S_INTDACGS) & M_INTDACGS)
53768 
53769 #define A_MAC_PORT_RX_LINKA_DIGITAL_EYE_CONTROL 0x32a8
53770 
53771 #define S_MINWDTH    5
53772 #define M_MINWDTH    0x1fU
53773 #define V_MINWDTH(x) ((x) << S_MINWDTH)
53774 #define G_MINWDTH(x) (((x) >> S_MINWDTH) & M_MINWDTH)
53775 
53776 #define A_MAC_PORT_RX_LINKA_DIGITAL_EYE_METRICS 0x32ac
53777 
53778 #define S_T5SMQM    13
53779 #define M_T5SMQM    0x7U
53780 #define V_T5SMQM(x) ((x) << S_T5SMQM)
53781 #define G_T5SMQM(x) (((x) >> S_T5SMQM) & M_T5SMQM)
53782 
53783 #define S_T5SMQ    5
53784 #define M_T5SMQ    0xffU
53785 #define V_T5SMQ(x) ((x) << S_T5SMQ)
53786 #define G_T5SMQ(x) (((x) >> S_T5SMQ) & M_T5SMQ)
53787 
53788 #define S_T5EMMD    3
53789 #define M_T5EMMD    0x3U
53790 #define V_T5EMMD(x) ((x) << S_T5EMMD)
53791 #define G_T5EMMD(x) (((x) >> S_T5EMMD) & M_T5EMMD)
53792 
53793 #define S_T5EMBRDY    2
53794 #define V_T5EMBRDY(x) ((x) << S_T5EMBRDY)
53795 #define F_T5EMBRDY    V_T5EMBRDY(1U)
53796 
53797 #define S_T5EMBUMP    1
53798 #define V_T5EMBUMP(x) ((x) << S_T5EMBUMP)
53799 #define F_T5EMBUMP    V_T5EMBUMP(1U)
53800 
53801 #define S_T5EMEN    0
53802 #define V_T5EMEN(x) ((x) << S_T5EMEN)
53803 #define F_T5EMEN    V_T5EMEN(1U)
53804 
53805 #define S_SMQM    13
53806 #define M_SMQM    0x7U
53807 #define V_SMQM(x) ((x) << S_SMQM)
53808 #define G_SMQM(x) (((x) >> S_SMQM) & M_SMQM)
53809 
53810 #define S_SMQ    5
53811 #define M_SMQ    0xffU
53812 #define V_SMQ(x) ((x) << S_SMQ)
53813 #define G_SMQ(x) (((x) >> S_SMQ) & M_SMQ)
53814 
53815 #define S_T6_EMMD    3
53816 #define M_T6_EMMD    0x3U
53817 #define V_T6_EMMD(x) ((x) << S_T6_EMMD)
53818 #define G_T6_EMMD(x) (((x) >> S_T6_EMMD) & M_T6_EMMD)
53819 
53820 #define S_T6_EMBRDY    2
53821 #define V_T6_EMBRDY(x) ((x) << S_T6_EMBRDY)
53822 #define F_T6_EMBRDY    V_T6_EMBRDY(1U)
53823 
53824 #define S_T6_EMBUMP    1
53825 #define V_T6_EMBUMP(x) ((x) << S_T6_EMBUMP)
53826 #define F_T6_EMBUMP    V_T6_EMBUMP(1U)
53827 
53828 #define A_MAC_PORT_RX_LINKA_DIGITAL_EYE_METRICS_ERROR_COUNT 0x32b0
53829 
53830 #define S_EMF8    15
53831 #define V_EMF8(x) ((x) << S_EMF8)
53832 #define F_EMF8    V_EMF8(1U)
53833 
53834 #define S_EMCNT    4
53835 #define M_EMCNT    0xffU
53836 #define V_EMCNT(x) ((x) << S_EMCNT)
53837 #define G_EMCNT(x) (((x) >> S_EMCNT) & M_EMCNT)
53838 
53839 #define S_EMOFLO    2
53840 #define V_EMOFLO(x) ((x) << S_EMOFLO)
53841 #define F_EMOFLO    V_EMOFLO(1U)
53842 
53843 #define S_EMCRST    1
53844 #define V_EMCRST(x) ((x) << S_EMCRST)
53845 #define F_EMCRST    V_EMCRST(1U)
53846 
53847 #define S_EMCEN    0
53848 #define V_EMCEN(x) ((x) << S_EMCEN)
53849 #define F_EMCEN    V_EMCEN(1U)
53850 
53851 #define S_EMSF    13
53852 #define V_EMSF(x) ((x) << S_EMSF)
53853 #define F_EMSF    V_EMSF(1U)
53854 
53855 #define S_EMDATA59    12
53856 #define V_EMDATA59(x) ((x) << S_EMDATA59)
53857 #define F_EMDATA59    V_EMDATA59(1U)
53858 
53859 #define A_MAC_PORT_RX_LINKA_DIGITAL_EYE_METRICS_PDF_EYE_COUNT 0x32b4
53860 
53861 #define S_SM2RDY    15
53862 #define V_SM2RDY(x) ((x) << S_SM2RDY)
53863 #define F_SM2RDY    V_SM2RDY(1U)
53864 
53865 #define S_SM2RST    14
53866 #define V_SM2RST(x) ((x) << S_SM2RST)
53867 #define F_SM2RST    V_SM2RST(1U)
53868 
53869 #define S_APDF    0
53870 #define M_APDF    0xfffU
53871 #define V_APDF(x) ((x) << S_APDF)
53872 #define G_APDF(x) (((x) >> S_APDF) & M_APDF)
53873 
53874 #define A_MAC_PORT_RX_LINKA_DIGITAL_EYE_METRICS_PATTERN_LENGTH 0x32b8
53875 
53876 #define S_SM0LEN    0
53877 #define M_SM0LEN    0x7fffU
53878 #define V_SM0LEN(x) ((x) << S_SM0LEN)
53879 #define G_SM0LEN(x) (((x) >> S_SM0LEN) & M_SM0LEN)
53880 
53881 #define A_MAC_PORT_RX_LINKA_DFE_FUNCTION_CONTROL_3 0x32bc
53882 
53883 #define S_FTIMEOUT    15
53884 #define V_FTIMEOUT(x) ((x) << S_FTIMEOUT)
53885 #define F_FTIMEOUT    V_FTIMEOUT(1U)
53886 
53887 #define S_FROTCAL4    14
53888 #define V_FROTCAL4(x) ((x) << S_FROTCAL4)
53889 #define F_FROTCAL4    V_FROTCAL4(1U)
53890 
53891 #define S_FDCD2    13
53892 #define V_FDCD2(x) ((x) << S_FDCD2)
53893 #define F_FDCD2    V_FDCD2(1U)
53894 
53895 #define S_FPRBSPOLTOG    12
53896 #define V_FPRBSPOLTOG(x) ((x) << S_FPRBSPOLTOG)
53897 #define F_FPRBSPOLTOG    V_FPRBSPOLTOG(1U)
53898 
53899 #define S_FPRBSOFF2    11
53900 #define V_FPRBSOFF2(x) ((x) << S_FPRBSOFF2)
53901 #define F_FPRBSOFF2    V_FPRBSOFF2(1U)
53902 
53903 #define S_FDDCAL2    10
53904 #define V_FDDCAL2(x) ((x) << S_FDDCAL2)
53905 #define F_FDDCAL2    V_FDDCAL2(1U)
53906 
53907 #define S_FDDCFLTR    9
53908 #define V_FDDCFLTR(x) ((x) << S_FDDCFLTR)
53909 #define F_FDDCFLTR    V_FDDCFLTR(1U)
53910 
53911 #define S_FDAC6    8
53912 #define V_FDAC6(x) ((x) << S_FDAC6)
53913 #define F_FDAC6    V_FDAC6(1U)
53914 
53915 #define S_FDDC5    7
53916 #define V_FDDC5(x) ((x) << S_FDDC5)
53917 #define F_FDDC5    V_FDDC5(1U)
53918 
53919 #define S_FDDC3456    6
53920 #define V_FDDC3456(x) ((x) << S_FDDC3456)
53921 #define F_FDDC3456    V_FDDC3456(1U)
53922 
53923 #define S_FSPY2DATA    5
53924 #define V_FSPY2DATA(x) ((x) << S_FSPY2DATA)
53925 #define F_FSPY2DATA    V_FSPY2DATA(1U)
53926 
53927 #define S_FPHSLOCK    4
53928 #define V_FPHSLOCK(x) ((x) << S_FPHSLOCK)
53929 #define F_FPHSLOCK    V_FPHSLOCK(1U)
53930 
53931 #define S_FCLKALGN    3
53932 #define V_FCLKALGN(x) ((x) << S_FCLKALGN)
53933 #define F_FCLKALGN    V_FCLKALGN(1U)
53934 
53935 #define S_FCLKALDYN    2
53936 #define V_FCLKALDYN(x) ((x) << S_FCLKALDYN)
53937 #define F_FCLKALDYN    V_FCLKALDYN(1U)
53938 
53939 #define S_FDFE    1
53940 #define V_FDFE(x) ((x) << S_FDFE)
53941 #define F_FDFE    V_FDFE(1U)
53942 
53943 #define S_FPRBSOFF    0
53944 #define V_FPRBSOFF(x) ((x) << S_FPRBSOFF)
53945 #define F_FPRBSOFF    V_FPRBSOFF(1U)
53946 
53947 #define A_MAC_PORT_RX_LINKA_DFE_TAP_ENABLE 0x32c0
53948 
53949 #define S_H_EN    1
53950 #define M_H_EN    0xfffU
53951 #define V_H_EN(x) ((x) << S_H_EN)
53952 #define G_H_EN(x) (((x) >> S_H_EN) & M_H_EN)
53953 
53954 #define A_MAC_PORT_RX_LINKA_DFE_TAP_CONTROL 0x32c0
53955 
53956 #define S_RX_LINKA_INDEX_DFE_TC    0
53957 #define M_RX_LINKA_INDEX_DFE_TC    0xfU
53958 #define V_RX_LINKA_INDEX_DFE_TC(x) ((x) << S_RX_LINKA_INDEX_DFE_TC)
53959 #define G_RX_LINKA_INDEX_DFE_TC(x) (((x) >> S_RX_LINKA_INDEX_DFE_TC) & M_RX_LINKA_INDEX_DFE_TC)
53960 
53961 #define A_MAC_PORT_RX_LINKA_DFE_H1 0x32c4
53962 #define A_MAC_PORT_RX_LINKA_DFE_TAP 0x32c4
53963 
53964 #define S_RX_LINKA_INDEX_DFE_TAP    0
53965 #define M_RX_LINKA_INDEX_DFE_TAP    0xfU
53966 #define V_RX_LINKA_INDEX_DFE_TAP(x) ((x) << S_RX_LINKA_INDEX_DFE_TAP)
53967 #define G_RX_LINKA_INDEX_DFE_TAP(x) (((x) >> S_RX_LINKA_INDEX_DFE_TAP) & M_RX_LINKA_INDEX_DFE_TAP)
53968 
53969 #define A_MAC_PORT_RX_LINKA_DFE_H2 0x32c8
53970 
53971 #define S_H2OSN_READWRITE    14
53972 #define V_H2OSN_READWRITE(x) ((x) << S_H2OSN_READWRITE)
53973 #define F_H2OSN_READWRITE    V_H2OSN_READWRITE(1U)
53974 
53975 #define S_H2OSN_READONLY    13
53976 #define V_H2OSN_READONLY(x) ((x) << S_H2OSN_READONLY)
53977 #define F_H2OSN_READONLY    V_H2OSN_READONLY(1U)
53978 
53979 #define S_H2ESN_READWRITE    6
53980 #define V_H2ESN_READWRITE(x) ((x) << S_H2ESN_READWRITE)
53981 #define F_H2ESN_READWRITE    V_H2ESN_READWRITE(1U)
53982 
53983 #define S_H2ESN_READONLY    5
53984 #define V_H2ESN_READONLY(x) ((x) << S_H2ESN_READONLY)
53985 #define F_H2ESN_READONLY    V_H2ESN_READONLY(1U)
53986 
53987 #define A_MAC_PORT_RX_LINKA_DFE_H3 0x32cc
53988 
53989 #define S_H3OSN_READWRITE    13
53990 #define V_H3OSN_READWRITE(x) ((x) << S_H3OSN_READWRITE)
53991 #define F_H3OSN_READWRITE    V_H3OSN_READWRITE(1U)
53992 
53993 #define S_H3OSN_READONLY    12
53994 #define V_H3OSN_READONLY(x) ((x) << S_H3OSN_READONLY)
53995 #define F_H3OSN_READONLY    V_H3OSN_READONLY(1U)
53996 
53997 #define S_H3ESN_READWRITE    5
53998 #define V_H3ESN_READWRITE(x) ((x) << S_H3ESN_READWRITE)
53999 #define F_H3ESN_READWRITE    V_H3ESN_READWRITE(1U)
54000 
54001 #define S_H3ESN_READONLY    4
54002 #define V_H3ESN_READONLY(x) ((x) << S_H3ESN_READONLY)
54003 #define F_H3ESN_READONLY    V_H3ESN_READONLY(1U)
54004 
54005 #define A_MAC_PORT_RX_LINKA_DFE_H4 0x32d0
54006 
54007 #define S_H4OGS    14
54008 #define M_H4OGS    0x3U
54009 #define V_H4OGS(x) ((x) << S_H4OGS)
54010 #define G_H4OGS(x) (((x) >> S_H4OGS) & M_H4OGS)
54011 
54012 #define S_H4OSN_READWRITE    13
54013 #define V_H4OSN_READWRITE(x) ((x) << S_H4OSN_READWRITE)
54014 #define F_H4OSN_READWRITE    V_H4OSN_READWRITE(1U)
54015 
54016 #define S_H4OSN_READONLY    12
54017 #define V_H4OSN_READONLY(x) ((x) << S_H4OSN_READONLY)
54018 #define F_H4OSN_READONLY    V_H4OSN_READONLY(1U)
54019 
54020 #define S_H4EGS    6
54021 #define M_H4EGS    0x3U
54022 #define V_H4EGS(x) ((x) << S_H4EGS)
54023 #define G_H4EGS(x) (((x) >> S_H4EGS) & M_H4EGS)
54024 
54025 #define S_H4ESN_READWRITE    5
54026 #define V_H4ESN_READWRITE(x) ((x) << S_H4ESN_READWRITE)
54027 #define F_H4ESN_READWRITE    V_H4ESN_READWRITE(1U)
54028 
54029 #define S_H4ESN_READONLY    4
54030 #define V_H4ESN_READONLY(x) ((x) << S_H4ESN_READONLY)
54031 #define F_H4ESN_READONLY    V_H4ESN_READONLY(1U)
54032 
54033 #define A_MAC_PORT_RX_LINKA_DFE_H5 0x32d4
54034 
54035 #define S_H5OGS    14
54036 #define M_H5OGS    0x3U
54037 #define V_H5OGS(x) ((x) << S_H5OGS)
54038 #define G_H5OGS(x) (((x) >> S_H5OGS) & M_H5OGS)
54039 
54040 #define S_H5OSN_READWRITE    13
54041 #define V_H5OSN_READWRITE(x) ((x) << S_H5OSN_READWRITE)
54042 #define F_H5OSN_READWRITE    V_H5OSN_READWRITE(1U)
54043 
54044 #define S_H5OSN_READONLY    12
54045 #define V_H5OSN_READONLY(x) ((x) << S_H5OSN_READONLY)
54046 #define F_H5OSN_READONLY    V_H5OSN_READONLY(1U)
54047 
54048 #define S_H5EGS    6
54049 #define M_H5EGS    0x3U
54050 #define V_H5EGS(x) ((x) << S_H5EGS)
54051 #define G_H5EGS(x) (((x) >> S_H5EGS) & M_H5EGS)
54052 
54053 #define S_H5ESN_READWRITE    5
54054 #define V_H5ESN_READWRITE(x) ((x) << S_H5ESN_READWRITE)
54055 #define F_H5ESN_READWRITE    V_H5ESN_READWRITE(1U)
54056 
54057 #define S_H5ESN_READONLY    4
54058 #define V_H5ESN_READONLY(x) ((x) << S_H5ESN_READONLY)
54059 #define F_H5ESN_READONLY    V_H5ESN_READONLY(1U)
54060 
54061 #define A_MAC_PORT_RX_LINKA_DFE_H6_AND_H7 0x32d8
54062 
54063 #define S_H7GS    14
54064 #define M_H7GS    0x3U
54065 #define V_H7GS(x) ((x) << S_H7GS)
54066 #define G_H7GS(x) (((x) >> S_H7GS) & M_H7GS)
54067 
54068 #define S_H7SN_READWRITE    13
54069 #define V_H7SN_READWRITE(x) ((x) << S_H7SN_READWRITE)
54070 #define F_H7SN_READWRITE    V_H7SN_READWRITE(1U)
54071 
54072 #define S_H7SN_READONLY    12
54073 #define V_H7SN_READONLY(x) ((x) << S_H7SN_READONLY)
54074 #define F_H7SN_READONLY    V_H7SN_READONLY(1U)
54075 
54076 #define S_H7MAG    8
54077 #define M_H7MAG    0xfU
54078 #define V_H7MAG(x) ((x) << S_H7MAG)
54079 #define G_H7MAG(x) (((x) >> S_H7MAG) & M_H7MAG)
54080 
54081 #define S_H6GS    6
54082 #define M_H6GS    0x3U
54083 #define V_H6GS(x) ((x) << S_H6GS)
54084 #define G_H6GS(x) (((x) >> S_H6GS) & M_H6GS)
54085 
54086 #define S_H6SN_READWRITE    5
54087 #define V_H6SN_READWRITE(x) ((x) << S_H6SN_READWRITE)
54088 #define F_H6SN_READWRITE    V_H6SN_READWRITE(1U)
54089 
54090 #define S_H6SN_READONLY    4
54091 #define V_H6SN_READONLY(x) ((x) << S_H6SN_READONLY)
54092 #define F_H6SN_READONLY    V_H6SN_READONLY(1U)
54093 
54094 #define S_H6MAG    0
54095 #define M_H6MAG    0xfU
54096 #define V_H6MAG(x) ((x) << S_H6MAG)
54097 #define G_H6MAG(x) (((x) >> S_H6MAG) & M_H6MAG)
54098 
54099 #define A_MAC_PORT_RX_LINKA_DFE_H8_AND_H9 0x32dc
54100 
54101 #define S_H9GS    14
54102 #define M_H9GS    0x3U
54103 #define V_H9GS(x) ((x) << S_H9GS)
54104 #define G_H9GS(x) (((x) >> S_H9GS) & M_H9GS)
54105 
54106 #define S_H9SN_READWRITE    13
54107 #define V_H9SN_READWRITE(x) ((x) << S_H9SN_READWRITE)
54108 #define F_H9SN_READWRITE    V_H9SN_READWRITE(1U)
54109 
54110 #define S_H9SN_READONLY    12
54111 #define V_H9SN_READONLY(x) ((x) << S_H9SN_READONLY)
54112 #define F_H9SN_READONLY    V_H9SN_READONLY(1U)
54113 
54114 #define S_H9MAG    8
54115 #define M_H9MAG    0xfU
54116 #define V_H9MAG(x) ((x) << S_H9MAG)
54117 #define G_H9MAG(x) (((x) >> S_H9MAG) & M_H9MAG)
54118 
54119 #define S_H8GS    6
54120 #define M_H8GS    0x3U
54121 #define V_H8GS(x) ((x) << S_H8GS)
54122 #define G_H8GS(x) (((x) >> S_H8GS) & M_H8GS)
54123 
54124 #define S_H8SN_READWRITE    5
54125 #define V_H8SN_READWRITE(x) ((x) << S_H8SN_READWRITE)
54126 #define F_H8SN_READWRITE    V_H8SN_READWRITE(1U)
54127 
54128 #define S_H8SN_READONLY    4
54129 #define V_H8SN_READONLY(x) ((x) << S_H8SN_READONLY)
54130 #define F_H8SN_READONLY    V_H8SN_READONLY(1U)
54131 
54132 #define S_H8MAG    0
54133 #define M_H8MAG    0xfU
54134 #define V_H8MAG(x) ((x) << S_H8MAG)
54135 #define G_H8MAG(x) (((x) >> S_H8MAG) & M_H8MAG)
54136 
54137 #define A_MAC_PORT_RX_LINKA_DFE_H10_AND_H11 0x32e0
54138 
54139 #define S_H11GS    14
54140 #define M_H11GS    0x3U
54141 #define V_H11GS(x) ((x) << S_H11GS)
54142 #define G_H11GS(x) (((x) >> S_H11GS) & M_H11GS)
54143 
54144 #define S_H11SN_READWRITE    13
54145 #define V_H11SN_READWRITE(x) ((x) << S_H11SN_READWRITE)
54146 #define F_H11SN_READWRITE    V_H11SN_READWRITE(1U)
54147 
54148 #define S_H11SN_READONLY    12
54149 #define V_H11SN_READONLY(x) ((x) << S_H11SN_READONLY)
54150 #define F_H11SN_READONLY    V_H11SN_READONLY(1U)
54151 
54152 #define S_H11MAG    8
54153 #define M_H11MAG    0xfU
54154 #define V_H11MAG(x) ((x) << S_H11MAG)
54155 #define G_H11MAG(x) (((x) >> S_H11MAG) & M_H11MAG)
54156 
54157 #define S_H10GS    6
54158 #define M_H10GS    0x3U
54159 #define V_H10GS(x) ((x) << S_H10GS)
54160 #define G_H10GS(x) (((x) >> S_H10GS) & M_H10GS)
54161 
54162 #define S_H10SN_READWRITE    5
54163 #define V_H10SN_READWRITE(x) ((x) << S_H10SN_READWRITE)
54164 #define F_H10SN_READWRITE    V_H10SN_READWRITE(1U)
54165 
54166 #define S_H10SN_READONLY    4
54167 #define V_H10SN_READONLY(x) ((x) << S_H10SN_READONLY)
54168 #define F_H10SN_READONLY    V_H10SN_READONLY(1U)
54169 
54170 #define S_H10MAG    0
54171 #define M_H10MAG    0xfU
54172 #define V_H10MAG(x) ((x) << S_H10MAG)
54173 #define G_H10MAG(x) (((x) >> S_H10MAG) & M_H10MAG)
54174 
54175 #define A_MAC_PORT_RX_LINKA_DFE_H12 0x32e4
54176 
54177 #define S_H12GS    6
54178 #define M_H12GS    0x3U
54179 #define V_H12GS(x) ((x) << S_H12GS)
54180 #define G_H12GS(x) (((x) >> S_H12GS) & M_H12GS)
54181 
54182 #define S_H12SN_READWRITE    5
54183 #define V_H12SN_READWRITE(x) ((x) << S_H12SN_READWRITE)
54184 #define F_H12SN_READWRITE    V_H12SN_READWRITE(1U)
54185 
54186 #define S_H12SN_READONLY    4
54187 #define V_H12SN_READONLY(x) ((x) << S_H12SN_READONLY)
54188 #define F_H12SN_READONLY    V_H12SN_READONLY(1U)
54189 
54190 #define S_H12MAG    0
54191 #define M_H12MAG    0xfU
54192 #define V_H12MAG(x) ((x) << S_H12MAG)
54193 #define G_H12MAG(x) (((x) >> S_H12MAG) & M_H12MAG)
54194 
54195 #define A_MAC_PORT_RX_LINKA_RECEIVER_INTERNAL_STATUS_2 0x32e4
54196 
54197 #define S_STNDBYSTAT    15
54198 #define V_STNDBYSTAT(x) ((x) << S_STNDBYSTAT)
54199 #define F_STNDBYSTAT    V_STNDBYSTAT(1U)
54200 
54201 #define S_CALSDONE    14
54202 #define V_CALSDONE(x) ((x) << S_CALSDONE)
54203 #define F_CALSDONE    V_CALSDONE(1U)
54204 
54205 #define S_ACISRCCMP    5
54206 #define V_ACISRCCMP(x) ((x) << S_ACISRCCMP)
54207 #define F_ACISRCCMP    V_ACISRCCMP(1U)
54208 
54209 #define S_PRBSOFFCMP    4
54210 #define V_PRBSOFFCMP(x) ((x) << S_PRBSOFFCMP)
54211 #define F_PRBSOFFCMP    V_PRBSOFFCMP(1U)
54212 
54213 #define S_CLKALGNCMP    3
54214 #define V_CLKALGNCMP(x) ((x) << S_CLKALGNCMP)
54215 #define F_CLKALGNCMP    V_CLKALGNCMP(1U)
54216 
54217 #define S_ROTFCMP    2
54218 #define V_ROTFCMP(x) ((x) << S_ROTFCMP)
54219 #define F_ROTFCMP    V_ROTFCMP(1U)
54220 
54221 #define S_DCDCMP    1
54222 #define V_DCDCMP(x) ((x) << S_DCDCMP)
54223 #define F_DCDCMP    V_DCDCMP(1U)
54224 
54225 #define S_QCCCMP    0
54226 #define V_QCCCMP(x) ((x) << S_QCCCMP)
54227 #define F_QCCCMP    V_QCCCMP(1U)
54228 
54229 #define A_MAC_PORT_RX_LINKA_AC_COUPLING_CURRENT_SOURCE_ADJUST 0x32e8
54230 
54231 #define S_FCSADJ    6
54232 #define V_FCSADJ(x) ((x) << S_FCSADJ)
54233 #define F_FCSADJ    V_FCSADJ(1U)
54234 
54235 #define S_CSIND    3
54236 #define M_CSIND    0x3U
54237 #define V_CSIND(x) ((x) << S_CSIND)
54238 #define G_CSIND(x) (((x) >> S_CSIND) & M_CSIND)
54239 
54240 #define S_CSVAL    0
54241 #define M_CSVAL    0x7U
54242 #define V_CSVAL(x) ((x) << S_CSVAL)
54243 #define G_CSVAL(x) (((x) >> S_CSVAL) & M_CSVAL)
54244 
54245 #define A_MAC_PORT_RX_LINKA_RECEIVER_DCD_CONTROL 0x32ec
54246 
54247 #define S_DCDTMDOUT    15
54248 #define V_DCDTMDOUT(x) ((x) << S_DCDTMDOUT)
54249 #define F_DCDTMDOUT    V_DCDTMDOUT(1U)
54250 
54251 #define S_DCDTOEN    14
54252 #define V_DCDTOEN(x) ((x) << S_DCDTOEN)
54253 #define F_DCDTOEN    V_DCDTOEN(1U)
54254 
54255 #define S_DCDLOCK    13
54256 #define V_DCDLOCK(x) ((x) << S_DCDLOCK)
54257 #define F_DCDLOCK    V_DCDLOCK(1U)
54258 
54259 #define S_DCDSTEP    11
54260 #define M_DCDSTEP    0x3U
54261 #define V_DCDSTEP(x) ((x) << S_DCDSTEP)
54262 #define G_DCDSTEP(x) (((x) >> S_DCDSTEP) & M_DCDSTEP)
54263 
54264 #define S_DCDALTWPDIS    10
54265 #define V_DCDALTWPDIS(x) ((x) << S_DCDALTWPDIS)
54266 #define F_DCDALTWPDIS    V_DCDALTWPDIS(1U)
54267 
54268 #define S_DCDOVRDEN    9
54269 #define V_DCDOVRDEN(x) ((x) << S_DCDOVRDEN)
54270 #define F_DCDOVRDEN    V_DCDOVRDEN(1U)
54271 
54272 #define S_DCCAOVRDEN    8
54273 #define V_DCCAOVRDEN(x) ((x) << S_DCCAOVRDEN)
54274 #define F_DCCAOVRDEN    V_DCCAOVRDEN(1U)
54275 
54276 #define S_DCDSIGN    6
54277 #define M_DCDSIGN    0x3U
54278 #define V_DCDSIGN(x) ((x) << S_DCDSIGN)
54279 #define G_DCDSIGN(x) (((x) >> S_DCDSIGN) & M_DCDSIGN)
54280 
54281 #define S_DCDAMP    0
54282 #define M_DCDAMP    0x3fU
54283 #define V_DCDAMP(x) ((x) << S_DCDAMP)
54284 #define G_DCDAMP(x) (((x) >> S_DCDAMP) & M_DCDAMP)
54285 
54286 #define A_MAC_PORT_RX_LINKA_RECEIVER_DCC_CONTROL 0x32f0
54287 
54288 #define S_PRBSMODE    14
54289 #define M_PRBSMODE    0x3U
54290 #define V_PRBSMODE(x) ((x) << S_PRBSMODE)
54291 #define G_PRBSMODE(x) (((x) >> S_PRBSMODE) & M_PRBSMODE)
54292 
54293 #define S_RX_LINKA_DCCSTEP_RXCTL    10
54294 #define M_RX_LINKA_DCCSTEP_RXCTL    0x3U
54295 #define V_RX_LINKA_DCCSTEP_RXCTL(x) ((x) << S_RX_LINKA_DCCSTEP_RXCTL)
54296 #define G_RX_LINKA_DCCSTEP_RXCTL(x) (((x) >> S_RX_LINKA_DCCSTEP_RXCTL) & M_RX_LINKA_DCCSTEP_RXCTL)
54297 
54298 #define S_DCCOVRDEN    9
54299 #define V_DCCOVRDEN(x) ((x) << S_DCCOVRDEN)
54300 #define F_DCCOVRDEN    V_DCCOVRDEN(1U)
54301 
54302 #define S_RX_LINKA_DCCLOCK_RXCTL    8
54303 #define V_RX_LINKA_DCCLOCK_RXCTL(x) ((x) << S_RX_LINKA_DCCLOCK_RXCTL)
54304 #define F_RX_LINKA_DCCLOCK_RXCTL    V_RX_LINKA_DCCLOCK_RXCTL(1U)
54305 
54306 #define A_MAC_PORT_RX_LINKA_RECEIVER_QCC_CONTROL 0x32f4
54307 
54308 #define S_DCCQCCMODE    15
54309 #define V_DCCQCCMODE(x) ((x) << S_DCCQCCMODE)
54310 #define F_DCCQCCMODE    V_DCCQCCMODE(1U)
54311 
54312 #define S_DCCQCCDYN    14
54313 #define V_DCCQCCDYN(x) ((x) << S_DCCQCCDYN)
54314 #define F_DCCQCCDYN    V_DCCQCCDYN(1U)
54315 
54316 #define S_DCCQCCHOLD    13
54317 #define V_DCCQCCHOLD(x) ((x) << S_DCCQCCHOLD)
54318 #define F_DCCQCCHOLD    V_DCCQCCHOLD(1U)
54319 
54320 #define S_QCCSTEP    10
54321 #define M_QCCSTEP    0x3U
54322 #define V_QCCSTEP(x) ((x) << S_QCCSTEP)
54323 #define G_QCCSTEP(x) (((x) >> S_QCCSTEP) & M_QCCSTEP)
54324 
54325 #define S_QCCOVRDEN    9
54326 #define V_QCCOVRDEN(x) ((x) << S_QCCOVRDEN)
54327 #define F_QCCOVRDEN    V_QCCOVRDEN(1U)
54328 
54329 #define S_QCCLOCK    8
54330 #define V_QCCLOCK(x) ((x) << S_QCCLOCK)
54331 #define F_QCCLOCK    V_QCCLOCK(1U)
54332 
54333 #define S_QCCSIGN    6
54334 #define M_QCCSIGN    0x3U
54335 #define V_QCCSIGN(x) ((x) << S_QCCSIGN)
54336 #define G_QCCSIGN(x) (((x) >> S_QCCSIGN) & M_QCCSIGN)
54337 
54338 #define S_QCDAMP    0
54339 #define M_QCDAMP    0x3fU
54340 #define V_QCDAMP(x) ((x) << S_QCDAMP)
54341 #define G_QCDAMP(x) (((x) >> S_QCDAMP) & M_QCDAMP)
54342 
54343 #define A_MAC_PORT_RX_LINKA_RECEIVER_MACRO_TEST_CONTROL_2 0x32f8
54344 
54345 #define S_DFEDACLSSD    6
54346 #define V_DFEDACLSSD(x) ((x) << S_DFEDACLSSD)
54347 #define F_DFEDACLSSD    V_DFEDACLSSD(1U)
54348 
54349 #define S_SDLSSD    5
54350 #define V_SDLSSD(x) ((x) << S_SDLSSD)
54351 #define F_SDLSSD    V_SDLSSD(1U)
54352 
54353 #define S_DFEOBSBIAS    4
54354 #define V_DFEOBSBIAS(x) ((x) << S_DFEOBSBIAS)
54355 #define F_DFEOBSBIAS    V_DFEOBSBIAS(1U)
54356 
54357 #define S_GBOFSTLSSD    3
54358 #define V_GBOFSTLSSD(x) ((x) << S_GBOFSTLSSD)
54359 #define F_GBOFSTLSSD    V_GBOFSTLSSD(1U)
54360 
54361 #define S_RXDOBS    2
54362 #define V_RXDOBS(x) ((x) << S_RXDOBS)
54363 #define F_RXDOBS    V_RXDOBS(1U)
54364 
54365 #define S_ACJZPT    1
54366 #define V_ACJZPT(x) ((x) << S_ACJZPT)
54367 #define F_ACJZPT    V_ACJZPT(1U)
54368 
54369 #define S_ACJZNT    0
54370 #define V_ACJZNT(x) ((x) << S_ACJZNT)
54371 #define F_ACJZNT    V_ACJZNT(1U)
54372 
54373 #define A_MAC_PORT_RX_LINKA_RECEIVER_MACRO_TEST_CONTROL_REGISTER_2 0x32f8
54374 
54375 #define S_TSTCMP    15
54376 #define V_TSTCMP(x) ((x) << S_TSTCMP)
54377 #define F_TSTCMP    V_TSTCMP(1U)
54378 
54379 #define A_MAC_PORT_RX_LINKA_RECEIVER_MACRO_TEST_CONTROL_1 0x32fc
54380 
54381 #define S_PHSLOCK    10
54382 #define V_PHSLOCK(x) ((x) << S_PHSLOCK)
54383 #define F_PHSLOCK    V_PHSLOCK(1U)
54384 
54385 #define S_TESTMODE    9
54386 #define V_TESTMODE(x) ((x) << S_TESTMODE)
54387 #define F_TESTMODE    V_TESTMODE(1U)
54388 
54389 #define S_CALMODE    8
54390 #define V_CALMODE(x) ((x) << S_CALMODE)
54391 #define F_CALMODE    V_CALMODE(1U)
54392 
54393 #define S_AMPSEL    7
54394 #define V_AMPSEL(x) ((x) << S_AMPSEL)
54395 #define F_AMPSEL    V_AMPSEL(1U)
54396 
54397 #define S_WHICHNRZ    6
54398 #define V_WHICHNRZ(x) ((x) << S_WHICHNRZ)
54399 #define F_WHICHNRZ    V_WHICHNRZ(1U)
54400 
54401 #define S_BANKA    5
54402 #define V_BANKA(x) ((x) << S_BANKA)
54403 #define F_BANKA    V_BANKA(1U)
54404 
54405 #define S_BANKB    4
54406 #define V_BANKB(x) ((x) << S_BANKB)
54407 #define F_BANKB    V_BANKB(1U)
54408 
54409 #define S_ACJPDP    3
54410 #define V_ACJPDP(x) ((x) << S_ACJPDP)
54411 #define F_ACJPDP    V_ACJPDP(1U)
54412 
54413 #define S_ACJPDN    2
54414 #define V_ACJPDN(x) ((x) << S_ACJPDN)
54415 #define F_ACJPDN    V_ACJPDN(1U)
54416 
54417 #define S_LSSDT    1
54418 #define V_LSSDT(x) ((x) << S_LSSDT)
54419 #define F_LSSDT    V_LSSDT(1U)
54420 
54421 #define S_MTHOLD    0
54422 #define V_MTHOLD(x) ((x) << S_MTHOLD)
54423 #define F_MTHOLD    V_MTHOLD(1U)
54424 
54425 #define S_CALMODEEDGE    14
54426 #define V_CALMODEEDGE(x) ((x) << S_CALMODEEDGE)
54427 #define F_CALMODEEDGE    V_CALMODEEDGE(1U)
54428 
54429 #define S_TESTCAP    13
54430 #define V_TESTCAP(x) ((x) << S_TESTCAP)
54431 #define F_TESTCAP    V_TESTCAP(1U)
54432 
54433 #define S_SNAPEN    12
54434 #define V_SNAPEN(x) ((x) << S_SNAPEN)
54435 #define F_SNAPEN    V_SNAPEN(1U)
54436 
54437 #define S_ASYNCDIR    11
54438 #define V_ASYNCDIR(x) ((x) << S_ASYNCDIR)
54439 #define F_ASYNCDIR    V_ASYNCDIR(1U)
54440 
54441 #define A_MAC_PORT_RX_LINKB_RECEIVER_CONFIGURATION_MODE 0x3300
54442 #define A_MAC_PORT_RX_LINKB_RECEIVER_TEST_CONTROL 0x3304
54443 #define A_MAC_PORT_RX_LINKB_PHASE_ROTATOR_CONTROL 0x3308
54444 #define A_MAC_PORT_RX_LINKB_PHASE_ROTATOR_OFFSET_CONTROL 0x330c
54445 
54446 #define S_T6_TMSCAL    8
54447 #define M_T6_TMSCAL    0x3U
54448 #define V_T6_TMSCAL(x) ((x) << S_T6_TMSCAL)
54449 #define G_T6_TMSCAL(x) (((x) >> S_T6_TMSCAL) & M_T6_TMSCAL)
54450 
54451 #define S_T6_APADJ    7
54452 #define V_T6_APADJ(x) ((x) << S_T6_APADJ)
54453 #define F_T6_APADJ    V_T6_APADJ(1U)
54454 
54455 #define S_T6_RSEL    6
54456 #define V_T6_RSEL(x) ((x) << S_T6_RSEL)
54457 #define F_T6_RSEL    V_T6_RSEL(1U)
54458 
54459 #define S_T6_PHOFFS    0
54460 #define M_T6_PHOFFS    0x3fU
54461 #define V_T6_PHOFFS(x) ((x) << S_T6_PHOFFS)
54462 #define G_T6_PHOFFS(x) (((x) >> S_T6_PHOFFS) & M_T6_PHOFFS)
54463 
54464 #define A_MAC_PORT_RX_LINKB_PHASE_ROTATOR_POSITION_1 0x3310
54465 #define A_MAC_PORT_RX_LINKB_PHASE_ROTATOR_POSITION_2 0x3314
54466 #define A_MAC_PORT_RX_LINKB_PHASE_ROTATOR_STATIC_PHASE_OFFSET_1 0x3318
54467 #define A_MAC_PORT_RX_LINKB_PHASE_ROTATOR_STATIC_PHASE_OFFSET_2 0x331c
54468 #define A_MAC_PORT_RX_LINKB_DFE_CONTROL 0x3320
54469 
54470 #define S_T6_SPIFMT    8
54471 #define M_T6_SPIFMT    0xfU
54472 #define V_T6_SPIFMT(x) ((x) << S_T6_SPIFMT)
54473 #define G_T6_SPIFMT(x) (((x) >> S_T6_SPIFMT) & M_T6_SPIFMT)
54474 
54475 #define A_MAC_PORT_RX_LINKB_DFE_SAMPLE_SNAPSHOT_1 0x3324
54476 #define A_MAC_PORT_RX_LINKB_DFE_SAMPLE_SNAPSHOT_2 0x3328
54477 #define A_MAC_PORT_RX_LINKB_RECEIVER_VGA_CONTROL_1 0x332c
54478 
54479 #define S_T6_WRAPSEL    15
54480 #define V_T6_WRAPSEL(x) ((x) << S_T6_WRAPSEL)
54481 #define F_T6_WRAPSEL    V_T6_WRAPSEL(1U)
54482 
54483 #define S_T6_PEAK    9
54484 #define M_T6_PEAK    0x1fU
54485 #define V_T6_PEAK(x) ((x) << S_T6_PEAK)
54486 #define G_T6_PEAK(x) (((x) >> S_T6_PEAK) & M_T6_PEAK)
54487 
54488 #define A_MAC_PORT_RX_LINKB_RECEIVER_VGA_CONTROL_2 0x3330
54489 
54490 #define S_T6_T5VGAIN    0
54491 #define M_T6_T5VGAIN    0x7fU
54492 #define V_T6_T5VGAIN(x) ((x) << S_T6_T5VGAIN)
54493 #define G_T6_T5VGAIN(x) (((x) >> S_T6_T5VGAIN) & M_T6_T5VGAIN)
54494 
54495 #define A_MAC_PORT_RX_LINKB_RECEIVER_VGA_CONTROL_3 0x3334
54496 #define A_MAC_PORT_RX_LINKB_RECEIVER_DQCC_CONTROL_1 0x3338
54497 #define A_MAC_PORT_RX_LINKB_RECEIVER_POWER_MANAGEMENT_CONTROL 0x3338
54498 #define A_MAC_PORT_RX_LINKB_RECEIVER_IQAMP_CONTROL_1 0x333c
54499 #define A_MAC_PORT_RX_LINKB_RECEIVER_DQCC_CONTROL_3 0x3340
54500 #define A_MAC_PORT_RX_LINKB_RECEIVER_IQAMP_CONTROL_2 0x3340
54501 #define A_MAC_PORT_RX_LINKB_RECEIVER_DACAP_AND_DACAN_SELECTION 0x3344
54502 #define A_MAC_PORT_RX_LINKB_RECEIVER_DACAP_AND_DACAN 0x3348
54503 #define A_MAC_PORT_RX_LINKB_RECEIVER_DACA_MIN_AND_DACAZ 0x334c
54504 #define A_MAC_PORT_RX_LINKB_RECEIVER_DACA_MIN 0x334c
54505 #define A_MAC_PORT_RX_LINKB_RECEIVER_ADAC_CONTROL 0x3350
54506 #define A_MAC_PORT_RX_LINKB_RECEIVER_AC_COUPLING_CONTROL 0x3354
54507 #define A_MAC_PORT_RX_LINKB_RECEIVER_AC_COUPLING_VALUE 0x3358
54508 #define A_MAC_PORT_RX_LINKB_DFE_H1_LOCAL_OFFSET_ODD2_EVN2 0x335c
54509 #define A_MAC_PORT_RX_LINKB_DFE_H1H2H3_LOCAL_OFFSET 0x335c
54510 #define A_MAC_PORT_RX_LINKB_DFE_H1_LOCAL_OFFSET_ODD3_EVN3 0x3360
54511 #define A_MAC_PORT_RX_LINKB_DFE_H1H2H3_LOCAL_OFFSET_VALUE 0x3360
54512 #define A_MAC_PORT_RX_LINKB_DFE_H1_LOCAL_OFFSET_ODD4_EVN4 0x3364
54513 #define A_MAC_PORT_RX_LINKB_PEAKED_INTEGRATOR 0x3364
54514 #define A_MAC_PORT_RX_LINKB_CDR_ANALOG_SWITCH 0x3368
54515 #define A_MAC_PORT_RX_LINKB_PEAKING_AMPLIFIER_INTIALIZATION_CONTROL 0x336c
54516 #define A_MAC_PORT_RX_LINKB_DYNAMIC_AMPLITUDE_CENTERING_DAC_AND_DYNAMIC_PEAKING_CONTROL_DPC 0x3370
54517 #define A_MAC_PORT_RX_LINKB_DYNAMIC_DATA_CENTERING_DDC 0x3374
54518 
54519 #define S_T6_ODEC    0
54520 #define M_T6_ODEC    0xfU
54521 #define V_T6_ODEC(x) ((x) << S_T6_ODEC)
54522 #define G_T6_ODEC(x) (((x) >> S_T6_ODEC) & M_T6_ODEC)
54523 
54524 #define A_MAC_PORT_RX_LINKB_RECEIVER_INTERNAL_STATUS 0x3378
54525 
54526 #define S_RX_LINKB_ACCCMP_RIS    11
54527 #define V_RX_LINKB_ACCCMP_RIS(x) ((x) << S_RX_LINKB_ACCCMP_RIS)
54528 #define F_RX_LINKB_ACCCMP_RIS    V_RX_LINKB_ACCCMP_RIS(1U)
54529 
54530 #define A_MAC_PORT_RX_LINKB_DFE_FUNCTION_CONTROL_1 0x337c
54531 #define A_MAC_PORT_RX_LINKB_DFE_FUNCTION_CONTROL_2 0x3380
54532 #define A_MAC_PORT_RX_LINKB_DFE_OFFSET_EVN1_EVN2 0x3384
54533 #define A_MAC_PORT_RX_LINKB_DFE_OFFSET_CHANNEL 0x3384
54534 #define A_MAC_PORT_RX_LINKB_DFE_OFFSET_ODD1_ODD2 0x3388
54535 #define A_MAC_PORT_RX_LINKB_DFE_OFFSET_VALUE 0x3388
54536 #define A_MAC_PORT_RX_LINKB_DFE_OFFSET_EVN3_EVN4 0x338c
54537 #define A_MAC_PORT_RX_LINKB_H_COEFFICIENBT_BIST 0x338c
54538 #define A_MAC_PORT_RX_LINKB_DFE_OFFSET_ODD3_ODD4 0x3390
54539 #define A_MAC_PORT_RX_LINKB_AC_CAPACITOR_BIST 0x3390
54540 
54541 #define S_RX_LINKB_ACCCMP_BIST    13
54542 #define V_RX_LINKB_ACCCMP_BIST(x) ((x) << S_RX_LINKB_ACCCMP_BIST)
54543 #define F_RX_LINKB_ACCCMP_BIST    V_RX_LINKB_ACCCMP_BIST(1U)
54544 
54545 #define A_MAC_PORT_RX_LINKB_DFE_E0_AND_E1_OFFSET 0x3394
54546 #define A_MAC_PORT_RX_LINKB_RECEIVER_LOFF_CONTROL 0x3398
54547 #define A_MAC_PORT_RX_LINKB_RECEIVER_LOFF_CONTROL_REGISTER 0x3398
54548 #define A_MAC_PORT_RX_LINKB_RECEIVER_SIGDET_CONTROL 0x339c
54549 #define A_MAC_PORT_RX_LINKB_RECEIVER_ANALOG_CONTROL_SWITCH 0x33a0
54550 #define A_MAC_PORT_RX_LINKB_INTEGRATOR_DAC_OFFSET 0x33a4
54551 #define A_MAC_PORT_RX_LINKB_DIGITAL_EYE_CONTROL 0x33a8
54552 #define A_MAC_PORT_RX_LINKB_DIGITAL_EYE_METRICS 0x33ac
54553 
54554 #define S_T6_EMMD    3
54555 #define M_T6_EMMD    0x3U
54556 #define V_T6_EMMD(x) ((x) << S_T6_EMMD)
54557 #define G_T6_EMMD(x) (((x) >> S_T6_EMMD) & M_T6_EMMD)
54558 
54559 #define S_T6_EMBRDY    2
54560 #define V_T6_EMBRDY(x) ((x) << S_T6_EMBRDY)
54561 #define F_T6_EMBRDY    V_T6_EMBRDY(1U)
54562 
54563 #define S_T6_EMBUMP    1
54564 #define V_T6_EMBUMP(x) ((x) << S_T6_EMBUMP)
54565 #define F_T6_EMBUMP    V_T6_EMBUMP(1U)
54566 
54567 #define A_MAC_PORT_RX_LINKB_DIGITAL_EYE_METRICS_ERROR_COUNT 0x33b0
54568 #define A_MAC_PORT_RX_LINKB_DIGITAL_EYE_METRICS_PDF_EYE_COUNT 0x33b4
54569 #define A_MAC_PORT_RX_LINKB_DIGITAL_EYE_METRICS_PATTERN_LENGTH 0x33b8
54570 #define A_MAC_PORT_RX_LINKB_DFE_FUNCTION_CONTROL_3 0x33bc
54571 #define A_MAC_PORT_RX_LINKB_DFE_TAP_ENABLE 0x33c0
54572 #define A_MAC_PORT_RX_LINKB_DFE_TAP_CONTROL 0x33c0
54573 
54574 #define S_RX_LINKB_INDEX_DFE_TC    0
54575 #define M_RX_LINKB_INDEX_DFE_TC    0xfU
54576 #define V_RX_LINKB_INDEX_DFE_TC(x) ((x) << S_RX_LINKB_INDEX_DFE_TC)
54577 #define G_RX_LINKB_INDEX_DFE_TC(x) (((x) >> S_RX_LINKB_INDEX_DFE_TC) & M_RX_LINKB_INDEX_DFE_TC)
54578 
54579 #define A_MAC_PORT_RX_LINKB_DFE_H1 0x33c4
54580 #define A_MAC_PORT_RX_LINKB_DFE_TAP 0x33c4
54581 
54582 #define S_RX_LINKB_INDEX_DFE_TAP    0
54583 #define M_RX_LINKB_INDEX_DFE_TAP    0xfU
54584 #define V_RX_LINKB_INDEX_DFE_TAP(x) ((x) << S_RX_LINKB_INDEX_DFE_TAP)
54585 #define G_RX_LINKB_INDEX_DFE_TAP(x) (((x) >> S_RX_LINKB_INDEX_DFE_TAP) & M_RX_LINKB_INDEX_DFE_TAP)
54586 
54587 #define A_MAC_PORT_RX_LINKB_DFE_H2 0x33c8
54588 #define A_MAC_PORT_RX_LINKB_DFE_H3 0x33cc
54589 #define A_MAC_PORT_RX_LINKB_DFE_H4 0x33d0
54590 #define A_MAC_PORT_RX_LINKB_DFE_H5 0x33d4
54591 #define A_MAC_PORT_RX_LINKB_DFE_H6_AND_H7 0x33d8
54592 #define A_MAC_PORT_RX_LINKB_DFE_H8_AND_H9 0x33dc
54593 #define A_MAC_PORT_RX_LINKB_DFE_H10_AND_H11 0x33e0
54594 #define A_MAC_PORT_RX_LINKB_DFE_H12 0x33e4
54595 #define A_MAC_PORT_RX_LINKB_RECEIVER_INTERNAL_STATUS_2 0x33e4
54596 #define A_MAC_PORT_RX_LINKB_AC_COUPLING_CURRENT_SOURCE_ADJUST 0x33e8
54597 #define A_MAC_PORT_RX_LINKB_RECEIVER_DCD_CONTROL 0x33ec
54598 #define A_MAC_PORT_RX_LINKB_RECEIVER_DCC_CONTROL 0x33f0
54599 
54600 #define S_RX_LINKB_DCCSTEP_RXCTL    10
54601 #define M_RX_LINKB_DCCSTEP_RXCTL    0x3U
54602 #define V_RX_LINKB_DCCSTEP_RXCTL(x) ((x) << S_RX_LINKB_DCCSTEP_RXCTL)
54603 #define G_RX_LINKB_DCCSTEP_RXCTL(x) (((x) >> S_RX_LINKB_DCCSTEP_RXCTL) & M_RX_LINKB_DCCSTEP_RXCTL)
54604 
54605 #define S_RX_LINKB_DCCLOCK_RXCTL    8
54606 #define V_RX_LINKB_DCCLOCK_RXCTL(x) ((x) << S_RX_LINKB_DCCLOCK_RXCTL)
54607 #define F_RX_LINKB_DCCLOCK_RXCTL    V_RX_LINKB_DCCLOCK_RXCTL(1U)
54608 
54609 #define A_MAC_PORT_RX_LINKB_RECEIVER_QCC_CONTROL 0x33f4
54610 #define A_MAC_PORT_RX_LINKB_RECEIVER_MACRO_TEST_CONTROL_2 0x33f8
54611 #define A_MAC_PORT_RX_LINKB_RECEIVER_MACRO_TEST_CONTROL_REGISTER_2 0x33f8
54612 #define A_MAC_PORT_RX_LINKB_RECEIVER_MACRO_TEST_CONTROL_1 0x33fc
54613 #define A_MAC_PORT_TX_LINKC_TRANSMIT_CONFIGURATION_MODE 0x3400
54614 
54615 #define S_T6_T5_TX_RXLOOP    5
54616 #define V_T6_T5_TX_RXLOOP(x) ((x) << S_T6_T5_TX_RXLOOP)
54617 #define F_T6_T5_TX_RXLOOP    V_T6_T5_TX_RXLOOP(1U)
54618 
54619 #define S_T6_T5_TX_BWSEL    2
54620 #define M_T6_T5_TX_BWSEL    0x3U
54621 #define V_T6_T5_TX_BWSEL(x) ((x) << S_T6_T5_TX_BWSEL)
54622 #define G_T6_T5_TX_BWSEL(x) (((x) >> S_T6_T5_TX_BWSEL) & M_T6_T5_TX_BWSEL)
54623 
54624 #define A_MAC_PORT_TX_LINKC_TRANSMIT_TEST_CONTROL 0x3404
54625 
54626 #define S_T6_ERROR    9
54627 #define V_T6_ERROR(x) ((x) << S_T6_ERROR)
54628 #define F_T6_ERROR    V_T6_ERROR(1U)
54629 
54630 #define A_MAC_PORT_TX_LINKC_TRANSMIT_COEFFICIENT_CONTROL 0x3408
54631 #define A_MAC_PORT_TX_LINKC_TRANSMIT_DRIVER_MODE_CONTROL 0x340c
54632 #define A_MAC_PORT_TX_LINKC_TRANSMIT_DRIVER_OVERRIDE_CONTROL 0x3410
54633 #define A_MAC_PORT_TX_LINKC_TRANSMIT_DCLK_ROTATOR_OVERRIDE 0x3414
54634 #define A_MAC_PORT_TX_LINKC_TRANSMIT_IMPEDANCE_CALIBRATION_OVERRIDE 0x3418
54635 
54636 #define S_T6_CALSSTN    8
54637 #define M_T6_CALSSTN    0x3fU
54638 #define V_T6_CALSSTN(x) ((x) << S_T6_CALSSTN)
54639 #define G_T6_CALSSTN(x) (((x) >> S_T6_CALSSTN) & M_T6_CALSSTN)
54640 
54641 #define S_T6_CALSSTP    0
54642 #define M_T6_CALSSTP    0x3fU
54643 #define V_T6_CALSSTP(x) ((x) << S_T6_CALSSTP)
54644 #define G_T6_CALSSTP(x) (((x) >> S_T6_CALSSTP) & M_T6_CALSSTP)
54645 
54646 #define A_MAC_PORT_TX_LINKC_TRANSMIT_DCLK_DRIFT_TOLERANCE 0x341c
54647 
54648 #define S_T6_DRTOL    2
54649 #define M_T6_DRTOL    0x7U
54650 #define V_T6_DRTOL(x) ((x) << S_T6_DRTOL)
54651 #define G_T6_DRTOL(x) (((x) >> S_T6_DRTOL) & M_T6_DRTOL)
54652 
54653 #define A_MAC_PORT_TX_LINKC_TRANSMIT_TAP_0_COEFFICIENT 0x3420
54654 
54655 #define S_T6_NXTT0    0
54656 #define M_T6_NXTT0    0x3fU
54657 #define V_T6_NXTT0(x) ((x) << S_T6_NXTT0)
54658 #define G_T6_NXTT0(x) (((x) >> S_T6_NXTT0) & M_T6_NXTT0)
54659 
54660 #define A_MAC_PORT_TX_LINKC_TRANSMIT_TAP_1_COEFFICIENT 0x3424
54661 #define A_MAC_PORT_TX_LINKC_TRANSMIT_TAP_2_COEFFICIENT 0x3428
54662 
54663 #define S_T6_NXTT2    0
54664 #define M_T6_NXTT2    0x3fU
54665 #define V_T6_NXTT2(x) ((x) << S_T6_NXTT2)
54666 #define G_T6_NXTT2(x) (((x) >> S_T6_NXTT2) & M_T6_NXTT2)
54667 
54668 #define A_MAC_PORT_TX_LINKC_TRANSMIT_TAP_3_COEFFICIENT 0x342c
54669 #define A_MAC_PORT_TX_LINKC_TRANSMIT_AMPLITUDE 0x3430
54670 #define A_MAC_PORT_TX_LINKC_TRANSMIT_POLARITY 0x3434
54671 
54672 #define S_T6_NXTPOL    0
54673 #define M_T6_NXTPOL    0xfU
54674 #define V_T6_NXTPOL(x) ((x) << S_T6_NXTPOL)
54675 #define G_T6_NXTPOL(x) (((x) >> S_T6_NXTPOL) & M_T6_NXTPOL)
54676 
54677 #define A_MAC_PORT_TX_LINKC_TRANSMIT_802_3AP_ADAPTIVE_EQUALIZATION_COMMAND 0x3438
54678 
54679 #define S_T6_C0UPDT    6
54680 #define M_T6_C0UPDT    0x3U
54681 #define V_T6_C0UPDT(x) ((x) << S_T6_C0UPDT)
54682 #define G_T6_C0UPDT(x) (((x) >> S_T6_C0UPDT) & M_T6_C0UPDT)
54683 
54684 #define S_T6_C2UPDT    2
54685 #define M_T6_C2UPDT    0x3U
54686 #define V_T6_C2UPDT(x) ((x) << S_T6_C2UPDT)
54687 #define G_T6_C2UPDT(x) (((x) >> S_T6_C2UPDT) & M_T6_C2UPDT)
54688 
54689 #define S_T6_C1UPDT    0
54690 #define M_T6_C1UPDT    0x3U
54691 #define V_T6_C1UPDT(x) ((x) << S_T6_C1UPDT)
54692 #define G_T6_C1UPDT(x) (((x) >> S_T6_C1UPDT) & M_T6_C1UPDT)
54693 
54694 #define A_MAC_PORT_TX_LINKC_TRANSMIT_802_3AP_ADAPTIVE_EQUALIZATION_STATUS 0x343c
54695 
54696 #define S_T6_C0STAT    6
54697 #define M_T6_C0STAT    0x3U
54698 #define V_T6_C0STAT(x) ((x) << S_T6_C0STAT)
54699 #define G_T6_C0STAT(x) (((x) >> S_T6_C0STAT) & M_T6_C0STAT)
54700 
54701 #define S_T6_C2STAT    2
54702 #define M_T6_C2STAT    0x3U
54703 #define V_T6_C2STAT(x) ((x) << S_T6_C2STAT)
54704 #define G_T6_C2STAT(x) (((x) >> S_T6_C2STAT) & M_T6_C2STAT)
54705 
54706 #define S_T6_C1STAT    0
54707 #define M_T6_C1STAT    0x3U
54708 #define V_T6_C1STAT(x) ((x) << S_T6_C1STAT)
54709 #define G_T6_C1STAT(x) (((x) >> S_T6_C1STAT) & M_T6_C1STAT)
54710 
54711 #define A_MAC_PORT_TX_LINKC_TRANSMIT_TAP_0_COEFFICIENT_OVERRIDE 0x3440
54712 #define A_MAC_PORT_TX_LINKC_TRANSMIT_AE_TAP_0_COEFFICIENT_OVERRIDE 0x3440
54713 #define A_MAC_PORT_TX_LINKC_TRANSMIT_TAP_1_COEFFICIENT_OVERRIDE 0x3444
54714 #define A_MAC_PORT_TX_LINKC_TRANSMIT_AE_TAP_1_COEFFICIENT_OVERRIDE 0x3444
54715 #define A_MAC_PORT_TX_LINKC_TRANSMIT_TAP_2_COEFFICIENT_OVERRIDE 0x3448
54716 #define A_MAC_PORT_TX_LINKC_TRANSMIT_AE_TAP_2_COEFFICIENT_OVERRIDE 0x3448
54717 #define A_MAC_PORT_TX_LINKC_TRANSMIT_AE_TAP_3_COEFFICIENT_OVERRIDE 0x344c
54718 #define A_MAC_PORT_TX_LINKC_TRANSMIT_APPLIED_TUNE_REGISTER 0x3450
54719 #define A_MAC_PORT_TX_LINKC_TRANSMIT_ANALOG_DIAGNOSTICS_REGISTER 0x3458
54720 #define A_MAC_PORT_TX_LINKC_TRANSMIT_TAP_0_COEFFICIENT_APPLIED 0x3460
54721 #define A_MAC_PORT_TX_LINKC_TRANSMIT_4X_SEGMENT_APPLIED 0x3460
54722 #define A_MAC_PORT_TX_LINKC_TRANSMIT_TAP_1_COEFFICIENT_APPLIED 0x3464
54723 #define A_MAC_PORT_TX_LINKC_TRANSMIT_2X_SEGMENT_APPLIED 0x3464
54724 #define A_MAC_PORT_TX_LINKC_TRANSMIT_TAP_2_COEFFICIENT_APPLIED 0x3468
54725 #define A_MAC_PORT_TX_LINKC_TRANSMIT_1X_SEGMENT_APPLIED 0x3468
54726 #define A_MAC_PORT_TX_LINKC_TRANSMIT_SEGMENT_4X_TERMINATION_APPLIED 0x346c
54727 #define A_MAC_PORT_TX_LINKC_TRANSMIT_SEGMENT_DISABLE_APPLIED_1 0x3470
54728 #define A_MAC_PORT_TX_LINKC_TRANSMIT_SEGMENT_2X1X_TERMINATION_APPLIED 0x3470
54729 #define A_MAC_PORT_TX_LINKC_TRANSMIT_SEGMENT_DISABLE_APPLIED_2 0x3474
54730 #define A_MAC_PORT_TX_LINKC_TRANSMIT_TAP_SIGN_APPLIED_REGISTER 0x3474
54731 #define A_MAC_PORT_TX_LINKC_TRANSMIT_EXTENDED_ADDRESS_DATA 0x3478
54732 #define A_MAC_PORT_TX_LINKC_TRANSMIT_EXTENDED_ADDRESS_ADDR 0x347c
54733 
54734 #define S_T6_XADDR    1
54735 #define M_T6_XADDR    0x1fU
54736 #define V_T6_XADDR(x) ((x) << S_T6_XADDR)
54737 #define G_T6_XADDR(x) (((x) >> S_T6_XADDR) & M_T6_XADDR)
54738 
54739 #define A_MAC_PORT_TX_LINKC_TRANSMIT_PATTERN_BUFFER_BYTES_1_0 0x3480
54740 #define A_MAC_PORT_TX_LINKC_TRANSMIT_PATTERN_BUFFER_BYTES_3_2 0x3484
54741 #define A_MAC_PORT_TX_LINKC_TRANSMIT_PATTERN_BUFFER_BYTE_4 0x3488
54742 #define A_MAC_PORT_TX_LINKC_TRANSMIT_PATTERN_BUFFER_BYTES_5_4 0x3488
54743 #define A_MAC_PORT_TX_LINKC_TRANSMIT_DCC_CONTROL 0x348c
54744 #define A_MAC_PORT_TX_LINKC_TRANSMIT_PATTERN_BUFFER_BYTES_7_6 0x348c
54745 #define A_MAC_PORT_TX_LINKC_TRANSMIT_DCC_OVERRIDE 0x3490
54746 #define A_MAC_PORT_TX_LINKC_TRANSMIT_DCC_APPLIED 0x3494
54747 #define A_MAC_PORT_TX_LINKC_TRANSMIT_DCC_TIME_OUT 0x3498
54748 #define A_MAC_PORT_TX_LINKC_TRANSMIT_802_3AZ_CONTROL 0x349c
54749 #define A_T6_MAC_PORT_TX_LINKC_TRANSMIT_DCC_CONTROL 0x34a0
54750 
54751 #define S_T6_DCCTIMEEN    13
54752 #define M_T6_DCCTIMEEN    0x3U
54753 #define V_T6_DCCTIMEEN(x) ((x) << S_T6_DCCTIMEEN)
54754 #define G_T6_DCCTIMEEN(x) (((x) >> S_T6_DCCTIMEEN) & M_T6_DCCTIMEEN)
54755 
54756 #define S_T6_DCCLOCK    11
54757 #define M_T6_DCCLOCK    0x3U
54758 #define V_T6_DCCLOCK(x) ((x) << S_T6_DCCLOCK)
54759 #define G_T6_DCCLOCK(x) (((x) >> S_T6_DCCLOCK) & M_T6_DCCLOCK)
54760 
54761 #define S_T6_DCCOFFSET    8
54762 #define M_T6_DCCOFFSET    0x7U
54763 #define V_T6_DCCOFFSET(x) ((x) << S_T6_DCCOFFSET)
54764 #define G_T6_DCCOFFSET(x) (((x) >> S_T6_DCCOFFSET) & M_T6_DCCOFFSET)
54765 
54766 #define S_TX_LINKC_DCCSTEP_CTL    6
54767 #define M_TX_LINKC_DCCSTEP_CTL    0x3U
54768 #define V_TX_LINKC_DCCSTEP_CTL(x) ((x) << S_TX_LINKC_DCCSTEP_CTL)
54769 #define G_TX_LINKC_DCCSTEP_CTL(x) (((x) >> S_TX_LINKC_DCCSTEP_CTL) & M_TX_LINKC_DCCSTEP_CTL)
54770 
54771 #define A_T6_MAC_PORT_TX_LINKC_TRANSMIT_DCC_OVERRIDE 0x34a4
54772 #define A_T6_MAC_PORT_TX_LINKC_TRANSMIT_DCC_APPLIED 0x34a8
54773 #define A_T6_MAC_PORT_TX_LINKC_TRANSMIT_DCC_TIME_OUT 0x34ac
54774 #define A_MAC_PORT_TX_LINKC_TRANSMIT_TAP_SIGN_OVERRIDE 0x34c0
54775 #define A_MAC_PORT_TX_LINKC_TRANSMIT_SEGMENT_4X_OVERRIDE 0x34c8
54776 #define A_MAC_PORT_TX_LINKC_TRANSMIT_SEGMENT_2X_OVERRIDE 0x34cc
54777 #define A_MAC_PORT_TX_LINKC_TRANSMIT_SEGMENT_1X_OVERRIDE 0x34d0
54778 #define A_MAC_PORT_TX_LINKC_TRANSMIT_TAP_SEGMENT_4X_TERMINATION_OVERRIDE 0x34d8
54779 #define A_MAC_PORT_TX_LINKC_TRANSMIT_TAP_SEGMENT_2X_TERMINATION_OVERRIDE 0x34dc
54780 #define A_MAC_PORT_TX_LINKC_TRANSMIT_TAP_SEGMENT_1X_TERMINATION_OVERRIDE 0x34e0
54781 #define A_MAC_PORT_TX_LINKC_TRANSMIT_MACRO_TEST_CONTROL_5 0x34ec
54782 #define A_MAC_PORT_TX_LINKC_TRANSMIT_MACRO_TEST_CONTROL_4 0x34f0
54783 
54784 #define S_T6_SDOVRD    0
54785 #define M_T6_SDOVRD    0xffffU
54786 #define V_T6_SDOVRD(x) ((x) << S_T6_SDOVRD)
54787 #define G_T6_SDOVRD(x) (((x) >> S_T6_SDOVRD) & M_T6_SDOVRD)
54788 
54789 #define A_MAC_PORT_TX_LINKC_TRANSMIT_MACRO_TEST_CONTROL_3 0x34f4
54790 #define A_MAC_PORT_TX_LINKC_TRANSMIT_MACRO_TEST_CONTROL_2 0x34f8
54791 #define A_MAC_PORT_TX_LINKC_TRANSMIT_MACRO_TEST_CONTROL_1 0x34fc
54792 
54793 #define S_T6_SDOVRDEN    15
54794 #define V_T6_SDOVRDEN(x) ((x) << S_T6_SDOVRDEN)
54795 #define F_T6_SDOVRDEN    V_T6_SDOVRDEN(1U)
54796 
54797 #define A_MAC_PORT_TX_LINKD_TRANSMIT_CONFIGURATION_MODE 0x3500
54798 
54799 #define S_T6_T5_TX_RXLOOP    5
54800 #define V_T6_T5_TX_RXLOOP(x) ((x) << S_T6_T5_TX_RXLOOP)
54801 #define F_T6_T5_TX_RXLOOP    V_T6_T5_TX_RXLOOP(1U)
54802 
54803 #define S_T6_T5_TX_BWSEL    2
54804 #define M_T6_T5_TX_BWSEL    0x3U
54805 #define V_T6_T5_TX_BWSEL(x) ((x) << S_T6_T5_TX_BWSEL)
54806 #define G_T6_T5_TX_BWSEL(x) (((x) >> S_T6_T5_TX_BWSEL) & M_T6_T5_TX_BWSEL)
54807 
54808 #define A_MAC_PORT_TX_LINKD_TRANSMIT_TEST_CONTROL 0x3504
54809 
54810 #define S_T6_ERROR    9
54811 #define V_T6_ERROR(x) ((x) << S_T6_ERROR)
54812 #define F_T6_ERROR    V_T6_ERROR(1U)
54813 
54814 #define A_MAC_PORT_TX_LINKD_TRANSMIT_COEFFICIENT_CONTROL 0x3508
54815 #define A_MAC_PORT_TX_LINKD_TRANSMIT_DRIVER_MODE_CONTROL 0x350c
54816 #define A_MAC_PORT_TX_LINKD_TRANSMIT_DRIVER_OVERRIDE_CONTROL 0x3510
54817 #define A_MAC_PORT_TX_LINKD_TRANSMIT_DCLK_ROTATOR_OVERRIDE 0x3514
54818 #define A_MAC_PORT_TX_LINKD_TRANSMIT_IMPEDANCE_CALIBRATION_OVERRIDE 0x3518
54819 
54820 #define S_T6_CALSSTN    8
54821 #define M_T6_CALSSTN    0x3fU
54822 #define V_T6_CALSSTN(x) ((x) << S_T6_CALSSTN)
54823 #define G_T6_CALSSTN(x) (((x) >> S_T6_CALSSTN) & M_T6_CALSSTN)
54824 
54825 #define S_T6_CALSSTP    0
54826 #define M_T6_CALSSTP    0x3fU
54827 #define V_T6_CALSSTP(x) ((x) << S_T6_CALSSTP)
54828 #define G_T6_CALSSTP(x) (((x) >> S_T6_CALSSTP) & M_T6_CALSSTP)
54829 
54830 #define A_MAC_PORT_TX_LINKD_TRANSMIT_DCLK_DRIFT_TOLERANCE 0x351c
54831 
54832 #define S_T6_DRTOL    2
54833 #define M_T6_DRTOL    0x7U
54834 #define V_T6_DRTOL(x) ((x) << S_T6_DRTOL)
54835 #define G_T6_DRTOL(x) (((x) >> S_T6_DRTOL) & M_T6_DRTOL)
54836 
54837 #define A_MAC_PORT_TX_LINKD_TRANSMIT_TAP_0_COEFFICIENT 0x3520
54838 
54839 #define S_T6_NXTT0    0
54840 #define M_T6_NXTT0    0x3fU
54841 #define V_T6_NXTT0(x) ((x) << S_T6_NXTT0)
54842 #define G_T6_NXTT0(x) (((x) >> S_T6_NXTT0) & M_T6_NXTT0)
54843 
54844 #define A_MAC_PORT_TX_LINKD_TRANSMIT_TAP_1_COEFFICIENT 0x3524
54845 #define A_MAC_PORT_TX_LINKD_TRANSMIT_TAP_2_COEFFICIENT 0x3528
54846 
54847 #define S_T6_NXTT2    0
54848 #define M_T6_NXTT2    0x3fU
54849 #define V_T6_NXTT2(x) ((x) << S_T6_NXTT2)
54850 #define G_T6_NXTT2(x) (((x) >> S_T6_NXTT2) & M_T6_NXTT2)
54851 
54852 #define A_MAC_PORT_TX_LINKD_TRANSMIT_TAP_3_COEFFICIENT 0x352c
54853 #define A_MAC_PORT_TX_LINKD_TRANSMIT_AMPLITUDE 0x3530
54854 #define A_MAC_PORT_TX_LINKD_TRANSMIT_POLARITY 0x3534
54855 
54856 #define S_T6_NXTPOL    0
54857 #define M_T6_NXTPOL    0xfU
54858 #define V_T6_NXTPOL(x) ((x) << S_T6_NXTPOL)
54859 #define G_T6_NXTPOL(x) (((x) >> S_T6_NXTPOL) & M_T6_NXTPOL)
54860 
54861 #define A_MAC_PORT_TX_LINKD_TRANSMIT_802_3AP_ADAPTIVE_EQUALIZATION_COMMAND 0x3538
54862 
54863 #define S_T6_C0UPDT    6
54864 #define M_T6_C0UPDT    0x3U
54865 #define V_T6_C0UPDT(x) ((x) << S_T6_C0UPDT)
54866 #define G_T6_C0UPDT(x) (((x) >> S_T6_C0UPDT) & M_T6_C0UPDT)
54867 
54868 #define S_T6_C2UPDT    2
54869 #define M_T6_C2UPDT    0x3U
54870 #define V_T6_C2UPDT(x) ((x) << S_T6_C2UPDT)
54871 #define G_T6_C2UPDT(x) (((x) >> S_T6_C2UPDT) & M_T6_C2UPDT)
54872 
54873 #define S_T6_C1UPDT    0
54874 #define M_T6_C1UPDT    0x3U
54875 #define V_T6_C1UPDT(x) ((x) << S_T6_C1UPDT)
54876 #define G_T6_C1UPDT(x) (((x) >> S_T6_C1UPDT) & M_T6_C1UPDT)
54877 
54878 #define A_MAC_PORT_TX_LINKD_TRANSMIT_802_3AP_ADAPTIVE_EQUALIZATION_STATUS 0x353c
54879 
54880 #define S_T6_C0STAT    6
54881 #define M_T6_C0STAT    0x3U
54882 #define V_T6_C0STAT(x) ((x) << S_T6_C0STAT)
54883 #define G_T6_C0STAT(x) (((x) >> S_T6_C0STAT) & M_T6_C0STAT)
54884 
54885 #define S_T6_C2STAT    2
54886 #define M_T6_C2STAT    0x3U
54887 #define V_T6_C2STAT(x) ((x) << S_T6_C2STAT)
54888 #define G_T6_C2STAT(x) (((x) >> S_T6_C2STAT) & M_T6_C2STAT)
54889 
54890 #define S_T6_C1STAT    0
54891 #define M_T6_C1STAT    0x3U
54892 #define V_T6_C1STAT(x) ((x) << S_T6_C1STAT)
54893 #define G_T6_C1STAT(x) (((x) >> S_T6_C1STAT) & M_T6_C1STAT)
54894 
54895 #define A_MAC_PORT_TX_LINKD_TRANSMIT_TAP_0_COEFFICIENT_OVERRIDE 0x3540
54896 #define A_MAC_PORT_TX_LINKD_TRANSMIT_AE_TAP_0_COEFFICIENT_OVERRIDE 0x3540
54897 #define A_MAC_PORT_TX_LINKD_TRANSMIT_TAP_1_COEFFICIENT_OVERRIDE 0x3544
54898 #define A_MAC_PORT_TX_LINKD_TRANSMIT_AE_TAP_1_COEFFICIENT_OVERRIDE 0x3544
54899 #define A_MAC_PORT_TX_LINKD_TRANSMIT_TAP_2_COEFFICIENT_OVERRIDE 0x3548
54900 #define A_MAC_PORT_TX_LINKD_TRANSMIT_AE_TAP_2_COEFFICIENT_OVERRIDE 0x3548
54901 #define A_MAC_PORT_TX_LINKD_TRANSMIT_AE_TAP_3_COEFFICIENT_OVERRIDE 0x354c
54902 #define A_MAC_PORT_TX_LINKD_TRANSMIT_APPLIED_TUNE_REGISTER 0x3550
54903 #define A_MAC_PORT_TX_LINKD_TRANSMIT_ANALOG_DIAGNOSTICS_REGISTER 0x3558
54904 #define A_MAC_PORT_TX_LINKD_TRANSMIT_TAP_0_COEFFICIENT_APPLIED 0x3560
54905 #define A_MAC_PORT_TX_LINKD_TRANSMIT_4X_SEGMENT_APPLIED 0x3560
54906 #define A_MAC_PORT_TX_LINKD_TRANSMIT_TAP_1_COEFFICIENT_APPLIED 0x3564
54907 #define A_MAC_PORT_TX_LINKD_TRANSMIT_2X_SEGMENT_APPLIED 0x3564
54908 #define A_MAC_PORT_TX_LINKD_TRANSMIT_TAP_2_COEFFICIENT_APPLIED 0x3568
54909 #define A_MAC_PORT_TX_LINKD_TRANSMIT_1X_SEGMENT_APPLIED 0x3568
54910 #define A_MAC_PORT_TX_LINKD_TRANSMIT_SEGMENT_4X_TERMINATION_APPLIED 0x356c
54911 #define A_MAC_PORT_TX_LINKD_TRANSMIT_SEGMENT_DISABLE_APPLIED_1 0x3570
54912 #define A_MAC_PORT_TX_LINKD_TRANSMIT_SEGMENT_2X1X_TERMINATION_APPLIED 0x3570
54913 #define A_MAC_PORT_TX_LINKD_TRANSMIT_SEGMENT_DISABLE_APPLIED_2 0x3574
54914 #define A_MAC_PORT_TX_LINKD_TRANSMIT_TAP_SIGN_APPLIED_REGISTER 0x3574
54915 #define A_MAC_PORT_TX_LINKD_TRANSMIT_EXTENDED_ADDRESS_DATA 0x3578
54916 #define A_MAC_PORT_TX_LINKD_TRANSMIT_EXTENDED_ADDRESS_ADDR 0x357c
54917 
54918 #define S_T6_XADDR    1
54919 #define M_T6_XADDR    0x1fU
54920 #define V_T6_XADDR(x) ((x) << S_T6_XADDR)
54921 #define G_T6_XADDR(x) (((x) >> S_T6_XADDR) & M_T6_XADDR)
54922 
54923 #define A_MAC_PORT_TX_LINKD_TRANSMIT_PATTERN_BUFFER_BYTES_1_0 0x3580
54924 #define A_MAC_PORT_TX_LINKD_TRANSMIT_PATTERN_BUFFER_BYTES_3_2 0x3584
54925 #define A_MAC_PORT_TX_LINKD_TRANSMIT_PATTERN_BUFFER_BYTE_4 0x3588
54926 #define A_MAC_PORT_TX_LINKD_TRANSMIT_PATTERN_BUFFER_BYTES_5_4 0x3588
54927 #define A_MAC_PORT_TX_LINKD_TRANSMIT_DCC_CONTROL 0x358c
54928 #define A_MAC_PORT_TX_LINKD_TRANSMIT_PATTERN_BUFFER_BYTES_7_6 0x358c
54929 #define A_MAC_PORT_TX_LINKD_TRANSMIT_DCC_OVERRIDE 0x3590
54930 #define A_MAC_PORT_TX_LINKD_TRANSMIT_DCC_APPLIED 0x3594
54931 #define A_MAC_PORT_TX_LINKD_TRANSMIT_DCC_TIME_OUT 0x3598
54932 #define A_MAC_PORT_TX_LINKD_TRANSMIT_802_3AZ_CONTROL 0x359c
54933 #define A_T6_MAC_PORT_TX_LINKD_TRANSMIT_DCC_CONTROL 0x35a0
54934 
54935 #define S_T6_DCCTIMEEN    13
54936 #define M_T6_DCCTIMEEN    0x3U
54937 #define V_T6_DCCTIMEEN(x) ((x) << S_T6_DCCTIMEEN)
54938 #define G_T6_DCCTIMEEN(x) (((x) >> S_T6_DCCTIMEEN) & M_T6_DCCTIMEEN)
54939 
54940 #define S_T6_DCCLOCK    11
54941 #define M_T6_DCCLOCK    0x3U
54942 #define V_T6_DCCLOCK(x) ((x) << S_T6_DCCLOCK)
54943 #define G_T6_DCCLOCK(x) (((x) >> S_T6_DCCLOCK) & M_T6_DCCLOCK)
54944 
54945 #define S_T6_DCCOFFSET    8
54946 #define M_T6_DCCOFFSET    0x7U
54947 #define V_T6_DCCOFFSET(x) ((x) << S_T6_DCCOFFSET)
54948 #define G_T6_DCCOFFSET(x) (((x) >> S_T6_DCCOFFSET) & M_T6_DCCOFFSET)
54949 
54950 #define S_TX_LINKD_DCCSTEP_CTL    6
54951 #define M_TX_LINKD_DCCSTEP_CTL    0x3U
54952 #define V_TX_LINKD_DCCSTEP_CTL(x) ((x) << S_TX_LINKD_DCCSTEP_CTL)
54953 #define G_TX_LINKD_DCCSTEP_CTL(x) (((x) >> S_TX_LINKD_DCCSTEP_CTL) & M_TX_LINKD_DCCSTEP_CTL)
54954 
54955 #define A_T6_MAC_PORT_TX_LINKD_TRANSMIT_DCC_OVERRIDE 0x35a4
54956 #define A_T6_MAC_PORT_TX_LINKD_TRANSMIT_DCC_APPLIED 0x35a8
54957 #define A_T6_MAC_PORT_TX_LINKD_TRANSMIT_DCC_TIME_OUT 0x35ac
54958 #define A_MAC_PORT_TX_LINKD_TRANSMIT_TAP_SIGN_OVERRIDE 0x35c0
54959 #define A_MAC_PORT_TX_LINKD_TRANSMIT_SEGMENT_4X_OVERRIDE 0x35c8
54960 #define A_MAC_PORT_TX_LINKD_TRANSMIT_SEGMENT_2X_OVERRIDE 0x35cc
54961 #define A_MAC_PORT_TX_LINKD_TRANSMIT_SEGMENT_1X_OVERRIDE 0x35d0
54962 #define A_MAC_PORT_TX_LINKD_TRANSMIT_TAP_SEGMENT_4X_TERMINATION_OVERRIDE 0x35d8
54963 #define A_MAC_PORT_TX_LINKD_TRANSMIT_TAP_SEGMENT_2X_TERMINATION_OVERRIDE 0x35dc
54964 #define A_MAC_PORT_TX_LINKD_TRANSMIT_TAP_SEGMENT_1X_TERMINATION_OVERRIDE 0x35e0
54965 #define A_MAC_PORT_TX_LINKD_TRANSMIT_MACRO_TEST_CONTROL_5 0x35ec
54966 #define A_MAC_PORT_TX_LINKD_TRANSMIT_MACRO_TEST_CONTROL_4 0x35f0
54967 
54968 #define S_T6_SDOVRD    0
54969 #define M_T6_SDOVRD    0xffffU
54970 #define V_T6_SDOVRD(x) ((x) << S_T6_SDOVRD)
54971 #define G_T6_SDOVRD(x) (((x) >> S_T6_SDOVRD) & M_T6_SDOVRD)
54972 
54973 #define A_MAC_PORT_TX_LINKD_TRANSMIT_MACRO_TEST_CONTROL_3 0x35f4
54974 #define A_MAC_PORT_TX_LINKD_TRANSMIT_MACRO_TEST_CONTROL_2 0x35f8
54975 #define A_MAC_PORT_TX_LINKD_TRANSMIT_MACRO_TEST_CONTROL_1 0x35fc
54976 
54977 #define S_T6_SDOVRDEN    15
54978 #define V_T6_SDOVRDEN(x) ((x) << S_T6_SDOVRDEN)
54979 #define F_T6_SDOVRDEN    V_T6_SDOVRDEN(1U)
54980 
54981 #define A_MAC_PORT_RX_LINKC_RECEIVER_CONFIGURATION_MODE 0x3600
54982 #define A_MAC_PORT_RX_LINKC_RECEIVER_TEST_CONTROL 0x3604
54983 #define A_MAC_PORT_RX_LINKC_PHASE_ROTATOR_CONTROL 0x3608
54984 #define A_MAC_PORT_RX_LINKC_PHASE_ROTATOR_OFFSET_CONTROL 0x360c
54985 
54986 #define S_T6_TMSCAL    8
54987 #define M_T6_TMSCAL    0x3U
54988 #define V_T6_TMSCAL(x) ((x) << S_T6_TMSCAL)
54989 #define G_T6_TMSCAL(x) (((x) >> S_T6_TMSCAL) & M_T6_TMSCAL)
54990 
54991 #define S_T6_APADJ    7
54992 #define V_T6_APADJ(x) ((x) << S_T6_APADJ)
54993 #define F_T6_APADJ    V_T6_APADJ(1U)
54994 
54995 #define S_T6_RSEL    6
54996 #define V_T6_RSEL(x) ((x) << S_T6_RSEL)
54997 #define F_T6_RSEL    V_T6_RSEL(1U)
54998 
54999 #define S_T6_PHOFFS    0
55000 #define M_T6_PHOFFS    0x3fU
55001 #define V_T6_PHOFFS(x) ((x) << S_T6_PHOFFS)
55002 #define G_T6_PHOFFS(x) (((x) >> S_T6_PHOFFS) & M_T6_PHOFFS)
55003 
55004 #define A_MAC_PORT_RX_LINKC_PHASE_ROTATOR_POSITION_1 0x3610
55005 #define A_MAC_PORT_RX_LINKC_PHASE_ROTATOR_POSITION_2 0x3614
55006 #define A_MAC_PORT_RX_LINKC_PHASE_ROTATOR_STATIC_PHASE_OFFSET_1 0x3618
55007 #define A_MAC_PORT_RX_LINKC_PHASE_ROTATOR_STATIC_PHASE_OFFSET_2 0x361c
55008 #define A_MAC_PORT_RX_LINKC_DFE_CONTROL 0x3620
55009 
55010 #define S_T6_SPIFMT    8
55011 #define M_T6_SPIFMT    0xfU
55012 #define V_T6_SPIFMT(x) ((x) << S_T6_SPIFMT)
55013 #define G_T6_SPIFMT(x) (((x) >> S_T6_SPIFMT) & M_T6_SPIFMT)
55014 
55015 #define A_MAC_PORT_RX_LINKC_DFE_SAMPLE_SNAPSHOT_1 0x3624
55016 #define A_MAC_PORT_RX_LINKC_DFE_SAMPLE_SNAPSHOT_2 0x3628
55017 #define A_MAC_PORT_RX_LINKC_RECEIVER_VGA_CONTROL_1 0x362c
55018 
55019 #define S_T6_WRAPSEL    15
55020 #define V_T6_WRAPSEL(x) ((x) << S_T6_WRAPSEL)
55021 #define F_T6_WRAPSEL    V_T6_WRAPSEL(1U)
55022 
55023 #define S_T6_PEAK    9
55024 #define M_T6_PEAK    0x1fU
55025 #define V_T6_PEAK(x) ((x) << S_T6_PEAK)
55026 #define G_T6_PEAK(x) (((x) >> S_T6_PEAK) & M_T6_PEAK)
55027 
55028 #define A_MAC_PORT_RX_LINKC_RECEIVER_VGA_CONTROL_2 0x3630
55029 
55030 #define S_T6_T5VGAIN    0
55031 #define M_T6_T5VGAIN    0x7fU
55032 #define V_T6_T5VGAIN(x) ((x) << S_T6_T5VGAIN)
55033 #define G_T6_T5VGAIN(x) (((x) >> S_T6_T5VGAIN) & M_T6_T5VGAIN)
55034 
55035 #define A_MAC_PORT_RX_LINKC_RECEIVER_VGA_CONTROL_3 0x3634
55036 #define A_MAC_PORT_RX_LINKC_RECEIVER_DQCC_CONTROL_1 0x3638
55037 #define A_MAC_PORT_RX_LINKC_RECEIVER_POWER_MANAGEMENT_CONTROL 0x3638
55038 #define A_MAC_PORT_RX_LINKC_RECEIVER_IQAMP_CONTROL_1 0x363c
55039 #define A_MAC_PORT_RX_LINKC_RECEIVER_DQCC_CONTROL_3 0x3640
55040 #define A_MAC_PORT_RX_LINKC_RECEIVER_IQAMP_CONTROL_2 0x3640
55041 #define A_MAC_PORT_RX_LINKC_RECEIVER_DACAP_AND_DACAN_SELECTION 0x3644
55042 #define A_MAC_PORT_RX_LINKC_RECEIVER_DACAP_AND_DACAN 0x3648
55043 #define A_MAC_PORT_RX_LINKC_RECEIVER_DACA_MIN_AND_DACAZ 0x364c
55044 #define A_MAC_PORT_RX_LINKC_RECEIVER_DACA_MIN 0x364c
55045 #define A_MAC_PORT_RX_LINKC_RECEIVER_ADAC_CONTROL 0x3650
55046 #define A_MAC_PORT_RX_LINKC_RECEIVER_AC_COUPLING_CONTROL 0x3654
55047 #define A_MAC_PORT_RX_LINKC_RECEIVER_AC_COUPLING_VALUE 0x3658
55048 #define A_MAC_PORT_RX_LINKC_DFE_H1_LOCAL_OFFSET_ODD2_EVN2 0x365c
55049 #define A_MAC_PORT_RX_LINKC_DFE_H1H2H3_LOCAL_OFFSET 0x365c
55050 #define A_MAC_PORT_RX_LINKC_DFE_H1_LOCAL_OFFSET_ODD3_EVN3 0x3660
55051 #define A_MAC_PORT_RX_LINKC_DFE_H1H2H3_LOCAL_OFFSET_VALUE 0x3660
55052 #define A_MAC_PORT_RX_LINKC_DFE_H1_LOCAL_OFFSET_ODD4_EVN4 0x3664
55053 #define A_MAC_PORT_RX_LINKC_PEAKED_INTEGRATOR 0x3664
55054 #define A_MAC_PORT_RX_LINKC_CDR_ANALOG_SWITCH 0x3668
55055 #define A_MAC_PORT_RX_LINKC_PEAKING_AMPLIFIER_INTIALIZATION_CONTROL 0x366c
55056 #define A_MAC_PORT_RX_LINKC_DYNAMIC_AMPLITUDE_CENTERING_DAC_AND_DYNAMIC_PEAKING_CONTROL_DPC 0x3670
55057 #define A_MAC_PORT_RX_LINKC_DYNAMIC_DATA_CENTERING_DDC 0x3674
55058 
55059 #define S_T6_ODEC    0
55060 #define M_T6_ODEC    0xfU
55061 #define V_T6_ODEC(x) ((x) << S_T6_ODEC)
55062 #define G_T6_ODEC(x) (((x) >> S_T6_ODEC) & M_T6_ODEC)
55063 
55064 #define A_MAC_PORT_RX_LINKC_RECEIVER_INTERNAL_STATUS 0x3678
55065 
55066 #define S_RX_LINKC_ACCCMP_RIS    11
55067 #define V_RX_LINKC_ACCCMP_RIS(x) ((x) << S_RX_LINKC_ACCCMP_RIS)
55068 #define F_RX_LINKC_ACCCMP_RIS    V_RX_LINKC_ACCCMP_RIS(1U)
55069 
55070 #define A_MAC_PORT_RX_LINKC_DFE_FUNCTION_CONTROL_1 0x367c
55071 #define A_MAC_PORT_RX_LINKC_DFE_FUNCTION_CONTROL_2 0x3680
55072 #define A_MAC_PORT_RX_LINKC_DFE_OFFSET_EVN1_EVN2 0x3684
55073 #define A_MAC_PORT_RX_LINKC_DFE_OFFSET_CHANNEL 0x3684
55074 #define A_MAC_PORT_RX_LINKC_DFE_OFFSET_ODD1_ODD2 0x3688
55075 #define A_MAC_PORT_RX_LINKC_DFE_OFFSET_VALUE 0x3688
55076 #define A_MAC_PORT_RX_LINKC_DFE_OFFSET_EVN3_EVN4 0x368c
55077 #define A_MAC_PORT_RX_LINKC_H_COEFFICIENBT_BIST 0x368c
55078 #define A_MAC_PORT_RX_LINKC_DFE_OFFSET_ODD3_ODD4 0x3690
55079 #define A_MAC_PORT_RX_LINKC_AC_CAPACITOR_BIST 0x3690
55080 
55081 #define S_RX_LINKC_ACCCMP_BIST    13
55082 #define V_RX_LINKC_ACCCMP_BIST(x) ((x) << S_RX_LINKC_ACCCMP_BIST)
55083 #define F_RX_LINKC_ACCCMP_BIST    V_RX_LINKC_ACCCMP_BIST(1U)
55084 
55085 #define A_MAC_PORT_RX_LINKC_DFE_E0_AND_E1_OFFSET 0x3694
55086 #define A_MAC_PORT_RX_LINKC_RECEIVER_LOFF_CONTROL 0x3698
55087 #define A_MAC_PORT_RX_LINKC_RECEIVER_LOFF_CONTROL_REGISTER 0x3698
55088 #define A_MAC_PORT_RX_LINKC_RECEIVER_SIGDET_CONTROL 0x369c
55089 #define A_MAC_PORT_RX_LINKC_RECEIVER_ANALOG_CONTROL_SWITCH 0x36a0
55090 #define A_MAC_PORT_RX_LINKC_INTEGRATOR_DAC_OFFSET 0x36a4
55091 #define A_MAC_PORT_RX_LINKC_DIGITAL_EYE_CONTROL 0x36a8
55092 #define A_MAC_PORT_RX_LINKC_DIGITAL_EYE_METRICS 0x36ac
55093 
55094 #define S_T6_EMMD    3
55095 #define M_T6_EMMD    0x3U
55096 #define V_T6_EMMD(x) ((x) << S_T6_EMMD)
55097 #define G_T6_EMMD(x) (((x) >> S_T6_EMMD) & M_T6_EMMD)
55098 
55099 #define S_T6_EMBRDY    2
55100 #define V_T6_EMBRDY(x) ((x) << S_T6_EMBRDY)
55101 #define F_T6_EMBRDY    V_T6_EMBRDY(1U)
55102 
55103 #define S_T6_EMBUMP    1
55104 #define V_T6_EMBUMP(x) ((x) << S_T6_EMBUMP)
55105 #define F_T6_EMBUMP    V_T6_EMBUMP(1U)
55106 
55107 #define A_MAC_PORT_RX_LINKC_DIGITAL_EYE_METRICS_ERROR_COUNT 0x36b0
55108 #define A_MAC_PORT_RX_LINKC_DIGITAL_EYE_METRICS_PDF_EYE_COUNT 0x36b4
55109 #define A_MAC_PORT_RX_LINKC_DIGITAL_EYE_METRICS_PATTERN_LENGTH 0x36b8
55110 #define A_MAC_PORT_RX_LINKC_DFE_FUNCTION_CONTROL_3 0x36bc
55111 #define A_MAC_PORT_RX_LINKC_DFE_TAP_ENABLE 0x36c0
55112 #define A_MAC_PORT_RX_LINKC_DFE_TAP_CONTROL 0x36c0
55113 
55114 #define S_RX_LINKC_INDEX_DFE_TC    0
55115 #define M_RX_LINKC_INDEX_DFE_TC    0xfU
55116 #define V_RX_LINKC_INDEX_DFE_TC(x) ((x) << S_RX_LINKC_INDEX_DFE_TC)
55117 #define G_RX_LINKC_INDEX_DFE_TC(x) (((x) >> S_RX_LINKC_INDEX_DFE_TC) & M_RX_LINKC_INDEX_DFE_TC)
55118 
55119 #define A_MAC_PORT_RX_LINKC_DFE_H1 0x36c4
55120 #define A_MAC_PORT_RX_LINKC_DFE_TAP 0x36c4
55121 
55122 #define S_RX_LINKC_INDEX_DFE_TAP    0
55123 #define M_RX_LINKC_INDEX_DFE_TAP    0xfU
55124 #define V_RX_LINKC_INDEX_DFE_TAP(x) ((x) << S_RX_LINKC_INDEX_DFE_TAP)
55125 #define G_RX_LINKC_INDEX_DFE_TAP(x) (((x) >> S_RX_LINKC_INDEX_DFE_TAP) & M_RX_LINKC_INDEX_DFE_TAP)
55126 
55127 #define A_MAC_PORT_RX_LINKC_DFE_H2 0x36c8
55128 #define A_MAC_PORT_RX_LINKC_DFE_H3 0x36cc
55129 #define A_MAC_PORT_RX_LINKC_DFE_H4 0x36d0
55130 #define A_MAC_PORT_RX_LINKC_DFE_H5 0x36d4
55131 #define A_MAC_PORT_RX_LINKC_DFE_H6_AND_H7 0x36d8
55132 #define A_MAC_PORT_RX_LINKC_DFE_H8_AND_H9 0x36dc
55133 #define A_MAC_PORT_RX_LINKC_DFE_H10_AND_H11 0x36e0
55134 #define A_MAC_PORT_RX_LINKC_DFE_H12 0x36e4
55135 #define A_MAC_PORT_RX_LINKC_RECEIVER_INTERNAL_STATUS_2 0x36e4
55136 #define A_MAC_PORT_RX_LINKC_AC_COUPLING_CURRENT_SOURCE_ADJUST 0x36e8
55137 #define A_MAC_PORT_RX_LINKC_RECEIVER_DCD_CONTROL 0x36ec
55138 #define A_MAC_PORT_RX_LINKC_RECEIVER_DCC_CONTROL 0x36f0
55139 
55140 #define S_RX_LINKC_DCCSTEP_RXCTL    10
55141 #define M_RX_LINKC_DCCSTEP_RXCTL    0x3U
55142 #define V_RX_LINKC_DCCSTEP_RXCTL(x) ((x) << S_RX_LINKC_DCCSTEP_RXCTL)
55143 #define G_RX_LINKC_DCCSTEP_RXCTL(x) (((x) >> S_RX_LINKC_DCCSTEP_RXCTL) & M_RX_LINKC_DCCSTEP_RXCTL)
55144 
55145 #define S_RX_LINKC_DCCLOCK_RXCTL    8
55146 #define V_RX_LINKC_DCCLOCK_RXCTL(x) ((x) << S_RX_LINKC_DCCLOCK_RXCTL)
55147 #define F_RX_LINKC_DCCLOCK_RXCTL    V_RX_LINKC_DCCLOCK_RXCTL(1U)
55148 
55149 #define A_MAC_PORT_RX_LINKC_RECEIVER_QCC_CONTROL 0x36f4
55150 #define A_MAC_PORT_RX_LINKC_RECEIVER_MACRO_TEST_CONTROL_2 0x36f8
55151 #define A_MAC_PORT_RX_LINKC_RECEIVER_MACRO_TEST_CONTROL_REGISTER_2 0x36f8
55152 #define A_MAC_PORT_RX_LINKC_RECEIVER_MACRO_TEST_CONTROL_1 0x36fc
55153 #define A_MAC_PORT_RX_LINKD_RECEIVER_CONFIGURATION_MODE 0x3700
55154 #define A_MAC_PORT_RX_LINKD_RECEIVER_TEST_CONTROL 0x3704
55155 #define A_MAC_PORT_RX_LINKD_PHASE_ROTATOR_CONTROL 0x3708
55156 #define A_MAC_PORT_RX_LINKD_PHASE_ROTATOR_OFFSET_CONTROL 0x370c
55157 
55158 #define S_T6_TMSCAL    8
55159 #define M_T6_TMSCAL    0x3U
55160 #define V_T6_TMSCAL(x) ((x) << S_T6_TMSCAL)
55161 #define G_T6_TMSCAL(x) (((x) >> S_T6_TMSCAL) & M_T6_TMSCAL)
55162 
55163 #define S_T6_APADJ    7
55164 #define V_T6_APADJ(x) ((x) << S_T6_APADJ)
55165 #define F_T6_APADJ    V_T6_APADJ(1U)
55166 
55167 #define S_T6_RSEL    6
55168 #define V_T6_RSEL(x) ((x) << S_T6_RSEL)
55169 #define F_T6_RSEL    V_T6_RSEL(1U)
55170 
55171 #define S_T6_PHOFFS    0
55172 #define M_T6_PHOFFS    0x3fU
55173 #define V_T6_PHOFFS(x) ((x) << S_T6_PHOFFS)
55174 #define G_T6_PHOFFS(x) (((x) >> S_T6_PHOFFS) & M_T6_PHOFFS)
55175 
55176 #define A_MAC_PORT_RX_LINKD_PHASE_ROTATOR_POSITION_1 0x3710
55177 #define A_MAC_PORT_RX_LINKD_PHASE_ROTATOR_POSITION_2 0x3714
55178 #define A_MAC_PORT_RX_LINKD_PHASE_ROTATOR_STATIC_PHASE_OFFSET_1 0x3718
55179 #define A_MAC_PORT_RX_LINKD_PHASE_ROTATOR_STATIC_PHASE_OFFSET_2 0x371c
55180 #define A_MAC_PORT_RX_LINKD_DFE_CONTROL 0x3720
55181 
55182 #define S_T6_SPIFMT    8
55183 #define M_T6_SPIFMT    0xfU
55184 #define V_T6_SPIFMT(x) ((x) << S_T6_SPIFMT)
55185 #define G_T6_SPIFMT(x) (((x) >> S_T6_SPIFMT) & M_T6_SPIFMT)
55186 
55187 #define A_MAC_PORT_RX_LINKD_DFE_SAMPLE_SNAPSHOT_1 0x3724
55188 #define A_MAC_PORT_RX_LINKD_DFE_SAMPLE_SNAPSHOT_2 0x3728
55189 #define A_MAC_PORT_RX_LINKD_RECEIVER_VGA_CONTROL_1 0x372c
55190 
55191 #define S_T6_WRAPSEL    15
55192 #define V_T6_WRAPSEL(x) ((x) << S_T6_WRAPSEL)
55193 #define F_T6_WRAPSEL    V_T6_WRAPSEL(1U)
55194 
55195 #define S_T6_PEAK    9
55196 #define M_T6_PEAK    0x1fU
55197 #define V_T6_PEAK(x) ((x) << S_T6_PEAK)
55198 #define G_T6_PEAK(x) (((x) >> S_T6_PEAK) & M_T6_PEAK)
55199 
55200 #define A_MAC_PORT_RX_LINKD_RECEIVER_VGA_CONTROL_2 0x3730
55201 
55202 #define S_T6_T5VGAIN    0
55203 #define M_T6_T5VGAIN    0x7fU
55204 #define V_T6_T5VGAIN(x) ((x) << S_T6_T5VGAIN)
55205 #define G_T6_T5VGAIN(x) (((x) >> S_T6_T5VGAIN) & M_T6_T5VGAIN)
55206 
55207 #define A_MAC_PORT_RX_LINKD_RECEIVER_VGA_CONTROL_3 0x3734
55208 #define A_MAC_PORT_RX_LINKD_RECEIVER_DQCC_CONTROL_1 0x3738
55209 #define A_MAC_PORT_RX_LINKD_RECEIVER_POWER_MANAGEMENT_CONTROL 0x3738
55210 #define A_MAC_PORT_RX_LINKD_RECEIVER_IQAMP_CONTROL_1 0x373c
55211 #define A_MAC_PORT_RX_LINKD_RECEIVER_DQCC_CONTROL_3 0x3740
55212 #define A_MAC_PORT_RX_LINKD_RECEIVER_IQAMP_CONTROL_2 0x3740
55213 #define A_MAC_PORT_RX_LINKD_RECEIVER_DACAP_AND_DACAN_SELECTION 0x3744
55214 #define A_MAC_PORT_RX_LINKD_RECEIVER_DACAP_AND_DACAN 0x3748
55215 #define A_MAC_PORT_RX_LINKD_RECEIVER_DACA_MIN_AND_DACAZ 0x374c
55216 #define A_MAC_PORT_RX_LINKD_RECEIVER_DACA_MIN 0x374c
55217 #define A_MAC_PORT_RX_LINKD_RECEIVER_ADAC_CONTROL 0x3750
55218 #define A_MAC_PORT_RX_LINKD_RECEIVER_AC_COUPLING_CONTROL 0x3754
55219 #define A_MAC_PORT_RX_LINKD_RECEIVER_AC_COUPLING_VALUE 0x3758
55220 #define A_MAC_PORT_RX_LINKD_DFE_H1_LOCAL_OFFSET_ODD2_EVN2 0x375c
55221 #define A_MAC_PORT_RX_LINKD_DFE_H1H2H3_LOCAL_OFFSET 0x375c
55222 #define A_MAC_PORT_RX_LINKD_DFE_H1_LOCAL_OFFSET_ODD3_EVN3 0x3760
55223 #define A_MAC_PORT_RX_LINKD_DFE_H1H2H3_LOCAL_OFFSET_VALUE 0x3760
55224 #define A_MAC_PORT_RX_LINKD_DFE_H1_LOCAL_OFFSET_ODD4_EVN4 0x3764
55225 #define A_MAC_PORT_RX_LINKD_PEAKED_INTEGRATOR 0x3764
55226 #define A_MAC_PORT_RX_LINKD_CDR_ANALOG_SWITCH 0x3768
55227 #define A_MAC_PORT_RX_LINKD_PEAKING_AMPLIFIER_INTIALIZATION_CONTROL 0x376c
55228 #define A_MAC_PORT_RX_LINKD_DYNAMIC_AMPLITUDE_CENTERING_DAC_AND_DYNAMIC_PEAKING_CONTROL_DPC 0x3770
55229 #define A_MAC_PORT_RX_LINKD_DYNAMIC_DATA_CENTERING_DDC 0x3774
55230 
55231 #define S_T6_ODEC    0
55232 #define M_T6_ODEC    0xfU
55233 #define V_T6_ODEC(x) ((x) << S_T6_ODEC)
55234 #define G_T6_ODEC(x) (((x) >> S_T6_ODEC) & M_T6_ODEC)
55235 
55236 #define A_MAC_PORT_RX_LINKD_RECEIVER_INTERNAL_STATUS 0x3778
55237 
55238 #define S_RX_LINKD_ACCCMP_RIS    11
55239 #define V_RX_LINKD_ACCCMP_RIS(x) ((x) << S_RX_LINKD_ACCCMP_RIS)
55240 #define F_RX_LINKD_ACCCMP_RIS    V_RX_LINKD_ACCCMP_RIS(1U)
55241 
55242 #define A_MAC_PORT_RX_LINKD_DFE_FUNCTION_CONTROL_1 0x377c
55243 #define A_MAC_PORT_RX_LINKD_DFE_FUNCTION_CONTROL_2 0x3780
55244 #define A_MAC_PORT_RX_LINKD_DFE_OFFSET_EVN1_EVN2 0x3784
55245 #define A_MAC_PORT_RX_LINKD_DFE_OFFSET_CHANNEL 0x3784
55246 #define A_MAC_PORT_RX_LINKD_DFE_OFFSET_ODD1_ODD2 0x3788
55247 #define A_MAC_PORT_RX_LINKD_DFE_OFFSET_VALUE 0x3788
55248 #define A_MAC_PORT_RX_LINKD_DFE_OFFSET_EVN3_EVN4 0x378c
55249 #define A_MAC_PORT_RX_LINKD_H_COEFFICIENBT_BIST 0x378c
55250 #define A_MAC_PORT_RX_LINKD_DFE_OFFSET_ODD3_ODD4 0x3790
55251 #define A_MAC_PORT_RX_LINKD_AC_CAPACITOR_BIST 0x3790
55252 
55253 #define S_RX_LINKD_ACCCMP_BIST    13
55254 #define V_RX_LINKD_ACCCMP_BIST(x) ((x) << S_RX_LINKD_ACCCMP_BIST)
55255 #define F_RX_LINKD_ACCCMP_BIST    V_RX_LINKD_ACCCMP_BIST(1U)
55256 
55257 #define A_MAC_PORT_RX_LINKD_DFE_E0_AND_E1_OFFSET 0x3794
55258 #define A_MAC_PORT_RX_LINKD_RECEIVER_LOFF_CONTROL 0x3798
55259 #define A_MAC_PORT_RX_LINKD_RECEIVER_LOFF_CONTROL_REGISTER 0x3798
55260 #define A_MAC_PORT_RX_LINKD_RECEIVER_SIGDET_CONTROL 0x379c
55261 #define A_MAC_PORT_RX_LINKD_RECEIVER_ANALOG_CONTROL_SWITCH 0x37a0
55262 #define A_MAC_PORT_RX_LINKD_INTEGRATOR_DAC_OFFSET 0x37a4
55263 #define A_MAC_PORT_RX_LINKD_DIGITAL_EYE_CONTROL 0x37a8
55264 #define A_MAC_PORT_RX_LINKD_DIGITAL_EYE_METRICS 0x37ac
55265 
55266 #define S_T6_EMMD    3
55267 #define M_T6_EMMD    0x3U
55268 #define V_T6_EMMD(x) ((x) << S_T6_EMMD)
55269 #define G_T6_EMMD(x) (((x) >> S_T6_EMMD) & M_T6_EMMD)
55270 
55271 #define S_T6_EMBRDY    2
55272 #define V_T6_EMBRDY(x) ((x) << S_T6_EMBRDY)
55273 #define F_T6_EMBRDY    V_T6_EMBRDY(1U)
55274 
55275 #define S_T6_EMBUMP    1
55276 #define V_T6_EMBUMP(x) ((x) << S_T6_EMBUMP)
55277 #define F_T6_EMBUMP    V_T6_EMBUMP(1U)
55278 
55279 #define A_MAC_PORT_RX_LINKD_DIGITAL_EYE_METRICS_ERROR_COUNT 0x37b0
55280 #define A_MAC_PORT_RX_LINKD_DIGITAL_EYE_METRICS_PDF_EYE_COUNT 0x37b4
55281 #define A_MAC_PORT_RX_LINKD_DIGITAL_EYE_METRICS_PATTERN_LENGTH 0x37b8
55282 #define A_MAC_PORT_RX_LINKD_DFE_FUNCTION_CONTROL_3 0x37bc
55283 #define A_MAC_PORT_RX_LINKD_DFE_TAP_ENABLE 0x37c0
55284 #define A_MAC_PORT_RX_LINKD_DFE_TAP_CONTROL 0x37c0
55285 
55286 #define S_RX_LINKD_INDEX_DFE_TC    0
55287 #define M_RX_LINKD_INDEX_DFE_TC    0xfU
55288 #define V_RX_LINKD_INDEX_DFE_TC(x) ((x) << S_RX_LINKD_INDEX_DFE_TC)
55289 #define G_RX_LINKD_INDEX_DFE_TC(x) (((x) >> S_RX_LINKD_INDEX_DFE_TC) & M_RX_LINKD_INDEX_DFE_TC)
55290 
55291 #define A_MAC_PORT_RX_LINKD_DFE_H1 0x37c4
55292 #define A_MAC_PORT_RX_LINKD_DFE_TAP 0x37c4
55293 
55294 #define S_RX_LINKD_INDEX_DFE_TAP    0
55295 #define M_RX_LINKD_INDEX_DFE_TAP    0xfU
55296 #define V_RX_LINKD_INDEX_DFE_TAP(x) ((x) << S_RX_LINKD_INDEX_DFE_TAP)
55297 #define G_RX_LINKD_INDEX_DFE_TAP(x) (((x) >> S_RX_LINKD_INDEX_DFE_TAP) & M_RX_LINKD_INDEX_DFE_TAP)
55298 
55299 #define A_MAC_PORT_RX_LINKD_DFE_H2 0x37c8
55300 #define A_MAC_PORT_RX_LINKD_DFE_H3 0x37cc
55301 #define A_MAC_PORT_RX_LINKD_DFE_H4 0x37d0
55302 #define A_MAC_PORT_RX_LINKD_DFE_H5 0x37d4
55303 #define A_MAC_PORT_RX_LINKD_DFE_H6_AND_H7 0x37d8
55304 #define A_MAC_PORT_RX_LINKD_DFE_H8_AND_H9 0x37dc
55305 #define A_MAC_PORT_RX_LINKD_DFE_H10_AND_H11 0x37e0
55306 #define A_MAC_PORT_RX_LINKD_DFE_H12 0x37e4
55307 #define A_MAC_PORT_RX_LINKD_RECEIVER_INTERNAL_STATUS_2 0x37e4
55308 #define A_MAC_PORT_RX_LINKD_AC_COUPLING_CURRENT_SOURCE_ADJUST 0x37e8
55309 #define A_MAC_PORT_RX_LINKD_RECEIVER_DCD_CONTROL 0x37ec
55310 #define A_MAC_PORT_RX_LINKD_RECEIVER_DCC_CONTROL 0x37f0
55311 
55312 #define S_RX_LINKD_DCCSTEP_RXCTL    10
55313 #define M_RX_LINKD_DCCSTEP_RXCTL    0x3U
55314 #define V_RX_LINKD_DCCSTEP_RXCTL(x) ((x) << S_RX_LINKD_DCCSTEP_RXCTL)
55315 #define G_RX_LINKD_DCCSTEP_RXCTL(x) (((x) >> S_RX_LINKD_DCCSTEP_RXCTL) & M_RX_LINKD_DCCSTEP_RXCTL)
55316 
55317 #define S_RX_LINKD_DCCLOCK_RXCTL    8
55318 #define V_RX_LINKD_DCCLOCK_RXCTL(x) ((x) << S_RX_LINKD_DCCLOCK_RXCTL)
55319 #define F_RX_LINKD_DCCLOCK_RXCTL    V_RX_LINKD_DCCLOCK_RXCTL(1U)
55320 
55321 #define A_MAC_PORT_RX_LINKD_RECEIVER_QCC_CONTROL 0x37f4
55322 #define A_MAC_PORT_RX_LINKD_RECEIVER_MACRO_TEST_CONTROL_2 0x37f8
55323 #define A_MAC_PORT_RX_LINKD_RECEIVER_MACRO_TEST_CONTROL_REGISTER_2 0x37f8
55324 #define A_MAC_PORT_RX_LINKD_RECEIVER_MACRO_TEST_CONTROL_1 0x37fc
55325 #define A_MAC_PORT_ANALOG_TEST_MUX 0x3814
55326 #define A_MAC_PORT_BANDGAP_CONTROL 0x382c
55327 
55328 #define S_T5BGCTL    0
55329 #define M_T5BGCTL    0xfU
55330 #define V_T5BGCTL(x) ((x) << S_T5BGCTL)
55331 #define G_T5BGCTL(x) (((x) >> S_T5BGCTL) & M_T5BGCTL)
55332 
55333 #define A_MAC_PORT_PLLREFSEL_CONTROL 0x3854
55334 
55335 #define S_REFSEL    0
55336 #define M_REFSEL    0x7U
55337 #define V_REFSEL(x) ((x) << S_REFSEL)
55338 #define G_REFSEL(x) (((x) >> S_REFSEL) & M_REFSEL)
55339 
55340 #define A_MAC_PORT_REFISINK_CONTROL 0x3858
55341 
55342 #define S_REFISINK    0
55343 #define M_REFISINK    0x3fU
55344 #define V_REFISINK(x) ((x) << S_REFISINK)
55345 #define G_REFISINK(x) (((x) >> S_REFISINK) & M_REFISINK)
55346 
55347 #define A_MAC_PORT_REFISRC_CONTROL 0x385c
55348 
55349 #define S_REFISRC    0
55350 #define M_REFISRC    0x3fU
55351 #define V_REFISRC(x) ((x) << S_REFISRC)
55352 #define G_REFISRC(x) (((x) >> S_REFISRC) & M_REFISRC)
55353 
55354 #define A_MAC_PORT_REFVREG_CONTROL 0x3860
55355 
55356 #define S_REFVREG    0
55357 #define M_REFVREG    0x3fU
55358 #define V_REFVREG(x) ((x) << S_REFVREG)
55359 #define G_REFVREG(x) (((x) >> S_REFVREG) & M_REFVREG)
55360 
55361 #define A_MAC_PORT_VBGENDOC_CONTROL 0x3864
55362 
55363 #define S_BGCLKSEL    2
55364 #define V_BGCLKSEL(x) ((x) << S_BGCLKSEL)
55365 #define F_BGCLKSEL    V_BGCLKSEL(1U)
55366 
55367 #define S_VBGENDOC    0
55368 #define M_VBGENDOC    0x3U
55369 #define V_VBGENDOC(x) ((x) << S_VBGENDOC)
55370 #define G_VBGENDOC(x) (((x) >> S_VBGENDOC) & M_VBGENDOC)
55371 
55372 #define A_MAC_PORT_VREFTUNE_CONTROL 0x3868
55373 
55374 #define S_VREFTUNE    0
55375 #define M_VREFTUNE    0xfU
55376 #define V_VREFTUNE(x) ((x) << S_VREFTUNE)
55377 #define G_VREFTUNE(x) (((x) >> S_VREFTUNE) & M_VREFTUNE)
55378 
55379 #define A_MAC_PORT_RESISTOR_CALIBRATION_CONTROL 0x3880
55380 
55381 #define S_RCCTL1    5
55382 #define V_RCCTL1(x) ((x) << S_RCCTL1)
55383 #define F_RCCTL1    V_RCCTL1(1U)
55384 
55385 #define S_RCCTL0    4
55386 #define V_RCCTL0(x) ((x) << S_RCCTL0)
55387 #define F_RCCTL0    V_RCCTL0(1U)
55388 
55389 #define S_RCAMP1    3
55390 #define V_RCAMP1(x) ((x) << S_RCAMP1)
55391 #define F_RCAMP1    V_RCAMP1(1U)
55392 
55393 #define S_RCAMP0    2
55394 #define V_RCAMP0(x) ((x) << S_RCAMP0)
55395 #define F_RCAMP0    V_RCAMP0(1U)
55396 
55397 #define S_RCAMPEN    1
55398 #define V_RCAMPEN(x) ((x) << S_RCAMPEN)
55399 #define F_RCAMPEN    V_RCAMPEN(1U)
55400 
55401 #define S_RCRST    0
55402 #define V_RCRST(x) ((x) << S_RCRST)
55403 #define F_RCRST    V_RCRST(1U)
55404 
55405 #define A_MAC_PORT_IMPEDENCE_CALIBRATION_CONTROL 0x3880
55406 
55407 #define S_FRCCAL_COMP    6
55408 #define V_FRCCAL_COMP(x) ((x) << S_FRCCAL_COMP)
55409 #define F_FRCCAL_COMP    V_FRCCAL_COMP(1U)
55410 
55411 #define S_IC_FRCERR    5
55412 #define V_IC_FRCERR(x) ((x) << S_IC_FRCERR)
55413 #define F_IC_FRCERR    V_IC_FRCERR(1U)
55414 
55415 #define S_CAL_BISTENAB    4
55416 #define V_CAL_BISTENAB(x) ((x) << S_CAL_BISTENAB)
55417 #define F_CAL_BISTENAB    V_CAL_BISTENAB(1U)
55418 
55419 #define S_RCAL_RESET    0
55420 #define V_RCAL_RESET(x) ((x) << S_RCAL_RESET)
55421 #define F_RCAL_RESET    V_RCAL_RESET(1U)
55422 
55423 #define A_MAC_PORT_RESISTOR_CALIBRATION_STATUS_1 0x3884
55424 
55425 #define S_RCERR    1
55426 #define V_RCERR(x) ((x) << S_RCERR)
55427 #define F_RCERR    V_RCERR(1U)
55428 
55429 #define S_RCCOMP    0
55430 #define V_RCCOMP(x) ((x) << S_RCCOMP)
55431 #define F_RCCOMP    V_RCCOMP(1U)
55432 
55433 #define A_MAC_PORT_IMPEDENCE_CALIBRATION_STATUS_1 0x3884
55434 
55435 #define S_RCALBENAB    3
55436 #define V_RCALBENAB(x) ((x) << S_RCALBENAB)
55437 #define F_RCALBENAB    V_RCALBENAB(1U)
55438 
55439 #define S_RCALBUSY    2
55440 #define V_RCALBUSY(x) ((x) << S_RCALBUSY)
55441 #define F_RCALBUSY    V_RCALBUSY(1U)
55442 
55443 #define S_RCALERR    1
55444 #define V_RCALERR(x) ((x) << S_RCALERR)
55445 #define F_RCALERR    V_RCALERR(1U)
55446 
55447 #define S_RCALCOMP    0
55448 #define V_RCALCOMP(x) ((x) << S_RCALCOMP)
55449 #define F_RCALCOMP    V_RCALCOMP(1U)
55450 
55451 #define A_MAC_PORT_RESISTOR_CALIBRATION_STATUS_2 0x3888
55452 
55453 #define S_RESREG2    0
55454 #define M_RESREG2    0xffU
55455 #define V_RESREG2(x) ((x) << S_RESREG2)
55456 #define G_RESREG2(x) (((x) >> S_RESREG2) & M_RESREG2)
55457 
55458 #define A_MAC_PORT_IMPEDENCE_CALIBRATION_STATUS_2 0x3888
55459 
55460 #define S_T6_RESREG2    0
55461 #define M_T6_RESREG2    0x3fU
55462 #define V_T6_RESREG2(x) ((x) << S_T6_RESREG2)
55463 #define G_T6_RESREG2(x) (((x) >> S_T6_RESREG2) & M_T6_RESREG2)
55464 
55465 #define A_MAC_PORT_RESISTOR_CALIBRATION_STATUS_3 0x388c
55466 
55467 #define S_RESREG3    0
55468 #define M_RESREG3    0xffU
55469 #define V_RESREG3(x) ((x) << S_RESREG3)
55470 #define G_RESREG3(x) (((x) >> S_RESREG3) & M_RESREG3)
55471 
55472 #define A_MAC_PORT_IMPEDENCE_CALIBRATION_STATUS_3 0x388c
55473 
55474 #define S_T6_RESREG3    0
55475 #define M_T6_RESREG3    0x3fU
55476 #define V_T6_RESREG3(x) ((x) << S_T6_RESREG3)
55477 #define G_T6_RESREG3(x) (((x) >> S_T6_RESREG3) & M_T6_RESREG3)
55478 
55479 #define A_MAC_PORT_INEQUALITY_CONTROL_AND_RESULT 0x38c0
55480 
55481 #define S_ISGT    7
55482 #define V_ISGT(x) ((x) << S_ISGT)
55483 #define F_ISGT    V_ISGT(1U)
55484 
55485 #define S_ISLT    6
55486 #define V_ISLT(x) ((x) << S_ISLT)
55487 #define F_ISLT    V_ISLT(1U)
55488 
55489 #define S_ISEQ    5
55490 #define V_ISEQ(x) ((x) << S_ISEQ)
55491 #define F_ISEQ    V_ISEQ(1U)
55492 
55493 #define S_ISVAL    3
55494 #define M_ISVAL    0x3U
55495 #define V_ISVAL(x) ((x) << S_ISVAL)
55496 #define G_ISVAL(x) (((x) >> S_ISVAL) & M_ISVAL)
55497 
55498 #define S_GTORLT    1
55499 #define M_GTORLT    0x3U
55500 #define V_GTORLT(x) ((x) << S_GTORLT)
55501 #define G_GTORLT(x) (((x) >> S_GTORLT) & M_GTORLT)
55502 
55503 #define S_INEQ    0
55504 #define V_INEQ(x) ((x) << S_INEQ)
55505 #define F_INEQ    V_INEQ(1U)
55506 
55507 #define A_MAC_PORT_INEQUALITY_LOW_LIMIT 0x38c4
55508 
55509 #define S_LLIM    0
55510 #define M_LLIM    0xffffU
55511 #define V_LLIM(x) ((x) << S_LLIM)
55512 #define G_LLIM(x) (((x) >> S_LLIM) & M_LLIM)
55513 
55514 #define A_MAC_PORT_INEQUALITY_LOW_LIMIT_MASK 0x38c8
55515 
55516 #define S_LMSK    0
55517 #define M_LMSK    0xffffU
55518 #define V_LMSK(x) ((x) << S_LMSK)
55519 #define G_LMSK(x) (((x) >> S_LMSK) & M_LMSK)
55520 
55521 #define A_MAC_PORT_INEQUALITY_HIGH_LIMIT 0x38cc
55522 
55523 #define S_HLIM    0
55524 #define M_HLIM    0xffffU
55525 #define V_HLIM(x) ((x) << S_HLIM)
55526 #define G_HLIM(x) (((x) >> S_HLIM) & M_HLIM)
55527 
55528 #define A_MAC_PORT_INEQUALITY_HIGH_LIMIT_MASK 0x38d0
55529 
55530 #define S_HMSK    0
55531 #define M_HMSK    0xffffU
55532 #define V_HMSK(x) ((x) << S_HMSK)
55533 #define G_HMSK(x) (((x) >> S_HMSK) & M_HMSK)
55534 
55535 #define A_MAC_PORT_MACRO_TEST_CONTROL_6 0x38e8
55536 
55537 #define S_LBIST    7
55538 #define V_LBIST(x) ((x) << S_LBIST)
55539 #define F_LBIST    V_LBIST(1U)
55540 
55541 #define S_LOGICTEST    6
55542 #define V_LOGICTEST(x) ((x) << S_LOGICTEST)
55543 #define F_LOGICTEST    V_LOGICTEST(1U)
55544 
55545 #define S_MAVDHI    5
55546 #define V_MAVDHI(x) ((x) << S_MAVDHI)
55547 #define F_MAVDHI    V_MAVDHI(1U)
55548 
55549 #define S_AUXEN    4
55550 #define V_AUXEN(x) ((x) << S_AUXEN)
55551 #define F_AUXEN    V_AUXEN(1U)
55552 
55553 #define S_JTAGMD    3
55554 #define V_JTAGMD(x) ((x) << S_JTAGMD)
55555 #define F_JTAGMD    V_JTAGMD(1U)
55556 
55557 #define S_RXACMODE    2
55558 #define V_RXACMODE(x) ((x) << S_RXACMODE)
55559 #define F_RXACMODE    V_RXACMODE(1U)
55560 
55561 #define S_HSSACJPC    1
55562 #define V_HSSACJPC(x) ((x) << S_HSSACJPC)
55563 #define F_HSSACJPC    V_HSSACJPC(1U)
55564 
55565 #define S_HSSACJAC    0
55566 #define V_HSSACJAC(x) ((x) << S_HSSACJAC)
55567 #define F_HSSACJAC    V_HSSACJAC(1U)
55568 
55569 #define A_MAC_PORT_MACRO_TEST_CONTROL_5 0x38ec
55570 
55571 #define S_REFVALIDD    6
55572 #define V_REFVALIDD(x) ((x) << S_REFVALIDD)
55573 #define F_REFVALIDD    V_REFVALIDD(1U)
55574 
55575 #define S_REFVALIDC    5
55576 #define V_REFVALIDC(x) ((x) << S_REFVALIDC)
55577 #define F_REFVALIDC    V_REFVALIDC(1U)
55578 
55579 #define S_REFVALIDB    4
55580 #define V_REFVALIDB(x) ((x) << S_REFVALIDB)
55581 #define F_REFVALIDB    V_REFVALIDB(1U)
55582 
55583 #define S_REFVALIDA    3
55584 #define V_REFVALIDA(x) ((x) << S_REFVALIDA)
55585 #define F_REFVALIDA    V_REFVALIDA(1U)
55586 
55587 #define S_REFSELRESET    2
55588 #define V_REFSELRESET(x) ((x) << S_REFSELRESET)
55589 #define F_REFSELRESET    V_REFSELRESET(1U)
55590 
55591 #define S_SOFTRESET    1
55592 #define V_SOFTRESET(x) ((x) << S_SOFTRESET)
55593 #define F_SOFTRESET    V_SOFTRESET(1U)
55594 
55595 #define S_MACROTEST    0
55596 #define V_MACROTEST(x) ((x) << S_MACROTEST)
55597 #define F_MACROTEST    V_MACROTEST(1U)
55598 
55599 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_CONFIGURATION_MODE 0x3900
55600 
55601 #define S_T6_T5_TX_RXLOOP    5
55602 #define V_T6_T5_TX_RXLOOP(x) ((x) << S_T6_T5_TX_RXLOOP)
55603 #define F_T6_T5_TX_RXLOOP    V_T6_T5_TX_RXLOOP(1U)
55604 
55605 #define S_T6_T5_TX_BWSEL    2
55606 #define M_T6_T5_TX_BWSEL    0x3U
55607 #define V_T6_T5_TX_BWSEL(x) ((x) << S_T6_T5_TX_BWSEL)
55608 #define G_T6_T5_TX_BWSEL(x) (((x) >> S_T6_T5_TX_BWSEL) & M_T6_T5_TX_BWSEL)
55609 
55610 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_TEST_CONTROL 0x3904
55611 
55612 #define S_T6_ERROR    9
55613 #define V_T6_ERROR(x) ((x) << S_T6_ERROR)
55614 #define F_T6_ERROR    V_T6_ERROR(1U)
55615 
55616 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_COEFFICIENT_CONTROL 0x3908
55617 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_DRIVER_MODE_CONTROL 0x390c
55618 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_DRIVER_OVERRIDE_CONTROL 0x3910
55619 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_DCLK_ROTATOR_OVERRIDE 0x3914
55620 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_IMPEDANCE_CALIBRATION_OVERRIDE 0x3918
55621 
55622 #define S_T6_CALSSTN    8
55623 #define M_T6_CALSSTN    0x3fU
55624 #define V_T6_CALSSTN(x) ((x) << S_T6_CALSSTN)
55625 #define G_T6_CALSSTN(x) (((x) >> S_T6_CALSSTN) & M_T6_CALSSTN)
55626 
55627 #define S_T6_CALSSTP    0
55628 #define M_T6_CALSSTP    0x3fU
55629 #define V_T6_CALSSTP(x) ((x) << S_T6_CALSSTP)
55630 #define G_T6_CALSSTP(x) (((x) >> S_T6_CALSSTP) & M_T6_CALSSTP)
55631 
55632 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_DCLK_DRIFT_TOLERANCE 0x391c
55633 
55634 #define S_T6_DRTOL    2
55635 #define M_T6_DRTOL    0x7U
55636 #define V_T6_DRTOL(x) ((x) << S_T6_DRTOL)
55637 #define G_T6_DRTOL(x) (((x) >> S_T6_DRTOL) & M_T6_DRTOL)
55638 
55639 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_TAP_0_COEFFICIENT 0x3920
55640 
55641 #define S_T6_NXTT0    0
55642 #define M_T6_NXTT0    0x3fU
55643 #define V_T6_NXTT0(x) ((x) << S_T6_NXTT0)
55644 #define G_T6_NXTT0(x) (((x) >> S_T6_NXTT0) & M_T6_NXTT0)
55645 
55646 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_TAP_1_COEFFICIENT 0x3924
55647 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_TAP_2_COEFFICIENT 0x3928
55648 
55649 #define S_T6_NXTT2    0
55650 #define M_T6_NXTT2    0x3fU
55651 #define V_T6_NXTT2(x) ((x) << S_T6_NXTT2)
55652 #define G_T6_NXTT2(x) (((x) >> S_T6_NXTT2) & M_T6_NXTT2)
55653 
55654 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_TAP_3_COEFFICIENT 0x392c
55655 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_AMPLITUDE 0x3930
55656 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_POLARITY 0x3934
55657 
55658 #define S_T6_NXTPOL    0
55659 #define M_T6_NXTPOL    0xfU
55660 #define V_T6_NXTPOL(x) ((x) << S_T6_NXTPOL)
55661 #define G_T6_NXTPOL(x) (((x) >> S_T6_NXTPOL) & M_T6_NXTPOL)
55662 
55663 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_802_3AP_ADAPTIVE_EQUALIZATION_COMMAND 0x3938
55664 
55665 #define S_T6_C0UPDT    6
55666 #define M_T6_C0UPDT    0x3U
55667 #define V_T6_C0UPDT(x) ((x) << S_T6_C0UPDT)
55668 #define G_T6_C0UPDT(x) (((x) >> S_T6_C0UPDT) & M_T6_C0UPDT)
55669 
55670 #define S_T6_C2UPDT    2
55671 #define M_T6_C2UPDT    0x3U
55672 #define V_T6_C2UPDT(x) ((x) << S_T6_C2UPDT)
55673 #define G_T6_C2UPDT(x) (((x) >> S_T6_C2UPDT) & M_T6_C2UPDT)
55674 
55675 #define S_T6_C1UPDT    0
55676 #define M_T6_C1UPDT    0x3U
55677 #define V_T6_C1UPDT(x) ((x) << S_T6_C1UPDT)
55678 #define G_T6_C1UPDT(x) (((x) >> S_T6_C1UPDT) & M_T6_C1UPDT)
55679 
55680 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_802_3AP_ADAPTIVE_EQUALIZATION_STATUS 0x393c
55681 
55682 #define S_T6_C0STAT    6
55683 #define M_T6_C0STAT    0x3U
55684 #define V_T6_C0STAT(x) ((x) << S_T6_C0STAT)
55685 #define G_T6_C0STAT(x) (((x) >> S_T6_C0STAT) & M_T6_C0STAT)
55686 
55687 #define S_T6_C2STAT    2
55688 #define M_T6_C2STAT    0x3U
55689 #define V_T6_C2STAT(x) ((x) << S_T6_C2STAT)
55690 #define G_T6_C2STAT(x) (((x) >> S_T6_C2STAT) & M_T6_C2STAT)
55691 
55692 #define S_T6_C1STAT    0
55693 #define M_T6_C1STAT    0x3U
55694 #define V_T6_C1STAT(x) ((x) << S_T6_C1STAT)
55695 #define G_T6_C1STAT(x) (((x) >> S_T6_C1STAT) & M_T6_C1STAT)
55696 
55697 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_TAP_0_COEFFICIENT_OVERRIDE 0x3940
55698 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_AE_TAP_0_COEFFICIENT_OVERRIDE 0x3940
55699 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_TAP_1_COEFFICIENT_OVERRIDE 0x3944
55700 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_AE_TAP_1_COEFFICIENT_OVERRIDE 0x3944
55701 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_TAP_2_COEFFICIENT_OVERRIDE 0x3948
55702 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_AE_TAP_2_COEFFICIENT_OVERRIDE 0x3948
55703 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_AE_TAP_3_COEFFICIENT_OVERRIDE 0x394c
55704 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_APPLIED_TUNE_REGISTER 0x3950
55705 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_ANALOG_DIAGNOSTICS_REGISTER 0x3958
55706 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_TAP_0_COEFFICIENT_APPLIED 0x3960
55707 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_4X_SEGMENT_APPLIED 0x3960
55708 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_TAP_1_COEFFICIENT_APPLIED 0x3964
55709 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_2X_SEGMENT_APPLIED 0x3964
55710 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_TAP_2_COEFFICIENT_APPLIED 0x3968
55711 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_1X_SEGMENT_APPLIED 0x3968
55712 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_SEGMENT_4X_TERMINATION_APPLIED 0x396c
55713 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_SEGMENT_DISABLE_APPLIED_1 0x3970
55714 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_SEGMENT_2X1X_TERMINATION_APPLIED 0x3970
55715 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_SEGMENT_DISABLE_APPLIED_2 0x3974
55716 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_TAP_SIGN_APPLIED_REGISTER 0x3974
55717 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_EXTENDED_ADDRESS_DATA 0x3978
55718 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_EXTENDED_ADDRESS_ADDR 0x397c
55719 
55720 #define S_T6_XADDR    1
55721 #define M_T6_XADDR    0x1fU
55722 #define V_T6_XADDR(x) ((x) << S_T6_XADDR)
55723 #define G_T6_XADDR(x) (((x) >> S_T6_XADDR) & M_T6_XADDR)
55724 
55725 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_PATTERN_BUFFER_BYTES_1_0 0x3980
55726 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_PATTERN_BUFFER_BYTES_3_2 0x3984
55727 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_PATTERN_BUFFER_BYTE_4 0x3988
55728 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_PATTERN_BUFFER_BYTES_5_4 0x3988
55729 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_DCC_CONTROL 0x398c
55730 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_PATTERN_BUFFER_BYTES_7_6 0x398c
55731 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_DCC_OVERRIDE 0x3990
55732 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_DCC_APPLIED 0x3994
55733 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_DCC_TIME_OUT 0x3998
55734 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_802_3AZ_CONTROL 0x399c
55735 #define A_T6_MAC_PORT_TX_LINK_BCST_TRANSMIT_DCC_CONTROL 0x39a0
55736 
55737 #define S_T6_DCCTIMEEN    13
55738 #define M_T6_DCCTIMEEN    0x3U
55739 #define V_T6_DCCTIMEEN(x) ((x) << S_T6_DCCTIMEEN)
55740 #define G_T6_DCCTIMEEN(x) (((x) >> S_T6_DCCTIMEEN) & M_T6_DCCTIMEEN)
55741 
55742 #define S_T6_DCCLOCK    11
55743 #define M_T6_DCCLOCK    0x3U
55744 #define V_T6_DCCLOCK(x) ((x) << S_T6_DCCLOCK)
55745 #define G_T6_DCCLOCK(x) (((x) >> S_T6_DCCLOCK) & M_T6_DCCLOCK)
55746 
55747 #define S_T6_DCCOFFSET    8
55748 #define M_T6_DCCOFFSET    0x7U
55749 #define V_T6_DCCOFFSET(x) ((x) << S_T6_DCCOFFSET)
55750 #define G_T6_DCCOFFSET(x) (((x) >> S_T6_DCCOFFSET) & M_T6_DCCOFFSET)
55751 
55752 #define S_TX_LINK_BCST_DCCSTEP_CTL    6
55753 #define M_TX_LINK_BCST_DCCSTEP_CTL    0x3U
55754 #define V_TX_LINK_BCST_DCCSTEP_CTL(x) ((x) << S_TX_LINK_BCST_DCCSTEP_CTL)
55755 #define G_TX_LINK_BCST_DCCSTEP_CTL(x) (((x) >> S_TX_LINK_BCST_DCCSTEP_CTL) & M_TX_LINK_BCST_DCCSTEP_CTL)
55756 
55757 #define A_T6_MAC_PORT_TX_LINK_BCST_TRANSMIT_DCC_OVERRIDE 0x39a4
55758 #define A_T6_MAC_PORT_TX_LINK_BCST_TRANSMIT_DCC_APPLIED 0x39a8
55759 #define A_T6_MAC_PORT_TX_LINK_BCST_TRANSMIT_DCC_TIME_OUT 0x39ac
55760 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_TAP_SIGN_OVERRIDE 0x39c0
55761 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_SEGMENT_4X_OVERRIDE 0x39c8
55762 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_SEGMENT_2X_OVERRIDE 0x39cc
55763 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_SEGMENT_1X_OVERRIDE 0x39d0
55764 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_TAP_SEGMENT_4X_TERMINATION_OVERRIDE 0x39d8
55765 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_TAP_SEGMENT_2X_TERMINATION_OVERRIDE 0x39dc
55766 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_TAP_SEGMENT_1X_TERMINATION_OVERRIDE 0x39e0
55767 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_MACRO_TEST_CONTROL_5 0x39ec
55768 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_MACRO_TEST_CONTROL_4 0x39f0
55769 
55770 #define S_T6_SDOVRD    0
55771 #define M_T6_SDOVRD    0xffffU
55772 #define V_T6_SDOVRD(x) ((x) << S_T6_SDOVRD)
55773 #define G_T6_SDOVRD(x) (((x) >> S_T6_SDOVRD) & M_T6_SDOVRD)
55774 
55775 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_MACRO_TEST_CONTROL_3 0x39f4
55776 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_MACRO_TEST_CONTROL_2 0x39f8
55777 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_MACRO_TEST_CONTROL_1 0x39fc
55778 
55779 #define S_T6_SDOVRDEN    15
55780 #define V_T6_SDOVRDEN(x) ((x) << S_T6_SDOVRDEN)
55781 #define F_T6_SDOVRDEN    V_T6_SDOVRDEN(1U)
55782 
55783 #define A_MAC_PORT_RX_LINK_BCST_RECEIVER_CONFIGURATION_MODE 0x3a00
55784 #define A_MAC_PORT_RX_LINK_BCST_RECEIVER_TEST_CONTROL 0x3a04
55785 #define A_MAC_PORT_RX_LINK_BCST_PHASE_ROTATOR_CONTROL 0x3a08
55786 #define A_MAC_PORT_RX_LINK_BCST_PHASE_ROTATOR_OFFSET_CONTROL 0x3a0c
55787 
55788 #define S_T6_TMSCAL    8
55789 #define M_T6_TMSCAL    0x3U
55790 #define V_T6_TMSCAL(x) ((x) << S_T6_TMSCAL)
55791 #define G_T6_TMSCAL(x) (((x) >> S_T6_TMSCAL) & M_T6_TMSCAL)
55792 
55793 #define S_T6_APADJ    7
55794 #define V_T6_APADJ(x) ((x) << S_T6_APADJ)
55795 #define F_T6_APADJ    V_T6_APADJ(1U)
55796 
55797 #define S_T6_RSEL    6
55798 #define V_T6_RSEL(x) ((x) << S_T6_RSEL)
55799 #define F_T6_RSEL    V_T6_RSEL(1U)
55800 
55801 #define S_T6_PHOFFS    0
55802 #define M_T6_PHOFFS    0x3fU
55803 #define V_T6_PHOFFS(x) ((x) << S_T6_PHOFFS)
55804 #define G_T6_PHOFFS(x) (((x) >> S_T6_PHOFFS) & M_T6_PHOFFS)
55805 
55806 #define A_MAC_PORT_RX_LINK_BCST_PHASE_ROTATOR_POSITION_1 0x3a10
55807 #define A_MAC_PORT_RX_LINK_BCST_PHASE_ROTATOR_POSITION_2 0x3a14
55808 #define A_MAC_PORT_RX_LINK_BCST_PHASE_ROTATOR_STATIC_PHASE_OFFSET_1 0x3a18
55809 #define A_MAC_PORT_RX_LINK_BCST_PHASE_ROTATOR_STATIC_PHASE_OFFSET_2 0x3a1c
55810 #define A_MAC_PORT_RX_LINK_BCST_DFE_CONTROL 0x3a20
55811 
55812 #define S_T6_SPIFMT    8
55813 #define M_T6_SPIFMT    0xfU
55814 #define V_T6_SPIFMT(x) ((x) << S_T6_SPIFMT)
55815 #define G_T6_SPIFMT(x) (((x) >> S_T6_SPIFMT) & M_T6_SPIFMT)
55816 
55817 #define A_MAC_PORT_RX_LINK_BCST_DFE_SAMPLE_SNAPSHOT_1 0x3a24
55818 #define A_MAC_PORT_RX_LINK_BCST_DFE_SAMPLE_SNAPSHOT_2 0x3a28
55819 #define A_MAC_PORT_RX_LINK_BCST_RECEIVER_VGA_CONTROL_1 0x3a2c
55820 
55821 #define S_T6_WRAPSEL    15
55822 #define V_T6_WRAPSEL(x) ((x) << S_T6_WRAPSEL)
55823 #define F_T6_WRAPSEL    V_T6_WRAPSEL(1U)
55824 
55825 #define S_T6_PEAK    9
55826 #define M_T6_PEAK    0x1fU
55827 #define V_T6_PEAK(x) ((x) << S_T6_PEAK)
55828 #define G_T6_PEAK(x) (((x) >> S_T6_PEAK) & M_T6_PEAK)
55829 
55830 #define A_MAC_PORT_RX_LINK_BCST_RECEIVER_VGA_CONTROL_2 0x3a30
55831 
55832 #define S_T6_T5VGAIN    0
55833 #define M_T6_T5VGAIN    0x7fU
55834 #define V_T6_T5VGAIN(x) ((x) << S_T6_T5VGAIN)
55835 #define G_T6_T5VGAIN(x) (((x) >> S_T6_T5VGAIN) & M_T6_T5VGAIN)
55836 
55837 #define A_MAC_PORT_RX_LINK_BCST_RECEIVER_VGA_CONTROL_3 0x3a34
55838 #define A_MAC_PORT_RX_LINK_BCST_RECEIVER_DQCC_CONTROL_1 0x3a38
55839 #define A_MAC_PORT_RX_LINK_BCST_RECEIVER_POWER_MANAGEMENT_CONTROL 0x3a38
55840 #define A_MAC_PORT_RX_LINK_BCST_RECEIVER_IQAMP_CONTROL_1 0x3a3c
55841 #define A_MAC_PORT_RX_LINK_BCST_RECEIVER_DQCC_CONTROL_3 0x3a40
55842 #define A_MAC_PORT_RX_LINK_BCST_RECEIVER_IQAMP_CONTROL_2 0x3a40
55843 #define A_MAC_PORT_RX_LINK_BCST_RECEIVER_DACAP_AND_DACAN_SELECTION 0x3a44
55844 #define A_MAC_PORT_RX_LINK_BCST_RECEIVER_DACAP_AND_DACAN 0x3a48
55845 #define A_MAC_PORT_RX_LINK_BCST_RECEIVER_DACA_MIN_AND_DACAZ 0x3a4c
55846 #define A_MAC_PORT_RX_LINK_BCST_RECEIVER_DACA_MIN 0x3a4c
55847 #define A_MAC_PORT_RX_LINK_BCST_RECEIVER_ADAC_CONTROL 0x3a50
55848 #define A_MAC_PORT_RX_LINK_BCST_RECEIVER_AC_COUPLING_CONTROL 0x3a54
55849 #define A_MAC_PORT_RX_LINK_BCST_RECEIVER_AC_COUPLING_VALUE 0x3a58
55850 #define A_MAC_PORT_RX_LINK_BCST_DFE_H1_LOCAL_OFFSET_ODD2_EVN2 0x3a5c
55851 #define A_MAC_PORT_RX_LINK_BCST_DFE_H1H2H3_LOCAL_OFFSET 0x3a5c
55852 #define A_MAC_PORT_RX_LINK_BCST_DFE_H1_LOCAL_OFFSET_ODD3_EVN3 0x3a60
55853 #define A_MAC_PORT_RX_LINK_BCST_DFE_H1H2H3_LOCAL_OFFSET_VALUE 0x3a60
55854 #define A_MAC_PORT_RX_LINK_BCST_DFE_H1_LOCAL_OFFSET_ODD4_EVN4 0x3a64
55855 #define A_MAC_PORT_RX_LINK_BCST_PEAKED_INTEGRATOR 0x3a64
55856 #define A_MAC_PORT_RX_LINK_BCST_CDR_ANALOG_SWITCH 0x3a68
55857 #define A_MAC_PORT_RX_LINK_BCST_PEAKING_AMPLIFIER_INTIALIZATION_CONTROL 0x3a6c
55858 #define A_MAC_PORT_RX_LINK_BCST_DYNAMIC_AMPLITUDE_CENTERING_DAC_AND_DYNAMIC_PEAKING_CONTROL_DPC 0x3a70
55859 #define A_MAC_PORT_RX_LINK_BCST_DYNAMIC_DATA_CENTERING_DDC 0x3a74
55860 
55861 #define S_T6_ODEC    0
55862 #define M_T6_ODEC    0xfU
55863 #define V_T6_ODEC(x) ((x) << S_T6_ODEC)
55864 #define G_T6_ODEC(x) (((x) >> S_T6_ODEC) & M_T6_ODEC)
55865 
55866 #define A_MAC_PORT_RX_LINK_BCST_RECEIVER_INTERNAL_STATUS 0x3a78
55867 
55868 #define S_RX_LINK_BCST_ACCCMP_RIS    11
55869 #define V_RX_LINK_BCST_ACCCMP_RIS(x) ((x) << S_RX_LINK_BCST_ACCCMP_RIS)
55870 #define F_RX_LINK_BCST_ACCCMP_RIS    V_RX_LINK_BCST_ACCCMP_RIS(1U)
55871 
55872 #define A_MAC_PORT_RX_LINK_BCST_DFE_FUNCTION_CONTROL_1 0x3a7c
55873 #define A_MAC_PORT_RX_LINK_BCST_DFE_FUNCTION_CONTROL_2 0x3a80
55874 #define A_MAC_PORT_RX_LINK_BCST_DFE_OFFSET_EVN1_EVN2 0x3a84
55875 #define A_MAC_PORT_RX_LINK_BCST_DFE_OFFSET_CHANNEL 0x3a84
55876 #define A_MAC_PORT_RX_LINK_BCST_DFE_OFFSET_ODD1_ODD2 0x3a88
55877 #define A_MAC_PORT_RX_LINK_BCST_DFE_OFFSET_VALUE 0x3a88
55878 #define A_MAC_PORT_RX_LINK_BCST_DFE_OFFSET_EVN3_EVN4 0x3a8c
55879 #define A_MAC_PORT_RX_LINK_BCST_H_COEFFICIENBT_BIST 0x3a8c
55880 #define A_MAC_PORT_RX_LINK_BCST_DFE_OFFSET_ODD3_ODD4 0x3a90
55881 #define A_MAC_PORT_RX_LINK_BCST_AC_CAPACITOR_BIST 0x3a90
55882 
55883 #define S_RX_LINK_BCST_ACCCMP_BIST    13
55884 #define V_RX_LINK_BCST_ACCCMP_BIST(x) ((x) << S_RX_LINK_BCST_ACCCMP_BIST)
55885 #define F_RX_LINK_BCST_ACCCMP_BIST    V_RX_LINK_BCST_ACCCMP_BIST(1U)
55886 
55887 #define A_MAC_PORT_RX_LINK_BCST_DFE_E0_AND_E1_OFFSET 0x3a94
55888 #define A_MAC_PORT_RX_LINK_BCST_RECEIVER_LOFF_CONTROL 0x3a98
55889 #define A_MAC_PORT_RX_LINK_BCST_RECEIVER_LOFF_CONTROL_REGISTER 0x3a98
55890 #define A_MAC_PORT_RX_LINK_BCST_RECEIVER_SIGDET_CONTROL 0x3a9c
55891 #define A_MAC_PORT_RX_LINK_BCST_RECEIVER_ANALOG_CONTROL_SWITCH 0x3aa0
55892 #define A_MAC_PORT_RX_LINK_BCST_INTEGRATOR_DAC_OFFSET 0x3aa4
55893 #define A_MAC_PORT_RX_LINK_BCST_DIGITAL_EYE_CONTROL 0x3aa8
55894 #define A_MAC_PORT_RX_LINK_BCST_DIGITAL_EYE_METRICS 0x3aac
55895 
55896 #define S_T6_EMMD    3
55897 #define M_T6_EMMD    0x3U
55898 #define V_T6_EMMD(x) ((x) << S_T6_EMMD)
55899 #define G_T6_EMMD(x) (((x) >> S_T6_EMMD) & M_T6_EMMD)
55900 
55901 #define S_T6_EMBRDY    2
55902 #define V_T6_EMBRDY(x) ((x) << S_T6_EMBRDY)
55903 #define F_T6_EMBRDY    V_T6_EMBRDY(1U)
55904 
55905 #define S_T6_EMBUMP    1
55906 #define V_T6_EMBUMP(x) ((x) << S_T6_EMBUMP)
55907 #define F_T6_EMBUMP    V_T6_EMBUMP(1U)
55908 
55909 #define A_MAC_PORT_RX_LINK_BCST_DIGITAL_EYE_METRICS_ERROR_COUNT 0x3ab0
55910 #define A_MAC_PORT_RX_LINK_BCST_DIGITAL_EYE_METRICS_PDF_EYE_COUNT 0x3ab4
55911 #define A_MAC_PORT_RX_LINK_BCST_DIGITAL_EYE_METRICS_PATTERN_LENGTH 0x3ab8
55912 #define A_MAC_PORT_RX_LINK_BCST_DFE_FUNCTION_CONTROL_3 0x3abc
55913 #define A_MAC_PORT_RX_LINK_BCST_DFE_TAP_ENABLE 0x3ac0
55914 #define A_MAC_PORT_RX_LINK_BCST_DFE_TAP_CONTROL 0x3ac0
55915 
55916 #define S_RX_LINK_BCST_INDEX_DFE_TC    0
55917 #define M_RX_LINK_BCST_INDEX_DFE_TC    0xfU
55918 #define V_RX_LINK_BCST_INDEX_DFE_TC(x) ((x) << S_RX_LINK_BCST_INDEX_DFE_TC)
55919 #define G_RX_LINK_BCST_INDEX_DFE_TC(x) (((x) >> S_RX_LINK_BCST_INDEX_DFE_TC) & M_RX_LINK_BCST_INDEX_DFE_TC)
55920 
55921 #define A_MAC_PORT_RX_LINK_BCST_DFE_H1 0x3ac4
55922 #define A_MAC_PORT_RX_LINK_BCST_DFE_TAP 0x3ac4
55923 
55924 #define S_RX_LINK_BCST_INDEX_DFE_TAP    0
55925 #define M_RX_LINK_BCST_INDEX_DFE_TAP    0xfU
55926 #define V_RX_LINK_BCST_INDEX_DFE_TAP(x) ((x) << S_RX_LINK_BCST_INDEX_DFE_TAP)
55927 #define G_RX_LINK_BCST_INDEX_DFE_TAP(x) (((x) >> S_RX_LINK_BCST_INDEX_DFE_TAP) & M_RX_LINK_BCST_INDEX_DFE_TAP)
55928 
55929 #define A_MAC_PORT_RX_LINK_BCST_DFE_H2 0x3ac8
55930 #define A_MAC_PORT_RX_LINK_BCST_DFE_H3 0x3acc
55931 #define A_MAC_PORT_RX_LINK_BCST_DFE_H4 0x3ad0
55932 #define A_MAC_PORT_RX_LINK_BCST_DFE_H5 0x3ad4
55933 #define A_MAC_PORT_RX_LINK_BCST_DFE_H6_AND_H7 0x3ad8
55934 #define A_MAC_PORT_RX_LINK_BCST_DFE_H8_AND_H9 0x3adc
55935 #define A_MAC_PORT_RX_LINK_BCST_DFE_H10_AND_H11 0x3ae0
55936 #define A_MAC_PORT_RX_LINK_BCST_DFE_H12 0x3ae4
55937 #define A_MAC_PORT_RX_LINK_BCST_RECEIVER_INTERNAL_STATUS_2 0x3ae4
55938 #define A_MAC_PORT_RX_LINK_BCST_AC_COUPLING_CURRENT_SOURCE_ADJUST 0x3ae8
55939 #define A_MAC_PORT_RX_LINK_BCST_RECEIVER_DCD_CONTROL 0x3aec
55940 #define A_MAC_PORT_RX_LINK_BCST_RECEIVER_DCC_CONTROL 0x3af0
55941 
55942 #define S_RX_LINK_BCST_DCCSTEP_RXCTL    10
55943 #define M_RX_LINK_BCST_DCCSTEP_RXCTL    0x3U
55944 #define V_RX_LINK_BCST_DCCSTEP_RXCTL(x) ((x) << S_RX_LINK_BCST_DCCSTEP_RXCTL)
55945 #define G_RX_LINK_BCST_DCCSTEP_RXCTL(x) (((x) >> S_RX_LINK_BCST_DCCSTEP_RXCTL) & M_RX_LINK_BCST_DCCSTEP_RXCTL)
55946 
55947 #define S_RX_LINK_BCST_DCCLOCK_RXCTL    8
55948 #define V_RX_LINK_BCST_DCCLOCK_RXCTL(x) ((x) << S_RX_LINK_BCST_DCCLOCK_RXCTL)
55949 #define F_RX_LINK_BCST_DCCLOCK_RXCTL    V_RX_LINK_BCST_DCCLOCK_RXCTL(1U)
55950 
55951 #define A_MAC_PORT_RX_LINK_BCST_RECEIVER_QCC_CONTROL 0x3af4
55952 #define A_MAC_PORT_RX_LINK_BCST_RECEIVER_MACRO_TEST_CONTROL_2 0x3af8
55953 #define A_MAC_PORT_RX_LINK_BCST_RECEIVER_MACRO_TEST_CONTROL_REGISTER_2 0x3af8
55954 #define A_MAC_PORT_RX_LINK_BCST_RECEIVER_MACRO_TEST_CONTROL_1 0x3afc
55955 #define A_MAC_PORT_PLLA_VCO_COARSE_CALIBRATION_0 0x3b00
55956 #define A_MAC_PORT_PLLA_VCO_COARSE_CALIBRATION_1 0x3b04
55957 #define A_MAC_PORT_PLLA_VCO_COARSE_CALIBRATION_2 0x3b08
55958 #define A_MAC_PORT_PLLA_VCO_COARSE_CALIBRATION_3 0x3b0c
55959 #define A_MAC_PORT_PLLA_VCO_COARSE_CALIBRATION_4 0x3b10
55960 #define A_MAC_PORT_PLLA_POWER_CONTROL 0x3b24
55961 
55962 #define S_SPWRENA    1
55963 #define V_SPWRENA(x) ((x) << S_SPWRENA)
55964 #define F_SPWRENA    V_SPWRENA(1U)
55965 
55966 #define S_NPWRENA    0
55967 #define V_NPWRENA(x) ((x) << S_NPWRENA)
55968 #define F_NPWRENA    V_NPWRENA(1U)
55969 
55970 #define A_MAC_PORT_PLLA_CHARGE_PUMP_CONTROL 0x3b28
55971 
55972 #define S_T5CPISEL    0
55973 #define M_T5CPISEL    0x7U
55974 #define V_T5CPISEL(x) ((x) << S_T5CPISEL)
55975 #define G_T5CPISEL(x) (((x) >> S_T5CPISEL) & M_T5CPISEL)
55976 
55977 #define A_MAC_PORT_PLLA_PLL_MICELLANEOUS_CONTROL 0x3b38
55978 #define A_MAC_PORT_PLLA_PCLK_CONTROL 0x3b3c
55979 
55980 #define S_SPEDIV    3
55981 #define M_SPEDIV    0x1fU
55982 #define V_SPEDIV(x) ((x) << S_SPEDIV)
55983 #define G_SPEDIV(x) (((x) >> S_SPEDIV) & M_SPEDIV)
55984 
55985 #define S_PCKSEL    0
55986 #define M_PCKSEL    0x7U
55987 #define V_PCKSEL(x) ((x) << S_PCKSEL)
55988 #define G_PCKSEL(x) (((x) >> S_PCKSEL) & M_PCKSEL)
55989 
55990 #define A_MAC_PORT_PLLA_EYE_METRICS_INTERVAL_CONTROL 0x3b40
55991 
55992 #define S_EMIL    2
55993 #define V_EMIL(x) ((x) << S_EMIL)
55994 #define F_EMIL    V_EMIL(1U)
55995 
55996 #define S_EMID    1
55997 #define V_EMID(x) ((x) << S_EMID)
55998 #define F_EMID    V_EMID(1U)
55999 
56000 #define S_EMIS    0
56001 #define V_EMIS(x) ((x) << S_EMIS)
56002 #define F_EMIS    V_EMIS(1U)
56003 
56004 #define A_MAC_PORT_PLLA_EYE_METRICS_INTERVAL_LIMIT_1 0x3b44
56005 
56006 #define S_EMIL1    0
56007 #define M_EMIL1    0xffU
56008 #define V_EMIL1(x) ((x) << S_EMIL1)
56009 #define G_EMIL1(x) (((x) >> S_EMIL1) & M_EMIL1)
56010 
56011 #define A_MAC_PORT_PLLA_EYE_METRICS_INTERVAL_LIMIT_2 0x3b48
56012 
56013 #define S_EMIL2    0
56014 #define M_EMIL2    0xffU
56015 #define V_EMIL2(x) ((x) << S_EMIL2)
56016 #define G_EMIL2(x) (((x) >> S_EMIL2) & M_EMIL2)
56017 
56018 #define A_MAC_PORT_PLLA_EYE_METRICS_INTERVAL_LIMIT_3 0x3b4c
56019 
56020 #define S_EMIL3    0
56021 #define M_EMIL3    0xffU
56022 #define V_EMIL3(x) ((x) << S_EMIL3)
56023 #define G_EMIL3(x) (((x) >> S_EMIL3) & M_EMIL3)
56024 
56025 #define A_MAC_PORT_PLLA_EYE_METRICS_INTERVAL_LIMIT_4 0x3b50
56026 
56027 #define S_EMIL4    0
56028 #define M_EMIL4    0xffU
56029 #define V_EMIL4(x) ((x) << S_EMIL4)
56030 #define G_EMIL4(x) (((x) >> S_EMIL4) & M_EMIL4)
56031 
56032 #define A_MAC_PORT_PLLA_MACRO_TEST_CONTROL_4 0x3bf0
56033 
56034 #define S_VBST    1
56035 #define M_VBST    0x7U
56036 #define V_VBST(x) ((x) << S_VBST)
56037 #define G_VBST(x) (((x) >> S_VBST) & M_VBST)
56038 
56039 #define S_PLLDIVA    4
56040 #define V_PLLDIVA(x) ((x) << S_PLLDIVA)
56041 #define F_PLLDIVA    V_PLLDIVA(1U)
56042 
56043 #define S_REFDIV    0
56044 #define M_REFDIV    0xfU
56045 #define V_REFDIV(x) ((x) << S_REFDIV)
56046 #define G_REFDIV(x) (((x) >> S_REFDIV) & M_REFDIV)
56047 
56048 #define A_MAC_PORT_PLLA_MACRO_TEST_CONTROL_3 0x3bf4
56049 
56050 #define S_RESYNC    6
56051 #define V_RESYNC(x) ((x) << S_RESYNC)
56052 #define F_RESYNC    V_RESYNC(1U)
56053 
56054 #define S_RXCLKSEL    5
56055 #define V_RXCLKSEL(x) ((x) << S_RXCLKSEL)
56056 #define F_RXCLKSEL    V_RXCLKSEL(1U)
56057 
56058 #define S_FRCBAND    4
56059 #define V_FRCBAND(x) ((x) << S_FRCBAND)
56060 #define F_FRCBAND    V_FRCBAND(1U)
56061 
56062 #define S_PLLBYP    3
56063 #define V_PLLBYP(x) ((x) << S_PLLBYP)
56064 #define F_PLLBYP    V_PLLBYP(1U)
56065 
56066 #define S_PDWNP    2
56067 #define V_PDWNP(x) ((x) << S_PDWNP)
56068 #define F_PDWNP    V_PDWNP(1U)
56069 
56070 #define S_VCOSEL    1
56071 #define V_VCOSEL(x) ((x) << S_VCOSEL)
56072 #define F_VCOSEL    V_VCOSEL(1U)
56073 
56074 #define S_DIVSEL8    0
56075 #define V_DIVSEL8(x) ((x) << S_DIVSEL8)
56076 #define F_DIVSEL8    V_DIVSEL8(1U)
56077 
56078 #define A_MAC_PORT_PLLA_MACRO_TEST_CONTROL_2 0x3bf8
56079 
56080 #define S_DIVSEL    0
56081 #define M_DIVSEL    0xffU
56082 #define V_DIVSEL(x) ((x) << S_DIVSEL)
56083 #define G_DIVSEL(x) (((x) >> S_DIVSEL) & M_DIVSEL)
56084 
56085 #define A_MAC_PORT_PLLA_MACRO_TEST_CONTROL_1 0x3bfc
56086 
56087 #define S_CONFIG    0
56088 #define M_CONFIG    0xffU
56089 #define V_CONFIG(x) ((x) << S_CONFIG)
56090 #define G_CONFIG(x) (((x) >> S_CONFIG) & M_CONFIG)
56091 
56092 #define A_MAC_PORT_PLLB_VCO_COARSE_CALIBRATION_0 0x3c00
56093 #define A_MAC_PORT_PLLB_VCO_COARSE_CALIBRATION_1 0x3c04
56094 #define A_MAC_PORT_PLLB_VCO_COARSE_CALIBRATION_2 0x3c08
56095 #define A_MAC_PORT_PLLB_VCO_COARSE_CALIBRATION_3 0x3c0c
56096 #define A_MAC_PORT_PLLB_VCO_COARSE_CALIBRATION_4 0x3c10
56097 #define A_MAC_PORT_PLLB_POWER_CONTROL 0x3c24
56098 #define A_MAC_PORT_PLLB_CHARGE_PUMP_CONTROL 0x3c28
56099 #define A_MAC_PORT_PLLB_PLL_MICELLANEOUS_CONTROL 0x3c38
56100 #define A_MAC_PORT_PLLB_PCLK_CONTROL 0x3c3c
56101 #define A_MAC_PORT_PLLB_EYE_METRICS_INTERVAL_CONTROL 0x3c40
56102 #define A_MAC_PORT_PLLB_EYE_METRICS_INTERVAL_LIMIT_1 0x3c44
56103 #define A_MAC_PORT_PLLB_EYE_METRICS_INTERVAL_LIMIT_2 0x3c48
56104 #define A_MAC_PORT_PLLB_EYE_METRICS_INTERVAL_LIMIT_3 0x3c4c
56105 #define A_MAC_PORT_PLLB_EYE_METRICS_INTERVAL_LIMIT_4 0x3c50
56106 #define A_MAC_PORT_PLLB_MACRO_TEST_CONTROL_4 0x3cf0
56107 #define A_MAC_PORT_PLLB_MACRO_TEST_CONTROL_3 0x3cf4
56108 #define A_MAC_PORT_PLLB_MACRO_TEST_CONTROL_2 0x3cf8
56109 #define A_MAC_PORT_PLLB_MACRO_TEST_CONTROL_1 0x3cfc
56110 #define A_MAC_PORT_TX_LINKA_TRANSMIT_802_3AP_STEP_SIZE_EXTENDED 0x0
56111 
56112 #define S_STEP    0
56113 #define M_STEP    0x7U
56114 #define V_STEP(x) ((x) << S_STEP)
56115 #define G_STEP(x) (((x) >> S_STEP) & M_STEP)
56116 
56117 #define A_MAC_PORT_TX_LINKA_TRANSMIT_AE_STEP_SIZE_EXTENDED 0x0
56118 #define A_MAC_PORT_TX_LINKA_TRANSMIT_802_3AP_C0_INIT_EXTENDED 0x8
56119 
56120 #define S_C0INIT    0
56121 #define M_C0INIT    0x1fU
56122 #define V_C0INIT(x) ((x) << S_C0INIT)
56123 #define G_C0INIT(x) (((x) >> S_C0INIT) & M_C0INIT)
56124 
56125 #define S_C0PRESET    8
56126 #define M_C0PRESET    0x7fU
56127 #define V_C0PRESET(x) ((x) << S_C0PRESET)
56128 #define G_C0PRESET(x) (((x) >> S_C0PRESET) & M_C0PRESET)
56129 
56130 #define S_C0INIT1    0
56131 #define M_C0INIT1    0x7fU
56132 #define V_C0INIT1(x) ((x) << S_C0INIT1)
56133 #define G_C0INIT1(x) (((x) >> S_C0INIT1) & M_C0INIT1)
56134 
56135 #define A_MAC_PORT_TX_LINKA_TRANSMIT_802_3AP_C0_LIMIT_EXTENDED 0x10
56136 
56137 #define S_C0MAX    8
56138 #define M_C0MAX    0x1fU
56139 #define V_C0MAX(x) ((x) << S_C0MAX)
56140 #define G_C0MAX(x) (((x) >> S_C0MAX) & M_C0MAX)
56141 
56142 #define S_C0MIN    0
56143 #define M_C0MIN    0x1fU
56144 #define V_C0MIN(x) ((x) << S_C0MIN)
56145 #define G_C0MIN(x) (((x) >> S_C0MIN) & M_C0MIN)
56146 
56147 #define A_MAC_PORT_TX_LINKA_TRANSMIT_AE_C0_LIMIT_EXTENDED 0x10
56148 
56149 #define S_T6_C0MAX    8
56150 #define M_T6_C0MAX    0x7fU
56151 #define V_T6_C0MAX(x) ((x) << S_T6_C0MAX)
56152 #define G_T6_C0MAX(x) (((x) >> S_T6_C0MAX) & M_T6_C0MAX)
56153 
56154 #define S_T6_C0MIN    0
56155 #define M_T6_C0MIN    0x7fU
56156 #define V_T6_C0MIN(x) ((x) << S_T6_C0MIN)
56157 #define G_T6_C0MIN(x) (((x) >> S_T6_C0MIN) & M_T6_C0MIN)
56158 
56159 #define A_MAC_PORT_TX_LINKA_TRANSMIT_802_3AP_C1_INIT_EXTENDED 0x18
56160 
56161 #define S_C1INIT    0
56162 #define M_C1INIT    0x7fU
56163 #define V_C1INIT(x) ((x) << S_C1INIT)
56164 #define G_C1INIT(x) (((x) >> S_C1INIT) & M_C1INIT)
56165 
56166 #define A_MAC_PORT_TX_LINKA_TRANSMIT_AE_C1_INIT_EXTENDED 0x18
56167 
56168 #define S_C1PRESET    8
56169 #define M_C1PRESET    0x7fU
56170 #define V_C1PRESET(x) ((x) << S_C1PRESET)
56171 #define G_C1PRESET(x) (((x) >> S_C1PRESET) & M_C1PRESET)
56172 
56173 #define S_C1INIT1    0
56174 #define M_C1INIT1    0x7fU
56175 #define V_C1INIT1(x) ((x) << S_C1INIT1)
56176 #define G_C1INIT1(x) (((x) >> S_C1INIT1) & M_C1INIT1)
56177 
56178 #define A_MAC_PORT_TX_LINKA_TRANSMIT_802_3AP_C1_LIMIT_EXTENDED 0x20
56179 
56180 #define S_C1MAX    8
56181 #define M_C1MAX    0x7fU
56182 #define V_C1MAX(x) ((x) << S_C1MAX)
56183 #define G_C1MAX(x) (((x) >> S_C1MAX) & M_C1MAX)
56184 
56185 #define S_C1MIN    0
56186 #define M_C1MIN    0x7fU
56187 #define V_C1MIN(x) ((x) << S_C1MIN)
56188 #define G_C1MIN(x) (((x) >> S_C1MIN) & M_C1MIN)
56189 
56190 #define A_MAC_PORT_TX_LINKA_TRANSMIT_AE_C1_LIMIT_EXTENDED 0x20
56191 #define A_MAC_PORT_TX_LINKA_TRANSMIT_802_3AP_C2_INIT_EXTENDED 0x28
56192 
56193 #define S_C2INIT    0
56194 #define M_C2INIT    0x3fU
56195 #define V_C2INIT(x) ((x) << S_C2INIT)
56196 #define G_C2INIT(x) (((x) >> S_C2INIT) & M_C2INIT)
56197 
56198 #define A_MAC_PORT_TX_LINKA_TRANSMIT_AE_C2_INIT_EXTENDED 0x28
56199 
56200 #define S_C2PRESET    8
56201 #define M_C2PRESET    0x7fU
56202 #define V_C2PRESET(x) ((x) << S_C2PRESET)
56203 #define G_C2PRESET(x) (((x) >> S_C2PRESET) & M_C2PRESET)
56204 
56205 #define S_C2INIT1    0
56206 #define M_C2INIT1    0x7fU
56207 #define V_C2INIT1(x) ((x) << S_C2INIT1)
56208 #define G_C2INIT1(x) (((x) >> S_C2INIT1) & M_C2INIT1)
56209 
56210 #define A_MAC_PORT_TX_LINKA_TRANSMIT_802_3AP_C2_LIMIT_EXTENDED 0x30
56211 
56212 #define S_C2MAX    8
56213 #define M_C2MAX    0x3fU
56214 #define V_C2MAX(x) ((x) << S_C2MAX)
56215 #define G_C2MAX(x) (((x) >> S_C2MAX) & M_C2MAX)
56216 
56217 #define S_C2MIN    0
56218 #define M_C2MIN    0x3fU
56219 #define V_C2MIN(x) ((x) << S_C2MIN)
56220 #define G_C2MIN(x) (((x) >> S_C2MIN) & M_C2MIN)
56221 
56222 #define A_MAC_PORT_TX_LINKA_TRANSMIT_AE_C2_LIMIT_EXTENDED 0x30
56223 
56224 #define S_T6_C2MAX    8
56225 #define M_T6_C2MAX    0x7fU
56226 #define V_T6_C2MAX(x) ((x) << S_T6_C2MAX)
56227 #define G_T6_C2MAX(x) (((x) >> S_T6_C2MAX) & M_T6_C2MAX)
56228 
56229 #define S_T6_C2MIN    0
56230 #define M_T6_C2MIN    0x7fU
56231 #define V_T6_C2MIN(x) ((x) << S_T6_C2MIN)
56232 #define G_T6_C2MIN(x) (((x) >> S_T6_C2MIN) & M_T6_C2MIN)
56233 
56234 #define A_MAC_PORT_TX_LINKA_TRANSMIT_802_3AP_VM_LIMIT_EXTENDED 0x38
56235 
56236 #define S_VMMAX    0
56237 #define M_VMMAX    0x7fU
56238 #define V_VMMAX(x) ((x) << S_VMMAX)
56239 #define G_VMMAX(x) (((x) >> S_VMMAX) & M_VMMAX)
56240 
56241 #define A_MAC_PORT_TX_LINKA_TRANSMIT_AE_VM_LIMIT_EXTENDED 0x38
56242 #define A_MAC_PORT_TX_LINKA_TRANSMIT_802_3AP_V2_LIMIT_EXTENDED 0x40
56243 
56244 #define S_V2MIN    0
56245 #define M_V2MIN    0x7fU
56246 #define V_V2MIN(x) ((x) << S_V2MIN)
56247 #define G_V2MIN(x) (((x) >> S_V2MIN) & M_V2MIN)
56248 
56249 #define A_MAC_PORT_TX_LINKA_TRANSMIT_AE_V2_LIMIT_EXTENDED 0x40
56250 #define A_MAC_PORT_TX_LINKA_TRANSMIT_AE_C3_INIT_EXTENDED 0x48
56251 
56252 #define S_C3PRESET    8
56253 #define M_C3PRESET    0x7fU
56254 #define V_C3PRESET(x) ((x) << S_C3PRESET)
56255 #define G_C3PRESET(x) (((x) >> S_C3PRESET) & M_C3PRESET)
56256 
56257 #define S_C3INIT1    0
56258 #define M_C3INIT1    0x7fU
56259 #define V_C3INIT1(x) ((x) << S_C3INIT1)
56260 #define G_C3INIT1(x) (((x) >> S_C3INIT1) & M_C3INIT1)
56261 
56262 #define A_MAC_PORT_TX_LINKA_TRANSMIT_AE_C3_LIMIT_EXTENDED 0x50
56263 
56264 #define S_C3MAX    8
56265 #define M_C3MAX    0x7fU
56266 #define V_C3MAX(x) ((x) << S_C3MAX)
56267 #define G_C3MAX(x) (((x) >> S_C3MAX) & M_C3MAX)
56268 
56269 #define S_C3MIN    0
56270 #define M_C3MIN    0x7fU
56271 #define V_C3MIN(x) ((x) << S_C3MIN)
56272 #define G_C3MIN(x) (((x) >> S_C3MIN) & M_C3MIN)
56273 
56274 #define A_MAC_PORT_TX_LINKA_TRANSMIT_AE_C0_INIT2_EXTENDED 0x5c
56275 
56276 #define S_C0INIT2    0
56277 #define M_C0INIT2    0x7fU
56278 #define V_C0INIT2(x) ((x) << S_C0INIT2)
56279 #define G_C0INIT2(x) (((x) >> S_C0INIT2) & M_C0INIT2)
56280 
56281 #define A_MAC_PORT_TX_LINKA_TRANSMIT_AE_C1_INIT2_EXTENDED 0x60
56282 
56283 #define S_C1INIT2    0
56284 #define M_C1INIT2    0x7fU
56285 #define V_C1INIT2(x) ((x) << S_C1INIT2)
56286 #define G_C1INIT2(x) (((x) >> S_C1INIT2) & M_C1INIT2)
56287 
56288 #define A_MAC_PORT_TX_LINKA_TRANSMIT_AE_C2_INIT2_EXTENDED 0x68
56289 
56290 #define S_C2INIT2    0
56291 #define M_C2INIT2    0x7fU
56292 #define V_C2INIT2(x) ((x) << S_C2INIT2)
56293 #define G_C2INIT2(x) (((x) >> S_C2INIT2) & M_C2INIT2)
56294 
56295 #define A_MAC_PORT_TX_LINKA_TRANSMIT_AE_C3_INIT2_EXTENDED 0x70
56296 
56297 #define S_C3INIT2    0
56298 #define M_C3INIT2    0x7fU
56299 #define V_C3INIT2(x) ((x) << S_C3INIT2)
56300 #define G_C3INIT2(x) (((x) >> S_C3INIT2) & M_C3INIT2)
56301 
56302 #define A_MAC_PORT_TX_LINKB_TRANSMIT_802_3AP_STEP_SIZE_EXTENDED 0x0
56303 #define A_MAC_PORT_TX_LINKB_TRANSMIT_AE_STEP_SIZE_EXTENDED 0x0
56304 #define A_MAC_PORT_TX_LINKB_TRANSMIT_802_3AP_C0_INIT_EXTENDED 0x8
56305 #define A_MAC_PORT_TX_LINKB_TRANSMIT_802_3AP_C0_LIMIT_EXTENDED 0x10
56306 #define A_MAC_PORT_TX_LINKB_TRANSMIT_AE_C0_LIMIT_EXTENDED 0x10
56307 
56308 #define S_T6_C0MAX    8
56309 #define M_T6_C0MAX    0x7fU
56310 #define V_T6_C0MAX(x) ((x) << S_T6_C0MAX)
56311 #define G_T6_C0MAX(x) (((x) >> S_T6_C0MAX) & M_T6_C0MAX)
56312 
56313 #define S_T6_C0MIN    0
56314 #define M_T6_C0MIN    0x7fU
56315 #define V_T6_C0MIN(x) ((x) << S_T6_C0MIN)
56316 #define G_T6_C0MIN(x) (((x) >> S_T6_C0MIN) & M_T6_C0MIN)
56317 
56318 #define A_MAC_PORT_TX_LINKB_TRANSMIT_802_3AP_C1_INIT_EXTENDED 0x18
56319 #define A_MAC_PORT_TX_LINKB_TRANSMIT_AE_C1_INIT_EXTENDED 0x18
56320 #define A_MAC_PORT_TX_LINKB_TRANSMIT_802_3AP_C1_LIMIT_EXTENDED 0x20
56321 #define A_MAC_PORT_TX_LINKB_TRANSMIT_AE_C1_LIMIT_EXTENDED 0x20
56322 #define A_MAC_PORT_TX_LINKB_TRANSMIT_802_3AP_C2_INIT_EXTENDED 0x28
56323 #define A_MAC_PORT_TX_LINKB_TRANSMIT_AE_C2_INIT_EXTENDED 0x28
56324 #define A_MAC_PORT_TX_LINKB_TRANSMIT_802_3AP_C2_LIMIT_EXTENDED 0x30
56325 #define A_MAC_PORT_TX_LINKB_TRANSMIT_AE_C2_LIMIT_EXTENDED 0x30
56326 
56327 #define S_T6_C2MAX    8
56328 #define M_T6_C2MAX    0x7fU
56329 #define V_T6_C2MAX(x) ((x) << S_T6_C2MAX)
56330 #define G_T6_C2MAX(x) (((x) >> S_T6_C2MAX) & M_T6_C2MAX)
56331 
56332 #define S_T6_C2MIN    0
56333 #define M_T6_C2MIN    0x7fU
56334 #define V_T6_C2MIN(x) ((x) << S_T6_C2MIN)
56335 #define G_T6_C2MIN(x) (((x) >> S_T6_C2MIN) & M_T6_C2MIN)
56336 
56337 #define A_MAC_PORT_TX_LINKB_TRANSMIT_802_3AP_VM_LIMIT_EXTENDED 0x38
56338 #define A_MAC_PORT_TX_LINKB_TRANSMIT_AE_VM_LIMIT_EXTENDED 0x38
56339 #define A_MAC_PORT_TX_LINKB_TRANSMIT_802_3AP_V2_LIMIT_EXTENDED 0x40
56340 #define A_MAC_PORT_TX_LINKB_TRANSMIT_AE_V2_LIMIT_EXTENDED 0x40
56341 #define A_MAC_PORT_TX_LINKB_TRANSMIT_AE_C3_INIT_EXTENDED 0x48
56342 #define A_MAC_PORT_TX_LINKB_TRANSMIT_AE_C3_LIMIT_EXTENDED 0x50
56343 #define A_MAC_PORT_TX_LINKB_TRANSMIT_AE_C0_INIT2_EXTENDED 0x5c
56344 #define A_MAC_PORT_TX_LINKB_TRANSMIT_AE_C1_INIT2_EXTENDED 0x60
56345 #define A_MAC_PORT_TX_LINKB_TRANSMIT_AE_C2_INIT2_EXTENDED 0x68
56346 #define A_MAC_PORT_TX_LINKB_TRANSMIT_AE_C3_INIT2_EXTENDED 0x70
56347 #define A_MAC_PORT_TX_LINKC_TRANSMIT_802_3AP_STEP_SIZE_EXTENDED 0x0
56348 #define A_MAC_PORT_TX_LINKC_TRANSMIT_AE_STEP_SIZE_EXTENDED 0x0
56349 #define A_MAC_PORT_TX_LINKC_TRANSMIT_802_3AP_C0_INIT_EXTENDED 0x8
56350 #define A_MAC_PORT_TX_LINKC_TRANSMIT_802_3AP_C0_LIMIT_EXTENDED 0x10
56351 #define A_MAC_PORT_TX_LINKC_TRANSMIT_AE_C0_LIMIT_EXTENDED 0x10
56352 
56353 #define S_T6_C0MAX    8
56354 #define M_T6_C0MAX    0x7fU
56355 #define V_T6_C0MAX(x) ((x) << S_T6_C0MAX)
56356 #define G_T6_C0MAX(x) (((x) >> S_T6_C0MAX) & M_T6_C0MAX)
56357 
56358 #define S_T6_C0MIN    0
56359 #define M_T6_C0MIN    0x7fU
56360 #define V_T6_C0MIN(x) ((x) << S_T6_C0MIN)
56361 #define G_T6_C0MIN(x) (((x) >> S_T6_C0MIN) & M_T6_C0MIN)
56362 
56363 #define A_MAC_PORT_TX_LINKC_TRANSMIT_802_3AP_C1_INIT_EXTENDED 0x18
56364 #define A_MAC_PORT_TX_LINKC_TRANSMIT_AE_C1_INIT_EXTENDED 0x18
56365 #define A_MAC_PORT_TX_LINKC_TRANSMIT_802_3AP_C1_LIMIT_EXTENDED 0x20
56366 #define A_MAC_PORT_TX_LINKC_TRANSMIT_AE_C1_LIMIT_EXTENDED 0x20
56367 #define A_MAC_PORT_TX_LINKC_TRANSMIT_802_3AP_C2_INIT_EXTENDED 0x28
56368 #define A_MAC_PORT_TX_LINKC_TRANSMIT_AE_C2_INIT_EXTENDED 0x28
56369 #define A_MAC_PORT_TX_LINKC_TRANSMIT_802_3AP_C2_LIMIT_EXTENDED 0x30
56370 #define A_MAC_PORT_TX_LINKC_TRANSMIT_AE_C2_LIMIT_EXTENDED 0x30
56371 
56372 #define S_T6_C2MAX    8
56373 #define M_T6_C2MAX    0x7fU
56374 #define V_T6_C2MAX(x) ((x) << S_T6_C2MAX)
56375 #define G_T6_C2MAX(x) (((x) >> S_T6_C2MAX) & M_T6_C2MAX)
56376 
56377 #define S_T6_C2MIN    0
56378 #define M_T6_C2MIN    0x7fU
56379 #define V_T6_C2MIN(x) ((x) << S_T6_C2MIN)
56380 #define G_T6_C2MIN(x) (((x) >> S_T6_C2MIN) & M_T6_C2MIN)
56381 
56382 #define A_MAC_PORT_TX_LINKC_TRANSMIT_802_3AP_VM_LIMIT_EXTENDED 0x38
56383 #define A_MAC_PORT_TX_LINKC_TRANSMIT_AE_VM_LIMIT_EXTENDED 0x38
56384 #define A_MAC_PORT_TX_LINKC_TRANSMIT_802_3AP_V2_LIMIT_EXTENDED 0x40
56385 #define A_MAC_PORT_TX_LINKC_TRANSMIT_AE_V2_LIMIT_EXTENDED 0x40
56386 #define A_MAC_PORT_TX_LINKC_TRANSMIT_AE_C3_INIT_EXTENDED 0x48
56387 #define A_MAC_PORT_TX_LINKC_TRANSMIT_AE_C3_LIMIT_EXTENDED 0x50
56388 #define A_MAC_PORT_TX_LINKC_TRANSMIT_AE_C0_INIT2_EXTENDED 0x5c
56389 #define A_MAC_PORT_TX_LINKC_TRANSMIT_AE_C1_INIT2_EXTENDED 0x60
56390 #define A_MAC_PORT_TX_LINKC_TRANSMIT_AE_C2_INIT2_EXTENDED 0x68
56391 #define A_MAC_PORT_TX_LINKC_TRANSMIT_AE_C3_INIT2_EXTENDED 0x70
56392 #define A_MAC_PORT_TX_LINKD_TRANSMIT_802_3AP_STEP_SIZE_EXTENDED 0x0
56393 #define A_MAC_PORT_TX_LINKD_TRANSMIT_AE_STEP_SIZE_EXTENDED 0x0
56394 #define A_MAC_PORT_TX_LINKD_TRANSMIT_802_3AP_C0_INIT_EXTENDED 0x8
56395 #define A_MAC_PORT_TX_LINKD_TRANSMIT_802_3AP_C0_LIMIT_EXTENDED 0x10
56396 #define A_MAC_PORT_TX_LINKD_TRANSMIT_AE_C0_LIMIT_EXTENDED 0x10
56397 
56398 #define S_T6_C0MAX    8
56399 #define M_T6_C0MAX    0x7fU
56400 #define V_T6_C0MAX(x) ((x) << S_T6_C0MAX)
56401 #define G_T6_C0MAX(x) (((x) >> S_T6_C0MAX) & M_T6_C0MAX)
56402 
56403 #define S_T6_C0MIN    0
56404 #define M_T6_C0MIN    0x7fU
56405 #define V_T6_C0MIN(x) ((x) << S_T6_C0MIN)
56406 #define G_T6_C0MIN(x) (((x) >> S_T6_C0MIN) & M_T6_C0MIN)
56407 
56408 #define A_MAC_PORT_TX_LINKD_TRANSMIT_802_3AP_C1_INIT_EXTENDED 0x18
56409 #define A_MAC_PORT_TX_LINKD_TRANSMIT_AE_C1_INIT_EXTENDED 0x18
56410 #define A_MAC_PORT_TX_LINKD_TRANSMIT_802_3AP_C1_LIMIT_EXTENDED 0x20
56411 #define A_MAC_PORT_TX_LINKD_TRANSMIT_AE_C1_LIMIT_EXTENDED 0x20
56412 #define A_MAC_PORT_TX_LINKD_TRANSMIT_802_3AP_C2_INIT_EXTENDED 0x28
56413 #define A_MAC_PORT_TX_LINKD_TRANSMIT_AE_C2_INIT_EXTENDED 0x28
56414 #define A_MAC_PORT_TX_LINKD_TRANSMIT_802_3AP_C2_LIMIT_EXTENDED 0x30
56415 #define A_MAC_PORT_TX_LINKD_TRANSMIT_AE_C2_LIMIT_EXTENDED 0x30
56416 
56417 #define S_T6_C2MAX    8
56418 #define M_T6_C2MAX    0x7fU
56419 #define V_T6_C2MAX(x) ((x) << S_T6_C2MAX)
56420 #define G_T6_C2MAX(x) (((x) >> S_T6_C2MAX) & M_T6_C2MAX)
56421 
56422 #define S_T6_C2MIN    0
56423 #define M_T6_C2MIN    0x7fU
56424 #define V_T6_C2MIN(x) ((x) << S_T6_C2MIN)
56425 #define G_T6_C2MIN(x) (((x) >> S_T6_C2MIN) & M_T6_C2MIN)
56426 
56427 #define A_MAC_PORT_TX_LINKD_TRANSMIT_802_3AP_VM_LIMIT_EXTENDED 0x38
56428 #define A_MAC_PORT_TX_LINKD_TRANSMIT_AE_VM_LIMIT_EXTENDED 0x38
56429 #define A_MAC_PORT_TX_LINKD_TRANSMIT_802_3AP_V2_LIMIT_EXTENDED 0x40
56430 #define A_MAC_PORT_TX_LINKD_TRANSMIT_AE_V2_LIMIT_EXTENDED 0x40
56431 #define A_MAC_PORT_TX_LINKD_TRANSMIT_AE_C3_INIT_EXTENDED 0x48
56432 #define A_MAC_PORT_TX_LINKD_TRANSMIT_AE_C3_LIMIT_EXTENDED 0x50
56433 #define A_MAC_PORT_TX_LINKD_TRANSMIT_AE_C0_INIT2_EXTENDED 0x5c
56434 #define A_MAC_PORT_TX_LINKD_TRANSMIT_AE_C1_INIT2_EXTENDED 0x60
56435 #define A_MAC_PORT_TX_LINKD_TRANSMIT_AE_C2_INIT2_EXTENDED 0x68
56436 #define A_MAC_PORT_TX_LINKD_TRANSMIT_AE_C3_INIT2_EXTENDED 0x70
56437 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_802_3AP_STEP_SIZE_EXTENDED 0x0
56438 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_AE_STEP_SIZE_EXTENDED 0x0
56439 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_802_3AP_C0_INIT_EXTENDED 0x8
56440 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_802_3AP_C0_LIMIT_EXTENDED 0x10
56441 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_AE_C0_LIMIT_EXTENDED 0x10
56442 
56443 #define S_T6_C0MAX    8
56444 #define M_T6_C0MAX    0x7fU
56445 #define V_T6_C0MAX(x) ((x) << S_T6_C0MAX)
56446 #define G_T6_C0MAX(x) (((x) >> S_T6_C0MAX) & M_T6_C0MAX)
56447 
56448 #define S_T6_C0MIN    0
56449 #define M_T6_C0MIN    0x7fU
56450 #define V_T6_C0MIN(x) ((x) << S_T6_C0MIN)
56451 #define G_T6_C0MIN(x) (((x) >> S_T6_C0MIN) & M_T6_C0MIN)
56452 
56453 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_802_3AP_C1_INIT_EXTENDED 0x18
56454 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_AE_C1_INIT_EXTENDED 0x18
56455 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_802_3AP_C1_LIMIT_EXTENDED 0x20
56456 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_AE_C1_LIMIT_EXTENDED 0x20
56457 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_802_3AP_C2_INIT_EXTENDED 0x28
56458 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_AE_C2_INIT_EXTENDED 0x28
56459 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_802_3AP_C2_LIMIT_EXTENDED 0x30
56460 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_AE_C2_LIMIT_EXTENDED 0x30
56461 
56462 #define S_T6_C2MAX    8
56463 #define M_T6_C2MAX    0x7fU
56464 #define V_T6_C2MAX(x) ((x) << S_T6_C2MAX)
56465 #define G_T6_C2MAX(x) (((x) >> S_T6_C2MAX) & M_T6_C2MAX)
56466 
56467 #define S_T6_C2MIN    0
56468 #define M_T6_C2MIN    0x7fU
56469 #define V_T6_C2MIN(x) ((x) << S_T6_C2MIN)
56470 #define G_T6_C2MIN(x) (((x) >> S_T6_C2MIN) & M_T6_C2MIN)
56471 
56472 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_802_3AP_VM_LIMIT_EXTENDED 0x38
56473 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_AE_VM_LIMIT_EXTENDED 0x38
56474 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_802_3AP_V2_LIMIT_EXTENDED 0x40
56475 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_AE_V2_LIMIT_EXTENDED 0x40
56476 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_AE_C3_INIT_EXTENDED 0x48
56477 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_AE_C3_LIMIT_EXTENDED 0x50
56478 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_AE_C0_INIT2_EXTENDED 0x5c
56479 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_AE_C1_INIT2_EXTENDED 0x60
56480 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_AE_C2_INIT2_EXTENDED 0x68
56481 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_AE_C3_INIT2_EXTENDED 0x70
56482 #define A_T6_MAC_PORT_RX_LINKA_DFE_TAP_ENABLE 0x2a00
56483 
56484 #define S_RX_LINKA_INDEX_DFE_EN    1
56485 #define M_RX_LINKA_INDEX_DFE_EN    0x7fffU
56486 #define V_RX_LINKA_INDEX_DFE_EN(x) ((x) << S_RX_LINKA_INDEX_DFE_EN)
56487 #define G_RX_LINKA_INDEX_DFE_EN(x) (((x) >> S_RX_LINKA_INDEX_DFE_EN) & M_RX_LINKA_INDEX_DFE_EN)
56488 
56489 #define A_T6_MAC_PORT_RX_LINKA_DFE_H1 0x2a04
56490 
56491 #define S_T6_H1OSN    13
56492 #define M_T6_H1OSN    0x7U
56493 #define V_T6_H1OSN(x) ((x) << S_T6_H1OSN)
56494 #define G_T6_H1OSN(x) (((x) >> S_T6_H1OSN) & M_T6_H1OSN)
56495 
56496 #define S_T6_H1OMAG    8
56497 #define M_T6_H1OMAG    0x1fU
56498 #define V_T6_H1OMAG(x) ((x) << S_T6_H1OMAG)
56499 #define G_T6_H1OMAG(x) (((x) >> S_T6_H1OMAG) & M_T6_H1OMAG)
56500 
56501 #define A_T6_MAC_PORT_RX_LINKA_DFE_H2 0x2a08
56502 #define A_T6_MAC_PORT_RX_LINKA_DFE_H3 0x2a0c
56503 #define A_T6_MAC_PORT_RX_LINKA_DFE_H4 0x2a10
56504 
56505 #define S_H4SN    4
56506 #define M_H4SN    0x3U
56507 #define V_H4SN(x) ((x) << S_H4SN)
56508 #define G_H4SN(x) (((x) >> S_H4SN) & M_H4SN)
56509 
56510 #define S_H4MAG    0
56511 #define M_H4MAG    0xfU
56512 #define V_H4MAG(x) ((x) << S_H4MAG)
56513 #define G_H4MAG(x) (((x) >> S_H4MAG) & M_H4MAG)
56514 
56515 #define A_T6_MAC_PORT_RX_LINKA_DFE_H5 0x2a14
56516 
56517 #define S_H5GS    6
56518 #define M_H5GS    0x3U
56519 #define V_H5GS(x) ((x) << S_H5GS)
56520 #define G_H5GS(x) (((x) >> S_H5GS) & M_H5GS)
56521 
56522 #define S_H5SN    4
56523 #define M_H5SN    0x3U
56524 #define V_H5SN(x) ((x) << S_H5SN)
56525 #define G_H5SN(x) (((x) >> S_H5SN) & M_H5SN)
56526 
56527 #define S_H5MAG    0
56528 #define M_H5MAG    0xfU
56529 #define V_H5MAG(x) ((x) << S_H5MAG)
56530 #define G_H5MAG(x) (((x) >> S_H5MAG) & M_H5MAG)
56531 
56532 #define A_T6_MAC_PORT_RX_LINKA_DFE_H6_AND_H7 0x2a18
56533 
56534 #define S_H7SN    12
56535 #define M_H7SN    0x3U
56536 #define V_H7SN(x) ((x) << S_H7SN)
56537 #define G_H7SN(x) (((x) >> S_H7SN) & M_H7SN)
56538 
56539 #define S_H6SN    4
56540 #define M_H6SN    0x3U
56541 #define V_H6SN(x) ((x) << S_H6SN)
56542 #define G_H6SN(x) (((x) >> S_H6SN) & M_H6SN)
56543 
56544 #define A_T6_MAC_PORT_RX_LINKA_DFE_H8_AND_H9 0x2a1c
56545 
56546 #define S_H9SN    12
56547 #define M_H9SN    0x3U
56548 #define V_H9SN(x) ((x) << S_H9SN)
56549 #define G_H9SN(x) (((x) >> S_H9SN) & M_H9SN)
56550 
56551 #define S_H8SN    4
56552 #define M_H8SN    0x3U
56553 #define V_H8SN(x) ((x) << S_H8SN)
56554 #define G_H8SN(x) (((x) >> S_H8SN) & M_H8SN)
56555 
56556 #define A_T6_MAC_PORT_RX_LINKA_DFE_H10_AND_H11 0x2a20
56557 
56558 #define S_H11SN    12
56559 #define M_H11SN    0x3U
56560 #define V_H11SN(x) ((x) << S_H11SN)
56561 #define G_H11SN(x) (((x) >> S_H11SN) & M_H11SN)
56562 
56563 #define S_H10SN    4
56564 #define M_H10SN    0x3U
56565 #define V_H10SN(x) ((x) << S_H10SN)
56566 #define G_H10SN(x) (((x) >> S_H10SN) & M_H10SN)
56567 
56568 #define A_MAC_PORT_RX_LINKA_DFE_H12_13 0x2a24
56569 
56570 #define S_H13GS    13
56571 #define M_H13GS    0x7U
56572 #define V_H13GS(x) ((x) << S_H13GS)
56573 #define G_H13GS(x) (((x) >> S_H13GS) & M_H13GS)
56574 
56575 #define S_H13SN    10
56576 #define M_H13SN    0x7U
56577 #define V_H13SN(x) ((x) << S_H13SN)
56578 #define G_H13SN(x) (((x) >> S_H13SN) & M_H13SN)
56579 
56580 #define S_H13MAG    8
56581 #define M_H13MAG    0x3U
56582 #define V_H13MAG(x) ((x) << S_H13MAG)
56583 #define G_H13MAG(x) (((x) >> S_H13MAG) & M_H13MAG)
56584 
56585 #define S_H12SN    4
56586 #define M_H12SN    0x3U
56587 #define V_H12SN(x) ((x) << S_H12SN)
56588 #define G_H12SN(x) (((x) >> S_H12SN) & M_H12SN)
56589 
56590 #define A_MAC_PORT_RX_LINKA_DFE_H14_15 0x2a28
56591 
56592 #define S_H15GS    13
56593 #define M_H15GS    0x7U
56594 #define V_H15GS(x) ((x) << S_H15GS)
56595 #define G_H15GS(x) (((x) >> S_H15GS) & M_H15GS)
56596 
56597 #define S_H15SN    10
56598 #define M_H15SN    0x7U
56599 #define V_H15SN(x) ((x) << S_H15SN)
56600 #define G_H15SN(x) (((x) >> S_H15SN) & M_H15SN)
56601 
56602 #define S_H15MAG    8
56603 #define M_H15MAG    0x3U
56604 #define V_H15MAG(x) ((x) << S_H15MAG)
56605 #define G_H15MAG(x) (((x) >> S_H15MAG) & M_H15MAG)
56606 
56607 #define S_H14GS    6
56608 #define M_H14GS    0x3U
56609 #define V_H14GS(x) ((x) << S_H14GS)
56610 #define G_H14GS(x) (((x) >> S_H14GS) & M_H14GS)
56611 
56612 #define S_H14SN    4
56613 #define M_H14SN    0x3U
56614 #define V_H14SN(x) ((x) << S_H14SN)
56615 #define G_H14SN(x) (((x) >> S_H14SN) & M_H14SN)
56616 
56617 #define S_H14MAG    0
56618 #define M_H14MAG    0xfU
56619 #define V_H14MAG(x) ((x) << S_H14MAG)
56620 #define G_H14MAG(x) (((x) >> S_H14MAG) & M_H14MAG)
56621 
56622 #define A_MAC_PORT_RX_LINKA_DFE_H1ODD_DELTA_AND_H1EVEN_DELTA 0x2a2c
56623 
56624 #define S_H1ODELTA    8
56625 #define M_H1ODELTA    0x1fU
56626 #define V_H1ODELTA(x) ((x) << S_H1ODELTA)
56627 #define G_H1ODELTA(x) (((x) >> S_H1ODELTA) & M_H1ODELTA)
56628 
56629 #define S_H1EDELTA    0
56630 #define M_H1EDELTA    0x3fU
56631 #define V_H1EDELTA(x) ((x) << S_H1EDELTA)
56632 #define G_H1EDELTA(x) (((x) >> S_H1EDELTA) & M_H1EDELTA)
56633 
56634 #define A_T6_MAC_PORT_RX_LINKB_DFE_TAP_ENABLE 0x2b00
56635 
56636 #define S_RX_LINKB_INDEX_DFE_EN    1
56637 #define M_RX_LINKB_INDEX_DFE_EN    0x7fffU
56638 #define V_RX_LINKB_INDEX_DFE_EN(x) ((x) << S_RX_LINKB_INDEX_DFE_EN)
56639 #define G_RX_LINKB_INDEX_DFE_EN(x) (((x) >> S_RX_LINKB_INDEX_DFE_EN) & M_RX_LINKB_INDEX_DFE_EN)
56640 
56641 #define A_T6_MAC_PORT_RX_LINKB_DFE_H1 0x2b04
56642 
56643 #define S_T6_H1OSN    13
56644 #define M_T6_H1OSN    0x7U
56645 #define V_T6_H1OSN(x) ((x) << S_T6_H1OSN)
56646 #define G_T6_H1OSN(x) (((x) >> S_T6_H1OSN) & M_T6_H1OSN)
56647 
56648 #define S_T6_H1OMAG    8
56649 #define M_T6_H1OMAG    0x1fU
56650 #define V_T6_H1OMAG(x) ((x) << S_T6_H1OMAG)
56651 #define G_T6_H1OMAG(x) (((x) >> S_T6_H1OMAG) & M_T6_H1OMAG)
56652 
56653 #define A_T6_MAC_PORT_RX_LINKB_DFE_H2 0x2b08
56654 #define A_T6_MAC_PORT_RX_LINKB_DFE_H3 0x2b0c
56655 #define A_T6_MAC_PORT_RX_LINKB_DFE_H4 0x2b10
56656 #define A_T6_MAC_PORT_RX_LINKB_DFE_H5 0x2b14
56657 #define A_T6_MAC_PORT_RX_LINKB_DFE_H6_AND_H7 0x2b18
56658 #define A_T6_MAC_PORT_RX_LINKB_DFE_H8_AND_H9 0x2b1c
56659 #define A_T6_MAC_PORT_RX_LINKB_DFE_H10_AND_H11 0x2b20
56660 #define A_MAC_PORT_RX_LINKB_DFE_H12_13 0x2b24
56661 #define A_MAC_PORT_RX_LINKB_DFE_H14_15 0x2b28
56662 #define A_MAC_PORT_RX_LINKB_DFE_H1ODD_DELTA_AND_H1EVEN_DELTA 0x2b2c
56663 #define A_T6_MAC_PORT_RX_LINKC_DFE_TAP_ENABLE 0x2e00
56664 
56665 #define S_RX_LINKC_INDEX_DFE_EN    1
56666 #define M_RX_LINKC_INDEX_DFE_EN    0x7fffU
56667 #define V_RX_LINKC_INDEX_DFE_EN(x) ((x) << S_RX_LINKC_INDEX_DFE_EN)
56668 #define G_RX_LINKC_INDEX_DFE_EN(x) (((x) >> S_RX_LINKC_INDEX_DFE_EN) & M_RX_LINKC_INDEX_DFE_EN)
56669 
56670 #define A_T6_MAC_PORT_RX_LINKC_DFE_H1 0x2e04
56671 
56672 #define S_T6_H1OSN    13
56673 #define M_T6_H1OSN    0x7U
56674 #define V_T6_H1OSN(x) ((x) << S_T6_H1OSN)
56675 #define G_T6_H1OSN(x) (((x) >> S_T6_H1OSN) & M_T6_H1OSN)
56676 
56677 #define S_T6_H1OMAG    8
56678 #define M_T6_H1OMAG    0x1fU
56679 #define V_T6_H1OMAG(x) ((x) << S_T6_H1OMAG)
56680 #define G_T6_H1OMAG(x) (((x) >> S_T6_H1OMAG) & M_T6_H1OMAG)
56681 
56682 #define A_T6_MAC_PORT_RX_LINKC_DFE_H2 0x2e08
56683 #define A_T6_MAC_PORT_RX_LINKC_DFE_H3 0x2e0c
56684 #define A_T6_MAC_PORT_RX_LINKC_DFE_H4 0x2e10
56685 #define A_T6_MAC_PORT_RX_LINKC_DFE_H5 0x2e14
56686 #define A_T6_MAC_PORT_RX_LINKC_DFE_H6_AND_H7 0x2e18
56687 #define A_T6_MAC_PORT_RX_LINKC_DFE_H8_AND_H9 0x2e1c
56688 #define A_T6_MAC_PORT_RX_LINKC_DFE_H10_AND_H11 0x2e20
56689 #define A_MAC_PORT_RX_LINKC_DFE_H12_13 0x2e24
56690 #define A_MAC_PORT_RX_LINKC_DFE_H14_15 0x2e28
56691 #define A_MAC_PORT_RX_LINKC_DFE_H1ODD_DELTA_AND_H1EVEN_DELTA 0x2e2c
56692 #define A_T6_MAC_PORT_RX_LINKD_DFE_TAP_ENABLE 0x2f00
56693 
56694 #define S_RX_LINKD_INDEX_DFE_EN    1
56695 #define M_RX_LINKD_INDEX_DFE_EN    0x7fffU
56696 #define V_RX_LINKD_INDEX_DFE_EN(x) ((x) << S_RX_LINKD_INDEX_DFE_EN)
56697 #define G_RX_LINKD_INDEX_DFE_EN(x) (((x) >> S_RX_LINKD_INDEX_DFE_EN) & M_RX_LINKD_INDEX_DFE_EN)
56698 
56699 #define A_T6_MAC_PORT_RX_LINKD_DFE_H1 0x2f04
56700 
56701 #define S_T6_H1OSN    13
56702 #define M_T6_H1OSN    0x7U
56703 #define V_T6_H1OSN(x) ((x) << S_T6_H1OSN)
56704 #define G_T6_H1OSN(x) (((x) >> S_T6_H1OSN) & M_T6_H1OSN)
56705 
56706 #define S_T6_H1OMAG    8
56707 #define M_T6_H1OMAG    0x1fU
56708 #define V_T6_H1OMAG(x) ((x) << S_T6_H1OMAG)
56709 #define G_T6_H1OMAG(x) (((x) >> S_T6_H1OMAG) & M_T6_H1OMAG)
56710 
56711 #define A_T6_MAC_PORT_RX_LINKD_DFE_H2 0x2f08
56712 #define A_T6_MAC_PORT_RX_LINKD_DFE_H3 0x2f0c
56713 #define A_T6_MAC_PORT_RX_LINKD_DFE_H4 0x2f10
56714 #define A_T6_MAC_PORT_RX_LINKD_DFE_H5 0x2f14
56715 #define A_T6_MAC_PORT_RX_LINKD_DFE_H6_AND_H7 0x2f18
56716 #define A_T6_MAC_PORT_RX_LINKD_DFE_H8_AND_H9 0x2f1c
56717 #define A_T6_MAC_PORT_RX_LINKD_DFE_H10_AND_H11 0x2f20
56718 #define A_MAC_PORT_RX_LINKD_DFE_H12_13 0x2f24
56719 #define A_MAC_PORT_RX_LINKD_DFE_H14_15 0x2f28
56720 #define A_MAC_PORT_RX_LINKD_DFE_H1ODD_DELTA_AND_H1EVEN_DELTA 0x2f2c
56721 #define A_T6_MAC_PORT_RX_LINK_BCST_DFE_TAP_ENABLE 0x3200
56722 
56723 #define S_RX_LINK_BCST_INDEX_DFE_EN    1
56724 #define M_RX_LINK_BCST_INDEX_DFE_EN    0x7fffU
56725 #define V_RX_LINK_BCST_INDEX_DFE_EN(x) ((x) << S_RX_LINK_BCST_INDEX_DFE_EN)
56726 #define G_RX_LINK_BCST_INDEX_DFE_EN(x) (((x) >> S_RX_LINK_BCST_INDEX_DFE_EN) & M_RX_LINK_BCST_INDEX_DFE_EN)
56727 
56728 #define A_T6_MAC_PORT_RX_LINK_BCST_DFE_H1 0x3204
56729 
56730 #define S_T6_H1OSN    13
56731 #define M_T6_H1OSN    0x7U
56732 #define V_T6_H1OSN(x) ((x) << S_T6_H1OSN)
56733 #define G_T6_H1OSN(x) (((x) >> S_T6_H1OSN) & M_T6_H1OSN)
56734 
56735 #define S_T6_H1OMAG    8
56736 #define M_T6_H1OMAG    0x1fU
56737 #define V_T6_H1OMAG(x) ((x) << S_T6_H1OMAG)
56738 #define G_T6_H1OMAG(x) (((x) >> S_T6_H1OMAG) & M_T6_H1OMAG)
56739 
56740 #define A_T6_MAC_PORT_RX_LINK_BCST_DFE_H2 0x3208
56741 #define A_T6_MAC_PORT_RX_LINK_BCST_DFE_H3 0x320c
56742 #define A_T6_MAC_PORT_RX_LINK_BCST_DFE_H4 0x3210
56743 #define A_T6_MAC_PORT_RX_LINK_BCST_DFE_H5 0x3214
56744 #define A_T6_MAC_PORT_RX_LINK_BCST_DFE_H6_AND_H7 0x3218
56745 #define A_T6_MAC_PORT_RX_LINK_BCST_DFE_H8_AND_H9 0x321c
56746 #define A_T6_MAC_PORT_RX_LINK_BCST_DFE_H10_AND_H11 0x3220
56747 #define A_MAC_PORT_RX_LINK_BCST_DFE_H12_13 0x3224
56748 #define A_MAC_PORT_RX_LINK_BCST_DFE_H14_15 0x3228
56749 #define A_MAC_PORT_RX_LINK_BCST_DFE_H1ODD_DELTA_AND_H1EVEN_DELTA 0x322c
56750 
56751 /* registers for module MC_0 */
56752 #define MC_0_BASE_ADDR 0x40000
56753 
56754 #define A_MC_UPCTL_SCFG 0x40000
56755 
56756 #define S_BBFLAGS_TIMING    8
56757 #define M_BBFLAGS_TIMING    0xfU
56758 #define V_BBFLAGS_TIMING(x) ((x) << S_BBFLAGS_TIMING)
56759 #define G_BBFLAGS_TIMING(x) (((x) >> S_BBFLAGS_TIMING) & M_BBFLAGS_TIMING)
56760 
56761 #define S_NFIFO_NIF1_DIS    6
56762 #define V_NFIFO_NIF1_DIS(x) ((x) << S_NFIFO_NIF1_DIS)
56763 #define F_NFIFO_NIF1_DIS    V_NFIFO_NIF1_DIS(1U)
56764 
56765 #define A_MC_UPCTL_SCTL 0x40004
56766 #define A_MC_UPCTL_STAT 0x40008
56767 
56768 #define S_LP_TRIG    4
56769 #define M_LP_TRIG    0x7U
56770 #define V_LP_TRIG(x) ((x) << S_LP_TRIG)
56771 #define G_LP_TRIG(x) (((x) >> S_LP_TRIG) & M_LP_TRIG)
56772 
56773 #define A_MC_UPCTL_INTRSTAT 0x4000c
56774 
56775 #define S_PARITY_INTR    1
56776 #define V_PARITY_INTR(x) ((x) << S_PARITY_INTR)
56777 #define F_PARITY_INTR    V_PARITY_INTR(1U)
56778 
56779 #define S_ECC_INTR    0
56780 #define V_ECC_INTR(x) ((x) << S_ECC_INTR)
56781 #define F_ECC_INTR    V_ECC_INTR(1U)
56782 
56783 #define A_MC_UPCTL_MCMD 0x40040
56784 
56785 #define S_CMD_OPCODE0    0
56786 #define M_CMD_OPCODE0    0xfU
56787 #define V_CMD_OPCODE0(x) ((x) << S_CMD_OPCODE0)
56788 #define G_CMD_OPCODE0(x) (((x) >> S_CMD_OPCODE0) & M_CMD_OPCODE0)
56789 
56790 #define A_MC_LMC_MCSTAT 0x40040
56791 
56792 #define S_INIT_COMPLETE    31
56793 #define V_INIT_COMPLETE(x) ((x) << S_INIT_COMPLETE)
56794 #define F_INIT_COMPLETE    V_INIT_COMPLETE(1U)
56795 
56796 #define S_SELF_REF_MODE    30
56797 #define V_SELF_REF_MODE(x) ((x) << S_SELF_REF_MODE)
56798 #define F_SELF_REF_MODE    V_SELF_REF_MODE(1U)
56799 
56800 #define S_IDLE    29
56801 #define V_IDLE(x) ((x) << S_IDLE)
56802 #define F_IDLE    V_IDLE(1U)
56803 
56804 #define S_T6_DFI_INIT_COMPLETE    28
56805 #define V_T6_DFI_INIT_COMPLETE(x) ((x) << S_T6_DFI_INIT_COMPLETE)
56806 #define F_T6_DFI_INIT_COMPLETE    V_T6_DFI_INIT_COMPLETE(1U)
56807 
56808 #define S_PREFILL_COMPLETE    27
56809 #define V_PREFILL_COMPLETE(x) ((x) << S_PREFILL_COMPLETE)
56810 #define F_PREFILL_COMPLETE    V_PREFILL_COMPLETE(1U)
56811 
56812 #define A_MC_UPCTL_POWCTL 0x40044
56813 #define A_MC_UPCTL_POWSTAT 0x40048
56814 #define A_MC_UPCTL_CMDTSTAT 0x4004c
56815 
56816 #define S_CMD_TSTAT    0
56817 #define V_CMD_TSTAT(x) ((x) << S_CMD_TSTAT)
56818 #define F_CMD_TSTAT    V_CMD_TSTAT(1U)
56819 
56820 #define A_MC_UPCTL_CMDTSTATEN 0x40050
56821 
56822 #define S_CMD_TSTAT_EN    0
56823 #define V_CMD_TSTAT_EN(x) ((x) << S_CMD_TSTAT_EN)
56824 #define F_CMD_TSTAT_EN    V_CMD_TSTAT_EN(1U)
56825 
56826 #define A_MC_UPCTL_MRRCFG0 0x40060
56827 
56828 #define S_MRR_BYTE_SEL    0
56829 #define M_MRR_BYTE_SEL    0xfU
56830 #define V_MRR_BYTE_SEL(x) ((x) << S_MRR_BYTE_SEL)
56831 #define G_MRR_BYTE_SEL(x) (((x) >> S_MRR_BYTE_SEL) & M_MRR_BYTE_SEL)
56832 
56833 #define A_MC_UPCTL_MRRSTAT0 0x40064
56834 
56835 #define S_MRRSTAT_BEAT3    24
56836 #define M_MRRSTAT_BEAT3    0xffU
56837 #define V_MRRSTAT_BEAT3(x) ((x) << S_MRRSTAT_BEAT3)
56838 #define G_MRRSTAT_BEAT3(x) (((x) >> S_MRRSTAT_BEAT3) & M_MRRSTAT_BEAT3)
56839 
56840 #define S_MRRSTAT_BEAT2    16
56841 #define M_MRRSTAT_BEAT2    0xffU
56842 #define V_MRRSTAT_BEAT2(x) ((x) << S_MRRSTAT_BEAT2)
56843 #define G_MRRSTAT_BEAT2(x) (((x) >> S_MRRSTAT_BEAT2) & M_MRRSTAT_BEAT2)
56844 
56845 #define S_MRRSTAT_BEAT1    8
56846 #define M_MRRSTAT_BEAT1    0xffU
56847 #define V_MRRSTAT_BEAT1(x) ((x) << S_MRRSTAT_BEAT1)
56848 #define G_MRRSTAT_BEAT1(x) (((x) >> S_MRRSTAT_BEAT1) & M_MRRSTAT_BEAT1)
56849 
56850 #define S_MRRSTAT_BEAT0    0
56851 #define M_MRRSTAT_BEAT0    0xffU
56852 #define V_MRRSTAT_BEAT0(x) ((x) << S_MRRSTAT_BEAT0)
56853 #define G_MRRSTAT_BEAT0(x) (((x) >> S_MRRSTAT_BEAT0) & M_MRRSTAT_BEAT0)
56854 
56855 #define A_MC_UPCTL_MRRSTAT1 0x40068
56856 
56857 #define S_MRRSTAT_BEAT7    24
56858 #define M_MRRSTAT_BEAT7    0xffU
56859 #define V_MRRSTAT_BEAT7(x) ((x) << S_MRRSTAT_BEAT7)
56860 #define G_MRRSTAT_BEAT7(x) (((x) >> S_MRRSTAT_BEAT7) & M_MRRSTAT_BEAT7)
56861 
56862 #define S_MRRSTAT_BEAT6    16
56863 #define M_MRRSTAT_BEAT6    0xffU
56864 #define V_MRRSTAT_BEAT6(x) ((x) << S_MRRSTAT_BEAT6)
56865 #define G_MRRSTAT_BEAT6(x) (((x) >> S_MRRSTAT_BEAT6) & M_MRRSTAT_BEAT6)
56866 
56867 #define S_MRRSTAT_BEAT5    8
56868 #define M_MRRSTAT_BEAT5    0xffU
56869 #define V_MRRSTAT_BEAT5(x) ((x) << S_MRRSTAT_BEAT5)
56870 #define G_MRRSTAT_BEAT5(x) (((x) >> S_MRRSTAT_BEAT5) & M_MRRSTAT_BEAT5)
56871 
56872 #define S_MRRSTAT_BEAT4    0
56873 #define M_MRRSTAT_BEAT4    0xffU
56874 #define V_MRRSTAT_BEAT4(x) ((x) << S_MRRSTAT_BEAT4)
56875 #define G_MRRSTAT_BEAT4(x) (((x) >> S_MRRSTAT_BEAT4) & M_MRRSTAT_BEAT4)
56876 
56877 #define A_MC_UPCTL_MCFG1 0x4007c
56878 
56879 #define S_HW_EXIT_IDLE_EN    31
56880 #define V_HW_EXIT_IDLE_EN(x) ((x) << S_HW_EXIT_IDLE_EN)
56881 #define F_HW_EXIT_IDLE_EN    V_HW_EXIT_IDLE_EN(1U)
56882 
56883 #define S_HW_IDLE    16
56884 #define M_HW_IDLE    0xffU
56885 #define V_HW_IDLE(x) ((x) << S_HW_IDLE)
56886 #define G_HW_IDLE(x) (((x) >> S_HW_IDLE) & M_HW_IDLE)
56887 
56888 #define S_SR_IDLE    0
56889 #define M_SR_IDLE    0xffU
56890 #define V_SR_IDLE(x) ((x) << S_SR_IDLE)
56891 #define G_SR_IDLE(x) (((x) >> S_SR_IDLE) & M_SR_IDLE)
56892 
56893 #define A_MC_UPCTL_MCFG 0x40080
56894 
56895 #define S_MDDR_LPDDR2_CLK_STOP_IDLE    24
56896 #define M_MDDR_LPDDR2_CLK_STOP_IDLE    0xffU
56897 #define V_MDDR_LPDDR2_CLK_STOP_IDLE(x) ((x) << S_MDDR_LPDDR2_CLK_STOP_IDLE)
56898 #define G_MDDR_LPDDR2_CLK_STOP_IDLE(x) (((x) >> S_MDDR_LPDDR2_CLK_STOP_IDLE) & M_MDDR_LPDDR2_CLK_STOP_IDLE)
56899 
56900 #define S_MDDR_LPDDR2_EN    22
56901 #define M_MDDR_LPDDR2_EN    0x3U
56902 #define V_MDDR_LPDDR2_EN(x) ((x) << S_MDDR_LPDDR2_EN)
56903 #define G_MDDR_LPDDR2_EN(x) (((x) >> S_MDDR_LPDDR2_EN) & M_MDDR_LPDDR2_EN)
56904 
56905 #define S_MDDR_LPDDR2_BL    20
56906 #define M_MDDR_LPDDR2_BL    0x3U
56907 #define V_MDDR_LPDDR2_BL(x) ((x) << S_MDDR_LPDDR2_BL)
56908 #define G_MDDR_LPDDR2_BL(x) (((x) >> S_MDDR_LPDDR2_BL) & M_MDDR_LPDDR2_BL)
56909 
56910 #define S_LPDDR2_S4    6
56911 #define V_LPDDR2_S4(x) ((x) << S_LPDDR2_S4)
56912 #define F_LPDDR2_S4    V_LPDDR2_S4(1U)
56913 
56914 #define S_STAGGER_CS    4
56915 #define V_STAGGER_CS(x) ((x) << S_STAGGER_CS)
56916 #define F_STAGGER_CS    V_STAGGER_CS(1U)
56917 
56918 #define S_CKE_OR_EN    1
56919 #define V_CKE_OR_EN(x) ((x) << S_CKE_OR_EN)
56920 #define F_CKE_OR_EN    V_CKE_OR_EN(1U)
56921 
56922 #define A_MC_LMC_MCOPT1 0x40080
56923 
56924 #define S_MC_PROTOCOL    31
56925 #define V_MC_PROTOCOL(x) ((x) << S_MC_PROTOCOL)
56926 #define F_MC_PROTOCOL    V_MC_PROTOCOL(1U)
56927 
56928 #define S_DM_ENABLE    30
56929 #define V_DM_ENABLE(x) ((x) << S_DM_ENABLE)
56930 #define F_DM_ENABLE    V_DM_ENABLE(1U)
56931 
56932 #define S_T6_ECC_EN    29
56933 #define V_T6_ECC_EN(x) ((x) << S_T6_ECC_EN)
56934 #define F_T6_ECC_EN    V_T6_ECC_EN(1U)
56935 
56936 #define S_ECC_COR    28
56937 #define V_ECC_COR(x) ((x) << S_ECC_COR)
56938 #define F_ECC_COR    V_ECC_COR(1U)
56939 
56940 #define S_RDIMM    27
56941 #define V_RDIMM(x) ((x) << S_RDIMM)
56942 #define F_RDIMM    V_RDIMM(1U)
56943 
56944 #define S_PMUM    25
56945 #define M_PMUM    0x3U
56946 #define V_PMUM(x) ((x) << S_PMUM)
56947 #define G_PMUM(x) (((x) >> S_PMUM) & M_PMUM)
56948 
56949 #define S_WIDTH0    24
56950 #define V_WIDTH0(x) ((x) << S_WIDTH0)
56951 #define F_WIDTH0    V_WIDTH0(1U)
56952 
56953 #define S_PORT_ID_CHK_EN    23
56954 #define V_PORT_ID_CHK_EN(x) ((x) << S_PORT_ID_CHK_EN)
56955 #define F_PORT_ID_CHK_EN    V_PORT_ID_CHK_EN(1U)
56956 
56957 #define S_UIOS    22
56958 #define V_UIOS(x) ((x) << S_UIOS)
56959 #define F_UIOS    V_UIOS(1U)
56960 
56961 #define S_QUADCS_RDIMM    21
56962 #define V_QUADCS_RDIMM(x) ((x) << S_QUADCS_RDIMM)
56963 #define F_QUADCS_RDIMM    V_QUADCS_RDIMM(1U)
56964 
56965 #define S_ZQCL_EN    20
56966 #define V_ZQCL_EN(x) ((x) << S_ZQCL_EN)
56967 #define F_ZQCL_EN    V_ZQCL_EN(1U)
56968 
56969 #define S_WIDTH1    19
56970 #define V_WIDTH1(x) ((x) << S_WIDTH1)
56971 #define F_WIDTH1    V_WIDTH1(1U)
56972 
56973 #define S_WD_DLY    18
56974 #define V_WD_DLY(x) ((x) << S_WD_DLY)
56975 #define F_WD_DLY    V_WD_DLY(1U)
56976 
56977 #define S_QDEPTH    16
56978 #define M_QDEPTH    0x3U
56979 #define V_QDEPTH(x) ((x) << S_QDEPTH)
56980 #define G_QDEPTH(x) (((x) >> S_QDEPTH) & M_QDEPTH)
56981 
56982 #define S_RWOO    15
56983 #define V_RWOO(x) ((x) << S_RWOO)
56984 #define F_RWOO    V_RWOO(1U)
56985 
56986 #define S_WOOO    14
56987 #define V_WOOO(x) ((x) << S_WOOO)
56988 #define F_WOOO    V_WOOO(1U)
56989 
56990 #define S_DCOO    13
56991 #define V_DCOO(x) ((x) << S_DCOO)
56992 #define F_DCOO    V_DCOO(1U)
56993 
56994 #define S_DEF_REF    12
56995 #define V_DEF_REF(x) ((x) << S_DEF_REF)
56996 #define F_DEF_REF    V_DEF_REF(1U)
56997 
56998 #define S_DEV_TYPE    11
56999 #define V_DEV_TYPE(x) ((x) << S_DEV_TYPE)
57000 #define F_DEV_TYPE    V_DEV_TYPE(1U)
57001 
57002 #define S_CA_PTY_DLY    10
57003 #define V_CA_PTY_DLY(x) ((x) << S_CA_PTY_DLY)
57004 #define F_CA_PTY_DLY    V_CA_PTY_DLY(1U)
57005 
57006 #define S_ECC_MUX    8
57007 #define M_ECC_MUX    0x3U
57008 #define V_ECC_MUX(x) ((x) << S_ECC_MUX)
57009 #define G_ECC_MUX(x) (((x) >> S_ECC_MUX) & M_ECC_MUX)
57010 
57011 #define S_CE_THRESHOLD    0
57012 #define M_CE_THRESHOLD    0xffU
57013 #define V_CE_THRESHOLD(x) ((x) << S_CE_THRESHOLD)
57014 #define G_CE_THRESHOLD(x) (((x) >> S_CE_THRESHOLD) & M_CE_THRESHOLD)
57015 
57016 #define A_MC_UPCTL_PPCFG 0x40084
57017 #define A_MC_LMC_MCOPT2 0x40084
57018 
57019 #define S_SELF_REF_EN    31
57020 #define V_SELF_REF_EN(x) ((x) << S_SELF_REF_EN)
57021 #define F_SELF_REF_EN    V_SELF_REF_EN(1U)
57022 
57023 #define S_XSR_PREVENT    30
57024 #define V_XSR_PREVENT(x) ((x) << S_XSR_PREVENT)
57025 #define F_XSR_PREVENT    V_XSR_PREVENT(1U)
57026 
57027 #define S_INIT_START    29
57028 #define V_INIT_START(x) ((x) << S_INIT_START)
57029 #define F_INIT_START    V_INIT_START(1U)
57030 
57031 #define S_MC_ENABLE    28
57032 #define V_MC_ENABLE(x) ((x) << S_MC_ENABLE)
57033 #define F_MC_ENABLE    V_MC_ENABLE(1U)
57034 
57035 #define S_CLK_DISABLE    24
57036 #define M_CLK_DISABLE    0xfU
57037 #define V_CLK_DISABLE(x) ((x) << S_CLK_DISABLE)
57038 #define G_CLK_DISABLE(x) (((x) >> S_CLK_DISABLE) & M_CLK_DISABLE)
57039 
57040 #define S_RESET_RANK    20
57041 #define M_RESET_RANK    0xfU
57042 #define V_RESET_RANK(x) ((x) << S_RESET_RANK)
57043 #define G_RESET_RANK(x) (((x) >> S_RESET_RANK) & M_RESET_RANK)
57044 
57045 #define S_MCIF_COMP_PTY_EN    19
57046 #define V_MCIF_COMP_PTY_EN(x) ((x) << S_MCIF_COMP_PTY_EN)
57047 #define F_MCIF_COMP_PTY_EN    V_MCIF_COMP_PTY_EN(1U)
57048 
57049 #define S_CKE_OE    17
57050 #define V_CKE_OE(x) ((x) << S_CKE_OE)
57051 #define F_CKE_OE    V_CKE_OE(1U)
57052 
57053 #define S_RESET_OE    16
57054 #define V_RESET_OE(x) ((x) << S_RESET_OE)
57055 #define F_RESET_OE    V_RESET_OE(1U)
57056 
57057 #define S_DFI_PHYUD_CNTL    14
57058 #define V_DFI_PHYUD_CNTL(x) ((x) << S_DFI_PHYUD_CNTL)
57059 #define F_DFI_PHYUD_CNTL    V_DFI_PHYUD_CNTL(1U)
57060 
57061 #define S_DFI_PHYUD_ACK    13
57062 #define V_DFI_PHYUD_ACK(x) ((x) << S_DFI_PHYUD_ACK)
57063 #define F_DFI_PHYUD_ACK    V_DFI_PHYUD_ACK(1U)
57064 
57065 #define S_T6_DFI_INIT_START    12
57066 #define V_T6_DFI_INIT_START(x) ((x) << S_T6_DFI_INIT_START)
57067 #define F_T6_DFI_INIT_START    V_T6_DFI_INIT_START(1U)
57068 
57069 #define S_PM_ENABLE    8
57070 #define M_PM_ENABLE    0xfU
57071 #define V_PM_ENABLE(x) ((x) << S_PM_ENABLE)
57072 #define G_PM_ENABLE(x) (((x) >> S_PM_ENABLE) & M_PM_ENABLE)
57073 
57074 #define S_RD_DEFREF_CNT    4
57075 #define M_RD_DEFREF_CNT    0xfU
57076 #define V_RD_DEFREF_CNT(x) ((x) << S_RD_DEFREF_CNT)
57077 #define G_RD_DEFREF_CNT(x) (((x) >> S_RD_DEFREF_CNT) & M_RD_DEFREF_CNT)
57078 
57079 #define A_MC_UPCTL_MSTAT 0x40088
57080 
57081 #define S_SELF_REFRESH    2
57082 #define V_SELF_REFRESH(x) ((x) << S_SELF_REFRESH)
57083 #define F_SELF_REFRESH    V_SELF_REFRESH(1U)
57084 
57085 #define S_CLOCK_STOP    1
57086 #define V_CLOCK_STOP(x) ((x) << S_CLOCK_STOP)
57087 #define F_CLOCK_STOP    V_CLOCK_STOP(1U)
57088 
57089 #define A_MC_UPCTL_LPDDR2ZQCFG 0x4008c
57090 
57091 #define S_ZQCL_OP    24
57092 #define M_ZQCL_OP    0xffU
57093 #define V_ZQCL_OP(x) ((x) << S_ZQCL_OP)
57094 #define G_ZQCL_OP(x) (((x) >> S_ZQCL_OP) & M_ZQCL_OP)
57095 
57096 #define S_ZQCL_MA    16
57097 #define M_ZQCL_MA    0xffU
57098 #define V_ZQCL_MA(x) ((x) << S_ZQCL_MA)
57099 #define G_ZQCL_MA(x) (((x) >> S_ZQCL_MA) & M_ZQCL_MA)
57100 
57101 #define S_ZQCS_OP    8
57102 #define M_ZQCS_OP    0xffU
57103 #define V_ZQCS_OP(x) ((x) << S_ZQCS_OP)
57104 #define G_ZQCS_OP(x) (((x) >> S_ZQCS_OP) & M_ZQCS_OP)
57105 
57106 #define S_ZQCS_MA    0
57107 #define M_ZQCS_MA    0xffU
57108 #define V_ZQCS_MA(x) ((x) << S_ZQCS_MA)
57109 #define G_ZQCS_MA(x) (((x) >> S_ZQCS_MA) & M_ZQCS_MA)
57110 
57111 #define A_MC_UPCTL_DTUPDES 0x40094
57112 
57113 #define S_DTU_ERR_B7    7
57114 #define V_DTU_ERR_B7(x) ((x) << S_DTU_ERR_B7)
57115 #define F_DTU_ERR_B7    V_DTU_ERR_B7(1U)
57116 
57117 #define A_MC_UPCTL_DTUNA 0x40098
57118 #define A_MC_UPCTL_DTUNE 0x4009c
57119 #define A_MC_UPCTL_DTUPRD0 0x400a0
57120 #define A_MC_UPCTL_DTUPRD1 0x400a4
57121 #define A_MC_UPCTL_DTUPRD2 0x400a8
57122 #define A_MC_UPCTL_DTUPRD3 0x400ac
57123 #define A_MC_UPCTL_DTUAWDT 0x400b0
57124 #define A_MC_UPCTL_TOGCNT1U 0x400c0
57125 #define A_MC_UPCTL_TINIT 0x400c4
57126 #define A_MC_UPCTL_TRSTH 0x400c8
57127 #define A_MC_UPCTL_TOGCNT100N 0x400cc
57128 #define A_MC_UPCTL_TREFI 0x400d0
57129 #define A_MC_UPCTL_TMRD 0x400d4
57130 #define A_MC_UPCTL_TRFC 0x400d8
57131 
57132 #define S_T_RFC0    0
57133 #define M_T_RFC0    0x1ffU
57134 #define V_T_RFC0(x) ((x) << S_T_RFC0)
57135 #define G_T_RFC0(x) (((x) >> S_T_RFC0) & M_T_RFC0)
57136 
57137 #define A_MC_UPCTL_TRP 0x400dc
57138 
57139 #define S_PREA_EXTRA    16
57140 #define M_PREA_EXTRA    0x3U
57141 #define V_PREA_EXTRA(x) ((x) << S_PREA_EXTRA)
57142 #define G_PREA_EXTRA(x) (((x) >> S_PREA_EXTRA) & M_PREA_EXTRA)
57143 
57144 #define A_MC_UPCTL_TRTW 0x400e0
57145 
57146 #define S_T_RTW0    0
57147 #define M_T_RTW0    0xfU
57148 #define V_T_RTW0(x) ((x) << S_T_RTW0)
57149 #define G_T_RTW0(x) (((x) >> S_T_RTW0) & M_T_RTW0)
57150 
57151 #define A_MC_UPCTL_TAL 0x400e4
57152 #define A_MC_UPCTL_TCL 0x400e8
57153 #define A_MC_UPCTL_TCWL 0x400ec
57154 #define A_MC_UPCTL_TRAS 0x400f0
57155 #define A_MC_UPCTL_TRC 0x400f4
57156 #define A_MC_UPCTL_TRCD 0x400f8
57157 #define A_MC_UPCTL_TRRD 0x400fc
57158 #define A_MC_UPCTL_TRTP 0x40100
57159 
57160 #define S_T_RTP0    0
57161 #define M_T_RTP0    0xfU
57162 #define V_T_RTP0(x) ((x) << S_T_RTP0)
57163 #define G_T_RTP0(x) (((x) >> S_T_RTP0) & M_T_RTP0)
57164 
57165 #define A_MC_LMC_CFGR0 0x40100
57166 
57167 #define S_ROW_WIDTH    12
57168 #define M_ROW_WIDTH    0x7U
57169 #define V_ROW_WIDTH(x) ((x) << S_ROW_WIDTH)
57170 #define G_ROW_WIDTH(x) (((x) >> S_ROW_WIDTH) & M_ROW_WIDTH)
57171 
57172 #define S_ADDR_MODE    8
57173 #define M_ADDR_MODE    0xfU
57174 #define V_ADDR_MODE(x) ((x) << S_ADDR_MODE)
57175 #define G_ADDR_MODE(x) (((x) >> S_ADDR_MODE) & M_ADDR_MODE)
57176 
57177 #define S_MIRROR    4
57178 #define V_MIRROR(x) ((x) << S_MIRROR)
57179 #define F_MIRROR    V_MIRROR(1U)
57180 
57181 #define S_RANK_ENABLE    0
57182 #define V_RANK_ENABLE(x) ((x) << S_RANK_ENABLE)
57183 #define F_RANK_ENABLE    V_RANK_ENABLE(1U)
57184 
57185 #define A_MC_UPCTL_TWR 0x40104
57186 
57187 #define S_U_T_WR    0
57188 #define M_U_T_WR    0x1fU
57189 #define V_U_T_WR(x) ((x) << S_U_T_WR)
57190 #define G_U_T_WR(x) (((x) >> S_U_T_WR) & M_U_T_WR)
57191 
57192 #define A_MC_UPCTL_TWTR 0x40108
57193 
57194 #define S_T_WTR0    0
57195 #define M_T_WTR0    0xfU
57196 #define V_T_WTR0(x) ((x) << S_T_WTR0)
57197 #define G_T_WTR0(x) (((x) >> S_T_WTR0) & M_T_WTR0)
57198 
57199 #define A_MC_UPCTL_TEXSR 0x4010c
57200 #define A_MC_UPCTL_TXP 0x40110
57201 #define A_MC_UPCTL_TXPDLL 0x40114
57202 #define A_MC_UPCTL_TZQCS 0x40118
57203 #define A_MC_UPCTL_TZQCSI 0x4011c
57204 #define A_MC_UPCTL_TDQS 0x40120
57205 #define A_MC_UPCTL_TCKSRE 0x40124
57206 
57207 #define S_T_CKSRE0    0
57208 #define M_T_CKSRE0    0x1fU
57209 #define V_T_CKSRE0(x) ((x) << S_T_CKSRE0)
57210 #define G_T_CKSRE0(x) (((x) >> S_T_CKSRE0) & M_T_CKSRE0)
57211 
57212 #define A_MC_UPCTL_TCKSRX 0x40128
57213 
57214 #define S_T_CKSRX0    0
57215 #define M_T_CKSRX0    0x1fU
57216 #define V_T_CKSRX0(x) ((x) << S_T_CKSRX0)
57217 #define G_T_CKSRX0(x) (((x) >> S_T_CKSRX0) & M_T_CKSRX0)
57218 
57219 #define A_MC_UPCTL_TCKE 0x4012c
57220 #define A_MC_UPCTL_TMOD 0x40130
57221 
57222 #define S_T_MOD0    0
57223 #define M_T_MOD0    0x1fU
57224 #define V_T_MOD0(x) ((x) << S_T_MOD0)
57225 #define G_T_MOD0(x) (((x) >> S_T_MOD0) & M_T_MOD0)
57226 
57227 #define A_MC_UPCTL_TRSTL 0x40134
57228 
57229 #define S_T_RSTL    0
57230 #define M_T_RSTL    0x7fU
57231 #define V_T_RSTL(x) ((x) << S_T_RSTL)
57232 #define G_T_RSTL(x) (((x) >> S_T_RSTL) & M_T_RSTL)
57233 
57234 #define A_MC_UPCTL_TZQCL 0x40138
57235 #define A_MC_UPCTL_TMRR 0x4013c
57236 
57237 #define S_T_MRR    0
57238 #define M_T_MRR    0xffU
57239 #define V_T_MRR(x) ((x) << S_T_MRR)
57240 #define G_T_MRR(x) (((x) >> S_T_MRR) & M_T_MRR)
57241 
57242 #define A_MC_UPCTL_TCKESR 0x40140
57243 
57244 #define S_T_CKESR    0
57245 #define M_T_CKESR    0xfU
57246 #define V_T_CKESR(x) ((x) << S_T_CKESR)
57247 #define G_T_CKESR(x) (((x) >> S_T_CKESR) & M_T_CKESR)
57248 
57249 #define A_MC_LMC_INITSEQ0 0x40140
57250 
57251 #define S_INIT_ENABLE    31
57252 #define V_INIT_ENABLE(x) ((x) << S_INIT_ENABLE)
57253 #define F_INIT_ENABLE    V_INIT_ENABLE(1U)
57254 
57255 #define S_WAIT    16
57256 #define M_WAIT    0xfffU
57257 #define CXGBE_V_WAIT(x) ((x) << S_WAIT)
57258 #define G_WAIT(x) (((x) >> S_WAIT) & M_WAIT)
57259 
57260 #define S_EN_MULTI_RANK_SEL    4
57261 #define V_EN_MULTI_RANK_SEL(x) ((x) << S_EN_MULTI_RANK_SEL)
57262 #define F_EN_MULTI_RANK_SEL    V_EN_MULTI_RANK_SEL(1U)
57263 
57264 #define S_T6_RANK    0
57265 #define M_T6_RANK    0xfU
57266 #define V_T6_RANK(x) ((x) << S_T6_RANK)
57267 #define G_T6_RANK(x) (((x) >> S_T6_RANK) & M_T6_RANK)
57268 
57269 #define A_MC_UPCTL_TDPD 0x40144
57270 
57271 #define S_T_DPD    0
57272 #define M_T_DPD    0x3ffU
57273 #define V_T_DPD(x) ((x) << S_T_DPD)
57274 #define G_T_DPD(x) (((x) >> S_T_DPD) & M_T_DPD)
57275 
57276 #define A_MC_LMC_CMD0 0x40144
57277 
57278 #define S_CMD    29
57279 #define M_CMD    0x7U
57280 #define V_CMD(x) ((x) << S_CMD)
57281 #define G_CMD(x) (((x) >> S_CMD) & M_CMD)
57282 
57283 #define S_CMD_ACTN    28
57284 #define V_CMD_ACTN(x) ((x) << S_CMD_ACTN)
57285 #define F_CMD_ACTN    V_CMD_ACTN(1U)
57286 
57287 #define S_BG1    23
57288 #define V_BG1(x) ((x) << S_BG1)
57289 #define F_BG1    V_BG1(1U)
57290 
57291 #define S_BANK    20
57292 #define M_BANK    0x7U
57293 #define V_BANK(x) ((x) << S_BANK)
57294 #define G_BANK(x) (((x) >> S_BANK) & M_BANK)
57295 
57296 #define A_MC_LMC_INITSEQ1 0x40148
57297 
57298 #define S_T6_RANK    0
57299 #define M_T6_RANK    0xfU
57300 #define V_T6_RANK(x) ((x) << S_T6_RANK)
57301 #define G_T6_RANK(x) (((x) >> S_T6_RANK) & M_T6_RANK)
57302 
57303 #define A_MC_LMC_CMD1 0x4014c
57304 #define A_MC_LMC_INITSEQ2 0x40150
57305 
57306 #define S_T6_RANK    0
57307 #define M_T6_RANK    0xfU
57308 #define V_T6_RANK(x) ((x) << S_T6_RANK)
57309 #define G_T6_RANK(x) (((x) >> S_T6_RANK) & M_T6_RANK)
57310 
57311 #define A_MC_LMC_CMD2 0x40154
57312 #define A_MC_LMC_INITSEQ3 0x40158
57313 
57314 #define S_T6_RANK    0
57315 #define M_T6_RANK    0xfU
57316 #define V_T6_RANK(x) ((x) << S_T6_RANK)
57317 #define G_T6_RANK(x) (((x) >> S_T6_RANK) & M_T6_RANK)
57318 
57319 #define A_MC_LMC_CMD3 0x4015c
57320 #define A_MC_LMC_INITSEQ4 0x40160
57321 
57322 #define S_T6_RANK    0
57323 #define M_T6_RANK    0xfU
57324 #define V_T6_RANK(x) ((x) << S_T6_RANK)
57325 #define G_T6_RANK(x) (((x) >> S_T6_RANK) & M_T6_RANK)
57326 
57327 #define A_MC_LMC_CMD4 0x40164
57328 #define A_MC_LMC_INITSEQ5 0x40168
57329 
57330 #define S_T6_RANK    0
57331 #define M_T6_RANK    0xfU
57332 #define V_T6_RANK(x) ((x) << S_T6_RANK)
57333 #define G_T6_RANK(x) (((x) >> S_T6_RANK) & M_T6_RANK)
57334 
57335 #define A_MC_LMC_CMD5 0x4016c
57336 #define A_MC_LMC_INITSEQ6 0x40170
57337 
57338 #define S_T6_RANK    0
57339 #define M_T6_RANK    0xfU
57340 #define V_T6_RANK(x) ((x) << S_T6_RANK)
57341 #define G_T6_RANK(x) (((x) >> S_T6_RANK) & M_T6_RANK)
57342 
57343 #define A_MC_LMC_CMD6 0x40174
57344 #define A_MC_LMC_INITSEQ7 0x40178
57345 
57346 #define S_T6_RANK    0
57347 #define M_T6_RANK    0xfU
57348 #define V_T6_RANK(x) ((x) << S_T6_RANK)
57349 #define G_T6_RANK(x) (((x) >> S_T6_RANK) & M_T6_RANK)
57350 
57351 #define A_MC_LMC_CMD7 0x4017c
57352 #define A_MC_UPCTL_ECCCFG 0x40180
57353 #define A_MC_LMC_INITSEQ8 0x40180
57354 
57355 #define S_T6_RANK    0
57356 #define M_T6_RANK    0xfU
57357 #define V_T6_RANK(x) ((x) << S_T6_RANK)
57358 #define G_T6_RANK(x) (((x) >> S_T6_RANK) & M_T6_RANK)
57359 
57360 #define A_MC_UPCTL_ECCTST 0x40184
57361 
57362 #define S_ECC_TEST_MASK0    0
57363 #define M_ECC_TEST_MASK0    0x7fU
57364 #define V_ECC_TEST_MASK0(x) ((x) << S_ECC_TEST_MASK0)
57365 #define G_ECC_TEST_MASK0(x) (((x) >> S_ECC_TEST_MASK0) & M_ECC_TEST_MASK0)
57366 
57367 #define A_MC_LMC_CMD8 0x40184
57368 #define A_MC_UPCTL_ECCCLR 0x40188
57369 #define A_MC_LMC_INITSEQ9 0x40188
57370 
57371 #define S_T6_RANK    0
57372 #define M_T6_RANK    0xfU
57373 #define V_T6_RANK(x) ((x) << S_T6_RANK)
57374 #define G_T6_RANK(x) (((x) >> S_T6_RANK) & M_T6_RANK)
57375 
57376 #define A_MC_UPCTL_ECCLOG 0x4018c
57377 #define A_MC_LMC_CMD9 0x4018c
57378 #define A_MC_LMC_INITSEQ10 0x40190
57379 
57380 #define S_T6_RANK    0
57381 #define M_T6_RANK    0xfU
57382 #define V_T6_RANK(x) ((x) << S_T6_RANK)
57383 #define G_T6_RANK(x) (((x) >> S_T6_RANK) & M_T6_RANK)
57384 
57385 #define A_MC_LMC_CMD10 0x40194
57386 #define A_MC_LMC_INITSEQ11 0x40198
57387 
57388 #define S_T6_RANK    0
57389 #define M_T6_RANK    0xfU
57390 #define V_T6_RANK(x) ((x) << S_T6_RANK)
57391 #define G_T6_RANK(x) (((x) >> S_T6_RANK) & M_T6_RANK)
57392 
57393 #define A_MC_LMC_CMD11 0x4019c
57394 #define A_MC_LMC_INITSEQ12 0x401a0
57395 
57396 #define S_T6_RANK    0
57397 #define M_T6_RANK    0xfU
57398 #define V_T6_RANK(x) ((x) << S_T6_RANK)
57399 #define G_T6_RANK(x) (((x) >> S_T6_RANK) & M_T6_RANK)
57400 
57401 #define A_MC_LMC_CMD12 0x401a4
57402 #define A_MC_LMC_INITSEQ13 0x401a8
57403 
57404 #define S_T6_RANK    0
57405 #define M_T6_RANK    0xfU
57406 #define V_T6_RANK(x) ((x) << S_T6_RANK)
57407 #define G_T6_RANK(x) (((x) >> S_T6_RANK) & M_T6_RANK)
57408 
57409 #define A_MC_LMC_CMD13 0x401ac
57410 #define A_MC_LMC_INITSEQ14 0x401b0
57411 
57412 #define S_T6_RANK    0
57413 #define M_T6_RANK    0xfU
57414 #define V_T6_RANK(x) ((x) << S_T6_RANK)
57415 #define G_T6_RANK(x) (((x) >> S_T6_RANK) & M_T6_RANK)
57416 
57417 #define A_MC_LMC_CMD14 0x401b4
57418 #define A_MC_LMC_INITSEQ15 0x401b8
57419 
57420 #define S_T6_RANK    0
57421 #define M_T6_RANK    0xfU
57422 #define V_T6_RANK(x) ((x) << S_T6_RANK)
57423 #define G_T6_RANK(x) (((x) >> S_T6_RANK) & M_T6_RANK)
57424 
57425 #define A_MC_LMC_CMD15 0x401bc
57426 #define A_MC_UPCTL_DTUWACTL 0x40200
57427 
57428 #define S_DTU_WR_ROW0    13
57429 #define M_DTU_WR_ROW0    0xffffU
57430 #define V_DTU_WR_ROW0(x) ((x) << S_DTU_WR_ROW0)
57431 #define G_DTU_WR_ROW0(x) (((x) >> S_DTU_WR_ROW0) & M_DTU_WR_ROW0)
57432 
57433 #define A_MC_LMC_SDTR0 0x40200
57434 
57435 #define S_REFI    16
57436 #define M_REFI    0xffffU
57437 #define V_REFI(x) ((x) << S_REFI)
57438 #define G_REFI(x) (((x) >> S_REFI) & M_REFI)
57439 
57440 #define S_T_RFC_XPR    0
57441 #define M_T_RFC_XPR    0xfffU
57442 #define V_T_RFC_XPR(x) ((x) << S_T_RFC_XPR)
57443 #define G_T_RFC_XPR(x) (((x) >> S_T_RFC_XPR) & M_T_RFC_XPR)
57444 
57445 #define A_MC_UPCTL_DTURACTL 0x40204
57446 
57447 #define S_DTU_RD_ROW0    13
57448 #define M_DTU_RD_ROW0    0xffffU
57449 #define V_DTU_RD_ROW0(x) ((x) << S_DTU_RD_ROW0)
57450 #define G_DTU_RD_ROW0(x) (((x) >> S_DTU_RD_ROW0) & M_DTU_RD_ROW0)
57451 
57452 #define A_MC_LMC_SDTR1 0x40204
57453 
57454 #define S_T_LEADOFF    31
57455 #define V_T_LEADOFF(x) ((x) << S_T_LEADOFF)
57456 #define F_T_LEADOFF    V_T_LEADOFF(1U)
57457 
57458 #define S_ODT_DELAY    30
57459 #define V_ODT_DELAY(x) ((x) << S_ODT_DELAY)
57460 #define F_ODT_DELAY    V_ODT_DELAY(1U)
57461 
57462 #define S_ODT_WIDTH    29
57463 #define V_ODT_WIDTH(x) ((x) << S_ODT_WIDTH)
57464 #define F_ODT_WIDTH    V_ODT_WIDTH(1U)
57465 
57466 #define S_T_WTRO    24
57467 #define M_T_WTRO    0xfU
57468 #define V_T_WTRO(x) ((x) << S_T_WTRO)
57469 #define G_T_WTRO(x) (((x) >> S_T_WTRO) & M_T_WTRO)
57470 
57471 #define S_T_RTWO    16
57472 #define M_T_RTWO    0xfU
57473 #define V_T_RTWO(x) ((x) << S_T_RTWO)
57474 #define G_T_RTWO(x) (((x) >> S_T_RTWO) & M_T_RTWO)
57475 
57476 #define S_T_RTW_ADJ    12
57477 #define M_T_RTW_ADJ    0xfU
57478 #define V_T_RTW_ADJ(x) ((x) << S_T_RTW_ADJ)
57479 #define G_T_RTW_ADJ(x) (((x) >> S_T_RTW_ADJ) & M_T_RTW_ADJ)
57480 
57481 #define S_T_WTWO    8
57482 #define M_T_WTWO    0xfU
57483 #define V_T_WTWO(x) ((x) << S_T_WTWO)
57484 #define G_T_WTWO(x) (((x) >> S_T_WTWO) & M_T_WTWO)
57485 
57486 #define S_T_RTRO    0
57487 #define M_T_RTRO    0xfU
57488 #define V_T_RTRO(x) ((x) << S_T_RTRO)
57489 #define G_T_RTRO(x) (((x) >> S_T_RTRO) & M_T_RTRO)
57490 
57491 #define A_MC_UPCTL_DTUCFG 0x40208
57492 #define A_MC_LMC_SDTR2 0x40208
57493 
57494 #define S_T6_T_CWL    28
57495 #define M_T6_T_CWL    0xfU
57496 #define V_T6_T_CWL(x) ((x) << S_T6_T_CWL)
57497 #define G_T6_T_CWL(x) (((x) >> S_T6_T_CWL) & M_T6_T_CWL)
57498 
57499 #define S_T_RCD0    24
57500 #define M_T_RCD0    0xfU
57501 #define V_T_RCD0(x) ((x) << S_T_RCD0)
57502 #define G_T_RCD0(x) (((x) >> S_T_RCD0) & M_T_RCD0)
57503 
57504 #define S_T_PL    20
57505 #define M_T_PL    0xfU
57506 #define V_T_PL(x) ((x) << S_T_PL)
57507 #define G_T_PL(x) (((x) >> S_T_PL) & M_T_PL)
57508 
57509 #define S_T_RP0    16
57510 #define M_T_RP0    0xfU
57511 #define V_T_RP0(x) ((x) << S_T_RP0)
57512 #define G_T_RP0(x) (((x) >> S_T_RP0) & M_T_RP0)
57513 
57514 #define S_T_RP1    15
57515 #define V_T_RP1(x) ((x) << S_T_RP1)
57516 #define F_T_RP1    V_T_RP1(1U)
57517 
57518 #define S_T_RCD1    14
57519 #define V_T_RCD1(x) ((x) << S_T_RCD1)
57520 #define F_T_RCD1    V_T_RCD1(1U)
57521 
57522 #define S_T6_T_RC    8
57523 #define M_T6_T_RC    0x3fU
57524 #define V_T6_T_RC(x) ((x) << S_T6_T_RC)
57525 #define G_T6_T_RC(x) (((x) >> S_T6_T_RC) & M_T6_T_RC)
57526 
57527 #define A_MC_UPCTL_DTUECTL 0x4020c
57528 #define A_MC_LMC_SDTR3 0x4020c
57529 
57530 #define S_T_WTR_S    28
57531 #define M_T_WTR_S    0xfU
57532 #define V_T_WTR_S(x) ((x) << S_T_WTR_S)
57533 #define G_T_WTR_S(x) (((x) >> S_T_WTR_S) & M_T_WTR_S)
57534 
57535 #define S_T6_T_WTR    24
57536 #define M_T6_T_WTR    0xfU
57537 #define V_T6_T_WTR(x) ((x) << S_T6_T_WTR)
57538 #define G_T6_T_WTR(x) (((x) >> S_T6_T_WTR) & M_T6_T_WTR)
57539 
57540 #define S_FAW_ADJ    20
57541 #define M_FAW_ADJ    0x3U
57542 #define V_FAW_ADJ(x) ((x) << S_FAW_ADJ)
57543 #define G_FAW_ADJ(x) (((x) >> S_FAW_ADJ) & M_FAW_ADJ)
57544 
57545 #define S_T6_T_RTP    16
57546 #define M_T6_T_RTP    0xfU
57547 #define V_T6_T_RTP(x) ((x) << S_T6_T_RTP)
57548 #define G_T6_T_RTP(x) (((x) >> S_T6_T_RTP) & M_T6_T_RTP)
57549 
57550 #define S_T_RRD_L    12
57551 #define M_T_RRD_L    0xfU
57552 #define V_T_RRD_L(x) ((x) << S_T_RRD_L)
57553 #define G_T_RRD_L(x) (((x) >> S_T_RRD_L) & M_T_RRD_L)
57554 
57555 #define S_T6_T_RRD    8
57556 #define M_T6_T_RRD    0xfU
57557 #define V_T6_T_RRD(x) ((x) << S_T6_T_RRD)
57558 #define G_T6_T_RRD(x) (((x) >> S_T6_T_RRD) & M_T6_T_RRD)
57559 
57560 #define S_T_XSDLL    0
57561 #define M_T_XSDLL    0xffU
57562 #define V_T_XSDLL(x) ((x) << S_T_XSDLL)
57563 #define G_T_XSDLL(x) (((x) >> S_T_XSDLL) & M_T_XSDLL)
57564 
57565 #define A_MC_UPCTL_DTUWD0 0x40210
57566 #define A_MC_LMC_SDTR4 0x40210
57567 
57568 #define S_T_RDDATA_EN    24
57569 #define M_T_RDDATA_EN    0x7fU
57570 #define V_T_RDDATA_EN(x) ((x) << S_T_RDDATA_EN)
57571 #define G_T_RDDATA_EN(x) (((x) >> S_T_RDDATA_EN) & M_T_RDDATA_EN)
57572 
57573 #define S_T_SYS_RDLAT    16
57574 #define M_T_SYS_RDLAT    0x3fU
57575 #define V_T_SYS_RDLAT(x) ((x) << S_T_SYS_RDLAT)
57576 #define G_T_SYS_RDLAT(x) (((x) >> S_T_SYS_RDLAT) & M_T_SYS_RDLAT)
57577 
57578 #define S_T_CCD_L    12
57579 #define M_T_CCD_L    0xfU
57580 #define V_T_CCD_L(x) ((x) << S_T_CCD_L)
57581 #define G_T_CCD_L(x) (((x) >> S_T_CCD_L) & M_T_CCD_L)
57582 
57583 #define S_T_CCD    8
57584 #define M_T_CCD    0x7U
57585 #define V_T_CCD(x) ((x) << S_T_CCD)
57586 #define G_T_CCD(x) (((x) >> S_T_CCD) & M_T_CCD)
57587 
57588 #define S_T_CPDED    5
57589 #define M_T_CPDED    0x7U
57590 #define V_T_CPDED(x) ((x) << S_T_CPDED)
57591 #define G_T_CPDED(x) (((x) >> S_T_CPDED) & M_T_CPDED)
57592 
57593 #define S_T6_T_MOD    0
57594 #define M_T6_T_MOD    0x1fU
57595 #define V_T6_T_MOD(x) ((x) << S_T6_T_MOD)
57596 #define G_T6_T_MOD(x) (((x) >> S_T6_T_MOD) & M_T6_T_MOD)
57597 
57598 #define A_MC_UPCTL_DTUWD1 0x40214
57599 #define A_MC_LMC_SDTR5 0x40214
57600 
57601 #define S_T_PHY_WRDATA    24
57602 #define M_T_PHY_WRDATA    0x7U
57603 #define V_T_PHY_WRDATA(x) ((x) << S_T_PHY_WRDATA)
57604 #define G_T_PHY_WRDATA(x) (((x) >> S_T_PHY_WRDATA) & M_T_PHY_WRDATA)
57605 
57606 #define S_T_PHY_WRLAT    16
57607 #define M_T_PHY_WRLAT    0x1fU
57608 #define V_T_PHY_WRLAT(x) ((x) << S_T_PHY_WRLAT)
57609 #define G_T_PHY_WRLAT(x) (((x) >> S_T_PHY_WRLAT) & M_T_PHY_WRLAT)
57610 
57611 #define A_MC_UPCTL_DTUWD2 0x40218
57612 #define A_MC_UPCTL_DTUWD3 0x4021c
57613 #define A_MC_UPCTL_DTUWDM 0x40220
57614 #define A_MC_UPCTL_DTURD0 0x40224
57615 #define A_MC_UPCTL_DTURD1 0x40228
57616 #define A_MC_LMC_DBG0 0x40228
57617 
57618 #define S_T_SYS_RDLAT_DBG    16
57619 #define M_T_SYS_RDLAT_DBG    0x1fU
57620 #define V_T_SYS_RDLAT_DBG(x) ((x) << S_T_SYS_RDLAT_DBG)
57621 #define G_T_SYS_RDLAT_DBG(x) (((x) >> S_T_SYS_RDLAT_DBG) & M_T_SYS_RDLAT_DBG)
57622 
57623 #define A_MC_UPCTL_DTURD2 0x4022c
57624 #define A_MC_UPCTL_DTURD3 0x40230
57625 #define A_MC_UPCTL_DTULFSRWD 0x40234
57626 #define A_MC_UPCTL_DTULFSRRD 0x40238
57627 #define A_MC_UPCTL_DTUEAF 0x4023c
57628 
57629 #define S_EA_ROW0    13
57630 #define M_EA_ROW0    0xffffU
57631 #define V_EA_ROW0(x) ((x) << S_EA_ROW0)
57632 #define G_EA_ROW0(x) (((x) >> S_EA_ROW0) & M_EA_ROW0)
57633 
57634 #define A_MC_UPCTL_DFITCTRLDELAY 0x40240
57635 
57636 #define S_TCTRL_DELAY    0
57637 #define M_TCTRL_DELAY    0xfU
57638 #define V_TCTRL_DELAY(x) ((x) << S_TCTRL_DELAY)
57639 #define G_TCTRL_DELAY(x) (((x) >> S_TCTRL_DELAY) & M_TCTRL_DELAY)
57640 
57641 #define A_MC_LMC_SMR0 0x40240
57642 
57643 #define S_SMR0_RFU0    13
57644 #define M_SMR0_RFU0    0x7U
57645 #define V_SMR0_RFU0(x) ((x) << S_SMR0_RFU0)
57646 #define G_SMR0_RFU0(x) (((x) >> S_SMR0_RFU0) & M_SMR0_RFU0)
57647 
57648 #define S_PPD    12
57649 #define V_PPD(x) ((x) << S_PPD)
57650 #define F_PPD    V_PPD(1U)
57651 
57652 #define S_WR_RTP    9
57653 #define M_WR_RTP    0x7U
57654 #define V_WR_RTP(x) ((x) << S_WR_RTP)
57655 #define G_WR_RTP(x) (((x) >> S_WR_RTP) & M_WR_RTP)
57656 
57657 #define S_SMR0_DLL    8
57658 #define V_SMR0_DLL(x) ((x) << S_SMR0_DLL)
57659 #define F_SMR0_DLL    V_SMR0_DLL(1U)
57660 
57661 #define S_TM    7
57662 #define V_TM(x) ((x) << S_TM)
57663 #define F_TM    V_TM(1U)
57664 
57665 #define S_CL31    4
57666 #define M_CL31    0x7U
57667 #define V_CL31(x) ((x) << S_CL31)
57668 #define G_CL31(x) (((x) >> S_CL31) & M_CL31)
57669 
57670 #define S_RBT    3
57671 #define V_RBT(x) ((x) << S_RBT)
57672 #define F_RBT    V_RBT(1U)
57673 
57674 #define S_CL0    2
57675 #define V_CL0(x) ((x) << S_CL0)
57676 #define F_CL0    V_CL0(1U)
57677 
57678 #define S_BL    0
57679 #define M_BL    0x3U
57680 #define V_BL(x) ((x) << S_BL)
57681 #define G_BL(x) (((x) >> S_BL) & M_BL)
57682 
57683 #define A_MC_UPCTL_DFIODTCFG 0x40244
57684 
57685 #define S_RANK3_ODT_WRITE_NSEL    26
57686 #define V_RANK3_ODT_WRITE_NSEL(x) ((x) << S_RANK3_ODT_WRITE_NSEL)
57687 #define F_RANK3_ODT_WRITE_NSEL    V_RANK3_ODT_WRITE_NSEL(1U)
57688 
57689 #define A_MC_LMC_SMR1 0x40244
57690 
57691 #define S_QOFF    12
57692 #define V_QOFF(x) ((x) << S_QOFF)
57693 #define F_QOFF    V_QOFF(1U)
57694 
57695 #define S_TDQS    11
57696 #define V_TDQS(x) ((x) << S_TDQS)
57697 #define F_TDQS    V_TDQS(1U)
57698 
57699 #define S_SMR1_RFU0    10
57700 #define V_SMR1_RFU0(x) ((x) << S_SMR1_RFU0)
57701 #define F_SMR1_RFU0    V_SMR1_RFU0(1U)
57702 
57703 #define S_RTT_NOM0    9
57704 #define V_RTT_NOM0(x) ((x) << S_RTT_NOM0)
57705 #define F_RTT_NOM0    V_RTT_NOM0(1U)
57706 
57707 #define S_SMR1_RFU1    8
57708 #define V_SMR1_RFU1(x) ((x) << S_SMR1_RFU1)
57709 #define F_SMR1_RFU1    V_SMR1_RFU1(1U)
57710 
57711 #define S_WR_LEVEL    7
57712 #define V_WR_LEVEL(x) ((x) << S_WR_LEVEL)
57713 #define F_WR_LEVEL    V_WR_LEVEL(1U)
57714 
57715 #define S_RTT_NOM1    6
57716 #define V_RTT_NOM1(x) ((x) << S_RTT_NOM1)
57717 #define F_RTT_NOM1    V_RTT_NOM1(1U)
57718 
57719 #define S_DIC0    5
57720 #define V_DIC0(x) ((x) << S_DIC0)
57721 #define F_DIC0    V_DIC0(1U)
57722 
57723 #define S_AL    3
57724 #define M_AL    0x3U
57725 #define V_AL(x) ((x) << S_AL)
57726 #define G_AL(x) (((x) >> S_AL) & M_AL)
57727 
57728 #define S_RTT_NOM2    2
57729 #define V_RTT_NOM2(x) ((x) << S_RTT_NOM2)
57730 #define F_RTT_NOM2    V_RTT_NOM2(1U)
57731 
57732 #define S_DIC1    1
57733 #define V_DIC1(x) ((x) << S_DIC1)
57734 #define F_DIC1    V_DIC1(1U)
57735 
57736 #define S_SMR1_DLL    0
57737 #define V_SMR1_DLL(x) ((x) << S_SMR1_DLL)
57738 #define F_SMR1_DLL    V_SMR1_DLL(1U)
57739 
57740 #define A_MC_UPCTL_DFIODTCFG1 0x40248
57741 
57742 #define S_ODT_LEN_B8_R    24
57743 #define M_ODT_LEN_B8_R    0x7U
57744 #define V_ODT_LEN_B8_R(x) ((x) << S_ODT_LEN_B8_R)
57745 #define G_ODT_LEN_B8_R(x) (((x) >> S_ODT_LEN_B8_R) & M_ODT_LEN_B8_R)
57746 
57747 #define S_ODT_LEN_BL8_W    16
57748 #define M_ODT_LEN_BL8_W    0x7U
57749 #define V_ODT_LEN_BL8_W(x) ((x) << S_ODT_LEN_BL8_W)
57750 #define G_ODT_LEN_BL8_W(x) (((x) >> S_ODT_LEN_BL8_W) & M_ODT_LEN_BL8_W)
57751 
57752 #define S_ODT_LAT_R    8
57753 #define M_ODT_LAT_R    0x1fU
57754 #define V_ODT_LAT_R(x) ((x) << S_ODT_LAT_R)
57755 #define G_ODT_LAT_R(x) (((x) >> S_ODT_LAT_R) & M_ODT_LAT_R)
57756 
57757 #define S_ODT_LAT_W    0
57758 #define M_ODT_LAT_W    0x1fU
57759 #define V_ODT_LAT_W(x) ((x) << S_ODT_LAT_W)
57760 #define G_ODT_LAT_W(x) (((x) >> S_ODT_LAT_W) & M_ODT_LAT_W)
57761 
57762 #define A_MC_LMC_SMR2 0x40248
57763 
57764 #define S_WR_CRC    12
57765 #define V_WR_CRC(x) ((x) << S_WR_CRC)
57766 #define F_WR_CRC    V_WR_CRC(1U)
57767 
57768 #define S_RD_CRC    11
57769 #define V_RD_CRC(x) ((x) << S_RD_CRC)
57770 #define F_RD_CRC    V_RD_CRC(1U)
57771 
57772 #define S_RTT_WR    9
57773 #define M_RTT_WR    0x3U
57774 #define V_RTT_WR(x) ((x) << S_RTT_WR)
57775 #define G_RTT_WR(x) (((x) >> S_RTT_WR) & M_RTT_WR)
57776 
57777 #define S_SMR2_RFU0    8
57778 #define V_SMR2_RFU0(x) ((x) << S_SMR2_RFU0)
57779 #define F_SMR2_RFU0    V_SMR2_RFU0(1U)
57780 
57781 #define S_SRT_ASR1    7
57782 #define V_SRT_ASR1(x) ((x) << S_SRT_ASR1)
57783 #define F_SRT_ASR1    V_SRT_ASR1(1U)
57784 
57785 #define S_ASR0    6
57786 #define V_ASR0(x) ((x) << S_ASR0)
57787 #define F_ASR0    V_ASR0(1U)
57788 
57789 #define S_CWL    3
57790 #define M_CWL    0x7U
57791 #define V_CWL(x) ((x) << S_CWL)
57792 #define G_CWL(x) (((x) >> S_CWL) & M_CWL)
57793 
57794 #define S_PASR    0
57795 #define M_PASR    0x7U
57796 #define V_PASR(x) ((x) << S_PASR)
57797 #define G_PASR(x) (((x) >> S_PASR) & M_PASR)
57798 
57799 #define A_MC_UPCTL_DFIODTRANKMAP 0x4024c
57800 
57801 #define S_ODT_RANK_MAP3    12
57802 #define M_ODT_RANK_MAP3    0xfU
57803 #define V_ODT_RANK_MAP3(x) ((x) << S_ODT_RANK_MAP3)
57804 #define G_ODT_RANK_MAP3(x) (((x) >> S_ODT_RANK_MAP3) & M_ODT_RANK_MAP3)
57805 
57806 #define S_ODT_RANK_MAP2    8
57807 #define M_ODT_RANK_MAP2    0xfU
57808 #define V_ODT_RANK_MAP2(x) ((x) << S_ODT_RANK_MAP2)
57809 #define G_ODT_RANK_MAP2(x) (((x) >> S_ODT_RANK_MAP2) & M_ODT_RANK_MAP2)
57810 
57811 #define S_ODT_RANK_MAP1    4
57812 #define M_ODT_RANK_MAP1    0xfU
57813 #define V_ODT_RANK_MAP1(x) ((x) << S_ODT_RANK_MAP1)
57814 #define G_ODT_RANK_MAP1(x) (((x) >> S_ODT_RANK_MAP1) & M_ODT_RANK_MAP1)
57815 
57816 #define S_ODT_RANK_MAP0    0
57817 #define M_ODT_RANK_MAP0    0xfU
57818 #define V_ODT_RANK_MAP0(x) ((x) << S_ODT_RANK_MAP0)
57819 #define G_ODT_RANK_MAP0(x) (((x) >> S_ODT_RANK_MAP0) & M_ODT_RANK_MAP0)
57820 
57821 #define A_MC_LMC_SMR3 0x4024c
57822 
57823 #define S_MPR_RD_FMT    11
57824 #define M_MPR_RD_FMT    0x3U
57825 #define V_MPR_RD_FMT(x) ((x) << S_MPR_RD_FMT)
57826 #define G_MPR_RD_FMT(x) (((x) >> S_MPR_RD_FMT) & M_MPR_RD_FMT)
57827 
57828 #define S_SMR3_RFU0    9
57829 #define M_SMR3_RFU0    0x3U
57830 #define V_SMR3_RFU0(x) ((x) << S_SMR3_RFU0)
57831 #define G_SMR3_RFU0(x) (((x) >> S_SMR3_RFU0) & M_SMR3_RFU0)
57832 
57833 #define S_FGR_MODE    6
57834 #define M_FGR_MODE    0x7U
57835 #define V_FGR_MODE(x) ((x) << S_FGR_MODE)
57836 #define G_FGR_MODE(x) (((x) >> S_FGR_MODE) & M_FGR_MODE)
57837 
57838 #define S_MRS_RDO    5
57839 #define V_MRS_RDO(x) ((x) << S_MRS_RDO)
57840 #define F_MRS_RDO    V_MRS_RDO(1U)
57841 
57842 #define S_DRAM_ADR    4
57843 #define V_DRAM_ADR(x) ((x) << S_DRAM_ADR)
57844 #define F_DRAM_ADR    V_DRAM_ADR(1U)
57845 
57846 #define S_GD_MODE    3
57847 #define V_GD_MODE(x) ((x) << S_GD_MODE)
57848 #define F_GD_MODE    V_GD_MODE(1U)
57849 
57850 #define S_MPR    2
57851 #define V_MPR(x) ((x) << S_MPR)
57852 #define F_MPR    V_MPR(1U)
57853 
57854 #define S_MPR_SEL    0
57855 #define M_MPR_SEL    0x3U
57856 #define V_MPR_SEL(x) ((x) << S_MPR_SEL)
57857 #define G_MPR_SEL(x) (((x) >> S_MPR_SEL) & M_MPR_SEL)
57858 
57859 #define A_MC_UPCTL_DFITPHYWRDATA 0x40250
57860 
57861 #define S_TPHY_WRDATA    0
57862 #define M_TPHY_WRDATA    0x1fU
57863 #define V_TPHY_WRDATA(x) ((x) << S_TPHY_WRDATA)
57864 #define G_TPHY_WRDATA(x) (((x) >> S_TPHY_WRDATA) & M_TPHY_WRDATA)
57865 
57866 #define A_MC_LMC_SMR4 0x40250
57867 
57868 #define S_WR_PRE    12
57869 #define V_WR_PRE(x) ((x) << S_WR_PRE)
57870 #define F_WR_PRE    V_WR_PRE(1U)
57871 
57872 #define S_RD_PRE    11
57873 #define V_RD_PRE(x) ((x) << S_RD_PRE)
57874 #define F_RD_PRE    V_RD_PRE(1U)
57875 
57876 #define S_RPT_MODE    10
57877 #define V_RPT_MODE(x) ((x) << S_RPT_MODE)
57878 #define F_RPT_MODE    V_RPT_MODE(1U)
57879 
57880 #define S_FESR_MODE    9
57881 #define V_FESR_MODE(x) ((x) << S_FESR_MODE)
57882 #define F_FESR_MODE    V_FESR_MODE(1U)
57883 
57884 #define S_CS_LAT_MODE    6
57885 #define M_CS_LAT_MODE    0x7U
57886 #define V_CS_LAT_MODE(x) ((x) << S_CS_LAT_MODE)
57887 #define G_CS_LAT_MODE(x) (((x) >> S_CS_LAT_MODE) & M_CS_LAT_MODE)
57888 
57889 #define S_ALERT_STAT    5
57890 #define V_ALERT_STAT(x) ((x) << S_ALERT_STAT)
57891 #define F_ALERT_STAT    V_ALERT_STAT(1U)
57892 
57893 #define S_IVM_MODE    4
57894 #define V_IVM_MODE(x) ((x) << S_IVM_MODE)
57895 #define F_IVM_MODE    V_IVM_MODE(1U)
57896 
57897 #define S_TCR_MODE    3
57898 #define V_TCR_MODE(x) ((x) << S_TCR_MODE)
57899 #define F_TCR_MODE    V_TCR_MODE(1U)
57900 
57901 #define S_TCR_RANGE    2
57902 #define V_TCR_RANGE(x) ((x) << S_TCR_RANGE)
57903 #define F_TCR_RANGE    V_TCR_RANGE(1U)
57904 
57905 #define S_MPD_MODE    1
57906 #define V_MPD_MODE(x) ((x) << S_MPD_MODE)
57907 #define F_MPD_MODE    V_MPD_MODE(1U)
57908 
57909 #define S_SMR4_RFU    0
57910 #define V_SMR4_RFU(x) ((x) << S_SMR4_RFU)
57911 #define F_SMR4_RFU    V_SMR4_RFU(1U)
57912 
57913 #define A_MC_UPCTL_DFITPHYWRLAT 0x40254
57914 
57915 #define S_TPHY_WRLAT    0
57916 #define M_TPHY_WRLAT    0x1fU
57917 #define V_TPHY_WRLAT(x) ((x) << S_TPHY_WRLAT)
57918 #define G_TPHY_WRLAT(x) (((x) >> S_TPHY_WRLAT) & M_TPHY_WRLAT)
57919 
57920 #define A_MC_LMC_SMR5 0x40254
57921 
57922 #define S_RD_DBI    11
57923 #define V_RD_DBI(x) ((x) << S_RD_DBI)
57924 #define F_RD_DBI    V_RD_DBI(1U)
57925 
57926 #define S_WR_DBI    10
57927 #define V_WR_DBI(x) ((x) << S_WR_DBI)
57928 #define F_WR_DBI    V_WR_DBI(1U)
57929 
57930 #define S_DM_MODE    9
57931 #define V_DM_MODE(x) ((x) << S_DM_MODE)
57932 #define F_DM_MODE    V_DM_MODE(1U)
57933 
57934 #define S_RTT_PARK    6
57935 #define M_RTT_PARK    0x7U
57936 #define V_RTT_PARK(x) ((x) << S_RTT_PARK)
57937 #define G_RTT_PARK(x) (((x) >> S_RTT_PARK) & M_RTT_PARK)
57938 
57939 #define S_SMR5_RFU    5
57940 #define V_SMR5_RFU(x) ((x) << S_SMR5_RFU)
57941 #define F_SMR5_RFU    V_SMR5_RFU(1U)
57942 
57943 #define S_PAR_ERR_STAT    4
57944 #define V_PAR_ERR_STAT(x) ((x) << S_PAR_ERR_STAT)
57945 #define F_PAR_ERR_STAT    V_PAR_ERR_STAT(1U)
57946 
57947 #define S_CRC_CLEAR    3
57948 #define V_CRC_CLEAR(x) ((x) << S_CRC_CLEAR)
57949 #define F_CRC_CLEAR    V_CRC_CLEAR(1U)
57950 
57951 #define S_PAR_LAT_MODE    0
57952 #define M_PAR_LAT_MODE    0x7U
57953 #define V_PAR_LAT_MODE(x) ((x) << S_PAR_LAT_MODE)
57954 #define G_PAR_LAT_MODE(x) (((x) >> S_PAR_LAT_MODE) & M_PAR_LAT_MODE)
57955 
57956 #define A_MC_LMC_SMR6 0x40258
57957 
57958 #define S_TCCD_L    10
57959 #define M_TCCD_L    0x7U
57960 #define V_TCCD_L(x) ((x) << S_TCCD_L)
57961 #define G_TCCD_L(x) (((x) >> S_TCCD_L) & M_TCCD_L)
57962 
57963 #define S_SRM6_RFU    7
57964 #define M_SRM6_RFU    0x7U
57965 #define V_SRM6_RFU(x) ((x) << S_SRM6_RFU)
57966 #define G_SRM6_RFU(x) (((x) >> S_SRM6_RFU) & M_SRM6_RFU)
57967 
57968 #define S_VREF_DQ_RANGE    6
57969 #define V_VREF_DQ_RANGE(x) ((x) << S_VREF_DQ_RANGE)
57970 #define F_VREF_DQ_RANGE    V_VREF_DQ_RANGE(1U)
57971 
57972 #define S_VREF_DQ_VALUE    0
57973 #define M_VREF_DQ_VALUE    0x3fU
57974 #define V_VREF_DQ_VALUE(x) ((x) << S_VREF_DQ_VALUE)
57975 #define G_VREF_DQ_VALUE(x) (((x) >> S_VREF_DQ_VALUE) & M_VREF_DQ_VALUE)
57976 
57977 #define A_MC_UPCTL_DFITRDDATAEN 0x40260
57978 
57979 #define S_TRDDATA_EN    0
57980 #define M_TRDDATA_EN    0x1fU
57981 #define V_TRDDATA_EN(x) ((x) << S_TRDDATA_EN)
57982 #define G_TRDDATA_EN(x) (((x) >> S_TRDDATA_EN) & M_TRDDATA_EN)
57983 
57984 #define A_MC_UPCTL_DFITPHYRDLAT 0x40264
57985 
57986 #define S_TPHY_RDLAT    0
57987 #define M_TPHY_RDLAT    0x3fU
57988 #define V_TPHY_RDLAT(x) ((x) << S_TPHY_RDLAT)
57989 #define G_TPHY_RDLAT(x) (((x) >> S_TPHY_RDLAT) & M_TPHY_RDLAT)
57990 
57991 #define A_MC_UPCTL_DFITPHYUPDTYPE0 0x40270
57992 
57993 #define S_TPHYUPD_TYPE0    0
57994 #define M_TPHYUPD_TYPE0    0xfffU
57995 #define V_TPHYUPD_TYPE0(x) ((x) << S_TPHYUPD_TYPE0)
57996 #define G_TPHYUPD_TYPE0(x) (((x) >> S_TPHYUPD_TYPE0) & M_TPHYUPD_TYPE0)
57997 
57998 #define A_MC_UPCTL_DFITPHYUPDTYPE1 0x40274
57999 
58000 #define S_TPHYUPD_TYPE1    0
58001 #define M_TPHYUPD_TYPE1    0xfffU
58002 #define V_TPHYUPD_TYPE1(x) ((x) << S_TPHYUPD_TYPE1)
58003 #define G_TPHYUPD_TYPE1(x) (((x) >> S_TPHYUPD_TYPE1) & M_TPHYUPD_TYPE1)
58004 
58005 #define A_MC_UPCTL_DFITPHYUPDTYPE2 0x40278
58006 
58007 #define S_TPHYUPD_TYPE2    0
58008 #define M_TPHYUPD_TYPE2    0xfffU
58009 #define V_TPHYUPD_TYPE2(x) ((x) << S_TPHYUPD_TYPE2)
58010 #define G_TPHYUPD_TYPE2(x) (((x) >> S_TPHYUPD_TYPE2) & M_TPHYUPD_TYPE2)
58011 
58012 #define A_MC_UPCTL_DFITPHYUPDTYPE3 0x4027c
58013 
58014 #define S_TPHYUPD_TYPE3    0
58015 #define M_TPHYUPD_TYPE3    0xfffU
58016 #define V_TPHYUPD_TYPE3(x) ((x) << S_TPHYUPD_TYPE3)
58017 #define G_TPHYUPD_TYPE3(x) (((x) >> S_TPHYUPD_TYPE3) & M_TPHYUPD_TYPE3)
58018 
58019 #define A_MC_UPCTL_DFITCTRLUPDMIN 0x40280
58020 
58021 #define S_TCTRLUPD_MIN    0
58022 #define M_TCTRLUPD_MIN    0xffffU
58023 #define V_TCTRLUPD_MIN(x) ((x) << S_TCTRLUPD_MIN)
58024 #define G_TCTRLUPD_MIN(x) (((x) >> S_TCTRLUPD_MIN) & M_TCTRLUPD_MIN)
58025 
58026 #define A_MC_LMC_ODTR0 0x40280
58027 
58028 #define S_RK0W    25
58029 #define V_RK0W(x) ((x) << S_RK0W)
58030 #define F_RK0W    V_RK0W(1U)
58031 
58032 #define S_RK0R    24
58033 #define V_RK0R(x) ((x) << S_RK0R)
58034 #define F_RK0R    V_RK0R(1U)
58035 
58036 #define A_MC_UPCTL_DFITCTRLUPDMAX 0x40284
58037 
58038 #define S_TCTRLUPD_MAX    0
58039 #define M_TCTRLUPD_MAX    0xffffU
58040 #define V_TCTRLUPD_MAX(x) ((x) << S_TCTRLUPD_MAX)
58041 #define G_TCTRLUPD_MAX(x) (((x) >> S_TCTRLUPD_MAX) & M_TCTRLUPD_MAX)
58042 
58043 #define A_MC_UPCTL_DFITCTRLUPDDLY 0x40288
58044 
58045 #define S_TCTRLUPD_DLY    0
58046 #define M_TCTRLUPD_DLY    0xfU
58047 #define V_TCTRLUPD_DLY(x) ((x) << S_TCTRLUPD_DLY)
58048 #define G_TCTRLUPD_DLY(x) (((x) >> S_TCTRLUPD_DLY) & M_TCTRLUPD_DLY)
58049 
58050 #define A_MC_UPCTL_DFIUPDCFG 0x40290
58051 
58052 #define S_DFI_PHYUPD_EN    1
58053 #define V_DFI_PHYUPD_EN(x) ((x) << S_DFI_PHYUPD_EN)
58054 #define F_DFI_PHYUPD_EN    V_DFI_PHYUPD_EN(1U)
58055 
58056 #define S_DFI_CTRLUPD_EN    0
58057 #define V_DFI_CTRLUPD_EN(x) ((x) << S_DFI_CTRLUPD_EN)
58058 #define F_DFI_CTRLUPD_EN    V_DFI_CTRLUPD_EN(1U)
58059 
58060 #define A_MC_UPCTL_DFITREFMSKI 0x40294
58061 
58062 #define S_TREFMSKI    0
58063 #define M_TREFMSKI    0xffU
58064 #define V_TREFMSKI(x) ((x) << S_TREFMSKI)
58065 #define G_TREFMSKI(x) (((x) >> S_TREFMSKI) & M_TREFMSKI)
58066 
58067 #define A_MC_UPCTL_DFITCTRLUPDI 0x40298
58068 #define A_MC_UPCTL_DFITRCFG0 0x402ac
58069 
58070 #define S_DFI_WRLVL_RANK_SEL    16
58071 #define M_DFI_WRLVL_RANK_SEL    0xfU
58072 #define V_DFI_WRLVL_RANK_SEL(x) ((x) << S_DFI_WRLVL_RANK_SEL)
58073 #define G_DFI_WRLVL_RANK_SEL(x) (((x) >> S_DFI_WRLVL_RANK_SEL) & M_DFI_WRLVL_RANK_SEL)
58074 
58075 #define S_DFI_RDLVL_EDGE    4
58076 #define M_DFI_RDLVL_EDGE    0x1ffU
58077 #define V_DFI_RDLVL_EDGE(x) ((x) << S_DFI_RDLVL_EDGE)
58078 #define G_DFI_RDLVL_EDGE(x) (((x) >> S_DFI_RDLVL_EDGE) & M_DFI_RDLVL_EDGE)
58079 
58080 #define S_DFI_RDLVL_RANK_SEL    0
58081 #define M_DFI_RDLVL_RANK_SEL    0xfU
58082 #define V_DFI_RDLVL_RANK_SEL(x) ((x) << S_DFI_RDLVL_RANK_SEL)
58083 #define G_DFI_RDLVL_RANK_SEL(x) (((x) >> S_DFI_RDLVL_RANK_SEL) & M_DFI_RDLVL_RANK_SEL)
58084 
58085 #define A_MC_UPCTL_DFITRSTAT0 0x402b0
58086 
58087 #define S_DFI_WRLVL_MODE    16
58088 #define M_DFI_WRLVL_MODE    0x3U
58089 #define V_DFI_WRLVL_MODE(x) ((x) << S_DFI_WRLVL_MODE)
58090 #define G_DFI_WRLVL_MODE(x) (((x) >> S_DFI_WRLVL_MODE) & M_DFI_WRLVL_MODE)
58091 
58092 #define S_DFI_RDLVL_GATE_MODE    8
58093 #define M_DFI_RDLVL_GATE_MODE    0x3U
58094 #define V_DFI_RDLVL_GATE_MODE(x) ((x) << S_DFI_RDLVL_GATE_MODE)
58095 #define G_DFI_RDLVL_GATE_MODE(x) (((x) >> S_DFI_RDLVL_GATE_MODE) & M_DFI_RDLVL_GATE_MODE)
58096 
58097 #define S_DFI_RDLVL_MODE    0
58098 #define M_DFI_RDLVL_MODE    0x3U
58099 #define V_DFI_RDLVL_MODE(x) ((x) << S_DFI_RDLVL_MODE)
58100 #define G_DFI_RDLVL_MODE(x) (((x) >> S_DFI_RDLVL_MODE) & M_DFI_RDLVL_MODE)
58101 
58102 #define A_MC_UPCTL_DFITRWRLVLEN 0x402b4
58103 
58104 #define S_DFI_WRLVL_EN    0
58105 #define M_DFI_WRLVL_EN    0x1ffU
58106 #define V_DFI_WRLVL_EN(x) ((x) << S_DFI_WRLVL_EN)
58107 #define G_DFI_WRLVL_EN(x) (((x) >> S_DFI_WRLVL_EN) & M_DFI_WRLVL_EN)
58108 
58109 #define A_MC_UPCTL_DFITRRDLVLEN 0x402b8
58110 
58111 #define S_DFI_RDLVL_EN    0
58112 #define M_DFI_RDLVL_EN    0x1ffU
58113 #define V_DFI_RDLVL_EN(x) ((x) << S_DFI_RDLVL_EN)
58114 #define G_DFI_RDLVL_EN(x) (((x) >> S_DFI_RDLVL_EN) & M_DFI_RDLVL_EN)
58115 
58116 #define A_MC_UPCTL_DFITRRDLVLGATEEN 0x402bc
58117 
58118 #define S_DFI_RDLVL_GATE_EN    0
58119 #define M_DFI_RDLVL_GATE_EN    0x1ffU
58120 #define V_DFI_RDLVL_GATE_EN(x) ((x) << S_DFI_RDLVL_GATE_EN)
58121 #define G_DFI_RDLVL_GATE_EN(x) (((x) >> S_DFI_RDLVL_GATE_EN) & M_DFI_RDLVL_GATE_EN)
58122 
58123 #define A_MC_UPCTL_DFISTSTAT0 0x402c0
58124 
58125 #define S_DFI_DATA_BYTE_DISABLE    16
58126 #define M_DFI_DATA_BYTE_DISABLE    0x1ffU
58127 #define V_DFI_DATA_BYTE_DISABLE(x) ((x) << S_DFI_DATA_BYTE_DISABLE)
58128 #define G_DFI_DATA_BYTE_DISABLE(x) (((x) >> S_DFI_DATA_BYTE_DISABLE) & M_DFI_DATA_BYTE_DISABLE)
58129 
58130 #define S_DFI_FREQ_RATIO    4
58131 #define M_DFI_FREQ_RATIO    0x3U
58132 #define V_DFI_FREQ_RATIO(x) ((x) << S_DFI_FREQ_RATIO)
58133 #define G_DFI_FREQ_RATIO(x) (((x) >> S_DFI_FREQ_RATIO) & M_DFI_FREQ_RATIO)
58134 
58135 #define S_DFI_INIT_START0    1
58136 #define V_DFI_INIT_START0(x) ((x) << S_DFI_INIT_START0)
58137 #define F_DFI_INIT_START0    V_DFI_INIT_START0(1U)
58138 
58139 #define S_DFI_INIT_COMPLETE    0
58140 #define V_DFI_INIT_COMPLETE(x) ((x) << S_DFI_INIT_COMPLETE)
58141 #define F_DFI_INIT_COMPLETE    V_DFI_INIT_COMPLETE(1U)
58142 
58143 #define A_MC_UPCTL_DFISTCFG0 0x402c4
58144 
58145 #define S_DFI_DATA_BYTE_DISABLE_EN    2
58146 #define V_DFI_DATA_BYTE_DISABLE_EN(x) ((x) << S_DFI_DATA_BYTE_DISABLE_EN)
58147 #define F_DFI_DATA_BYTE_DISABLE_EN    V_DFI_DATA_BYTE_DISABLE_EN(1U)
58148 
58149 #define S_DFI_FREQ_RATIO_EN    1
58150 #define V_DFI_FREQ_RATIO_EN(x) ((x) << S_DFI_FREQ_RATIO_EN)
58151 #define F_DFI_FREQ_RATIO_EN    V_DFI_FREQ_RATIO_EN(1U)
58152 
58153 #define S_DFI_INIT_START    0
58154 #define V_DFI_INIT_START(x) ((x) << S_DFI_INIT_START)
58155 #define F_DFI_INIT_START    V_DFI_INIT_START(1U)
58156 
58157 #define A_MC_UPCTL_DFISTCFG1 0x402c8
58158 
58159 #define S_DFI_DRAM_CLK_DISABLE_EN_DPD    1
58160 #define V_DFI_DRAM_CLK_DISABLE_EN_DPD(x) ((x) << S_DFI_DRAM_CLK_DISABLE_EN_DPD)
58161 #define F_DFI_DRAM_CLK_DISABLE_EN_DPD    V_DFI_DRAM_CLK_DISABLE_EN_DPD(1U)
58162 
58163 #define S_DFI_DRAM_CLK_DISABLE_EN    0
58164 #define V_DFI_DRAM_CLK_DISABLE_EN(x) ((x) << S_DFI_DRAM_CLK_DISABLE_EN)
58165 #define F_DFI_DRAM_CLK_DISABLE_EN    V_DFI_DRAM_CLK_DISABLE_EN(1U)
58166 
58167 #define A_MC_UPCTL_DFITDRAMCLKEN 0x402d0
58168 
58169 #define S_TDRAM_CLK_ENABLE    0
58170 #define M_TDRAM_CLK_ENABLE    0xfU
58171 #define V_TDRAM_CLK_ENABLE(x) ((x) << S_TDRAM_CLK_ENABLE)
58172 #define G_TDRAM_CLK_ENABLE(x) (((x) >> S_TDRAM_CLK_ENABLE) & M_TDRAM_CLK_ENABLE)
58173 
58174 #define A_MC_UPCTL_DFITDRAMCLKDIS 0x402d4
58175 
58176 #define S_TDRAM_CLK_DISABLE    0
58177 #define M_TDRAM_CLK_DISABLE    0xfU
58178 #define V_TDRAM_CLK_DISABLE(x) ((x) << S_TDRAM_CLK_DISABLE)
58179 #define G_TDRAM_CLK_DISABLE(x) (((x) >> S_TDRAM_CLK_DISABLE) & M_TDRAM_CLK_DISABLE)
58180 
58181 #define A_MC_UPCTL_DFISTCFG2 0x402d8
58182 
58183 #define S_PARITY_EN    1
58184 #define V_PARITY_EN(x) ((x) << S_PARITY_EN)
58185 #define F_PARITY_EN    V_PARITY_EN(1U)
58186 
58187 #define S_PARITY_INTR_EN    0
58188 #define V_PARITY_INTR_EN(x) ((x) << S_PARITY_INTR_EN)
58189 #define F_PARITY_INTR_EN    V_PARITY_INTR_EN(1U)
58190 
58191 #define A_MC_UPCTL_DFISTPARCLR 0x402dc
58192 
58193 #define S_PARITY_LOG_CLR    1
58194 #define V_PARITY_LOG_CLR(x) ((x) << S_PARITY_LOG_CLR)
58195 #define F_PARITY_LOG_CLR    V_PARITY_LOG_CLR(1U)
58196 
58197 #define S_PARITY_INTR_CLR    0
58198 #define V_PARITY_INTR_CLR(x) ((x) << S_PARITY_INTR_CLR)
58199 #define F_PARITY_INTR_CLR    V_PARITY_INTR_CLR(1U)
58200 
58201 #define A_MC_UPCTL_DFISTPARLOG 0x402e0
58202 #define A_MC_UPCTL_DFILPCFG0 0x402f0
58203 
58204 #define S_DFI_LP_WAKEUP_DPD    28
58205 #define M_DFI_LP_WAKEUP_DPD    0xfU
58206 #define V_DFI_LP_WAKEUP_DPD(x) ((x) << S_DFI_LP_WAKEUP_DPD)
58207 #define G_DFI_LP_WAKEUP_DPD(x) (((x) >> S_DFI_LP_WAKEUP_DPD) & M_DFI_LP_WAKEUP_DPD)
58208 
58209 #define S_DFI_LP_EN_DPD    24
58210 #define V_DFI_LP_EN_DPD(x) ((x) << S_DFI_LP_EN_DPD)
58211 #define F_DFI_LP_EN_DPD    V_DFI_LP_EN_DPD(1U)
58212 
58213 #define S_DFI_TLP_RESP    16
58214 #define M_DFI_TLP_RESP    0xfU
58215 #define V_DFI_TLP_RESP(x) ((x) << S_DFI_TLP_RESP)
58216 #define G_DFI_TLP_RESP(x) (((x) >> S_DFI_TLP_RESP) & M_DFI_TLP_RESP)
58217 
58218 #define S_DFI_LP_EN_SR    8
58219 #define V_DFI_LP_EN_SR(x) ((x) << S_DFI_LP_EN_SR)
58220 #define F_DFI_LP_EN_SR    V_DFI_LP_EN_SR(1U)
58221 
58222 #define S_DFI_LP_WAKEUP_PD    4
58223 #define M_DFI_LP_WAKEUP_PD    0xfU
58224 #define V_DFI_LP_WAKEUP_PD(x) ((x) << S_DFI_LP_WAKEUP_PD)
58225 #define G_DFI_LP_WAKEUP_PD(x) (((x) >> S_DFI_LP_WAKEUP_PD) & M_DFI_LP_WAKEUP_PD)
58226 
58227 #define S_DFI_LP_EN_PD    0
58228 #define V_DFI_LP_EN_PD(x) ((x) << S_DFI_LP_EN_PD)
58229 #define F_DFI_LP_EN_PD    V_DFI_LP_EN_PD(1U)
58230 
58231 #define A_MC_UPCTL_DFITRWRLVLRESP0 0x40300
58232 #define A_MC_UPCTL_DFITRWRLVLRESP1 0x40304
58233 #define A_MC_LMC_CALSTAT 0x40304
58234 
58235 #define S_PHYUPD_ERR    28
58236 #define M_PHYUPD_ERR    0xfU
58237 #define V_PHYUPD_ERR(x) ((x) << S_PHYUPD_ERR)
58238 #define G_PHYUPD_ERR(x) (((x) >> S_PHYUPD_ERR) & M_PHYUPD_ERR)
58239 
58240 #define S_PHYUPD_BUSY    27
58241 #define V_PHYUPD_BUSY(x) ((x) << S_PHYUPD_BUSY)
58242 #define F_PHYUPD_BUSY    V_PHYUPD_BUSY(1U)
58243 
58244 #define A_MC_UPCTL_DFITRWRLVLRESP2 0x40308
58245 
58246 #define S_DFI_WRLVL_RESP2    0
58247 #define M_DFI_WRLVL_RESP2    0xffU
58248 #define V_DFI_WRLVL_RESP2(x) ((x) << S_DFI_WRLVL_RESP2)
58249 #define G_DFI_WRLVL_RESP2(x) (((x) >> S_DFI_WRLVL_RESP2) & M_DFI_WRLVL_RESP2)
58250 
58251 #define A_MC_UPCTL_DFITRRDLVLRESP0 0x4030c
58252 #define A_MC_UPCTL_DFITRRDLVLRESP1 0x40310
58253 #define A_MC_UPCTL_DFITRRDLVLRESP2 0x40314
58254 
58255 #define S_DFI_RDLVL_RESP2    0
58256 #define M_DFI_RDLVL_RESP2    0xffU
58257 #define V_DFI_RDLVL_RESP2(x) ((x) << S_DFI_RDLVL_RESP2)
58258 #define G_DFI_RDLVL_RESP2(x) (((x) >> S_DFI_RDLVL_RESP2) & M_DFI_RDLVL_RESP2)
58259 
58260 #define A_MC_UPCTL_DFITRWRLVLDELAY0 0x40318
58261 #define A_MC_UPCTL_DFITRWRLVLDELAY1 0x4031c
58262 #define A_MC_UPCTL_DFITRWRLVLDELAY2 0x40320
58263 
58264 #define S_DFI_WRLVL_DELAY2    0
58265 #define M_DFI_WRLVL_DELAY2    0xffU
58266 #define V_DFI_WRLVL_DELAY2(x) ((x) << S_DFI_WRLVL_DELAY2)
58267 #define G_DFI_WRLVL_DELAY2(x) (((x) >> S_DFI_WRLVL_DELAY2) & M_DFI_WRLVL_DELAY2)
58268 
58269 #define A_MC_UPCTL_DFITRRDLVLDELAY0 0x40324
58270 #define A_MC_UPCTL_DFITRRDLVLDELAY1 0x40328
58271 #define A_MC_UPCTL_DFITRRDLVLDELAY2 0x4032c
58272 
58273 #define S_DFI_RDLVL_DELAY2    0
58274 #define M_DFI_RDLVL_DELAY2    0xffU
58275 #define V_DFI_RDLVL_DELAY2(x) ((x) << S_DFI_RDLVL_DELAY2)
58276 #define G_DFI_RDLVL_DELAY2(x) (((x) >> S_DFI_RDLVL_DELAY2) & M_DFI_RDLVL_DELAY2)
58277 
58278 #define A_MC_UPCTL_DFITRRDLVLGATEDELAY0 0x40330
58279 #define A_MC_LMC_T_PHYUPD0 0x40330
58280 #define A_MC_UPCTL_DFITRRDLVLGATEDELAY1 0x40334
58281 #define A_MC_LMC_T_PHYUPD1 0x40334
58282 #define A_MC_UPCTL_DFITRRDLVLGATEDELAY2 0x40338
58283 
58284 #define S_DFI_RDLVL_GATE_DELAY2    0
58285 #define M_DFI_RDLVL_GATE_DELAY2    0xffU
58286 #define V_DFI_RDLVL_GATE_DELAY2(x) ((x) << S_DFI_RDLVL_GATE_DELAY2)
58287 #define G_DFI_RDLVL_GATE_DELAY2(x) (((x) >> S_DFI_RDLVL_GATE_DELAY2) & M_DFI_RDLVL_GATE_DELAY2)
58288 
58289 #define A_MC_LMC_T_PHYUPD2 0x40338
58290 #define A_MC_UPCTL_DFITRCMD 0x4033c
58291 
58292 #define S_DFITRCMD_START    31
58293 #define V_DFITRCMD_START(x) ((x) << S_DFITRCMD_START)
58294 #define F_DFITRCMD_START    V_DFITRCMD_START(1U)
58295 
58296 #define S_DFITRCMD_EN    4
58297 #define M_DFITRCMD_EN    0x1ffU
58298 #define V_DFITRCMD_EN(x) ((x) << S_DFITRCMD_EN)
58299 #define G_DFITRCMD_EN(x) (((x) >> S_DFITRCMD_EN) & M_DFITRCMD_EN)
58300 
58301 #define S_DFITRCMD_OPCODE    0
58302 #define M_DFITRCMD_OPCODE    0x3U
58303 #define V_DFITRCMD_OPCODE(x) ((x) << S_DFITRCMD_OPCODE)
58304 #define G_DFITRCMD_OPCODE(x) (((x) >> S_DFITRCMD_OPCODE) & M_DFITRCMD_OPCODE)
58305 
58306 #define A_MC_LMC_T_PHYUPD3 0x4033c
58307 #define A_MC_UPCTL_IPVR 0x403f8
58308 #define A_MC_UPCTL_IPTR 0x403fc
58309 #define A_MC_P_DDRPHY_RST_CTRL 0x41300
58310 
58311 #define S_PHY_DRAM_WL    17
58312 #define M_PHY_DRAM_WL    0x1fU
58313 #define V_PHY_DRAM_WL(x) ((x) << S_PHY_DRAM_WL)
58314 #define G_PHY_DRAM_WL(x) (((x) >> S_PHY_DRAM_WL) & M_PHY_DRAM_WL)
58315 
58316 #define S_PHY_CALIB_DONE    5
58317 #define V_PHY_CALIB_DONE(x) ((x) << S_PHY_CALIB_DONE)
58318 #define F_PHY_CALIB_DONE    V_PHY_CALIB_DONE(1U)
58319 
58320 #define S_CTL_CAL_REQ    4
58321 #define V_CTL_CAL_REQ(x) ((x) << S_CTL_CAL_REQ)
58322 #define F_CTL_CAL_REQ    V_CTL_CAL_REQ(1U)
58323 
58324 #define S_CTL_CKE    3
58325 #define V_CTL_CKE(x) ((x) << S_CTL_CKE)
58326 #define F_CTL_CKE    V_CTL_CKE(1U)
58327 
58328 #define S_CTL_RST_N    2
58329 #define V_CTL_RST_N(x) ((x) << S_CTL_RST_N)
58330 #define F_CTL_RST_N    V_CTL_RST_N(1U)
58331 
58332 #define S_PHY_CAL_REQ    21
58333 #define V_PHY_CAL_REQ(x) ((x) << S_PHY_CAL_REQ)
58334 #define F_PHY_CAL_REQ    V_PHY_CAL_REQ(1U)
58335 
58336 #define S_T6_PHY_DRAM_WL    17
58337 #define M_T6_PHY_DRAM_WL    0xfU
58338 #define V_T6_PHY_DRAM_WL(x) ((x) << S_T6_PHY_DRAM_WL)
58339 #define G_T6_PHY_DRAM_WL(x) (((x) >> S_T6_PHY_DRAM_WL) & M_T6_PHY_DRAM_WL)
58340 
58341 #define A_MC_P_PERFORMANCE_CTRL 0x41304
58342 
58343 #define S_BUF_USE_TH    12
58344 #define M_BUF_USE_TH    0x7U
58345 #define V_BUF_USE_TH(x) ((x) << S_BUF_USE_TH)
58346 #define G_BUF_USE_TH(x) (((x) >> S_BUF_USE_TH) & M_BUF_USE_TH)
58347 
58348 #define S_MC_IDLE_TH    8
58349 #define M_MC_IDLE_TH    0xfU
58350 #define V_MC_IDLE_TH(x) ((x) << S_MC_IDLE_TH)
58351 #define G_MC_IDLE_TH(x) (((x) >> S_MC_IDLE_TH) & M_MC_IDLE_TH)
58352 
58353 #define S_RMW_DEFER_EN    7
58354 #define V_RMW_DEFER_EN(x) ((x) << S_RMW_DEFER_EN)
58355 #define F_RMW_DEFER_EN    V_RMW_DEFER_EN(1U)
58356 
58357 #define S_DDR3_BRBC_MODE    6
58358 #define V_DDR3_BRBC_MODE(x) ((x) << S_DDR3_BRBC_MODE)
58359 #define F_DDR3_BRBC_MODE    V_DDR3_BRBC_MODE(1U)
58360 
58361 #define S_RMW_DWRITE_EN    5
58362 #define V_RMW_DWRITE_EN(x) ((x) << S_RMW_DWRITE_EN)
58363 #define F_RMW_DWRITE_EN    V_RMW_DWRITE_EN(1U)
58364 
58365 #define S_RMW_MERGE_EN    4
58366 #define V_RMW_MERGE_EN(x) ((x) << S_RMW_MERGE_EN)
58367 #define F_RMW_MERGE_EN    V_RMW_MERGE_EN(1U)
58368 
58369 #define S_SYNC_PAB_EN    3
58370 #define V_SYNC_PAB_EN(x) ((x) << S_SYNC_PAB_EN)
58371 #define F_SYNC_PAB_EN    V_SYNC_PAB_EN(1U)
58372 
58373 #define A_MC_P_ECC_CTRL 0x41308
58374 #define A_MC_P_PAR_ENABLE 0x4130c
58375 #define A_MC_P_PAR_CAUSE 0x41310
58376 #define A_MC_P_INT_ENABLE 0x41314
58377 #define A_MC_P_INT_CAUSE 0x41318
58378 #define A_MC_P_ECC_STATUS 0x4131c
58379 #define A_MC_P_PHY_CTRL 0x41320
58380 #define A_MC_P_STATIC_CFG_STATUS 0x41324
58381 
58382 #define S_STATIC_AWEN    23
58383 #define V_STATIC_AWEN(x) ((x) << S_STATIC_AWEN)
58384 #define F_STATIC_AWEN    V_STATIC_AWEN(1U)
58385 
58386 #define S_STATIC_SWLAT    18
58387 #define M_STATIC_SWLAT    0x1fU
58388 #define V_STATIC_SWLAT(x) ((x) << S_STATIC_SWLAT)
58389 #define G_STATIC_SWLAT(x) (((x) >> S_STATIC_SWLAT) & M_STATIC_SWLAT)
58390 
58391 #define S_STATIC_WLAT    17
58392 #define V_STATIC_WLAT(x) ((x) << S_STATIC_WLAT)
58393 #define F_STATIC_WLAT    V_STATIC_WLAT(1U)
58394 
58395 #define S_STATIC_ALIGN    16
58396 #define V_STATIC_ALIGN(x) ((x) << S_STATIC_ALIGN)
58397 #define F_STATIC_ALIGN    V_STATIC_ALIGN(1U)
58398 
58399 #define S_STATIC_SLAT    11
58400 #define M_STATIC_SLAT    0x1fU
58401 #define V_STATIC_SLAT(x) ((x) << S_STATIC_SLAT)
58402 #define G_STATIC_SLAT(x) (((x) >> S_STATIC_SLAT) & M_STATIC_SLAT)
58403 
58404 #define S_STATIC_LAT    10
58405 #define V_STATIC_LAT(x) ((x) << S_STATIC_LAT)
58406 #define F_STATIC_LAT    V_STATIC_LAT(1U)
58407 
58408 #define S_STATIC_PP64    26
58409 #define V_STATIC_PP64(x) ((x) << S_STATIC_PP64)
58410 #define F_STATIC_PP64    V_STATIC_PP64(1U)
58411 
58412 #define S_STATIC_PPEN    25
58413 #define V_STATIC_PPEN(x) ((x) << S_STATIC_PPEN)
58414 #define F_STATIC_PPEN    V_STATIC_PPEN(1U)
58415 
58416 #define S_STATIC_OOOEN    24
58417 #define V_STATIC_OOOEN(x) ((x) << S_STATIC_OOOEN)
58418 #define F_STATIC_OOOEN    V_STATIC_OOOEN(1U)
58419 
58420 #define A_MC_P_CORE_PCTL_STAT 0x41328
58421 #define A_MC_P_DEBUG_CNT 0x4132c
58422 #define A_MC_CE_ERR_DATA_RDATA 0x41330
58423 #define A_MC_CE_COR_DATA_RDATA 0x41350
58424 #define A_MC_UE_ERR_DATA_RDATA 0x41370
58425 #define A_MC_UE_COR_DATA_RDATA 0x41390
58426 #define A_MC_CE_ADDR 0x413b0
58427 #define A_MC_UE_ADDR 0x413b4
58428 #define A_MC_P_DEEP_SLEEP 0x413b8
58429 
58430 #define S_SLEEPSTATUS    1
58431 #define V_SLEEPSTATUS(x) ((x) << S_SLEEPSTATUS)
58432 #define F_SLEEPSTATUS    V_SLEEPSTATUS(1U)
58433 
58434 #define S_SLEEPREQ    0
58435 #define V_SLEEPREQ(x) ((x) << S_SLEEPREQ)
58436 #define F_SLEEPREQ    V_SLEEPREQ(1U)
58437 
58438 #define A_MC_P_FPGA_BONUS 0x413bc
58439 #define A_MC_P_DEBUG_CFG 0x413c0
58440 #define A_MC_P_DEBUG_RPT 0x413c4
58441 #define A_MC_P_PHY_ADR_CK_EN 0x413c8
58442 
58443 #define S_ADR_CK_EN    0
58444 #define V_ADR_CK_EN(x) ((x) << S_ADR_CK_EN)
58445 #define F_ADR_CK_EN    V_ADR_CK_EN(1U)
58446 
58447 #define A_MC_CE_ERR_ECC_DATA0 0x413d0
58448 #define A_MC_CE_ERR_ECC_DATA1 0x413d4
58449 #define A_MC_UE_ERR_ECC_DATA0 0x413d8
58450 #define A_MC_UE_ERR_ECC_DATA1 0x413dc
58451 #define A_MC_P_RMW_PRIO 0x413f0
58452 
58453 #define S_WR_HI_TH    24
58454 #define M_WR_HI_TH    0xffU
58455 #define V_WR_HI_TH(x) ((x) << S_WR_HI_TH)
58456 #define G_WR_HI_TH(x) (((x) >> S_WR_HI_TH) & M_WR_HI_TH)
58457 
58458 #define S_WR_MID_TH    16
58459 #define M_WR_MID_TH    0xffU
58460 #define V_WR_MID_TH(x) ((x) << S_WR_MID_TH)
58461 #define G_WR_MID_TH(x) (((x) >> S_WR_MID_TH) & M_WR_MID_TH)
58462 
58463 #define S_RD_HI_TH    8
58464 #define M_RD_HI_TH    0xffU
58465 #define V_RD_HI_TH(x) ((x) << S_RD_HI_TH)
58466 #define G_RD_HI_TH(x) (((x) >> S_RD_HI_TH) & M_RD_HI_TH)
58467 
58468 #define S_RD_MID_TH    0
58469 #define M_RD_MID_TH    0xffU
58470 #define V_RD_MID_TH(x) ((x) << S_RD_MID_TH)
58471 #define G_RD_MID_TH(x) (((x) >> S_RD_MID_TH) & M_RD_MID_TH)
58472 
58473 #define A_MC_P_BIST_CMD 0x41400
58474 
58475 #define S_BURST_LEN    16
58476 #define M_BURST_LEN    0x3U
58477 #define V_BURST_LEN(x) ((x) << S_BURST_LEN)
58478 #define G_BURST_LEN(x) (((x) >> S_BURST_LEN) & M_BURST_LEN)
58479 
58480 #define A_MC_P_BIST_CMD_ADDR 0x41404
58481 #define A_MC_P_BIST_CMD_LEN 0x41408
58482 #define A_MC_P_BIST_DATA_PATTERN 0x4140c
58483 #define A_MC_P_BIST_USER_WDATA0 0x41414
58484 #define A_MC_P_BIST_USER_WMASK0 0x41414
58485 #define A_MC_P_BIST_USER_WDATA1 0x41418
58486 #define A_MC_P_BIST_USER_WMASK1 0x41418
58487 #define A_MC_P_BIST_USER_WDATA2 0x4141c
58488 
58489 #define S_USER_DATA_MASK    8
58490 #define M_USER_DATA_MASK    0x1ffU
58491 #define V_USER_DATA_MASK(x) ((x) << S_USER_DATA_MASK)
58492 #define G_USER_DATA_MASK(x) (((x) >> S_USER_DATA_MASK) & M_USER_DATA_MASK)
58493 
58494 #define A_MC_P_BIST_USER_WMASK2 0x4141c
58495 
58496 #define S_MASK_128_1    9
58497 #define V_MASK_128_1(x) ((x) << S_MASK_128_1)
58498 #define F_MASK_128_1    V_MASK_128_1(1U)
58499 
58500 #define S_MASK_128_0    8
58501 #define V_MASK_128_0(x) ((x) << S_MASK_128_0)
58502 #define F_MASK_128_0    V_MASK_128_0(1U)
58503 
58504 #define S_USER_MASK_ECC    0
58505 #define M_USER_MASK_ECC    0xffU
58506 #define V_USER_MASK_ECC(x) ((x) << S_USER_MASK_ECC)
58507 #define G_USER_MASK_ECC(x) (((x) >> S_USER_MASK_ECC) & M_USER_MASK_ECC)
58508 
58509 #define A_MC_P_BIST_NUM_ERR 0x41480
58510 #define A_MC_P_BIST_ERR_FIRST_ADDR 0x41484
58511 #define A_MC_P_BIST_STATUS_RDATA 0x41488
58512 #define A_MC_P_BIST_CRC_SEED 0x414d0
58513 #define A_MC_DDRPHY_DP18_DATA_BIT_ENABLE0 0x44000
58514 
58515 #define S_DATA_BIT_ENABLE_0_15    0
58516 #define M_DATA_BIT_ENABLE_0_15    0xffffU
58517 #define V_DATA_BIT_ENABLE_0_15(x) ((x) << S_DATA_BIT_ENABLE_0_15)
58518 #define G_DATA_BIT_ENABLE_0_15(x) (((x) >> S_DATA_BIT_ENABLE_0_15) & M_DATA_BIT_ENABLE_0_15)
58519 
58520 #define A_MC_DDRPHY_DP18_DATA_BIT_ENABLE1 0x44004
58521 
58522 #define S_DATA_BIT_ENABLE_16_23    8
58523 #define M_DATA_BIT_ENABLE_16_23    0xffU
58524 #define V_DATA_BIT_ENABLE_16_23(x) ((x) << S_DATA_BIT_ENABLE_16_23)
58525 #define G_DATA_BIT_ENABLE_16_23(x) (((x) >> S_DATA_BIT_ENABLE_16_23) & M_DATA_BIT_ENABLE_16_23)
58526 
58527 #define S_DFT_FORCE_OUTPUTS    7
58528 #define V_DFT_FORCE_OUTPUTS(x) ((x) << S_DFT_FORCE_OUTPUTS)
58529 #define F_DFT_FORCE_OUTPUTS    V_DFT_FORCE_OUTPUTS(1U)
58530 
58531 #define S_DFT_PRBS7_GEN_EN    6
58532 #define V_DFT_PRBS7_GEN_EN(x) ((x) << S_DFT_PRBS7_GEN_EN)
58533 #define F_DFT_PRBS7_GEN_EN    V_DFT_PRBS7_GEN_EN(1U)
58534 
58535 #define S_WRAPSEL    5
58536 #define V_WRAPSEL(x) ((x) << S_WRAPSEL)
58537 #define F_WRAPSEL    V_WRAPSEL(1U)
58538 
58539 #define S_MRS_CMD_DATA_N0    3
58540 #define V_MRS_CMD_DATA_N0(x) ((x) << S_MRS_CMD_DATA_N0)
58541 #define F_MRS_CMD_DATA_N0    V_MRS_CMD_DATA_N0(1U)
58542 
58543 #define S_MRS_CMD_DATA_N1    2
58544 #define V_MRS_CMD_DATA_N1(x) ((x) << S_MRS_CMD_DATA_N1)
58545 #define F_MRS_CMD_DATA_N1    V_MRS_CMD_DATA_N1(1U)
58546 
58547 #define S_MRS_CMD_DATA_N2    1
58548 #define V_MRS_CMD_DATA_N2(x) ((x) << S_MRS_CMD_DATA_N2)
58549 #define F_MRS_CMD_DATA_N2    V_MRS_CMD_DATA_N2(1U)
58550 
58551 #define S_MRS_CMD_DATA_N3    0
58552 #define V_MRS_CMD_DATA_N3(x) ((x) << S_MRS_CMD_DATA_N3)
58553 #define F_MRS_CMD_DATA_N3    V_MRS_CMD_DATA_N3(1U)
58554 
58555 #define S_DP18_WRAPSEL    5
58556 #define V_DP18_WRAPSEL(x) ((x) << S_DP18_WRAPSEL)
58557 #define F_DP18_WRAPSEL    V_DP18_WRAPSEL(1U)
58558 
58559 #define S_HW_VALUE    4
58560 #define V_HW_VALUE(x) ((x) << S_HW_VALUE)
58561 #define F_HW_VALUE    V_HW_VALUE(1U)
58562 
58563 #define A_MC_DDRPHY_DP18_DATA_BIT_DIR0 0x44008
58564 
58565 #define S_DATA_BIT_DIR_0_15    0
58566 #define M_DATA_BIT_DIR_0_15    0xffffU
58567 #define V_DATA_BIT_DIR_0_15(x) ((x) << S_DATA_BIT_DIR_0_15)
58568 #define G_DATA_BIT_DIR_0_15(x) (((x) >> S_DATA_BIT_DIR_0_15) & M_DATA_BIT_DIR_0_15)
58569 
58570 #define A_MC_DDRPHY_DP18_DATA_BIT_DIR1 0x4400c
58571 
58572 #define S_DATA_BIT_DIR_16_23    8
58573 #define M_DATA_BIT_DIR_16_23    0xffU
58574 #define V_DATA_BIT_DIR_16_23(x) ((x) << S_DATA_BIT_DIR_16_23)
58575 #define G_DATA_BIT_DIR_16_23(x) (((x) >> S_DATA_BIT_DIR_16_23) & M_DATA_BIT_DIR_16_23)
58576 
58577 #define S_WL_ADVANCE_DISABLE    7
58578 #define V_WL_ADVANCE_DISABLE(x) ((x) << S_WL_ADVANCE_DISABLE)
58579 #define F_WL_ADVANCE_DISABLE    V_WL_ADVANCE_DISABLE(1U)
58580 
58581 #define S_DISABLE_PING_PONG    6
58582 #define V_DISABLE_PING_PONG(x) ((x) << S_DISABLE_PING_PONG)
58583 #define F_DISABLE_PING_PONG    V_DISABLE_PING_PONG(1U)
58584 
58585 #define S_DELAY_PING_PONG_HALF    5
58586 #define V_DELAY_PING_PONG_HALF(x) ((x) << S_DELAY_PING_PONG_HALF)
58587 #define F_DELAY_PING_PONG_HALF    V_DELAY_PING_PONG_HALF(1U)
58588 
58589 #define S_ADVANCE_PING_PONG    4
58590 #define V_ADVANCE_PING_PONG(x) ((x) << S_ADVANCE_PING_PONG)
58591 #define F_ADVANCE_PING_PONG    V_ADVANCE_PING_PONG(1U)
58592 
58593 #define S_ATEST_MUX_CTL0    3
58594 #define V_ATEST_MUX_CTL0(x) ((x) << S_ATEST_MUX_CTL0)
58595 #define F_ATEST_MUX_CTL0    V_ATEST_MUX_CTL0(1U)
58596 
58597 #define S_ATEST_MUX_CTL1    2
58598 #define V_ATEST_MUX_CTL1(x) ((x) << S_ATEST_MUX_CTL1)
58599 #define F_ATEST_MUX_CTL1    V_ATEST_MUX_CTL1(1U)
58600 
58601 #define S_ATEST_MUX_CTL2    1
58602 #define V_ATEST_MUX_CTL2(x) ((x) << S_ATEST_MUX_CTL2)
58603 #define F_ATEST_MUX_CTL2    V_ATEST_MUX_CTL2(1U)
58604 
58605 #define S_ATEST_MUX_CTL3    0
58606 #define V_ATEST_MUX_CTL3(x) ((x) << S_ATEST_MUX_CTL3)
58607 #define F_ATEST_MUX_CTL3    V_ATEST_MUX_CTL3(1U)
58608 
58609 #define A_MC_DDRPHY_DP18_READ_CLOCK_RANK_PAIR 0x44010
58610 
58611 #define S_QUAD0_CLK16_BIT0    15
58612 #define V_QUAD0_CLK16_BIT0(x) ((x) << S_QUAD0_CLK16_BIT0)
58613 #define F_QUAD0_CLK16_BIT0    V_QUAD0_CLK16_BIT0(1U)
58614 
58615 #define S_QUAD1_CLK16_BIT1    14
58616 #define V_QUAD1_CLK16_BIT1(x) ((x) << S_QUAD1_CLK16_BIT1)
58617 #define F_QUAD1_CLK16_BIT1    V_QUAD1_CLK16_BIT1(1U)
58618 
58619 #define S_QUAD2_CLK16_BIT2    13
58620 #define V_QUAD2_CLK16_BIT2(x) ((x) << S_QUAD2_CLK16_BIT2)
58621 #define F_QUAD2_CLK16_BIT2    V_QUAD2_CLK16_BIT2(1U)
58622 
58623 #define S_QUAD3_CLK16_BIT3    12
58624 #define V_QUAD3_CLK16_BIT3(x) ((x) << S_QUAD3_CLK16_BIT3)
58625 #define F_QUAD3_CLK16_BIT3    V_QUAD3_CLK16_BIT3(1U)
58626 
58627 #define S_QUAD0_CLK18_BIT4    11
58628 #define V_QUAD0_CLK18_BIT4(x) ((x) << S_QUAD0_CLK18_BIT4)
58629 #define F_QUAD0_CLK18_BIT4    V_QUAD0_CLK18_BIT4(1U)
58630 
58631 #define S_QUAD1_CLK18_BIT5    10
58632 #define V_QUAD1_CLK18_BIT5(x) ((x) << S_QUAD1_CLK18_BIT5)
58633 #define F_QUAD1_CLK18_BIT5    V_QUAD1_CLK18_BIT5(1U)
58634 
58635 #define S_QUAD2_CLK20_BIT6    9
58636 #define V_QUAD2_CLK20_BIT6(x) ((x) << S_QUAD2_CLK20_BIT6)
58637 #define F_QUAD2_CLK20_BIT6    V_QUAD2_CLK20_BIT6(1U)
58638 
58639 #define S_QUAD3_CLK20_BIT7    8
58640 #define V_QUAD3_CLK20_BIT7(x) ((x) << S_QUAD3_CLK20_BIT7)
58641 #define F_QUAD3_CLK20_BIT7    V_QUAD3_CLK20_BIT7(1U)
58642 
58643 #define S_QUAD2_CLK22_BIT8    7
58644 #define V_QUAD2_CLK22_BIT8(x) ((x) << S_QUAD2_CLK22_BIT8)
58645 #define F_QUAD2_CLK22_BIT8    V_QUAD2_CLK22_BIT8(1U)
58646 
58647 #define S_QUAD3_CLK22_BIT9    6
58648 #define V_QUAD3_CLK22_BIT9(x) ((x) << S_QUAD3_CLK22_BIT9)
58649 #define F_QUAD3_CLK22_BIT9    V_QUAD3_CLK22_BIT9(1U)
58650 
58651 #define S_CLK16_SINGLE_ENDED_BIT10    5
58652 #define V_CLK16_SINGLE_ENDED_BIT10(x) ((x) << S_CLK16_SINGLE_ENDED_BIT10)
58653 #define F_CLK16_SINGLE_ENDED_BIT10    V_CLK16_SINGLE_ENDED_BIT10(1U)
58654 
58655 #define S_CLK18_SINGLE_ENDED_BIT11    4
58656 #define V_CLK18_SINGLE_ENDED_BIT11(x) ((x) << S_CLK18_SINGLE_ENDED_BIT11)
58657 #define F_CLK18_SINGLE_ENDED_BIT11    V_CLK18_SINGLE_ENDED_BIT11(1U)
58658 
58659 #define S_CLK20_SINGLE_ENDED_BIT12    3
58660 #define V_CLK20_SINGLE_ENDED_BIT12(x) ((x) << S_CLK20_SINGLE_ENDED_BIT12)
58661 #define F_CLK20_SINGLE_ENDED_BIT12    V_CLK20_SINGLE_ENDED_BIT12(1U)
58662 
58663 #define S_CLK22_SINGLE_ENDED_BIT13    2
58664 #define V_CLK22_SINGLE_ENDED_BIT13(x) ((x) << S_CLK22_SINGLE_ENDED_BIT13)
58665 #define F_CLK22_SINGLE_ENDED_BIT13    V_CLK22_SINGLE_ENDED_BIT13(1U)
58666 
58667 #define A_MC_DDRPHY_DP18_WRCLK_EN_RP 0x44014
58668 
58669 #define S_QUAD2_CLK18_BIT14    1
58670 #define V_QUAD2_CLK18_BIT14(x) ((x) << S_QUAD2_CLK18_BIT14)
58671 #define F_QUAD2_CLK18_BIT14    V_QUAD2_CLK18_BIT14(1U)
58672 
58673 #define S_QUAD3_CLK18_BIT15    0
58674 #define V_QUAD3_CLK18_BIT15(x) ((x) << S_QUAD3_CLK18_BIT15)
58675 #define F_QUAD3_CLK18_BIT15    V_QUAD3_CLK18_BIT15(1U)
58676 
58677 #define A_MC_DDRPHY_DP18_RX_PEAK_AMP 0x44018
58678 
58679 #define S_PEAK_AMP_CTL_SIDE0    13
58680 #define M_PEAK_AMP_CTL_SIDE0    0x7U
58681 #define V_PEAK_AMP_CTL_SIDE0(x) ((x) << S_PEAK_AMP_CTL_SIDE0)
58682 #define G_PEAK_AMP_CTL_SIDE0(x) (((x) >> S_PEAK_AMP_CTL_SIDE0) & M_PEAK_AMP_CTL_SIDE0)
58683 
58684 #define S_PEAK_AMP_CTL_SIDE1    9
58685 #define M_PEAK_AMP_CTL_SIDE1    0x7U
58686 #define V_PEAK_AMP_CTL_SIDE1(x) ((x) << S_PEAK_AMP_CTL_SIDE1)
58687 #define G_PEAK_AMP_CTL_SIDE1(x) (((x) >> S_PEAK_AMP_CTL_SIDE1) & M_PEAK_AMP_CTL_SIDE1)
58688 
58689 #define S_SXMCVREF_0_3    4
58690 #define M_SXMCVREF_0_3    0xfU
58691 #define V_SXMCVREF_0_3(x) ((x) << S_SXMCVREF_0_3)
58692 #define G_SXMCVREF_0_3(x) (((x) >> S_SXMCVREF_0_3) & M_SXMCVREF_0_3)
58693 
58694 #define S_SXPODVREF    3
58695 #define V_SXPODVREF(x) ((x) << S_SXPODVREF)
58696 #define F_SXPODVREF    V_SXPODVREF(1U)
58697 
58698 #define S_DISABLE_TERMINATION    2
58699 #define V_DISABLE_TERMINATION(x) ((x) << S_DISABLE_TERMINATION)
58700 #define F_DISABLE_TERMINATION    V_DISABLE_TERMINATION(1U)
58701 
58702 #define S_READ_CENTERING_MODE    0
58703 #define M_READ_CENTERING_MODE    0x3U
58704 #define V_READ_CENTERING_MODE(x) ((x) << S_READ_CENTERING_MODE)
58705 #define G_READ_CENTERING_MODE(x) (((x) >> S_READ_CENTERING_MODE) & M_READ_CENTERING_MODE)
58706 
58707 #define A_MC_DDRPHY_DP18_SYSCLK_PR 0x4401c
58708 
58709 #define S_SYSCLK_PHASE_ALIGN_RESET    6
58710 #define V_SYSCLK_PHASE_ALIGN_RESET(x) ((x) << S_SYSCLK_PHASE_ALIGN_RESET)
58711 #define F_SYSCLK_PHASE_ALIGN_RESET    V_SYSCLK_PHASE_ALIGN_RESET(1U)
58712 
58713 #define A_MC_DDRPHY_DP18_DFT_DIG_EYE 0x44020
58714 
58715 #define S_DIGITAL_EYE_EN    15
58716 #define V_DIGITAL_EYE_EN(x) ((x) << S_DIGITAL_EYE_EN)
58717 #define F_DIGITAL_EYE_EN    V_DIGITAL_EYE_EN(1U)
58718 
58719 #define S_BUMP    14
58720 #define V_BUMP(x) ((x) << S_BUMP)
58721 #define F_BUMP    V_BUMP(1U)
58722 
58723 #define S_TRIG_PERIOD    13
58724 #define V_TRIG_PERIOD(x) ((x) << S_TRIG_PERIOD)
58725 #define F_TRIG_PERIOD    V_TRIG_PERIOD(1U)
58726 
58727 #define S_CNTL_POL    12
58728 #define V_CNTL_POL(x) ((x) << S_CNTL_POL)
58729 #define F_CNTL_POL    V_CNTL_POL(1U)
58730 
58731 #define S_CNTL_SRC    8
58732 #define V_CNTL_SRC(x) ((x) << S_CNTL_SRC)
58733 #define F_CNTL_SRC    V_CNTL_SRC(1U)
58734 
58735 #define S_DIGITAL_EYE_VALUE    0
58736 #define M_DIGITAL_EYE_VALUE    0xffU
58737 #define V_DIGITAL_EYE_VALUE(x) ((x) << S_DIGITAL_EYE_VALUE)
58738 #define G_DIGITAL_EYE_VALUE(x) (((x) >> S_DIGITAL_EYE_VALUE) & M_DIGITAL_EYE_VALUE)
58739 
58740 #define A_MC_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR 0x44024
58741 
58742 #define S_DQSCLK_SELECT0    14
58743 #define M_DQSCLK_SELECT0    0x3U
58744 #define V_DQSCLK_SELECT0(x) ((x) << S_DQSCLK_SELECT0)
58745 #define G_DQSCLK_SELECT0(x) (((x) >> S_DQSCLK_SELECT0) & M_DQSCLK_SELECT0)
58746 
58747 #define S_RDCLK_SELECT0    12
58748 #define M_RDCLK_SELECT0    0x3U
58749 #define V_RDCLK_SELECT0(x) ((x) << S_RDCLK_SELECT0)
58750 #define G_RDCLK_SELECT0(x) (((x) >> S_RDCLK_SELECT0) & M_RDCLK_SELECT0)
58751 
58752 #define S_DQSCLK_SELECT1    10
58753 #define M_DQSCLK_SELECT1    0x3U
58754 #define V_DQSCLK_SELECT1(x) ((x) << S_DQSCLK_SELECT1)
58755 #define G_DQSCLK_SELECT1(x) (((x) >> S_DQSCLK_SELECT1) & M_DQSCLK_SELECT1)
58756 
58757 #define S_RDCLK_SELECT1    8
58758 #define M_RDCLK_SELECT1    0x3U
58759 #define V_RDCLK_SELECT1(x) ((x) << S_RDCLK_SELECT1)
58760 #define G_RDCLK_SELECT1(x) (((x) >> S_RDCLK_SELECT1) & M_RDCLK_SELECT1)
58761 
58762 #define S_DQSCLK_SELECT2    6
58763 #define M_DQSCLK_SELECT2    0x3U
58764 #define V_DQSCLK_SELECT2(x) ((x) << S_DQSCLK_SELECT2)
58765 #define G_DQSCLK_SELECT2(x) (((x) >> S_DQSCLK_SELECT2) & M_DQSCLK_SELECT2)
58766 
58767 #define S_RDCLK_SELECT2    4
58768 #define M_RDCLK_SELECT2    0x3U
58769 #define V_RDCLK_SELECT2(x) ((x) << S_RDCLK_SELECT2)
58770 #define G_RDCLK_SELECT2(x) (((x) >> S_RDCLK_SELECT2) & M_RDCLK_SELECT2)
58771 
58772 #define S_DQSCLK_SELECT3    2
58773 #define M_DQSCLK_SELECT3    0x3U
58774 #define V_DQSCLK_SELECT3(x) ((x) << S_DQSCLK_SELECT3)
58775 #define G_DQSCLK_SELECT3(x) (((x) >> S_DQSCLK_SELECT3) & M_DQSCLK_SELECT3)
58776 
58777 #define S_RDCLK_SELECT3    0
58778 #define M_RDCLK_SELECT3    0x3U
58779 #define V_RDCLK_SELECT3(x) ((x) << S_RDCLK_SELECT3)
58780 #define G_RDCLK_SELECT3(x) (((x) >> S_RDCLK_SELECT3) & M_RDCLK_SELECT3)
58781 
58782 #define A_MC_DDRPHY_DP18_DRIFT_LIMITS 0x44028
58783 
58784 #define S_MIN_RD_EYE_SIZE    8
58785 #define M_MIN_RD_EYE_SIZE    0x3fU
58786 #define V_MIN_RD_EYE_SIZE(x) ((x) << S_MIN_RD_EYE_SIZE)
58787 #define G_MIN_RD_EYE_SIZE(x) (((x) >> S_MIN_RD_EYE_SIZE) & M_MIN_RD_EYE_SIZE)
58788 
58789 #define S_MAX_DQS_DRIFT    0
58790 #define M_MAX_DQS_DRIFT    0x3fU
58791 #define V_MAX_DQS_DRIFT(x) ((x) << S_MAX_DQS_DRIFT)
58792 #define G_MAX_DQS_DRIFT(x) (((x) >> S_MAX_DQS_DRIFT) & M_MAX_DQS_DRIFT)
58793 
58794 #define A_MC_DDRPHY_DP18_DEBUG_SEL 0x4402c
58795 
58796 #define S_HS_PROBE_A_SEL    11
58797 #define M_HS_PROBE_A_SEL    0x1fU
58798 #define V_HS_PROBE_A_SEL(x) ((x) << S_HS_PROBE_A_SEL)
58799 #define G_HS_PROBE_A_SEL(x) (((x) >> S_HS_PROBE_A_SEL) & M_HS_PROBE_A_SEL)
58800 
58801 #define S_HS_PROBE_B_SEL    6
58802 #define M_HS_PROBE_B_SEL    0x1fU
58803 #define V_HS_PROBE_B_SEL(x) ((x) << S_HS_PROBE_B_SEL)
58804 #define G_HS_PROBE_B_SEL(x) (((x) >> S_HS_PROBE_B_SEL) & M_HS_PROBE_B_SEL)
58805 
58806 #define S_RD_DEBUG_SEL    3
58807 #define M_RD_DEBUG_SEL    0x7U
58808 #define V_RD_DEBUG_SEL(x) ((x) << S_RD_DEBUG_SEL)
58809 #define G_RD_DEBUG_SEL(x) (((x) >> S_RD_DEBUG_SEL) & M_RD_DEBUG_SEL)
58810 
58811 #define S_WR_DEBUG_SEL    0
58812 #define M_WR_DEBUG_SEL    0x7U
58813 #define V_WR_DEBUG_SEL(x) ((x) << S_WR_DEBUG_SEL)
58814 #define G_WR_DEBUG_SEL(x) (((x) >> S_WR_DEBUG_SEL) & M_WR_DEBUG_SEL)
58815 
58816 #define S_DP18_HS_PROBE_A_SEL    11
58817 #define M_DP18_HS_PROBE_A_SEL    0x1fU
58818 #define V_DP18_HS_PROBE_A_SEL(x) ((x) << S_DP18_HS_PROBE_A_SEL)
58819 #define G_DP18_HS_PROBE_A_SEL(x) (((x) >> S_DP18_HS_PROBE_A_SEL) & M_DP18_HS_PROBE_A_SEL)
58820 
58821 #define S_DP18_HS_PROBE_B_SEL    6
58822 #define M_DP18_HS_PROBE_B_SEL    0x1fU
58823 #define V_DP18_HS_PROBE_B_SEL(x) ((x) << S_DP18_HS_PROBE_B_SEL)
58824 #define G_DP18_HS_PROBE_B_SEL(x) (((x) >> S_DP18_HS_PROBE_B_SEL) & M_DP18_HS_PROBE_B_SEL)
58825 
58826 #define A_MC_DDRPHY_DP18_READ_DELAY_OFFSET0_RANK_PAIR 0x44030
58827 
58828 #define S_OFFSET_BITS1_7    8
58829 #define M_OFFSET_BITS1_7    0x7fU
58830 #define V_OFFSET_BITS1_7(x) ((x) << S_OFFSET_BITS1_7)
58831 #define G_OFFSET_BITS1_7(x) (((x) >> S_OFFSET_BITS1_7) & M_OFFSET_BITS1_7)
58832 
58833 #define S_OFFSET_BITS9_15    0
58834 #define M_OFFSET_BITS9_15    0x7fU
58835 #define V_OFFSET_BITS9_15(x) ((x) << S_OFFSET_BITS9_15)
58836 #define G_OFFSET_BITS9_15(x) (((x) >> S_OFFSET_BITS9_15) & M_OFFSET_BITS9_15)
58837 
58838 #define A_MC_DDRPHY_DP18_READ_DELAY_OFFSET1_RANK_PAIR 0x44034
58839 #define A_MC_DDRPHY_DP18_RD_LVL_STATUS0 0x44038
58840 
58841 #define S_LEADING_EDGE_NOT_FOUND_0    0
58842 #define M_LEADING_EDGE_NOT_FOUND_0    0xffffU
58843 #define V_LEADING_EDGE_NOT_FOUND_0(x) ((x) << S_LEADING_EDGE_NOT_FOUND_0)
58844 #define G_LEADING_EDGE_NOT_FOUND_0(x) (((x) >> S_LEADING_EDGE_NOT_FOUND_0) & M_LEADING_EDGE_NOT_FOUND_0)
58845 
58846 #define A_MC_DDRPHY_DP18_RD_LVL_STATUS1 0x4403c
58847 
58848 #define S_LEADING_EDGE_NOT_FOUND_1    8
58849 #define M_LEADING_EDGE_NOT_FOUND_1    0xffU
58850 #define V_LEADING_EDGE_NOT_FOUND_1(x) ((x) << S_LEADING_EDGE_NOT_FOUND_1)
58851 #define G_LEADING_EDGE_NOT_FOUND_1(x) (((x) >> S_LEADING_EDGE_NOT_FOUND_1) & M_LEADING_EDGE_NOT_FOUND_1)
58852 
58853 #define A_MC_DDRPHY_DP18_RD_LVL_STATUS2 0x44040
58854 
58855 #define S_TRAILING_EDGE_NOT_FOUND    0
58856 #define M_TRAILING_EDGE_NOT_FOUND    0xffffU
58857 #define V_TRAILING_EDGE_NOT_FOUND(x) ((x) << S_TRAILING_EDGE_NOT_FOUND)
58858 #define G_TRAILING_EDGE_NOT_FOUND(x) (((x) >> S_TRAILING_EDGE_NOT_FOUND) & M_TRAILING_EDGE_NOT_FOUND)
58859 
58860 #define A_MC_DDRPHY_DP18_RD_LVL_STATUS3 0x44044
58861 
58862 #define S_TRAILING_EDGE_NOT_FOUND_16_23    8
58863 #define M_TRAILING_EDGE_NOT_FOUND_16_23    0xffU
58864 #define V_TRAILING_EDGE_NOT_FOUND_16_23(x) ((x) << S_TRAILING_EDGE_NOT_FOUND_16_23)
58865 #define G_TRAILING_EDGE_NOT_FOUND_16_23(x) (((x) >> S_TRAILING_EDGE_NOT_FOUND_16_23) & M_TRAILING_EDGE_NOT_FOUND_16_23)
58866 
58867 #define A_MC_DDRPHY_DP18_RD_DIA_CONFIG5 0x44048
58868 
58869 #define S_DYN_POWER_CNTL_EN    15
58870 #define V_DYN_POWER_CNTL_EN(x) ((x) << S_DYN_POWER_CNTL_EN)
58871 #define F_DYN_POWER_CNTL_EN    V_DYN_POWER_CNTL_EN(1U)
58872 
58873 #define S_DYN_MCTERM_CNTL_EN    14
58874 #define V_DYN_MCTERM_CNTL_EN(x) ((x) << S_DYN_MCTERM_CNTL_EN)
58875 #define F_DYN_MCTERM_CNTL_EN    V_DYN_MCTERM_CNTL_EN(1U)
58876 
58877 #define S_DYN_RX_GATE_CNTL_EN    13
58878 #define V_DYN_RX_GATE_CNTL_EN(x) ((x) << S_DYN_RX_GATE_CNTL_EN)
58879 #define F_DYN_RX_GATE_CNTL_EN    V_DYN_RX_GATE_CNTL_EN(1U)
58880 
58881 #define S_CALGATE_ON    12
58882 #define V_CALGATE_ON(x) ((x) << S_CALGATE_ON)
58883 #define F_CALGATE_ON    V_CALGATE_ON(1U)
58884 
58885 #define S_PER_RDCLK_UPDATE_DIS    11
58886 #define V_PER_RDCLK_UPDATE_DIS(x) ((x) << S_PER_RDCLK_UPDATE_DIS)
58887 #define F_PER_RDCLK_UPDATE_DIS    V_PER_RDCLK_UPDATE_DIS(1U)
58888 
58889 #define S_DQS_ALIGN_BY_QUAD    4
58890 #define V_DQS_ALIGN_BY_QUAD(x) ((x) << S_DQS_ALIGN_BY_QUAD)
58891 #define F_DQS_ALIGN_BY_QUAD    V_DQS_ALIGN_BY_QUAD(1U)
58892 
58893 #define A_MC_DDRPHY_DP18_DQS_GATE_DELAY_RP 0x4404c
58894 
58895 #define S_DQS_GATE_DELAY_N0    12
58896 #define M_DQS_GATE_DELAY_N0    0x7U
58897 #define V_DQS_GATE_DELAY_N0(x) ((x) << S_DQS_GATE_DELAY_N0)
58898 #define G_DQS_GATE_DELAY_N0(x) (((x) >> S_DQS_GATE_DELAY_N0) & M_DQS_GATE_DELAY_N0)
58899 
58900 #define S_DQS_GATE_DELAY_N1    8
58901 #define M_DQS_GATE_DELAY_N1    0x7U
58902 #define V_DQS_GATE_DELAY_N1(x) ((x) << S_DQS_GATE_DELAY_N1)
58903 #define G_DQS_GATE_DELAY_N1(x) (((x) >> S_DQS_GATE_DELAY_N1) & M_DQS_GATE_DELAY_N1)
58904 
58905 #define S_DQS_GATE_DELAY_N2    4
58906 #define M_DQS_GATE_DELAY_N2    0x7U
58907 #define V_DQS_GATE_DELAY_N2(x) ((x) << S_DQS_GATE_DELAY_N2)
58908 #define G_DQS_GATE_DELAY_N2(x) (((x) >> S_DQS_GATE_DELAY_N2) & M_DQS_GATE_DELAY_N2)
58909 
58910 #define S_DQS_GATE_DELAY_N3    0
58911 #define M_DQS_GATE_DELAY_N3    0x7U
58912 #define V_DQS_GATE_DELAY_N3(x) ((x) << S_DQS_GATE_DELAY_N3)
58913 #define G_DQS_GATE_DELAY_N3(x) (((x) >> S_DQS_GATE_DELAY_N3) & M_DQS_GATE_DELAY_N3)
58914 
58915 #define A_MC_DDRPHY_DP18_RD_STATUS0 0x44050
58916 
58917 #define S_NO_EYE_DETECTED    15
58918 #define V_NO_EYE_DETECTED(x) ((x) << S_NO_EYE_DETECTED)
58919 #define F_NO_EYE_DETECTED    V_NO_EYE_DETECTED(1U)
58920 
58921 #define S_LEADING_EDGE_FOUND    14
58922 #define V_LEADING_EDGE_FOUND(x) ((x) << S_LEADING_EDGE_FOUND)
58923 #define F_LEADING_EDGE_FOUND    V_LEADING_EDGE_FOUND(1U)
58924 
58925 #define S_TRAILING_EDGE_FOUND    13
58926 #define V_TRAILING_EDGE_FOUND(x) ((x) << S_TRAILING_EDGE_FOUND)
58927 #define F_TRAILING_EDGE_FOUND    V_TRAILING_EDGE_FOUND(1U)
58928 
58929 #define S_INCOMPLETE_RD_CAL_N0    12
58930 #define V_INCOMPLETE_RD_CAL_N0(x) ((x) << S_INCOMPLETE_RD_CAL_N0)
58931 #define F_INCOMPLETE_RD_CAL_N0    V_INCOMPLETE_RD_CAL_N0(1U)
58932 
58933 #define S_INCOMPLETE_RD_CAL_N1    11
58934 #define V_INCOMPLETE_RD_CAL_N1(x) ((x) << S_INCOMPLETE_RD_CAL_N1)
58935 #define F_INCOMPLETE_RD_CAL_N1    V_INCOMPLETE_RD_CAL_N1(1U)
58936 
58937 #define S_INCOMPLETE_RD_CAL_N2    10
58938 #define V_INCOMPLETE_RD_CAL_N2(x) ((x) << S_INCOMPLETE_RD_CAL_N2)
58939 #define F_INCOMPLETE_RD_CAL_N2    V_INCOMPLETE_RD_CAL_N2(1U)
58940 
58941 #define S_INCOMPLETE_RD_CAL_N3    9
58942 #define V_INCOMPLETE_RD_CAL_N3(x) ((x) << S_INCOMPLETE_RD_CAL_N3)
58943 #define F_INCOMPLETE_RD_CAL_N3    V_INCOMPLETE_RD_CAL_N3(1U)
58944 
58945 #define S_COARSE_PATTERN_ERR_N0    8
58946 #define V_COARSE_PATTERN_ERR_N0(x) ((x) << S_COARSE_PATTERN_ERR_N0)
58947 #define F_COARSE_PATTERN_ERR_N0    V_COARSE_PATTERN_ERR_N0(1U)
58948 
58949 #define S_COARSE_PATTERN_ERR_N1    7
58950 #define V_COARSE_PATTERN_ERR_N1(x) ((x) << S_COARSE_PATTERN_ERR_N1)
58951 #define F_COARSE_PATTERN_ERR_N1    V_COARSE_PATTERN_ERR_N1(1U)
58952 
58953 #define S_COARSE_PATTERN_ERR_N2    6
58954 #define V_COARSE_PATTERN_ERR_N2(x) ((x) << S_COARSE_PATTERN_ERR_N2)
58955 #define F_COARSE_PATTERN_ERR_N2    V_COARSE_PATTERN_ERR_N2(1U)
58956 
58957 #define S_COARSE_PATTERN_ERR_N3    5
58958 #define V_COARSE_PATTERN_ERR_N3(x) ((x) << S_COARSE_PATTERN_ERR_N3)
58959 #define F_COARSE_PATTERN_ERR_N3    V_COARSE_PATTERN_ERR_N3(1U)
58960 
58961 #define S_EYE_CLIPPING    4
58962 #define V_EYE_CLIPPING(x) ((x) << S_EYE_CLIPPING)
58963 #define F_EYE_CLIPPING    V_EYE_CLIPPING(1U)
58964 
58965 #define S_NO_DQS    3
58966 #define V_NO_DQS(x) ((x) << S_NO_DQS)
58967 #define F_NO_DQS    V_NO_DQS(1U)
58968 
58969 #define S_NO_LOCK    2
58970 #define V_NO_LOCK(x) ((x) << S_NO_LOCK)
58971 #define F_NO_LOCK    V_NO_LOCK(1U)
58972 
58973 #define S_DRIFT_ERROR    1
58974 #define V_DRIFT_ERROR(x) ((x) << S_DRIFT_ERROR)
58975 #define F_DRIFT_ERROR    V_DRIFT_ERROR(1U)
58976 
58977 #define S_MIN_EYE    0
58978 #define V_MIN_EYE(x) ((x) << S_MIN_EYE)
58979 #define F_MIN_EYE    V_MIN_EYE(1U)
58980 
58981 #define A_MC_DDRPHY_DP18_RD_ERROR_MASK0 0x44054
58982 
58983 #define S_NO_EYE_DETECTED_MASK    15
58984 #define V_NO_EYE_DETECTED_MASK(x) ((x) << S_NO_EYE_DETECTED_MASK)
58985 #define F_NO_EYE_DETECTED_MASK    V_NO_EYE_DETECTED_MASK(1U)
58986 
58987 #define S_LEADING_EDGE_FOUND_MASK    14
58988 #define V_LEADING_EDGE_FOUND_MASK(x) ((x) << S_LEADING_EDGE_FOUND_MASK)
58989 #define F_LEADING_EDGE_FOUND_MASK    V_LEADING_EDGE_FOUND_MASK(1U)
58990 
58991 #define S_TRAILING_EDGE_FOUND_MASK    13
58992 #define V_TRAILING_EDGE_FOUND_MASK(x) ((x) << S_TRAILING_EDGE_FOUND_MASK)
58993 #define F_TRAILING_EDGE_FOUND_MASK    V_TRAILING_EDGE_FOUND_MASK(1U)
58994 
58995 #define S_INCOMPLETE_RD_CAL_N0_MASK    12
58996 #define V_INCOMPLETE_RD_CAL_N0_MASK(x) ((x) << S_INCOMPLETE_RD_CAL_N0_MASK)
58997 #define F_INCOMPLETE_RD_CAL_N0_MASK    V_INCOMPLETE_RD_CAL_N0_MASK(1U)
58998 
58999 #define S_INCOMPLETE_RD_CAL_N1_MASK    11
59000 #define V_INCOMPLETE_RD_CAL_N1_MASK(x) ((x) << S_INCOMPLETE_RD_CAL_N1_MASK)
59001 #define F_INCOMPLETE_RD_CAL_N1_MASK    V_INCOMPLETE_RD_CAL_N1_MASK(1U)
59002 
59003 #define S_INCOMPLETE_RD_CAL_N2_MASK    10
59004 #define V_INCOMPLETE_RD_CAL_N2_MASK(x) ((x) << S_INCOMPLETE_RD_CAL_N2_MASK)
59005 #define F_INCOMPLETE_RD_CAL_N2_MASK    V_INCOMPLETE_RD_CAL_N2_MASK(1U)
59006 
59007 #define S_INCOMPLETE_RD_CAL_N3_MASK    9
59008 #define V_INCOMPLETE_RD_CAL_N3_MASK(x) ((x) << S_INCOMPLETE_RD_CAL_N3_MASK)
59009 #define F_INCOMPLETE_RD_CAL_N3_MASK    V_INCOMPLETE_RD_CAL_N3_MASK(1U)
59010 
59011 #define S_COARSE_PATTERN_ERR_N0_MASK    8
59012 #define V_COARSE_PATTERN_ERR_N0_MASK(x) ((x) << S_COARSE_PATTERN_ERR_N0_MASK)
59013 #define F_COARSE_PATTERN_ERR_N0_MASK    V_COARSE_PATTERN_ERR_N0_MASK(1U)
59014 
59015 #define S_COARSE_PATTERN_ERR_N1_MASK    7
59016 #define V_COARSE_PATTERN_ERR_N1_MASK(x) ((x) << S_COARSE_PATTERN_ERR_N1_MASK)
59017 #define F_COARSE_PATTERN_ERR_N1_MASK    V_COARSE_PATTERN_ERR_N1_MASK(1U)
59018 
59019 #define S_COARSE_PATTERN_ERR_N2_MASK    6
59020 #define V_COARSE_PATTERN_ERR_N2_MASK(x) ((x) << S_COARSE_PATTERN_ERR_N2_MASK)
59021 #define F_COARSE_PATTERN_ERR_N2_MASK    V_COARSE_PATTERN_ERR_N2_MASK(1U)
59022 
59023 #define S_COARSE_PATTERN_ERR_N3_MASK    5
59024 #define V_COARSE_PATTERN_ERR_N3_MASK(x) ((x) << S_COARSE_PATTERN_ERR_N3_MASK)
59025 #define F_COARSE_PATTERN_ERR_N3_MASK    V_COARSE_PATTERN_ERR_N3_MASK(1U)
59026 
59027 #define S_EYE_CLIPPING_MASK    4
59028 #define V_EYE_CLIPPING_MASK(x) ((x) << S_EYE_CLIPPING_MASK)
59029 #define F_EYE_CLIPPING_MASK    V_EYE_CLIPPING_MASK(1U)
59030 
59031 #define S_NO_DQS_MASK    3
59032 #define V_NO_DQS_MASK(x) ((x) << S_NO_DQS_MASK)
59033 #define F_NO_DQS_MASK    V_NO_DQS_MASK(1U)
59034 
59035 #define S_NO_LOCK_MASK    2
59036 #define V_NO_LOCK_MASK(x) ((x) << S_NO_LOCK_MASK)
59037 #define F_NO_LOCK_MASK    V_NO_LOCK_MASK(1U)
59038 
59039 #define S_DRIFT_ERROR_MASK    1
59040 #define V_DRIFT_ERROR_MASK(x) ((x) << S_DRIFT_ERROR_MASK)
59041 #define F_DRIFT_ERROR_MASK    V_DRIFT_ERROR_MASK(1U)
59042 
59043 #define S_MIN_EYE_MASK    0
59044 #define V_MIN_EYE_MASK(x) ((x) << S_MIN_EYE_MASK)
59045 #define F_MIN_EYE_MASK    V_MIN_EYE_MASK(1U)
59046 
59047 #define A_MC_DDRPHY_DP18_WRCLK_CNTL 0x44058
59048 
59049 #define S_PRBS_WAIT    14
59050 #define M_PRBS_WAIT    0x3U
59051 #define V_PRBS_WAIT(x) ((x) << S_PRBS_WAIT)
59052 #define G_PRBS_WAIT(x) (((x) >> S_PRBS_WAIT) & M_PRBS_WAIT)
59053 
59054 #define S_PRBS_SYNC_EARLY    13
59055 #define V_PRBS_SYNC_EARLY(x) ((x) << S_PRBS_SYNC_EARLY)
59056 #define F_PRBS_SYNC_EARLY    V_PRBS_SYNC_EARLY(1U)
59057 
59058 #define S_RD_DELAY_EARLY    12
59059 #define V_RD_DELAY_EARLY(x) ((x) << S_RD_DELAY_EARLY)
59060 #define F_RD_DELAY_EARLY    V_RD_DELAY_EARLY(1U)
59061 
59062 #define S_SS_QUAD_CAL    10
59063 #define V_SS_QUAD_CAL(x) ((x) << S_SS_QUAD_CAL)
59064 #define F_SS_QUAD_CAL    V_SS_QUAD_CAL(1U)
59065 
59066 #define S_SS_QUAD    8
59067 #define M_SS_QUAD    0x3U
59068 #define V_SS_QUAD(x) ((x) << S_SS_QUAD)
59069 #define G_SS_QUAD(x) (((x) >> S_SS_QUAD) & M_SS_QUAD)
59070 
59071 #define S_SS_RD_DELAY    7
59072 #define V_SS_RD_DELAY(x) ((x) << S_SS_RD_DELAY)
59073 #define F_SS_RD_DELAY    V_SS_RD_DELAY(1U)
59074 
59075 #define S_FORCE_HI_Z    6
59076 #define V_FORCE_HI_Z(x) ((x) << S_FORCE_HI_Z)
59077 #define F_FORCE_HI_Z    V_FORCE_HI_Z(1U)
59078 
59079 #define A_MC_DDRPHY_DP18_WR_LVL_STATUS0 0x4405c
59080 
59081 #define S_CLK_LEVEL    14
59082 #define M_CLK_LEVEL    0x3U
59083 #define V_CLK_LEVEL(x) ((x) << S_CLK_LEVEL)
59084 #define G_CLK_LEVEL(x) (((x) >> S_CLK_LEVEL) & M_CLK_LEVEL)
59085 
59086 #define S_FINE_STEPPING    13
59087 #define V_FINE_STEPPING(x) ((x) << S_FINE_STEPPING)
59088 #define F_FINE_STEPPING    V_FINE_STEPPING(1U)
59089 
59090 #define S_DONE    12
59091 #define V_DONE(x) ((x) << S_DONE)
59092 #define F_DONE    V_DONE(1U)
59093 
59094 #define S_WL_ERR_CLK16_ST    11
59095 #define V_WL_ERR_CLK16_ST(x) ((x) << S_WL_ERR_CLK16_ST)
59096 #define F_WL_ERR_CLK16_ST    V_WL_ERR_CLK16_ST(1U)
59097 
59098 #define S_WL_ERR_CLK18_ST    10
59099 #define V_WL_ERR_CLK18_ST(x) ((x) << S_WL_ERR_CLK18_ST)
59100 #define F_WL_ERR_CLK18_ST    V_WL_ERR_CLK18_ST(1U)
59101 
59102 #define S_WL_ERR_CLK20_ST    9
59103 #define V_WL_ERR_CLK20_ST(x) ((x) << S_WL_ERR_CLK20_ST)
59104 #define F_WL_ERR_CLK20_ST    V_WL_ERR_CLK20_ST(1U)
59105 
59106 #define S_WL_ERR_CLK22_ST    8
59107 #define V_WL_ERR_CLK22_ST(x) ((x) << S_WL_ERR_CLK22_ST)
59108 #define F_WL_ERR_CLK22_ST    V_WL_ERR_CLK22_ST(1U)
59109 
59110 #define S_ZERO_DETECTED    7
59111 #define V_ZERO_DETECTED(x) ((x) << S_ZERO_DETECTED)
59112 #define F_ZERO_DETECTED    V_ZERO_DETECTED(1U)
59113 
59114 #define S_WR_LVL_DONE    12
59115 #define V_WR_LVL_DONE(x) ((x) << S_WR_LVL_DONE)
59116 #define F_WR_LVL_DONE    V_WR_LVL_DONE(1U)
59117 
59118 #define A_MC_DDRPHY_DP18_WR_CNTR_STATUS0 0x44060
59119 
59120 #define S_BIT_CENTERED    11
59121 #define M_BIT_CENTERED    0x1fU
59122 #define V_BIT_CENTERED(x) ((x) << S_BIT_CENTERED)
59123 #define G_BIT_CENTERED(x) (((x) >> S_BIT_CENTERED) & M_BIT_CENTERED)
59124 
59125 #define S_SMALL_STEP_LEFT    10
59126 #define V_SMALL_STEP_LEFT(x) ((x) << S_SMALL_STEP_LEFT)
59127 #define F_SMALL_STEP_LEFT    V_SMALL_STEP_LEFT(1U)
59128 
59129 #define S_BIG_STEP_RIGHT    9
59130 #define V_BIG_STEP_RIGHT(x) ((x) << S_BIG_STEP_RIGHT)
59131 #define F_BIG_STEP_RIGHT    V_BIG_STEP_RIGHT(1U)
59132 
59133 #define S_MATCH_STEP_RIGHT    8
59134 #define V_MATCH_STEP_RIGHT(x) ((x) << S_MATCH_STEP_RIGHT)
59135 #define F_MATCH_STEP_RIGHT    V_MATCH_STEP_RIGHT(1U)
59136 
59137 #define S_JUMP_BACK_RIGHT    7
59138 #define V_JUMP_BACK_RIGHT(x) ((x) << S_JUMP_BACK_RIGHT)
59139 #define F_JUMP_BACK_RIGHT    V_JUMP_BACK_RIGHT(1U)
59140 
59141 #define S_SMALL_STEP_RIGHT    6
59142 #define V_SMALL_STEP_RIGHT(x) ((x) << S_SMALL_STEP_RIGHT)
59143 #define F_SMALL_STEP_RIGHT    V_SMALL_STEP_RIGHT(1U)
59144 
59145 #define S_DDONE    5
59146 #define V_DDONE(x) ((x) << S_DDONE)
59147 #define F_DDONE    V_DDONE(1U)
59148 
59149 #define S_WR_CNTR_DONE    5
59150 #define V_WR_CNTR_DONE(x) ((x) << S_WR_CNTR_DONE)
59151 #define F_WR_CNTR_DONE    V_WR_CNTR_DONE(1U)
59152 
59153 #define A_MC_DDRPHY_DP18_WR_CNTR_STATUS1 0x44064
59154 
59155 #define S_FW_LEFT_SIDE    5
59156 #define M_FW_LEFT_SIDE    0x7ffU
59157 #define V_FW_LEFT_SIDE(x) ((x) << S_FW_LEFT_SIDE)
59158 #define G_FW_LEFT_SIDE(x) (((x) >> S_FW_LEFT_SIDE) & M_FW_LEFT_SIDE)
59159 
59160 #define A_MC_DDRPHY_DP18_WR_CNTR_STATUS2 0x44068
59161 
59162 #define S_FW_RIGHT_SIDE    5
59163 #define M_FW_RIGHT_SIDE    0x7ffU
59164 #define V_FW_RIGHT_SIDE(x) ((x) << S_FW_RIGHT_SIDE)
59165 #define G_FW_RIGHT_SIDE(x) (((x) >> S_FW_RIGHT_SIDE) & M_FW_RIGHT_SIDE)
59166 
59167 #define A_MC_DDRPHY_DP18_WR_ERROR0 0x4406c
59168 
59169 #define S_WL_ERR_CLK16    15
59170 #define V_WL_ERR_CLK16(x) ((x) << S_WL_ERR_CLK16)
59171 #define F_WL_ERR_CLK16    V_WL_ERR_CLK16(1U)
59172 
59173 #define S_WL_ERR_CLK18    14
59174 #define V_WL_ERR_CLK18(x) ((x) << S_WL_ERR_CLK18)
59175 #define F_WL_ERR_CLK18    V_WL_ERR_CLK18(1U)
59176 
59177 #define S_WL_ERR_CLK20    13
59178 #define V_WL_ERR_CLK20(x) ((x) << S_WL_ERR_CLK20)
59179 #define F_WL_ERR_CLK20    V_WL_ERR_CLK20(1U)
59180 
59181 #define S_WL_ERR_CLK22    12
59182 #define V_WL_ERR_CLK22(x) ((x) << S_WL_ERR_CLK22)
59183 #define F_WL_ERR_CLK22    V_WL_ERR_CLK22(1U)
59184 
59185 #define S_VALID_NS_BIG_L    7
59186 #define V_VALID_NS_BIG_L(x) ((x) << S_VALID_NS_BIG_L)
59187 #define F_VALID_NS_BIG_L    V_VALID_NS_BIG_L(1U)
59188 
59189 #define S_INVALID_NS_SMALL_L    6
59190 #define V_INVALID_NS_SMALL_L(x) ((x) << S_INVALID_NS_SMALL_L)
59191 #define F_INVALID_NS_SMALL_L    V_INVALID_NS_SMALL_L(1U)
59192 
59193 #define S_VALID_NS_BIG_R    5
59194 #define V_VALID_NS_BIG_R(x) ((x) << S_VALID_NS_BIG_R)
59195 #define F_VALID_NS_BIG_R    V_VALID_NS_BIG_R(1U)
59196 
59197 #define S_INVALID_NS_BIG_R    4
59198 #define V_INVALID_NS_BIG_R(x) ((x) << S_INVALID_NS_BIG_R)
59199 #define F_INVALID_NS_BIG_R    V_INVALID_NS_BIG_R(1U)
59200 
59201 #define S_VALID_NS_JUMP_BACK    3
59202 #define V_VALID_NS_JUMP_BACK(x) ((x) << S_VALID_NS_JUMP_BACK)
59203 #define F_VALID_NS_JUMP_BACK    V_VALID_NS_JUMP_BACK(1U)
59204 
59205 #define S_INVALID_NS_SMALL_R    2
59206 #define V_INVALID_NS_SMALL_R(x) ((x) << S_INVALID_NS_SMALL_R)
59207 #define F_INVALID_NS_SMALL_R    V_INVALID_NS_SMALL_R(1U)
59208 
59209 #define S_OFFSET_ERR    1
59210 #define V_OFFSET_ERR(x) ((x) << S_OFFSET_ERR)
59211 #define F_OFFSET_ERR    V_OFFSET_ERR(1U)
59212 
59213 #define A_MC_DDRPHY_DP18_WR_ERROR_MASK0 0x44070
59214 
59215 #define S_WL_ERR_CLK16_MASK    15
59216 #define V_WL_ERR_CLK16_MASK(x) ((x) << S_WL_ERR_CLK16_MASK)
59217 #define F_WL_ERR_CLK16_MASK    V_WL_ERR_CLK16_MASK(1U)
59218 
59219 #define S_WL_ERR_CLK18_MASK    14
59220 #define V_WL_ERR_CLK18_MASK(x) ((x) << S_WL_ERR_CLK18_MASK)
59221 #define F_WL_ERR_CLK18_MASK    V_WL_ERR_CLK18_MASK(1U)
59222 
59223 #define S_WL_ERR_CLK20_MASK    13
59224 #define V_WL_ERR_CLK20_MASK(x) ((x) << S_WL_ERR_CLK20_MASK)
59225 #define F_WL_ERR_CLK20_MASK    V_WL_ERR_CLK20_MASK(1U)
59226 
59227 #define S_WR_ERR_CLK22_MASK    12
59228 #define V_WR_ERR_CLK22_MASK(x) ((x) << S_WR_ERR_CLK22_MASK)
59229 #define F_WR_ERR_CLK22_MASK    V_WR_ERR_CLK22_MASK(1U)
59230 
59231 #define S_VALID_NS_BIG_L_MASK    7
59232 #define V_VALID_NS_BIG_L_MASK(x) ((x) << S_VALID_NS_BIG_L_MASK)
59233 #define F_VALID_NS_BIG_L_MASK    V_VALID_NS_BIG_L_MASK(1U)
59234 
59235 #define S_INVALID_NS_SMALL_L_MASK    6
59236 #define V_INVALID_NS_SMALL_L_MASK(x) ((x) << S_INVALID_NS_SMALL_L_MASK)
59237 #define F_INVALID_NS_SMALL_L_MASK    V_INVALID_NS_SMALL_L_MASK(1U)
59238 
59239 #define S_VALID_NS_BIG_R_MASK    5
59240 #define V_VALID_NS_BIG_R_MASK(x) ((x) << S_VALID_NS_BIG_R_MASK)
59241 #define F_VALID_NS_BIG_R_MASK    V_VALID_NS_BIG_R_MASK(1U)
59242 
59243 #define S_INVALID_NS_BIG_R_MASK    4
59244 #define V_INVALID_NS_BIG_R_MASK(x) ((x) << S_INVALID_NS_BIG_R_MASK)
59245 #define F_INVALID_NS_BIG_R_MASK    V_INVALID_NS_BIG_R_MASK(1U)
59246 
59247 #define S_VALID_NS_JUMP_BACK_MASK    3
59248 #define V_VALID_NS_JUMP_BACK_MASK(x) ((x) << S_VALID_NS_JUMP_BACK_MASK)
59249 #define F_VALID_NS_JUMP_BACK_MASK    V_VALID_NS_JUMP_BACK_MASK(1U)
59250 
59251 #define S_INVALID_NS_SMALL_R_MASK    2
59252 #define V_INVALID_NS_SMALL_R_MASK(x) ((x) << S_INVALID_NS_SMALL_R_MASK)
59253 #define F_INVALID_NS_SMALL_R_MASK    V_INVALID_NS_SMALL_R_MASK(1U)
59254 
59255 #define S_OFFSET_ERR_MASK    1
59256 #define V_OFFSET_ERR_MASK(x) ((x) << S_OFFSET_ERR_MASK)
59257 #define F_OFFSET_ERR_MASK    V_OFFSET_ERR_MASK(1U)
59258 
59259 #define S_DQS_REC_LOW_POWER    11
59260 #define V_DQS_REC_LOW_POWER(x) ((x) << S_DQS_REC_LOW_POWER)
59261 #define F_DQS_REC_LOW_POWER    V_DQS_REC_LOW_POWER(1U)
59262 
59263 #define S_DQ_REC_LOW_POWER    10
59264 #define V_DQ_REC_LOW_POWER(x) ((x) << S_DQ_REC_LOW_POWER)
59265 #define F_DQ_REC_LOW_POWER    V_DQ_REC_LOW_POWER(1U)
59266 
59267 #define S_ADVANCE_PR_VALUE    0
59268 #define V_ADVANCE_PR_VALUE(x) ((x) << S_ADVANCE_PR_VALUE)
59269 #define F_ADVANCE_PR_VALUE    V_ADVANCE_PR_VALUE(1U)
59270 
59271 #define A_MC_DDRPHY_DP18_DFT_WRAP_STATUS 0x44074
59272 
59273 #define S_CHECKER_RESET    14
59274 #define V_CHECKER_RESET(x) ((x) << S_CHECKER_RESET)
59275 #define F_CHECKER_RESET    V_CHECKER_RESET(1U)
59276 
59277 #define S_DP18_DFT_SYNC    6
59278 #define M_DP18_DFT_SYNC    0x3fU
59279 #define V_DP18_DFT_SYNC(x) ((x) << S_DP18_DFT_SYNC)
59280 #define G_DP18_DFT_SYNC(x) (((x) >> S_DP18_DFT_SYNC) & M_DP18_DFT_SYNC)
59281 
59282 #define S_ERROR    0
59283 #define M_ERROR    0x3fU
59284 #define V_ERROR(x) ((x) << S_ERROR)
59285 #define G_ERROR(x) (((x) >> S_ERROR) & M_ERROR)
59286 
59287 #define S_CHECKER_ENABLE    15
59288 #define V_CHECKER_ENABLE(x) ((x) << S_CHECKER_ENABLE)
59289 #define F_CHECKER_ENABLE    V_CHECKER_ENABLE(1U)
59290 
59291 #define S_DP18_DFT_ERROR    0
59292 #define M_DP18_DFT_ERROR    0x3fU
59293 #define V_DP18_DFT_ERROR(x) ((x) << S_DP18_DFT_ERROR)
59294 #define G_DP18_DFT_ERROR(x) (((x) >> S_DP18_DFT_ERROR) & M_DP18_DFT_ERROR)
59295 
59296 #define A_MC_DDRPHY_DP18_RD_DIA_CONFIG0 0x44078
59297 
59298 #define S_SYSCLK_RDCLK_OFFSET    8
59299 #define M_SYSCLK_RDCLK_OFFSET    0x7fU
59300 #define V_SYSCLK_RDCLK_OFFSET(x) ((x) << S_SYSCLK_RDCLK_OFFSET)
59301 #define G_SYSCLK_RDCLK_OFFSET(x) (((x) >> S_SYSCLK_RDCLK_OFFSET) & M_SYSCLK_RDCLK_OFFSET)
59302 
59303 #define S_SYSCLK_DQSCLK_OFFSET    0
59304 #define M_SYSCLK_DQSCLK_OFFSET    0x7fU
59305 #define V_SYSCLK_DQSCLK_OFFSET(x) ((x) << S_SYSCLK_DQSCLK_OFFSET)
59306 #define G_SYSCLK_DQSCLK_OFFSET(x) (((x) >> S_SYSCLK_DQSCLK_OFFSET) & M_SYSCLK_DQSCLK_OFFSET)
59307 
59308 #define S_T6_SYSCLK_DQSCLK_OFFSET    8
59309 #define M_T6_SYSCLK_DQSCLK_OFFSET    0x7fU
59310 #define V_T6_SYSCLK_DQSCLK_OFFSET(x) ((x) << S_T6_SYSCLK_DQSCLK_OFFSET)
59311 #define G_T6_SYSCLK_DQSCLK_OFFSET(x) (((x) >> S_T6_SYSCLK_DQSCLK_OFFSET) & M_T6_SYSCLK_DQSCLK_OFFSET)
59312 
59313 #define S_T6_SYSCLK_RDCLK_OFFSET    0
59314 #define M_T6_SYSCLK_RDCLK_OFFSET    0x7fU
59315 #define V_T6_SYSCLK_RDCLK_OFFSET(x) ((x) << S_T6_SYSCLK_RDCLK_OFFSET)
59316 #define G_T6_SYSCLK_RDCLK_OFFSET(x) (((x) >> S_T6_SYSCLK_RDCLK_OFFSET) & M_T6_SYSCLK_RDCLK_OFFSET)
59317 
59318 #define A_MC_DDRPHY_DP18_WRCLK_AUX_CNTL 0x4407c
59319 #define A_MC_DDRPHY_DP18_DQSCLK_PR0_RANK_PAIR 0x440c0
59320 
59321 #define S_DQSCLK_ROT_CLK_N0_N2    8
59322 #define M_DQSCLK_ROT_CLK_N0_N2    0x7fU
59323 #define V_DQSCLK_ROT_CLK_N0_N2(x) ((x) << S_DQSCLK_ROT_CLK_N0_N2)
59324 #define G_DQSCLK_ROT_CLK_N0_N2(x) (((x) >> S_DQSCLK_ROT_CLK_N0_N2) & M_DQSCLK_ROT_CLK_N0_N2)
59325 
59326 #define S_DQSCLK_ROT_CLK_N1_N3    0
59327 #define M_DQSCLK_ROT_CLK_N1_N3    0x7fU
59328 #define V_DQSCLK_ROT_CLK_N1_N3(x) ((x) << S_DQSCLK_ROT_CLK_N1_N3)
59329 #define G_DQSCLK_ROT_CLK_N1_N3(x) (((x) >> S_DQSCLK_ROT_CLK_N1_N3) & M_DQSCLK_ROT_CLK_N1_N3)
59330 
59331 #define A_MC_DDRPHY_DP18_DQSCLK_PR1_RANK_PAIR 0x440c4
59332 #define A_MC_DDRPHY_DP18_PATTERN_POS_0 0x440c8
59333 
59334 #define S_MEMINTD00_POS    14
59335 #define M_MEMINTD00_POS    0x3U
59336 #define V_MEMINTD00_POS(x) ((x) << S_MEMINTD00_POS)
59337 #define G_MEMINTD00_POS(x) (((x) >> S_MEMINTD00_POS) & M_MEMINTD00_POS)
59338 
59339 #define S_MEMINTD01_PO    12
59340 #define M_MEMINTD01_PO    0x3U
59341 #define V_MEMINTD01_PO(x) ((x) << S_MEMINTD01_PO)
59342 #define G_MEMINTD01_PO(x) (((x) >> S_MEMINTD01_PO) & M_MEMINTD01_PO)
59343 
59344 #define S_MEMINTD02_POS    10
59345 #define M_MEMINTD02_POS    0x3U
59346 #define V_MEMINTD02_POS(x) ((x) << S_MEMINTD02_POS)
59347 #define G_MEMINTD02_POS(x) (((x) >> S_MEMINTD02_POS) & M_MEMINTD02_POS)
59348 
59349 #define S_MEMINTD03_POS    8
59350 #define M_MEMINTD03_POS    0x3U
59351 #define V_MEMINTD03_POS(x) ((x) << S_MEMINTD03_POS)
59352 #define G_MEMINTD03_POS(x) (((x) >> S_MEMINTD03_POS) & M_MEMINTD03_POS)
59353 
59354 #define S_MEMINTD04_POS    6
59355 #define M_MEMINTD04_POS    0x3U
59356 #define V_MEMINTD04_POS(x) ((x) << S_MEMINTD04_POS)
59357 #define G_MEMINTD04_POS(x) (((x) >> S_MEMINTD04_POS) & M_MEMINTD04_POS)
59358 
59359 #define S_MEMINTD05_POS    4
59360 #define M_MEMINTD05_POS    0x3U
59361 #define V_MEMINTD05_POS(x) ((x) << S_MEMINTD05_POS)
59362 #define G_MEMINTD05_POS(x) (((x) >> S_MEMINTD05_POS) & M_MEMINTD05_POS)
59363 
59364 #define S_MEMINTD06_POS    2
59365 #define M_MEMINTD06_POS    0x3U
59366 #define V_MEMINTD06_POS(x) ((x) << S_MEMINTD06_POS)
59367 #define G_MEMINTD06_POS(x) (((x) >> S_MEMINTD06_POS) & M_MEMINTD06_POS)
59368 
59369 #define S_MEMINTD07_POS    0
59370 #define M_MEMINTD07_POS    0x3U
59371 #define V_MEMINTD07_POS(x) ((x) << S_MEMINTD07_POS)
59372 #define G_MEMINTD07_POS(x) (((x) >> S_MEMINTD07_POS) & M_MEMINTD07_POS)
59373 
59374 #define A_MC_DDRPHY_DP18_PATTERN_POS_1 0x440cc
59375 
59376 #define S_MEMINTD08_POS    14
59377 #define M_MEMINTD08_POS    0x3U
59378 #define V_MEMINTD08_POS(x) ((x) << S_MEMINTD08_POS)
59379 #define G_MEMINTD08_POS(x) (((x) >> S_MEMINTD08_POS) & M_MEMINTD08_POS)
59380 
59381 #define S_MEMINTD09_POS    12
59382 #define M_MEMINTD09_POS    0x3U
59383 #define V_MEMINTD09_POS(x) ((x) << S_MEMINTD09_POS)
59384 #define G_MEMINTD09_POS(x) (((x) >> S_MEMINTD09_POS) & M_MEMINTD09_POS)
59385 
59386 #define S_MEMINTD10_POS    10
59387 #define M_MEMINTD10_POS    0x3U
59388 #define V_MEMINTD10_POS(x) ((x) << S_MEMINTD10_POS)
59389 #define G_MEMINTD10_POS(x) (((x) >> S_MEMINTD10_POS) & M_MEMINTD10_POS)
59390 
59391 #define S_MEMINTD11_POS    8
59392 #define M_MEMINTD11_POS    0x3U
59393 #define V_MEMINTD11_POS(x) ((x) << S_MEMINTD11_POS)
59394 #define G_MEMINTD11_POS(x) (((x) >> S_MEMINTD11_POS) & M_MEMINTD11_POS)
59395 
59396 #define S_MEMINTD12_POS    6
59397 #define M_MEMINTD12_POS    0x3U
59398 #define V_MEMINTD12_POS(x) ((x) << S_MEMINTD12_POS)
59399 #define G_MEMINTD12_POS(x) (((x) >> S_MEMINTD12_POS) & M_MEMINTD12_POS)
59400 
59401 #define S_MEMINTD13_POS    4
59402 #define M_MEMINTD13_POS    0x3U
59403 #define V_MEMINTD13_POS(x) ((x) << S_MEMINTD13_POS)
59404 #define G_MEMINTD13_POS(x) (((x) >> S_MEMINTD13_POS) & M_MEMINTD13_POS)
59405 
59406 #define S_MEMINTD14_POS    2
59407 #define M_MEMINTD14_POS    0x3U
59408 #define V_MEMINTD14_POS(x) ((x) << S_MEMINTD14_POS)
59409 #define G_MEMINTD14_POS(x) (((x) >> S_MEMINTD14_POS) & M_MEMINTD14_POS)
59410 
59411 #define S_MEMINTD15_POS    0
59412 #define M_MEMINTD15_POS    0x3U
59413 #define V_MEMINTD15_POS(x) ((x) << S_MEMINTD15_POS)
59414 #define G_MEMINTD15_POS(x) (((x) >> S_MEMINTD15_POS) & M_MEMINTD15_POS)
59415 
59416 #define A_MC_DDRPHY_DP18_PATTERN_POS_2 0x440d0
59417 
59418 #define S_MEMINTD16_POS    14
59419 #define M_MEMINTD16_POS    0x3U
59420 #define V_MEMINTD16_POS(x) ((x) << S_MEMINTD16_POS)
59421 #define G_MEMINTD16_POS(x) (((x) >> S_MEMINTD16_POS) & M_MEMINTD16_POS)
59422 
59423 #define S_MEMINTD17_POS    12
59424 #define M_MEMINTD17_POS    0x3U
59425 #define V_MEMINTD17_POS(x) ((x) << S_MEMINTD17_POS)
59426 #define G_MEMINTD17_POS(x) (((x) >> S_MEMINTD17_POS) & M_MEMINTD17_POS)
59427 
59428 #define S_MEMINTD18_POS    10
59429 #define M_MEMINTD18_POS    0x3U
59430 #define V_MEMINTD18_POS(x) ((x) << S_MEMINTD18_POS)
59431 #define G_MEMINTD18_POS(x) (((x) >> S_MEMINTD18_POS) & M_MEMINTD18_POS)
59432 
59433 #define S_MEMINTD19_POS    8
59434 #define M_MEMINTD19_POS    0x3U
59435 #define V_MEMINTD19_POS(x) ((x) << S_MEMINTD19_POS)
59436 #define G_MEMINTD19_POS(x) (((x) >> S_MEMINTD19_POS) & M_MEMINTD19_POS)
59437 
59438 #define S_MEMINTD20_POS    6
59439 #define M_MEMINTD20_POS    0x3U
59440 #define V_MEMINTD20_POS(x) ((x) << S_MEMINTD20_POS)
59441 #define G_MEMINTD20_POS(x) (((x) >> S_MEMINTD20_POS) & M_MEMINTD20_POS)
59442 
59443 #define S_MEMINTD21_POS    4
59444 #define M_MEMINTD21_POS    0x3U
59445 #define V_MEMINTD21_POS(x) ((x) << S_MEMINTD21_POS)
59446 #define G_MEMINTD21_POS(x) (((x) >> S_MEMINTD21_POS) & M_MEMINTD21_POS)
59447 
59448 #define S_MEMINTD22_POS    2
59449 #define M_MEMINTD22_POS    0x3U
59450 #define V_MEMINTD22_POS(x) ((x) << S_MEMINTD22_POS)
59451 #define G_MEMINTD22_POS(x) (((x) >> S_MEMINTD22_POS) & M_MEMINTD22_POS)
59452 
59453 #define S_MEMINTD23_POS    0
59454 #define M_MEMINTD23_POS    0x3U
59455 #define V_MEMINTD23_POS(x) ((x) << S_MEMINTD23_POS)
59456 #define G_MEMINTD23_POS(x) (((x) >> S_MEMINTD23_POS) & M_MEMINTD23_POS)
59457 
59458 #define A_MC_DDRPHY_DP18_RD_DIA_CONFIG1 0x440d4
59459 
59460 #define S_DQS_ALIGN_SM    11
59461 #define M_DQS_ALIGN_SM    0x1fU
59462 #define V_DQS_ALIGN_SM(x) ((x) << S_DQS_ALIGN_SM)
59463 #define G_DQS_ALIGN_SM(x) (((x) >> S_DQS_ALIGN_SM) & M_DQS_ALIGN_SM)
59464 
59465 #define S_DQS_ALIGN_CNTR    7
59466 #define M_DQS_ALIGN_CNTR    0xfU
59467 #define V_DQS_ALIGN_CNTR(x) ((x) << S_DQS_ALIGN_CNTR)
59468 #define G_DQS_ALIGN_CNTR(x) (((x) >> S_DQS_ALIGN_CNTR) & M_DQS_ALIGN_CNTR)
59469 
59470 #define S_ITERATION_CNTR    6
59471 #define V_ITERATION_CNTR(x) ((x) << S_ITERATION_CNTR)
59472 #define F_ITERATION_CNTR    V_ITERATION_CNTR(1U)
59473 
59474 #define S_DQS_ALIGN_ITER_CNTR    0
59475 #define M_DQS_ALIGN_ITER_CNTR    0x3fU
59476 #define V_DQS_ALIGN_ITER_CNTR(x) ((x) << S_DQS_ALIGN_ITER_CNTR)
59477 #define G_DQS_ALIGN_ITER_CNTR(x) (((x) >> S_DQS_ALIGN_ITER_CNTR) & M_DQS_ALIGN_ITER_CNTR)
59478 
59479 #define A_MC_DDRPHY_DP18_RD_DIA_CONFIG2 0x440d8
59480 
59481 #define S_CALIBRATE_BIT    13
59482 #define M_CALIBRATE_BIT    0x7U
59483 #define V_CALIBRATE_BIT(x) ((x) << S_CALIBRATE_BIT)
59484 #define G_CALIBRATE_BIT(x) (((x) >> S_CALIBRATE_BIT) & M_CALIBRATE_BIT)
59485 
59486 #define S_DQS_ALIGN_QUAD    11
59487 #define M_DQS_ALIGN_QUAD    0x3U
59488 #define V_DQS_ALIGN_QUAD(x) ((x) << S_DQS_ALIGN_QUAD)
59489 #define G_DQS_ALIGN_QUAD(x) (((x) >> S_DQS_ALIGN_QUAD) & M_DQS_ALIGN_QUAD)
59490 
59491 #define S_DQS_QUAD_CONFIG    8
59492 #define M_DQS_QUAD_CONFIG    0x7U
59493 #define V_DQS_QUAD_CONFIG(x) ((x) << S_DQS_QUAD_CONFIG)
59494 #define G_DQS_QUAD_CONFIG(x) (((x) >> S_DQS_QUAD_CONFIG) & M_DQS_QUAD_CONFIG)
59495 
59496 #define S_OPERATE_MODE    4
59497 #define M_OPERATE_MODE    0xfU
59498 #define V_OPERATE_MODE(x) ((x) << S_OPERATE_MODE)
59499 #define G_OPERATE_MODE(x) (((x) >> S_OPERATE_MODE) & M_OPERATE_MODE)
59500 
59501 #define S_EN_DQS_OFFSET    3
59502 #define V_EN_DQS_OFFSET(x) ((x) << S_EN_DQS_OFFSET)
59503 #define F_EN_DQS_OFFSET    V_EN_DQS_OFFSET(1U)
59504 
59505 #define S_DQS_ALIGN_JITTER    2
59506 #define V_DQS_ALIGN_JITTER(x) ((x) << S_DQS_ALIGN_JITTER)
59507 #define F_DQS_ALIGN_JITTER    V_DQS_ALIGN_JITTER(1U)
59508 
59509 #define S_DIS_CLK_GATE    1
59510 #define V_DIS_CLK_GATE(x) ((x) << S_DIS_CLK_GATE)
59511 #define F_DIS_CLK_GATE    V_DIS_CLK_GATE(1U)
59512 
59513 #define S_MAX_DQS_ITER    0
59514 #define V_MAX_DQS_ITER(x) ((x) << S_MAX_DQS_ITER)
59515 #define F_MAX_DQS_ITER    V_MAX_DQS_ITER(1U)
59516 
59517 #define A_MC_DDRPHY_DP18_DQSCLK_OFFSET 0x440dc
59518 
59519 #define S_DQS_OFFSET    8
59520 #define M_DQS_OFFSET    0x7fU
59521 #define V_DQS_OFFSET(x) ((x) << S_DQS_OFFSET)
59522 #define G_DQS_OFFSET(x) (((x) >> S_DQS_OFFSET) & M_DQS_OFFSET)
59523 
59524 #define A_MC_DDRPHY_DP18_WR_DELAY_VALUE_0_RP 0x440e0
59525 
59526 #define S_WR_DELAY    6
59527 #define M_WR_DELAY    0x3ffU
59528 #define V_WR_DELAY(x) ((x) << S_WR_DELAY)
59529 #define G_WR_DELAY(x) (((x) >> S_WR_DELAY) & M_WR_DELAY)
59530 
59531 #define A_MC_DDRPHY_DP18_WR_DELAY_VALUE_1_RP 0x440e4
59532 #define A_MC_DDRPHY_DP18_WR_DELAY_VALUE_2_RP 0x440e8
59533 #define A_MC_DDRPHY_DP18_WR_DELAY_VALUE_3_RP 0x440ec
59534 #define A_MC_DDRPHY_DP18_WR_DELAY_VALUE_4_RP 0x440f0
59535 #define A_MC_DDRPHY_DP18_WR_DELAY_VALUE_5_RP 0x440f4
59536 #define A_MC_DDRPHY_DP18_WR_DELAY_VALUE_6_RP 0x440f8
59537 #define A_MC_DDRPHY_DP18_WR_DELAY_VALUE_7_RP 0x440fc
59538 #define A_MC_DDRPHY_DP18_WR_DELAY_VALUE_8_RP 0x44100
59539 #define A_MC_DDRPHY_DP18_WR_DELAY_VALUE_9_RP 0x44104
59540 #define A_MC_DDRPHY_DP18_WR_DELAY_VALUE_10_RP 0x44108
59541 #define A_MC_DDRPHY_DP18_WR_DELAY_VALUE_11_RP 0x4410c
59542 #define A_MC_DDRPHY_DP18_WR_DELAY_VALUE_12_RP 0x44110
59543 #define A_MC_DDRPHY_DP18_WR_DELAY_VALUE_13_RP 0x44114
59544 #define A_MC_DDRPHY_DP18_WR_DELAY_VALUE_14_RP 0x44118
59545 #define A_MC_DDRPHY_DP18_WR_DELAY_VALUE_15_RP 0x4411c
59546 #define A_MC_DDRPHY_DP18_WR_DELAY_VALUE_16_RP 0x44120
59547 #define A_MC_DDRPHY_DP18_WR_DELAY_VALUE_17_RP 0x44124
59548 #define A_MC_DDRPHY_DP18_WR_DELAY_VALUE_18_RP 0x44128
59549 #define A_MC_DDRPHY_DP18_WR_DELAY_VALUE_19_RP 0x4412c
59550 #define A_MC_DDRPHY_DP18_WR_DELAY_VALUE_20_RP 0x44130
59551 #define A_MC_DDRPHY_DP18_WR_DELAY_VALUE_21_RP 0x44134
59552 #define A_MC_DDRPHY_DP18_WR_DELAY_VALUE_22_RP 0x44138
59553 #define A_MC_DDRPHY_DP18_WR_DELAY_VALUE_23_RP 0x4413c
59554 #define A_MC_DDRPHY_DP18_READ_DELAY0_RANK_PAIR 0x44140
59555 
59556 #define S_RD_DELAY_BITS0_6    9
59557 #define M_RD_DELAY_BITS0_6    0x7fU
59558 #define V_RD_DELAY_BITS0_6(x) ((x) << S_RD_DELAY_BITS0_6)
59559 #define G_RD_DELAY_BITS0_6(x) (((x) >> S_RD_DELAY_BITS0_6) & M_RD_DELAY_BITS0_6)
59560 
59561 #define S_RD_DELAY_BITS8_14    1
59562 #define M_RD_DELAY_BITS8_14    0x7fU
59563 #define V_RD_DELAY_BITS8_14(x) ((x) << S_RD_DELAY_BITS8_14)
59564 #define G_RD_DELAY_BITS8_14(x) (((x) >> S_RD_DELAY_BITS8_14) & M_RD_DELAY_BITS8_14)
59565 
59566 #define A_MC_DDRPHY_DP18_READ_DELAY1_RANK_PAIR 0x44144
59567 #define A_MC_DDRPHY_DP18_READ_DELAY2_RANK_PAIR 0x44148
59568 #define A_MC_DDRPHY_DP18_READ_DELAY3_RANK_PAIR 0x4414c
59569 #define A_MC_DDRPHY_DP18_READ_DELAY4_RANK_PAIR 0x44150
59570 #define A_MC_DDRPHY_DP18_READ_DELAY5_RANK_PAIR 0x44154
59571 #define A_MC_DDRPHY_DP18_READ_DELAY6_RANK_PAIR 0x44158
59572 #define A_MC_DDRPHY_DP18_READ_DELAY7_RANK_PAIR 0x4415c
59573 #define A_MC_DDRPHY_DP18_READ_DELAY8_RANK_PAIR 0x44160
59574 #define A_MC_DDRPHY_DP18_READ_DELAY9_RANK_PAIR 0x44164
59575 #define A_MC_DDRPHY_DP18_READ_DELAY10_RANK_PAIR 0x44168
59576 #define A_MC_DDRPHY_DP18_READ_DELAY11_RANK_PAIR 0x4416c
59577 #define A_MC_DDRPHY_DP18_INITIAL_DQS_ALIGN0_RANK_PAIR 0x44170
59578 
59579 #define S_INITIAL_DQS_ROT_N0_N2    8
59580 #define M_INITIAL_DQS_ROT_N0_N2    0x7fU
59581 #define V_INITIAL_DQS_ROT_N0_N2(x) ((x) << S_INITIAL_DQS_ROT_N0_N2)
59582 #define G_INITIAL_DQS_ROT_N0_N2(x) (((x) >> S_INITIAL_DQS_ROT_N0_N2) & M_INITIAL_DQS_ROT_N0_N2)
59583 
59584 #define S_INITIAL_DQS_ROT_N1_N3    0
59585 #define M_INITIAL_DQS_ROT_N1_N3    0x7fU
59586 #define V_INITIAL_DQS_ROT_N1_N3(x) ((x) << S_INITIAL_DQS_ROT_N1_N3)
59587 #define G_INITIAL_DQS_ROT_N1_N3(x) (((x) >> S_INITIAL_DQS_ROT_N1_N3) & M_INITIAL_DQS_ROT_N1_N3)
59588 
59589 #define A_MC_DDRPHY_DP18_INITIAL_DQS_ALIGN1_RANK_PAIR 0x44174
59590 #define A_MC_DDRPHY_DP18_WRCLK_STATUS 0x44178
59591 
59592 #define S_WRCLK_CALIB_DONE    15
59593 #define V_WRCLK_CALIB_DONE(x) ((x) << S_WRCLK_CALIB_DONE)
59594 #define F_WRCLK_CALIB_DONE    V_WRCLK_CALIB_DONE(1U)
59595 
59596 #define S_VALUE_UPDATED    14
59597 #define V_VALUE_UPDATED(x) ((x) << S_VALUE_UPDATED)
59598 #define F_VALUE_UPDATED    V_VALUE_UPDATED(1U)
59599 
59600 #define S_FAIL_PASS_V    13
59601 #define V_FAIL_PASS_V(x) ((x) << S_FAIL_PASS_V)
59602 #define F_FAIL_PASS_V    V_FAIL_PASS_V(1U)
59603 
59604 #define S_PASS_FAIL_V    12
59605 #define V_PASS_FAIL_V(x) ((x) << S_PASS_FAIL_V)
59606 #define F_PASS_FAIL_V    V_PASS_FAIL_V(1U)
59607 
59608 #define S_FP_PF_EDGE_NF    11
59609 #define V_FP_PF_EDGE_NF(x) ((x) << S_FP_PF_EDGE_NF)
59610 #define F_FP_PF_EDGE_NF    V_FP_PF_EDGE_NF(1U)
59611 
59612 #define S_NON_SYMETRIC    10
59613 #define V_NON_SYMETRIC(x) ((x) << S_NON_SYMETRIC)
59614 #define F_NON_SYMETRIC    V_NON_SYMETRIC(1U)
59615 
59616 #define S_FULL_RANGE    8
59617 #define V_FULL_RANGE(x) ((x) << S_FULL_RANGE)
59618 #define F_FULL_RANGE    V_FULL_RANGE(1U)
59619 
59620 #define S_QUAD3_EDGES    7
59621 #define V_QUAD3_EDGES(x) ((x) << S_QUAD3_EDGES)
59622 #define F_QUAD3_EDGES    V_QUAD3_EDGES(1U)
59623 
59624 #define S_QUAD2_EDGES    6
59625 #define V_QUAD2_EDGES(x) ((x) << S_QUAD2_EDGES)
59626 #define F_QUAD2_EDGES    V_QUAD2_EDGES(1U)
59627 
59628 #define S_QUAD1_EDGES    5
59629 #define V_QUAD1_EDGES(x) ((x) << S_QUAD1_EDGES)
59630 #define F_QUAD1_EDGES    V_QUAD1_EDGES(1U)
59631 
59632 #define S_QUAD0_EDGES    4
59633 #define V_QUAD0_EDGES(x) ((x) << S_QUAD0_EDGES)
59634 #define F_QUAD0_EDGES    V_QUAD0_EDGES(1U)
59635 
59636 #define S_QUAD3_CAVEAT    3
59637 #define V_QUAD3_CAVEAT(x) ((x) << S_QUAD3_CAVEAT)
59638 #define F_QUAD3_CAVEAT    V_QUAD3_CAVEAT(1U)
59639 
59640 #define S_QUAD2_CAVEAT    2
59641 #define V_QUAD2_CAVEAT(x) ((x) << S_QUAD2_CAVEAT)
59642 #define F_QUAD2_CAVEAT    V_QUAD2_CAVEAT(1U)
59643 
59644 #define S_QUAD1_CAVEAT    1
59645 #define V_QUAD1_CAVEAT(x) ((x) << S_QUAD1_CAVEAT)
59646 #define F_QUAD1_CAVEAT    V_QUAD1_CAVEAT(1U)
59647 
59648 #define S_QUAD0_CAVEAT    0
59649 #define V_QUAD0_CAVEAT(x) ((x) << S_QUAD0_CAVEAT)
59650 #define F_QUAD0_CAVEAT    V_QUAD0_CAVEAT(1U)
59651 
59652 #define A_MC_DDRPHY_DP18_WRCLK_EDGE 0x4417c
59653 
59654 #define S_FAIL_PASS_VALUE    8
59655 #define M_FAIL_PASS_VALUE    0x7fU
59656 #define V_FAIL_PASS_VALUE(x) ((x) << S_FAIL_PASS_VALUE)
59657 #define G_FAIL_PASS_VALUE(x) (((x) >> S_FAIL_PASS_VALUE) & M_FAIL_PASS_VALUE)
59658 
59659 #define S_PASS_FAIL_VALUE    0
59660 #define M_PASS_FAIL_VALUE    0xffU
59661 #define V_PASS_FAIL_VALUE(x) ((x) << S_PASS_FAIL_VALUE)
59662 #define G_PASS_FAIL_VALUE(x) (((x) >> S_PASS_FAIL_VALUE) & M_PASS_FAIL_VALUE)
59663 
59664 #define A_MC_DDRPHY_DP18_READ_EYE_SIZE0_RANK_PAIR 0x44180
59665 
59666 #define S_RD_EYE_SIZE_BITS2_7    8
59667 #define M_RD_EYE_SIZE_BITS2_7    0x3fU
59668 #define V_RD_EYE_SIZE_BITS2_7(x) ((x) << S_RD_EYE_SIZE_BITS2_7)
59669 #define G_RD_EYE_SIZE_BITS2_7(x) (((x) >> S_RD_EYE_SIZE_BITS2_7) & M_RD_EYE_SIZE_BITS2_7)
59670 
59671 #define S_RD_EYE_SIZE_BITS10_15    0
59672 #define M_RD_EYE_SIZE_BITS10_15    0x3fU
59673 #define V_RD_EYE_SIZE_BITS10_15(x) ((x) << S_RD_EYE_SIZE_BITS10_15)
59674 #define G_RD_EYE_SIZE_BITS10_15(x) (((x) >> S_RD_EYE_SIZE_BITS10_15) & M_RD_EYE_SIZE_BITS10_15)
59675 
59676 #define A_MC_DDRPHY_DP18_READ_EYE_SIZE1_RANK_PAIR 0x44184
59677 #define A_MC_DDRPHY_DP18_READ_EYE_SIZE2_RANK_PAIR 0x44188
59678 #define A_MC_DDRPHY_DP18_READ_EYE_SIZE3_RANK_PAIR 0x4418c
59679 #define A_MC_DDRPHY_DP18_READ_EYE_SIZE4_RANK_PAIR 0x44190
59680 #define A_MC_DDRPHY_DP18_READ_EYE_SIZE5_RANK_PAIR 0x44194
59681 #define A_MC_DDRPHY_DP18_READ_EYE_SIZE6_RANK_PAIR 0x44198
59682 #define A_MC_DDRPHY_DP18_READ_EYE_SIZE7_RANK_PAIR 0x4419c
59683 #define A_MC_DDRPHY_DP18_READ_EYE_SIZE8_RANK_PAIR 0x441a0
59684 #define A_MC_DDRPHY_DP18_READ_EYE_SIZE9_RANK_PAIR 0x441a4
59685 #define A_MC_DDRPHY_DP18_READ_EYE_SIZE10_RANK_PAIR 0x441a8
59686 #define A_MC_DDRPHY_DP18_READ_EYE_SIZE11_RANK_PAIR 0x441ac
59687 #define A_MC_DDRPHY_DP18_RD_DIA_CONFIG3 0x441b4
59688 
59689 #define S_DESIRED_EDGE_CNTR_TARGET_HIGH    8
59690 #define M_DESIRED_EDGE_CNTR_TARGET_HIGH    0xffU
59691 #define V_DESIRED_EDGE_CNTR_TARGET_HIGH(x) ((x) << S_DESIRED_EDGE_CNTR_TARGET_HIGH)
59692 #define G_DESIRED_EDGE_CNTR_TARGET_HIGH(x) (((x) >> S_DESIRED_EDGE_CNTR_TARGET_HIGH) & M_DESIRED_EDGE_CNTR_TARGET_HIGH)
59693 
59694 #define S_DESIRED_EDGE_CNTR_TARGET_LOW    0
59695 #define M_DESIRED_EDGE_CNTR_TARGET_LOW    0xffU
59696 #define V_DESIRED_EDGE_CNTR_TARGET_LOW(x) ((x) << S_DESIRED_EDGE_CNTR_TARGET_LOW)
59697 #define G_DESIRED_EDGE_CNTR_TARGET_LOW(x) (((x) >> S_DESIRED_EDGE_CNTR_TARGET_LOW) & M_DESIRED_EDGE_CNTR_TARGET_LOW)
59698 
59699 #define A_MC_DDRPHY_DP18_RD_DIA_CONFIG4 0x441b8
59700 
59701 #define S_APPROACH_ALIGNMENT    15
59702 #define V_APPROACH_ALIGNMENT(x) ((x) << S_APPROACH_ALIGNMENT)
59703 #define F_APPROACH_ALIGNMENT    V_APPROACH_ALIGNMENT(1U)
59704 
59705 #define A_MC_DDRPHY_DP18_DELAY_LINE_PWR_CTL 0x441bc
59706 
59707 #define S_QUAD0_PWR_CTL    12
59708 #define M_QUAD0_PWR_CTL    0xfU
59709 #define V_QUAD0_PWR_CTL(x) ((x) << S_QUAD0_PWR_CTL)
59710 #define G_QUAD0_PWR_CTL(x) (((x) >> S_QUAD0_PWR_CTL) & M_QUAD0_PWR_CTL)
59711 
59712 #define S_QUAD1_PWR_CTL    8
59713 #define M_QUAD1_PWR_CTL    0xfU
59714 #define V_QUAD1_PWR_CTL(x) ((x) << S_QUAD1_PWR_CTL)
59715 #define G_QUAD1_PWR_CTL(x) (((x) >> S_QUAD1_PWR_CTL) & M_QUAD1_PWR_CTL)
59716 
59717 #define S_QUAD2_PWR_CTL    4
59718 #define M_QUAD2_PWR_CTL    0xfU
59719 #define V_QUAD2_PWR_CTL(x) ((x) << S_QUAD2_PWR_CTL)
59720 #define G_QUAD2_PWR_CTL(x) (((x) >> S_QUAD2_PWR_CTL) & M_QUAD2_PWR_CTL)
59721 
59722 #define S_QUAD3_PWR_CTL    0
59723 #define M_QUAD3_PWR_CTL    0xfU
59724 #define V_QUAD3_PWR_CTL(x) ((x) << S_QUAD3_PWR_CTL)
59725 #define G_QUAD3_PWR_CTL(x) (((x) >> S_QUAD3_PWR_CTL) & M_QUAD3_PWR_CTL)
59726 
59727 #define A_MC_DDRPHY_DP18_READ_TIMING_REFERENCE0 0x441c0
59728 
59729 #define S_REFERENCE_BITS1_7    8
59730 #define M_REFERENCE_BITS1_7    0x7fU
59731 #define V_REFERENCE_BITS1_7(x) ((x) << S_REFERENCE_BITS1_7)
59732 #define G_REFERENCE_BITS1_7(x) (((x) >> S_REFERENCE_BITS1_7) & M_REFERENCE_BITS1_7)
59733 
59734 #define S_REFERENCE_BITS9_15    0
59735 #define M_REFERENCE_BITS9_15    0x7fU
59736 #define V_REFERENCE_BITS9_15(x) ((x) << S_REFERENCE_BITS9_15)
59737 #define G_REFERENCE_BITS9_15(x) (((x) >> S_REFERENCE_BITS9_15) & M_REFERENCE_BITS9_15)
59738 
59739 #define A_MC_DDRPHY_DP18_READ_TIMING_REFERENCE1 0x441c4
59740 #define A_MC_DDRPHY_DP18_READ_DQS_TIMING_REFERENCE 0x441c8
59741 
59742 #define S_REFERENCE    8
59743 #define M_REFERENCE    0x7fU
59744 #define V_REFERENCE(x) ((x) << S_REFERENCE)
59745 #define G_REFERENCE(x) (((x) >> S_REFERENCE) & M_REFERENCE)
59746 
59747 #define A_MC_DDRPHY_DP18_SYSCLK_PR_VALUE 0x441cc
59748 #define A_MC_DDRPHY_DP18_WRCLK_PR 0x441d0
59749 #define A_MC_DDRPHY_DP18_IO_TX_CONFIG0 0x441d4
59750 
59751 #define S_INTERP_SIG_SLEW    12
59752 #define M_INTERP_SIG_SLEW    0xfU
59753 #define V_INTERP_SIG_SLEW(x) ((x) << S_INTERP_SIG_SLEW)
59754 #define G_INTERP_SIG_SLEW(x) (((x) >> S_INTERP_SIG_SLEW) & M_INTERP_SIG_SLEW)
59755 
59756 #define S_POST_CURSOR    8
59757 #define M_POST_CURSOR    0xfU
59758 #define V_POST_CURSOR(x) ((x) << S_POST_CURSOR)
59759 #define G_POST_CURSOR(x) (((x) >> S_POST_CURSOR) & M_POST_CURSOR)
59760 
59761 #define S_SLEW_CTL    4
59762 #define M_SLEW_CTL    0xfU
59763 #define V_SLEW_CTL(x) ((x) << S_SLEW_CTL)
59764 #define G_SLEW_CTL(x) (((x) >> S_SLEW_CTL) & M_SLEW_CTL)
59765 
59766 #define A_MC_DDRPHY_DP18_PLL_CONFIG0 0x441d8
59767 #define A_MC_DDRPHY_DP18_PLL_CONFIG1 0x441dc
59768 
59769 #define S_CE0DLTVCCA    7
59770 #define V_CE0DLTVCCA(x) ((x) << S_CE0DLTVCCA)
59771 #define F_CE0DLTVCCA    V_CE0DLTVCCA(1U)
59772 
59773 #define S_CE0DLTVCCD1    4
59774 #define V_CE0DLTVCCD1(x) ((x) << S_CE0DLTVCCD1)
59775 #define F_CE0DLTVCCD1    V_CE0DLTVCCD1(1U)
59776 
59777 #define S_CE0DLTVCCD2    3
59778 #define V_CE0DLTVCCD2(x) ((x) << S_CE0DLTVCCD2)
59779 #define F_CE0DLTVCCD2    V_CE0DLTVCCD2(1U)
59780 
59781 #define S_S0INSDLYTAP    2
59782 #define V_S0INSDLYTAP(x) ((x) << S_S0INSDLYTAP)
59783 #define F_S0INSDLYTAP    V_S0INSDLYTAP(1U)
59784 
59785 #define S_S1INSDLYTAP    1
59786 #define V_S1INSDLYTAP(x) ((x) << S_S1INSDLYTAP)
59787 #define F_S1INSDLYTAP    V_S1INSDLYTAP(1U)
59788 
59789 #define A_MC_DDRPHY_DP18_IO_TX_NFET_SLICE 0x441e0
59790 
59791 #define S_EN_SLICE_N_WR    8
59792 #define M_EN_SLICE_N_WR    0xffU
59793 #define V_EN_SLICE_N_WR(x) ((x) << S_EN_SLICE_N_WR)
59794 #define G_EN_SLICE_N_WR(x) (((x) >> S_EN_SLICE_N_WR) & M_EN_SLICE_N_WR)
59795 
59796 #define A_MC_DDRPHY_DP18_IO_TX_PFET_SLICE 0x441e4
59797 #define A_MC_DDRPHY_DP18_IO_TX_NFET_TERM 0x441e8
59798 
59799 #define S_EN_TERM_N_WR    8
59800 #define M_EN_TERM_N_WR    0xffU
59801 #define V_EN_TERM_N_WR(x) ((x) << S_EN_TERM_N_WR)
59802 #define G_EN_TERM_N_WR(x) (((x) >> S_EN_TERM_N_WR) & M_EN_TERM_N_WR)
59803 
59804 #define S_EN_TERM_N_WR_FFE    4
59805 #define M_EN_TERM_N_WR_FFE    0xfU
59806 #define V_EN_TERM_N_WR_FFE(x) ((x) << S_EN_TERM_N_WR_FFE)
59807 #define G_EN_TERM_N_WR_FFE(x) (((x) >> S_EN_TERM_N_WR_FFE) & M_EN_TERM_N_WR_FFE)
59808 
59809 #define A_MC_DDRPHY_DP18_IO_TX_PFET_TERM 0x441ec
59810 
59811 #define S_EN_TERM_P_WR    8
59812 #define M_EN_TERM_P_WR    0xffU
59813 #define V_EN_TERM_P_WR(x) ((x) << S_EN_TERM_P_WR)
59814 #define G_EN_TERM_P_WR(x) (((x) >> S_EN_TERM_P_WR) & M_EN_TERM_P_WR)
59815 
59816 #define S_EN_TERM_P_WR_FFE    4
59817 #define M_EN_TERM_P_WR_FFE    0xfU
59818 #define V_EN_TERM_P_WR_FFE(x) ((x) << S_EN_TERM_P_WR_FFE)
59819 #define G_EN_TERM_P_WR_FFE(x) (((x) >> S_EN_TERM_P_WR_FFE) & M_EN_TERM_P_WR_FFE)
59820 
59821 #define A_MC_DDRPHY_DP18_DATA_BIT_DISABLE0_RP 0x441f0
59822 
59823 #define S_DATA_BIT_DISABLE_0_15    0
59824 #define M_DATA_BIT_DISABLE_0_15    0xffffU
59825 #define V_DATA_BIT_DISABLE_0_15(x) ((x) << S_DATA_BIT_DISABLE_0_15)
59826 #define G_DATA_BIT_DISABLE_0_15(x) (((x) >> S_DATA_BIT_DISABLE_0_15) & M_DATA_BIT_DISABLE_0_15)
59827 
59828 #define A_MC_DDRPHY_DP18_DATA_BIT_DISABLE1_RP 0x441f4
59829 
59830 #define S_DATA_BIT_DISABLE_16_23    8
59831 #define M_DATA_BIT_DISABLE_16_23    0xffU
59832 #define V_DATA_BIT_DISABLE_16_23(x) ((x) << S_DATA_BIT_DISABLE_16_23)
59833 #define G_DATA_BIT_DISABLE_16_23(x) (((x) >> S_DATA_BIT_DISABLE_16_23) & M_DATA_BIT_DISABLE_16_23)
59834 
59835 #define A_MC_DDRPHY_DP18_DQ_WR_OFFSET_RP 0x441f8
59836 
59837 #define S_DQ_WR_OFFSET_N0    12
59838 #define M_DQ_WR_OFFSET_N0    0xfU
59839 #define V_DQ_WR_OFFSET_N0(x) ((x) << S_DQ_WR_OFFSET_N0)
59840 #define G_DQ_WR_OFFSET_N0(x) (((x) >> S_DQ_WR_OFFSET_N0) & M_DQ_WR_OFFSET_N0)
59841 
59842 #define S_DQ_WR_OFFSET_N1    8
59843 #define M_DQ_WR_OFFSET_N1    0xfU
59844 #define V_DQ_WR_OFFSET_N1(x) ((x) << S_DQ_WR_OFFSET_N1)
59845 #define G_DQ_WR_OFFSET_N1(x) (((x) >> S_DQ_WR_OFFSET_N1) & M_DQ_WR_OFFSET_N1)
59846 
59847 #define S_DQ_WR_OFFSET_N2    4
59848 #define M_DQ_WR_OFFSET_N2    0xfU
59849 #define V_DQ_WR_OFFSET_N2(x) ((x) << S_DQ_WR_OFFSET_N2)
59850 #define G_DQ_WR_OFFSET_N2(x) (((x) >> S_DQ_WR_OFFSET_N2) & M_DQ_WR_OFFSET_N2)
59851 
59852 #define S_DQ_WR_OFFSET_N3    0
59853 #define M_DQ_WR_OFFSET_N3    0xfU
59854 #define V_DQ_WR_OFFSET_N3(x) ((x) << S_DQ_WR_OFFSET_N3)
59855 #define G_DQ_WR_OFFSET_N3(x) (((x) >> S_DQ_WR_OFFSET_N3) & M_DQ_WR_OFFSET_N3)
59856 
59857 #define A_MC_DDRPHY_DP18_POWERDOWN_1 0x441fc
59858 
59859 #define S_EYEDAC_PD    13
59860 #define V_EYEDAC_PD(x) ((x) << S_EYEDAC_PD)
59861 #define F_EYEDAC_PD    V_EYEDAC_PD(1U)
59862 
59863 #define S_ANALOG_OUTPUT_STAB    9
59864 #define V_ANALOG_OUTPUT_STAB(x) ((x) << S_ANALOG_OUTPUT_STAB)
59865 #define F_ANALOG_OUTPUT_STAB    V_ANALOG_OUTPUT_STAB(1U)
59866 
59867 #define S_DP18_RX_PD    2
59868 #define M_DP18_RX_PD    0x3U
59869 #define V_DP18_RX_PD(x) ((x) << S_DP18_RX_PD)
59870 #define G_DP18_RX_PD(x) (((x) >> S_DP18_RX_PD) & M_DP18_RX_PD)
59871 
59872 #define S_DELAY_LINE_CTL_OVERRIDE    4
59873 #define V_DELAY_LINE_CTL_OVERRIDE(x) ((x) << S_DELAY_LINE_CTL_OVERRIDE)
59874 #define F_DELAY_LINE_CTL_OVERRIDE    V_DELAY_LINE_CTL_OVERRIDE(1U)
59875 
59876 #define S_VCC_REG_PD    0
59877 #define V_VCC_REG_PD(x) ((x) << S_VCC_REG_PD)
59878 #define F_VCC_REG_PD    V_VCC_REG_PD(1U)
59879 
59880 #define A_MC_ADR_DDRPHY_ADR_BIT_ENABLE 0x45000
59881 
59882 #define S_BIT_ENABLE_0_11    4
59883 #define M_BIT_ENABLE_0_11    0xfffU
59884 #define V_BIT_ENABLE_0_11(x) ((x) << S_BIT_ENABLE_0_11)
59885 #define G_BIT_ENABLE_0_11(x) (((x) >> S_BIT_ENABLE_0_11) & M_BIT_ENABLE_0_11)
59886 
59887 #define S_BIT_ENABLE_12_15    0
59888 #define M_BIT_ENABLE_12_15    0xfU
59889 #define V_BIT_ENABLE_12_15(x) ((x) << S_BIT_ENABLE_12_15)
59890 #define G_BIT_ENABLE_12_15(x) (((x) >> S_BIT_ENABLE_12_15) & M_BIT_ENABLE_12_15)
59891 
59892 #define A_MC_ADR_DDRPHY_ADR_DIFFPAIR_ENABLE 0x45004
59893 
59894 #define S_DI_ADR0_ADR1    15
59895 #define V_DI_ADR0_ADR1(x) ((x) << S_DI_ADR0_ADR1)
59896 #define F_DI_ADR0_ADR1    V_DI_ADR0_ADR1(1U)
59897 
59898 #define S_DI_ADR2_ADR3    14
59899 #define V_DI_ADR2_ADR3(x) ((x) << S_DI_ADR2_ADR3)
59900 #define F_DI_ADR2_ADR3    V_DI_ADR2_ADR3(1U)
59901 
59902 #define S_DI_ADR4_ADR5    13
59903 #define V_DI_ADR4_ADR5(x) ((x) << S_DI_ADR4_ADR5)
59904 #define F_DI_ADR4_ADR5    V_DI_ADR4_ADR5(1U)
59905 
59906 #define S_DI_ADR6_ADR7    12
59907 #define V_DI_ADR6_ADR7(x) ((x) << S_DI_ADR6_ADR7)
59908 #define F_DI_ADR6_ADR7    V_DI_ADR6_ADR7(1U)
59909 
59910 #define S_DI_ADR8_ADR9    11
59911 #define V_DI_ADR8_ADR9(x) ((x) << S_DI_ADR8_ADR9)
59912 #define F_DI_ADR8_ADR9    V_DI_ADR8_ADR9(1U)
59913 
59914 #define S_DI_ADR10_ADR11    10
59915 #define V_DI_ADR10_ADR11(x) ((x) << S_DI_ADR10_ADR11)
59916 #define F_DI_ADR10_ADR11    V_DI_ADR10_ADR11(1U)
59917 
59918 #define S_DI_ADR12_ADR13    9
59919 #define V_DI_ADR12_ADR13(x) ((x) << S_DI_ADR12_ADR13)
59920 #define F_DI_ADR12_ADR13    V_DI_ADR12_ADR13(1U)
59921 
59922 #define S_DI_ADR14_ADR15    8
59923 #define V_DI_ADR14_ADR15(x) ((x) << S_DI_ADR14_ADR15)
59924 #define F_DI_ADR14_ADR15    V_DI_ADR14_ADR15(1U)
59925 
59926 #define A_MC_ADR_DDRPHY_ADR_DELAY0 0x45010
59927 
59928 #define S_ADR_DELAY_BITS1_7    8
59929 #define M_ADR_DELAY_BITS1_7    0x7fU
59930 #define V_ADR_DELAY_BITS1_7(x) ((x) << S_ADR_DELAY_BITS1_7)
59931 #define G_ADR_DELAY_BITS1_7(x) (((x) >> S_ADR_DELAY_BITS1_7) & M_ADR_DELAY_BITS1_7)
59932 
59933 #define S_ADR_DELAY_BITS9_15    0
59934 #define M_ADR_DELAY_BITS9_15    0x7fU
59935 #define V_ADR_DELAY_BITS9_15(x) ((x) << S_ADR_DELAY_BITS9_15)
59936 #define G_ADR_DELAY_BITS9_15(x) (((x) >> S_ADR_DELAY_BITS9_15) & M_ADR_DELAY_BITS9_15)
59937 
59938 #define A_MC_ADR_DDRPHY_ADR_DELAY1 0x45014
59939 #define A_MC_ADR_DDRPHY_ADR_DELAY2 0x45018
59940 #define A_MC_ADR_DDRPHY_ADR_DELAY3 0x4501c
59941 #define A_MC_ADR_DDRPHY_ADR_DELAY4 0x45020
59942 #define A_MC_ADR_DDRPHY_ADR_DELAY5 0x45024
59943 #define A_MC_ADR_DDRPHY_ADR_DELAY6 0x45028
59944 #define A_MC_ADR_DDRPHY_ADR_DELAY7 0x4502c
59945 #define A_MC_ADR_DDRPHY_ADR_DFT_WRAP_STATUS_CONTROL 0x45030
59946 
59947 #define S_ADR_TEST_LANE_PAIR_FAIL    8
59948 #define M_ADR_TEST_LANE_PAIR_FAIL    0xffU
59949 #define V_ADR_TEST_LANE_PAIR_FAIL(x) ((x) << S_ADR_TEST_LANE_PAIR_FAIL)
59950 #define G_ADR_TEST_LANE_PAIR_FAIL(x) (((x) >> S_ADR_TEST_LANE_PAIR_FAIL) & M_ADR_TEST_LANE_PAIR_FAIL)
59951 
59952 #define S_ADR_TEST_DATA_EN    7
59953 #define V_ADR_TEST_DATA_EN(x) ((x) << S_ADR_TEST_DATA_EN)
59954 #define F_ADR_TEST_DATA_EN    V_ADR_TEST_DATA_EN(1U)
59955 
59956 #define S_DADR_TEST_MODE    5
59957 #define M_DADR_TEST_MODE    0x3U
59958 #define V_DADR_TEST_MODE(x) ((x) << S_DADR_TEST_MODE)
59959 #define G_DADR_TEST_MODE(x) (((x) >> S_DADR_TEST_MODE) & M_DADR_TEST_MODE)
59960 
59961 #define S_ADR_TEST_4TO1_MODE    4
59962 #define V_ADR_TEST_4TO1_MODE(x) ((x) << S_ADR_TEST_4TO1_MODE)
59963 #define F_ADR_TEST_4TO1_MODE    V_ADR_TEST_4TO1_MODE(1U)
59964 
59965 #define S_ADR_TEST_RESET    3
59966 #define V_ADR_TEST_RESET(x) ((x) << S_ADR_TEST_RESET)
59967 #define F_ADR_TEST_RESET    V_ADR_TEST_RESET(1U)
59968 
59969 #define S_ADR_TEST_GEN_EN    2
59970 #define V_ADR_TEST_GEN_EN(x) ((x) << S_ADR_TEST_GEN_EN)
59971 #define F_ADR_TEST_GEN_EN    V_ADR_TEST_GEN_EN(1U)
59972 
59973 #define S_ADR_TEST_CLEAR_ERROR    1
59974 #define V_ADR_TEST_CLEAR_ERROR(x) ((x) << S_ADR_TEST_CLEAR_ERROR)
59975 #define F_ADR_TEST_CLEAR_ERROR    V_ADR_TEST_CLEAR_ERROR(1U)
59976 
59977 #define S_ADR_TEST_CHECK_EN    0
59978 #define V_ADR_TEST_CHECK_EN(x) ((x) << S_ADR_TEST_CHECK_EN)
59979 #define F_ADR_TEST_CHECK_EN    V_ADR_TEST_CHECK_EN(1U)
59980 
59981 #define A_MC_ADR_DDRPHY_ADR_IO_NFET_SLICE_EN0 0x45040
59982 
59983 #define S_EN_SLICE_N_WR_0    8
59984 #define M_EN_SLICE_N_WR_0    0xffU
59985 #define V_EN_SLICE_N_WR_0(x) ((x) << S_EN_SLICE_N_WR_0)
59986 #define G_EN_SLICE_N_WR_0(x) (((x) >> S_EN_SLICE_N_WR_0) & M_EN_SLICE_N_WR_0)
59987 
59988 #define S_EN_SLICE_N_WR_FFE    4
59989 #define M_EN_SLICE_N_WR_FFE    0xfU
59990 #define V_EN_SLICE_N_WR_FFE(x) ((x) << S_EN_SLICE_N_WR_FFE)
59991 #define G_EN_SLICE_N_WR_FFE(x) (((x) >> S_EN_SLICE_N_WR_FFE) & M_EN_SLICE_N_WR_FFE)
59992 
59993 #define A_MC_ADR_DDRPHY_ADR_IO_NFET_SLICE_EN1 0x45044
59994 
59995 #define S_EN_SLICE_N_WR_1    8
59996 #define M_EN_SLICE_N_WR_1    0xffU
59997 #define V_EN_SLICE_N_WR_1(x) ((x) << S_EN_SLICE_N_WR_1)
59998 #define G_EN_SLICE_N_WR_1(x) (((x) >> S_EN_SLICE_N_WR_1) & M_EN_SLICE_N_WR_1)
59999 
60000 #define A_MC_ADR_DDRPHY_ADR_IO_NFET_SLICE_EN2 0x45048
60001 
60002 #define S_EN_SLICE_N_WR_2    8
60003 #define M_EN_SLICE_N_WR_2    0xffU
60004 #define V_EN_SLICE_N_WR_2(x) ((x) << S_EN_SLICE_N_WR_2)
60005 #define G_EN_SLICE_N_WR_2(x) (((x) >> S_EN_SLICE_N_WR_2) & M_EN_SLICE_N_WR_2)
60006 
60007 #define A_MC_ADR_DDRPHY_ADR_IO_NFET_SLICE_EN3 0x4504c
60008 
60009 #define S_EN_SLICE_N_WR_3    8
60010 #define M_EN_SLICE_N_WR_3    0xffU
60011 #define V_EN_SLICE_N_WR_3(x) ((x) << S_EN_SLICE_N_WR_3)
60012 #define G_EN_SLICE_N_WR_3(x) (((x) >> S_EN_SLICE_N_WR_3) & M_EN_SLICE_N_WR_3)
60013 
60014 #define A_MC_ADR_DDRPHY_ADR_IO_PFET_SLICE_EN0 0x45050
60015 
60016 #define S_EN_SLICE_P_WR    8
60017 #define M_EN_SLICE_P_WR    0xffU
60018 #define V_EN_SLICE_P_WR(x) ((x) << S_EN_SLICE_P_WR)
60019 #define G_EN_SLICE_P_WR(x) (((x) >> S_EN_SLICE_P_WR) & M_EN_SLICE_P_WR)
60020 
60021 #define S_EN_SLICE_P_WR_FFE    4
60022 #define M_EN_SLICE_P_WR_FFE    0xfU
60023 #define V_EN_SLICE_P_WR_FFE(x) ((x) << S_EN_SLICE_P_WR_FFE)
60024 #define G_EN_SLICE_P_WR_FFE(x) (((x) >> S_EN_SLICE_P_WR_FFE) & M_EN_SLICE_P_WR_FFE)
60025 
60026 #define A_MC_ADR_DDRPHY_ADR_IO_PFET_SLICE_EN1 0x45054
60027 #define A_MC_ADR_DDRPHY_ADR_IO_PFET_SLICE_EN2 0x45058
60028 #define A_MC_ADR_DDRPHY_ADR_IO_PFET_SLICE_EN3 0x4505c
60029 #define A_MC_ADR_DDRPHY_ADR_IO_POST_CURSOR_VALUE 0x45060
60030 
60031 #define S_POST_CURSOR0    12
60032 #define M_POST_CURSOR0    0xfU
60033 #define V_POST_CURSOR0(x) ((x) << S_POST_CURSOR0)
60034 #define G_POST_CURSOR0(x) (((x) >> S_POST_CURSOR0) & M_POST_CURSOR0)
60035 
60036 #define S_POST_CURSOR1    8
60037 #define M_POST_CURSOR1    0xfU
60038 #define V_POST_CURSOR1(x) ((x) << S_POST_CURSOR1)
60039 #define G_POST_CURSOR1(x) (((x) >> S_POST_CURSOR1) & M_POST_CURSOR1)
60040 
60041 #define S_POST_CURSOR2    4
60042 #define M_POST_CURSOR2    0xfU
60043 #define V_POST_CURSOR2(x) ((x) << S_POST_CURSOR2)
60044 #define G_POST_CURSOR2(x) (((x) >> S_POST_CURSOR2) & M_POST_CURSOR2)
60045 
60046 #define S_POST_CURSOR3    0
60047 #define M_POST_CURSOR3    0xfU
60048 #define V_POST_CURSOR3(x) ((x) << S_POST_CURSOR3)
60049 #define G_POST_CURSOR3(x) (((x) >> S_POST_CURSOR3) & M_POST_CURSOR3)
60050 
60051 #define A_MC_ADR_DDRPHY_ADR_IO_SLEW_CTL_VALUE 0x45068
60052 
60053 #define S_SLEW_CTL0    12
60054 #define M_SLEW_CTL0    0xfU
60055 #define V_SLEW_CTL0(x) ((x) << S_SLEW_CTL0)
60056 #define G_SLEW_CTL0(x) (((x) >> S_SLEW_CTL0) & M_SLEW_CTL0)
60057 
60058 #define S_SLEW_CTL1    8
60059 #define M_SLEW_CTL1    0xfU
60060 #define V_SLEW_CTL1(x) ((x) << S_SLEW_CTL1)
60061 #define G_SLEW_CTL1(x) (((x) >> S_SLEW_CTL1) & M_SLEW_CTL1)
60062 
60063 #define S_SLEW_CTL2    4
60064 #define M_SLEW_CTL2    0xfU
60065 #define V_SLEW_CTL2(x) ((x) << S_SLEW_CTL2)
60066 #define G_SLEW_CTL2(x) (((x) >> S_SLEW_CTL2) & M_SLEW_CTL2)
60067 
60068 #define S_SLEW_CTL3    0
60069 #define M_SLEW_CTL3    0xfU
60070 #define V_SLEW_CTL3(x) ((x) << S_SLEW_CTL3)
60071 #define G_SLEW_CTL3(x) (((x) >> S_SLEW_CTL3) & M_SLEW_CTL3)
60072 
60073 #define A_MC_ADR_DDRPHY_ADR_IO_FET_SLICE_EN_MAP0 0x45080
60074 
60075 #define S_SLICE_SEL_REG_BITS0_1    14
60076 #define M_SLICE_SEL_REG_BITS0_1    0x3U
60077 #define V_SLICE_SEL_REG_BITS0_1(x) ((x) << S_SLICE_SEL_REG_BITS0_1)
60078 #define G_SLICE_SEL_REG_BITS0_1(x) (((x) >> S_SLICE_SEL_REG_BITS0_1) & M_SLICE_SEL_REG_BITS0_1)
60079 
60080 #define S_SLICE_SEL_REG_BITS2_3    12
60081 #define M_SLICE_SEL_REG_BITS2_3    0x3U
60082 #define V_SLICE_SEL_REG_BITS2_3(x) ((x) << S_SLICE_SEL_REG_BITS2_3)
60083 #define G_SLICE_SEL_REG_BITS2_3(x) (((x) >> S_SLICE_SEL_REG_BITS2_3) & M_SLICE_SEL_REG_BITS2_3)
60084 
60085 #define S_SLICE_SEL_REG_BITS4_5    10
60086 #define M_SLICE_SEL_REG_BITS4_5    0x3U
60087 #define V_SLICE_SEL_REG_BITS4_5(x) ((x) << S_SLICE_SEL_REG_BITS4_5)
60088 #define G_SLICE_SEL_REG_BITS4_5(x) (((x) >> S_SLICE_SEL_REG_BITS4_5) & M_SLICE_SEL_REG_BITS4_5)
60089 
60090 #define S_SLICE_SEL_REG_BITS6_7    8
60091 #define M_SLICE_SEL_REG_BITS6_7    0x3U
60092 #define V_SLICE_SEL_REG_BITS6_7(x) ((x) << S_SLICE_SEL_REG_BITS6_7)
60093 #define G_SLICE_SEL_REG_BITS6_7(x) (((x) >> S_SLICE_SEL_REG_BITS6_7) & M_SLICE_SEL_REG_BITS6_7)
60094 
60095 #define S_SLICE_SEL_REG_BITS8_9    6
60096 #define M_SLICE_SEL_REG_BITS8_9    0x3U
60097 #define V_SLICE_SEL_REG_BITS8_9(x) ((x) << S_SLICE_SEL_REG_BITS8_9)
60098 #define G_SLICE_SEL_REG_BITS8_9(x) (((x) >> S_SLICE_SEL_REG_BITS8_9) & M_SLICE_SEL_REG_BITS8_9)
60099 
60100 #define S_SLICE_SEL_REG_BITS10_11    4
60101 #define M_SLICE_SEL_REG_BITS10_11    0x3U
60102 #define V_SLICE_SEL_REG_BITS10_11(x) ((x) << S_SLICE_SEL_REG_BITS10_11)
60103 #define G_SLICE_SEL_REG_BITS10_11(x) (((x) >> S_SLICE_SEL_REG_BITS10_11) & M_SLICE_SEL_REG_BITS10_11)
60104 
60105 #define S_SLICE_SEL_REG_BITS12_13    2
60106 #define M_SLICE_SEL_REG_BITS12_13    0x3U
60107 #define V_SLICE_SEL_REG_BITS12_13(x) ((x) << S_SLICE_SEL_REG_BITS12_13)
60108 #define G_SLICE_SEL_REG_BITS12_13(x) (((x) >> S_SLICE_SEL_REG_BITS12_13) & M_SLICE_SEL_REG_BITS12_13)
60109 
60110 #define S_SLICE_SEL_REG_BITS14_15    0
60111 #define M_SLICE_SEL_REG_BITS14_15    0x3U
60112 #define V_SLICE_SEL_REG_BITS14_15(x) ((x) << S_SLICE_SEL_REG_BITS14_15)
60113 #define G_SLICE_SEL_REG_BITS14_15(x) (((x) >> S_SLICE_SEL_REG_BITS14_15) & M_SLICE_SEL_REG_BITS14_15)
60114 
60115 #define A_MC_ADR_DDRPHY_ADR_IO_FET_SLICE_EN_MAP1 0x45084
60116 #define A_MC_ADR_DDRPHY_ADR_IO_POST_CURSOR_VALUE_MAP0 0x450a0
60117 
60118 #define S_POST_CUR_SEL_BITS0_1    14
60119 #define M_POST_CUR_SEL_BITS0_1    0x3U
60120 #define V_POST_CUR_SEL_BITS0_1(x) ((x) << S_POST_CUR_SEL_BITS0_1)
60121 #define G_POST_CUR_SEL_BITS0_1(x) (((x) >> S_POST_CUR_SEL_BITS0_1) & M_POST_CUR_SEL_BITS0_1)
60122 
60123 #define S_POST_CUR_SEL_BITS2_3    12
60124 #define M_POST_CUR_SEL_BITS2_3    0x3U
60125 #define V_POST_CUR_SEL_BITS2_3(x) ((x) << S_POST_CUR_SEL_BITS2_3)
60126 #define G_POST_CUR_SEL_BITS2_3(x) (((x) >> S_POST_CUR_SEL_BITS2_3) & M_POST_CUR_SEL_BITS2_3)
60127 
60128 #define S_POST_CUR_SEL_BITS4_5    10
60129 #define M_POST_CUR_SEL_BITS4_5    0x3U
60130 #define V_POST_CUR_SEL_BITS4_5(x) ((x) << S_POST_CUR_SEL_BITS4_5)
60131 #define G_POST_CUR_SEL_BITS4_5(x) (((x) >> S_POST_CUR_SEL_BITS4_5) & M_POST_CUR_SEL_BITS4_5)
60132 
60133 #define S_POST_CUR_SEL_BITS6_7    8
60134 #define M_POST_CUR_SEL_BITS6_7    0x3U
60135 #define V_POST_CUR_SEL_BITS6_7(x) ((x) << S_POST_CUR_SEL_BITS6_7)
60136 #define G_POST_CUR_SEL_BITS6_7(x) (((x) >> S_POST_CUR_SEL_BITS6_7) & M_POST_CUR_SEL_BITS6_7)
60137 
60138 #define S_POST_CUR_SEL_BITS8_9    6
60139 #define M_POST_CUR_SEL_BITS8_9    0x3U
60140 #define V_POST_CUR_SEL_BITS8_9(x) ((x) << S_POST_CUR_SEL_BITS8_9)
60141 #define G_POST_CUR_SEL_BITS8_9(x) (((x) >> S_POST_CUR_SEL_BITS8_9) & M_POST_CUR_SEL_BITS8_9)
60142 
60143 #define S_POST_CUR_SEL_BITS10_11    4
60144 #define M_POST_CUR_SEL_BITS10_11    0x3U
60145 #define V_POST_CUR_SEL_BITS10_11(x) ((x) << S_POST_CUR_SEL_BITS10_11)
60146 #define G_POST_CUR_SEL_BITS10_11(x) (((x) >> S_POST_CUR_SEL_BITS10_11) & M_POST_CUR_SEL_BITS10_11)
60147 
60148 #define S_POST_CUR_SEL_BITS12_13    2
60149 #define M_POST_CUR_SEL_BITS12_13    0x3U
60150 #define V_POST_CUR_SEL_BITS12_13(x) ((x) << S_POST_CUR_SEL_BITS12_13)
60151 #define G_POST_CUR_SEL_BITS12_13(x) (((x) >> S_POST_CUR_SEL_BITS12_13) & M_POST_CUR_SEL_BITS12_13)
60152 
60153 #define S_POST_CUR_SEL_BITS14_15    0
60154 #define M_POST_CUR_SEL_BITS14_15    0x3U
60155 #define V_POST_CUR_SEL_BITS14_15(x) ((x) << S_POST_CUR_SEL_BITS14_15)
60156 #define G_POST_CUR_SEL_BITS14_15(x) (((x) >> S_POST_CUR_SEL_BITS14_15) & M_POST_CUR_SEL_BITS14_15)
60157 
60158 #define A_MC_ADR_DDRPHY_ADR_IO_POST_CURSOR_VALUE_MAP1 0x450a4
60159 #define A_MC_ADR_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP0 0x450a8
60160 
60161 #define S_SLEW_CTL_SEL_BITS0_1    14
60162 #define M_SLEW_CTL_SEL_BITS0_1    0x3U
60163 #define V_SLEW_CTL_SEL_BITS0_1(x) ((x) << S_SLEW_CTL_SEL_BITS0_1)
60164 #define G_SLEW_CTL_SEL_BITS0_1(x) (((x) >> S_SLEW_CTL_SEL_BITS0_1) & M_SLEW_CTL_SEL_BITS0_1)
60165 
60166 #define S_SLEW_CTL_SEL_BITS2_3    12
60167 #define M_SLEW_CTL_SEL_BITS2_3    0x3U
60168 #define V_SLEW_CTL_SEL_BITS2_3(x) ((x) << S_SLEW_CTL_SEL_BITS2_3)
60169 #define G_SLEW_CTL_SEL_BITS2_3(x) (((x) >> S_SLEW_CTL_SEL_BITS2_3) & M_SLEW_CTL_SEL_BITS2_3)
60170 
60171 #define S_SLEW_CTL_SEL_BITS4_5    10
60172 #define M_SLEW_CTL_SEL_BITS4_5    0x3U
60173 #define V_SLEW_CTL_SEL_BITS4_5(x) ((x) << S_SLEW_CTL_SEL_BITS4_5)
60174 #define G_SLEW_CTL_SEL_BITS4_5(x) (((x) >> S_SLEW_CTL_SEL_BITS4_5) & M_SLEW_CTL_SEL_BITS4_5)
60175 
60176 #define S_SLEW_CTL_SEL_BITS6_7    8
60177 #define M_SLEW_CTL_SEL_BITS6_7    0x3U
60178 #define V_SLEW_CTL_SEL_BITS6_7(x) ((x) << S_SLEW_CTL_SEL_BITS6_7)
60179 #define G_SLEW_CTL_SEL_BITS6_7(x) (((x) >> S_SLEW_CTL_SEL_BITS6_7) & M_SLEW_CTL_SEL_BITS6_7)
60180 
60181 #define S_SLEW_CTL_SEL_BITS8_9    6
60182 #define M_SLEW_CTL_SEL_BITS8_9    0x3U
60183 #define V_SLEW_CTL_SEL_BITS8_9(x) ((x) << S_SLEW_CTL_SEL_BITS8_9)
60184 #define G_SLEW_CTL_SEL_BITS8_9(x) (((x) >> S_SLEW_CTL_SEL_BITS8_9) & M_SLEW_CTL_SEL_BITS8_9)
60185 
60186 #define S_SLEW_CTL_SEL_BITS10_11    4
60187 #define M_SLEW_CTL_SEL_BITS10_11    0x3U
60188 #define V_SLEW_CTL_SEL_BITS10_11(x) ((x) << S_SLEW_CTL_SEL_BITS10_11)
60189 #define G_SLEW_CTL_SEL_BITS10_11(x) (((x) >> S_SLEW_CTL_SEL_BITS10_11) & M_SLEW_CTL_SEL_BITS10_11)
60190 
60191 #define S_SLEW_CTL_SEL_BITS12_13    2
60192 #define M_SLEW_CTL_SEL_BITS12_13    0x3U
60193 #define V_SLEW_CTL_SEL_BITS12_13(x) ((x) << S_SLEW_CTL_SEL_BITS12_13)
60194 #define G_SLEW_CTL_SEL_BITS12_13(x) (((x) >> S_SLEW_CTL_SEL_BITS12_13) & M_SLEW_CTL_SEL_BITS12_13)
60195 
60196 #define S_SLEW_CTL_SEL_BITS14_15    0
60197 #define M_SLEW_CTL_SEL_BITS14_15    0x3U
60198 #define V_SLEW_CTL_SEL_BITS14_15(x) ((x) << S_SLEW_CTL_SEL_BITS14_15)
60199 #define G_SLEW_CTL_SEL_BITS14_15(x) (((x) >> S_SLEW_CTL_SEL_BITS14_15) & M_SLEW_CTL_SEL_BITS14_15)
60200 
60201 #define A_MC_ADR_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP1 0x450ac
60202 #define A_MC_ADR_DDRPHY_ADR_POWERDOWN_2 0x450b0
60203 
60204 #define S_ADR_LANE_0_11_PD    4
60205 #define M_ADR_LANE_0_11_PD    0xfffU
60206 #define V_ADR_LANE_0_11_PD(x) ((x) << S_ADR_LANE_0_11_PD)
60207 #define G_ADR_LANE_0_11_PD(x) (((x) >> S_ADR_LANE_0_11_PD) & M_ADR_LANE_0_11_PD)
60208 
60209 #define S_ADR_LANE_12_15_PD    0
60210 #define M_ADR_LANE_12_15_PD    0xfU
60211 #define V_ADR_LANE_12_15_PD(x) ((x) << S_ADR_LANE_12_15_PD)
60212 #define G_ADR_LANE_12_15_PD(x) (((x) >> S_ADR_LANE_12_15_PD) & M_ADR_LANE_12_15_PD)
60213 
60214 #define A_T6_MC_ADR_DDRPHY_ADR_BIT_ENABLE 0x45800
60215 #define A_T6_MC_ADR_DDRPHY_ADR_DIFFPAIR_ENABLE 0x45804
60216 #define A_T6_MC_ADR_DDRPHY_ADR_DELAY0 0x45810
60217 #define A_T6_MC_ADR_DDRPHY_ADR_DELAY1 0x45814
60218 #define A_T6_MC_ADR_DDRPHY_ADR_DELAY2 0x45818
60219 #define A_T6_MC_ADR_DDRPHY_ADR_DELAY3 0x4581c
60220 #define A_T6_MC_ADR_DDRPHY_ADR_DELAY4 0x45820
60221 #define A_T6_MC_ADR_DDRPHY_ADR_DELAY5 0x45824
60222 #define A_T6_MC_ADR_DDRPHY_ADR_DELAY6 0x45828
60223 #define A_T6_MC_ADR_DDRPHY_ADR_DELAY7 0x4582c
60224 #define A_T6_MC_ADR_DDRPHY_ADR_DFT_WRAP_STATUS_CONTROL 0x45830
60225 
60226 #define S_ADR_TEST_MODE    5
60227 #define M_ADR_TEST_MODE    0x3U
60228 #define V_ADR_TEST_MODE(x) ((x) << S_ADR_TEST_MODE)
60229 #define G_ADR_TEST_MODE(x) (((x) >> S_ADR_TEST_MODE) & M_ADR_TEST_MODE)
60230 
60231 #define A_T6_MC_ADR_DDRPHY_ADR_IO_NFET_SLICE_EN0 0x45840
60232 #define A_T6_MC_ADR_DDRPHY_ADR_IO_NFET_SLICE_EN1 0x45844
60233 #define A_T6_MC_ADR_DDRPHY_ADR_IO_NFET_SLICE_EN2 0x45848
60234 #define A_T6_MC_ADR_DDRPHY_ADR_IO_NFET_SLICE_EN3 0x4584c
60235 #define A_T6_MC_ADR_DDRPHY_ADR_IO_PFET_SLICE_EN0 0x45850
60236 #define A_T6_MC_ADR_DDRPHY_ADR_IO_PFET_SLICE_EN1 0x45854
60237 #define A_T6_MC_ADR_DDRPHY_ADR_IO_PFET_SLICE_EN2 0x45858
60238 #define A_T6_MC_ADR_DDRPHY_ADR_IO_PFET_SLICE_EN3 0x4585c
60239 #define A_T6_MC_ADR_DDRPHY_ADR_IO_POST_CURSOR_VALUE 0x45860
60240 #define A_T6_MC_ADR_DDRPHY_ADR_IO_SLEW_CTL_VALUE 0x45868
60241 #define A_T6_MC_ADR_DDRPHY_ADR_IO_FET_SLICE_EN_MAP0 0x45880
60242 #define A_T6_MC_ADR_DDRPHY_ADR_IO_FET_SLICE_EN_MAP1 0x45884
60243 #define A_T6_MC_ADR_DDRPHY_ADR_IO_POST_CURSOR_VALUE_MAP0 0x458a0
60244 #define A_T6_MC_ADR_DDRPHY_ADR_IO_POST_CURSOR_VALUE_MAP1 0x458a4
60245 #define A_T6_MC_ADR_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP0 0x458a8
60246 #define A_T6_MC_ADR_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP1 0x458ac
60247 #define A_T6_MC_ADR_DDRPHY_ADR_POWERDOWN_2 0x458b0
60248 #define A_MC_DDRPHY_ADR_PLL_VREG_CONFIG_0 0x460c0
60249 
60250 #define S_PLL_TUNE_0_2    13
60251 #define M_PLL_TUNE_0_2    0x7U
60252 #define V_PLL_TUNE_0_2(x) ((x) << S_PLL_TUNE_0_2)
60253 #define G_PLL_TUNE_0_2(x) (((x) >> S_PLL_TUNE_0_2) & M_PLL_TUNE_0_2)
60254 
60255 #define S_PLL_TUNECP_0_2    10
60256 #define M_PLL_TUNECP_0_2    0x7U
60257 #define V_PLL_TUNECP_0_2(x) ((x) << S_PLL_TUNECP_0_2)
60258 #define G_PLL_TUNECP_0_2(x) (((x) >> S_PLL_TUNECP_0_2) & M_PLL_TUNECP_0_2)
60259 
60260 #define S_PLL_TUNEF_0_5    4
60261 #define M_PLL_TUNEF_0_5    0x3fU
60262 #define V_PLL_TUNEF_0_5(x) ((x) << S_PLL_TUNEF_0_5)
60263 #define G_PLL_TUNEF_0_5(x) (((x) >> S_PLL_TUNEF_0_5) & M_PLL_TUNEF_0_5)
60264 
60265 #define S_PLL_TUNEVCO_0_1    2
60266 #define M_PLL_TUNEVCO_0_1    0x3U
60267 #define V_PLL_TUNEVCO_0_1(x) ((x) << S_PLL_TUNEVCO_0_1)
60268 #define G_PLL_TUNEVCO_0_1(x) (((x) >> S_PLL_TUNEVCO_0_1) & M_PLL_TUNEVCO_0_1)
60269 
60270 #define S_PLL_PLLXTR_0_1    0
60271 #define M_PLL_PLLXTR_0_1    0x3U
60272 #define V_PLL_PLLXTR_0_1(x) ((x) << S_PLL_PLLXTR_0_1)
60273 #define G_PLL_PLLXTR_0_1(x) (((x) >> S_PLL_PLLXTR_0_1) & M_PLL_PLLXTR_0_1)
60274 
60275 #define A_MC_DDRPHY_AD32S_PLL_VREG_CONFIG_0 0x460c0
60276 #define A_MC_DDRPHY_ADR_PLL_VREG_CONFIG_1 0x460c4
60277 
60278 #define S_PLL_TUNETDIV_0_2    13
60279 #define M_PLL_TUNETDIV_0_2    0x7U
60280 #define V_PLL_TUNETDIV_0_2(x) ((x) << S_PLL_TUNETDIV_0_2)
60281 #define G_PLL_TUNETDIV_0_2(x) (((x) >> S_PLL_TUNETDIV_0_2) & M_PLL_TUNETDIV_0_2)
60282 
60283 #define S_PLL_TUNEMDIV_0_1    11
60284 #define M_PLL_TUNEMDIV_0_1    0x3U
60285 #define V_PLL_TUNEMDIV_0_1(x) ((x) << S_PLL_TUNEMDIV_0_1)
60286 #define G_PLL_TUNEMDIV_0_1(x) (((x) >> S_PLL_TUNEMDIV_0_1) & M_PLL_TUNEMDIV_0_1)
60287 
60288 #define S_PLL_TUNEATST    10
60289 #define V_PLL_TUNEATST(x) ((x) << S_PLL_TUNEATST)
60290 #define F_PLL_TUNEATST    V_PLL_TUNEATST(1U)
60291 
60292 #define S_VREG_RANGE_0_1    8
60293 #define M_VREG_RANGE_0_1    0x3U
60294 #define V_VREG_RANGE_0_1(x) ((x) << S_VREG_RANGE_0_1)
60295 #define G_VREG_RANGE_0_1(x) (((x) >> S_VREG_RANGE_0_1) & M_VREG_RANGE_0_1)
60296 
60297 #define S_VREG_VREGSPARE    7
60298 #define V_VREG_VREGSPARE(x) ((x) << S_VREG_VREGSPARE)
60299 #define F_VREG_VREGSPARE    V_VREG_VREGSPARE(1U)
60300 
60301 #define S_VREG_VCCTUNE_0_1    5
60302 #define M_VREG_VCCTUNE_0_1    0x3U
60303 #define V_VREG_VCCTUNE_0_1(x) ((x) << S_VREG_VCCTUNE_0_1)
60304 #define G_VREG_VCCTUNE_0_1(x) (((x) >> S_VREG_VCCTUNE_0_1) & M_VREG_VCCTUNE_0_1)
60305 
60306 #define S_INTERP_SIG_SLEW_0_3    1
60307 #define M_INTERP_SIG_SLEW_0_3    0xfU
60308 #define V_INTERP_SIG_SLEW_0_3(x) ((x) << S_INTERP_SIG_SLEW_0_3)
60309 #define G_INTERP_SIG_SLEW_0_3(x) (((x) >> S_INTERP_SIG_SLEW_0_3) & M_INTERP_SIG_SLEW_0_3)
60310 
60311 #define S_ANALOG_WRAPON    0
60312 #define V_ANALOG_WRAPON(x) ((x) << S_ANALOG_WRAPON)
60313 #define F_ANALOG_WRAPON    V_ANALOG_WRAPON(1U)
60314 
60315 #define A_MC_DDRPHY_AD32S_PLL_VREG_CONFIG_1 0x460c4
60316 #define A_MC_DDRPHY_ADR_SYSCLK_CNTL_PR 0x460c8
60317 
60318 #define S_SYSCLK_ENABLE    15
60319 #define V_SYSCLK_ENABLE(x) ((x) << S_SYSCLK_ENABLE)
60320 #define F_SYSCLK_ENABLE    V_SYSCLK_ENABLE(1U)
60321 
60322 #define S_SYSCLK_ROT_OVERRIDE    8
60323 #define M_SYSCLK_ROT_OVERRIDE    0x7fU
60324 #define V_SYSCLK_ROT_OVERRIDE(x) ((x) << S_SYSCLK_ROT_OVERRIDE)
60325 #define G_SYSCLK_ROT_OVERRIDE(x) (((x) >> S_SYSCLK_ROT_OVERRIDE) & M_SYSCLK_ROT_OVERRIDE)
60326 
60327 #define S_SYSCLK_ROT_OVERRIDE_EN    7
60328 #define V_SYSCLK_ROT_OVERRIDE_EN(x) ((x) << S_SYSCLK_ROT_OVERRIDE_EN)
60329 #define F_SYSCLK_ROT_OVERRIDE_EN    V_SYSCLK_ROT_OVERRIDE_EN(1U)
60330 
60331 #define S_SYSCLK_PHASE_ALIGN_RESE    6
60332 #define V_SYSCLK_PHASE_ALIGN_RESE(x) ((x) << S_SYSCLK_PHASE_ALIGN_RESE)
60333 #define F_SYSCLK_PHASE_ALIGN_RESE    V_SYSCLK_PHASE_ALIGN_RESE(1U)
60334 
60335 #define S_SYSCLK_PHASE_CNTL_EN    5
60336 #define V_SYSCLK_PHASE_CNTL_EN(x) ((x) << S_SYSCLK_PHASE_CNTL_EN)
60337 #define F_SYSCLK_PHASE_CNTL_EN    V_SYSCLK_PHASE_CNTL_EN(1U)
60338 
60339 #define S_SYSCLK_PHASE_DEFAULT_EN    4
60340 #define V_SYSCLK_PHASE_DEFAULT_EN(x) ((x) << S_SYSCLK_PHASE_DEFAULT_EN)
60341 #define F_SYSCLK_PHASE_DEFAULT_EN    V_SYSCLK_PHASE_DEFAULT_EN(1U)
60342 
60343 #define S_SYSCLK_POS_EDGE_ALIGN    3
60344 #define V_SYSCLK_POS_EDGE_ALIGN(x) ((x) << S_SYSCLK_POS_EDGE_ALIGN)
60345 #define F_SYSCLK_POS_EDGE_ALIGN    V_SYSCLK_POS_EDGE_ALIGN(1U)
60346 
60347 #define S_CONTINUOUS_UPDATE    2
60348 #define V_CONTINUOUS_UPDATE(x) ((x) << S_CONTINUOUS_UPDATE)
60349 #define F_CONTINUOUS_UPDATE    V_CONTINUOUS_UPDATE(1U)
60350 
60351 #define S_CE0DLTVCC    0
60352 #define M_CE0DLTVCC    0x3U
60353 #define V_CE0DLTVCC(x) ((x) << S_CE0DLTVCC)
60354 #define G_CE0DLTVCC(x) (((x) >> S_CE0DLTVCC) & M_CE0DLTVCC)
60355 
60356 #define A_MC_DDRPHY_AD32S_SYSCLK_CNTL_PR 0x460c8
60357 #define A_MC_DDRPHY_ADR_MCCLK_WRCLK_PR_STATIC_OFFSET 0x460cc
60358 
60359 #define S_TSYS_WRCLK    8
60360 #define M_TSYS_WRCLK    0x7fU
60361 #define V_TSYS_WRCLK(x) ((x) << S_TSYS_WRCLK)
60362 #define G_TSYS_WRCLK(x) (((x) >> S_TSYS_WRCLK) & M_TSYS_WRCLK)
60363 
60364 #define A_MC_DDRPHY_AD32S_MCCLK_WRCLK_PR_STATIC_OFFSET 0x460cc
60365 #define A_MC_DDRPHY_ADR_SYSCLK_PR_VALUE_RO 0x460d0
60366 
60367 #define S_SLEW_LATE_SAMPLE    15
60368 #define V_SLEW_LATE_SAMPLE(x) ((x) << S_SLEW_LATE_SAMPLE)
60369 #define F_SLEW_LATE_SAMPLE    V_SLEW_LATE_SAMPLE(1U)
60370 
60371 #define S_SYSCLK_ROT    8
60372 #define M_SYSCLK_ROT    0x7fU
60373 #define V_SYSCLK_ROT(x) ((x) << S_SYSCLK_ROT)
60374 #define G_SYSCLK_ROT(x) (((x) >> S_SYSCLK_ROT) & M_SYSCLK_ROT)
60375 
60376 #define S_BB_LOCK    7
60377 #define V_BB_LOCK(x) ((x) << S_BB_LOCK)
60378 #define F_BB_LOCK    V_BB_LOCK(1U)
60379 
60380 #define S_SLEW_EARLY_SAMPLE    6
60381 #define V_SLEW_EARLY_SAMPLE(x) ((x) << S_SLEW_EARLY_SAMPLE)
60382 #define F_SLEW_EARLY_SAMPLE    V_SLEW_EARLY_SAMPLE(1U)
60383 
60384 #define S_SLEW_DONE_STATUS    4
60385 #define M_SLEW_DONE_STATUS    0x3U
60386 #define V_SLEW_DONE_STATUS(x) ((x) << S_SLEW_DONE_STATUS)
60387 #define G_SLEW_DONE_STATUS(x) (((x) >> S_SLEW_DONE_STATUS) & M_SLEW_DONE_STATUS)
60388 
60389 #define S_SLEW_CNTL    0
60390 #define M_SLEW_CNTL    0xfU
60391 #define V_SLEW_CNTL(x) ((x) << S_SLEW_CNTL)
60392 #define G_SLEW_CNTL(x) (((x) >> S_SLEW_CNTL) & M_SLEW_CNTL)
60393 
60394 #define A_MC_DDRPHY_AD32S_SYSCLK_PR_VALUE_RO 0x460d0
60395 #define A_MC_DDRPHY_ADR_GMTEST_ATEST_CNTL 0x460d4
60396 
60397 #define S_FLUSH    15
60398 #define V_FLUSH(x) ((x) << S_FLUSH)
60399 #define F_FLUSH    V_FLUSH(1U)
60400 
60401 #define S_GIANT_MUX_TEST_EN    14
60402 #define V_GIANT_MUX_TEST_EN(x) ((x) << S_GIANT_MUX_TEST_EN)
60403 #define F_GIANT_MUX_TEST_EN    V_GIANT_MUX_TEST_EN(1U)
60404 
60405 #define S_GIANT_MUX_TEST_VAL    13
60406 #define V_GIANT_MUX_TEST_VAL(x) ((x) << S_GIANT_MUX_TEST_VAL)
60407 #define F_GIANT_MUX_TEST_VAL    V_GIANT_MUX_TEST_VAL(1U)
60408 
60409 #define S_HS_PROBE_A_SEL_    8
60410 #define M_HS_PROBE_A_SEL_    0xfU
60411 #define V_HS_PROBE_A_SEL_(x) ((x) << S_HS_PROBE_A_SEL_)
60412 #define G_HS_PROBE_A_SEL_(x) (((x) >> S_HS_PROBE_A_SEL_) & M_HS_PROBE_A_SEL_)
60413 
60414 #define S_HS_PROBE_B_SEL_    4
60415 #define M_HS_PROBE_B_SEL_    0xfU
60416 #define V_HS_PROBE_B_SEL_(x) ((x) << S_HS_PROBE_B_SEL_)
60417 #define G_HS_PROBE_B_SEL_(x) (((x) >> S_HS_PROBE_B_SEL_) & M_HS_PROBE_B_SEL_)
60418 
60419 #define S_ATEST1CTL0    3
60420 #define V_ATEST1CTL0(x) ((x) << S_ATEST1CTL0)
60421 #define F_ATEST1CTL0    V_ATEST1CTL0(1U)
60422 
60423 #define S_ATEST1CTL1    2
60424 #define V_ATEST1CTL1(x) ((x) << S_ATEST1CTL1)
60425 #define F_ATEST1CTL1    V_ATEST1CTL1(1U)
60426 
60427 #define S_ATEST1CTL2    1
60428 #define V_ATEST1CTL2(x) ((x) << S_ATEST1CTL2)
60429 #define F_ATEST1CTL2    V_ATEST1CTL2(1U)
60430 
60431 #define S_ATEST1CTL3    0
60432 #define V_ATEST1CTL3(x) ((x) << S_ATEST1CTL3)
60433 #define F_ATEST1CTL3    V_ATEST1CTL3(1U)
60434 
60435 #define A_MC_DDRPHY_AD32S_OUTPUT_FORCE_ATEST_CNTL 0x460d4
60436 
60437 #define S_FORCE_EN    14
60438 #define V_FORCE_EN(x) ((x) << S_FORCE_EN)
60439 #define F_FORCE_EN    V_FORCE_EN(1U)
60440 
60441 #define S_AD32S_HS_PROBE_A_SEL    8
60442 #define M_AD32S_HS_PROBE_A_SEL    0xfU
60443 #define V_AD32S_HS_PROBE_A_SEL(x) ((x) << S_AD32S_HS_PROBE_A_SEL)
60444 #define G_AD32S_HS_PROBE_A_SEL(x) (((x) >> S_AD32S_HS_PROBE_A_SEL) & M_AD32S_HS_PROBE_A_SEL)
60445 
60446 #define S_AD32S_HS_PROBE_B_SEL    4
60447 #define M_AD32S_HS_PROBE_B_SEL    0xfU
60448 #define V_AD32S_HS_PROBE_B_SEL(x) ((x) << S_AD32S_HS_PROBE_B_SEL)
60449 #define G_AD32S_HS_PROBE_B_SEL(x) (((x) >> S_AD32S_HS_PROBE_B_SEL) & M_AD32S_HS_PROBE_B_SEL)
60450 
60451 #define A_MC_DDRPHY_ADR_GIANT_MUX_RESULTS_A0 0x460d8
60452 
60453 #define S_GIANT_MUX_TEST_RESULTS    0
60454 #define M_GIANT_MUX_TEST_RESULTS    0xffffU
60455 #define V_GIANT_MUX_TEST_RESULTS(x) ((x) << S_GIANT_MUX_TEST_RESULTS)
60456 #define G_GIANT_MUX_TEST_RESULTS(x) (((x) >> S_GIANT_MUX_TEST_RESULTS) & M_GIANT_MUX_TEST_RESULTS)
60457 
60458 #define A_MC_DDRPHY_AD32S_OUTPUT_DRIVER_FORCE_VALUE0 0x460d8
60459 
60460 #define S_OUTPUT_DRIVER_FORCE_VALUE    0
60461 #define M_OUTPUT_DRIVER_FORCE_VALUE    0xffffU
60462 #define V_OUTPUT_DRIVER_FORCE_VALUE(x) ((x) << S_OUTPUT_DRIVER_FORCE_VALUE)
60463 #define G_OUTPUT_DRIVER_FORCE_VALUE(x) (((x) >> S_OUTPUT_DRIVER_FORCE_VALUE) & M_OUTPUT_DRIVER_FORCE_VALUE)
60464 
60465 #define A_MC_DDRPHY_ADR_GIANT_MUX_RESULTS_A1 0x460dc
60466 #define A_MC_DDRPHY_AD32S_OUTPUT_DRIVER_FORCE_VALUE1 0x460dc
60467 #define A_MC_DDRPHY_ADR_POWERDOWN_1 0x460e0
60468 
60469 #define S_MASTER_PD_CNTL    15
60470 #define V_MASTER_PD_CNTL(x) ((x) << S_MASTER_PD_CNTL)
60471 #define F_MASTER_PD_CNTL    V_MASTER_PD_CNTL(1U)
60472 
60473 #define S_ANALOG_INPUT_STAB2    14
60474 #define V_ANALOG_INPUT_STAB2(x) ((x) << S_ANALOG_INPUT_STAB2)
60475 #define F_ANALOG_INPUT_STAB2    V_ANALOG_INPUT_STAB2(1U)
60476 
60477 #define S_ANALOG_INPUT_STAB1    8
60478 #define V_ANALOG_INPUT_STAB1(x) ((x) << S_ANALOG_INPUT_STAB1)
60479 #define F_ANALOG_INPUT_STAB1    V_ANALOG_INPUT_STAB1(1U)
60480 
60481 #define S_SYSCLK_CLK_GATE    6
60482 #define M_SYSCLK_CLK_GATE    0x3U
60483 #define V_SYSCLK_CLK_GATE(x) ((x) << S_SYSCLK_CLK_GATE)
60484 #define G_SYSCLK_CLK_GATE(x) (((x) >> S_SYSCLK_CLK_GATE) & M_SYSCLK_CLK_GATE)
60485 
60486 #define S_WR_FIFO_STAB    5
60487 #define V_WR_FIFO_STAB(x) ((x) << S_WR_FIFO_STAB)
60488 #define F_WR_FIFO_STAB    V_WR_FIFO_STAB(1U)
60489 
60490 #define S_ADR_RX_PD    4
60491 #define V_ADR_RX_PD(x) ((x) << S_ADR_RX_PD)
60492 #define F_ADR_RX_PD    V_ADR_RX_PD(1U)
60493 
60494 #define S_TX_TRISTATE_CNTL    1
60495 #define V_TX_TRISTATE_CNTL(x) ((x) << S_TX_TRISTATE_CNTL)
60496 #define F_TX_TRISTATE_CNTL    V_TX_TRISTATE_CNTL(1U)
60497 
60498 #define S_DVCC_REG_PD    0
60499 #define V_DVCC_REG_PD(x) ((x) << S_DVCC_REG_PD)
60500 #define F_DVCC_REG_PD    V_DVCC_REG_PD(1U)
60501 
60502 #define A_MC_DDRPHY_AD32S_POWERDOWN_1 0x460e0
60503 #define A_MC_DDRPHY_ADR_SLEW_CAL_CNTL 0x460e4
60504 
60505 #define S_SLEW_CAL_ENABLE    15
60506 #define V_SLEW_CAL_ENABLE(x) ((x) << S_SLEW_CAL_ENABLE)
60507 #define F_SLEW_CAL_ENABLE    V_SLEW_CAL_ENABLE(1U)
60508 
60509 #define S_SLEW_CAL_START    14
60510 #define V_SLEW_CAL_START(x) ((x) << S_SLEW_CAL_START)
60511 #define F_SLEW_CAL_START    V_SLEW_CAL_START(1U)
60512 
60513 #define S_SLEW_CAL_OVERRIDE_EN    12
60514 #define V_SLEW_CAL_OVERRIDE_EN(x) ((x) << S_SLEW_CAL_OVERRIDE_EN)
60515 #define F_SLEW_CAL_OVERRIDE_EN    V_SLEW_CAL_OVERRIDE_EN(1U)
60516 
60517 #define S_SLEW_CAL_OVERRIDE    8
60518 #define M_SLEW_CAL_OVERRIDE    0xfU
60519 #define V_SLEW_CAL_OVERRIDE(x) ((x) << S_SLEW_CAL_OVERRIDE)
60520 #define G_SLEW_CAL_OVERRIDE(x) (((x) >> S_SLEW_CAL_OVERRIDE) & M_SLEW_CAL_OVERRIDE)
60521 
60522 #define S_SLEW_TARGET_PR_OFFSET    0
60523 #define M_SLEW_TARGET_PR_OFFSET    0x1fU
60524 #define V_SLEW_TARGET_PR_OFFSET(x) ((x) << S_SLEW_TARGET_PR_OFFSET)
60525 #define G_SLEW_TARGET_PR_OFFSET(x) (((x) >> S_SLEW_TARGET_PR_OFFSET) & M_SLEW_TARGET_PR_OFFSET)
60526 
60527 #define A_MC_DDRPHY_AD32S_SLEW_CAL_CNTL 0x460e4
60528 #define A_MC_DDRPHY_PC_DP18_PLL_LOCK_STATUS 0x47000
60529 
60530 #define S_DP18_PLL_LOCK    1
60531 #define M_DP18_PLL_LOCK    0x7fffU
60532 #define V_DP18_PLL_LOCK(x) ((x) << S_DP18_PLL_LOCK)
60533 #define G_DP18_PLL_LOCK(x) (((x) >> S_DP18_PLL_LOCK) & M_DP18_PLL_LOCK)
60534 
60535 #define A_MC_DDRPHY_PC_AD32S_PLL_LOCK_STATUS 0x47004
60536 
60537 #define S_AD32S_PLL_LOCK    14
60538 #define M_AD32S_PLL_LOCK    0x3U
60539 #define V_AD32S_PLL_LOCK(x) ((x) << S_AD32S_PLL_LOCK)
60540 #define G_AD32S_PLL_LOCK(x) (((x) >> S_AD32S_PLL_LOCK) & M_AD32S_PLL_LOCK)
60541 
60542 #define A_MC_DDRPHY_PC_RANK_PAIR0 0x47008
60543 
60544 #define S_RANK_PAIR0_PRI    13
60545 #define M_RANK_PAIR0_PRI    0x7U
60546 #define V_RANK_PAIR0_PRI(x) ((x) << S_RANK_PAIR0_PRI)
60547 #define G_RANK_PAIR0_PRI(x) (((x) >> S_RANK_PAIR0_PRI) & M_RANK_PAIR0_PRI)
60548 
60549 #define S_RANK_PAIR0_PRI_V    12
60550 #define V_RANK_PAIR0_PRI_V(x) ((x) << S_RANK_PAIR0_PRI_V)
60551 #define F_RANK_PAIR0_PRI_V    V_RANK_PAIR0_PRI_V(1U)
60552 
60553 #define S_RANK_PAIR0_SEC    9
60554 #define M_RANK_PAIR0_SEC    0x7U
60555 #define V_RANK_PAIR0_SEC(x) ((x) << S_RANK_PAIR0_SEC)
60556 #define G_RANK_PAIR0_SEC(x) (((x) >> S_RANK_PAIR0_SEC) & M_RANK_PAIR0_SEC)
60557 
60558 #define S_RANK_PAIR0_SEC_V    8
60559 #define V_RANK_PAIR0_SEC_V(x) ((x) << S_RANK_PAIR0_SEC_V)
60560 #define F_RANK_PAIR0_SEC_V    V_RANK_PAIR0_SEC_V(1U)
60561 
60562 #define S_RANK_PAIR1_PRI    5
60563 #define M_RANK_PAIR1_PRI    0x7U
60564 #define V_RANK_PAIR1_PRI(x) ((x) << S_RANK_PAIR1_PRI)
60565 #define G_RANK_PAIR1_PRI(x) (((x) >> S_RANK_PAIR1_PRI) & M_RANK_PAIR1_PRI)
60566 
60567 #define S_RANK_PAIR1_PRI_V    4
60568 #define V_RANK_PAIR1_PRI_V(x) ((x) << S_RANK_PAIR1_PRI_V)
60569 #define F_RANK_PAIR1_PRI_V    V_RANK_PAIR1_PRI_V(1U)
60570 
60571 #define S_RANK_PAIR1_SEC    1
60572 #define M_RANK_PAIR1_SEC    0x7U
60573 #define V_RANK_PAIR1_SEC(x) ((x) << S_RANK_PAIR1_SEC)
60574 #define G_RANK_PAIR1_SEC(x) (((x) >> S_RANK_PAIR1_SEC) & M_RANK_PAIR1_SEC)
60575 
60576 #define S_RANK_PAIR1_SEC_V    0
60577 #define V_RANK_PAIR1_SEC_V(x) ((x) << S_RANK_PAIR1_SEC_V)
60578 #define F_RANK_PAIR1_SEC_V    V_RANK_PAIR1_SEC_V(1U)
60579 
60580 #define A_MC_DDRPHY_PC_RANK_PAIR1 0x4700c
60581 
60582 #define S_RANK_PAIR2_PRI    13
60583 #define M_RANK_PAIR2_PRI    0x7U
60584 #define V_RANK_PAIR2_PRI(x) ((x) << S_RANK_PAIR2_PRI)
60585 #define G_RANK_PAIR2_PRI(x) (((x) >> S_RANK_PAIR2_PRI) & M_RANK_PAIR2_PRI)
60586 
60587 #define S_RANK_PAIR2_PRI_V    12
60588 #define V_RANK_PAIR2_PRI_V(x) ((x) << S_RANK_PAIR2_PRI_V)
60589 #define F_RANK_PAIR2_PRI_V    V_RANK_PAIR2_PRI_V(1U)
60590 
60591 #define S_RANK_PAIR2_SEC    9
60592 #define M_RANK_PAIR2_SEC    0x7U
60593 #define V_RANK_PAIR2_SEC(x) ((x) << S_RANK_PAIR2_SEC)
60594 #define G_RANK_PAIR2_SEC(x) (((x) >> S_RANK_PAIR2_SEC) & M_RANK_PAIR2_SEC)
60595 
60596 #define S_RANK_PAIR2_SEC_V    8
60597 #define V_RANK_PAIR2_SEC_V(x) ((x) << S_RANK_PAIR2_SEC_V)
60598 #define F_RANK_PAIR2_SEC_V    V_RANK_PAIR2_SEC_V(1U)
60599 
60600 #define S_RANK_PAIR3_PRI    5
60601 #define M_RANK_PAIR3_PRI    0x7U
60602 #define V_RANK_PAIR3_PRI(x) ((x) << S_RANK_PAIR3_PRI)
60603 #define G_RANK_PAIR3_PRI(x) (((x) >> S_RANK_PAIR3_PRI) & M_RANK_PAIR3_PRI)
60604 
60605 #define S_RANK_PAIR3_PRI_V    4
60606 #define V_RANK_PAIR3_PRI_V(x) ((x) << S_RANK_PAIR3_PRI_V)
60607 #define F_RANK_PAIR3_PRI_V    V_RANK_PAIR3_PRI_V(1U)
60608 
60609 #define S_RANK_PAIR3_SEC    1
60610 #define M_RANK_PAIR3_SEC    0x7U
60611 #define V_RANK_PAIR3_SEC(x) ((x) << S_RANK_PAIR3_SEC)
60612 #define G_RANK_PAIR3_SEC(x) (((x) >> S_RANK_PAIR3_SEC) & M_RANK_PAIR3_SEC)
60613 
60614 #define S_RANK_PAIR3_SEC_V    0
60615 #define V_RANK_PAIR3_SEC_V(x) ((x) << S_RANK_PAIR3_SEC_V)
60616 #define F_RANK_PAIR3_SEC_V    V_RANK_PAIR3_SEC_V(1U)
60617 
60618 #define A_MC_DDRPHY_PC_BASE_CNTR0 0x47010
60619 
60620 #define S_PERIODIC_BASE_CNTR0    0
60621 #define M_PERIODIC_BASE_CNTR0    0xffffU
60622 #define V_PERIODIC_BASE_CNTR0(x) ((x) << S_PERIODIC_BASE_CNTR0)
60623 #define G_PERIODIC_BASE_CNTR0(x) (((x) >> S_PERIODIC_BASE_CNTR0) & M_PERIODIC_BASE_CNTR0)
60624 
60625 #define A_MC_DDRPHY_PC_RELOAD_VALUE0 0x47014
60626 
60627 #define S_PERIODIC_CAL_REQ_EN    15
60628 #define V_PERIODIC_CAL_REQ_EN(x) ((x) << S_PERIODIC_CAL_REQ_EN)
60629 #define F_PERIODIC_CAL_REQ_EN    V_PERIODIC_CAL_REQ_EN(1U)
60630 
60631 #define S_PERIODIC_RELOAD_VALUE0    0
60632 #define M_PERIODIC_RELOAD_VALUE0    0x7fffU
60633 #define V_PERIODIC_RELOAD_VALUE0(x) ((x) << S_PERIODIC_RELOAD_VALUE0)
60634 #define G_PERIODIC_RELOAD_VALUE0(x) (((x) >> S_PERIODIC_RELOAD_VALUE0) & M_PERIODIC_RELOAD_VALUE0)
60635 
60636 #define A_MC_DDRPHY_PC_BASE_CNTR1 0x47018
60637 
60638 #define S_PERIODIC_BASE_CNTR1    0
60639 #define M_PERIODIC_BASE_CNTR1    0xffffU
60640 #define V_PERIODIC_BASE_CNTR1(x) ((x) << S_PERIODIC_BASE_CNTR1)
60641 #define G_PERIODIC_BASE_CNTR1(x) (((x) >> S_PERIODIC_BASE_CNTR1) & M_PERIODIC_BASE_CNTR1)
60642 
60643 #define A_MC_DDRPHY_PC_CAL_TIMER 0x4701c
60644 
60645 #define S_PERIODIC_CAL_TIMER    0
60646 #define M_PERIODIC_CAL_TIMER    0xffffU
60647 #define V_PERIODIC_CAL_TIMER(x) ((x) << S_PERIODIC_CAL_TIMER)
60648 #define G_PERIODIC_CAL_TIMER(x) (((x) >> S_PERIODIC_CAL_TIMER) & M_PERIODIC_CAL_TIMER)
60649 
60650 #define A_MC_DDRPHY_PC_CAL_TIMER_RELOAD_VALUE 0x47020
60651 
60652 #define S_PERIODIC_TIMER_RELOAD_VALUE    0
60653 #define M_PERIODIC_TIMER_RELOAD_VALUE    0xffffU
60654 #define V_PERIODIC_TIMER_RELOAD_VALUE(x) ((x) << S_PERIODIC_TIMER_RELOAD_VALUE)
60655 #define G_PERIODIC_TIMER_RELOAD_VALUE(x) (((x) >> S_PERIODIC_TIMER_RELOAD_VALUE) & M_PERIODIC_TIMER_RELOAD_VALUE)
60656 
60657 #define A_MC_DDRPHY_PC_ZCAL_TIMER 0x47024
60658 
60659 #define S_PERIODIC_ZCAL_TIMER    0
60660 #define M_PERIODIC_ZCAL_TIMER    0xffffU
60661 #define V_PERIODIC_ZCAL_TIMER(x) ((x) << S_PERIODIC_ZCAL_TIMER)
60662 #define G_PERIODIC_ZCAL_TIMER(x) (((x) >> S_PERIODIC_ZCAL_TIMER) & M_PERIODIC_ZCAL_TIMER)
60663 
60664 #define A_MC_DDRPHY_PC_ZCAL_TIMER_RELOAD_VALUE 0x47028
60665 #define A_MC_DDRPHY_PC_PER_CAL_CONFIG 0x4702c
60666 
60667 #define S_PER_ENA_RANK_PAIR    12
60668 #define M_PER_ENA_RANK_PAIR    0xfU
60669 #define V_PER_ENA_RANK_PAIR(x) ((x) << S_PER_ENA_RANK_PAIR)
60670 #define G_PER_ENA_RANK_PAIR(x) (((x) >> S_PER_ENA_RANK_PAIR) & M_PER_ENA_RANK_PAIR)
60671 
60672 #define S_PER_ENA_ZCAL    11
60673 #define V_PER_ENA_ZCAL(x) ((x) << S_PER_ENA_ZCAL)
60674 #define F_PER_ENA_ZCAL    V_PER_ENA_ZCAL(1U)
60675 
60676 #define S_PER_ENA_SYSCLK_ALIGN    10
60677 #define V_PER_ENA_SYSCLK_ALIGN(x) ((x) << S_PER_ENA_SYSCLK_ALIGN)
60678 #define F_PER_ENA_SYSCLK_ALIGN    V_PER_ENA_SYSCLK_ALIGN(1U)
60679 
60680 #define S_ENA_PER_READ_CTR    9
60681 #define V_ENA_PER_READ_CTR(x) ((x) << S_ENA_PER_READ_CTR)
60682 #define F_ENA_PER_READ_CTR    V_ENA_PER_READ_CTR(1U)
60683 
60684 #define S_ENA_PER_RDCLK_ALIGN    8
60685 #define V_ENA_PER_RDCLK_ALIGN(x) ((x) << S_ENA_PER_RDCLK_ALIGN)
60686 #define F_ENA_PER_RDCLK_ALIGN    V_ENA_PER_RDCLK_ALIGN(1U)
60687 
60688 #define S_ENA_PER_DQS_ALIGN    7
60689 #define V_ENA_PER_DQS_ALIGN(x) ((x) << S_ENA_PER_DQS_ALIGN)
60690 #define F_ENA_PER_DQS_ALIGN    V_ENA_PER_DQS_ALIGN(1U)
60691 
60692 #define S_PER_NEXT_RANK_PAIR    5
60693 #define M_PER_NEXT_RANK_PAIR    0x3U
60694 #define V_PER_NEXT_RANK_PAIR(x) ((x) << S_PER_NEXT_RANK_PAIR)
60695 #define G_PER_NEXT_RANK_PAIR(x) (((x) >> S_PER_NEXT_RANK_PAIR) & M_PER_NEXT_RANK_PAIR)
60696 
60697 #define S_FAST_SIM_PER_CNTR    4
60698 #define V_FAST_SIM_PER_CNTR(x) ((x) << S_FAST_SIM_PER_CNTR)
60699 #define F_FAST_SIM_PER_CNTR    V_FAST_SIM_PER_CNTR(1U)
60700 
60701 #define S_START_INIT_CAL    3
60702 #define V_START_INIT_CAL(x) ((x) << S_START_INIT_CAL)
60703 #define F_START_INIT_CAL    V_START_INIT_CAL(1U)
60704 
60705 #define S_START_PER_CAL    2
60706 #define V_START_PER_CAL(x) ((x) << S_START_PER_CAL)
60707 #define F_START_PER_CAL    V_START_PER_CAL(1U)
60708 
60709 #define S_ABORT_ON_ERR_EN    1
60710 #define V_ABORT_ON_ERR_EN(x) ((x) << S_ABORT_ON_ERR_EN)
60711 #define F_ABORT_ON_ERR_EN    V_ABORT_ON_ERR_EN(1U)
60712 
60713 #define S_ENA_PER_RD_CTR    9
60714 #define V_ENA_PER_RD_CTR(x) ((x) << S_ENA_PER_RD_CTR)
60715 #define F_ENA_PER_RD_CTR    V_ENA_PER_RD_CTR(1U)
60716 
60717 #define A_MC_DDRPHY_PC_CONFIG0 0x47030
60718 
60719 #define S_PROTOCOL_DDR    12
60720 #define M_PROTOCOL_DDR    0xfU
60721 #define V_PROTOCOL_DDR(x) ((x) << S_PROTOCOL_DDR)
60722 #define G_PROTOCOL_DDR(x) (((x) >> S_PROTOCOL_DDR) & M_PROTOCOL_DDR)
60723 
60724 #define S_DATA_MUX4_1MODE    11
60725 #define V_DATA_MUX4_1MODE(x) ((x) << S_DATA_MUX4_1MODE)
60726 #define F_DATA_MUX4_1MODE    V_DATA_MUX4_1MODE(1U)
60727 
60728 #define S_DDR4_CMD_SIG_REDUCTION    9
60729 #define V_DDR4_CMD_SIG_REDUCTION(x) ((x) << S_DDR4_CMD_SIG_REDUCTION)
60730 #define F_DDR4_CMD_SIG_REDUCTION    V_DDR4_CMD_SIG_REDUCTION(1U)
60731 
60732 #define S_SYSCLK_2X_MEMINTCLKO    8
60733 #define V_SYSCLK_2X_MEMINTCLKO(x) ((x) << S_SYSCLK_2X_MEMINTCLKO)
60734 #define F_SYSCLK_2X_MEMINTCLKO    V_SYSCLK_2X_MEMINTCLKO(1U)
60735 
60736 #define S_RANK_OVERRIDE    7
60737 #define V_RANK_OVERRIDE(x) ((x) << S_RANK_OVERRIDE)
60738 #define F_RANK_OVERRIDE    V_RANK_OVERRIDE(1U)
60739 
60740 #define S_RANK_OVERRIDE_VALUE    4
60741 #define M_RANK_OVERRIDE_VALUE    0x7U
60742 #define V_RANK_OVERRIDE_VALUE(x) ((x) << S_RANK_OVERRIDE_VALUE)
60743 #define G_RANK_OVERRIDE_VALUE(x) (((x) >> S_RANK_OVERRIDE_VALUE) & M_RANK_OVERRIDE_VALUE)
60744 
60745 #define S_LOW_LATENCY    3
60746 #define V_LOW_LATENCY(x) ((x) << S_LOW_LATENCY)
60747 #define F_LOW_LATENCY    V_LOW_LATENCY(1U)
60748 
60749 #define S_DDR4_BANK_REFRESH    2
60750 #define V_DDR4_BANK_REFRESH(x) ((x) << S_DDR4_BANK_REFRESH)
60751 #define F_DDR4_BANK_REFRESH    V_DDR4_BANK_REFRESH(1U)
60752 
60753 #define S_DDR4_VLEVEL_BANK_GROUP    1
60754 #define V_DDR4_VLEVEL_BANK_GROUP(x) ((x) << S_DDR4_VLEVEL_BANK_GROUP)
60755 #define F_DDR4_VLEVEL_BANK_GROUP    V_DDR4_VLEVEL_BANK_GROUP(1U)
60756 
60757 #define S_DDRPHY_PROTOCOL    12
60758 #define M_DDRPHY_PROTOCOL    0xfU
60759 #define V_DDRPHY_PROTOCOL(x) ((x) << S_DDRPHY_PROTOCOL)
60760 #define G_DDRPHY_PROTOCOL(x) (((x) >> S_DDRPHY_PROTOCOL) & M_DDRPHY_PROTOCOL)
60761 
60762 #define S_SPAM_EN    10
60763 #define V_SPAM_EN(x) ((x) << S_SPAM_EN)
60764 #define F_SPAM_EN    V_SPAM_EN(1U)
60765 
60766 #define S_DDR4_IPW_LOOP_DIS    2
60767 #define V_DDR4_IPW_LOOP_DIS(x) ((x) << S_DDR4_IPW_LOOP_DIS)
60768 #define F_DDR4_IPW_LOOP_DIS    V_DDR4_IPW_LOOP_DIS(1U)
60769 
60770 #define A_MC_DDRPHY_PC_CONFIG1 0x47034
60771 
60772 #define S_WRITE_LATENCY_OFFSET    12
60773 #define M_WRITE_LATENCY_OFFSET    0xfU
60774 #define V_WRITE_LATENCY_OFFSET(x) ((x) << S_WRITE_LATENCY_OFFSET)
60775 #define G_WRITE_LATENCY_OFFSET(x) (((x) >> S_WRITE_LATENCY_OFFSET) & M_WRITE_LATENCY_OFFSET)
60776 
60777 #define S_READ_LATENCY_OFFSET    8
60778 #define M_READ_LATENCY_OFFSET    0xfU
60779 #define V_READ_LATENCY_OFFSET(x) ((x) << S_READ_LATENCY_OFFSET)
60780 #define G_READ_LATENCY_OFFSET(x) (((x) >> S_READ_LATENCY_OFFSET) & M_READ_LATENCY_OFFSET)
60781 
60782 #define S_MEMCTL_CIC_FAST    7
60783 #define V_MEMCTL_CIC_FAST(x) ((x) << S_MEMCTL_CIC_FAST)
60784 #define F_MEMCTL_CIC_FAST    V_MEMCTL_CIC_FAST(1U)
60785 
60786 #define S_MEMCTL_CTRN_IGNORE    6
60787 #define V_MEMCTL_CTRN_IGNORE(x) ((x) << S_MEMCTL_CTRN_IGNORE)
60788 #define F_MEMCTL_CTRN_IGNORE    V_MEMCTL_CTRN_IGNORE(1U)
60789 
60790 #define S_DISABLE_MEMCTL_CAL    5
60791 #define V_DISABLE_MEMCTL_CAL(x) ((x) << S_DISABLE_MEMCTL_CAL)
60792 #define F_DISABLE_MEMCTL_CAL    V_DISABLE_MEMCTL_CAL(1U)
60793 
60794 #define S_MEMCTL_CIS_IGNORE    6
60795 #define V_MEMCTL_CIS_IGNORE(x) ((x) << S_MEMCTL_CIS_IGNORE)
60796 #define F_MEMCTL_CIS_IGNORE    V_MEMCTL_CIS_IGNORE(1U)
60797 
60798 #define S_MEMORY_TYPE    2
60799 #define M_MEMORY_TYPE    0x7U
60800 #define V_MEMORY_TYPE(x) ((x) << S_MEMORY_TYPE)
60801 #define G_MEMORY_TYPE(x) (((x) >> S_MEMORY_TYPE) & M_MEMORY_TYPE)
60802 
60803 #define S_DDR4_PDA_MODE    1
60804 #define V_DDR4_PDA_MODE(x) ((x) << S_DDR4_PDA_MODE)
60805 #define F_DDR4_PDA_MODE    V_DDR4_PDA_MODE(1U)
60806 
60807 #define A_MC_DDRPHY_PC_RESETS 0x47038
60808 
60809 #define S_PLL_RESET    15
60810 #define V_PLL_RESET(x) ((x) << S_PLL_RESET)
60811 #define F_PLL_RESET    V_PLL_RESET(1U)
60812 
60813 #define S_SYSCLK_RESET    14
60814 #define V_SYSCLK_RESET(x) ((x) << S_SYSCLK_RESET)
60815 #define F_SYSCLK_RESET    V_SYSCLK_RESET(1U)
60816 
60817 #define A_MC_DDRPHY_PC_PER_ZCAL_CONFIG 0x4703c
60818 
60819 #define S_PER_ZCAL_ENA_RANK    8
60820 #define M_PER_ZCAL_ENA_RANK    0xffU
60821 #define V_PER_ZCAL_ENA_RANK(x) ((x) << S_PER_ZCAL_ENA_RANK)
60822 #define G_PER_ZCAL_ENA_RANK(x) (((x) >> S_PER_ZCAL_ENA_RANK) & M_PER_ZCAL_ENA_RANK)
60823 
60824 #define S_PER_ZCAL_NEXT_RANK    5
60825 #define M_PER_ZCAL_NEXT_RANK    0x7U
60826 #define V_PER_ZCAL_NEXT_RANK(x) ((x) << S_PER_ZCAL_NEXT_RANK)
60827 #define G_PER_ZCAL_NEXT_RANK(x) (((x) >> S_PER_ZCAL_NEXT_RANK) & M_PER_ZCAL_NEXT_RANK)
60828 
60829 #define S_START_PER_ZCAL    4
60830 #define V_START_PER_ZCAL(x) ((x) << S_START_PER_ZCAL)
60831 #define F_START_PER_ZCAL    V_START_PER_ZCAL(1U)
60832 
60833 #define A_MC_DDRPHY_PC_RANK_GROUP 0x47044
60834 
60835 #define S_ADDR_MIRROR_RP0_PRI    15
60836 #define V_ADDR_MIRROR_RP0_PRI(x) ((x) << S_ADDR_MIRROR_RP0_PRI)
60837 #define F_ADDR_MIRROR_RP0_PRI    V_ADDR_MIRROR_RP0_PRI(1U)
60838 
60839 #define S_ADDR_MIRROR_RP0_SEC    14
60840 #define V_ADDR_MIRROR_RP0_SEC(x) ((x) << S_ADDR_MIRROR_RP0_SEC)
60841 #define F_ADDR_MIRROR_RP0_SEC    V_ADDR_MIRROR_RP0_SEC(1U)
60842 
60843 #define S_ADDR_MIRROR_RP1_PRI    13
60844 #define V_ADDR_MIRROR_RP1_PRI(x) ((x) << S_ADDR_MIRROR_RP1_PRI)
60845 #define F_ADDR_MIRROR_RP1_PRI    V_ADDR_MIRROR_RP1_PRI(1U)
60846 
60847 #define S_ADDR_MIRROR_RP1_SEC    12
60848 #define V_ADDR_MIRROR_RP1_SEC(x) ((x) << S_ADDR_MIRROR_RP1_SEC)
60849 #define F_ADDR_MIRROR_RP1_SEC    V_ADDR_MIRROR_RP1_SEC(1U)
60850 
60851 #define S_ADDR_MIRROR_RP2_PRI    11
60852 #define V_ADDR_MIRROR_RP2_PRI(x) ((x) << S_ADDR_MIRROR_RP2_PRI)
60853 #define F_ADDR_MIRROR_RP2_PRI    V_ADDR_MIRROR_RP2_PRI(1U)
60854 
60855 #define S_ADDR_MIRROR_RP2_SEC    10
60856 #define V_ADDR_MIRROR_RP2_SEC(x) ((x) << S_ADDR_MIRROR_RP2_SEC)
60857 #define F_ADDR_MIRROR_RP2_SEC    V_ADDR_MIRROR_RP2_SEC(1U)
60858 
60859 #define S_ADDR_MIRROR_RP3_PRI    9
60860 #define V_ADDR_MIRROR_RP3_PRI(x) ((x) << S_ADDR_MIRROR_RP3_PRI)
60861 #define F_ADDR_MIRROR_RP3_PRI    V_ADDR_MIRROR_RP3_PRI(1U)
60862 
60863 #define S_ADDR_MIRROR_RP3_SEC    8
60864 #define V_ADDR_MIRROR_RP3_SEC(x) ((x) << S_ADDR_MIRROR_RP3_SEC)
60865 #define F_ADDR_MIRROR_RP3_SEC    V_ADDR_MIRROR_RP3_SEC(1U)
60866 
60867 #define S_RANK_GROUPING    6
60868 #define M_RANK_GROUPING    0x3U
60869 #define V_RANK_GROUPING(x) ((x) << S_RANK_GROUPING)
60870 #define G_RANK_GROUPING(x) (((x) >> S_RANK_GROUPING) & M_RANK_GROUPING)
60871 
60872 #define S_ADDR_MIRROR_A3_A4    5
60873 #define V_ADDR_MIRROR_A3_A4(x) ((x) << S_ADDR_MIRROR_A3_A4)
60874 #define F_ADDR_MIRROR_A3_A4    V_ADDR_MIRROR_A3_A4(1U)
60875 
60876 #define S_ADDR_MIRROR_A5_A6    4
60877 #define V_ADDR_MIRROR_A5_A6(x) ((x) << S_ADDR_MIRROR_A5_A6)
60878 #define F_ADDR_MIRROR_A5_A6    V_ADDR_MIRROR_A5_A6(1U)
60879 
60880 #define S_ADDR_MIRROR_A7_A8    3
60881 #define V_ADDR_MIRROR_A7_A8(x) ((x) << S_ADDR_MIRROR_A7_A8)
60882 #define F_ADDR_MIRROR_A7_A8    V_ADDR_MIRROR_A7_A8(1U)
60883 
60884 #define S_ADDR_MIRROR_A11_A13    2
60885 #define V_ADDR_MIRROR_A11_A13(x) ((x) << S_ADDR_MIRROR_A11_A13)
60886 #define F_ADDR_MIRROR_A11_A13    V_ADDR_MIRROR_A11_A13(1U)
60887 
60888 #define S_ADDR_MIRROR_BA0_BA1    1
60889 #define V_ADDR_MIRROR_BA0_BA1(x) ((x) << S_ADDR_MIRROR_BA0_BA1)
60890 #define F_ADDR_MIRROR_BA0_BA1    V_ADDR_MIRROR_BA0_BA1(1U)
60891 
60892 #define S_ADDR_MIRROR_BG0_BG1    0
60893 #define V_ADDR_MIRROR_BG0_BG1(x) ((x) << S_ADDR_MIRROR_BG0_BG1)
60894 #define F_ADDR_MIRROR_BG0_BG1    V_ADDR_MIRROR_BG0_BG1(1U)
60895 
60896 #define A_MC_DDRPHY_PC_ERROR_STATUS0 0x47048
60897 
60898 #define S_RC_ERROR    15
60899 #define V_RC_ERROR(x) ((x) << S_RC_ERROR)
60900 #define F_RC_ERROR    V_RC_ERROR(1U)
60901 
60902 #define S_WC_ERROR    14
60903 #define V_WC_ERROR(x) ((x) << S_WC_ERROR)
60904 #define F_WC_ERROR    V_WC_ERROR(1U)
60905 
60906 #define S_SEQ_ERROR    13
60907 #define V_SEQ_ERROR(x) ((x) << S_SEQ_ERROR)
60908 #define F_SEQ_ERROR    V_SEQ_ERROR(1U)
60909 
60910 #define S_CC_ERROR    12
60911 #define V_CC_ERROR(x) ((x) << S_CC_ERROR)
60912 #define F_CC_ERROR    V_CC_ERROR(1U)
60913 
60914 #define S_APB_ERROR    11
60915 #define V_APB_ERROR(x) ((x) << S_APB_ERROR)
60916 #define F_APB_ERROR    V_APB_ERROR(1U)
60917 
60918 #define S_PC_ERROR    10
60919 #define V_PC_ERROR(x) ((x) << S_PC_ERROR)
60920 #define F_PC_ERROR    V_PC_ERROR(1U)
60921 
60922 #define A_MC_DDRPHY_PC_ERROR_MASK0 0x4704c
60923 
60924 #define S_RC_ERROR_MASK    15
60925 #define V_RC_ERROR_MASK(x) ((x) << S_RC_ERROR_MASK)
60926 #define F_RC_ERROR_MASK    V_RC_ERROR_MASK(1U)
60927 
60928 #define S_WC_ERROR_MASK    14
60929 #define V_WC_ERROR_MASK(x) ((x) << S_WC_ERROR_MASK)
60930 #define F_WC_ERROR_MASK    V_WC_ERROR_MASK(1U)
60931 
60932 #define S_SEQ_ERROR_MASK    13
60933 #define V_SEQ_ERROR_MASK(x) ((x) << S_SEQ_ERROR_MASK)
60934 #define F_SEQ_ERROR_MASK    V_SEQ_ERROR_MASK(1U)
60935 
60936 #define S_CC_ERROR_MASK    12
60937 #define V_CC_ERROR_MASK(x) ((x) << S_CC_ERROR_MASK)
60938 #define F_CC_ERROR_MASK    V_CC_ERROR_MASK(1U)
60939 
60940 #define S_APB_ERROR_MASK    11
60941 #define V_APB_ERROR_MASK(x) ((x) << S_APB_ERROR_MASK)
60942 #define F_APB_ERROR_MASK    V_APB_ERROR_MASK(1U)
60943 
60944 #define S_PC_ERROR_MASK    10
60945 #define V_PC_ERROR_MASK(x) ((x) << S_PC_ERROR_MASK)
60946 #define F_PC_ERROR_MASK    V_PC_ERROR_MASK(1U)
60947 
60948 #define A_MC_DDRPHY_PC_IO_PVT_FET_CONTROL 0x47050
60949 
60950 #define S_PVTP    11
60951 #define M_PVTP    0x1fU
60952 #define V_PVTP(x) ((x) << S_PVTP)
60953 #define G_PVTP(x) (((x) >> S_PVTP) & M_PVTP)
60954 
60955 #define S_PVTN    6
60956 #define M_PVTN    0x1fU
60957 #define V_PVTN(x) ((x) << S_PVTN)
60958 #define G_PVTN(x) (((x) >> S_PVTN) & M_PVTN)
60959 
60960 #define S_PVT_OVERRIDE    5
60961 #define V_PVT_OVERRIDE(x) ((x) << S_PVT_OVERRIDE)
60962 #define F_PVT_OVERRIDE    V_PVT_OVERRIDE(1U)
60963 
60964 #define S_ENABLE_ZCAL    4
60965 #define V_ENABLE_ZCAL(x) ((x) << S_ENABLE_ZCAL)
60966 #define F_ENABLE_ZCAL    V_ENABLE_ZCAL(1U)
60967 
60968 #define A_MC_DDRPHY_PC_VREF_DRV_CONTROL 0x47054
60969 
60970 #define S_VREFDQ0DSGN    15
60971 #define V_VREFDQ0DSGN(x) ((x) << S_VREFDQ0DSGN)
60972 #define F_VREFDQ0DSGN    V_VREFDQ0DSGN(1U)
60973 
60974 #define S_VREFDQ0D    11
60975 #define M_VREFDQ0D    0xfU
60976 #define V_VREFDQ0D(x) ((x) << S_VREFDQ0D)
60977 #define G_VREFDQ0D(x) (((x) >> S_VREFDQ0D) & M_VREFDQ0D)
60978 
60979 #define S_VREFDQ1DSGN    10
60980 #define V_VREFDQ1DSGN(x) ((x) << S_VREFDQ1DSGN)
60981 #define F_VREFDQ1DSGN    V_VREFDQ1DSGN(1U)
60982 
60983 #define S_VREFDQ1D    6
60984 #define M_VREFDQ1D    0xfU
60985 #define V_VREFDQ1D(x) ((x) << S_VREFDQ1D)
60986 #define G_VREFDQ1D(x) (((x) >> S_VREFDQ1D) & M_VREFDQ1D)
60987 
60988 #define S_EN_ANALOG_PD    3
60989 #define V_EN_ANALOG_PD(x) ((x) << S_EN_ANALOG_PD)
60990 #define F_EN_ANALOG_PD    V_EN_ANALOG_PD(1U)
60991 
60992 #define S_ANALOG_PD_DLY    2
60993 #define V_ANALOG_PD_DLY(x) ((x) << S_ANALOG_PD_DLY)
60994 #define F_ANALOG_PD_DLY    V_ANALOG_PD_DLY(1U)
60995 
60996 #define S_ANALOG_PD_DIV    0
60997 #define M_ANALOG_PD_DIV    0x3U
60998 #define V_ANALOG_PD_DIV(x) ((x) << S_ANALOG_PD_DIV)
60999 #define G_ANALOG_PD_DIV(x) (((x) >> S_ANALOG_PD_DIV) & M_ANALOG_PD_DIV)
61000 
61001 #define A_MC_DDRPHY_PC_INIT_CAL_CONFIG0 0x47058
61002 
61003 #define S_ENA_WR_LEVEL    15
61004 #define V_ENA_WR_LEVEL(x) ((x) << S_ENA_WR_LEVEL)
61005 #define F_ENA_WR_LEVEL    V_ENA_WR_LEVEL(1U)
61006 
61007 #define S_ENA_INITIAL_PAT_WR    14
61008 #define V_ENA_INITIAL_PAT_WR(x) ((x) << S_ENA_INITIAL_PAT_WR)
61009 #define F_ENA_INITIAL_PAT_WR    V_ENA_INITIAL_PAT_WR(1U)
61010 
61011 #define S_ENA_DQS_ALIGN    13
61012 #define V_ENA_DQS_ALIGN(x) ((x) << S_ENA_DQS_ALIGN)
61013 #define F_ENA_DQS_ALIGN    V_ENA_DQS_ALIGN(1U)
61014 
61015 #define S_ENA_RDCLK_ALIGN    12
61016 #define V_ENA_RDCLK_ALIGN(x) ((x) << S_ENA_RDCLK_ALIGN)
61017 #define F_ENA_RDCLK_ALIGN    V_ENA_RDCLK_ALIGN(1U)
61018 
61019 #define S_ENA_READ_CTR    11
61020 #define V_ENA_READ_CTR(x) ((x) << S_ENA_READ_CTR)
61021 #define F_ENA_READ_CTR    V_ENA_READ_CTR(1U)
61022 
61023 #define S_ENA_WRITE_CTR    10
61024 #define V_ENA_WRITE_CTR(x) ((x) << S_ENA_WRITE_CTR)
61025 #define F_ENA_WRITE_CTR    V_ENA_WRITE_CTR(1U)
61026 
61027 #define S_ENA_INITIAL_COARSE_WR    9
61028 #define V_ENA_INITIAL_COARSE_WR(x) ((x) << S_ENA_INITIAL_COARSE_WR)
61029 #define F_ENA_INITIAL_COARSE_WR    V_ENA_INITIAL_COARSE_WR(1U)
61030 
61031 #define S_ENA_COARSE_RD    8
61032 #define V_ENA_COARSE_RD(x) ((x) << S_ENA_COARSE_RD)
61033 #define F_ENA_COARSE_RD    V_ENA_COARSE_RD(1U)
61034 
61035 #define S_ENA_CUSTOM_RD    7
61036 #define V_ENA_CUSTOM_RD(x) ((x) << S_ENA_CUSTOM_RD)
61037 #define F_ENA_CUSTOM_RD    V_ENA_CUSTOM_RD(1U)
61038 
61039 #define S_ENA_CUSTOM_WR    6
61040 #define V_ENA_CUSTOM_WR(x) ((x) << S_ENA_CUSTOM_WR)
61041 #define F_ENA_CUSTOM_WR    V_ENA_CUSTOM_WR(1U)
61042 
61043 #define S_ABORT_ON_CAL_ERROR    5
61044 #define V_ABORT_ON_CAL_ERROR(x) ((x) << S_ABORT_ON_CAL_ERROR)
61045 #define F_ABORT_ON_CAL_ERROR    V_ABORT_ON_CAL_ERROR(1U)
61046 
61047 #define S_ENA_DIGITAL_EYE    4
61048 #define V_ENA_DIGITAL_EYE(x) ((x) << S_ENA_DIGITAL_EYE)
61049 #define F_ENA_DIGITAL_EYE    V_ENA_DIGITAL_EYE(1U)
61050 
61051 #define S_ENA_RANK_PAIR    0
61052 #define M_ENA_RANK_PAIR    0xfU
61053 #define V_ENA_RANK_PAIR(x) ((x) << S_ENA_RANK_PAIR)
61054 #define G_ENA_RANK_PAIR(x) (((x) >> S_ENA_RANK_PAIR) & M_ENA_RANK_PAIR)
61055 
61056 #define A_MC_DDRPHY_PC_INIT_CAL_CONFIG1 0x4705c
61057 
61058 #define S_REFRESH_COUNT    12
61059 #define M_REFRESH_COUNT    0xfU
61060 #define V_REFRESH_COUNT(x) ((x) << S_REFRESH_COUNT)
61061 #define G_REFRESH_COUNT(x) (((x) >> S_REFRESH_COUNT) & M_REFRESH_COUNT)
61062 
61063 #define S_REFRESH_CONTROL    10
61064 #define M_REFRESH_CONTROL    0x3U
61065 #define V_REFRESH_CONTROL(x) ((x) << S_REFRESH_CONTROL)
61066 #define G_REFRESH_CONTROL(x) (((x) >> S_REFRESH_CONTROL) & M_REFRESH_CONTROL)
61067 
61068 #define S_REFRESH_ALL_RANKS    9
61069 #define V_REFRESH_ALL_RANKS(x) ((x) << S_REFRESH_ALL_RANKS)
61070 #define F_REFRESH_ALL_RANKS    V_REFRESH_ALL_RANKS(1U)
61071 
61072 #define S_REFRESH_INTERVAL    0
61073 #define M_REFRESH_INTERVAL    0x7fU
61074 #define V_REFRESH_INTERVAL(x) ((x) << S_REFRESH_INTERVAL)
61075 #define G_REFRESH_INTERVAL(x) (((x) >> S_REFRESH_INTERVAL) & M_REFRESH_INTERVAL)
61076 
61077 #define A_MC_DDRPHY_PC_INIT_CAL_ERROR 0x47060
61078 
61079 #define S_ERROR_WR_LEVEL    15
61080 #define V_ERROR_WR_LEVEL(x) ((x) << S_ERROR_WR_LEVEL)
61081 #define F_ERROR_WR_LEVEL    V_ERROR_WR_LEVEL(1U)
61082 
61083 #define S_ERROR_INITIAL_PAT_WRITE    14
61084 #define V_ERROR_INITIAL_PAT_WRITE(x) ((x) << S_ERROR_INITIAL_PAT_WRITE)
61085 #define F_ERROR_INITIAL_PAT_WRITE    V_ERROR_INITIAL_PAT_WRITE(1U)
61086 
61087 #define S_ERROR_DQS_ALIGN    13
61088 #define V_ERROR_DQS_ALIGN(x) ((x) << S_ERROR_DQS_ALIGN)
61089 #define F_ERROR_DQS_ALIGN    V_ERROR_DQS_ALIGN(1U)
61090 
61091 #define S_ERROR_RDCLK_ALIGN    12
61092 #define V_ERROR_RDCLK_ALIGN(x) ((x) << S_ERROR_RDCLK_ALIGN)
61093 #define F_ERROR_RDCLK_ALIGN    V_ERROR_RDCLK_ALIGN(1U)
61094 
61095 #define S_ERROR_READ_CTR    11
61096 #define V_ERROR_READ_CTR(x) ((x) << S_ERROR_READ_CTR)
61097 #define F_ERROR_READ_CTR    V_ERROR_READ_CTR(1U)
61098 
61099 #define S_ERROR_WRITE_CTR    10
61100 #define V_ERROR_WRITE_CTR(x) ((x) << S_ERROR_WRITE_CTR)
61101 #define F_ERROR_WRITE_CTR    V_ERROR_WRITE_CTR(1U)
61102 
61103 #define S_ERROR_INITIAL_COARSE_WR    9
61104 #define V_ERROR_INITIAL_COARSE_WR(x) ((x) << S_ERROR_INITIAL_COARSE_WR)
61105 #define F_ERROR_INITIAL_COARSE_WR    V_ERROR_INITIAL_COARSE_WR(1U)
61106 
61107 #define S_ERROR_COARSE_RD    8
61108 #define V_ERROR_COARSE_RD(x) ((x) << S_ERROR_COARSE_RD)
61109 #define F_ERROR_COARSE_RD    V_ERROR_COARSE_RD(1U)
61110 
61111 #define S_ERROR_CUSTOM_RD    7
61112 #define V_ERROR_CUSTOM_RD(x) ((x) << S_ERROR_CUSTOM_RD)
61113 #define F_ERROR_CUSTOM_RD    V_ERROR_CUSTOM_RD(1U)
61114 
61115 #define S_ERROR_CUSTOM_WR    6
61116 #define V_ERROR_CUSTOM_WR(x) ((x) << S_ERROR_CUSTOM_WR)
61117 #define F_ERROR_CUSTOM_WR    V_ERROR_CUSTOM_WR(1U)
61118 
61119 #define S_ERROR_DIGITAL_EYE    5
61120 #define V_ERROR_DIGITAL_EYE(x) ((x) << S_ERROR_DIGITAL_EYE)
61121 #define F_ERROR_DIGITAL_EYE    V_ERROR_DIGITAL_EYE(1U)
61122 
61123 #define S_ERROR_RANK_PAIR    0
61124 #define M_ERROR_RANK_PAIR    0xfU
61125 #define V_ERROR_RANK_PAIR(x) ((x) << S_ERROR_RANK_PAIR)
61126 #define G_ERROR_RANK_PAIR(x) (((x) >> S_ERROR_RANK_PAIR) & M_ERROR_RANK_PAIR)
61127 
61128 #define A_MC_DDRPHY_PC_INIT_CAL_STATUS 0x47064
61129 
61130 #define S_INIT_CAL_COMPLETE    12
61131 #define M_INIT_CAL_COMPLETE    0xfU
61132 #define V_INIT_CAL_COMPLETE(x) ((x) << S_INIT_CAL_COMPLETE)
61133 #define G_INIT_CAL_COMPLETE(x) (((x) >> S_INIT_CAL_COMPLETE) & M_INIT_CAL_COMPLETE)
61134 
61135 #define S_PER_CAL_ABORT    6
61136 #define V_PER_CAL_ABORT(x) ((x) << S_PER_CAL_ABORT)
61137 #define F_PER_CAL_ABORT    V_PER_CAL_ABORT(1U)
61138 
61139 #define A_MC_DDRPHY_PC_INIT_CAL_MASK 0x47068
61140 
61141 #define S_ERROR_WR_LEVEL_MASK    15
61142 #define V_ERROR_WR_LEVEL_MASK(x) ((x) << S_ERROR_WR_LEVEL_MASK)
61143 #define F_ERROR_WR_LEVEL_MASK    V_ERROR_WR_LEVEL_MASK(1U)
61144 
61145 #define S_ERROR_INITIAL_PAT_WRITE_MASK    14
61146 #define V_ERROR_INITIAL_PAT_WRITE_MASK(x) ((x) << S_ERROR_INITIAL_PAT_WRITE_MASK)
61147 #define F_ERROR_INITIAL_PAT_WRITE_MASK    V_ERROR_INITIAL_PAT_WRITE_MASK(1U)
61148 
61149 #define S_ERROR_DQS_ALIGN_MASK    13
61150 #define V_ERROR_DQS_ALIGN_MASK(x) ((x) << S_ERROR_DQS_ALIGN_MASK)
61151 #define F_ERROR_DQS_ALIGN_MASK    V_ERROR_DQS_ALIGN_MASK(1U)
61152 
61153 #define S_ERROR_RDCLK_ALIGN_MASK    12
61154 #define V_ERROR_RDCLK_ALIGN_MASK(x) ((x) << S_ERROR_RDCLK_ALIGN_MASK)
61155 #define F_ERROR_RDCLK_ALIGN_MASK    V_ERROR_RDCLK_ALIGN_MASK(1U)
61156 
61157 #define S_ERROR_READ_CTR_MASK    11
61158 #define V_ERROR_READ_CTR_MASK(x) ((x) << S_ERROR_READ_CTR_MASK)
61159 #define F_ERROR_READ_CTR_MASK    V_ERROR_READ_CTR_MASK(1U)
61160 
61161 #define S_ERROR_WRITE_CTR_MASK    10
61162 #define V_ERROR_WRITE_CTR_MASK(x) ((x) << S_ERROR_WRITE_CTR_MASK)
61163 #define F_ERROR_WRITE_CTR_MASK    V_ERROR_WRITE_CTR_MASK(1U)
61164 
61165 #define S_ERROR_INITIAL_COARSE_WR_MASK    9
61166 #define V_ERROR_INITIAL_COARSE_WR_MASK(x) ((x) << S_ERROR_INITIAL_COARSE_WR_MASK)
61167 #define F_ERROR_INITIAL_COARSE_WR_MASK    V_ERROR_INITIAL_COARSE_WR_MASK(1U)
61168 
61169 #define S_ERROR_COARSE_RD_MASK    8
61170 #define V_ERROR_COARSE_RD_MASK(x) ((x) << S_ERROR_COARSE_RD_MASK)
61171 #define F_ERROR_COARSE_RD_MASK    V_ERROR_COARSE_RD_MASK(1U)
61172 
61173 #define S_ERROR_CUSTOM_RD_MASK    7
61174 #define V_ERROR_CUSTOM_RD_MASK(x) ((x) << S_ERROR_CUSTOM_RD_MASK)
61175 #define F_ERROR_CUSTOM_RD_MASK    V_ERROR_CUSTOM_RD_MASK(1U)
61176 
61177 #define S_ERROR_CUSTOM_WR_MASK    6
61178 #define V_ERROR_CUSTOM_WR_MASK(x) ((x) << S_ERROR_CUSTOM_WR_MASK)
61179 #define F_ERROR_CUSTOM_WR_MASK    V_ERROR_CUSTOM_WR_MASK(1U)
61180 
61181 #define S_ERROR_DIGITAL_EYE_MASK    5
61182 #define V_ERROR_DIGITAL_EYE_MASK(x) ((x) << S_ERROR_DIGITAL_EYE_MASK)
61183 #define F_ERROR_DIGITAL_EYE_MASK    V_ERROR_DIGITAL_EYE_MASK(1U)
61184 
61185 #define A_MC_DDRPHY_PC_IO_PVT_FET_STATUS 0x4706c
61186 #define A_MC_DDRPHY_PC_MR0_PRI_RP 0x47070
61187 
61188 #define S_MODEREGISTER0VALUE    0
61189 #define M_MODEREGISTER0VALUE    0xffffU
61190 #define V_MODEREGISTER0VALUE(x) ((x) << S_MODEREGISTER0VALUE)
61191 #define G_MODEREGISTER0VALUE(x) (((x) >> S_MODEREGISTER0VALUE) & M_MODEREGISTER0VALUE)
61192 
61193 #define A_MC_DDRPHY_PC_MR1_PRI_RP 0x47074
61194 
61195 #define S_MODEREGISTER1VALUE    0
61196 #define M_MODEREGISTER1VALUE    0xffffU
61197 #define V_MODEREGISTER1VALUE(x) ((x) << S_MODEREGISTER1VALUE)
61198 #define G_MODEREGISTER1VALUE(x) (((x) >> S_MODEREGISTER1VALUE) & M_MODEREGISTER1VALUE)
61199 
61200 #define A_MC_DDRPHY_PC_MR2_PRI_RP 0x47078
61201 
61202 #define S_MODEREGISTER2VALUE    0
61203 #define M_MODEREGISTER2VALUE    0xffffU
61204 #define V_MODEREGISTER2VALUE(x) ((x) << S_MODEREGISTER2VALUE)
61205 #define G_MODEREGISTER2VALUE(x) (((x) >> S_MODEREGISTER2VALUE) & M_MODEREGISTER2VALUE)
61206 
61207 #define A_MC_DDRPHY_PC_MR3_PRI_RP 0x4707c
61208 
61209 #define S_MODEREGISTER3VALUE    0
61210 #define M_MODEREGISTER3VALUE    0xffffU
61211 #define V_MODEREGISTER3VALUE(x) ((x) << S_MODEREGISTER3VALUE)
61212 #define G_MODEREGISTER3VALUE(x) (((x) >> S_MODEREGISTER3VALUE) & M_MODEREGISTER3VALUE)
61213 
61214 #define A_MC_DDRPHY_PC_MR0_SEC_RP 0x47080
61215 #define A_MC_DDRPHY_PC_MR1_SEC_RP 0x47084
61216 #define A_MC_DDRPHY_PC_MR2_SEC_RP 0x47088
61217 #define A_MC_DDRPHY_PC_MR3_SEC_RP 0x4708c
61218 
61219 #define S_MODE_REGISTER_3_VALUE    0
61220 #define M_MODE_REGISTER_3_VALUE    0xffffU
61221 #define V_MODE_REGISTER_3_VALUE(x) ((x) << S_MODE_REGISTER_3_VALUE)
61222 #define G_MODE_REGISTER_3_VALUE(x) (((x) >> S_MODE_REGISTER_3_VALUE) & M_MODE_REGISTER_3_VALUE)
61223 
61224 #define A_MC_DDRPHY_SEQ_RD_WR_DATA0 0x47200
61225 
61226 #define S_DRD_WR_DATA_REG    0
61227 #define M_DRD_WR_DATA_REG    0xffffU
61228 #define V_DRD_WR_DATA_REG(x) ((x) << S_DRD_WR_DATA_REG)
61229 #define G_DRD_WR_DATA_REG(x) (((x) >> S_DRD_WR_DATA_REG) & M_DRD_WR_DATA_REG)
61230 
61231 #define A_MC_DDRPHY_SEQ_RD_WR_DATA1 0x47204
61232 #define A_MC_DDRPHY_SEQ_CONFIG0 0x47208
61233 
61234 #define S_MPR_PATTERN_BIT    15
61235 #define V_MPR_PATTERN_BIT(x) ((x) << S_MPR_PATTERN_BIT)
61236 #define F_MPR_PATTERN_BIT    V_MPR_PATTERN_BIT(1U)
61237 
61238 #define S_TWO_CYCLE_ADDR_EN    14
61239 #define V_TWO_CYCLE_ADDR_EN(x) ((x) << S_TWO_CYCLE_ADDR_EN)
61240 #define F_TWO_CYCLE_ADDR_EN    V_TWO_CYCLE_ADDR_EN(1U)
61241 
61242 #define S_MR_MASK_EN    10
61243 #define M_MR_MASK_EN    0xfU
61244 #define V_MR_MASK_EN(x) ((x) << S_MR_MASK_EN)
61245 #define G_MR_MASK_EN(x) (((x) >> S_MR_MASK_EN) & M_MR_MASK_EN)
61246 
61247 #define S_PARITY_DLY    9
61248 #define V_PARITY_DLY(x) ((x) << S_PARITY_DLY)
61249 #define F_PARITY_DLY    V_PARITY_DLY(1U)
61250 
61251 #define S_FORCE_RESERVED    7
61252 #define V_FORCE_RESERVED(x) ((x) << S_FORCE_RESERVED)
61253 #define F_FORCE_RESERVED    V_FORCE_RESERVED(1U)
61254 
61255 #define S_HALT_ROTATION    6
61256 #define V_HALT_ROTATION(x) ((x) << S_HALT_ROTATION)
61257 #define F_HALT_ROTATION    V_HALT_ROTATION(1U)
61258 
61259 #define S_FORCE_MPR    5
61260 #define V_FORCE_MPR(x) ((x) << S_FORCE_MPR)
61261 #define F_FORCE_MPR    V_FORCE_MPR(1U)
61262 
61263 #define S_IPW_SIDEAB_SEL    2
61264 #define V_IPW_SIDEAB_SEL(x) ((x) << S_IPW_SIDEAB_SEL)
61265 #define F_IPW_SIDEAB_SEL    V_IPW_SIDEAB_SEL(1U)
61266 
61267 #define S_PARITY_A17_MASK    1
61268 #define V_PARITY_A17_MASK(x) ((x) << S_PARITY_A17_MASK)
61269 #define F_PARITY_A17_MASK    V_PARITY_A17_MASK(1U)
61270 
61271 #define S_X16_DEVICE    0
61272 #define V_X16_DEVICE(x) ((x) << S_X16_DEVICE)
61273 #define F_X16_DEVICE    V_X16_DEVICE(1U)
61274 
61275 #define A_MC_DDRPHY_SEQ_RESERVED_ADDR0 0x4720c
61276 #define A_MC_DDRPHY_SEQ_RESERVED_ADDR1 0x47210
61277 #define A_MC_DDRPHY_SEQ_RESERVED_ADDR2 0x47214
61278 #define A_MC_DDRPHY_SEQ_RESERVED_ADDR3 0x47218
61279 #define A_MC_DDRPHY_SEQ_RESERVED_ADDR4 0x4721c
61280 #define A_MC_DDRPHY_SEQ_ERROR_STATUS0 0x47220
61281 
61282 #define S_MULTIPLE_REQ_ERROR    15
61283 #define V_MULTIPLE_REQ_ERROR(x) ((x) << S_MULTIPLE_REQ_ERROR)
61284 #define F_MULTIPLE_REQ_ERROR    V_MULTIPLE_REQ_ERROR(1U)
61285 
61286 #define S_INVALID_REQTYPE_ERRO    14
61287 #define V_INVALID_REQTYPE_ERRO(x) ((x) << S_INVALID_REQTYPE_ERRO)
61288 #define F_INVALID_REQTYPE_ERRO    V_INVALID_REQTYPE_ERRO(1U)
61289 
61290 #define S_EARLY_REQ_ERROR    13
61291 #define V_EARLY_REQ_ERROR(x) ((x) << S_EARLY_REQ_ERROR)
61292 #define F_EARLY_REQ_ERROR    V_EARLY_REQ_ERROR(1U)
61293 
61294 #define S_MULTIPLE_REQ_SOURCE    10
61295 #define M_MULTIPLE_REQ_SOURCE    0x7U
61296 #define V_MULTIPLE_REQ_SOURCE(x) ((x) << S_MULTIPLE_REQ_SOURCE)
61297 #define G_MULTIPLE_REQ_SOURCE(x) (((x) >> S_MULTIPLE_REQ_SOURCE) & M_MULTIPLE_REQ_SOURCE)
61298 
61299 #define S_INVALID_REQTYPE    6
61300 #define M_INVALID_REQTYPE    0xfU
61301 #define V_INVALID_REQTYPE(x) ((x) << S_INVALID_REQTYPE)
61302 #define G_INVALID_REQTYPE(x) (((x) >> S_INVALID_REQTYPE) & M_INVALID_REQTYPE)
61303 
61304 #define S_INVALID_REQ_SOURCE    3
61305 #define M_INVALID_REQ_SOURCE    0x7U
61306 #define V_INVALID_REQ_SOURCE(x) ((x) << S_INVALID_REQ_SOURCE)
61307 #define G_INVALID_REQ_SOURCE(x) (((x) >> S_INVALID_REQ_SOURCE) & M_INVALID_REQ_SOURCE)
61308 
61309 #define S_EARLY_REQ_SOURCE    0
61310 #define M_EARLY_REQ_SOURCE    0x7U
61311 #define V_EARLY_REQ_SOURCE(x) ((x) << S_EARLY_REQ_SOURCE)
61312 #define G_EARLY_REQ_SOURCE(x) (((x) >> S_EARLY_REQ_SOURCE) & M_EARLY_REQ_SOURCE)
61313 
61314 #define A_MC_DDRPHY_SEQ_ERROR_MASK0 0x47224
61315 
61316 #define S_MULT_REQ_ERR_MASK    15
61317 #define V_MULT_REQ_ERR_MASK(x) ((x) << S_MULT_REQ_ERR_MASK)
61318 #define F_MULT_REQ_ERR_MASK    V_MULT_REQ_ERR_MASK(1U)
61319 
61320 #define S_INVALID_REQTYPE_ERR_MASK    14
61321 #define V_INVALID_REQTYPE_ERR_MASK(x) ((x) << S_INVALID_REQTYPE_ERR_MASK)
61322 #define F_INVALID_REQTYPE_ERR_MASK    V_INVALID_REQTYPE_ERR_MASK(1U)
61323 
61324 #define S_EARLY_REQ_ERR_MASK    13
61325 #define V_EARLY_REQ_ERR_MASK(x) ((x) << S_EARLY_REQ_ERR_MASK)
61326 #define F_EARLY_REQ_ERR_MASK    V_EARLY_REQ_ERR_MASK(1U)
61327 
61328 #define A_MC_DDRPHY_SEQ_ODT_WR_CONFIG0 0x47228
61329 
61330 #define S_ODT_WR_VALUES_BITS0_7    8
61331 #define M_ODT_WR_VALUES_BITS0_7    0xffU
61332 #define V_ODT_WR_VALUES_BITS0_7(x) ((x) << S_ODT_WR_VALUES_BITS0_7)
61333 #define G_ODT_WR_VALUES_BITS0_7(x) (((x) >> S_ODT_WR_VALUES_BITS0_7) & M_ODT_WR_VALUES_BITS0_7)
61334 
61335 #define S_ODT_WR_VALUES_BITS8_15    0
61336 #define M_ODT_WR_VALUES_BITS8_15    0xffU
61337 #define V_ODT_WR_VALUES_BITS8_15(x) ((x) << S_ODT_WR_VALUES_BITS8_15)
61338 #define G_ODT_WR_VALUES_BITS8_15(x) (((x) >> S_ODT_WR_VALUES_BITS8_15) & M_ODT_WR_VALUES_BITS8_15)
61339 
61340 #define A_MC_DDRPHY_SEQ_ODT_WR_CONFIG1 0x4722c
61341 #define A_MC_DDRPHY_SEQ_ODT_WR_CONFIG2 0x47230
61342 #define A_MC_DDRPHY_SEQ_ODT_WR_CONFIG3 0x47234
61343 #define A_MC_DDRPHY_SEQ_ODT_RD_CONFIG0 0x47238
61344 
61345 #define S_ODT_RD_VALUES_X2    8
61346 #define M_ODT_RD_VALUES_X2    0xffU
61347 #define V_ODT_RD_VALUES_X2(x) ((x) << S_ODT_RD_VALUES_X2)
61348 #define G_ODT_RD_VALUES_X2(x) (((x) >> S_ODT_RD_VALUES_X2) & M_ODT_RD_VALUES_X2)
61349 
61350 #define S_ODT_RD_VALUES_X2PLUS1    0
61351 #define M_ODT_RD_VALUES_X2PLUS1    0xffU
61352 #define V_ODT_RD_VALUES_X2PLUS1(x) ((x) << S_ODT_RD_VALUES_X2PLUS1)
61353 #define G_ODT_RD_VALUES_X2PLUS1(x) (((x) >> S_ODT_RD_VALUES_X2PLUS1) & M_ODT_RD_VALUES_X2PLUS1)
61354 
61355 #define A_MC_DDRPHY_SEQ_ODT_RD_CONFIG1 0x4723c
61356 #define A_MC_DDRPHY_SEQ_ODT_RD_CONFIG2 0x47240
61357 #define A_MC_DDRPHY_SEQ_ODT_RD_CONFIG3 0x47244
61358 #define A_MC_DDRPHY_SEQ_MEM_TIMING_PARAM0 0x47248
61359 
61360 #define S_TMOD_CYCLES    12
61361 #define M_TMOD_CYCLES    0xfU
61362 #define V_TMOD_CYCLES(x) ((x) << S_TMOD_CYCLES)
61363 #define G_TMOD_CYCLES(x) (((x) >> S_TMOD_CYCLES) & M_TMOD_CYCLES)
61364 
61365 #define S_TRCD_CYCLES    8
61366 #define M_TRCD_CYCLES    0xfU
61367 #define V_TRCD_CYCLES(x) ((x) << S_TRCD_CYCLES)
61368 #define G_TRCD_CYCLES(x) (((x) >> S_TRCD_CYCLES) & M_TRCD_CYCLES)
61369 
61370 #define S_TRP_CYCLES    4
61371 #define M_TRP_CYCLES    0xfU
61372 #define V_TRP_CYCLES(x) ((x) << S_TRP_CYCLES)
61373 #define G_TRP_CYCLES(x) (((x) >> S_TRP_CYCLES) & M_TRP_CYCLES)
61374 
61375 #define S_TRFC_CYCLES    0
61376 #define M_TRFC_CYCLES    0xfU
61377 #define V_TRFC_CYCLES(x) ((x) << S_TRFC_CYCLES)
61378 #define G_TRFC_CYCLES(x) (((x) >> S_TRFC_CYCLES) & M_TRFC_CYCLES)
61379 
61380 #define A_MC_DDRPHY_SEQ_MEM_TIMING_PARAM1 0x4724c
61381 
61382 #define S_TZQINIT_CYCLES    12
61383 #define M_TZQINIT_CYCLES    0xfU
61384 #define V_TZQINIT_CYCLES(x) ((x) << S_TZQINIT_CYCLES)
61385 #define G_TZQINIT_CYCLES(x) (((x) >> S_TZQINIT_CYCLES) & M_TZQINIT_CYCLES)
61386 
61387 #define S_TZQCS_CYCLES    8
61388 #define M_TZQCS_CYCLES    0xfU
61389 #define V_TZQCS_CYCLES(x) ((x) << S_TZQCS_CYCLES)
61390 #define G_TZQCS_CYCLES(x) (((x) >> S_TZQCS_CYCLES) & M_TZQCS_CYCLES)
61391 
61392 #define S_TWLDQSEN_CYCLES    4
61393 #define M_TWLDQSEN_CYCLES    0xfU
61394 #define V_TWLDQSEN_CYCLES(x) ((x) << S_TWLDQSEN_CYCLES)
61395 #define G_TWLDQSEN_CYCLES(x) (((x) >> S_TWLDQSEN_CYCLES) & M_TWLDQSEN_CYCLES)
61396 
61397 #define S_TWRMRD_CYCLES    0
61398 #define M_TWRMRD_CYCLES    0xfU
61399 #define V_TWRMRD_CYCLES(x) ((x) << S_TWRMRD_CYCLES)
61400 #define G_TWRMRD_CYCLES(x) (((x) >> S_TWRMRD_CYCLES) & M_TWRMRD_CYCLES)
61401 
61402 #define A_MC_DDRPHY_SEQ_MEM_TIMING_PARAM2 0x47250
61403 
61404 #define S_TODTLON_OFF_CYCLES    12
61405 #define M_TODTLON_OFF_CYCLES    0xfU
61406 #define V_TODTLON_OFF_CYCLES(x) ((x) << S_TODTLON_OFF_CYCLES)
61407 #define G_TODTLON_OFF_CYCLES(x) (((x) >> S_TODTLON_OFF_CYCLES) & M_TODTLON_OFF_CYCLES)
61408 
61409 #define S_TRC_CYCLES    8
61410 #define M_TRC_CYCLES    0xfU
61411 #define V_TRC_CYCLES(x) ((x) << S_TRC_CYCLES)
61412 #define G_TRC_CYCLES(x) (((x) >> S_TRC_CYCLES) & M_TRC_CYCLES)
61413 
61414 #define S_TMRSC_CYCLES    4
61415 #define M_TMRSC_CYCLES    0xfU
61416 #define V_TMRSC_CYCLES(x) ((x) << S_TMRSC_CYCLES)
61417 #define G_TMRSC_CYCLES(x) (((x) >> S_TMRSC_CYCLES) & M_TMRSC_CYCLES)
61418 
61419 #define S_MRS_CMD_SPACE    0
61420 #define M_MRS_CMD_SPACE    0xfU
61421 #define V_MRS_CMD_SPACE(x) ((x) << S_MRS_CMD_SPACE)
61422 #define G_MRS_CMD_SPACE(x) (((x) >> S_MRS_CMD_SPACE) & M_MRS_CMD_SPACE)
61423 
61424 #define A_MC_DDRPHY_RC_CONFIG0 0x47400
61425 
61426 #define S_GLOBAL_PHY_OFFSET    12
61427 #define M_GLOBAL_PHY_OFFSET    0xfU
61428 #define V_GLOBAL_PHY_OFFSET(x) ((x) << S_GLOBAL_PHY_OFFSET)
61429 #define G_GLOBAL_PHY_OFFSET(x) (((x) >> S_GLOBAL_PHY_OFFSET) & M_GLOBAL_PHY_OFFSET)
61430 
61431 #define S_ADVANCE_RD_VALID    11
61432 #define V_ADVANCE_RD_VALID(x) ((x) << S_ADVANCE_RD_VALID)
61433 #define F_ADVANCE_RD_VALID    V_ADVANCE_RD_VALID(1U)
61434 
61435 #define S_SINGLE_BIT_MPR_RP0    6
61436 #define V_SINGLE_BIT_MPR_RP0(x) ((x) << S_SINGLE_BIT_MPR_RP0)
61437 #define F_SINGLE_BIT_MPR_RP0    V_SINGLE_BIT_MPR_RP0(1U)
61438 
61439 #define S_SINGLE_BIT_MPR_RP1    5
61440 #define V_SINGLE_BIT_MPR_RP1(x) ((x) << S_SINGLE_BIT_MPR_RP1)
61441 #define F_SINGLE_BIT_MPR_RP1    V_SINGLE_BIT_MPR_RP1(1U)
61442 
61443 #define S_SINGLE_BIT_MPR_RP2    4
61444 #define V_SINGLE_BIT_MPR_RP2(x) ((x) << S_SINGLE_BIT_MPR_RP2)
61445 #define F_SINGLE_BIT_MPR_RP2    V_SINGLE_BIT_MPR_RP2(1U)
61446 
61447 #define S_SINGLE_BIT_MPR_RP3    3
61448 #define V_SINGLE_BIT_MPR_RP3(x) ((x) << S_SINGLE_BIT_MPR_RP3)
61449 #define F_SINGLE_BIT_MPR_RP3    V_SINGLE_BIT_MPR_RP3(1U)
61450 
61451 #define S_ALIGN_ON_EVEN_CYCLES    2
61452 #define V_ALIGN_ON_EVEN_CYCLES(x) ((x) << S_ALIGN_ON_EVEN_CYCLES)
61453 #define F_ALIGN_ON_EVEN_CYCLES    V_ALIGN_ON_EVEN_CYCLES(1U)
61454 
61455 #define S_PERFORM_RDCLK_ALIGN    1
61456 #define V_PERFORM_RDCLK_ALIGN(x) ((x) << S_PERFORM_RDCLK_ALIGN)
61457 #define F_PERFORM_RDCLK_ALIGN    V_PERFORM_RDCLK_ALIGN(1U)
61458 
61459 #define S_STAGGERED_PATTERN    0
61460 #define V_STAGGERED_PATTERN(x) ((x) << S_STAGGERED_PATTERN)
61461 #define F_STAGGERED_PATTERN    V_STAGGERED_PATTERN(1U)
61462 
61463 #define S_ERS_MODE    10
61464 #define V_ERS_MODE(x) ((x) << S_ERS_MODE)
61465 #define F_ERS_MODE    V_ERS_MODE(1U)
61466 
61467 #define A_MC_DDRPHY_RC_CONFIG1 0x47404
61468 
61469 #define S_OUTER_LOOP_CNT    2
61470 #define M_OUTER_LOOP_CNT    0x3fffU
61471 #define V_OUTER_LOOP_CNT(x) ((x) << S_OUTER_LOOP_CNT)
61472 #define G_OUTER_LOOP_CNT(x) (((x) >> S_OUTER_LOOP_CNT) & M_OUTER_LOOP_CNT)
61473 
61474 #define A_MC_DDRPHY_RC_CONFIG2 0x47408
61475 
61476 #define S_CONSEQ_PASS    11
61477 #define M_CONSEQ_PASS    0x1fU
61478 #define V_CONSEQ_PASS(x) ((x) << S_CONSEQ_PASS)
61479 #define G_CONSEQ_PASS(x) (((x) >> S_CONSEQ_PASS) & M_CONSEQ_PASS)
61480 
61481 #define S_BURST_WINDOW    5
61482 #define M_BURST_WINDOW    0x3U
61483 #define V_BURST_WINDOW(x) ((x) << S_BURST_WINDOW)
61484 #define G_BURST_WINDOW(x) (((x) >> S_BURST_WINDOW) & M_BURST_WINDOW)
61485 
61486 #define S_ALLOW_RD_FIFO_AUTO_R_ESET    4
61487 #define V_ALLOW_RD_FIFO_AUTO_R_ESET(x) ((x) << S_ALLOW_RD_FIFO_AUTO_R_ESET)
61488 #define F_ALLOW_RD_FIFO_AUTO_R_ESET    V_ALLOW_RD_FIFO_AUTO_R_ESET(1U)
61489 
61490 #define S_DIS_LOW_PWR_PER_CAL    3
61491 #define V_DIS_LOW_PWR_PER_CAL(x) ((x) << S_DIS_LOW_PWR_PER_CAL)
61492 #define F_DIS_LOW_PWR_PER_CAL    V_DIS_LOW_PWR_PER_CAL(1U)
61493 
61494 #define A_MC_DDRPHY_RC_ERROR_STATUS0 0x47414
61495 
61496 #define S_RD_CNTL_ERROR    15
61497 #define V_RD_CNTL_ERROR(x) ((x) << S_RD_CNTL_ERROR)
61498 #define F_RD_CNTL_ERROR    V_RD_CNTL_ERROR(1U)
61499 
61500 #define A_MC_DDRPHY_RC_ERROR_MASK0 0x47418
61501 
61502 #define S_RD_CNTL_ERROR_MASK    15
61503 #define V_RD_CNTL_ERROR_MASK(x) ((x) << S_RD_CNTL_ERROR_MASK)
61504 #define F_RD_CNTL_ERROR_MASK    V_RD_CNTL_ERROR_MASK(1U)
61505 
61506 #define A_MC_DDRPHY_RC_CONFIG3 0x4741c
61507 
61508 #define S_FINE_CAL_STEP_SIZE    13
61509 #define M_FINE_CAL_STEP_SIZE    0x7U
61510 #define V_FINE_CAL_STEP_SIZE(x) ((x) << S_FINE_CAL_STEP_SIZE)
61511 #define G_FINE_CAL_STEP_SIZE(x) (((x) >> S_FINE_CAL_STEP_SIZE) & M_FINE_CAL_STEP_SIZE)
61512 
61513 #define S_COARSE_CAL_STEP_SIZE    9
61514 #define M_COARSE_CAL_STEP_SIZE    0xfU
61515 #define V_COARSE_CAL_STEP_SIZE(x) ((x) << S_COARSE_CAL_STEP_SIZE)
61516 #define G_COARSE_CAL_STEP_SIZE(x) (((x) >> S_COARSE_CAL_STEP_SIZE) & M_COARSE_CAL_STEP_SIZE)
61517 
61518 #define S_DQ_SEL_QUAD    7
61519 #define M_DQ_SEL_QUAD    0x3U
61520 #define V_DQ_SEL_QUAD(x) ((x) << S_DQ_SEL_QUAD)
61521 #define G_DQ_SEL_QUAD(x) (((x) >> S_DQ_SEL_QUAD) & M_DQ_SEL_QUAD)
61522 
61523 #define S_DQ_SEL_LANE    4
61524 #define M_DQ_SEL_LANE    0x7U
61525 #define V_DQ_SEL_LANE(x) ((x) << S_DQ_SEL_LANE)
61526 #define G_DQ_SEL_LANE(x) (((x) >> S_DQ_SEL_LANE) & M_DQ_SEL_LANE)
61527 
61528 #define A_MC_DDRPHY_RC_PERIODIC 0x47420
61529 #define A_MC_DDRPHY_WC_CONFIG0 0x47600
61530 
61531 #define S_TWLO_TWLOE    8
61532 #define M_TWLO_TWLOE    0xffU
61533 #define V_TWLO_TWLOE(x) ((x) << S_TWLO_TWLOE)
61534 #define G_TWLO_TWLOE(x) (((x) >> S_TWLO_TWLOE) & M_TWLO_TWLOE)
61535 
61536 #define S_WL_ONE_DQS_PULSE    7
61537 #define V_WL_ONE_DQS_PULSE(x) ((x) << S_WL_ONE_DQS_PULSE)
61538 #define F_WL_ONE_DQS_PULSE    V_WL_ONE_DQS_PULSE(1U)
61539 
61540 #define S_FW_WR_RD    1
61541 #define M_FW_WR_RD    0x3fU
61542 #define V_FW_WR_RD(x) ((x) << S_FW_WR_RD)
61543 #define G_FW_WR_RD(x) (((x) >> S_FW_WR_RD) & M_FW_WR_RD)
61544 
61545 #define S_CUSTOM_INIT_WRITE    0
61546 #define V_CUSTOM_INIT_WRITE(x) ((x) << S_CUSTOM_INIT_WRITE)
61547 #define F_CUSTOM_INIT_WRITE    V_CUSTOM_INIT_WRITE(1U)
61548 
61549 #define A_MC_DDRPHY_WC_CONFIG1 0x47604
61550 
61551 #define S_BIG_STEP    12
61552 #define M_BIG_STEP    0xfU
61553 #define V_BIG_STEP(x) ((x) << S_BIG_STEP)
61554 #define G_BIG_STEP(x) (((x) >> S_BIG_STEP) & M_BIG_STEP)
61555 
61556 #define S_SMALL_STEP    9
61557 #define M_SMALL_STEP    0x7U
61558 #define V_SMALL_STEP(x) ((x) << S_SMALL_STEP)
61559 #define G_SMALL_STEP(x) (((x) >> S_SMALL_STEP) & M_SMALL_STEP)
61560 
61561 #define S_WR_PRE_DLY    3
61562 #define M_WR_PRE_DLY    0x3fU
61563 #define V_WR_PRE_DLY(x) ((x) << S_WR_PRE_DLY)
61564 #define G_WR_PRE_DLY(x) (((x) >> S_WR_PRE_DLY) & M_WR_PRE_DLY)
61565 
61566 #define A_MC_DDRPHY_WC_CONFIG2 0x47608
61567 
61568 #define S_NUM_VALID_SAMPLES    12
61569 #define M_NUM_VALID_SAMPLES    0xfU
61570 #define V_NUM_VALID_SAMPLES(x) ((x) << S_NUM_VALID_SAMPLES)
61571 #define G_NUM_VALID_SAMPLES(x) (((x) >> S_NUM_VALID_SAMPLES) & M_NUM_VALID_SAMPLES)
61572 
61573 #define S_FW_RD_WR    6
61574 #define M_FW_RD_WR    0x3fU
61575 #define V_FW_RD_WR(x) ((x) << S_FW_RD_WR)
61576 #define G_FW_RD_WR(x) (((x) >> S_FW_RD_WR) & M_FW_RD_WR)
61577 
61578 #define S_EN_RESET_WR_DELAY_WL    0
61579 #define V_EN_RESET_WR_DELAY_WL(x) ((x) << S_EN_RESET_WR_DELAY_WL)
61580 #define F_EN_RESET_WR_DELAY_WL    V_EN_RESET_WR_DELAY_WL(1U)
61581 
61582 #define S_TWR_MPR    2
61583 #define M_TWR_MPR    0xfU
61584 #define V_TWR_MPR(x) ((x) << S_TWR_MPR)
61585 #define G_TWR_MPR(x) (((x) >> S_TWR_MPR) & M_TWR_MPR)
61586 
61587 #define A_MC_DDRPHY_WC_ERROR_STATUS0 0x4760c
61588 
61589 #define S_WR_CNTL_ERROR    15
61590 #define V_WR_CNTL_ERROR(x) ((x) << S_WR_CNTL_ERROR)
61591 #define F_WR_CNTL_ERROR    V_WR_CNTL_ERROR(1U)
61592 
61593 #define A_MC_DDRPHY_WC_ERROR_MASK0 0x47610
61594 
61595 #define S_WR_CNTL_ERROR_MASK    15
61596 #define V_WR_CNTL_ERROR_MASK(x) ((x) << S_WR_CNTL_ERROR_MASK)
61597 #define F_WR_CNTL_ERROR_MASK    V_WR_CNTL_ERROR_MASK(1U)
61598 
61599 #define A_MC_DDRPHY_WC_CONFIG3 0x47614
61600 
61601 #define S_DDR4_MRS_CMD_DQ_EN    15
61602 #define V_DDR4_MRS_CMD_DQ_EN(x) ((x) << S_DDR4_MRS_CMD_DQ_EN)
61603 #define F_DDR4_MRS_CMD_DQ_EN    V_DDR4_MRS_CMD_DQ_EN(1U)
61604 
61605 #define S_MRS_CMD_DQ_ON    9
61606 #define M_MRS_CMD_DQ_ON    0x3fU
61607 #define V_MRS_CMD_DQ_ON(x) ((x) << S_MRS_CMD_DQ_ON)
61608 #define G_MRS_CMD_DQ_ON(x) (((x) >> S_MRS_CMD_DQ_ON) & M_MRS_CMD_DQ_ON)
61609 
61610 #define S_MRS_CMD_DQ_OFF    3
61611 #define M_MRS_CMD_DQ_OFF    0x3fU
61612 #define V_MRS_CMD_DQ_OFF(x) ((x) << S_MRS_CMD_DQ_OFF)
61613 #define G_MRS_CMD_DQ_OFF(x) (((x) >> S_MRS_CMD_DQ_OFF) & M_MRS_CMD_DQ_OFF)
61614 
61615 #define A_MC_DDRPHY_WC_WRCLK_CNTL 0x47618
61616 
61617 #define S_WRCLK_CAL_START    15
61618 #define V_WRCLK_CAL_START(x) ((x) << S_WRCLK_CAL_START)
61619 #define F_WRCLK_CAL_START    V_WRCLK_CAL_START(1U)
61620 
61621 #define S_WRCLK_CAL_DONE    14
61622 #define V_WRCLK_CAL_DONE(x) ((x) << S_WRCLK_CAL_DONE)
61623 #define F_WRCLK_CAL_DONE    V_WRCLK_CAL_DONE(1U)
61624 
61625 #define A_MC_DDRPHY_APB_CONFIG0 0x47800
61626 
61627 #define S_DISABLE_PARITY_CHECKER    15
61628 #define V_DISABLE_PARITY_CHECKER(x) ((x) << S_DISABLE_PARITY_CHECKER)
61629 #define F_DISABLE_PARITY_CHECKER    V_DISABLE_PARITY_CHECKER(1U)
61630 
61631 #define S_GENERATE_EVEN_PARITY    14
61632 #define V_GENERATE_EVEN_PARITY(x) ((x) << S_GENERATE_EVEN_PARITY)
61633 #define F_GENERATE_EVEN_PARITY    V_GENERATE_EVEN_PARITY(1U)
61634 
61635 #define S_FORCE_ON_CLK_GATE    13
61636 #define V_FORCE_ON_CLK_GATE(x) ((x) << S_FORCE_ON_CLK_GATE)
61637 #define F_FORCE_ON_CLK_GATE    V_FORCE_ON_CLK_GATE(1U)
61638 
61639 #define S_DEBUG_BUS_SEL_LO    12
61640 #define V_DEBUG_BUS_SEL_LO(x) ((x) << S_DEBUG_BUS_SEL_LO)
61641 #define F_DEBUG_BUS_SEL_LO    V_DEBUG_BUS_SEL_LO(1U)
61642 
61643 #define S_DEBUG_BUS_SEL_HI    8
61644 #define M_DEBUG_BUS_SEL_HI    0xfU
61645 #define V_DEBUG_BUS_SEL_HI(x) ((x) << S_DEBUG_BUS_SEL_HI)
61646 #define G_DEBUG_BUS_SEL_HI(x) (((x) >> S_DEBUG_BUS_SEL_HI) & M_DEBUG_BUS_SEL_HI)
61647 
61648 #define A_MC_DDRPHY_APB_ERROR_STATUS0 0x47804
61649 
61650 #define S_INVALID_ADDRESS    15
61651 #define V_INVALID_ADDRESS(x) ((x) << S_INVALID_ADDRESS)
61652 #define F_INVALID_ADDRESS    V_INVALID_ADDRESS(1U)
61653 
61654 #define S_WR_PAR_ERR    14
61655 #define V_WR_PAR_ERR(x) ((x) << S_WR_PAR_ERR)
61656 #define F_WR_PAR_ERR    V_WR_PAR_ERR(1U)
61657 
61658 #define A_MC_DDRPHY_APB_ERROR_MASK0 0x47808
61659 
61660 #define S_INVALID_ADDRESS_MASK    15
61661 #define V_INVALID_ADDRESS_MASK(x) ((x) << S_INVALID_ADDRESS_MASK)
61662 #define F_INVALID_ADDRESS_MASK    V_INVALID_ADDRESS_MASK(1U)
61663 
61664 #define S_WR_PAR_ERR_MASK    14
61665 #define V_WR_PAR_ERR_MASK(x) ((x) << S_WR_PAR_ERR_MASK)
61666 #define F_WR_PAR_ERR_MASK    V_WR_PAR_ERR_MASK(1U)
61667 
61668 #define A_MC_DDRPHY_APB_DP18_POPULATION 0x4780c
61669 
61670 #define S_DP18_0_POPULATED    15
61671 #define V_DP18_0_POPULATED(x) ((x) << S_DP18_0_POPULATED)
61672 #define F_DP18_0_POPULATED    V_DP18_0_POPULATED(1U)
61673 
61674 #define S_DP18_1_POPULATED    14
61675 #define V_DP18_1_POPULATED(x) ((x) << S_DP18_1_POPULATED)
61676 #define F_DP18_1_POPULATED    V_DP18_1_POPULATED(1U)
61677 
61678 #define S_DP18_2_POPULATED    13
61679 #define V_DP18_2_POPULATED(x) ((x) << S_DP18_2_POPULATED)
61680 #define F_DP18_2_POPULATED    V_DP18_2_POPULATED(1U)
61681 
61682 #define S_DP18_3_POPULATED    12
61683 #define V_DP18_3_POPULATED(x) ((x) << S_DP18_3_POPULATED)
61684 #define F_DP18_3_POPULATED    V_DP18_3_POPULATED(1U)
61685 
61686 #define S_DP18_4_POPULATED    11
61687 #define V_DP18_4_POPULATED(x) ((x) << S_DP18_4_POPULATED)
61688 #define F_DP18_4_POPULATED    V_DP18_4_POPULATED(1U)
61689 
61690 #define S_DP18_5_POPULATED    10
61691 #define V_DP18_5_POPULATED(x) ((x) << S_DP18_5_POPULATED)
61692 #define F_DP18_5_POPULATED    V_DP18_5_POPULATED(1U)
61693 
61694 #define S_DP18_6_POPULATED    9
61695 #define V_DP18_6_POPULATED(x) ((x) << S_DP18_6_POPULATED)
61696 #define F_DP18_6_POPULATED    V_DP18_6_POPULATED(1U)
61697 
61698 #define S_DP18_7_POPULATED    8
61699 #define V_DP18_7_POPULATED(x) ((x) << S_DP18_7_POPULATED)
61700 #define F_DP18_7_POPULATED    V_DP18_7_POPULATED(1U)
61701 
61702 #define S_DP18_8_POPULATED    7
61703 #define V_DP18_8_POPULATED(x) ((x) << S_DP18_8_POPULATED)
61704 #define F_DP18_8_POPULATED    V_DP18_8_POPULATED(1U)
61705 
61706 #define S_DP18_9_POPULATED    6
61707 #define V_DP18_9_POPULATED(x) ((x) << S_DP18_9_POPULATED)
61708 #define F_DP18_9_POPULATED    V_DP18_9_POPULATED(1U)
61709 
61710 #define S_DP18_10_POPULATED    5
61711 #define V_DP18_10_POPULATED(x) ((x) << S_DP18_10_POPULATED)
61712 #define F_DP18_10_POPULATED    V_DP18_10_POPULATED(1U)
61713 
61714 #define S_DP18_11_POPULATED    4
61715 #define V_DP18_11_POPULATED(x) ((x) << S_DP18_11_POPULATED)
61716 #define F_DP18_11_POPULATED    V_DP18_11_POPULATED(1U)
61717 
61718 #define S_DP18_12_POPULATED    3
61719 #define V_DP18_12_POPULATED(x) ((x) << S_DP18_12_POPULATED)
61720 #define F_DP18_12_POPULATED    V_DP18_12_POPULATED(1U)
61721 
61722 #define S_DP18_13_POPULATED    2
61723 #define V_DP18_13_POPULATED(x) ((x) << S_DP18_13_POPULATED)
61724 #define F_DP18_13_POPULATED    V_DP18_13_POPULATED(1U)
61725 
61726 #define S_DP18_14_POPULATED    1
61727 #define V_DP18_14_POPULATED(x) ((x) << S_DP18_14_POPULATED)
61728 #define F_DP18_14_POPULATED    V_DP18_14_POPULATED(1U)
61729 
61730 #define A_MC_DDRPHY_APB_ADR_POPULATION 0x47810
61731 
61732 #define S_ADR16_0_POPULATED    15
61733 #define V_ADR16_0_POPULATED(x) ((x) << S_ADR16_0_POPULATED)
61734 #define F_ADR16_0_POPULATED    V_ADR16_0_POPULATED(1U)
61735 
61736 #define S_ADR16_1_POPULATED    14
61737 #define V_ADR16_1_POPULATED(x) ((x) << S_ADR16_1_POPULATED)
61738 #define F_ADR16_1_POPULATED    V_ADR16_1_POPULATED(1U)
61739 
61740 #define S_ADR16_2_POPULATED    13
61741 #define V_ADR16_2_POPULATED(x) ((x) << S_ADR16_2_POPULATED)
61742 #define F_ADR16_2_POPULATED    V_ADR16_2_POPULATED(1U)
61743 
61744 #define S_ADR16_3_POPULATED    12
61745 #define V_ADR16_3_POPULATED(x) ((x) << S_ADR16_3_POPULATED)
61746 #define F_ADR16_3_POPULATED    V_ADR16_3_POPULATED(1U)
61747 
61748 #define S_ADR12_0_POPULATED    7
61749 #define V_ADR12_0_POPULATED(x) ((x) << S_ADR12_0_POPULATED)
61750 #define F_ADR12_0_POPULATED    V_ADR12_0_POPULATED(1U)
61751 
61752 #define S_ADR12_1_POPULATED    6
61753 #define V_ADR12_1_POPULATED(x) ((x) << S_ADR12_1_POPULATED)
61754 #define F_ADR12_1_POPULATED    V_ADR12_1_POPULATED(1U)
61755 
61756 #define S_ADR12_2_POPULATED    5
61757 #define V_ADR12_2_POPULATED(x) ((x) << S_ADR12_2_POPULATED)
61758 #define F_ADR12_2_POPULATED    V_ADR12_2_POPULATED(1U)
61759 
61760 #define S_ADR12_3_POPULATED    4
61761 #define V_ADR12_3_POPULATED(x) ((x) << S_ADR12_3_POPULATED)
61762 #define F_ADR12_3_POPULATED    V_ADR12_3_POPULATED(1U)
61763 
61764 #define A_MC_DDRPHY_APB_ATEST_MUX_SEL 0x47814
61765 
61766 #define S_ATEST_CNTL    10
61767 #define M_ATEST_CNTL    0x3fU
61768 #define V_ATEST_CNTL(x) ((x) << S_ATEST_CNTL)
61769 #define G_ATEST_CNTL(x) (((x) >> S_ATEST_CNTL) & M_ATEST_CNTL)
61770 
61771 #define A_MC_DDRPHY_APB_MTCTL_REG0 0x47820
61772 
61773 #define S_MT_DATA_MUX4_1MODE    15
61774 #define V_MT_DATA_MUX4_1MODE(x) ((x) << S_MT_DATA_MUX4_1MODE)
61775 #define F_MT_DATA_MUX4_1MODE    V_MT_DATA_MUX4_1MODE(1U)
61776 
61777 #define S_MT_PLL_RESET    14
61778 #define V_MT_PLL_RESET(x) ((x) << S_MT_PLL_RESET)
61779 #define F_MT_PLL_RESET    V_MT_PLL_RESET(1U)
61780 
61781 #define S_MT_SYSCLK_RESET    13
61782 #define V_MT_SYSCLK_RESET(x) ((x) << S_MT_SYSCLK_RESET)
61783 #define F_MT_SYSCLK_RESET    V_MT_SYSCLK_RESET(1U)
61784 
61785 #define S_MT_GLOBAL_PHY_OFFSET    9
61786 #define M_MT_GLOBAL_PHY_OFFSET    0xfU
61787 #define V_MT_GLOBAL_PHY_OFFSET(x) ((x) << S_MT_GLOBAL_PHY_OFFSET)
61788 #define G_MT_GLOBAL_PHY_OFFSET(x) (((x) >> S_MT_GLOBAL_PHY_OFFSET) & M_MT_GLOBAL_PHY_OFFSET)
61789 
61790 #define S_MT_DQ_SEL_QUAD    7
61791 #define M_MT_DQ_SEL_QUAD    0x3U
61792 #define V_MT_DQ_SEL_QUAD(x) ((x) << S_MT_DQ_SEL_QUAD)
61793 #define G_MT_DQ_SEL_QUAD(x) (((x) >> S_MT_DQ_SEL_QUAD) & M_MT_DQ_SEL_QUAD)
61794 
61795 #define S_MT_PERFORM_RDCLK_ALIGN    6
61796 #define V_MT_PERFORM_RDCLK_ALIGN(x) ((x) << S_MT_PERFORM_RDCLK_ALIGN)
61797 #define F_MT_PERFORM_RDCLK_ALIGN    V_MT_PERFORM_RDCLK_ALIGN(1U)
61798 
61799 #define S_MT_ALIGN_ON_EVEN_CYCLES    5
61800 #define V_MT_ALIGN_ON_EVEN_CYCLES(x) ((x) << S_MT_ALIGN_ON_EVEN_CYCLES)
61801 #define F_MT_ALIGN_ON_EVEN_CYCLES    V_MT_ALIGN_ON_EVEN_CYCLES(1U)
61802 
61803 #define S_MT_WRCLK_CAL_START    4
61804 #define V_MT_WRCLK_CAL_START(x) ((x) << S_MT_WRCLK_CAL_START)
61805 #define F_MT_WRCLK_CAL_START    V_MT_WRCLK_CAL_START(1U)
61806 
61807 #define A_MC_DDRPHY_APB_MTCTL_REG1 0x47824
61808 
61809 #define S_MT_WPRD_ENABLE    15
61810 #define V_MT_WPRD_ENABLE(x) ((x) << S_MT_WPRD_ENABLE)
61811 #define F_MT_WPRD_ENABLE    V_MT_WPRD_ENABLE(1U)
61812 
61813 #define S_MT_PVTP    10
61814 #define M_MT_PVTP    0x1fU
61815 #define V_MT_PVTP(x) ((x) << S_MT_PVTP)
61816 #define G_MT_PVTP(x) (((x) >> S_MT_PVTP) & M_MT_PVTP)
61817 
61818 #define S_MT_PVTN    5
61819 #define M_MT_PVTN    0x1fU
61820 #define V_MT_PVTN(x) ((x) << S_MT_PVTN)
61821 #define G_MT_PVTN(x) (((x) >> S_MT_PVTN) & M_MT_PVTN)
61822 
61823 #define A_MC_DDRPHY_APB_MTSTAT_REG0 0x47828
61824 #define A_MC_DDRPHY_APB_MTSTAT_REG1 0x4782c
61825 
61826 #define S_MT_ADR32_PLL_LOCK_SUM    1
61827 #define V_MT_ADR32_PLL_LOCK_SUM(x) ((x) << S_MT_ADR32_PLL_LOCK_SUM)
61828 #define F_MT_ADR32_PLL_LOCK_SUM    V_MT_ADR32_PLL_LOCK_SUM(1U)
61829 
61830 #define S_MT_DP18_PLL_LOCK_SUM    0
61831 #define V_MT_DP18_PLL_LOCK_SUM(x) ((x) << S_MT_DP18_PLL_LOCK_SUM)
61832 #define F_MT_DP18_PLL_LOCK_SUM    V_MT_DP18_PLL_LOCK_SUM(1U)
61833 
61834 /* registers for module MC_1 */
61835 #define MC_1_BASE_ADDR 0x48000
61836 
61837 /* registers for module EDC_T50 */
61838 #define EDC_T50_BASE_ADDR 0x50000
61839 
61840 #define A_EDC_H_REF 0x50000
61841 
61842 #define S_EDC_SLEEPSTATUS    31
61843 #define V_EDC_SLEEPSTATUS(x) ((x) << S_EDC_SLEEPSTATUS)
61844 #define F_EDC_SLEEPSTATUS    V_EDC_SLEEPSTATUS(1U)
61845 
61846 #define S_EDC_SLEEPREQ    30
61847 #define V_EDC_SLEEPREQ(x) ((x) << S_EDC_SLEEPREQ)
61848 #define F_EDC_SLEEPREQ    V_EDC_SLEEPREQ(1U)
61849 
61850 #define S_PING_PONG    29
61851 #define V_PING_PONG(x) ((x) << S_PING_PONG)
61852 #define F_PING_PONG    V_PING_PONG(1U)
61853 
61854 #define A_EDC_H_BIST_CMD 0x50004
61855 #define A_EDC_H_BIST_CMD_ADDR 0x50008
61856 #define A_EDC_H_BIST_CMD_LEN 0x5000c
61857 #define A_EDC_H_BIST_DATA_PATTERN 0x50010
61858 #define A_EDC_H_BIST_USER_WDATA0 0x50014
61859 #define A_EDC_H_BIST_USER_WDATA1 0x50018
61860 #define A_EDC_H_BIST_USER_WDATA2 0x5001c
61861 #define A_EDC_H_BIST_NUM_ERR 0x50020
61862 #define A_EDC_H_BIST_ERR_FIRST_ADDR 0x50024
61863 #define A_EDC_H_BIST_STATUS_RDATA 0x50028
61864 #define A_EDC_H_PAR_ENABLE 0x50070
61865 
61866 #define S_PERR_PAR_ENABLE    0
61867 #define V_PERR_PAR_ENABLE(x) ((x) << S_PERR_PAR_ENABLE)
61868 #define F_PERR_PAR_ENABLE    V_PERR_PAR_ENABLE(1U)
61869 
61870 #define A_EDC_H_INT_ENABLE 0x50074
61871 #define A_EDC_H_INT_CAUSE 0x50078
61872 
61873 #define S_ECC_UE_INT0_CAUSE    5
61874 #define V_ECC_UE_INT0_CAUSE(x) ((x) << S_ECC_UE_INT0_CAUSE)
61875 #define F_ECC_UE_INT0_CAUSE    V_ECC_UE_INT0_CAUSE(1U)
61876 
61877 #define S_ECC_CE_INT0_CAUSE    4
61878 #define V_ECC_CE_INT0_CAUSE(x) ((x) << S_ECC_CE_INT0_CAUSE)
61879 #define F_ECC_CE_INT0_CAUSE    V_ECC_CE_INT0_CAUSE(1U)
61880 
61881 #define S_PERR_INT0_CAUSE    3
61882 #define V_PERR_INT0_CAUSE(x) ((x) << S_PERR_INT0_CAUSE)
61883 #define F_PERR_INT0_CAUSE    V_PERR_INT0_CAUSE(1U)
61884 
61885 #define A_EDC_H_ECC_STATUS 0x5007c
61886 #define A_EDC_H_ECC_ERR_SEL 0x50080
61887 
61888 #define S_CFG    0
61889 #define M_CFG    0x3U
61890 #define V_CFG(x) ((x) << S_CFG)
61891 #define G_CFG(x) (((x) >> S_CFG) & M_CFG)
61892 
61893 #define A_EDC_H_ECC_ERR_ADDR 0x50084
61894 
61895 #define S_ECC_ADDR    0
61896 #define M_ECC_ADDR    0x7fffffU
61897 #define V_ECC_ADDR(x) ((x) << S_ECC_ADDR)
61898 #define G_ECC_ADDR(x) (((x) >> S_ECC_ADDR) & M_ECC_ADDR)
61899 
61900 #define A_EDC_H_ECC_ERR_DATA_RDATA 0x50090
61901 #define A_EDC_H_BIST_CRC_SEED 0x50400
61902 
61903 /* registers for module EDC_T51 */
61904 #define EDC_T51_BASE_ADDR 0x50800
61905 
61906 /* registers for module HMA_T5 */
61907 #define HMA_T5_BASE_ADDR 0x51000
61908 
61909 #define A_HMA_TABLE_ACCESS 0x51000
61910 
61911 #define S_TRIG    31
61912 #define V_TRIG(x) ((x) << S_TRIG)
61913 #define F_TRIG    V_TRIG(1U)
61914 
61915 #define S_RW    30
61916 #define V_RW(x) ((x) << S_RW)
61917 #define F_RW    V_RW(1U)
61918 
61919 #define S_L_SEL    0
61920 #define M_L_SEL    0xfU
61921 #define V_L_SEL(x) ((x) << S_L_SEL)
61922 #define G_L_SEL(x) (((x) >> S_L_SEL) & M_L_SEL)
61923 
61924 #define A_HMA_TABLE_LINE0 0x51004
61925 
61926 #define S_CLIENT_EN    0
61927 #define M_CLIENT_EN    0x1fffU
61928 #define V_CLIENT_EN(x) ((x) << S_CLIENT_EN)
61929 #define G_CLIENT_EN(x) (((x) >> S_CLIENT_EN) & M_CLIENT_EN)
61930 
61931 #define A_HMA_TABLE_LINE1 0x51008
61932 #define A_HMA_TABLE_LINE2 0x5100c
61933 #define A_HMA_TABLE_LINE3 0x51010
61934 #define A_HMA_TABLE_LINE4 0x51014
61935 #define A_HMA_TABLE_LINE5 0x51018
61936 
61937 #define S_FID    16
61938 #define M_FID    0x7ffU
61939 #define V_FID(x) ((x) << S_FID)
61940 #define G_FID(x) (((x) >> S_FID) & M_FID)
61941 
61942 #define S_NOS    15
61943 #define V_NOS(x) ((x) << S_NOS)
61944 #define F_NOS    V_NOS(1U)
61945 
61946 #define S_RO    14
61947 #define V_RO(x) ((x) << S_RO)
61948 #define F_RO    V_RO(1U)
61949 
61950 #define A_HMA_COOKIE 0x5101c
61951 
61952 #define S_C_REQ    31
61953 #define V_C_REQ(x) ((x) << S_C_REQ)
61954 #define F_C_REQ    V_C_REQ(1U)
61955 
61956 #define S_C_FID    18
61957 #define M_C_FID    0x7ffU
61958 #define V_C_FID(x) ((x) << S_C_FID)
61959 #define G_C_FID(x) (((x) >> S_C_FID) & M_C_FID)
61960 
61961 #define S_C_VAL    8
61962 #define M_C_VAL    0x3ffU
61963 #define V_C_VAL(x) ((x) << S_C_VAL)
61964 #define G_C_VAL(x) (((x) >> S_C_VAL) & M_C_VAL)
61965 
61966 #define S_C_SEL    0
61967 #define M_C_SEL    0xfU
61968 #define V_C_SEL(x) ((x) << S_C_SEL)
61969 #define G_C_SEL(x) (((x) >> S_C_SEL) & M_C_SEL)
61970 
61971 #define A_HMA_PAR_ENABLE 0x51300
61972 #define A_HMA_INT_ENABLE 0x51304
61973 #define A_HMA_INT_CAUSE 0x51308
61974 
61975 /* registers for module EDC_T60 */
61976 #define EDC_T60_BASE_ADDR 0x50000
61977 
61978 #define S_QDR_CLKPHASE    24
61979 #define M_QDR_CLKPHASE    0x7U
61980 #define V_QDR_CLKPHASE(x) ((x) << S_QDR_CLKPHASE)
61981 #define G_QDR_CLKPHASE(x) (((x) >> S_QDR_CLKPHASE) & M_QDR_CLKPHASE)
61982 
61983 #define S_MAXOPSPERTRC    21
61984 #define M_MAXOPSPERTRC    0x7U
61985 #define V_MAXOPSPERTRC(x) ((x) << S_MAXOPSPERTRC)
61986 #define G_MAXOPSPERTRC(x) (((x) >> S_MAXOPSPERTRC) & M_MAXOPSPERTRC)
61987 
61988 #define S_NUMPIPESTAGES    19
61989 #define M_NUMPIPESTAGES    0x3U
61990 #define V_NUMPIPESTAGES(x) ((x) << S_NUMPIPESTAGES)
61991 #define G_NUMPIPESTAGES(x) (((x) >> S_NUMPIPESTAGES) & M_NUMPIPESTAGES)
61992 
61993 #define A_EDC_H_DBG_MA_CMD_INTF 0x50300
61994 
61995 #define S_MCMDADDR    12
61996 #define M_MCMDADDR    0xfffffU
61997 #define V_MCMDADDR(x) ((x) << S_MCMDADDR)
61998 #define G_MCMDADDR(x) (((x) >> S_MCMDADDR) & M_MCMDADDR)
61999 
62000 #define S_MCMDLEN    5
62001 #define M_MCMDLEN    0x7fU
62002 #define V_MCMDLEN(x) ((x) << S_MCMDLEN)
62003 #define G_MCMDLEN(x) (((x) >> S_MCMDLEN) & M_MCMDLEN)
62004 
62005 #define S_MCMDNRE    4
62006 #define V_MCMDNRE(x) ((x) << S_MCMDNRE)
62007 #define F_MCMDNRE    V_MCMDNRE(1U)
62008 
62009 #define S_MCMDNRB    3
62010 #define V_MCMDNRB(x) ((x) << S_MCMDNRB)
62011 #define F_MCMDNRB    V_MCMDNRB(1U)
62012 
62013 #define S_MCMDWR    2
62014 #define V_MCMDWR(x) ((x) << S_MCMDWR)
62015 #define F_MCMDWR    V_MCMDWR(1U)
62016 
62017 #define S_MCMDRDY    1
62018 #define V_MCMDRDY(x) ((x) << S_MCMDRDY)
62019 #define F_MCMDRDY    V_MCMDRDY(1U)
62020 
62021 #define S_MCMDVLD    0
62022 #define V_MCMDVLD(x) ((x) << S_MCMDVLD)
62023 #define F_MCMDVLD    V_MCMDVLD(1U)
62024 
62025 #define A_EDC_H_DBG_MA_WDATA_INTF 0x50304
62026 
62027 #define S_MWDATAVLD    31
62028 #define V_MWDATAVLD(x) ((x) << S_MWDATAVLD)
62029 #define F_MWDATAVLD    V_MWDATAVLD(1U)
62030 
62031 #define S_MWDATARDY    30
62032 #define V_MWDATARDY(x) ((x) << S_MWDATARDY)
62033 #define F_MWDATARDY    V_MWDATARDY(1U)
62034 
62035 #define S_MWDATA    0
62036 #define M_MWDATA    0x3fffffffU
62037 #define V_MWDATA(x) ((x) << S_MWDATA)
62038 #define G_MWDATA(x) (((x) >> S_MWDATA) & M_MWDATA)
62039 
62040 #define A_EDC_H_DBG_MA_RDATA_INTF 0x50308
62041 
62042 #define S_MRSPVLD    31
62043 #define V_MRSPVLD(x) ((x) << S_MRSPVLD)
62044 #define F_MRSPVLD    V_MRSPVLD(1U)
62045 
62046 #define S_MRSPRDY    30
62047 #define V_MRSPRDY(x) ((x) << S_MRSPRDY)
62048 #define F_MRSPRDY    V_MRSPRDY(1U)
62049 
62050 #define S_MRSPDATA    0
62051 #define M_MRSPDATA    0x3fffffffU
62052 #define V_MRSPDATA(x) ((x) << S_MRSPDATA)
62053 #define G_MRSPDATA(x) (((x) >> S_MRSPDATA) & M_MRSPDATA)
62054 
62055 #define A_EDC_H_DBG_BIST_CMD_INTF 0x5030c
62056 
62057 #define S_BCMDADDR    9
62058 #define M_BCMDADDR    0x7fffffU
62059 #define V_BCMDADDR(x) ((x) << S_BCMDADDR)
62060 #define G_BCMDADDR(x) (((x) >> S_BCMDADDR) & M_BCMDADDR)
62061 
62062 #define S_BCMDLEN    3
62063 #define M_BCMDLEN    0x3fU
62064 #define V_BCMDLEN(x) ((x) << S_BCMDLEN)
62065 #define G_BCMDLEN(x) (((x) >> S_BCMDLEN) & M_BCMDLEN)
62066 
62067 #define S_BCMDWR    2
62068 #define V_BCMDWR(x) ((x) << S_BCMDWR)
62069 #define F_BCMDWR    V_BCMDWR(1U)
62070 
62071 #define S_BCMDRDY    1
62072 #define V_BCMDRDY(x) ((x) << S_BCMDRDY)
62073 #define F_BCMDRDY    V_BCMDRDY(1U)
62074 
62075 #define S_BCMDVLD    0
62076 #define V_BCMDVLD(x) ((x) << S_BCMDVLD)
62077 #define F_BCMDVLD    V_BCMDVLD(1U)
62078 
62079 #define A_EDC_H_DBG_BIST_WDATA_INTF 0x50310
62080 
62081 #define S_BWDATAVLD    31
62082 #define V_BWDATAVLD(x) ((x) << S_BWDATAVLD)
62083 #define F_BWDATAVLD    V_BWDATAVLD(1U)
62084 
62085 #define S_BWDATARDY    30
62086 #define V_BWDATARDY(x) ((x) << S_BWDATARDY)
62087 #define F_BWDATARDY    V_BWDATARDY(1U)
62088 
62089 #define S_BWDATA    0
62090 #define M_BWDATA    0x3fffffffU
62091 #define V_BWDATA(x) ((x) << S_BWDATA)
62092 #define G_BWDATA(x) (((x) >> S_BWDATA) & M_BWDATA)
62093 
62094 #define A_EDC_H_DBG_BIST_RDATA_INTF 0x50314
62095 
62096 #define S_BRSPVLD    31
62097 #define V_BRSPVLD(x) ((x) << S_BRSPVLD)
62098 #define F_BRSPVLD    V_BRSPVLD(1U)
62099 
62100 #define S_BRSPRDY    30
62101 #define V_BRSPRDY(x) ((x) << S_BRSPRDY)
62102 #define F_BRSPRDY    V_BRSPRDY(1U)
62103 
62104 #define S_BRSPDATA    0
62105 #define M_BRSPDATA    0x3fffffffU
62106 #define V_BRSPDATA(x) ((x) << S_BRSPDATA)
62107 #define G_BRSPDATA(x) (((x) >> S_BRSPDATA) & M_BRSPDATA)
62108 
62109 #define A_EDC_H_DBG_EDRAM_CMD_INTF 0x50318
62110 
62111 #define S_EDRAMADDR    16
62112 #define M_EDRAMADDR    0xffffU
62113 #define V_EDRAMADDR(x) ((x) << S_EDRAMADDR)
62114 #define G_EDRAMADDR(x) (((x) >> S_EDRAMADDR) & M_EDRAMADDR)
62115 
62116 #define S_EDRAMDWSN    8
62117 #define M_EDRAMDWSN    0xffU
62118 #define V_EDRAMDWSN(x) ((x) << S_EDRAMDWSN)
62119 #define G_EDRAMDWSN(x) (((x) >> S_EDRAMDWSN) & M_EDRAMDWSN)
62120 
62121 #define S_EDRAMCRA    5
62122 #define M_EDRAMCRA    0x7U
62123 #define V_EDRAMCRA(x) ((x) << S_EDRAMCRA)
62124 #define G_EDRAMCRA(x) (((x) >> S_EDRAMCRA) & M_EDRAMCRA)
62125 
62126 #define S_EDRAMREFENLO    4
62127 #define V_EDRAMREFENLO(x) ((x) << S_EDRAMREFENLO)
62128 #define F_EDRAMREFENLO    V_EDRAMREFENLO(1U)
62129 
62130 #define S_EDRAM1WRENLO    3
62131 #define V_EDRAM1WRENLO(x) ((x) << S_EDRAM1WRENLO)
62132 #define F_EDRAM1WRENLO    V_EDRAM1WRENLO(1U)
62133 
62134 #define S_EDRAM1RDENLO    2
62135 #define V_EDRAM1RDENLO(x) ((x) << S_EDRAM1RDENLO)
62136 #define F_EDRAM1RDENLO    V_EDRAM1RDENLO(1U)
62137 
62138 #define S_EDRAM0WRENLO    1
62139 #define V_EDRAM0WRENLO(x) ((x) << S_EDRAM0WRENLO)
62140 #define F_EDRAM0WRENLO    V_EDRAM0WRENLO(1U)
62141 
62142 #define S_EDRAM0RDENLO    0
62143 #define V_EDRAM0RDENLO(x) ((x) << S_EDRAM0RDENLO)
62144 #define F_EDRAM0RDENLO    V_EDRAM0RDENLO(1U)
62145 
62146 #define A_EDC_H_DBG_EDRAM_WDATA_INTF 0x5031c
62147 
62148 #define S_EDRAMWDATA    9
62149 #define M_EDRAMWDATA    0x7fffffU
62150 #define V_EDRAMWDATA(x) ((x) << S_EDRAMWDATA)
62151 #define G_EDRAMWDATA(x) (((x) >> S_EDRAMWDATA) & M_EDRAMWDATA)
62152 
62153 #define S_EDRAMWBYTEEN    0
62154 #define M_EDRAMWBYTEEN    0x1ffU
62155 #define V_EDRAMWBYTEEN(x) ((x) << S_EDRAMWBYTEEN)
62156 #define G_EDRAMWBYTEEN(x) (((x) >> S_EDRAMWBYTEEN) & M_EDRAMWBYTEEN)
62157 
62158 #define A_EDC_H_DBG_EDRAM0_RDATA_INTF 0x50320
62159 #define A_EDC_H_DBG_EDRAM1_RDATA_INTF 0x50324
62160 #define A_EDC_H_DBG_MA_WR_REQ_CNT 0x50328
62161 #define A_EDC_H_DBG_MA_WR_EXP_DAT_CYC_CNT 0x5032c
62162 #define A_EDC_H_DBG_MA_WR_DAT_CYC_CNT 0x50330
62163 #define A_EDC_H_DBG_MA_RD_REQ_CNT 0x50334
62164 #define A_EDC_H_DBG_MA_RD_EXP_DAT_CYC_CNT 0x50338
62165 #define A_EDC_H_DBG_MA_RD_DAT_CYC_CNT 0x5033c
62166 #define A_EDC_H_DBG_BIST_WR_REQ_CNT 0x50340
62167 #define A_EDC_H_DBG_BIST_WR_EXP_DAT_CYC_CNT 0x50344
62168 #define A_EDC_H_DBG_BIST_WR_DAT_CYC_CNT 0x50348
62169 #define A_EDC_H_DBG_BIST_RD_REQ_CNT 0x5034c
62170 #define A_EDC_H_DBG_BIST_RD_EXP_DAT_CYC_CNT 0x50350
62171 #define A_EDC_H_DBG_BIST_RD_DAT_CYC_CNT 0x50354
62172 #define A_EDC_H_DBG_EDRAM0_WR_REQ_CNT 0x50358
62173 #define A_EDC_H_DBG_EDRAM0_RD_REQ_CNT 0x5035c
62174 #define A_EDC_H_DBG_EDRAM0_RMW_CNT 0x50360
62175 #define A_EDC_H_DBG_EDRAM1_WR_REQ_CNT 0x50364
62176 #define A_EDC_H_DBG_EDRAM1_RD_REQ_CNT 0x50368
62177 #define A_EDC_H_DBG_EDRAM1_RMW_CNT 0x5036c
62178 #define A_EDC_H_DBG_EDRAM_REF_BURST_CNT 0x50370
62179 #define A_EDC_H_DBG_FIFO_STATUS 0x50374
62180 
62181 #define S_RDTAG_NOTFULL    17
62182 #define V_RDTAG_NOTFULL(x) ((x) << S_RDTAG_NOTFULL)
62183 #define F_RDTAG_NOTFULL    V_RDTAG_NOTFULL(1U)
62184 
62185 #define S_RDTAG_NOTEMPTY    16
62186 #define V_RDTAG_NOTEMPTY(x) ((x) << S_RDTAG_NOTEMPTY)
62187 #define F_RDTAG_NOTEMPTY    V_RDTAG_NOTEMPTY(1U)
62188 
62189 #define S_INP_CMDQ_NOTFULL_ARB    15
62190 #define V_INP_CMDQ_NOTFULL_ARB(x) ((x) << S_INP_CMDQ_NOTFULL_ARB)
62191 #define F_INP_CMDQ_NOTFULL_ARB    V_INP_CMDQ_NOTFULL_ARB(1U)
62192 
62193 #define S_INP_CMDQ_NOTEMPTY    14
62194 #define V_INP_CMDQ_NOTEMPTY(x) ((x) << S_INP_CMDQ_NOTEMPTY)
62195 #define F_INP_CMDQ_NOTEMPTY    V_INP_CMDQ_NOTEMPTY(1U)
62196 
62197 #define S_INP_WRDQ_WRRDY    13
62198 #define V_INP_WRDQ_WRRDY(x) ((x) << S_INP_WRDQ_WRRDY)
62199 #define F_INP_WRDQ_WRRDY    V_INP_WRDQ_WRRDY(1U)
62200 
62201 #define S_INP_WRDQ_NOTEMPTY    12
62202 #define V_INP_WRDQ_NOTEMPTY(x) ((x) << S_INP_WRDQ_NOTEMPTY)
62203 #define F_INP_WRDQ_NOTEMPTY    V_INP_WRDQ_NOTEMPTY(1U)
62204 
62205 #define S_INP_BEQ_WRRDY_OPEN    11
62206 #define V_INP_BEQ_WRRDY_OPEN(x) ((x) << S_INP_BEQ_WRRDY_OPEN)
62207 #define F_INP_BEQ_WRRDY_OPEN    V_INP_BEQ_WRRDY_OPEN(1U)
62208 
62209 #define S_INP_BEQ_NOTEMPTY    10
62210 #define V_INP_BEQ_NOTEMPTY(x) ((x) << S_INP_BEQ_NOTEMPTY)
62211 #define F_INP_BEQ_NOTEMPTY    V_INP_BEQ_NOTEMPTY(1U)
62212 
62213 #define S_RDDQ_NOTFULL_OPEN    9
62214 #define V_RDDQ_NOTFULL_OPEN(x) ((x) << S_RDDQ_NOTFULL_OPEN)
62215 #define F_RDDQ_NOTFULL_OPEN    V_RDDQ_NOTFULL_OPEN(1U)
62216 
62217 #define S_RDDQ_RDCNT    4
62218 #define M_RDDQ_RDCNT    0x1fU
62219 #define V_RDDQ_RDCNT(x) ((x) << S_RDDQ_RDCNT)
62220 #define G_RDDQ_RDCNT(x) (((x) >> S_RDDQ_RDCNT) & M_RDDQ_RDCNT)
62221 
62222 #define S_RDSIDEQ_NOTFULL    3
62223 #define V_RDSIDEQ_NOTFULL(x) ((x) << S_RDSIDEQ_NOTFULL)
62224 #define F_RDSIDEQ_NOTFULL    V_RDSIDEQ_NOTFULL(1U)
62225 
62226 #define S_RDSIDEQ_NOTEMPTY    2
62227 #define V_RDSIDEQ_NOTEMPTY(x) ((x) << S_RDSIDEQ_NOTEMPTY)
62228 #define F_RDSIDEQ_NOTEMPTY    V_RDSIDEQ_NOTEMPTY(1U)
62229 
62230 #define S_STG_CMDQ_NOTEMPTY    1
62231 #define V_STG_CMDQ_NOTEMPTY(x) ((x) << S_STG_CMDQ_NOTEMPTY)
62232 #define F_STG_CMDQ_NOTEMPTY    V_STG_CMDQ_NOTEMPTY(1U)
62233 
62234 #define S_STG_WRDQ_NOTEMPTY    0
62235 #define V_STG_WRDQ_NOTEMPTY(x) ((x) << S_STG_WRDQ_NOTEMPTY)
62236 #define F_STG_WRDQ_NOTEMPTY    V_STG_WRDQ_NOTEMPTY(1U)
62237 
62238 #define A_EDC_H_DBG_FSM_STATE 0x50378
62239 
62240 #define S_CMDSPLITFSM    3
62241 #define V_CMDSPLITFSM(x) ((x) << S_CMDSPLITFSM)
62242 #define F_CMDSPLITFSM    V_CMDSPLITFSM(1U)
62243 
62244 #define S_CMDFSM    0
62245 #define M_CMDFSM    0x7U
62246 #define V_CMDFSM(x) ((x) << S_CMDFSM)
62247 #define G_CMDFSM(x) (((x) >> S_CMDFSM) & M_CMDFSM)
62248 
62249 #define A_EDC_H_DBG_STALL_CYCLES 0x5037c
62250 
62251 #define S_STALL_RMW    19
62252 #define V_STALL_RMW(x) ((x) << S_STALL_RMW)
62253 #define F_STALL_RMW    V_STALL_RMW(1U)
62254 
62255 #define S_STALL_EDC_CMD    18
62256 #define V_STALL_EDC_CMD(x) ((x) << S_STALL_EDC_CMD)
62257 #define F_STALL_EDC_CMD    V_STALL_EDC_CMD(1U)
62258 
62259 #define S_DEAD_CYCLE0    17
62260 #define V_DEAD_CYCLE0(x) ((x) << S_DEAD_CYCLE0)
62261 #define F_DEAD_CYCLE0    V_DEAD_CYCLE0(1U)
62262 
62263 #define S_DEAD_CYCLE1    16
62264 #define V_DEAD_CYCLE1(x) ((x) << S_DEAD_CYCLE1)
62265 #define F_DEAD_CYCLE1    V_DEAD_CYCLE1(1U)
62266 
62267 #define S_DEAD_CYCLE0_BBI    15
62268 #define V_DEAD_CYCLE0_BBI(x) ((x) << S_DEAD_CYCLE0_BBI)
62269 #define F_DEAD_CYCLE0_BBI    V_DEAD_CYCLE0_BBI(1U)
62270 
62271 #define S_DEAD_CYCLE1_BBI    14
62272 #define V_DEAD_CYCLE1_BBI(x) ((x) << S_DEAD_CYCLE1_BBI)
62273 #define F_DEAD_CYCLE1_BBI    V_DEAD_CYCLE1_BBI(1U)
62274 
62275 #define S_DEAD_CYCLE0_MAX_OP    13
62276 #define V_DEAD_CYCLE0_MAX_OP(x) ((x) << S_DEAD_CYCLE0_MAX_OP)
62277 #define F_DEAD_CYCLE0_MAX_OP    V_DEAD_CYCLE0_MAX_OP(1U)
62278 
62279 #define S_DEAD_CYCLE1_MAX_OP    12
62280 #define V_DEAD_CYCLE1_MAX_OP(x) ((x) << S_DEAD_CYCLE1_MAX_OP)
62281 #define F_DEAD_CYCLE1_MAX_OP    V_DEAD_CYCLE1_MAX_OP(1U)
62282 
62283 #define S_DEAD_CYCLE0_PRE_REF    11
62284 #define V_DEAD_CYCLE0_PRE_REF(x) ((x) << S_DEAD_CYCLE0_PRE_REF)
62285 #define F_DEAD_CYCLE0_PRE_REF    V_DEAD_CYCLE0_PRE_REF(1U)
62286 
62287 #define S_DEAD_CYCLE1_PRE_REF    10
62288 #define V_DEAD_CYCLE1_PRE_REF(x) ((x) << S_DEAD_CYCLE1_PRE_REF)
62289 #define F_DEAD_CYCLE1_PRE_REF    V_DEAD_CYCLE1_PRE_REF(1U)
62290 
62291 #define S_DEAD_CYCLE0_POST_REF    9
62292 #define V_DEAD_CYCLE0_POST_REF(x) ((x) << S_DEAD_CYCLE0_POST_REF)
62293 #define F_DEAD_CYCLE0_POST_REF    V_DEAD_CYCLE0_POST_REF(1U)
62294 
62295 #define S_DEAD_CYCLE1_POST_REF    8
62296 #define V_DEAD_CYCLE1_POST_REF(x) ((x) << S_DEAD_CYCLE1_POST_REF)
62297 #define F_DEAD_CYCLE1_POST_REF    V_DEAD_CYCLE1_POST_REF(1U)
62298 
62299 #define S_DEAD_CYCLE0_RMW    7
62300 #define V_DEAD_CYCLE0_RMW(x) ((x) << S_DEAD_CYCLE0_RMW)
62301 #define F_DEAD_CYCLE0_RMW    V_DEAD_CYCLE0_RMW(1U)
62302 
62303 #define S_DEAD_CYCLE1_RMW    6
62304 #define V_DEAD_CYCLE1_RMW(x) ((x) << S_DEAD_CYCLE1_RMW)
62305 #define F_DEAD_CYCLE1_RMW    V_DEAD_CYCLE1_RMW(1U)
62306 
62307 #define S_DEAD_CYCLE0_BBI_RMW    5
62308 #define V_DEAD_CYCLE0_BBI_RMW(x) ((x) << S_DEAD_CYCLE0_BBI_RMW)
62309 #define F_DEAD_CYCLE0_BBI_RMW    V_DEAD_CYCLE0_BBI_RMW(1U)
62310 
62311 #define S_DEAD_CYCLE1_BBI_RMW    4
62312 #define V_DEAD_CYCLE1_BBI_RMW(x) ((x) << S_DEAD_CYCLE1_BBI_RMW)
62313 #define F_DEAD_CYCLE1_BBI_RMW    V_DEAD_CYCLE1_BBI_RMW(1U)
62314 
62315 #define S_DEAD_CYCLE0_PRE_REF_RMW    3
62316 #define V_DEAD_CYCLE0_PRE_REF_RMW(x) ((x) << S_DEAD_CYCLE0_PRE_REF_RMW)
62317 #define F_DEAD_CYCLE0_PRE_REF_RMW    V_DEAD_CYCLE0_PRE_REF_RMW(1U)
62318 
62319 #define S_DEAD_CYCLE1_PRE_REF_RMW    2
62320 #define V_DEAD_CYCLE1_PRE_REF_RMW(x) ((x) << S_DEAD_CYCLE1_PRE_REF_RMW)
62321 #define F_DEAD_CYCLE1_PRE_REF_RMW    V_DEAD_CYCLE1_PRE_REF_RMW(1U)
62322 
62323 #define S_DEAD_CYCLE0_POST_REF_RMW    1
62324 #define V_DEAD_CYCLE0_POST_REF_RMW(x) ((x) << S_DEAD_CYCLE0_POST_REF_RMW)
62325 #define F_DEAD_CYCLE0_POST_REF_RMW    V_DEAD_CYCLE0_POST_REF_RMW(1U)
62326 
62327 #define S_DEAD_CYCLE1_POST_REF_RMW    0
62328 #define V_DEAD_CYCLE1_POST_REF_RMW(x) ((x) << S_DEAD_CYCLE1_POST_REF_RMW)
62329 #define F_DEAD_CYCLE1_POST_REF_RMW    V_DEAD_CYCLE1_POST_REF_RMW(1U)
62330 
62331 #define A_EDC_H_DBG_CMD_QUEUE 0x50380
62332 
62333 #define S_ECMDNRE    31
62334 #define V_ECMDNRE(x) ((x) << S_ECMDNRE)
62335 #define F_ECMDNRE    V_ECMDNRE(1U)
62336 
62337 #define S_ECMDNRB    30
62338 #define V_ECMDNRB(x) ((x) << S_ECMDNRB)
62339 #define F_ECMDNRB    V_ECMDNRB(1U)
62340 
62341 #define S_ECMDWR    29
62342 #define V_ECMDWR(x) ((x) << S_ECMDWR)
62343 #define F_ECMDWR    V_ECMDWR(1U)
62344 
62345 #define S_ECMDLEN    22
62346 #define M_ECMDLEN    0x7fU
62347 #define V_ECMDLEN(x) ((x) << S_ECMDLEN)
62348 #define G_ECMDLEN(x) (((x) >> S_ECMDLEN) & M_ECMDLEN)
62349 
62350 #define S_ECMDADDR    0
62351 #define M_ECMDADDR    0x3fffffU
62352 #define V_ECMDADDR(x) ((x) << S_ECMDADDR)
62353 #define G_ECMDADDR(x) (((x) >> S_ECMDADDR) & M_ECMDADDR)
62354 
62355 #define A_EDC_H_DBG_REFRESH 0x50384
62356 
62357 #define S_REFDONE    12
62358 #define V_REFDONE(x) ((x) << S_REFDONE)
62359 #define F_REFDONE    V_REFDONE(1U)
62360 
62361 #define S_REFCNTEXPR    11
62362 #define V_REFCNTEXPR(x) ((x) << S_REFCNTEXPR)
62363 #define F_REFCNTEXPR    V_REFCNTEXPR(1U)
62364 
62365 #define S_REFPTR    8
62366 #define M_REFPTR    0x7U
62367 #define V_REFPTR(x) ((x) << S_REFPTR)
62368 #define G_REFPTR(x) (((x) >> S_REFPTR) & M_REFPTR)
62369 
62370 #define S_REFCNT    0
62371 #define M_REFCNT    0xffU
62372 #define V_REFCNT(x) ((x) << S_REFCNT)
62373 #define G_REFCNT(x) (((x) >> S_REFCNT) & M_REFCNT)
62374 
62375 /* registers for module EDC_T61 */
62376 #define EDC_T61_BASE_ADDR 0x50800
62377 
62378 /* registers for module HMA_T6 */
62379 #define HMA_T6_BASE_ADDR 0x51000
62380 
62381 #define S_TPH    12
62382 #define M_TPH    0x3U
62383 #define V_TPH(x) ((x) << S_TPH)
62384 #define G_TPH(x) (((x) >> S_TPH) & M_TPH)
62385 
62386 #define S_TPH_V    11
62387 #define V_TPH_V(x) ((x) << S_TPH_V)
62388 #define F_TPH_V    V_TPH_V(1U)
62389 
62390 #define S_DCA    0
62391 #define M_DCA    0x7ffU
62392 #define V_DCA(x) ((x) << S_DCA)
62393 #define G_DCA(x) (((x) >> S_DCA) & M_DCA)
62394 
62395 #define A_HMA_CFG 0x51020
62396 
62397 #define S_OP_MODE    31
62398 #define V_OP_MODE(x) ((x) << S_OP_MODE)
62399 #define F_OP_MODE    V_OP_MODE(1U)
62400 
62401 #define A_HMA_TLB_ACCESS 0x51028
62402 
62403 #define S_INV_ALL    29
62404 #define V_INV_ALL(x) ((x) << S_INV_ALL)
62405 #define F_INV_ALL    V_INV_ALL(1U)
62406 
62407 #define S_LOCK_ENTRY    28
62408 #define V_LOCK_ENTRY(x) ((x) << S_LOCK_ENTRY)
62409 #define F_LOCK_ENTRY    V_LOCK_ENTRY(1U)
62410 
62411 #define S_E_SEL    0
62412 #define M_E_SEL    0x1fU
62413 #define V_E_SEL(x) ((x) << S_E_SEL)
62414 #define G_E_SEL(x) (((x) >> S_E_SEL) & M_E_SEL)
62415 
62416 #define A_HMA_TLB_BITS 0x5102c
62417 
62418 #define S_VA    12
62419 #define M_VA    0xfffffU
62420 #define V_VA(x) ((x) << S_VA)
62421 #define G_VA(x) (((x) >> S_VA) & M_VA)
62422 
62423 #define S_VALID_E    4
62424 #define V_VALID_E(x) ((x) << S_VALID_E)
62425 #define F_VALID_E    V_VALID_E(1U)
62426 
62427 #define S_LOCK_HMA    3
62428 #define V_LOCK_HMA(x) ((x) << S_LOCK_HMA)
62429 #define F_LOCK_HMA    V_LOCK_HMA(1U)
62430 
62431 #define S_T6_USED    2
62432 #define V_T6_USED(x) ((x) << S_T6_USED)
62433 #define F_T6_USED    V_T6_USED(1U)
62434 
62435 #define S_REGION    0
62436 #define M_REGION    0x3U
62437 #define V_REGION(x) ((x) << S_REGION)
62438 #define G_REGION(x) (((x) >> S_REGION) & M_REGION)
62439 
62440 #define A_HMA_TLB_DESC_0_H 0x51030
62441 #define A_HMA_TLB_DESC_0_L 0x51034
62442 #define A_HMA_TLB_DESC_1_H 0x51038
62443 #define A_HMA_TLB_DESC_1_L 0x5103c
62444 #define A_HMA_TLB_DESC_2_H 0x51040
62445 #define A_HMA_TLB_DESC_2_L 0x51044
62446 #define A_HMA_TLB_DESC_3_H 0x51048
62447 #define A_HMA_TLB_DESC_3_L 0x5104c
62448 #define A_HMA_TLB_DESC_4_H 0x51050
62449 #define A_HMA_TLB_DESC_4_L 0x51054
62450 #define A_HMA_TLB_DESC_5_H 0x51058
62451 #define A_HMA_TLB_DESC_5_L 0x5105c
62452 #define A_HMA_TLB_DESC_6_H 0x51060
62453 #define A_HMA_TLB_DESC_6_L 0x51064
62454 #define A_HMA_TLB_DESC_7_H 0x51068
62455 #define A_HMA_TLB_DESC_7_L 0x5106c
62456 #define A_HMA_REG0_MIN 0x51070
62457 
62458 #define S_ADDR0_MIN    12
62459 #define M_ADDR0_MIN    0xfffffU
62460 #define V_ADDR0_MIN(x) ((x) << S_ADDR0_MIN)
62461 #define G_ADDR0_MIN(x) (((x) >> S_ADDR0_MIN) & M_ADDR0_MIN)
62462 
62463 #define A_HMA_REG0_MAX 0x51074
62464 
62465 #define S_ADDR0_MAX    12
62466 #define M_ADDR0_MAX    0xfffffU
62467 #define V_ADDR0_MAX(x) ((x) << S_ADDR0_MAX)
62468 #define G_ADDR0_MAX(x) (((x) >> S_ADDR0_MAX) & M_ADDR0_MAX)
62469 
62470 #define A_HMA_REG0_MASK 0x51078
62471 
62472 #define S_PAGE_SIZE0    12
62473 #define M_PAGE_SIZE0    0xfffffU
62474 #define V_PAGE_SIZE0(x) ((x) << S_PAGE_SIZE0)
62475 #define G_PAGE_SIZE0(x) (((x) >> S_PAGE_SIZE0) & M_PAGE_SIZE0)
62476 
62477 #define A_HMA_REG0_BASE 0x5107c
62478 #define A_HMA_REG1_MIN 0x51080
62479 
62480 #define S_ADDR1_MIN    12
62481 #define M_ADDR1_MIN    0xfffffU
62482 #define V_ADDR1_MIN(x) ((x) << S_ADDR1_MIN)
62483 #define G_ADDR1_MIN(x) (((x) >> S_ADDR1_MIN) & M_ADDR1_MIN)
62484 
62485 #define A_HMA_REG1_MAX 0x51084
62486 
62487 #define S_ADDR1_MAX    12
62488 #define M_ADDR1_MAX    0xfffffU
62489 #define V_ADDR1_MAX(x) ((x) << S_ADDR1_MAX)
62490 #define G_ADDR1_MAX(x) (((x) >> S_ADDR1_MAX) & M_ADDR1_MAX)
62491 
62492 #define A_HMA_REG1_MASK 0x51088
62493 
62494 #define S_PAGE_SIZE1    12
62495 #define M_PAGE_SIZE1    0xfffffU
62496 #define V_PAGE_SIZE1(x) ((x) << S_PAGE_SIZE1)
62497 #define G_PAGE_SIZE1(x) (((x) >> S_PAGE_SIZE1) & M_PAGE_SIZE1)
62498 
62499 #define A_HMA_REG1_BASE 0x5108c
62500 #define A_HMA_REG2_MIN 0x51090
62501 
62502 #define S_ADDR2_MIN    12
62503 #define M_ADDR2_MIN    0xfffffU
62504 #define V_ADDR2_MIN(x) ((x) << S_ADDR2_MIN)
62505 #define G_ADDR2_MIN(x) (((x) >> S_ADDR2_MIN) & M_ADDR2_MIN)
62506 
62507 #define A_HMA_REG2_MAX 0x51094
62508 
62509 #define S_ADDR2_MAX    12
62510 #define M_ADDR2_MAX    0xfffffU
62511 #define V_ADDR2_MAX(x) ((x) << S_ADDR2_MAX)
62512 #define G_ADDR2_MAX(x) (((x) >> S_ADDR2_MAX) & M_ADDR2_MAX)
62513 
62514 #define A_HMA_REG2_MASK 0x51098
62515 
62516 #define S_PAGE_SIZE2    12
62517 #define M_PAGE_SIZE2    0xfffffU
62518 #define V_PAGE_SIZE2(x) ((x) << S_PAGE_SIZE2)
62519 #define G_PAGE_SIZE2(x) (((x) >> S_PAGE_SIZE2) & M_PAGE_SIZE2)
62520 
62521 #define A_HMA_REG2_BASE 0x5109c
62522 #define A_HMA_REG3_MIN 0x510a0
62523 
62524 #define S_ADDR3_MIN    12
62525 #define M_ADDR3_MIN    0xfffffU
62526 #define V_ADDR3_MIN(x) ((x) << S_ADDR3_MIN)
62527 #define G_ADDR3_MIN(x) (((x) >> S_ADDR3_MIN) & M_ADDR3_MIN)
62528 
62529 #define A_HMA_REG3_MAX 0x510a4
62530 
62531 #define S_ADDR3_MAX    12
62532 #define M_ADDR3_MAX    0xfffffU
62533 #define V_ADDR3_MAX(x) ((x) << S_ADDR3_MAX)
62534 #define G_ADDR3_MAX(x) (((x) >> S_ADDR3_MAX) & M_ADDR3_MAX)
62535 
62536 #define A_HMA_REG3_MASK 0x510a8
62537 
62538 #define S_PAGE_SIZE3    12
62539 #define M_PAGE_SIZE3    0xfffffU
62540 #define V_PAGE_SIZE3(x) ((x) << S_PAGE_SIZE3)
62541 #define G_PAGE_SIZE3(x) (((x) >> S_PAGE_SIZE3) & M_PAGE_SIZE3)
62542 
62543 #define A_HMA_REG3_BASE 0x510ac
62544 #define A_HMA_SW_SYNC 0x510b0
62545 
62546 #define S_ENTER_SYNC    31
62547 #define V_ENTER_SYNC(x) ((x) << S_ENTER_SYNC)
62548 #define F_ENTER_SYNC    V_ENTER_SYNC(1U)
62549 
62550 #define S_EXIT_SYNC    30
62551 #define V_EXIT_SYNC(x) ((x) << S_EXIT_SYNC)
62552 #define F_EXIT_SYNC    V_EXIT_SYNC(1U)
62553 
62554 #define S_IDTF_INT_ENABLE    5
62555 #define V_IDTF_INT_ENABLE(x) ((x) << S_IDTF_INT_ENABLE)
62556 #define F_IDTF_INT_ENABLE    V_IDTF_INT_ENABLE(1U)
62557 
62558 #define S_OTF_INT_ENABLE    4
62559 #define V_OTF_INT_ENABLE(x) ((x) << S_OTF_INT_ENABLE)
62560 #define F_OTF_INT_ENABLE    V_OTF_INT_ENABLE(1U)
62561 
62562 #define S_RTF_INT_ENABLE    3
62563 #define V_RTF_INT_ENABLE(x) ((x) << S_RTF_INT_ENABLE)
62564 #define F_RTF_INT_ENABLE    V_RTF_INT_ENABLE(1U)
62565 
62566 #define S_PCIEMST_INT_ENABLE    2
62567 #define V_PCIEMST_INT_ENABLE(x) ((x) << S_PCIEMST_INT_ENABLE)
62568 #define F_PCIEMST_INT_ENABLE    V_PCIEMST_INT_ENABLE(1U)
62569 
62570 #define S_MAMST_INT_ENABLE    1
62571 #define V_MAMST_INT_ENABLE(x) ((x) << S_MAMST_INT_ENABLE)
62572 #define F_MAMST_INT_ENABLE    V_MAMST_INT_ENABLE(1U)
62573 
62574 #define S_IDTF_INT_CAUSE    5
62575 #define V_IDTF_INT_CAUSE(x) ((x) << S_IDTF_INT_CAUSE)
62576 #define F_IDTF_INT_CAUSE    V_IDTF_INT_CAUSE(1U)
62577 
62578 #define S_OTF_INT_CAUSE    4
62579 #define V_OTF_INT_CAUSE(x) ((x) << S_OTF_INT_CAUSE)
62580 #define F_OTF_INT_CAUSE    V_OTF_INT_CAUSE(1U)
62581 
62582 #define S_RTF_INT_CAUSE    3
62583 #define V_RTF_INT_CAUSE(x) ((x) << S_RTF_INT_CAUSE)
62584 #define F_RTF_INT_CAUSE    V_RTF_INT_CAUSE(1U)
62585 
62586 #define S_PCIEMST_INT_CAUSE    2
62587 #define V_PCIEMST_INT_CAUSE(x) ((x) << S_PCIEMST_INT_CAUSE)
62588 #define F_PCIEMST_INT_CAUSE    V_PCIEMST_INT_CAUSE(1U)
62589 
62590 #define S_MAMST_INT_CAUSE    1
62591 #define V_MAMST_INT_CAUSE(x) ((x) << S_MAMST_INT_CAUSE)
62592 #define F_MAMST_INT_CAUSE    V_MAMST_INT_CAUSE(1U)
62593 
62594 #define A_HMA_MA_MST_ERR 0x5130c
62595 #define A_HMA_RTF_ERR 0x51310
62596 #define A_HMA_OTF_ERR 0x51314
62597 #define A_HMA_IDTF_ERR 0x51318
62598 #define A_HMA_EXIT_TF 0x5131c
62599 
62600 #define S_RTF    30
62601 #define V_RTF(x) ((x) << S_RTF)
62602 #define F_RTF    V_RTF(1U)
62603 
62604 #define S_OTF    29
62605 #define V_OTF(x) ((x) << S_OTF)
62606 #define F_OTF    V_OTF(1U)
62607 
62608 #define S_IDTF    28
62609 #define V_IDTF(x) ((x) << S_IDTF)
62610 #define F_IDTF    V_IDTF(1U)
62611 
62612 #define A_HMA_LOCAL_DEBUG_CFG 0x51320
62613 #define A_HMA_LOCAL_DEBUG_RPT 0x51324
62614 #define A_HMA_DEBUG_FSM_0 0xa000
62615 
62616 #define S_EDC_FSM    18
62617 #define M_EDC_FSM    0x1fU
62618 #define V_EDC_FSM(x) ((x) << S_EDC_FSM)
62619 #define G_EDC_FSM(x) (((x) >> S_EDC_FSM) & M_EDC_FSM)
62620 
62621 #define S_RAS_FSM_SLV    15
62622 #define M_RAS_FSM_SLV    0x7U
62623 #define V_RAS_FSM_SLV(x) ((x) << S_RAS_FSM_SLV)
62624 #define G_RAS_FSM_SLV(x) (((x) >> S_RAS_FSM_SLV) & M_RAS_FSM_SLV)
62625 
62626 #define S_FC_FSM    10
62627 #define M_FC_FSM    0x1fU
62628 #define V_FC_FSM(x) ((x) << S_FC_FSM)
62629 #define G_FC_FSM(x) (((x) >> S_FC_FSM) & M_FC_FSM)
62630 
62631 #define S_COOKIE_ARB_FSM    8
62632 #define M_COOKIE_ARB_FSM    0x3U
62633 #define V_COOKIE_ARB_FSM(x) ((x) << S_COOKIE_ARB_FSM)
62634 #define G_COOKIE_ARB_FSM(x) (((x) >> S_COOKIE_ARB_FSM) & M_COOKIE_ARB_FSM)
62635 
62636 #define S_PCIE_CHUNK_FSM    6
62637 #define M_PCIE_CHUNK_FSM    0x3U
62638 #define V_PCIE_CHUNK_FSM(x) ((x) << S_PCIE_CHUNK_FSM)
62639 #define G_PCIE_CHUNK_FSM(x) (((x) >> S_PCIE_CHUNK_FSM) & M_PCIE_CHUNK_FSM)
62640 
62641 #define S_WTRANSFER_FSM    4
62642 #define M_WTRANSFER_FSM    0x3U
62643 #define V_WTRANSFER_FSM(x) ((x) << S_WTRANSFER_FSM)
62644 #define G_WTRANSFER_FSM(x) (((x) >> S_WTRANSFER_FSM) & M_WTRANSFER_FSM)
62645 
62646 #define S_WD_FSM    2
62647 #define M_WD_FSM    0x3U
62648 #define V_WD_FSM(x) ((x) << S_WD_FSM)
62649 #define G_WD_FSM(x) (((x) >> S_WD_FSM) & M_WD_FSM)
62650 
62651 #define S_RD_FSM    0
62652 #define M_RD_FSM    0x3U
62653 #define V_RD_FSM(x) ((x) << S_RD_FSM)
62654 #define G_RD_FSM(x) (((x) >> S_RD_FSM) & M_RD_FSM)
62655 
62656 #define A_HMA_DEBUG_FSM_1 0xa001
62657 
62658 #define S_SYNC_FSM    11
62659 #define M_SYNC_FSM    0x3ffU
62660 #define V_SYNC_FSM(x) ((x) << S_SYNC_FSM)
62661 #define G_SYNC_FSM(x) (((x) >> S_SYNC_FSM) & M_SYNC_FSM)
62662 
62663 #define S_OCHK_FSM    9
62664 #define M_OCHK_FSM    0x3U
62665 #define V_OCHK_FSM(x) ((x) << S_OCHK_FSM)
62666 #define G_OCHK_FSM(x) (((x) >> S_OCHK_FSM) & M_OCHK_FSM)
62667 
62668 #define S_TLB_FSM    5
62669 #define M_TLB_FSM    0xfU
62670 #define V_TLB_FSM(x) ((x) << S_TLB_FSM)
62671 #define G_TLB_FSM(x) (((x) >> S_TLB_FSM) & M_TLB_FSM)
62672 
62673 #define S_PIO_FSM    0
62674 #define M_PIO_FSM    0x1fU
62675 #define V_PIO_FSM(x) ((x) << S_PIO_FSM)
62676 #define G_PIO_FSM(x) (((x) >> S_PIO_FSM) & M_PIO_FSM)
62677 
62678 #define A_HMA_DEBUG_PCIE_INTF 0xa002
62679 
62680 #define S_T6_H_REQVLD    28
62681 #define V_T6_H_REQVLD(x) ((x) << S_T6_H_REQVLD)
62682 #define F_T6_H_REQVLD    V_T6_H_REQVLD(1U)
62683 
62684 #define S_H_REQFULL    27
62685 #define V_H_REQFULL(x) ((x) << S_H_REQFULL)
62686 #define F_H_REQFULL    V_H_REQFULL(1U)
62687 
62688 #define S_H_REQSOP    26
62689 #define V_H_REQSOP(x) ((x) << S_H_REQSOP)
62690 #define F_H_REQSOP    V_H_REQSOP(1U)
62691 
62692 #define S_H_REQEOP    25
62693 #define V_H_REQEOP(x) ((x) << S_H_REQEOP)
62694 #define F_H_REQEOP    V_H_REQEOP(1U)
62695 
62696 #define S_T6_H_RSPVLD    24
62697 #define V_T6_H_RSPVLD(x) ((x) << S_T6_H_RSPVLD)
62698 #define F_T6_H_RSPVLD    V_T6_H_RSPVLD(1U)
62699 
62700 #define S_H_RSPFULL    23
62701 #define V_H_RSPFULL(x) ((x) << S_H_RSPFULL)
62702 #define F_H_RSPFULL    V_H_RSPFULL(1U)
62703 
62704 #define S_H_RSPSOP    22
62705 #define V_H_RSPSOP(x) ((x) << S_H_RSPSOP)
62706 #define F_H_RSPSOP    V_H_RSPSOP(1U)
62707 
62708 #define S_H_RSPEOP    21
62709 #define V_H_RSPEOP(x) ((x) << S_H_RSPEOP)
62710 #define F_H_RSPEOP    V_H_RSPEOP(1U)
62711 
62712 #define S_H_RSPERR    20
62713 #define V_H_RSPERR(x) ((x) << S_H_RSPERR)
62714 #define F_H_RSPERR    V_H_RSPERR(1U)
62715 
62716 #define S_PCIE_CMD_AVAIL    19
62717 #define V_PCIE_CMD_AVAIL(x) ((x) << S_PCIE_CMD_AVAIL)
62718 #define F_PCIE_CMD_AVAIL    V_PCIE_CMD_AVAIL(1U)
62719 
62720 #define S_PCIE_CMD_RDY    18
62721 #define V_PCIE_CMD_RDY(x) ((x) << S_PCIE_CMD_RDY)
62722 #define F_PCIE_CMD_RDY    V_PCIE_CMD_RDY(1U)
62723 
62724 #define S_PCIE_WNR    17
62725 #define V_PCIE_WNR(x) ((x) << S_PCIE_WNR)
62726 #define F_PCIE_WNR    V_PCIE_WNR(1U)
62727 
62728 #define S_PCIE_LEN    9
62729 #define M_PCIE_LEN    0xffU
62730 #define V_PCIE_LEN(x) ((x) << S_PCIE_LEN)
62731 #define G_PCIE_LEN(x) (((x) >> S_PCIE_LEN) & M_PCIE_LEN)
62732 
62733 #define S_PCIE_TRWDAT_RDY    8
62734 #define V_PCIE_TRWDAT_RDY(x) ((x) << S_PCIE_TRWDAT_RDY)
62735 #define F_PCIE_TRWDAT_RDY    V_PCIE_TRWDAT_RDY(1U)
62736 
62737 #define S_PCIE_TRWDAT_AVAIL    7
62738 #define V_PCIE_TRWDAT_AVAIL(x) ((x) << S_PCIE_TRWDAT_AVAIL)
62739 #define F_PCIE_TRWDAT_AVAIL    V_PCIE_TRWDAT_AVAIL(1U)
62740 
62741 #define S_PCIE_TRWSOP    6
62742 #define V_PCIE_TRWSOP(x) ((x) << S_PCIE_TRWSOP)
62743 #define F_PCIE_TRWSOP    V_PCIE_TRWSOP(1U)
62744 
62745 #define S_PCIE_TRWEOP    5
62746 #define V_PCIE_TRWEOP(x) ((x) << S_PCIE_TRWEOP)
62747 #define F_PCIE_TRWEOP    V_PCIE_TRWEOP(1U)
62748 
62749 #define S_PCIE_TRRDAT_RDY    4
62750 #define V_PCIE_TRRDAT_RDY(x) ((x) << S_PCIE_TRRDAT_RDY)
62751 #define F_PCIE_TRRDAT_RDY    V_PCIE_TRRDAT_RDY(1U)
62752 
62753 #define S_PCIE_TRRDAT_AVAIL    3
62754 #define V_PCIE_TRRDAT_AVAIL(x) ((x) << S_PCIE_TRRDAT_AVAIL)
62755 #define F_PCIE_TRRDAT_AVAIL    V_PCIE_TRRDAT_AVAIL(1U)
62756 
62757 #define S_PCIE_TRRSOP    2
62758 #define V_PCIE_TRRSOP(x) ((x) << S_PCIE_TRRSOP)
62759 #define F_PCIE_TRRSOP    V_PCIE_TRRSOP(1U)
62760 
62761 #define S_PCIE_TRREOP    1
62762 #define V_PCIE_TRREOP(x) ((x) << S_PCIE_TRREOP)
62763 #define F_PCIE_TRREOP    V_PCIE_TRREOP(1U)
62764 
62765 #define S_PCIE_TRRERR    0
62766 #define V_PCIE_TRRERR(x) ((x) << S_PCIE_TRRERR)
62767 #define F_PCIE_TRRERR    V_PCIE_TRRERR(1U)
62768 
62769 #define A_HMA_DEBUG_PCIE_ADDR_INTERNAL_LO 0xa003
62770 #define A_HMA_DEBUG_PCIE_ADDR_INTERNAL_HI 0xa004
62771 #define A_HMA_DEBUG_PCIE_REQ_DATA_EXTERNAL 0xa005
62772 
62773 #define S_REQDATA2    24
62774 #define M_REQDATA2    0xffU
62775 #define V_REQDATA2(x) ((x) << S_REQDATA2)
62776 #define G_REQDATA2(x) (((x) >> S_REQDATA2) & M_REQDATA2)
62777 
62778 #define S_REQDATA1    21
62779 #define M_REQDATA1    0x7U
62780 #define V_REQDATA1(x) ((x) << S_REQDATA1)
62781 #define G_REQDATA1(x) (((x) >> S_REQDATA1) & M_REQDATA1)
62782 
62783 #define S_REQDATA0    0
62784 #define M_REQDATA0    0x1fffffU
62785 #define V_REQDATA0(x) ((x) << S_REQDATA0)
62786 #define G_REQDATA0(x) (((x) >> S_REQDATA0) & M_REQDATA0)
62787 
62788 #define A_HMA_DEBUG_PCIE_RSP_DATA_EXTERNAL 0xa006
62789 
62790 #define S_RSPDATA3    24
62791 #define M_RSPDATA3    0xffU
62792 #define V_RSPDATA3(x) ((x) << S_RSPDATA3)
62793 #define G_RSPDATA3(x) (((x) >> S_RSPDATA3) & M_RSPDATA3)
62794 
62795 #define S_RSPDATA2    16
62796 #define M_RSPDATA2    0xffU
62797 #define V_RSPDATA2(x) ((x) << S_RSPDATA2)
62798 #define G_RSPDATA2(x) (((x) >> S_RSPDATA2) & M_RSPDATA2)
62799 
62800 #define S_RSPDATA1    8
62801 #define M_RSPDATA1    0xffU
62802 #define V_RSPDATA1(x) ((x) << S_RSPDATA1)
62803 #define G_RSPDATA1(x) (((x) >> S_RSPDATA1) & M_RSPDATA1)
62804 
62805 #define S_RSPDATA0    0
62806 #define M_RSPDATA0    0xffU
62807 #define V_RSPDATA0(x) ((x) << S_RSPDATA0)
62808 #define G_RSPDATA0(x) (((x) >> S_RSPDATA0) & M_RSPDATA0)
62809 
62810 #define A_HMA_DEBUG_MA_SLV_CTL 0xa007
62811 
62812 #define S_MA_CMD_AVAIL    19
62813 #define V_MA_CMD_AVAIL(x) ((x) << S_MA_CMD_AVAIL)
62814 #define F_MA_CMD_AVAIL    V_MA_CMD_AVAIL(1U)
62815 
62816 #define S_MA_CLNT    15
62817 #define M_MA_CLNT    0xfU
62818 #define V_MA_CLNT(x) ((x) << S_MA_CLNT)
62819 #define G_MA_CLNT(x) (((x) >> S_MA_CLNT) & M_MA_CLNT)
62820 
62821 #define S_MA_WNR    14
62822 #define V_MA_WNR(x) ((x) << S_MA_WNR)
62823 #define F_MA_WNR    V_MA_WNR(1U)
62824 
62825 #define S_MA_LEN    6
62826 #define M_MA_LEN    0xffU
62827 #define V_MA_LEN(x) ((x) << S_MA_LEN)
62828 #define G_MA_LEN(x) (((x) >> S_MA_LEN) & M_MA_LEN)
62829 
62830 #define S_MA_MST_RD    5
62831 #define V_MA_MST_RD(x) ((x) << S_MA_MST_RD)
62832 #define F_MA_MST_RD    V_MA_MST_RD(1U)
62833 
62834 #define S_MA_MST_VLD    4
62835 #define V_MA_MST_VLD(x) ((x) << S_MA_MST_VLD)
62836 #define F_MA_MST_VLD    V_MA_MST_VLD(1U)
62837 
62838 #define S_MA_MST_ERR    3
62839 #define V_MA_MST_ERR(x) ((x) << S_MA_MST_ERR)
62840 #define F_MA_MST_ERR    V_MA_MST_ERR(1U)
62841 
62842 #define S_MAS_TLB_REQ    2
62843 #define V_MAS_TLB_REQ(x) ((x) << S_MAS_TLB_REQ)
62844 #define F_MAS_TLB_REQ    V_MAS_TLB_REQ(1U)
62845 
62846 #define S_MAS_TLB_ACK    1
62847 #define V_MAS_TLB_ACK(x) ((x) << S_MAS_TLB_ACK)
62848 #define F_MAS_TLB_ACK    V_MAS_TLB_ACK(1U)
62849 
62850 #define S_MAS_TLB_ERR    0
62851 #define V_MAS_TLB_ERR(x) ((x) << S_MAS_TLB_ERR)
62852 #define F_MAS_TLB_ERR    V_MAS_TLB_ERR(1U)
62853 
62854 #define A_HMA_DEBUG_MA_SLV_ADDR_INTERNAL 0xa008
62855 #define A_HMA_DEBUG_TLB_HIT_ENTRY 0xa009
62856 #define A_HMA_DEBUG_TLB_HIT_CNT 0xa00a
62857 #define A_HMA_DEBUG_TLB_MISS_CNT 0xa00b
62858 #define A_HMA_DEBUG_PAGE_TBL_LKP_CTL 0xa00c
62859 
62860 #define S_LKP_REQ_VLD    4
62861 #define V_LKP_REQ_VLD(x) ((x) << S_LKP_REQ_VLD)
62862 #define F_LKP_REQ_VLD    V_LKP_REQ_VLD(1U)
62863 
62864 #define S_LKP_DESC_SEL    1
62865 #define M_LKP_DESC_SEL    0x7U
62866 #define V_LKP_DESC_SEL(x) ((x) << S_LKP_DESC_SEL)
62867 #define G_LKP_DESC_SEL(x) (((x) >> S_LKP_DESC_SEL) & M_LKP_DESC_SEL)
62868 
62869 #define S_LKP_RSP_VLD    0
62870 #define V_LKP_RSP_VLD(x) ((x) << S_LKP_RSP_VLD)
62871 #define F_LKP_RSP_VLD    V_LKP_RSP_VLD(1U)
62872 
62873 #define A_HMA_DEBUG_PAGE_TBL_LKP_REQ_ADDR 0xa00d
62874 #define A_HMA_DEBUG_PAGE_TBL_LKP_RSP_0 0xa00e
62875 #define A_HMA_DEBUG_PAGE_TBL_LKP_RSP_1 0xa00f
62876 #define A_HMA_DEBUG_PAGE_TBL_LKP_RSP_2 0xa010
62877 #define A_HMA_DEBUG_PAGE_TBL_LKP_RSP_3 0xa011
62878 #define A_HMA_DEBUG_PAGE_TBL_LKP_RSP_4 0xa012
62879 #define A_HMA_DEBUG_PAGE_TBL_LKP_RSP_5 0xa013
62880 #define A_HMA_DEBUG_PAGE_TBL_LKP_RSP_6 0xa014
62881 #define A_HMA_DEBUG_PAGE_TBL_LKP_RSP_7 0xa015
62882 #define A_HMA_DEBUG_PHYS_DESC_INTERNAL_LO 0xa016
62883 #define A_HMA_DEBUG_PCIE_RD_REQ_CNT_LO 0xa017
62884 #define A_HMA_DEBUG_PCIE_RD_REQ_CNT_HI 0xa018
62885 #define A_HMA_DEBUG_PCIE_WR_REQ_CNT_LO 0xa019
62886 #define A_HMA_DEBUG_PCIE_WR_REQ_CNT_HI 0xa01a
62887 #define A_HMA_DEBUG_PCIE_RD_DATA_CYC_CNT_LO 0xa01b
62888 #define A_HMA_DEBUG_PCIE_RD_DATA_CYC_CNT_HI 0xa01c
62889 #define A_HMA_DEBUG_PCIE_WR_DATA_CYC_CNT_LO 0xa01d
62890 #define A_HMA_DEBUG_PCIE_WR_DATA_CYC_CNT_HI 0xa01e
62891 #define A_HMA_DEBUG_PCIE_SOP_EOP_CNT 0xa01f
62892 
62893 #define S_WR_EOP_CNT    16
62894 #define M_WR_EOP_CNT    0xffU
62895 #define V_WR_EOP_CNT(x) ((x) << S_WR_EOP_CNT)
62896 #define G_WR_EOP_CNT(x) (((x) >> S_WR_EOP_CNT) & M_WR_EOP_CNT)
62897 
62898 #define S_RD_SOP_CNT    8
62899 #define M_RD_SOP_CNT    0xffU
62900 #define V_RD_SOP_CNT(x) ((x) << S_RD_SOP_CNT)
62901 #define G_RD_SOP_CNT(x) (((x) >> S_RD_SOP_CNT) & M_RD_SOP_CNT)
62902 
62903 #define S_RD_EOP_CNT    0
62904 #define M_RD_EOP_CNT    0xffU
62905 #define V_RD_EOP_CNT(x) ((x) << S_RD_EOP_CNT)
62906 #define G_RD_EOP_CNT(x) (((x) >> S_RD_EOP_CNT) & M_RD_EOP_CNT)
62907