| /freebsd/bin/pax/ |
| H A D | options.c | 92 FSUB fsub[] = {
186 FSUB tmp; in pax_options()
363 if ((frmt = (FSUB *)bsearch((void *)&tmp, (void *)fsub, in pax_options()
364 sizeof(fsub)/sizeof(FSUB), sizeof(FSUB), c_frmt)) != NULL) { in pax_options()
370 for (i = 0; i < (sizeof(fsub)/sizeof(FSUB)); ++i) in pax_options()
1019 FSUB tmp; in cpio_options()
1185 if ((frmt = (FSUB *)bsearch((void *)&tmp, (void *)fsub, in cpio_options()
1186 sizeof(fsub)/sizeof(FSUB), sizeof(FSUB), c_frmt)) != NULL) in cpio_options()
1190 for (i = 0; i < (sizeof(fsub)/sizeof(FSUB)); ++i) in cpio_options()
1298 return(strcmp(((const FSUB *)a)->name, ((const FSUB *)b)->name)); in c_frmt()
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| H A D | extern.h | 180 extern FSUB fsub[];
203 extern FSUB *frmt;
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| H A D | pax.h | 71 typedef struct fsub FSUB; typedef
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| H A D | pax.c | 61 FSUB *frmt = NULL; /* archive format type */
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| H A D | ar_subs.c | 561 FSUB *orgfrmt; in append()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/ |
| H A D | PPCSchedPredicates.td | 83 FSUB,
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| H A D | P9InstrResources.td | 419 (instregex "FSUB(S)?$"),
477 (instregex "FSUB(S)?_rec$"),
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| /freebsd/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86TargetTransformInfo.cpp | 955 { ISD::FSUB, MVT::v8f64, { 1, 4, 1, 1 } }, // Skylake from http://www.agner.org/ in getArithmeticInstrCost()
956 { ISD::FSUB, MVT::v4f64, { 1, 4, 1, 1 } }, // Skylake from http://www.agner.org/ in getArithmeticInstrCost()
970 { ISD::FSUB, MVT::v16f32, { 1, 4, 1, 1 } }, // Skylake from http://www.agner.org/ in getArithmeticInstrCost()
971 { ISD::FSUB, MVT::v8f32, { 1, 4, 1, 1 } }, // Skylake from http://www.agner.org/ in getArithmeticInstrCost()
1100 { ISD::FSUB, MVT::v2f64, { 2, 4, 1, 1 } }, // subpd in getArithmeticInstrCost()
1164 { ISD::FSUB, MVT::f64, { 1, 4, 1, 1 } }, // vsubsd in getArithmeticInstrCost()
1165 { ISD::FSUB, MVT::f32, { 1, 4, 1, 1 } }, // vsubss in getArithmeticInstrCost()
1166 { ISD::FSUB, MVT::v2f64, { 1, 4, 1, 1 } }, // vsubpd in getArithmeticInstrCost()
1167 { ISD::FSUB, MVT::v4f32, { 1, 4, 1, 1 } }, // vsubps in getArithmeticInstrCost()
1168 { ISD::FSUB, MVT::v4f64, { 1, 4, 1, 2 } }, // vsubpd in getArithmeticInstrCost()
[all …]
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| H A D | X86IntrinsicsInfo.h | 1043 X86_INTRINSIC_DATA(avx512_sub_pd_512, INTR_TYPE_2OP, ISD::FSUB,
1045 X86_INTRINSIC_DATA(avx512_sub_ps_512, INTR_TYPE_2OP, ISD::FSUB,
1441 X86_INTRINSIC_DATA(avx512fp16_sub_ph_512, INTR_TYPE_2OP, ISD::FSUB,
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| /freebsd/contrib/llvm-project/llvm/lib/Target/VE/ |
| H A D | VVPNodes.def | 113 ADD_BINARY_VVP_OP_COMPACT(FSUB) REGISTER_PACKED(VVP_FSUB)
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| /freebsd/contrib/llvm-project/llvm/include/llvm/IR/ |
| H A D | ConstrainedOps.def | 53 DAG_INSTRUCTION(FSub, 2, 1, experimental_constrained_fsub, FSUB)
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| /freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/ |
| H A D | ISDOpcodes.h | 398 FSUB, enumerator
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| H A D | SDPatternMatch.h | 631 return BinaryOpc_match<LHS, RHS, false>(ISD::FSUB, L, R);
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| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | LegalizeVectorOps.cpp | 355 case ISD::FSUB: in LegalizeOp()
914 case ISD::FSUB: in Expand()
1670 if (TLI.isOperationLegalOrCustom(ISD::FSUB, Node->getValueType(0))) { in ExpandFNEG()
1674 return DAG.getNode(ISD::FSUB, DL, Node->getValueType(0), Zero, in ExpandFNEG()
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| H A D | SelectionDAGBuilder.cpp | 5400 SDValue X = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0, t1); in getLimitedPrecisionExp2()
5538 LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2, in expandLog()
5555 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2, in expandLog()
5561 LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6, in expandLog()
5580 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2, in expandLog()
5586 SDValue t7 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6, in expandLog()
5592 LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t10, in expandLog()
5634 Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2, in expandLog2()
5651 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2, in expandLog2()
5657 Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6, in expandLog2()
[all …]
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| H A D | SelectionDAGBuilder.h | 551 void visitFSub(const User &I) { visitBinary(I, ISD::FSUB); } in visitFSub()
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| H A D | SelectionDAGDumper.cpp | 287 case ISD::FSUB: return "fsub"; in getOperationName()
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| H A D | LegalizeFloatTypes.cpp | 143 case ISD::FSUB: R = SoftenFloatRes_FSUB(N); break; in SoftenFloatResult()
1467 case ISD::FSUB: ExpandFloatRes_FSUB(N, Lo, Hi); break; in ExpandFloatResult()
2637 case ISD::FSUB: R = PromoteFloatRes_BinOp(N); break; in PromoteFloatResult()
3077 case ISD::FSUB: R = SoftPromoteHalfRes_BinOp(N); break; in SoftPromoteHalfResult()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | AMDGPUTargetTransformInfo.cpp | 589 if (OPC == ISD::FADD || OPC == ISD::FSUB) { in getArithmeticInstrCost()
605 case ISD::FSUB: in getArithmeticInstrCost()
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| H A D | AMDGPUISelLowering.cpp | 432 setOperationAction(ISD::FSUB, MVT::f64, Expand); in AMDGPUTargetLowering()
537 ISD::FSQRT, ISD::FSIN, ISD::FSUB, in AMDGPUTargetLowering()
620 ISD::FSUB, ISD::FNEG, in AMDGPUTargetLowering()
648 case ISD::FSUB: in fnegFoldsIntoOpcode()
2464 SDValue Tmp2 = DAG.getNode(ISD::FSUB, SL, MVT::f64, Tmp1, CopySign); in LowerFROUNDEVEN()
2507 SDValue Diff = DAG.getNode(ISD::FSUB, SL, VT, X, T); in LowerFROUND()
2681 return DAG.getNode(ISD::FSUB, SL, VT, Log2, ResultOffset, Flags); in LowerFLOG2()
2758 SDValue YT = DAG.getNode(ISD::FSUB, DL, VT, Y, YH, Flags); in LowerFLOGCommon()
2781 R = DAG.getNode(ISD::FSUB, DL, VT, R, Shift, Flags); in LowerFLOGCommon()
3064 SDValue XL = DAG.getNode(ISD::FSUB, SL, VT, X, XH, Flags); in lowerFEXP()
[all …]
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64SchedFalkorDetails.td | 595 def : InstRW<[FalkorWr_1VXVY_3cyc], (instregex "^(FABD|FADD|FSUB)v2f32$")>;
622 def : InstRW<[FalkorWr_2VXVY_3cyc], (instregex "^(FABD|FADD(P)?|FSUB)(v2f64|v4f32)$")>;
1126 def : InstRW<[FalkorWr_1VXVY_3cyc], (instregex "^(FADD|FSUB)(S|D)rr$")>;
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| H A D | AArch64SchedA57.td | 446 def : InstRW<[A57Write_5cyc_1V], (instregex "^(FABD|FADD|FSUB)(v2f32|32|64|v2i32p)")>;
448 def : InstRW<[A57Write_5cyc_2V], (instregex "^(FABD|FADD|FSUB)(v4f32|v2f64|v2i64p)")>;
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| H A D | AArch64SchedKryoDetails.td | 639 (instregex "(FABD|FADD|FSUB|FADDP)(v4f32|v2f64)")>;
669 (instregex "(FADD|FSUB)(D|S)rr")>;
675 (instregex "(FADD|FSUB|FADDP)v2f32")>;
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Mips/ |
| H A D | MicroMipsInstrFPU.td | 40 defm FSUB : ADDS_MMM<"sub.d", II_SUB_D, 0, fsub>,
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| /freebsd/contrib/llvm-project/llvm/lib/Target/CSKY/ |
| H A D | CSKYInstrInfoF1.td | 124 defm FSUB : FT_XYZ<0b000001, "fsub", BinOpFrag<(fsub node:$LHS, node:$RHS)>>;
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