| /freebsd/contrib/one-true-awk/ |
| H A D | awk.h | 151 #define FSIN 9 macro
|
| H A D | lex.c | 86 { "sin", FSIN, BLTIN },
|
| H A D | run.c | 2098 case FSIN: in bltin()
|
| /freebsd/contrib/llvm-project/llvm/include/llvm/IR/ |
| H A D | ConstrainedOps.def | 101 DAG_FUNCTION(sin, 1, 1, experimental_constrained_sin, FSIN)
|
| H A D | RuntimeLibcalls.td | 2158 def zos___FSIN_B : RuntimeLibcallImpl<SIN_F32, "@@FSIN@B">;
|
| /freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/ |
| H A D | ISDOpcodes.h | 1006 FSIN, enumerator
|
| H A D | BasicTTIImpl.h | 2247 ISD = ISD::FSIN; in getTypeBasedIntrinsicInstrCost()
|
| /freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | R600ISelLowering.cpp | 94 setOperationAction({ISD::FCOS, ISD::FSIN}, MVT::f32, Custom); in R600TargetLowering()
413 case ISD::FSIN: return LowerTrig(Op, DAG); in LowerOperation()
705 case ISD::FSIN: in LowerTrig()
|
| H A D | AMDGPUISelLowering.cpp | 550 ISD::FSQRT, ISD::FSIN, ISD::FSUB, in AMDGPUTargetLowering()
674 case ISD::FSIN: in fnegFoldsIntoOpcode()
5124 case ISD::FSIN: in performFNegCombine()
|
| H A D | SIISelLowering.cpp | 219 ISD::FSIN, ISD::FCOS, ISD::FPOW, ISD::FPOWI, in SITargetLowering()
556 setOperationAction({ISD::FSIN, ISD::FCOS, ISD::FDIV}, MVT::f32, Custom); in SITargetLowering()
616 ISD::FSIN, ISD::FROUND}, in SITargetLowering()
6122 case ISD::FSIN: in LowerOperation()
11862 case ISD::FSIN: in LowerTrig()
13447 case ISD::FSIN: in isCanonicalized()
|
| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | SelectionDAGDumper.cpp | 222 case ISD::FSIN: return "fsin"; in getOperationName()
|
| H A D | LegalizeDAG.cpp | 2421 unsigned OtherOpcode = Node->getOpcode() == ISD::FSIN in useSinCos()
2422 ? ISD::FCOS : ISD::FSIN; in useSinCos()
3772 case ISD::FSIN: in ExpandNode()
3824 Tmp1 = DAG.getNode(ISD::FSIN, dl, VT, Op, Flags); in ExpandNode()
4704 case ISD::FSIN: in ConvertNodeToLibcall()
5800 case ISD::FSIN: in PromoteNode()
|
| H A D | LegalizeFloatTypes.cpp | 145 case ISD::FSIN: R = SoftenFloatRes_FSIN(N); break; in SoftenFloatResult()
1618 case ISD::FSIN: ExpandFloatRes_FSIN(N, Lo, Hi); break; in ExpandFloatResult()
2851 case ISD::FSIN: in PromoteFloatResult()
3337 case ISD::FSIN: in SoftPromoteHalfResult()
|
| H A D | LegalizeVectorOps.cpp | 415 case ISD::FSIN: in LegalizeOp()
|
| H A D | LegalizeVectorTypes.cpp | 121 case ISD::FSIN: in ScalarizeVectorResult()
1254 case ISD::FSIN: in SplitVectorResult()
4917 case ISD::FSIN: in WidenVectorResult()
|
| /freebsd/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86ScheduleAtom.td | 928 def : InstRW<[AtomWrite01_174], (instrs FSINCOS, FSIN, FCOS)>;
|
| H A D | X86InstrFPStack.td | 658 def FSIN : I<0xD9, MRM_FE, (outs), (ins), "fsin", []>;
|
| /freebsd/contrib/llvm-project/llvm/lib/Target/Sparc/ |
| H A D | SparcISelLowering.cpp | 1794 setOperationAction(ISD::FSIN , MVT::f128, Expand); in SparcTargetLowering()
1799 setOperationAction(ISD::FSIN , MVT::f64, Expand); in SparcTargetLowering()
1805 setOperationAction(ISD::FSIN , MVT::f32, Expand); in SparcTargetLowering()
|
| /freebsd/contrib/llvm-project/llvm/lib/Target/CSKY/ |
| H A D | CSKYISelLowering.cpp | 120 ISD::FSIN, ISD::FCOS, ISD::FSINCOS, ISD::FPOW, in CSKYTargetLowering()
|
| /freebsd/contrib/llvm-project/llvm/lib/Target/Xtensa/ |
| H A D | XtensaISelLowering.cpp | 217 setOperationAction(ISD::FSIN, VT, Expand); in XtensaTargetLowering()
|
| /freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
| H A D | HexagonISelLowering.cpp | 1677 {ISD::FDIV, ISD::FREM, ISD::FSQRT, ISD::FSIN, ISD::FCOS, ISD::FSINCOS, in HexagonTargetLowering()
1723 ISD::FREM, ISD::FNEG, ISD::FABS, ISD::FSQRT, ISD::FSIN, in HexagonTargetLowering()
|
| /freebsd/contrib/llvm-project/llvm/lib/Target/Mips/ |
| H A D | MipsISelLowering.cpp | 456 setOperationAction(ISD::FSIN, MVT::f32, Expand); in MipsTargetLowering()
457 setOperationAction(ISD::FSIN, MVT::f64, Expand); in MipsTargetLowering()
|
| /freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/ |
| H A D | PPCISelLowering.cpp | 407 setOperationAction(ISD::FSIN , MVT::f64, Expand); in PPCTargetLowering()
412 setOperationAction(ISD::FSIN , MVT::f32, Expand); in PPCTargetLowering()
421 setOperationAction(ISD::FSIN , MVT::f64, Custom); in PPCTargetLowering()
427 setOperationAction(ISD::FSIN , MVT::f32, Custom); in PPCTargetLowering()
870 setOperationAction(ISD::FSIN, VT, Expand); in PPCTargetLowering()
1207 setOperationAction(ISD::FSIN, MVT::f128, Expand); in PPCTargetLowering()
12544 case ISD::FSIN: return lowerSin(Op, DAG); in LowerOperation()
|
| /freebsd/contrib/llvm-project/llvm/lib/Target/ARM/ |
| H A D | ARMISelLowering.cpp | 387 setOperationAction(ISD::FSIN, VT, Expand); in addMVEVectorTypes()
870 setOperationAction(ISD::FSIN, MVT::v2f64, Expand); in ARMTargetLowering()
893 setOperationAction(ISD::FSIN, MVT::v4f32, Expand); in ARMTargetLowering()
912 setOperationAction(ISD::FSIN, MVT::v2f32, Expand); in ARMTargetLowering()
1062 setOperationAction(ISD::FSIN, MVT::f64, Expand); in ARMTargetLowering()
1415 setOperationAction(ISD::FSIN, MVT::f64, Expand); in ARMTargetLowering()
1416 setOperationAction(ISD::FSIN, MVT::f32, Expand); in ARMTargetLowering()
1501 setOperationAction(ISD::FSIN, MVT::f16, Promote); in ARMTargetLowering()
|
| /freebsd/contrib/llvm-project/llvm/lib/Target/VE/ |
| H A D | VEISelLowering.cpp | 253 setOperationAction(ISD::FSIN, VT, Expand); in initSPUActions()
|