| /freebsd/contrib/one-true-awk/ |
| H A D | awk.h | 151 #define FSIN 9 macro
|
| H A D | lex.c | 86 { "sin", FSIN, BLTIN },
|
| H A D | run.c | 2096 case FSIN: in bltin()
|
| /freebsd/contrib/llvm-project/llvm/include/llvm/IR/ |
| H A D | ConstrainedOps.def | 100 DAG_FUNCTION(sin, 1, 1, experimental_constrained_sin, FSIN)
|
| /freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/ |
| H A D | ISDOpcodes.h | 962 FSIN, enumerator
|
| H A D | BasicTTIImpl.h | 1974 ISD = ISD::FSIN; in getTypeBasedIntrinsicInstrCost()
|
| /freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | R600ISelLowering.cpp | 95 setOperationAction({ISD::FCOS, ISD::FSIN}, MVT::f32, Custom); in R600TargetLowering()
409 case ISD::FSIN: return LowerTrig(Op, DAG); in LowerOperation()
701 case ISD::FSIN: in LowerTrig()
|
| H A D | AMDGPUISelLowering.cpp | 537 ISD::FSQRT, ISD::FSIN, ISD::FSUB, in AMDGPUTargetLowering()
659 case ISD::FSIN: in fnegFoldsIntoOpcode()
4890 case ISD::FSIN: in performFNegCombine()
|
| H A D | SIISelLowering.cpp | 212 ISD::FSIN, ISD::FCOS, ISD::FPOW, ISD::FPOWI, in SITargetLowering()
540 setOperationAction({ISD::FSIN, ISD::FCOS, ISD::FDIV}, MVT::f32, Custom); in SITargetLowering()
600 ISD::FSIN, ISD::FROUND, ISD::FPTRUNC_ROUND}, in SITargetLowering()
5772 case ISD::FSIN: in LowerOperation()
11170 case ISD::FSIN: in LowerTrig()
12683 case ISD::FSIN: in isCanonicalized()
|
| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | SelectionDAGDumper.cpp | 210 case ISD::FSIN: return "fsin"; in getOperationName()
|
| H A D | LegalizeFloatTypes.cpp | 137 case ISD::FSIN: R = SoftenFloatRes_FSIN(N); break; in SoftenFloatResult()
1461 case ISD::FSIN: ExpandFloatRes_FSIN(N, Lo, Hi); break; in ExpandFloatResult()
2617 case ISD::FSIN: in PromoteFloatResult()
3059 case ISD::FSIN: in SoftPromoteHalfResult()
|
| H A D | LegalizeDAG.cpp | 2329 unsigned OtherOpcode = Node->getOpcode() == ISD::FSIN in useSinCos()
2330 ? ISD::FCOS : ISD::FSIN; in useSinCos()
3644 case ISD::FSIN: in ExpandNode()
4524 case ISD::FSIN: in ConvertNodeToLibcall()
5541 case ISD::FSIN: in PromoteNode()
|
| H A D | LegalizeVectorOps.cpp | 402 case ISD::FSIN: in LegalizeOp()
|
| H A D | LegalizeVectorTypes.cpp | 117 case ISD::FSIN: in ScalarizeVectorResult()
1204 case ISD::FSIN: in SplitVectorResult()
4547 case ISD::FSIN: in WidenVectorResult()
|
| /freebsd/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86ScheduleAtom.td | 928 def : InstRW<[AtomWrite01_174], (instrs FSINCOS, FSIN, FCOS)>;
|
| H A D | X86InstrFPStack.td | 658 def FSIN : I<0xD9, MRM_FE, (outs), (ins), "fsin", []>;
|
| /freebsd/contrib/llvm-project/llvm/lib/Target/Sparc/ |
| H A D | SparcISelLowering.cpp | 1800 setOperationAction(ISD::FSIN , MVT::f128, Expand); in SparcTargetLowering()
1805 setOperationAction(ISD::FSIN , MVT::f64, Expand); in SparcTargetLowering()
1810 setOperationAction(ISD::FSIN , MVT::f32, Expand); in SparcTargetLowering()
|
| /freebsd/contrib/llvm-project/llvm/lib/Target/CSKY/ |
| H A D | CSKYISelLowering.cpp | 120 ISD::FSIN, ISD::FCOS, ISD::FSINCOS, ISD::FPOW, in CSKYTargetLowering()
|
| /freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
| H A D | HexagonISelLowering.cpp | 1609 {ISD::FDIV, ISD::FREM, ISD::FSQRT, ISD::FSIN, ISD::FCOS, ISD::FSINCOS, in HexagonTargetLowering()
1654 ISD::FREM, ISD::FNEG, ISD::FABS, ISD::FSQRT, ISD::FSIN, in HexagonTargetLowering()
|
| /freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/ |
| H A D | PPCISelLowering.cpp | 399 setOperationAction(ISD::FSIN , MVT::f64, Expand); in PPCTargetLowering()
404 setOperationAction(ISD::FSIN , MVT::f32, Expand); in PPCTargetLowering()
413 setOperationAction(ISD::FSIN , MVT::f64, Custom); in PPCTargetLowering()
419 setOperationAction(ISD::FSIN , MVT::f32, Custom); in PPCTargetLowering()
861 setOperationAction(ISD::FSIN, VT, Expand); in PPCTargetLowering()
1190 setOperationAction(ISD::FSIN, MVT::f128, Expand); in PPCTargetLowering()
11797 case ISD::FSIN: return lowerSin(Op, DAG); in LowerOperation()
|
| /freebsd/contrib/llvm-project/llvm/lib/Target/Mips/ |
| H A D | MipsISelLowering.cpp | 448 setOperationAction(ISD::FSIN, MVT::f32, Expand); in MipsTargetLowering()
449 setOperationAction(ISD::FSIN, MVT::f64, Expand); in MipsTargetLowering()
|
| /freebsd/contrib/llvm-project/llvm/lib/Target/ARM/ |
| H A D | ARMISelLowering.cpp | 377 setOperationAction(ISD::FSIN, VT, Expand); in addMVEVectorTypes()
880 setOperationAction(ISD::FSIN, MVT::v2f64, Expand); in ARMTargetLowering()
903 setOperationAction(ISD::FSIN, MVT::v4f32, Expand); in ARMTargetLowering()
921 setOperationAction(ISD::FSIN, MVT::v2f32, Expand); in ARMTargetLowering()
1064 setOperationAction(ISD::FSIN, MVT::f64, Expand); in ARMTargetLowering()
1458 setOperationAction(ISD::FSIN, MVT::f64, Expand); in ARMTargetLowering()
1459 setOperationAction(ISD::FSIN, MVT::f32, Expand); in ARMTargetLowering()
1542 setOperationAction(ISD::FSIN, MVT::f16, Promote); in ARMTargetLowering()
|
| /freebsd/contrib/llvm-project/llvm/lib/Target/WebAssembly/ |
| H A D | WebAssemblyISelLowering.cpp | 132 {ISD::FSIN, ISD::FCOS, ISD::FSINCOS, ISD::FPOW, ISD::FREM, ISD::FMA}) in WebAssemblyTargetLowering()
|
| /freebsd/contrib/llvm-project/llvm/lib/Target/LoongArch/ |
| H A D | LoongArchISelLowering.cpp | 178 setOperationAction(ISD::FSIN, MVT::f32, Expand); in LoongArchTargetLowering()
215 setOperationAction(ISD::FSIN, MVT::f64, Expand); in LoongArchTargetLowering()
|
| /freebsd/contrib/llvm-project/llvm/lib/Target/VE/ |
| H A D | VEISelLowering.cpp | 253 setOperationAction(ISD::FSIN, VT, Expand); in initSPUActions()
|