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Searched refs:FSHR (Results 1 – 23 of 23) sorted by relevance

/freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DISDOpcodes.h739 FSHR, enumerator
/freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonISelLoweringHVX.cpp240 setOperationAction(ISD::FSHR, T, Custom); in initializeHVXLowering()
316 setOperationAction(ISD::FSHR, T, Custom); in initializeHVXLowering()
2075 assert(Opc == ISD::FSHL || Opc == ISD::FSHR); in LowerHvxFunnelShift()
2108 // FSHR A, B => A <<n | B >> in LowerHvxFunnelShift()
3180 case ISD::FSHR: in LowerHvxOperation()
3220 case ISD::FSHR: return LowerHvxFunnelShift(Op, DAG); in LowerHvxOperation()
H A DHexagonISelLowering.cpp1596 setOperationAction(ISD::FSHR, MVT::i32, Legal); in HexagonTargetLowering()
1597 setOperationAction(ISD::FSHR, MVT::i64, Legal); in HexagonTargetLowering()
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DSelectionDAGDumper.cpp284 case ISD::FSHR: return "fshr"; in getOperationName()
H A DLegalizeIntegerTypes.cpp316 case ISD::FSHR: in PromoteIntegerResult()
1541 bool IsFSHR = Opcode == ISD::FSHR; in PromoteIntRes_FunnelShift()
1983 case ISD::FSHR: Res = PromoteIntOp_FunnelShift(N); break; in PromoteIntegerOperand()
2940 case ISD::FSHR: in ExpandIntegerResult()
4341 Lo = DAG.getNode(ISD::FSHR, dl, NVT, Result[Part0 + 1], Result[Part0], in ExpandIntRes_MULFIX()
4343 Hi = DAG.getNode(ISD::FSHR, dl, NVT, Result[Part0 + 2], Result[Part0 + 1], in ExpandIntRes_MULFIX()
5184 unsigned Opcode = N->getOpcode() == ISD::ROTL ? ISD::FSHL : ISD::FSHR; in ExpandIntRes_Rotate()
H A DLegalizeVectorOps.cpp366 case ISD::FSHR: in LegalizeOp()
994 case ISD::FSHR: in Expand()
H A DTargetLowering.cpp2132 case ISD::FSHR: { in SimplifyDemandedBits()
4403 (N0.getOpcode() != ISD::FSHL && N0.getOpcode() != ISD::FSHR)) in foldSetCCWithFunnelShift()
4413 if (N0.getOpcode() == ISD::FSHR) in foldSetCCWithFunnelShift()
7997 unsigned RevOpcode = IsFSHL ? ISD::FSHR : ISD::FSHL; in expandFunnelShift()
8148 Tmp2 = DAG.getNode(ISD::FSHR, dl, VT, ShOpHi, ShOpLo, ShAmt); in expandShiftParts()
10729 SDValue Result = DAG.getNode(ISD::FSHR, dl, VT, Hi, Lo, in expandFixedPointMul()
H A DDAGCombiner.cpp1891 case ISD::FSHR: return visitFunnelShift(N); in visit()
5854 if ((HandOpcode == ISD::FSHL || HandOpcode == ISD::FSHR) && in hoistLogicOpWithSameOpcodeHands()
7808 if (N0.getOpcode() == ISD::FSHR && N1.getOpcode() == ISD::SRL && in visitORCommutative()
8374 TLI.isOperationLegalOrCustom(ISD::FSHR, VT)) { in MatchFunnelPosNeg()
8375 return DAG.getNode(ISD::FSHR, DL, VT, N0.getOperand(0), N1, Neg); in MatchFunnelPosNeg()
8384 TLI.isOperationLegalOrCustom(ISD::FSHR, VT)) { in MatchFunnelPosNeg()
8385 return DAG.getNode(ISD::FSHR, DL, VT, N0.getOperand(0), N1, Neg); in MatchFunnelPosNeg()
8405 bool HasFSHR = hasOperation(ISD::FSHR, VT); in MatchRotate()
8572 Res = DAG.getNode(UseFSHL ? ISD::FSHL : ISD::FSHR, DL, VT, LHSShiftArg, in MatchRotate()
8620 LExtOp0, RExtOp0, HasFSHL, ISD::FSHL, ISD::FSHR, DL); in MatchRotate()
[all …]
H A DLegalizeVectorTypes.cpp194 case ISD::FSHR: in ScalarizeVectorResult()
1288 case ISD::FSHR: in SplitVectorResult()
4594 case ISD::FSHR: in WidenVectorResult()
H A DLegalizeDAG.cpp1279 case ISD::FSHR: in LegalizeOp()
3881 case ISD::FSHR: in ExpandNode()
H A DSelectionDAG.cpp3618 case ISD::FSHR: in computeKnownBits()
5272 case ISD::FSHR: in canCreateUndefOrPoison()
H A DSelectionDAGBuilder.cpp7172 auto FunnelOpcode = IsFSHL ? ISD::FSHL : ISD::FSHR; in visitIntrinsicCall()
/freebsd/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86ISelLowering.h40 FSHR, enumerator
H A DX86InstrFragments.td145 def X86fshr : SDNode<"X86ISD::FSHR", SDTIntShiftDOp>;
H A DX86ISelLowering.cpp246 for (auto ShiftOp : {ISD::FSHL, ISD::FSHR}) { in X86TargetLowering()
1295 setOperationAction(ISD::FSHR, VT, Custom); in X86TargetLowering()
1502 setOperationAction(ISD::FSHR, VT, Custom); in X86TargetLowering()
1969 setOperationAction(ISD::FSHR, MVT::v64i8, Custom); in X86TargetLowering()
1971 setOperationAction(ISD::FSHR, MVT::v32i16, Custom); in X86TargetLowering()
1973 setOperationAction(ISD::FSHR, MVT::v16i32, Custom); in X86TargetLowering()
2041 setOperationAction(ISD::FSHR, VT, Custom); in X86TargetLowering()
2057 setOperationAction(ISD::FSHR, VT, Custom); in X86TargetLowering()
29951 assert((Op.getOpcode() == ISD::FSHL || Op.getOpcode() == ISD::FSHR) && in LowerFunnelShift()
29959 bool IsFSHR = Op.getOpcode() == ISD::FSHR; in LowerFunnelShift()
[all …]
/freebsd/contrib/llvm-project/llvm/include/llvm/IR/
H A DVPIntrinsics.def303 VP_PROPERTY_FUNCTIONAL_SDOPC(FSHR)
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/
H A DTargetLoweringBase.cpp719 ISD::FSHL, ISD::FSHR, in initActions()
/freebsd/contrib/llvm-project/llvm/include/llvm/Target/
H A DTargetSelectionDAG.td423 def fshr : SDNode<"ISD::FSHR" , SDTIntShiftDOp>;
/freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCISelLowering.cpp763 setOperationAction(ISD::FSHR, MVT::i64, Custom); in PPCTargetLowering()
766 setOperationAction(ISD::FSHR, MVT::i32, Custom); in PPCTargetLowering()
11850 case ISD::FSHR: return LowerFunnelShift(Op, DAG); in LowerOperation()
11977 case ISD::FSHR: in ReplaceNodeResults()
/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DSIISelLowering.cpp914 ISD::FSHR, in SITargetLowering()
11858 case ISD::FSHR: { in calculateByteProvider()
14714 case ISD::FSHR: { in PerformDAGCombine()
H A DAMDGPUISelLowering.cpp479 setOperationAction(ISD::FSHR, MVT::i32, Legal); in AMDGPUTargetLowering()
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64ISelLowering.cpp617 setOperationAction(ISD::FSHR, MVT::i32, Custom); in AArch64TargetLowering()
618 setOperationAction(ISD::FSHR, MVT::i64, Custom); in AArch64TargetLowering()
6641 ISD::FSHR, DL, VT, Op.getOperand(0), Op.getOperand(1), in LowerFunnelShift()
6643 } else if (Op.getOpcode() == ISD::FSHR) { in LowerFunnelShift()
7082 case ISD::FSHR: in LowerOperation()
/freebsd/contrib/llvm-project/llvm/lib/Target/NVPTX/
H A DNVPTXISelLowering.cpp531 ISD::FP_TO_SINT, ISD::FP_TO_UINT, ISD::FSHL, ISD::FSHR, in NVPTXTargetLowering()