| /freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/ |
| H A D | ISDOpcodes.h | 762 FSHR, enumerator
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| H A D | BasicTTIImpl.h | 2495 ISD = ISD::FSHR; in getTypeBasedIntrinsicInstrCost()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
| H A D | HexagonISelLoweringHVX.cpp | 244 setOperationAction(ISD::FSHR, T, Custom); in initializeHVXLowering()
322 setOperationAction(ISD::FSHR, T, Custom); in initializeHVXLowering()
2112 assert(Opc == ISD::FSHL || Opc == ISD::FSHR); in LowerHvxFunnelShift()
3217 case ISD::FSHR: in LowerHvxOperation()
3257 case ISD::FSHR: return LowerHvxFunnelShift(Op, DAG); in LowerHvxOperation()
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| H A D | HexagonISelLowering.cpp | 1664 setOperationAction(ISD::FSHR, MVT::i32, Legal); in HexagonTargetLowering()
1665 setOperationAction(ISD::FSHR, MVT::i64, Legal); in HexagonTargetLowering()
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| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | SelectionDAGDumper.cpp | 301 case ISD::FSHR: return "fshr"; in getOperationName()
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| H A D | LegalizeIntegerTypes.cpp | 336 case ISD::FSHR: in PromoteIntegerResult()
1586 bool IsFSHR = Opcode == ISD::FSHR; in PromoteIntRes_FunnelShift()
2034 case ISD::FSHR: Res = PromoteIntOp_FunnelShift(N); break; in PromoteIntegerOperand()
3123 case ISD::FSHR: in ExpandIntegerResult()
4565 Lo = DAG.getNode(ISD::FSHR, dl, NVT, Result[Part0 + 1], Result[Part0], in ExpandIntRes_MULFIX()
4567 Hi = DAG.getNode(ISD::FSHR, dl, NVT, Result[Part0 + 2], Result[Part0 + 1], in ExpandIntRes_MULFIX()
5420 unsigned Opcode = N->getOpcode() == ISD::ROTL ? ISD::FSHL : ISD::FSHR; in ExpandIntRes_Rotate()
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| H A D | LegalizeVectorOps.cpp | 377 case ISD::FSHR: in LegalizeOp()
1121 case ISD::FSHR: in Expand()
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| H A D | TargetLowering.cpp | 2200 case ISD::FSHR: { in SimplifyDemandedBits()
4613 (N0.getOpcode() != ISD::FSHL && N0.getOpcode() != ISD::FSHR)) in foldSetCCWithFunnelShift()
4626 if (N0.getOpcode() == ISD::FSHR) in foldSetCCWithFunnelShift()
8215 unsigned RevOpcode = IsFSHL ? ISD::FSHR : ISD::FSHL; in expandFunnelShift()
8366 Tmp2 = DAG.getNode(ISD::FSHR, dl, VT, ShOpHi, ShOpLo, ShAmt); in expandShiftParts()
11231 SDValue Result = DAG.getNode(ISD::FSHR, dl, VT, Hi, Lo, in expandFixedPointMul()
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| H A D | DAGCombiner.cpp | 1949 case ISD::FSHR: return visitFunnelShift(N); in visit()
6232 if ((HandOpcode == ISD::FSHL || HandOpcode == ISD::FSHR) && in hoistLogicOpWithSameOpcodeHands()
8268 if (N0.getOpcode() == ISD::FSHR && N1.getOpcode() == ISD::SRL && in visitORCommutative()
8831 TLI.isOperationLegalOrCustom(ISD::FSHR, VT)) { in MatchFunnelPosNeg()
8832 return DAG.getNode(ISD::FSHR, DL, VT, X, N1, Neg); in MatchFunnelPosNeg()
8841 TLI.isOperationLegalOrCustom(ISD::FSHR, VT)) { in MatchFunnelPosNeg()
8842 return DAG.getNode(ISD::FSHR, DL, VT, X, N1, Neg); in MatchFunnelPosNeg()
8863 bool HasFSHR = hasOperation(ISD::FSHR, VT); in MatchRotate()
9030 Res = DAG.getNode(UseFSHL ? ISD::FSHL : ISD::FSHR, DL, VT, LHSShiftArg, in MatchRotate()
9076 HasFSHL, ISD::FSHL, ISD::FSHR, DL)) in MatchRotate()
[all …]
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| H A D | LegalizeVectorTypes.cpp | 206 case ISD::FSHR: in ScalarizeVectorResult()
1347 case ISD::FSHR: in SplitVectorResult()
4965 case ISD::FSHR: in WidenVectorResult()
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| H A D | LegalizeDAG.cpp | 1314 case ISD::FSHR: in LegalizeOp()
4020 case ISD::FSHR: in ExpandNode()
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| H A D | SelectionDAG.cpp | 3861 case ISD::FSHR: in computeKnownBits()
5556 case ISD::FSHR: in canCreateUndefOrPoison()
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| H A D | SelectionDAGBuilder.cpp | 7224 auto FunnelOpcode = IsFSHL ? ISD::FSHL : ISD::FSHR; in visitIntrinsicCall()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86ISelLowering.h | 40 FSHR, enumerator
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| H A D | X86InstrFragments.td | 140 def X86fshr : SDNode<"X86ISD::FSHR", SDTIntShiftDOp>;
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| H A D | X86ISelLowering.cpp | 231 for (auto ShiftOp : {ISD::FSHL, ISD::FSHR}) { in X86TargetLowering()
1316 setOperationAction(ISD::FSHR, VT, Custom); in X86TargetLowering()
1526 setOperationAction(ISD::FSHR, VT, Custom); in X86TargetLowering()
2001 setOperationAction(ISD::FSHR, MVT::v64i8, Custom); in X86TargetLowering()
2003 setOperationAction(ISD::FSHR, MVT::v32i16, Custom); in X86TargetLowering()
2005 setOperationAction(ISD::FSHR, MVT::v16i32, Custom); in X86TargetLowering()
2075 setOperationAction(ISD::FSHR, VT, Custom); in X86TargetLowering()
2091 setOperationAction(ISD::FSHR, VT, Custom); in X86TargetLowering()
31168 assert((Op.getOpcode() == ISD::FSHL || Op.getOpcode() == ISD::FSHR) && in LowerFunnelShift()
31176 bool IsFSHR = Op.getOpcode() == ISD::FSHR; in LowerFunnelShift()
[all …]
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| /freebsd/contrib/llvm-project/llvm/include/llvm/IR/ |
| H A D | VPIntrinsics.def | 276 VP_PROPERTY_FUNCTIONAL_SDOPC(FSHR)
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| /freebsd/contrib/llvm-project/llvm/lib/Target/NVPTX/ |
| H A D | NVPTXISelLowering.cpp | 642 ISD::FP_TO_SINT, ISD::FP_TO_UINT, ISD::FSHL, ISD::FSHR, in NVPTXTargetLowering()
693 setOperationAction({ISD::FSHL, ISD::FSHR}, MVT::i32, Legal); in NVPTXTargetLowering()
694 setOperationAction({ISD::ROTL, ISD::ROTR, ISD::FSHL, ISD::FSHR}, MVT::i64, in NVPTXTargetLowering()
2809 unsigned Opcode = Op->getOpcode() == ISD::ROTL ? ISD::FSHL : ISD::FSHR; in lowerROT()
2938 case ISD::FSHR: in LowerOperation()
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| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/ |
| H A D | TargetLoweringBase.cpp | 800 ISD::FSHL, ISD::FSHR, in initActions()
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| /freebsd/contrib/llvm-project/llvm/include/llvm/Target/ |
| H A D | TargetSelectionDAG.td | 439 def fshr : SDNode<"ISD::FSHR" , SDTIntShiftDOp>;
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| /freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/ |
| H A D | PPCISelLowering.cpp | 770 setOperationAction(ISD::FSHR, MVT::i64, Custom); in PPCTargetLowering()
773 setOperationAction(ISD::FSHR, MVT::i32, Custom); in PPCTargetLowering()
12601 case ISD::FSHR: return LowerFunnelShift(Op, DAG); in LowerOperation()
12740 case ISD::FSHR: in ReplaceNodeResults()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64ISelLowering.cpp | 631 setOperationAction(ISD::FSHR, MVT::i32, Custom); in AArch64TargetLowering()
632 setOperationAction(ISD::FSHR, MVT::i64, Custom); in AArch64TargetLowering()
7069 ISD::FSHR, DL, VT, Op.getOperand(0), Op.getOperand(1), in LowerFunnelShift()
7073 if (Op.getOpcode() == ISD::FSHR) { in LowerFunnelShift()
7082 ISD::FSHR, DL, VT, Op.getOperand(0), Op.getOperand(1), in LowerFunnelShift()
7556 case ISD::FSHR: in LowerOperation()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/SystemZ/ |
| H A D | SystemZISelLowering.cpp | 258 setOperationAction(ISD::FSHR, MVT::i128, Custom); in SystemZTargetLowering()
7138 case ISD::FSHR: in LowerOperation()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | SIISelLowering.cpp | 982 ISD::FSHR, in SITargetLowering()
12628 case ISD::FSHR: { in calculateByteProvider()
15742 case ISD::FSHR: { in PerformDAGCombine()
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| H A D | AMDGPUISelLowering.cpp | 492 setOperationAction(ISD::FSHR, MVT::i32, Legal); in AMDGPUTargetLowering()
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