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Searched refs:FSHL (Results 1 – 24 of 24) sorted by relevance

/freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DISDOpcodes.h761 FSHL, enumerator
H A DBasicTTIImpl.h2492 ISD = ISD::FSHL; in getTypeBasedIntrinsicInstrCost()
/freebsd/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86TargetTransformInfo.cpp3627 { ISD::FSHL, MVT::v8i64, { 1, 1, 1, 1 } }, in getIntrinsicInstrCost()
3628 { ISD::FSHL, MVT::v4i64, { 1, 1, 1, 1 } }, in getIntrinsicInstrCost()
3629 { ISD::FSHL, MVT::v2i64, { 1, 1, 1, 1 } }, in getIntrinsicInstrCost()
3630 { ISD::FSHL, MVT::v16i32, { 1, 1, 1, 1 } }, in getIntrinsicInstrCost()
3631 { ISD::FSHL, MVT::v8i32, { 1, 1, 1, 1 } }, in getIntrinsicInstrCost()
3632 { ISD::FSHL, MVT::v4i32, { 1, 1, 1, 1 } }, in getIntrinsicInstrCost()
3633 { ISD::FSHL, MVT::v32i16, { 1, 1, 1, 1 } }, in getIntrinsicInstrCost()
3634 { ISD::FSHL, MVT::v16i16, { 1, 1, 1, 1 } }, in getIntrinsicInstrCost()
3635 { ISD::FSHL, MVT::v8i16, { 1, 1, 1, 1 } }, in getIntrinsicInstrCost()
4381 { ISD::FSHL, MVT::i64, { 4, 4, 1, 4 } }, in getIntrinsicInstrCost()
[all …]
H A DX86ISelLowering.h39 FSHL, enumerator
H A DX86InstrFragments.td139 def X86fshl : SDNode<"X86ISD::FSHL", SDTIntShiftDOp>;
H A DX86ISelLowering.cpp231 for (auto ShiftOp : {ISD::FSHL, ISD::FSHR}) { in X86TargetLowering()
1315 setOperationAction(ISD::FSHL, VT, Custom); in X86TargetLowering()
1525 setOperationAction(ISD::FSHL, VT, Custom); in X86TargetLowering()
2000 setOperationAction(ISD::FSHL, MVT::v64i8, Custom); in X86TargetLowering()
2002 setOperationAction(ISD::FSHL, MVT::v32i16, Custom); in X86TargetLowering()
2004 setOperationAction(ISD::FSHL, MVT::v16i32, Custom); in X86TargetLowering()
2074 setOperationAction(ISD::FSHL, VT, Custom); in X86TargetLowering()
2090 setOperationAction(ISD::FSHL, VT, Custom); in X86TargetLowering()
31168 assert((Op.getOpcode() == ISD::FSHL || Op.getOpcode() == ISD::FSHR) && in LowerFunnelShift()
31360 unsigned FSHOp = (IsFSHR ? X86ISD::FSHR : X86ISD::FSHL); in LowerFunnelShift()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonISelLoweringHVX.cpp243 setOperationAction(ISD::FSHL, T, Custom); in initializeHVXLowering()
321 setOperationAction(ISD::FSHL, T, Custom); in initializeHVXLowering()
2112 assert(Opc == ISD::FSHL || Opc == ISD::FSHR); in LowerHvxFunnelShift()
2125 bool IsLeft = Opc == ISD::FSHL; in LowerHvxFunnelShift()
2159 unsigned MOpc = Opc == ISD::FSHL ? HexagonISD::MFSHL : HexagonISD::MFSHR; in LowerHvxFunnelShift()
3216 case ISD::FSHL: in LowerHvxOperation()
3256 case ISD::FSHL: in LowerHvxOperation()
H A DHexagonISelLowering.cpp1662 setOperationAction(ISD::FSHL, MVT::i32, Legal); in HexagonTargetLowering()
1663 setOperationAction(ISD::FSHL, MVT::i64, Legal); in HexagonTargetLowering()
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DSelectionDAGDumper.cpp300 case ISD::FSHL: return "fshl"; in getOperationName()
H A DLegalizeVectorOps.cpp376 case ISD::FSHL: in LegalizeOp()
1119 case ISD::FSHL: in Expand()
H A DLegalizeIntegerTypes.cpp335 case ISD::FSHL: in PromoteIntegerResult()
2033 case ISD::FSHL: in PromoteIntegerOperand()
3122 case ISD::FSHL: in ExpandIntegerResult()
5420 unsigned Opcode = N->getOpcode() == ISD::ROTL ? ISD::FSHL : ISD::FSHR; in ExpandIntRes_Rotate()
5446 Opc == ISD::FSHL ? ISD::SETNE : ISD::SETEQ); in ExpandIntRes_FunnelShift()
H A DTargetLowering.cpp2199 case ISD::FSHL: in SimplifyDemandedBits()
2204 bool IsFSHL = (Op.getOpcode() == ISD::FSHL); in SimplifyDemandedBits()
4613 (N0.getOpcode() != ISD::FSHL && N0.getOpcode() != ISD::FSHR)) in foldSetCCWithFunnelShift()
8209 bool IsFSHL = Node->getOpcode() == ISD::FSHL; in expandFunnelShift()
8215 unsigned RevOpcode = IsFSHL ? ISD::FSHR : ISD::FSHL; in expandFunnelShift()
8363 Tmp2 = DAG.getNode(ISD::FSHL, dl, VT, ShOpHi, ShOpLo, ShAmt); in expandShiftParts()
H A DDAGCombiner.cpp1948 case ISD::FSHL: in visit()
6232 if ((HandOpcode == ISD::FSHL || HandOpcode == ISD::FSHR) && in hoistLogicOpWithSameOpcodeHands()
8262 if (N0.getOpcode() == ISD::FSHL && N1.getOpcode() == ISD::SHL && in visitORCommutative()
8815 if (PosOpcode == ISD::FSHL && isPowerOf2_32(EltBits)) { in MatchFunnelPosNeg()
8822 TLI.isOperationLegalOrCustom(ISD::FSHL, VT)) { in MatchFunnelPosNeg()
8823 return DAG.getNode(ISD::FSHL, DL, VT, N0, X, Pos); in MatchFunnelPosNeg()
8862 bool HasFSHL = hasOperation(ISD::FSHL, VT); in MatchRotate()
9030 Res = DAG.getNode(UseFSHL ? ISD::FSHL : ISD::FSHR, DL, VT, LHSShiftArg, in MatchRotate()
9076 HasFSHL, ISD::FSHL, ISD::FSHR, DL)) in MatchRotate()
9081 HasFSHR, ISD::FSHR, ISD::FSHL, DL)) in MatchRotate()
[all …]
H A DLegalizeVectorTypes.cpp205 case ISD::FSHL: in ScalarizeVectorResult()
1345 case ISD::FSHL: in SplitVectorResult()
4963 case ISD::FSHL: in WidenVectorResult()
H A DSelectionDAG.cpp3860 case ISD::FSHL: in computeKnownBits()
3868 Known = computeKnownBits(Op.getOperand(Opcode == ISD::FSHL ? 0 : 1), in computeKnownBits()
3877 if (Opcode == ISD::FSHL) { in computeKnownBits()
5555 case ISD::FSHL: in canCreateUndefOrPoison()
H A DLegalizeDAG.cpp1313 case ISD::FSHL: in LegalizeOp()
4019 case ISD::FSHL: in ExpandNode()
H A DSelectionDAGBuilder.cpp7224 auto FunnelOpcode = IsFSHL ? ISD::FSHL : ISD::FSHR; in visitIntrinsicCall()
/freebsd/contrib/llvm-project/llvm/lib/Target/NVPTX/
H A DNVPTXISelLowering.cpp642 ISD::FP_TO_SINT, ISD::FP_TO_UINT, ISD::FSHL, ISD::FSHR, in NVPTXTargetLowering()
693 setOperationAction({ISD::FSHL, ISD::FSHR}, MVT::i32, Legal); in NVPTXTargetLowering()
694 setOperationAction({ISD::ROTL, ISD::ROTR, ISD::FSHL, ISD::FSHR}, MVT::i64, in NVPTXTargetLowering()
2792 auto [High, Mid, Low] = ((Opcode == ISD::FSHL) == (Amt < 32)) in expandFSH64()
2809 unsigned Opcode = Op->getOpcode() == ISD::ROTL ? ISD::FSHL : ISD::FSHR; in lowerROT()
2937 case ISD::FSHL: in LowerOperation()
/freebsd/contrib/llvm-project/llvm/include/llvm/IR/
H A DVPIntrinsics.def270 VP_PROPERTY_FUNCTIONAL_SDOPC(FSHL)
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/
H A DTargetLoweringBase.cpp800 ISD::FSHL, ISD::FSHR, in initActions()
/freebsd/contrib/llvm-project/llvm/include/llvm/Target/
H A DTargetSelectionDAG.td438 def fshl : SDNode<"ISD::FSHL" , SDTIntShiftDOp>;
/freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCISelLowering.cpp769 setOperationAction(ISD::FSHL, MVT::i64, Custom); in PPCTargetLowering()
772 setOperationAction(ISD::FSHL, MVT::i32, Custom); in PPCTargetLowering()
9339 bool IsFSHL = Op.getOpcode() == ISD::FSHL; in LowerFunnelShift()
12600 case ISD::FSHL: return LowerFunnelShift(Op, DAG); in LowerOperation()
12739 case ISD::FSHL: in ReplaceNodeResults()
/freebsd/contrib/llvm-project/llvm/lib/Target/SystemZ/
H A DSystemZISelLowering.cpp257 setOperationAction(ISD::FSHL, MVT::i128, Custom); in SystemZTargetLowering()
7136 case ISD::FSHL: in LowerOperation()
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64ISelLowering.cpp633 setOperationAction(ISD::FSHL, MVT::i32, Custom); in AArch64TargetLowering()
634 setOperationAction(ISD::FSHL, MVT::i64, Custom); in AArch64TargetLowering()
7063 if (Op.getOpcode() == ISD::FSHL) { in LowerFunnelShift()
7555 case ISD::FSHL: in LowerOperation()