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Searched refs:FSHL (Results 1 – 22 of 22) sorted by relevance

/freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DISDOpcodes.h738 FSHL, enumerator
/freebsd/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86TargetTransformInfo.cpp3473 { ISD::FSHL, MVT::v8i64, { 1, 1, 1, 1 } }, in getIntrinsicInstrCost()
3474 { ISD::FSHL, MVT::v4i64, { 1, 1, 1, 1 } }, in getIntrinsicInstrCost()
3475 { ISD::FSHL, MVT::v2i64, { 1, 1, 1, 1 } }, in getIntrinsicInstrCost()
3476 { ISD::FSHL, MVT::v16i32, { 1, 1, 1, 1 } }, in getIntrinsicInstrCost()
3477 { ISD::FSHL, MVT::v8i32, { 1, 1, 1, 1 } }, in getIntrinsicInstrCost()
3478 { ISD::FSHL, MVT::v4i32, { 1, 1, 1, 1 } }, in getIntrinsicInstrCost()
3479 { ISD::FSHL, MVT::v32i16, { 1, 1, 1, 1 } }, in getIntrinsicInstrCost()
3480 { ISD::FSHL, MVT::v16i16, { 1, 1, 1, 1 } }, in getIntrinsicInstrCost()
3481 { ISD::FSHL, MVT::v8i16, { 1, 1, 1, 1 } }, in getIntrinsicInstrCost()
4109 { ISD::FSHL, MVT::i64, { 4, 4, 1, 4 } }, in getIntrinsicInstrCost()
[all …]
H A DX86ISelLowering.h39 FSHL, enumerator
H A DX86InstrFragments.td144 def X86fshl : SDNode<"X86ISD::FSHL", SDTIntShiftDOp>;
H A DX86ISelLowering.cpp246 for (auto ShiftOp : {ISD::FSHL, ISD::FSHR}) { in X86TargetLowering()
1294 setOperationAction(ISD::FSHL, VT, Custom); in X86TargetLowering()
1501 setOperationAction(ISD::FSHL, VT, Custom); in X86TargetLowering()
1968 setOperationAction(ISD::FSHL, MVT::v64i8, Custom); in X86TargetLowering()
1970 setOperationAction(ISD::FSHL, MVT::v32i16, Custom); in X86TargetLowering()
1972 setOperationAction(ISD::FSHL, MVT::v16i32, Custom); in X86TargetLowering()
2040 setOperationAction(ISD::FSHL, VT, Custom); in X86TargetLowering()
2056 setOperationAction(ISD::FSHL, VT, Custom); in X86TargetLowering()
29951 assert((Op.getOpcode() == ISD::FSHL || Op.getOpcode() == ISD::FSHR) && in LowerFunnelShift()
30143 unsigned FSHOp = (IsFSHR ? X86ISD::FSHR : X86ISD::FSHL); in LowerFunnelShift()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonISelLoweringHVX.cpp239 setOperationAction(ISD::FSHL, T, Custom); in initializeHVXLowering()
315 setOperationAction(ISD::FSHL, T, Custom); in initializeHVXLowering()
2075 assert(Opc == ISD::FSHL || Opc == ISD::FSHR); in LowerHvxFunnelShift()
2088 bool IsLeft = Opc == ISD::FSHL; in LowerHvxFunnelShift()
2107 // FSHL A, B => A << | B >>n in LowerHvxFunnelShift()
2122 unsigned MOpc = Opc == ISD::FSHL ? HexagonISD::MFSHL : HexagonISD::MFSHR; in LowerHvxFunnelShift()
3179 case ISD::FSHL: in LowerHvxOperation()
3219 case ISD::FSHL: in LowerHvxOperation()
H A DHexagonISelLowering.cpp1594 setOperationAction(ISD::FSHL, MVT::i32, Legal); in HexagonTargetLowering()
1595 setOperationAction(ISD::FSHL, MVT::i64, Legal); in HexagonTargetLowering()
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DSelectionDAGDumper.cpp283 case ISD::FSHL: return "fshl"; in getOperationName()
H A DLegalizeVectorOps.cpp365 case ISD::FSHL: in LegalizeOp()
992 case ISD::FSHL: in Expand()
H A DLegalizeIntegerTypes.cpp315 case ISD::FSHL: in PromoteIntegerResult()
1982 case ISD::FSHL: in PromoteIntegerOperand()
2939 case ISD::FSHL: in ExpandIntegerResult()
5184 unsigned Opcode = N->getOpcode() == ISD::ROTL ? ISD::FSHL : ISD::FSHR; in ExpandIntRes_Rotate()
5210 Opc == ISD::FSHL ? ISD::SETNE : ISD::SETEQ); in ExpandIntRes_FunnelShift()
H A DTargetLowering.cpp2131 case ISD::FSHL: in SimplifyDemandedBits()
2136 bool IsFSHL = (Op.getOpcode() == ISD::FSHL); in SimplifyDemandedBits()
4403 (N0.getOpcode() != ISD::FSHL && N0.getOpcode() != ISD::FSHR)) in foldSetCCWithFunnelShift()
7991 bool IsFSHL = Node->getOpcode() == ISD::FSHL; in expandFunnelShift()
7997 unsigned RevOpcode = IsFSHL ? ISD::FSHR : ISD::FSHL; in expandFunnelShift()
8145 Tmp2 = DAG.getNode(ISD::FSHL, dl, VT, ShOpHi, ShOpLo, ShAmt); in expandShiftParts()
H A DDAGCombiner.cpp1890 case ISD::FSHL: in visit()
5854 if ((HandOpcode == ISD::FSHL || HandOpcode == ISD::FSHR) && in hoistLogicOpWithSameOpcodeHands()
7802 if (N0.getOpcode() == ISD::FSHL && N1.getOpcode() == ISD::SHL && in visitORCommutative()
8352 if (PosOpcode == ISD::FSHL && isPowerOf2_32(EltBits)) { in MatchFunnelPosNeg()
8365 TLI.isOperationLegalOrCustom(ISD::FSHL, VT)) { in MatchFunnelPosNeg()
8366 return DAG.getNode(ISD::FSHL, DL, VT, N0, N1.getOperand(0), Pos); in MatchFunnelPosNeg()
8404 bool HasFSHL = hasOperation(ISD::FSHL, VT); in MatchRotate()
8572 Res = DAG.getNode(UseFSHL ? ISD::FSHL : ISD::FSHR, DL, VT, LHSShiftArg, in MatchRotate()
8620 LExtOp0, RExtOp0, HasFSHL, ISD::FSHL, ISD::FSHR, DL); in MatchRotate()
8626 RExtOp0, LExtOp0, HasFSHR, ISD::FSHR, ISD::FSHL, DL); in MatchRotate()
[all …]
H A DLegalizeVectorTypes.cpp193 case ISD::FSHL: in ScalarizeVectorResult()
1286 case ISD::FSHL: in SplitVectorResult()
4592 case ISD::FSHL: in WidenVectorResult()
H A DSelectionDAG.cpp3617 case ISD::FSHL: in computeKnownBits()
3625 Known = computeKnownBits(Op.getOperand(Opcode == ISD::FSHL ? 0 : 1), in computeKnownBits()
3634 if (Opcode == ISD::FSHL) { in computeKnownBits()
5271 case ISD::FSHL: in canCreateUndefOrPoison()
H A DLegalizeDAG.cpp1278 case ISD::FSHL: in LegalizeOp()
3880 case ISD::FSHL: in ExpandNode()
H A DSelectionDAGBuilder.cpp7172 auto FunnelOpcode = IsFSHL ? ISD::FSHL : ISD::FSHR; in visitIntrinsicCall()
/freebsd/contrib/llvm-project/llvm/include/llvm/IR/
H A DVPIntrinsics.def297 VP_PROPERTY_FUNCTIONAL_SDOPC(FSHL)
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/
H A DTargetLoweringBase.cpp719 ISD::FSHL, ISD::FSHR, in initActions()
/freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCISelLowering.cpp762 setOperationAction(ISD::FSHL, MVT::i64, Custom); in PPCTargetLowering()
765 setOperationAction(ISD::FSHL, MVT::i32, Custom); in PPCTargetLowering()
9193 bool IsFSHL = Op.getOpcode() == ISD::FSHL; in LowerFunnelShift()
11849 case ISD::FSHL: return LowerFunnelShift(Op, DAG); in LowerOperation()
11976 case ISD::FSHL: in ReplaceNodeResults()
/freebsd/contrib/llvm-project/llvm/include/llvm/Target/
H A DTargetSelectionDAG.td422 def fshl : SDNode<"ISD::FSHL" , SDTIntShiftDOp>;
/freebsd/contrib/llvm-project/llvm/lib/Target/NVPTX/
H A DNVPTXISelLowering.cpp531 ISD::FP_TO_SINT, ISD::FP_TO_UINT, ISD::FSHL, ISD::FSHR, in NVPTXTargetLowering()
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64ISelLowering.cpp619 setOperationAction(ISD::FSHL, MVT::i32, Custom); in AArch64TargetLowering()
620 setOperationAction(ISD::FSHL, MVT::i64, Custom); in AArch64TargetLowering()
6637 if (Op.getOpcode() == ISD::FSHL) { in LowerFunnelShift()
7081 case ISD::FSHL: in LowerOperation()