| /freebsd/contrib/llvm-project/llvm/lib/Target/SPIRV/ |
| H A D | SPIRVAsmPrinter.cpp | 512 MCRegister FReg = MAI->getFuncReg(&F); in outputExecutionMode() local
513 assert(FReg.isValid()); in outputExecutionMode()
523 Inst.addOperand(MCOperand::createReg(FReg)); in outputExecutionMode()
531 outputExecutionModeFromMDNode(FReg, Node, SPIRV::ExecutionMode::LocalSize, in outputExecutionMode()
535 FReg, Attr, SPIRV::ExecutionMode::LocalSize); in outputExecutionMode()
537 outputExecutionModeFromMDNode(FReg, Node, in outputExecutionMode()
540 outputExecutionModeFromMDNode(FReg, Node, in outputExecutionMode()
545 Inst.addOperand(MCOperand::createReg(FReg)); in outputExecutionMode()
556 Inst.addOperand(MCOperand::createReg(FReg)); in outputExecutionMode()
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| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/ |
| H A D | EarlyIfConversion.cpp | 116 Register TReg, FReg; member
530 PI.FReg = PI.PHI->getOperand(i).getReg(); in canConvertIf()
533 assert(PI.FReg.isVirtual() && "Bad PHI"); in canConvertIf()
537 PI.TReg, PI.FReg, PI.CondCycles, PI.TCycles, in canConvertIf()
574 Register FReg) { in hasSameValue() argument
575 if (TReg == FReg) in hasSameValue()
578 if (!TReg.isVirtual() || !FReg.isVirtual()) in hasSameValue()
582 const MachineInstr *FDef = MRI.getUniqueVRegDef(FReg); in hasSameValue()
610 int FIdx = FDef->findRegisterDefOperandIdx(FReg, /*TRI=*/nullptr); in hasSameValue()
630 if (hasSameValue(*MRI, TII, PI.TReg, PI.FReg)) { in replacePHIInstrs()
[all …]
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| /freebsd/contrib/llvm-project/llvm/lib/Target/CSKY/ |
| H A D | CSKYISelLowering.cpp | 909 unsigned FReg = StringSwitch<unsigned>(Constraint.lower()) in getRegForInlineAsmConstraint() local
943 if (FReg != CSKY::NoRegister) { in getRegForInlineAsmConstraint()
944 assert(CSKY::F0_32 <= FReg && FReg <= CSKY::F31_32 && "Unknown fp-reg"); in getRegForInlineAsmConstraint()
945 unsigned RegNo = FReg - CSKY::F0_32; in getRegForInlineAsmConstraint()
953 return std::make_pair(FReg, &CSKY::sFPR32RegClass); in getRegForInlineAsmConstraint()
955 return std::make_pair(FReg, &CSKY::FPR32RegClass); in getRegForInlineAsmConstraint()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
| H A D | HexagonLoadStoreWidening.cpp | 604 MachineOperand FReg = in createWideStores() local
611 assert(FReg.isReg() && SReg.isReg() && in createWideStores()
616 MachineInstr *CombI = BuildMI(*MF, DL, CombD, VReg).add(SReg).add(FReg); in createWideStores()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/SystemZ/ |
| H A D | SystemZInstrInfo.cpp | 655 Register FReg = MRI.createVirtualRegister(&SystemZ::GR32BitRegClass); in insertSelect() local
657 BuildMI(MBB, I, DL, get(TargetOpcode::COPY), FReg).addReg(FalseReg); in insertSelect()
659 FalseReg = FReg; in insertSelect()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/GISel/ |
| H A D | AArch64InstructionSelector.cpp | 3551 const Register FReg = Sel.getFalseReg(); in select() local
3562 if (!emitSelect(Sel.getReg(0), TReg, FReg, AArch64CC::NE, MIB)) in select()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/ |
| H A D | RISCVISelLowering.cpp | 23181 unsigned FReg = StringSwitch<unsigned>(Constraint.lower()) in getRegForInlineAsmConstraint() local
23215 if (FReg != RISCV::NoRegister) { in getRegForInlineAsmConstraint()
23216 assert(RISCV::F0_F <= FReg && FReg <= RISCV::F31_F && "Unknown fp-reg"); in getRegForInlineAsmConstraint()
23218 unsigned RegNo = FReg - RISCV::F0_F; in getRegForInlineAsmConstraint()
23223 return std::make_pair(FReg, &RISCV::FPR32RegClass); in getRegForInlineAsmConstraint()
23225 unsigned RegNo = FReg - RISCV::F0_F; in getRegForInlineAsmConstraint()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/ |
| H A D | PPCISelLowering.cpp | 6961 MCRegister FReg = State.AllocateReg(FPR); in CC_AIX() local
6962 if (FReg) in CC_AIX()
6963 State.addLoc(CCValAssign::getReg(ValNo, ValVT, FReg, LocVT, LocInfo)); in CC_AIX()
6968 assert(FReg && "An FPR should be available when a GPR is reserved."); in CC_AIX()
6985 FReg ? CCValAssign::getCustomMem(ValNo, ValVT, Offset, LocVT, in CC_AIX()
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