| /freebsd/contrib/llvm-project/llvm/include/llvm/IR/ |
| H A D | ConstrainedOps.def | 99 DAG_FUNCTION(roundeven, 1, 0, experimental_constrained_roundeven, FROUNDEVEN)
|
| H A D | VPIntrinsics.def | 452 VP_PROPERTY_FUNCTIONAL_SDOPC(FROUNDEVEN)
|
| /freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/ |
| H A D | ISDOpcodes.h | 992 FROUNDEVEN, enumerator
|
| H A D | BasicTTIImpl.h | 2064 ISD = ISD::FROUNDEVEN; in getTypeBasedIntrinsicInstrCost()
|
| /freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | AMDGPUISelLowering.cpp | 395 ISD::FROUNDEVEN, ISD::FTRUNC, ISD::FMINNUM, ISD::FMAXNUM}, in AMDGPUTargetLowering()
540 ISD::FCANONICALIZE, ISD::FROUNDEVEN}, in AMDGPUTargetLowering()
663 case ISD::FROUNDEVEN: in fnegFoldsIntoOpcode()
1386 case ISD::FROUNDEVEN: in LowerOperation()
2483 return DAG.getNode(ISD::FROUNDEVEN, SDLoc(Op), Op.getValueType(), in LowerFNEARBYINT()
2490 return DAG.getNode(ISD::FROUNDEVEN, SDLoc(Op), VT, Arg); in LowerFRINT()
3073 SDValue E = DAG.getNode(ISD::FROUNDEVEN, SL, VT, PH, Flags); in lowerFEXP()
4889 case ISD::FROUNDEVEN: in performFNegCombine()
|
| H A D | R600ISelLowering.cpp | 104 setOperationAction({ISD::FCEIL, ISD::FTRUNC, ISD::FROUNDEVEN, ISD::FFLOOR}, in R600TargetLowering()
|
| H A D | AMDGPUISelDAGToDAG.cpp | 163 case ISD::FROUNDEVEN: in fp16SrcZerosHighBits()
|
| H A D | SIISelLowering.cpp | 216 ISD::FROUND, ISD::FROUNDEVEN, ISD::FFLOOR, ISD::FCANONICALIZE, in SITargetLowering()
529 setOperationAction({ISD::FTRUNC, ISD::FCEIL, ISD::FROUNDEVEN}, MVT::f64, in SITargetLowering()
532 setOperationAction({ISD::FCEIL, ISD::FTRUNC, ISD::FROUNDEVEN, ISD::FFLOOR}, in SITargetLowering()
|
| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | SelectionDAGDumper.cpp | 241 case ISD::FROUNDEVEN: return "froundeven"; in getOperationName()
|
| H A D | LegalizeFloatTypes.cpp | 135 case ISD::FROUNDEVEN: R = SoftenFloatRes_FROUNDEVEN(N); break; in SoftenFloatResult()
1459 case ISD::FROUNDEVEN: ExpandFloatRes_FROUNDEVEN(N, Lo, Hi); break; in ExpandFloatResult()
2616 case ISD::FROUNDEVEN: in PromoteFloatResult()
3058 case ISD::FROUNDEVEN: in SoftPromoteHalfResult()
|
| H A D | LegalizeVectorOps.cpp | 425 case ISD::FROUNDEVEN: in LegalizeOp()
|
| H A D | LegalizeVectorTypes.cpp | 116 case ISD::FROUNDEVEN: in ScalarizeVectorResult()
1202 case ISD::FROUNDEVEN: in SplitVectorResult()
4546 case ISD::FROUNDEVEN: in WidenVectorResult()
|
| H A D | LegalizeDAG.cpp | 4644 case ISD::FROUNDEVEN: in ConvertNodeToLibcall()
5537 case ISD::FROUNDEVEN: in PromoteNode()
|
| H A D | SelectionDAGBuilder.cpp | 6832 case Intrinsic::roundeven: Opcode = ISD::FROUNDEVEN; break; in visitIntrinsicCall()
|
| H A D | SelectionDAG.cpp | 5422 case ISD::FROUNDEVEN: in isKnownNeverNaN()
|
| H A D | DAGCombiner.cpp | 18046 case ISD::FROUNDEVEN: in visitFTRUNC()
|
| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/ |
| H A D | TargetLoweringBase.cpp | 831 ISD::FROUNDEVEN, ISD::FTAN, ISD::FACOS, ISD::FASIN, in initActions()
|
| /freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/ |
| H A D | RISCVISelLowering.cpp | 448 ISD::FROUNDEVEN}; in RISCVTargetLowering()
462 ISD::FROUNDEVEN, ISD::SELECT}; in RISCVTargetLowering()
950 ISD::FFLOOR, ISD::FROUND, ISD::FROUNDEVEN, ISD::FRINT, in RISCVTargetLowering()
986 ISD::FROUNDEVEN, ISD::FRINT, ISD::FNEARBYINT, in RISCVTargetLowering()
1375 ISD::FROUNDEVEN, ISD::FRINT, ISD::FNEARBYINT}, in RISCVTargetLowering()
3008 case ISD::FROUNDEVEN: in matchRoundingOp()
3105 case ISD::FROUNDEVEN: in lowerVectorFTRUNC_FCEIL_FFLOOR_FROUND()
6770 case ISD::FROUNDEVEN: in LowerOperation()
|
| /freebsd/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86ISelDAGToDAG.cpp | 1214 case ISD::FROUNDEVEN: in PreprocessISelDAG()
1232 case ISD::FROUNDEVEN: Imm = 0x8; break; in PreprocessISelDAG()
|
| H A D | X86ISelLowering.cpp | 631 setOperationAction(ISD::FROUNDEVEN, VT, Action); in X86TargetLowering()
850 setOperationAction(ISD::FROUNDEVEN, MVT::f80, Expand); in X86TargetLowering()
991 setOperationAction(ISD::FROUNDEVEN, VT, Expand); in X86TargetLowering()
1341 setOperationAction(ISD::FROUNDEVEN, RoundedTy, Legal); in X86TargetLowering()
1442 setOperationAction(ISD::FROUNDEVEN, VT, Legal); in X86TargetLowering()
1888 setOperationAction(ISD::FROUNDEVEN, VT, Legal); in X86TargetLowering()
2194 setOperationAction(ISD::FROUNDEVEN, VT, Legal); in X86TargetLowering()
2226 setOperationAction(ISD::FROUNDEVEN, MVT::f16, Legal); in X86TargetLowering()
44968 case ISD::FROUNDEVEN: in scalarizeExtEltFP()
|
| /freebsd/contrib/llvm-project/llvm/lib/Target/WebAssembly/ |
| H A D | WebAssemblyISelLowering.cpp | 137 ISD::FRINT, ISD::FROUNDEVEN}) in WebAssemblyTargetLowering()
|
| /freebsd/contrib/llvm-project/llvm/lib/Target/NVPTX/ |
| H A D | NVPTXISelLowering.cpp | 454 case ISD::FROUNDEVEN: in NVPTXTargetLowering()
770 ISD::FROUNDEVEN, ISD::FTRUNC}) { in NVPTXTargetLowering()
|
| /freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64ISelLowering.cpp | 771 ISD::FROUNDEVEN, in AArch64TargetLowering()
817 setOperationPromotedToType(ISD::FROUNDEVEN, V4Narrow, MVT::v4f32); in AArch64TargetLowering()
843 setOperationAction(ISD::FROUNDEVEN, V8Narrow, Legal); in AArch64TargetLowering()
866 ISD::FROUNDEVEN, ISD::FMINNUM, ISD::FMAXNUM, in AArch64TargetLowering()
1194 ISD::FROUNDEVEN, ISD::FTRUNC, ISD::FMINNUM, in AArch64TargetLowering()
1350 ISD::FROUND, ISD::FROUNDEVEN, ISD::STRICT_FFLOOR, in AArch64TargetLowering()
1607 setOperationAction(ISD::FROUNDEVEN, VT, Custom); in AArch64TargetLowering()
2072 setOperationAction(ISD::FROUNDEVEN, VT, Default); in addTypeForFixedLengthSVE()
6833 case ISD::FROUNDEVEN: in LowerOperation()
|
| /freebsd/contrib/llvm-project/llvm/include/llvm/Target/ |
| H A D | TargetSelectionDAG.td | 545 def froundeven : SDNode<"ISD::FROUNDEVEN" , SDTFPUnaryOp>;
|