| /freebsd/contrib/llvm-project/llvm/include/llvm/IR/ |
| H A D | ConstrainedOps.def | 56 DAG_INSTRUCTION(FRem, 2, 1, experimental_constrained_frem, FREM)
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| H A D | VPIntrinsics.def | 333 HELPER_REGISTER_BINARY_FP_VP(frem, VP_FREM, FRem, FREM)
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| /freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/ |
| H A D | ISDOpcodes.h | 414 FREM, enumerator
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| H A D | SDPatternMatch.h | 913 return BinaryOpc_match<LHS, RHS>(ISD::FREM, L, R);
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| H A D | TargetLowering.h | 3028 case ISD::FREM: in isBinOp()
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| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | SelectionDAGBuilder.h | 555 void visitFRem(const User &I) { visitBinary(I, ISD::FREM); } in visitFRem()
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| H A D | SelectionDAGDumper.cpp | 313 case ISD::FREM: return "frem"; in getOperationName()
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| H A D | LegalizeFloatTypes.cpp | 137 case ISD::FREM: R = SoftenFloatRes_FREM(N); break; in SoftenFloatResult()
1637 case ISD::FREM: ExpandFloatRes_FREM(N, Lo, Hi); break; in ExpandFloatResult()
2876 case ISD::FREM: in PromoteFloatResult()
3360 case ISD::FREM: in SoftPromoteHalfResult()
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| H A D | LegalizeVectorOps.cpp | 369 case ISD::FREM: in LegalizeOp()
1259 case ISD::FREM: in Expand()
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| H A D | FastISel.cpp | 1773 return selectBinaryOp(I, ISD::FREM); in selectOperator()
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| H A D | SelectionDAG.cpp | 5627 case ISD::FREM: in canCreateUndefOrPoison()
5732 case ISD::FREM: in isKnownNeverNaN()
7241 case ISD::FREM: in foldConstantFPMath()
7283 case ISD::FREM: in foldConstantFPMath()
7585 case ISD::FREM: in getNode()
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| H A D | LegalizeVectorTypes.cpp | 179 case ISD::FREM: in ScalarizeVectorResult()
1328 case ISD::FREM: case ISD::VP_FREM: in SplitVectorResult()
4800 case ISD::FREM: in WidenVectorResult()
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| H A D | LegalizeDAG.cpp | 4944 case ISD::FREM: in ConvertNodeToLibcall()
5643 case ISD::FREM: in PromoteNode()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/CSKY/ |
| H A D | CSKYISelLowering.cpp | 121 ISD::FREM, ISD::FCOPYSIGN, ISD::FP16_TO_FP, ISD::FP_TO_FP16}; in CSKYTargetLowering()
128 setOperationAction(ISD::FREM, VT, Expand); in CSKYTargetLowering()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | AMDGPUTargetTransformInfo.cpp | 620 case ISD::FREM: in getArithmeticInstrCost()
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| H A D | AMDGPUISelLowering.cpp | 415 setOperationAction(ISD::FREM, {MVT::f16, MVT::f32, MVT::f64}, Custom); in AMDGPUTargetLowering()
546 ISD::FEXP10, ISD::FLOG2, ISD::FREM, in AMDGPUTargetLowering()
741 case ISD::FREM: in hasSourceMods()
1438 case ISD::FREM: return LowerFREM(Op, DAG); in LowerOperation()
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| H A D | AMDGPUISelDAGToDAG.cpp | 138 case ISD::FREM: in fp16SrcZerosHighBits()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Sparc/ |
| H A D | SparcISelLowering.cpp | 1797 setOperationAction(ISD::FREM , MVT::f128, Expand); in SparcTargetLowering()
1802 setOperationAction(ISD::FREM , MVT::f64, Expand); in SparcTargetLowering()
1808 setOperationAction(ISD::FREM , MVT::f32, Expand); in SparcTargetLowering()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Xtensa/ |
| H A D | XtensaISelLowering.cpp | 219 setOperationAction(ISD::FREM, VT, Expand); in XtensaTargetLowering()
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| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/ |
| H A D | TargetLoweringBase.cpp | 1872 case FRem: return ISD::FREM; in InstructionOpcodeToISD()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
| H A D | HexagonISelLowering.cpp | 1677 {ISD::FDIV, ISD::FREM, ISD::FSQRT, ISD::FSIN, ISD::FCOS, ISD::FSINCOS, in HexagonTargetLowering()
1723 ISD::FREM, ISD::FNEG, ISD::FABS, ISD::FSQRT, ISD::FSIN, in HexagonTargetLowering()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/NVPTX/ |
| H A D | NVPTXISelLowering.cpp | 953 {ISD::FDIV, ISD::FREM, ISD::FSQRT, ISD::FSIN, ISD::FCOS}) { in NVPTXTargetLowering()
961 setOperationAction(ISD::FREM, {MVT::f32, MVT::f64}, Custom); in NVPTXTargetLowering()
2971 case ISD::FREM: in LowerOperation()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Mips/ |
| H A D | MipsISelLowering.cpp | 470 setOperationAction(ISD::FREM, MVT::f32, Expand); in MipsTargetLowering()
471 setOperationAction(ISD::FREM, MVT::f64, Expand); in MipsTargetLowering()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/VE/ |
| H A D | VEISelLowering.cpp | 232 setOperationAction(ISD::FREM, VT, Expand); in initSPUActions()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/ARM/ |
| H A D | ARMISelLowering.cpp | 220 setOperationAction(ISD::FREM, VT, Expand); in addTypeForNEON()
385 setOperationAction(ISD::FREM, VT, Expand); in addMVEVectorTypes()
858 setOperationAction(ISD::FREM, MVT::v2f64, Expand); in ARMTargetLowering()
1056 setOperationAction(ISD::FREM, MVT::f64, Expand); in ARMTargetLowering()
1421 setOperationAction(ISD::FREM, MVT::f64, Expand); in ARMTargetLowering()
1422 setOperationAction(ISD::FREM, MVT::f32, Expand); in ARMTargetLowering()
1499 setOperationAction(ISD::FREM, MVT::f16, Promote); in ARMTargetLowering()
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