| /freebsd/contrib/llvm-project/llvm/include/llvm/IR/ |
| H A D | ConstrainedOps.def | 56 DAG_INSTRUCTION(FRem, 2, 1, experimental_constrained_frem, FREM)
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| H A D | VPIntrinsics.def | 360 HELPER_REGISTER_BINARY_FP_VP(frem, VP_FREM, FRem, FREM)
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| /freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/ |
| H A D | ISDOpcodes.h | 401 FREM, enumerator
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| H A D | SDPatternMatch.h | 646 return BinaryOpc_match<LHS, RHS, false>(ISD::FREM, L, R);
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| H A D | TargetLowering.h | 2942 case ISD::FREM: in isBinOp()
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| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | SelectionDAGBuilder.h | 556 void visitFRem(const User &I) { visitBinary(I, ISD::FREM); } in visitFRem()
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| H A D | SelectionDAGDumper.cpp | 296 case ISD::FREM: return "frem"; in getOperationName()
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| H A D | LegalizeVectorOps.cpp | 358 case ISD::FREM: in LegalizeOp()
1120 case ISD::FREM: in Expand()
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| H A D | LegalizeFloatTypes.cpp | 129 case ISD::FREM: R = SoftenFloatRes_FREM(N); break; in SoftenFloatResult()
1480 case ISD::FREM: ExpandFloatRes_FREM(N, Lo, Hi); break; in ExpandFloatResult()
2636 case ISD::FREM: in PromoteFloatResult()
3076 case ISD::FREM: in SoftPromoteHalfResult()
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| H A D | FastISel.cpp | 1831 return selectBinaryOp(I, ISD::FREM); in selectOperator()
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| H A D | LegalizeVectorTypes.cpp | 167 case ISD::FREM: in ScalarizeVectorResult()
1269 case ISD::FREM: case ISD::VP_FREM: in SplitVectorResult()
4431 case ISD::FREM: in WidenVectorResult()
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| H A D | SelectionDAG.cpp | 5397 case ISD::FREM: in isKnownNeverNaN()
6787 case ISD::FREM: in foldConstantFPMath()
6825 case ISD::FREM: in foldConstantFPMath()
7038 case ISD::FREM: in getNode()
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| H A D | LegalizeDAG.cpp | 4741 case ISD::FREM: in ConvertNodeToLibcall()
5433 case ISD::FREM: in PromoteNode()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/CSKY/ |
| H A D | CSKYISelLowering.cpp | 121 ISD::FREM, ISD::FCOPYSIGN, ISD::FP16_TO_FP, ISD::FP_TO_FP16}; in CSKYTargetLowering()
128 setOperationAction(ISD::FREM, VT, Expand); in CSKYTargetLowering()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | AMDGPUTargetTransformInfo.cpp | 618 case ISD::FREM: in getArithmeticInstrCost()
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| H A D | AMDGPUISelLowering.cpp | 409 setOperationAction(ISD::FREM, {MVT::f16, MVT::f32, MVT::f64}, Custom); in AMDGPUTargetLowering()
533 ISD::FEXP10, ISD::FLOG2, ISD::FREM, in AMDGPUTargetLowering()
726 case ISD::FREM: in hasSourceMods()
1381 case ISD::FREM: return LowerFREM(Op, DAG); in LowerOperation()
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| H A D | AMDGPUISelDAGToDAG.cpp | 142 case ISD::FREM: in fp16SrcZerosHighBits()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Sparc/ |
| H A D | SparcISelLowering.cpp | 1803 setOperationAction(ISD::FREM , MVT::f128, Expand); in SparcTargetLowering()
1808 setOperationAction(ISD::FREM , MVT::f64, Expand); in SparcTargetLowering()
1813 setOperationAction(ISD::FREM , MVT::f32, Expand); in SparcTargetLowering()
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| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/ |
| H A D | TargetLoweringBase.cpp | 1785 case FRem: return ISD::FREM; in InstructionOpcodeToISD()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
| H A D | HexagonISelLowering.cpp | 1609 {ISD::FDIV, ISD::FREM, ISD::FSQRT, ISD::FSIN, ISD::FCOS, ISD::FSINCOS, in HexagonTargetLowering()
1654 ISD::FREM, ISD::FNEG, ISD::FABS, ISD::FSQRT, ISD::FSIN, in HexagonTargetLowering()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Mips/ |
| H A D | MipsISelLowering.cpp | 462 setOperationAction(ISD::FREM, MVT::f32, Expand); in MipsTargetLowering()
463 setOperationAction(ISD::FREM, MVT::f64, Expand); in MipsTargetLowering()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/WebAssembly/ |
| H A D | WebAssemblyISelLowering.cpp | 132 {ISD::FSIN, ISD::FCOS, ISD::FSINCOS, ISD::FPOW, ISD::FREM, ISD::FMA}) in WebAssemblyTargetLowering()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/LoongArch/ |
| H A D | LoongArchISelLowering.cpp | 182 setOperationAction(ISD::FREM, MVT::f32, Expand); in LoongArchTargetLowering()
219 setOperationAction(ISD::FREM, MVT::f64, Expand); in LoongArchTargetLowering()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/VE/ |
| H A D | VEISelLowering.cpp | 232 setOperationAction(ISD::FREM, VT, Expand); in initSPUActions()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/ARM/ |
| H A D | ARMISelLowering.cpp | 215 setOperationAction(ISD::FREM, VT, Expand); in addTypeForNEON()
375 setOperationAction(ISD::FREM, VT, Expand); in addMVEVectorTypes()
868 setOperationAction(ISD::FREM, MVT::v2f64, Expand); in ARMTargetLowering()
1058 setOperationAction(ISD::FREM, MVT::f64, Expand); in ARMTargetLowering()
1464 setOperationAction(ISD::FREM, MVT::f64, Expand); in ARMTargetLowering()
1465 setOperationAction(ISD::FREM, MVT::f32, Expand); in ARMTargetLowering()
1540 setOperationAction(ISD::FREM, MVT::f16, Promote); in ARMTargetLowering()
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