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Searched refs:FP_TO_UINT_SAT (Results 1 – 19 of 19) sorted by relevance

/freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DISDOpcodes.h884 FP_TO_UINT_SAT, enumerator
/freebsd/contrib/llvm-project/llvm/lib/Target/WebAssembly/
H A DWebAssemblyISelLowering.cpp167 for (auto Op : {ISD::FP_TO_SINT_SAT, ISD::FP_TO_UINT_SAT}) in WebAssemblyTargetLowering()
192 setTargetDAGCombine({ISD::FP_TO_SINT_SAT, ISD::FP_TO_UINT_SAT, in WebAssemblyTargetLowering()
278 for (auto Op : {ISD::FP_TO_SINT_SAT, ISD::FP_TO_UINT_SAT}) in WebAssemblyTargetLowering()
1498 case ISD::FP_TO_UINT_SAT: in LowerOperation()
2582 case ISD::FP_TO_UINT_SAT: in performVectorTruncZeroCombine()
2621 case ISD::FP_TO_UINT_SAT: in performVectorTruncZeroCombine()
2666 case ISD::FP_TO_UINT_SAT: in performVectorTruncZeroCombine()
2898 case ISD::FP_TO_UINT_SAT: in PerformDAGCombine()
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DSelectionDAGDumper.cpp397 case ISD::FP_TO_UINT_SAT: return "fp_to_uint_sat"; in getOperationName()
H A DLegalizeVectorOps.cpp456 case ISD::FP_TO_UINT_SAT: in LegalizeOp()
1057 case ISD::FP_TO_UINT_SAT: in Expand()
H A DLegalizeFloatTypes.cpp1011 case ISD::FP_TO_UINT_SAT: in SoftenFloatOperand()
2415 case ISD::FP_TO_UINT_SAT: in PromoteFloatOperand()
3402 case ISD::FP_TO_UINT_SAT: in SoftPromoteHalfOperand()
H A DLegalizeVectorTypes.cpp204 case ISD::FP_TO_UINT_SAT: in ScalarizeVectorResult()
1303 case ISD::FP_TO_UINT_SAT: in SplitVectorResult()
3189 case ISD::FP_TO_UINT_SAT: in SplitVectorOperand()
4518 case ISD::FP_TO_UINT_SAT: in WidenVectorResult()
6426 case ISD::FP_TO_UINT_SAT: in WidenVectorOperand()
H A DLegalizeDAG.cpp1159 case ISD::FP_TO_UINT_SAT: in LegalizeOp()
3440 case ISD::FP_TO_UINT_SAT: in ExpandNode()
5186 case ISD::FP_TO_UINT_SAT: in PromoteNode()
H A DLegalizeIntegerTypes.cpp169 case ISD::FP_TO_UINT_SAT: in PromoteIntegerResult()
2802 case ISD::FP_TO_UINT_SAT: ExpandIntRes_FP_TO_XINT_SAT(N, Lo, Hi); break; in ExpandIntegerResult()
H A DSelectionDAG.cpp4149 case ISD::FP_TO_UINT_SAT: { in computeKnownBits()
7159 case ISD::FP_TO_UINT_SAT: { in getNode()
H A DDAGCombiner.cpp5630 unsigned NewOpc = Unsigned ? ISD::FP_TO_UINT_SAT : ISD::FP_TO_SINT_SAT; in PerformMinMaxFpToSatCombine()
5665 if (!DAG.getTargetLoweringInfo().shouldConvertFpToSat(ISD::FP_TO_UINT_SAT, in PerformUMinFpToSatCombine()
5670 DAG.getNode(ISD::FP_TO_UINT_SAT, SDLoc(N0), NewVT, N0.getOperand(0), in PerformUMinFpToSatCombine()
H A DSelectionDAGBuilder.cpp6993 setValue(&I, DAG.getNode(ISD::FP_TO_UINT_SAT, sdl, VT, in visitIntrinsicCall()
/freebsd/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86ISelLowering.h1189 return Op != ISD::FP_TO_UINT_SAT && isOperationLegalOrCustom(Op, VT); in shouldConvertFpToSat()
H A DX86ISelLowering.cpp331 setOperationAction(ISD::FP_TO_UINT_SAT, VT, Custom); in X86TargetLowering()
335 setOperationAction(ISD::FP_TO_UINT_SAT, MVT::i64, Custom); in X86TargetLowering()
32401 case ISD::FP_TO_UINT_SAT: return LowerFP_TO_INT_SAT(Op, DAG); in LowerOperation()
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/
H A DTargetLoweringBase.cpp727 ISD::FP_TO_SINT_SAT, ISD::FP_TO_UINT_SAT, in initActions()
/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMISelDAGToDAG.cpp3282 N->getOpcode() == ISD::FP_TO_UINT_SAT; in tryFP_TO_INT()
3786 case ISD::FP_TO_UINT_SAT: in Select()
H A DARMISelLowering.cpp322 setOperationAction(ISD::FP_TO_UINT_SAT, VT, Custom); in addMVEVectorTypes()
782 setOperationAction(ISD::FP_TO_UINT_SAT, MVT::i32, Custom); in ARMTargetLowering()
784 setOperationAction(ISD::FP_TO_UINT_SAT, MVT::i64, Custom); in ARMTargetLowering()
10591 case ISD::FP_TO_UINT_SAT: return LowerFP_TO_INT_SAT(Op, DAG, Subtarget); in LowerOperation()
10784 case ISD::FP_TO_UINT_SAT: in ReplaceNodeResults()
/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVISelLowering.cpp604 setOperationAction({ISD::FP_TO_UINT_SAT, ISD::FP_TO_SINT_SAT}, XLenVT, in RISCVTargetLowering()
787 setOperationAction({ISD::FP_TO_SINT_SAT, ISD::FP_TO_UINT_SAT}, VT, in RISCVTargetLowering()
847 setOperationAction({ISD::FP_TO_SINT_SAT, ISD::FP_TO_UINT_SAT}, VT, in RISCVTargetLowering()
1195 setOperationAction({ISD::FP_TO_SINT_SAT, ISD::FP_TO_UINT_SAT}, VT, in RISCVTargetLowering()
1492 ISD::FP_TO_SINT_SAT, ISD::FP_TO_UINT_SAT}); in RISCVTargetLowering()
6704 case ISD::FP_TO_UINT_SAT: in LowerOperation()
15437 // fcvt.wu.* sign extends bit 31 on RV64. FP_TO_UINT_SAT expects to zero in performFP_TO_INT_SATCombine()
17036 case ISD::FP_TO_UINT_SAT: in PerformDAGCombine()
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64ISelLowering.cpp601 setOperationAction(ISD::FP_TO_UINT_SAT, MVT::i32, Custom); in AArch64TargetLowering()
602 setOperationAction(ISD::FP_TO_UINT_SAT, MVT::i64, Custom); in AArch64TargetLowering()
1093 ISD::FP_TO_UINT_SAT, ISD::FADD}); in AArch64TargetLowering()
1206 ISD::FP_ROUND, ISD::FP_TO_SINT_SAT, ISD::FP_TO_UINT_SAT, ISD::MUL, in AArch64TargetLowering()
1896 ISD::FP_TO_UINT_SAT, ISD::STRICT_FP_TO_SINT, ISD::STRICT_FP_TO_UINT}) in addTypeForNEON()
6910 case ISD::FP_TO_UINT_SAT: in LowerOperation()
18628 N->getOpcode() == ISD::FP_TO_UINT_SAT) { in performFpToIntCombine()
25311 case ISD::FP_TO_UINT_SAT: in PerformDAGCombine()
/freebsd/contrib/llvm-project/llvm/include/llvm/Target/
H A DTargetSelectionDAG.td563 def fp_to_uint_sat : SDNode<"ISD::FP_TO_UINT_SAT" , SDTFPToIntSatOp>;