| /freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/ |
| H A D | ISDOpcodes.h | 928 FP_TO_UINT_SAT, enumerator
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| H A D | BasicTTIImpl.h | 2555 : ISD::FP_TO_UINT_SAT; in getTypeBasedIntrinsicInstrCost()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/WebAssembly/ |
| H A D | WebAssemblyISelLowering.cpp | 178 for (auto Op : {ISD::FP_TO_SINT_SAT, ISD::FP_TO_UINT_SAT}) in WebAssemblyTargetLowering() 210 setTargetDAGCombine({ISD::FP_TO_SINT_SAT, ISD::FP_TO_UINT_SAT, in WebAssemblyTargetLowering() 302 for (auto Op : {ISD::FP_TO_SINT_SAT, ISD::FP_TO_UINT_SAT}) { in WebAssemblyTargetLowering() 1676 case ISD::FP_TO_UINT_SAT: in LowerOperation() 2992 case ISD::FP_TO_UINT_SAT: in performVectorTruncZeroCombine() 3031 case ISD::FP_TO_UINT_SAT: in performVectorTruncZeroCombine() 3076 case ISD::FP_TO_UINT_SAT: in performVectorTruncZeroCombine() 3521 case ISD::FP_TO_UINT_SAT: in PerformDAGCombine()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86ISelLowering.h | 733 FP_TO_UINT_SAT, enumerator 1275 return Op != ISD::FP_TO_UINT_SAT && isOperationLegalOrCustom(Op, VT); in shouldConvertFpToSat()
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| H A D | X86InstrFragmentsSIMD.td | 398 def X86fp2uisat : SDNode<"X86ISD::FP_TO_UINT_SAT", SDTFPToxIntSatOp>;
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| H A D | X86ISelLowering.cpp | 316 setOperationAction(ISD::FP_TO_UINT_SAT, VT, Custom); in X86TargetLowering() 322 setOperationAction(ISD::FP_TO_UINT_SAT, MVT::i64, Custom); in X86TargetLowering() 327 setOperationAction(ISD::FP_TO_UINT_SAT, MVT::v2i32, Custom); in X86TargetLowering() 331 setOperationAction(ISD::FP_TO_UINT_SAT, VT, Legal); in X86TargetLowering() 335 setOperationAction(ISD::FP_TO_UINT_SAT, MVT::v8i64, Legal); in X86TargetLowering() 339 setOperationAction(ISD::FP_TO_UINT_SAT, MVT::i64, Legal); in X86TargetLowering() 2686 ISD::FP_TO_UINT_SAT, in X86TargetLowering() 33626 case ISD::FP_TO_UINT_SAT: return LowerFP_TO_INT_SAT(Op, DAG); in LowerOperation() 34129 case ISD::FP_TO_UINT_SAT: { in ReplaceNodeResults() 34143 Res = DAG.getNode(X86ISD::FP_TO_UINT_SAT, dl, MVT::v4i32, Op); in ReplaceNodeResults() [all …]
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| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | SelectionDAGDumper.cpp | 417 case ISD::FP_TO_UINT_SAT: return "fp_to_uint_sat"; in getOperationName()
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| H A D | LegalizeVectorOps.cpp | 473 case ISD::FP_TO_UINT_SAT: in LegalizeOp() 1188 case ISD::FP_TO_UINT_SAT: in Expand()
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| H A D | LegalizeVectorTypes.cpp | 216 case ISD::FP_TO_UINT_SAT: in ScalarizeVectorResult() 768 case ISD::FP_TO_UINT_SAT: in ScalarizeVectorOperand() 1362 case ISD::FP_TO_UINT_SAT: in SplitVectorResult() 3464 case ISD::FP_TO_UINT_SAT: in SplitVectorOperand() 4887 case ISD::FP_TO_UINT_SAT: in WidenVectorResult() 6873 case ISD::FP_TO_UINT_SAT: in WidenVectorOperand()
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| H A D | LegalizeFloatTypes.cpp | 1153 case ISD::FP_TO_UINT_SAT: in SoftenFloatOperand() 2631 case ISD::FP_TO_UINT_SAT: in PromoteFloatOperand() 3745 case ISD::FP_TO_UINT_SAT: in SoftPromoteHalfOperand()
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| H A D | LegalizeDAG.cpp | 1189 case ISD::FP_TO_UINT_SAT: in LegalizeOp() 3497 case ISD::FP_TO_UINT_SAT: in ExpandNode() 5397 case ISD::FP_TO_UINT_SAT: in PromoteNode()
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| H A D | LegalizeIntegerTypes.cpp | 187 case ISD::FP_TO_UINT_SAT: in PromoteIntegerResult() 2985 case ISD::FP_TO_UINT_SAT: ExpandIntRes_FP_TO_XINT_SAT(N, Lo, Hi); break; in ExpandIntegerResult()
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| H A D | DAGCombiner.cpp | 6005 unsigned NewOpc = Unsigned ? ISD::FP_TO_UINT_SAT : ISD::FP_TO_SINT_SAT; in PerformMinMaxFpToSatCombine() 6040 if (!DAG.getTargetLoweringInfo().shouldConvertFpToSat(ISD::FP_TO_UINT_SAT, in PerformUMinFpToSatCombine() 6045 DAG.getNode(ISD::FP_TO_UINT_SAT, SDLoc(N0), NewVT, N0.getOperand(0), in PerformUMinFpToSatCombine() 15837 ISD::FP_TO_UINT_SAT, FPVal.getValueType(), VT)) in visitTRUNCATE_USAT_U() 15838 return DAG.getNode(ISD::FP_TO_UINT_SAT, SDLoc(N0), VT, FPVal, in visitTRUNCATE_USAT_U()
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| H A D | SelectionDAG.cpp | 4386 case ISD::FP_TO_UINT_SAT: { in computeKnownBits() 7681 case ISD::FP_TO_UINT_SAT: { in getNode()
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| H A D | SelectionDAGBuilder.cpp | 7044 setValue(&I, DAG.getNode(ISD::FP_TO_UINT_SAT, sdl, VT, in visitIntrinsicCall()
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| /freebsd/contrib/llvm-project/llvm/include/llvm/Target/ |
| H A D | TargetSelectionDAG.td | 596 def fp_to_uint_sat : SDNode<"ISD::FP_TO_UINT_SAT" , SDTFPToIntSatOp>; 598 def fp_to_uint_sat_gi : SDNode<"ISD::FP_TO_UINT_SAT" , SDTFPToIntOp>;
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| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/ |
| H A D | TargetLoweringBase.cpp | 808 ISD::FP_TO_SINT_SAT, ISD::FP_TO_UINT_SAT, in initActions()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/ARM/ |
| H A D | ARMISelDAGToDAG.cpp | 3273 N->getOpcode() == ISD::FP_TO_UINT_SAT; in tryFP_TO_INT() 3781 case ISD::FP_TO_UINT_SAT: in Select()
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| H A D | ARMISelLowering.cpp | 327 setOperationAction(ISD::FP_TO_UINT_SAT, VT, Custom); in addMVEVectorTypes() 767 setOperationAction(ISD::FP_TO_UINT_SAT, MVT::i32, Custom); in ARMTargetLowering() 769 setOperationAction(ISD::FP_TO_UINT_SAT, MVT::i64, Custom); in ARMTargetLowering() 10652 case ISD::FP_TO_UINT_SAT: return LowerFP_TO_INT_SAT(Op, DAG, Subtarget); in LowerOperation() 10847 case ISD::FP_TO_UINT_SAT: in ReplaceNodeResults()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/ |
| H A D | RISCVISelLowering.cpp | 644 setOperationAction({ISD::FP_TO_UINT_SAT, ISD::FP_TO_SINT_SAT}, XLenVT, in RISCVTargetLowering() 834 setOperationAction({ISD::FP_TO_SINT_SAT, ISD::FP_TO_UINT_SAT}, VT, in RISCVTargetLowering() 895 setOperationAction({ISD::FP_TO_SINT_SAT, ISD::FP_TO_UINT_SAT}, VT, in RISCVTargetLowering() 1309 setOperationAction({ISD::FP_TO_SINT_SAT, ISD::FP_TO_UINT_SAT}, VT, in RISCVTargetLowering() 1646 ISD::FP_TO_SINT_SAT, ISD::FP_TO_UINT_SAT}); in RISCVTargetLowering() 7645 case ISD::FP_TO_UINT_SAT: in LowerOperation() 20080 case ISD::FP_TO_UINT_SAT: in PerformDAGCombine()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64ISelLowering.cpp | 615 setOperationAction(ISD::FP_TO_UINT_SAT, MVT::i32, Custom); in AArch64TargetLowering() 616 setOperationAction(ISD::FP_TO_UINT_SAT, MVT::i64, Custom); in AArch64TargetLowering() 1135 ISD::FP_TO_UINT_SAT, ISD::FADD}); in AArch64TargetLowering() 1258 ISD::FP_ROUND, ISD::FP_TO_SINT_SAT, ISD::FP_TO_UINT_SAT, ISD::MUL, in AArch64TargetLowering() 2065 ISD::FP_TO_UINT_SAT, ISD::STRICT_FP_TO_SINT, ISD::STRICT_FP_TO_UINT}) in addTypeForNEON() 7378 case ISD::FP_TO_UINT_SAT: in LowerOperation() 19271 N->getOpcode() == ISD::FP_TO_UINT_SAT) { in performFpToIntCombine() 26780 case ISD::FP_TO_UINT_SAT: in PerformDAGCombine()
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