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Searched refs:FP_TO_SINT_SAT (Results 1 – 19 of 19) sorted by relevance

/freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DISDOpcodes.h883 FP_TO_SINT_SAT, enumerator
/freebsd/contrib/llvm-project/llvm/lib/Target/WebAssembly/
H A DWebAssemblyISelLowering.cpp167 for (auto Op : {ISD::FP_TO_SINT_SAT, ISD::FP_TO_UINT_SAT}) in WebAssemblyTargetLowering()
192 setTargetDAGCombine({ISD::FP_TO_SINT_SAT, ISD::FP_TO_UINT_SAT, in WebAssemblyTargetLowering()
278 for (auto Op : {ISD::FP_TO_SINT_SAT, ISD::FP_TO_UINT_SAT}) in WebAssemblyTargetLowering()
1497 case ISD::FP_TO_SINT_SAT: in LowerOperation()
2580 case ISD::FP_TO_SINT_SAT: in performVectorTruncZeroCombine()
2620 case ISD::FP_TO_SINT_SAT: in performVectorTruncZeroCombine()
2665 case ISD::FP_TO_SINT_SAT: in performVectorTruncZeroCombine()
2897 case ISD::FP_TO_SINT_SAT: in PerformDAGCombine()
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DSelectionDAGDumper.cpp396 case ISD::FP_TO_SINT_SAT: return "fp_to_sint_sat"; in getOperationName()
H A DLegalizeVectorOps.cpp455 case ISD::FP_TO_SINT_SAT: in LegalizeOp()
1056 case ISD::FP_TO_SINT_SAT: in Expand()
H A DLegalizeFloatTypes.cpp1010 case ISD::FP_TO_SINT_SAT: in SoftenFloatOperand()
2414 case ISD::FP_TO_SINT_SAT: in PromoteFloatOperand()
3401 case ISD::FP_TO_SINT_SAT: in SoftPromoteHalfOperand()
H A DLegalizeVectorTypes.cpp205 case ISD::FP_TO_SINT_SAT: in ScalarizeVectorResult()
1304 case ISD::FP_TO_SINT_SAT: in SplitVectorResult()
3188 case ISD::FP_TO_SINT_SAT: in SplitVectorOperand()
4517 case ISD::FP_TO_SINT_SAT: in WidenVectorResult()
6425 case ISD::FP_TO_SINT_SAT: in WidenVectorOperand()
H A DLegalizeDAG.cpp1158 case ISD::FP_TO_SINT_SAT: in LegalizeOp()
3439 case ISD::FP_TO_SINT_SAT: in ExpandNode()
5187 case ISD::FP_TO_SINT_SAT: in PromoteNode()
H A DLegalizeIntegerTypes.cpp168 case ISD::FP_TO_SINT_SAT: in PromoteIntegerResult()
2801 case ISD::FP_TO_SINT_SAT: in ExpandIntegerResult()
H A DSelectionDAG.cpp4589 case ISD::FP_TO_SINT_SAT: in ComputeNumSignBits()
7158 case ISD::FP_TO_SINT_SAT: in getNode()
H A DSelectionDAGBuilder.cpp6986 setValue(&I, DAG.getNode(ISD::FP_TO_SINT_SAT, sdl, VT, in visitIntrinsicCall()
H A DTargetLowering.cpp11130 bool IsSigned = Node->getOpcode() == ISD::FP_TO_SINT_SAT; in expandFP_TO_INT_SAT()
H A DDAGCombiner.cpp5630 unsigned NewOpc = Unsigned ? ISD::FP_TO_UINT_SAT : ISD::FP_TO_SINT_SAT; in PerformMinMaxFpToSatCombine()
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/
H A DTargetLoweringBase.cpp727 ISD::FP_TO_SINT_SAT, ISD::FP_TO_UINT_SAT, in initActions()
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64ISelLowering.cpp603 setOperationAction(ISD::FP_TO_SINT_SAT, MVT::i32, Custom); in AArch64TargetLowering()
604 setOperationAction(ISD::FP_TO_SINT_SAT, MVT::i64, Custom); in AArch64TargetLowering()
1092 setTargetDAGCombine({ISD::FP_TO_SINT, ISD::FP_TO_UINT, ISD::FP_TO_SINT_SAT, in AArch64TargetLowering()
1206 ISD::FP_ROUND, ISD::FP_TO_SINT_SAT, ISD::FP_TO_UINT_SAT, ISD::MUL, in AArch64TargetLowering()
1895 {ISD::FP_TO_SINT, ISD::FP_TO_UINT, ISD::FP_TO_SINT_SAT, in addTypeForNEON()
4549 if (Op.getOpcode() == ISD::FP_TO_SINT_SAT) { in LowerVectorFP_TO_INT_SAT()
4606 if (Op.getOpcode() == ISD::FP_TO_SINT_SAT) { in LowerFP_TO_INT_SAT()
4638 return DAG.getNode(ISD::FP_TO_SINT_SAT, DL, VT, FOp, in LowerVectorXRINT()
6909 case ISD::FP_TO_SINT_SAT: in LowerOperation()
18627 if (N->getOpcode() == ISD::FP_TO_SINT_SAT || in performFpToIntCombine()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVISelLowering.cpp604 setOperationAction({ISD::FP_TO_UINT_SAT, ISD::FP_TO_SINT_SAT}, XLenVT, in RISCVTargetLowering()
787 setOperationAction({ISD::FP_TO_SINT_SAT, ISD::FP_TO_UINT_SAT}, VT, in RISCVTargetLowering()
847 setOperationAction({ISD::FP_TO_SINT_SAT, ISD::FP_TO_UINT_SAT}, VT, in RISCVTargetLowering()
1195 setOperationAction({ISD::FP_TO_SINT_SAT, ISD::FP_TO_UINT_SAT}, VT, in RISCVTargetLowering()
1492 ISD::FP_TO_SINT_SAT, ISD::FP_TO_UINT_SAT}); in RISCVTargetLowering()
2915 bool IsSigned = Op.getOpcode() == ISD::FP_TO_SINT_SAT; in lowerFP_TO_INT_SAT()
6703 case ISD::FP_TO_SINT_SAT: in LowerOperation()
15420 bool IsSigned = N->getOpcode() == ISD::FP_TO_SINT_SAT; in performFP_TO_INT_SATCombine()
17035 case ISD::FP_TO_SINT_SAT: in PerformDAGCombine()
/freebsd/contrib/llvm-project/llvm/include/llvm/Target/
H A DTargetSelectionDAG.td562 def fp_to_sint_sat : SDNode<"ISD::FP_TO_SINT_SAT" , SDTFPToIntSatOp>;
/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMISelLowering.cpp321 setOperationAction(ISD::FP_TO_SINT_SAT, VT, Custom); in addMVEVectorTypes()
781 setOperationAction(ISD::FP_TO_SINT_SAT, MVT::i32, Custom); in ARMTargetLowering()
783 setOperationAction(ISD::FP_TO_SINT_SAT, MVT::i64, Custom); in ARMTargetLowering()
5961 bool IsSigned = Op.getOpcode() == ISD::FP_TO_SINT_SAT; in LowerFP_TO_INT_SAT()
10590 case ISD::FP_TO_SINT_SAT: in LowerOperation()
10783 case ISD::FP_TO_SINT_SAT: in ReplaceNodeResults()
H A DARMISelDAGToDAG.cpp3787 case ISD::FP_TO_SINT_SAT: in Select()
/freebsd/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86ISelLowering.cpp332 setOperationAction(ISD::FP_TO_SINT_SAT, VT, Custom); in X86TargetLowering()
336 setOperationAction(ISD::FP_TO_SINT_SAT, MVT::i64, Custom); in X86TargetLowering()
21285 bool IsSigned = Node->getOpcode() == ISD::FP_TO_SINT_SAT; in LowerFP_TO_INT_SAT()
32400 case ISD::FP_TO_SINT_SAT: in LowerOperation()