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Searched refs:FP_TO_SINT_SAT (Results 1 – 22 of 22) sorted by relevance

/freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DISDOpcodes.h927 FP_TO_SINT_SAT, enumerator
H A DBasicTTIImpl.h2554 ISD = IID == Intrinsic::fptosi_sat ? ISD::FP_TO_SINT_SAT in getTypeBasedIntrinsicInstrCost()
/freebsd/contrib/llvm-project/llvm/lib/Target/WebAssembly/
H A DWebAssemblyISelLowering.cpp178 for (auto Op : {ISD::FP_TO_SINT_SAT, ISD::FP_TO_UINT_SAT}) in WebAssemblyTargetLowering()
210 setTargetDAGCombine({ISD::FP_TO_SINT_SAT, ISD::FP_TO_UINT_SAT, in WebAssemblyTargetLowering()
302 for (auto Op : {ISD::FP_TO_SINT_SAT, ISD::FP_TO_UINT_SAT}) { in WebAssemblyTargetLowering()
1675 case ISD::FP_TO_SINT_SAT: in LowerOperation()
2990 case ISD::FP_TO_SINT_SAT: in performVectorTruncZeroCombine()
3030 case ISD::FP_TO_SINT_SAT: in performVectorTruncZeroCombine()
3075 case ISD::FP_TO_SINT_SAT: in performVectorTruncZeroCombine()
3520 case ISD::FP_TO_SINT_SAT: in PerformDAGCombine()
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DSelectionDAGDumper.cpp416 case ISD::FP_TO_SINT_SAT: return "fp_to_sint_sat"; in getOperationName()
H A DLegalizeVectorOps.cpp472 case ISD::FP_TO_SINT_SAT: in LegalizeOp()
1187 case ISD::FP_TO_SINT_SAT: in Expand()
H A DLegalizeVectorTypes.cpp217 case ISD::FP_TO_SINT_SAT: in ScalarizeVectorResult()
767 case ISD::FP_TO_SINT_SAT: in ScalarizeVectorOperand()
1363 case ISD::FP_TO_SINT_SAT: in SplitVectorResult()
3463 case ISD::FP_TO_SINT_SAT: in SplitVectorOperand()
4886 case ISD::FP_TO_SINT_SAT: in WidenVectorResult()
6872 case ISD::FP_TO_SINT_SAT: in WidenVectorOperand()
H A DLegalizeFloatTypes.cpp1152 case ISD::FP_TO_SINT_SAT: in SoftenFloatOperand()
2630 case ISD::FP_TO_SINT_SAT: in PromoteFloatOperand()
3744 case ISD::FP_TO_SINT_SAT: in SoftPromoteHalfOperand()
H A DLegalizeDAG.cpp1188 case ISD::FP_TO_SINT_SAT: in LegalizeOp()
3496 case ISD::FP_TO_SINT_SAT: in ExpandNode()
5398 case ISD::FP_TO_SINT_SAT: in PromoteNode()
H A DLegalizeIntegerTypes.cpp186 case ISD::FP_TO_SINT_SAT: in PromoteIntegerResult()
2984 case ISD::FP_TO_SINT_SAT: in ExpandIntegerResult()
H A DSelectionDAG.cpp4860 case ISD::FP_TO_SINT_SAT: in ComputeNumSignBits()
7680 case ISD::FP_TO_SINT_SAT: in getNode()
H A DSelectionDAGBuilder.cpp7037 setValue(&I, DAG.getNode(ISD::FP_TO_SINT_SAT, sdl, VT, in visitIntrinsicCall()
H A DTargetLowering.cpp11637 bool IsSigned = Node->getOpcode() == ISD::FP_TO_SINT_SAT; in expandFP_TO_INT_SAT()
H A DDAGCombiner.cpp6005 unsigned NewOpc = Unsigned ? ISD::FP_TO_UINT_SAT : ISD::FP_TO_SINT_SAT; in PerformMinMaxFpToSatCombine()
/freebsd/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86ISelLowering.h732 FP_TO_SINT_SAT, enumerator
H A DX86InstrFragmentsSIMD.td397 def X86fp2sisat : SDNode<"X86ISD::FP_TO_SINT_SAT", SDTFPToxIntSatOp>;
H A DX86ISelLowering.cpp317 setOperationAction(ISD::FP_TO_SINT_SAT, VT, Custom); in X86TargetLowering()
323 setOperationAction(ISD::FP_TO_SINT_SAT, MVT::i64, Custom); in X86TargetLowering()
328 setOperationAction(ISD::FP_TO_SINT_SAT, MVT::v2i32, Custom); in X86TargetLowering()
332 setOperationAction(ISD::FP_TO_SINT_SAT, VT, Legal); in X86TargetLowering()
336 setOperationAction(ISD::FP_TO_SINT_SAT, MVT::v8i64, Legal); in X86TargetLowering()
340 setOperationAction(ISD::FP_TO_SINT_SAT, MVT::i64, Legal); in X86TargetLowering()
2685 ISD::FP_TO_SINT_SAT, in X86TargetLowering()
22014 bool IsSigned = Node->getOpcode() == ISD::FP_TO_SINT_SAT; in LowerFP_TO_INT_SAT()
33625 case ISD::FP_TO_SINT_SAT: in LowerOperation()
34128 case ISD::FP_TO_SINT_SAT: in ReplaceNodeResults()
[all …]
/freebsd/contrib/llvm-project/llvm/include/llvm/Target/
H A DTargetSelectionDAG.td595 def fp_to_sint_sat : SDNode<"ISD::FP_TO_SINT_SAT" , SDTFPToIntSatOp>;
597 def fp_to_sint_sat_gi : SDNode<"ISD::FP_TO_SINT_SAT" , SDTFPToIntOp>;
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/
H A DTargetLoweringBase.cpp808 ISD::FP_TO_SINT_SAT, ISD::FP_TO_UINT_SAT, in initActions()
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64ISelLowering.cpp617 setOperationAction(ISD::FP_TO_SINT_SAT, MVT::i32, Custom); in AArch64TargetLowering()
618 setOperationAction(ISD::FP_TO_SINT_SAT, MVT::i64, Custom); in AArch64TargetLowering()
1134 setTargetDAGCombine({ISD::FP_TO_SINT, ISD::FP_TO_UINT, ISD::FP_TO_SINT_SAT, in AArch64TargetLowering()
1258 ISD::FP_ROUND, ISD::FP_TO_SINT_SAT, ISD::FP_TO_UINT_SAT, ISD::MUL, in AArch64TargetLowering()
2064 {ISD::FP_TO_SINT, ISD::FP_TO_UINT, ISD::FP_TO_SINT_SAT, in addTypeForNEON()
4707 if (Op.getOpcode() == ISD::FP_TO_SINT_SAT) { in LowerVectorFP_TO_INT_SAT()
4772 if (Op.getOpcode() == ISD::FP_TO_SINT_SAT) { in LowerFP_TO_INT_SAT()
4804 return DAG.getNode(ISD::FP_TO_SINT_SAT, DL, VT, FOp, in LowerVectorXRINT()
7377 case ISD::FP_TO_SINT_SAT: in LowerOperation()
19270 if (N->getOpcode() == ISD::FP_TO_SINT_SAT || in performFpToIntCombine()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVISelLowering.cpp644 setOperationAction({ISD::FP_TO_UINT_SAT, ISD::FP_TO_SINT_SAT}, XLenVT, in RISCVTargetLowering()
834 setOperationAction({ISD::FP_TO_SINT_SAT, ISD::FP_TO_UINT_SAT}, VT, in RISCVTargetLowering()
895 setOperationAction({ISD::FP_TO_SINT_SAT, ISD::FP_TO_UINT_SAT}, VT, in RISCVTargetLowering()
1309 setOperationAction({ISD::FP_TO_SINT_SAT, ISD::FP_TO_UINT_SAT}, VT, in RISCVTargetLowering()
1646 ISD::FP_TO_SINT_SAT, ISD::FP_TO_UINT_SAT}); in RISCVTargetLowering()
3077 bool IsSigned = Op.getOpcode() == ISD::FP_TO_SINT_SAT; in lowerFP_TO_INT_SAT()
7644 case ISD::FP_TO_SINT_SAT: in LowerOperation()
17754 bool IsSigned = N->getOpcode() == ISD::FP_TO_SINT_SAT; in performFP_TO_INT_SATCombine()
20079 case ISD::FP_TO_SINT_SAT: in PerformDAGCombine()
/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMISelLowering.cpp326 setOperationAction(ISD::FP_TO_SINT_SAT, VT, Custom); in addMVEVectorTypes()
766 setOperationAction(ISD::FP_TO_SINT_SAT, MVT::i32, Custom); in ARMTargetLowering()
768 setOperationAction(ISD::FP_TO_SINT_SAT, MVT::i64, Custom); in ARMTargetLowering()
6034 bool IsSigned = Op.getOpcode() == ISD::FP_TO_SINT_SAT; in LowerFP_TO_INT_SAT()
10651 case ISD::FP_TO_SINT_SAT: in LowerOperation()
10846 case ISD::FP_TO_SINT_SAT: in ReplaceNodeResults()
H A DARMISelDAGToDAG.cpp3782 case ISD::FP_TO_SINT_SAT: in Select()