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Searched refs:FP_TO_SINT (Results 1 – 25 of 41) sorted by relevance

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/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64TargetTransformInfo.cpp2625 { ISD::FP_TO_SINT, MVT::v2i32, MVT::v2f32, 1 }, in getCastInstrCost()
2626 { ISD::FP_TO_SINT, MVT::v4i32, MVT::v4f32, 1 }, in getCastInstrCost()
2627 { ISD::FP_TO_SINT, MVT::v2i64, MVT::v2f64, 1 }, in getCastInstrCost()
2633 { ISD::FP_TO_SINT, MVT::v2i64, MVT::v2f32, 2 }, in getCastInstrCost()
2634 { ISD::FP_TO_SINT, MVT::v2i16, MVT::v2f32, 1 }, in getCastInstrCost()
2635 { ISD::FP_TO_SINT, MVT::v2i8, MVT::v2f32, 1 }, in getCastInstrCost()
2641 { ISD::FP_TO_SINT, MVT::v4i16, MVT::v4f32, 2 }, in getCastInstrCost()
2642 { ISD::FP_TO_SINT, MVT::v4i8, MVT::v4f32, 2 }, in getCastInstrCost()
2647 { ISD::FP_TO_SINT, MVT::nxv2i64, MVT::nxv2f32, 1 }, in getCastInstrCost()
2648 { ISD::FP_TO_SINT, MVT::nxv2i32, MVT::nxv2f32, 1 }, in getCastInstrCost()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86TargetTransformInfo.cpp2286 { ISD::FP_TO_SINT, MVT::v8i64, MVT::v8f32, { 1, 1, 1, 1 } }, in getCastInstrCost()
2287 { ISD::FP_TO_SINT, MVT::v8i64, MVT::v8f64, { 1, 1, 1, 1 } }, in getCastInstrCost()
2413 { ISD::FP_TO_SINT, MVT::v16i8, MVT::v16f32, { 2, 1, 1, 1 } }, in getCastInstrCost()
2414 { ISD::FP_TO_SINT, MVT::v16i8, MVT::v16f64, { 7, 1, 1, 1 } }, in getCastInstrCost()
2415 { ISD::FP_TO_SINT, MVT::v32i8, MVT::v32f64, {15, 1, 1, 1 } }, in getCastInstrCost()
2416 { ISD::FP_TO_SINT, MVT::v64i8, MVT::v64f32, {11, 1, 1, 1 } }, in getCastInstrCost()
2417 { ISD::FP_TO_SINT, MVT::v64i8, MVT::v64f64, {31, 1, 1, 1 } }, in getCastInstrCost()
2418 { ISD::FP_TO_SINT, MVT::v8i16, MVT::v8f64, { 3, 1, 1, 1 } }, in getCastInstrCost()
2419 { ISD::FP_TO_SINT, MVT::v16i16, MVT::v16f64, { 7, 1, 1, 1 } }, in getCastInstrCost()
2420 { ISD::FP_TO_SINT, MVT::v32i16, MVT::v32f32, { 5, 1, 1, 1 } }, in getCastInstrCost()
[all …]
H A DX86ISelLowering.cpp291 setOperationAction(ISD::FP_TO_SINT, MVT::i8, Promote); in X86TargetLowering()
294 setOperationAction(ISD::FP_TO_SINT, MVT::i16, Custom); in X86TargetLowering()
296 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom); in X86TargetLowering()
300 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom); in X86TargetLowering()
1006 setOperationAction(ISD::FP_TO_SINT, VT, Expand); in X86TargetLowering()
1205 setOperationAction(ISD::FP_TO_SINT, MVT::v4i32, Custom); in X86TargetLowering()
1207 setOperationAction(ISD::FP_TO_SINT, MVT::v2i32, Custom); in X86TargetLowering()
1214 setOperationAction(ISD::FP_TO_SINT, VT, Custom); in X86TargetLowering()
1460 setOperationPromotedToType(ISD::FP_TO_SINT, MVT::v8i16, MVT::v8i32); in X86TargetLowering()
1464 setOperationAction(ISD::FP_TO_SINT, MVT::v8i32, Custom); in X86TargetLowering()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMTargetTransformInfo.cpp709 { ISD::FP_TO_SINT, MVT::v4i32, MVT::v4f32, 1 }, in getCastInstrCost()
711 { ISD::FP_TO_SINT, MVT::v4i8, MVT::v4f32, 3 }, in getCastInstrCost()
713 { ISD::FP_TO_SINT, MVT::v4i16, MVT::v4f32, 2 }, in getCastInstrCost()
727 { ISD::FP_TO_SINT, MVT::v2i32, MVT::v2f64, 2 }, in getCastInstrCost()
729 { ISD::FP_TO_SINT, MVT::v8i16, MVT::v8f32, 4 }, in getCastInstrCost()
731 { ISD::FP_TO_SINT, MVT::v16i16, MVT::v16f32, 8 }, in getCastInstrCost()
744 { ISD::FP_TO_SINT, MVT::i1, MVT::f32, 2 }, in getCastInstrCost()
746 { ISD::FP_TO_SINT, MVT::i1, MVT::f64, 2 }, in getCastInstrCost()
748 { ISD::FP_TO_SINT, MVT::i8, MVT::f32, 2 }, in getCastInstrCost()
750 { ISD::FP_TO_SINT, MVT::i8, MVT::f64, 2 }, in getCastInstrCost()
[all …]
H A DARMISelLowering.cpp187 setOperationAction(ISD::FP_TO_SINT, VT, Custom); in addTypeForNEON()
192 setOperationAction(ISD::FP_TO_SINT, VT, Expand); in addTypeForNEON()
318 setOperationAction(ISD::FP_TO_SINT, VT, Expand); in addMVEVectorTypes()
472 setOperationAction(ISD::FP_TO_SINT, VT, Expand); in addMVEVectorTypes()
483 setOperationAction(ISD::FP_TO_SINT, MVT::v2i1, Expand); in addMVEVectorTypes()
958 setOperationAction(ISD::FP_TO_SINT, MVT::v4i16, Custom); in ARMTargetLowering()
959 setOperationAction(ISD::FP_TO_SINT, MVT::v8i16, Custom); in ARMTargetLowering()
1009 setTargetDAGCombine({ISD::SHL, ISD::SRL, ISD::SRA, ISD::FP_TO_SINT, in ARMTargetLowering()
1080 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom); in ARMTargetLowering()
1082 setOperationAction(ISD::FP_TO_SINT, MVT::f64, Custom); in ARMTargetLowering()
[all …]
/freebsd/contrib/llvm-project/llvm/include/llvm/IR/
H A DConstrainedOps.def60 DAG_INSTRUCTION(FPToSI, 1, 0, experimental_constrained_fptosi, FP_TO_SINT)
H A DVPIntrinsics.def506 HELPER_REGISTER_FP_CAST_VP(fptosi, VP_FP_TO_SINT, FPToSI, FP_TO_SINT, 0)
/freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DISDOpcodes.h864 FP_TO_SINT, enumerator
/freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonISelLoweringHVX.cpp256 setOperationAction(ISD::FP_TO_SINT, T, Custom); in initializeHVXLowering()
329 setOperationAction(ISD::FP_TO_SINT, T, Custom); in initializeHVXLowering()
426 setOperationAction(ISD::FP_TO_SINT, VecTy, Custom); in initializeHVXLowering()
2275 assert(Op.getOpcode() == ISD::FP_TO_SINT || in LowerHvxFpToInt()
2676 assert(Opc == ISD::FP_TO_SINT || Opc == ISD::FP_TO_UINT || in EqualizeFpIntConversion()
2687 bool Signed = Opc == ISD::FP_TO_SINT || Opc == ISD::SINT_TO_FP; in EqualizeFpIntConversion()
2699 assert(Opc == ISD::FP_TO_SINT || Opc == ISD::FP_TO_UINT); in ExpandHvxFpToInt()
2809 if (Opc == ISD::FP_TO_SINT) { in ExpandHvxFpToInt()
3156 case ISD::FP_TO_SINT: in LowerHvxOperation()
3234 case ISD::FP_TO_SINT in LowerHvxOperation()
[all...]
H A DHexagonISelLowering.cpp1796 setOperationAction(ISD::FP_TO_SINT, MVT::i1, Promote); in HexagonTargetLowering()
1797 setOperationAction(ISD::FP_TO_SINT, MVT::i8, Promote); in HexagonTargetLowering()
1798 setOperationAction(ISD::FP_TO_SINT, MVT::i16, Promote); in HexagonTargetLowering()
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DLegalizeVectorOps.cpp390 case ISD::FP_TO_SINT: in LegalizeOp()
676 case ISD::FP_TO_SINT: in Promote()
798 TLI.isOperationLegalOrCustom(ISD::FP_TO_SINT, NVT)) in PromoteFP_TO_INT()
799 NewOpc = ISD::FP_TO_SINT; in PromoteFP_TO_INT()
H A DLegalizeFloatTypes.cpp1008 case ISD::FP_TO_SINT: in SoftenFloatOperand()
1136 bool Signed = N->getOpcode() == ISD::FP_TO_SINT || in SoftenFloatOp_FP_TO_XINT()
2081 case ISD::FP_TO_SINT: in ExpandFloatOperand()
2213 bool Signed = N->getOpcode() == ISD::FP_TO_SINT || in ExpandFloatOp_FP_TO_XINT()
2410 case ISD::FP_TO_SINT: in PromoteFloatOperand()
3399 case ISD::FP_TO_SINT: in SoftPromoteHalfOperand()
H A DSelectionDAGDumper.cpp392 case ISD::FP_TO_SINT: return "fp_to_sint"; in getOperationName()
H A DLegalizeDAG.cpp2926 bool IsSigned = N->getOpcode() == ISD::FP_TO_SINT || in PromoteLegalFP_TO_INT()
2942 OpToUse = IsStrict ? ISD::STRICT_FP_TO_SINT : ISD::FP_TO_SINT; in PromoteLegalFP_TO_INT()
3414 case ISD::FP_TO_SINT: in ExpandNode()
4846 case ISD::FP_TO_SINT: in ConvertNodeToLibcall()
4852 bool Signed = Node->getOpcode() == ISD::FP_TO_SINT || in ConvertNodeToLibcall()
5182 case ISD::FP_TO_SINT: in PromoteNode()
H A DLegalizeIntegerTypes.cpp165 case ISD::FP_TO_SINT: in PromoteIntegerResult()
823 TLI.isOperationLegalOrCustom(ISD::FP_TO_SINT, NVT)) in PromoteIntRes_FP_TO_XINT()
824 NewOpc = ISD::FP_TO_SINT; in PromoteIntRes_FP_TO_XINT()
2798 case ISD::FP_TO_SINT: in ExpandIntegerResult()
3914 bool IsSigned = N->getOpcode() == ISD::FP_TO_SINT || in ExpandIntRes_FP_TO_XINT()
3928 Op = DAG.getNode(IsSigned ? ISD::FP_TO_SINT : ISD::FP_TO_UINT, dl, VT, Op); in ExpandIntRes_FP_TO_XINT()
H A DLegalizeVectorTypes.cpp110 case ISD::FP_TO_SINT: in ScalarizeVectorResult()
753 case ISD::FP_TO_SINT: in ScalarizeVectorOperand()
1190 case ISD::FP_TO_SINT: in SplitVectorResult()
3192 case ISD::FP_TO_SINT: in SplitVectorOperand()
4500 case ISD::FP_TO_SINT: in WidenVectorResult()
6413 case ISD::FP_TO_SINT: in WidenVectorOperand()
/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DR600ISelLowering.cpp110 setOperationAction({ISD::FP_TO_UINT, ISD::FP_TO_SINT}, {MVT::i1, MVT::i64}, in R600TargetLowering()
201 setTargetDAGCombine({ISD::FP_ROUND, ISD::FP_TO_SINT, ISD::EXTRACT_VECTOR_ELT, in R600TargetLowering()
595 case ISD::FP_TO_SINT: { in ReplaceNodeResults()
1737 case ISD::FP_TO_SINT: { in PerformDAGCombine()
H A DAMDGPUISelLowering.cpp489 {ISD::UINT_TO_FP, ISD::SINT_TO_FP, ISD::FP_TO_SINT, ISD::FP_TO_UINT}, in AMDGPUTargetLowering()
509 setOperationAction({ISD::ADD, ISD::AND, ISD::FP_TO_SINT, in AMDGPUTargetLowering()
1403 case ISD::FP_TO_SINT: in LowerOperation()
1929 ISD::NodeType ToInt = Sign ? ISD::FP_TO_SINT : ISD::FP_TO_UINT; in LowerDIVREM24()
3079 SDValue IntE = DAG.getNode(ISD::FP_TO_SINT, SL, MVT::i32, E); in lowerFEXP()
3499 SDValue Hi = DAG.getNode((Signed && SrcVT == MVT::f64) ? ISD::FP_TO_SINT in LowerFP_TO_INT64()
3654 OpOpcode == ISD::FP_TO_SINT ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND; in LowerFP_TO_INT()
3659 return LowerFP_TO_INT64(Op, DAG, OpOpcode == ISD::FP_TO_SINT); in LowerFP_TO_INT()
/freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCISelLowering.cpp284 setOperationAction(ISD::FP_TO_SINT, MVT::i1, Promote); in PPCTargetLowering()
285 AddPromotedToType(ISD::FP_TO_SINT, MVT::i1, in PPCTargetLowering()
316 setOperationAction(ISD::FP_TO_SINT, MVT::ppcf128, Custom); in PPCTargetLowering()
541 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Legal); in PPCTargetLowering()
551 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom); in PPCTargetLowering()
696 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom); in PPCTargetLowering()
727 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom); in PPCTargetLowering()
737 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom); in PPCTargetLowering()
924 setOperationAction(ISD::FP_TO_SINT, MVT::v4i32, Legal); in PPCTargetLowering()
1112 setOperationAction(ISD::FP_TO_SINT, MVT::v2i64, Legal); in PPCTargetLowering()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/Sparc/
H A DSparcISelLowering.cpp1687 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom); in SparcTargetLowering()
1689 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom); in SparcTargetLowering()
3253 case ISD::FP_TO_SINT: return LowerFP_TO_SINT(Op, DAG, *this, in LowerOperation()
3604 case ISD::FP_TO_SINT: in ReplaceNodeResults()
3610 libCall = ((N->getOpcode() == ISD::FP_TO_SINT) in ReplaceNodeResults()
/freebsd/contrib/llvm-project/llvm/lib/Target/Xtensa/
H A DXtensaISelLowering.cpp70 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Expand); in XtensaTargetLowering()
/freebsd/contrib/llvm-project/llvm/lib/Target/LoongArch/
H A DLoongArchISelLowering.cpp80 setOperationAction(ISD::FP_TO_SINT, GRLenVT, Custom); in LoongArchTargetLowering()
129 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom); in LoongArchTargetLowering()
273 setOperationAction({ISD::FP_TO_SINT, ISD::FP_TO_UINT}, VT, Legal); in LoongArchTargetLowering()
320 setOperationAction({ISD::FP_TO_SINT, ISD::FP_TO_UINT}, VT, Legal); in LoongArchTargetLowering()
404 case ISD::FP_TO_SINT: in LowerOperation()
2842 case ISD::FP_TO_SINT: { in ReplaceNodeResults()
/freebsd/contrib/llvm-project/llvm/lib/Target/NVPTX/
H A DNVPTXISelLowering.cpp531 ISD::FP_TO_SINT, ISD::FP_TO_UINT, ISD::FSHL, ISD::FSHR, in NVPTXTargetLowering()
703 ISD::MULHU, ISD::FP_TO_SINT, ISD::FP_TO_UINT, in NVPTXTargetLowering()
796 {ISD::SINT_TO_FP, ISD::UINT_TO_FP, ISD::FP_TO_SINT, ISD::FP_TO_UINT}, in NVPTXTargetLowering()
800 {ISD::SINT_TO_FP, ISD::UINT_TO_FP, ISD::FP_TO_SINT, ISD::FP_TO_UINT}, in NVPTXTargetLowering()
2791 case ISD::FP_TO_SINT: in LowerOperation()
/freebsd/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMipsISelLowering.cpp360 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom); in MipsTargetLowering()
389 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom); in MipsTargetLowering()
1264 case ISD::FP_TO_SINT: return lowerFP_TO_SINT(Op, DAG); in LowerOperation()
2818 if (Val.getOpcode() != ISD::FP_TO_SINT || in lowerFP_TO_SINT_STORE()
/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVTargetTransformInfo.cpp1101 case ISD::FP_TO_SINT: in getCastInstrCost()

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