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Searched refs:FP_TO_SINT (Results 1 – 25 of 43) sorted by relevance

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/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64TargetTransformInfo.cpp3384 {ISD::FP_TO_SINT, MVT::v2i32, MVT::v2f32, 1}, in getCastInstrCost()
3385 {ISD::FP_TO_SINT, MVT::v4i32, MVT::v4f32, 1}, in getCastInstrCost()
3386 {ISD::FP_TO_SINT, MVT::v2i64, MVT::v2f64, 1}, in getCastInstrCost()
3392 {ISD::FP_TO_SINT, MVT::v2i64, MVT::v2f32, 2}, in getCastInstrCost()
3393 {ISD::FP_TO_SINT, MVT::v2i16, MVT::v2f32, 1}, in getCastInstrCost()
3394 {ISD::FP_TO_SINT, MVT::v2i8, MVT::v2f32, 1}, in getCastInstrCost()
3400 {ISD::FP_TO_SINT, MVT::v4i16, MVT::v4f32, 2}, in getCastInstrCost()
3401 {ISD::FP_TO_SINT, MVT::v4i8, MVT::v4f32, 2}, in getCastInstrCost()
3406 {ISD::FP_TO_SINT, MVT::nxv2i64, MVT::nxv2f32, 1}, in getCastInstrCost()
3407 {ISD::FP_TO_SINT, MVT::nxv2i32, MVT::nxv2f32, 1}, in getCastInstrCost()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86TargetTransformInfo.cpp2403 { ISD::FP_TO_SINT, MVT::v8i64, MVT::v8f32, { 1, 1, 1, 1 } }, in getCastInstrCost()
2404 { ISD::FP_TO_SINT, MVT::v8i64, MVT::v8f64, { 1, 1, 1, 1 } }, in getCastInstrCost()
2533 { ISD::FP_TO_SINT, MVT::v16i8, MVT::v16f32, { 2, 1, 1, 1 } }, in getCastInstrCost()
2534 { ISD::FP_TO_SINT, MVT::v16i8, MVT::v16f64, { 7, 1, 1, 1 } }, in getCastInstrCost()
2535 { ISD::FP_TO_SINT, MVT::v32i8, MVT::v32f64, {15, 1, 1, 1 } }, in getCastInstrCost()
2536 { ISD::FP_TO_SINT, MVT::v64i8, MVT::v64f32, {11, 1, 1, 1 } }, in getCastInstrCost()
2537 { ISD::FP_TO_SINT, MVT::v64i8, MVT::v64f64, {31, 1, 1, 1 } }, in getCastInstrCost()
2538 { ISD::FP_TO_SINT, MVT::v8i16, MVT::v8f64, { 3, 1, 1, 1 } }, in getCastInstrCost()
2539 { ISD::FP_TO_SINT, MVT::v16i16, MVT::v16f64, { 7, 1, 1, 1 } }, in getCastInstrCost()
2540 { ISD::FP_TO_SINT, MVT::v32i16, MVT::v32f32, { 5, 1, 1, 1 } }, in getCastInstrCost()
[all …]
H A DX86ISelLowering.cpp276 setOperationAction(ISD::FP_TO_SINT, MVT::i8, Promote); in X86TargetLowering()
279 setOperationAction(ISD::FP_TO_SINT, MVT::i16, Custom); in X86TargetLowering()
281 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom); in X86TargetLowering()
285 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom); in X86TargetLowering()
1019 setOperationAction(ISD::FP_TO_SINT, VT, Expand); in X86TargetLowering()
1226 setOperationAction(ISD::FP_TO_SINT, MVT::v4i32, Custom); in X86TargetLowering()
1228 setOperationAction(ISD::FP_TO_SINT, MVT::v2i32, Custom); in X86TargetLowering()
1235 setOperationAction(ISD::FP_TO_SINT, VT, Custom); in X86TargetLowering()
1484 setOperationPromotedToType(ISD::FP_TO_SINT, MVT::v8i16, MVT::v8i32); in X86TargetLowering()
1488 setOperationAction(ISD::FP_TO_SINT, MVT::v8i32, Custom); in X86TargetLowering()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMTargetTransformInfo.cpp729 { ISD::FP_TO_SINT, MVT::v4i32, MVT::v4f32, 1 }, in getCastInstrCost()
731 { ISD::FP_TO_SINT, MVT::v4i8, MVT::v4f32, 3 }, in getCastInstrCost()
733 { ISD::FP_TO_SINT, MVT::v4i16, MVT::v4f32, 2 }, in getCastInstrCost()
747 { ISD::FP_TO_SINT, MVT::v2i32, MVT::v2f64, 2 }, in getCastInstrCost()
749 { ISD::FP_TO_SINT, MVT::v8i16, MVT::v8f32, 4 }, in getCastInstrCost()
751 { ISD::FP_TO_SINT, MVT::v16i16, MVT::v16f32, 8 }, in getCastInstrCost()
764 { ISD::FP_TO_SINT, MVT::i1, MVT::f32, 2 }, in getCastInstrCost()
766 { ISD::FP_TO_SINT, MVT::i1, MVT::f64, 2 }, in getCastInstrCost()
768 { ISD::FP_TO_SINT, MVT::i8, MVT::f32, 2 }, in getCastInstrCost()
770 { ISD::FP_TO_SINT, MVT::i8, MVT::f64, 2 }, in getCastInstrCost()
[all …]
H A DARMISelLowering.cpp192 setOperationAction(ISD::FP_TO_SINT, VT, Custom); in addTypeForNEON()
197 setOperationAction(ISD::FP_TO_SINT, VT, Expand); in addTypeForNEON()
323 setOperationAction(ISD::FP_TO_SINT, VT, Expand); in addMVEVectorTypes()
482 setOperationAction(ISD::FP_TO_SINT, VT, Expand); in addMVEVectorTypes()
493 setOperationAction(ISD::FP_TO_SINT, MVT::v2i1, Expand); in addMVEVectorTypes()
956 setOperationAction(ISD::FP_TO_SINT, MVT::v4i16, Custom); in ARMTargetLowering()
957 setOperationAction(ISD::FP_TO_SINT, MVT::v8i16, Custom); in ARMTargetLowering()
1007 setTargetDAGCombine({ISD::SHL, ISD::SRL, ISD::SRA, ISD::FP_TO_SINT, in ARMTargetLowering()
1079 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom); in ARMTargetLowering()
1081 setOperationAction(ISD::FP_TO_SINT, MVT::f64, Custom); in ARMTargetLowering()
[all …]
/freebsd/contrib/llvm-project/llvm/include/llvm/IR/
H A DConstrainedOps.def60 DAG_INSTRUCTION(FPToSI, 1, 0, experimental_constrained_fptosi, FP_TO_SINT)
H A DVPIntrinsics.def478 HELPER_REGISTER_FP_CAST_VP(fptosi, VP_FP_TO_SINT, FPToSI, FP_TO_SINT)
/freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DISDOpcodes.h908 FP_TO_SINT, enumerator
/freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonISelLoweringHVX.cpp260 setOperationAction(ISD::FP_TO_SINT, T, Custom); in initializeHVXLowering()
335 setOperationAction(ISD::FP_TO_SINT, T, Custom); in initializeHVXLowering()
436 setOperationAction(ISD::FP_TO_SINT, VecTy, Custom); in initializeHVXLowering()
2312 assert(Op.getOpcode() == ISD::FP_TO_SINT || in LowerHvxFpToInt()
2713 assert(Opc == ISD::FP_TO_SINT || Opc == ISD::FP_TO_UINT || in EqualizeFpIntConversion()
2724 bool Signed = Opc == ISD::FP_TO_SINT || Opc == ISD::SINT_TO_FP; in EqualizeFpIntConversion()
2736 assert(Opc == ISD::FP_TO_SINT || Opc == ISD::FP_TO_UINT); in ExpandHvxFpToInt()
2846 if (Opc == ISD::FP_TO_SINT) { in ExpandHvxFpToInt()
3193 case ISD::FP_TO_SINT: in LowerHvxOperation()
3271 case ISD::FP_TO_SINT: in LowerHvxOperation()
[all …]
H A DHexagonISelLowering.cpp1870 setOperationAction(ISD::FP_TO_SINT, MVT::i1, Promote); in HexagonTargetLowering()
1871 setOperationAction(ISD::FP_TO_SINT, MVT::i8, Promote); in HexagonTargetLowering()
1872 setOperationAction(ISD::FP_TO_SINT, MVT::i16, Promote); in HexagonTargetLowering()
/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DR600ISelLowering.cpp114 setOperationAction({ISD::FP_TO_UINT, ISD::FP_TO_SINT}, {MVT::i1, MVT::i64}, in R600TargetLowering()
205 setTargetDAGCombine({ISD::FP_ROUND, ISD::FP_TO_SINT, ISD::EXTRACT_VECTOR_ELT, in R600TargetLowering()
599 case ISD::FP_TO_SINT: { in ReplaceNodeResults()
1742 case ISD::FP_TO_SINT: { in PerformDAGCombine()
H A DAMDGPUISelLowering.cpp502 {ISD::UINT_TO_FP, ISD::SINT_TO_FP, ISD::FP_TO_SINT, ISD::FP_TO_UINT}, in AMDGPUTargetLowering()
522 setOperationAction({ISD::ADD, ISD::AND, ISD::FP_TO_SINT, in AMDGPUTargetLowering()
1460 case ISD::FP_TO_SINT: in LowerOperation()
1986 ISD::NodeType ToInt = Sign ? ISD::FP_TO_SINT : ISD::FP_TO_UINT; in LowerDIVREM24()
3137 SDValue IntE = DAG.getNode(ISD::FP_TO_SINT, SL, MVT::i32, E); in lowerFEXP()
3557 SDValue Hi = DAG.getNode((Signed && SrcVT == MVT::f64) ? ISD::FP_TO_SINT in LowerFP_TO_INT64()
3718 OpOpcode == ISD::FP_TO_SINT ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND; in LowerFP_TO_INT()
3723 return LowerFP_TO_INT64(Op, DAG, OpOpcode == ISD::FP_TO_SINT); in LowerFP_TO_INT()
/freebsd/contrib/llvm-project/llvm/lib/Target/Xtensa/
H A DXtensaISelLowering.cpp92 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Expand); in XtensaTargetLowering()
234 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Legal); in XtensaTargetLowering()
241 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Expand); in XtensaTargetLowering()
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DLegalizeVectorOps.cpp401 case ISD::FP_TO_SINT: in LegalizeOp()
721 case ISD::FP_TO_SINT: in Promote()
874 TLI.isOperationLegalOrCustom(ISD::FP_TO_SINT, NVT)) in PromoteFP_TO_INT()
875 NewOpc = ISD::FP_TO_SINT; in PromoteFP_TO_INT()
H A DLegalizeFloatTypes.cpp1150 case ISD::FP_TO_SINT: in SoftenFloatOperand()
1281 bool Signed = N->getOpcode() == ISD::FP_TO_SINT || in SoftenFloatOp_FP_TO_XINT()
2297 case ISD::FP_TO_SINT: in ExpandFloatOperand()
2429 bool Signed = N->getOpcode() == ISD::FP_TO_SINT || in ExpandFloatOp_FP_TO_XINT()
2623 case ISD::FP_TO_SINT: in PromoteFloatOperand()
3742 case ISD::FP_TO_SINT: in SoftPromoteHalfOperand()
H A DLegalizeDAG.cpp2953 bool IsSigned = N->getOpcode() == ISD::FP_TO_SINT || in PromoteLegalFP_TO_INT()
2969 OpToUse = IsStrict ? ISD::STRICT_FP_TO_SINT : ISD::FP_TO_SINT; in PromoteLegalFP_TO_INT()
3471 case ISD::FP_TO_SINT: in ExpandNode()
3507 Results.push_back(DAG.getNode(ISD::FP_TO_SINT, dl, ResVT, RoundNode)); in ExpandNode()
4475 Results.push_back(DAG.getNode(ISD::FP_TO_SINT, dl, ResVT, RoundNode)); in ExpandNode()
5054 case ISD::FP_TO_SINT: in ConvertNodeToLibcall()
5060 bool Signed = Node->getOpcode() == ISD::FP_TO_SINT || in ConvertNodeToLibcall()
5393 case ISD::FP_TO_SINT: in PromoteNode()
H A DSelectionDAGDumper.cpp412 case ISD::FP_TO_SINT: return "fp_to_sint"; in getOperationName()
H A DLegalizeVectorTypes.cpp112 case ISD::FP_TO_SINT: in ScalarizeVectorResult()
757 case ISD::FP_TO_SINT: in ScalarizeVectorOperand()
1238 case ISD::FP_TO_SINT: in SplitVectorResult()
3467 case ISD::FP_TO_SINT: in SplitVectorOperand()
4869 case ISD::FP_TO_SINT: in WidenVectorResult()
6860 case ISD::FP_TO_SINT: in WidenVectorOperand()
/freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCISelLowering.cpp294 setOperationAction(ISD::FP_TO_SINT, MVT::i1, Promote); in PPCTargetLowering()
295 AddPromotedToType(ISD::FP_TO_SINT, MVT::i1, RegVT); in PPCTargetLowering()
324 setOperationAction(ISD::FP_TO_SINT, MVT::ppcf128, Custom); in PPCTargetLowering()
548 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Legal); in PPCTargetLowering()
558 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom); in PPCTargetLowering()
703 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom); in PPCTargetLowering()
734 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom); in PPCTargetLowering()
744 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom); in PPCTargetLowering()
933 setOperationAction(ISD::FP_TO_SINT, MVT::v4i32, Legal); in PPCTargetLowering()
1129 setOperationAction(ISD::FP_TO_SINT, MVT::v2i64, Legal); in PPCTargetLowering()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/Sparc/
H A DSparcISelLowering.cpp1678 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom); in SparcTargetLowering()
1680 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom); in SparcTargetLowering()
3113 case ISD::FP_TO_SINT: return LowerFP_TO_SINT(Op, DAG, *this, in LowerOperation()
3458 case ISD::FP_TO_SINT: in ReplaceNodeResults()
3464 libCall = ((N->getOpcode() == ISD::FP_TO_SINT) in ReplaceNodeResults()
/freebsd/contrib/llvm-project/llvm/lib/Target/NVPTX/
H A DNVPTXISelLowering.cpp642 ISD::FP_TO_SINT, ISD::FP_TO_UINT, ISD::FSHL, ISD::FSHR, in NVPTXTargetLowering()
813 ISD::MULHU, ISD::FP_TO_SINT, ISD::FP_TO_UINT, in NVPTXTargetLowering()
925 {ISD::SINT_TO_FP, ISD::UINT_TO_FP, ISD::FP_TO_SINT, ISD::FP_TO_UINT}, in NVPTXTargetLowering()
929 {ISD::SINT_TO_FP, ISD::UINT_TO_FP, ISD::FP_TO_SINT, ISD::FP_TO_UINT}, in NVPTXTargetLowering()
2924 case ISD::FP_TO_SINT: in LowerOperation()
6346 if (isOperationLegal(ISD::FP_TO_SINT, ToVT)) in getPreferredFPToIntOpcode()
6347 return ISD::FP_TO_SINT; in getPreferredFPToIntOpcode()
/freebsd/contrib/llvm-project/llvm/lib/Target/SystemZ/
H A DSystemZISelLowering.cpp232 for (auto Op : {ISD::FP_TO_SINT, ISD::STRICT_FP_TO_SINT, in SystemZTargetLowering()
295 setOperationAction(ISD::FP_TO_SINT, MVT::i128, Custom); in SystemZTargetLowering()
501 setOperationAction(ISD::FP_TO_SINT, MVT::v2i64, Legal); in SystemZTargetLowering()
502 setOperationAction(ISD::FP_TO_SINT, MVT::v2f64, Legal); in SystemZTargetLowering()
521 setOperationAction(ISD::FP_TO_SINT, MVT::v4i32, Legal); in SystemZTargetLowering()
522 setOperationAction(ISD::FP_TO_SINT, MVT::v4f32, Legal); in SystemZTargetLowering()
6819 bool IsSigned = (Op->getOpcode() == ISD::FP_TO_SINT || in lower_FP_TO_INT()
7144 case ISD::FP_TO_SINT: in LowerOperation()
7336 case ISD::FP_TO_SINT: in LowerOperationWrapper()
/freebsd/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMipsISelLowering.cpp358 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom); in MipsTargetLowering()
397 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom); in MipsTargetLowering()
1357 case ISD::FP_TO_SINT: return lowerFP_TO_SINT(Op, DAG); in LowerOperation()
2970 if (Val.getOpcode() != ISD::FP_TO_SINT || in lowerFP_TO_SINT_STORE()
/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVTargetTransformInfo.cpp1615 case ISD::FP_TO_SINT: in getCastInstrCost()
1617 unsigned IsSigned = ISD == ISD::FP_TO_SINT; in getCastInstrCost()
/freebsd/contrib/llvm-project/llvm/lib/Target/LoongArch/
H A DLoongArchISelLowering.cpp82 setOperationAction(ISD::FP_TO_SINT, GRLenVT, Custom); in LoongArchTargetLowering()
144 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom); in LoongArchTargetLowering()
319 setOperationAction({ISD::FP_TO_SINT, ISD::FP_TO_UINT}, VT, Legal); in LoongArchTargetLowering()
386 setOperationAction({ISD::FP_TO_SINT, ISD::FP_TO_UINT}, VT, Legal); in LoongArchTargetLowering()
482 case ISD::FP_TO_SINT: in LowerOperation()
4053 case ISD::FP_TO_SINT: { in ReplaceNodeResults()

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