| /freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/ |
| H A D | ISDOpcodes.h | 942 FP_TO_FP16, enumerator
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | AMDGPUISelLowering.h | 543 FP_TO_FP16, enumerator
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| H A D | AMDGPUInstrInfo.td | 144 def AMDGPUfp_to_f16 : SDNode<"AMDGPUISD::FP_TO_FP16" , SDTFPToIntOp>;
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| H A D | AMDGPUISelLowering.cpp | 458 setOperationAction(ISD::FP_TO_FP16, {MVT::f64, MVT::f32}, Custom); in AMDGPUTargetLowering()
1402 case ISD::FP_TO_FP16: return LowerFP_TO_FP16(Op, DAG); in LowerOperation()
3527 return DAG.getNode(AMDGPUISD::FP_TO_FP16, DL, Op.getValueType(), N0); in LowerFP_TO_FP16()
5507 NODE_NAME_CASE(FP_TO_FP16) in getTargetNodeName()
5659 case AMDGPUISD::FP_TO_FP16: { in computeKnownBitsForTargetNode()
5828 case AMDGPUISD::FP_TO_FP16: in ComputeNumSignBitsForTargetNode()
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| H A D | SIISelLowering.cpp | 573 setOperationAction(ISD::FP_TO_FP16, MVT::i16, Promote); in SITargetLowering()
574 AddPromotedToType(ISD::FP_TO_FP16, MVT::i16, MVT::i32); in SITargetLowering()
6686 SDValue FpToFp16 = DAG.getNode(ISD::FP_TO_FP16, DL, MVT::i32, Src); in lowerFP_ROUND()
12635 case ISD::FP_TO_FP16: in isCanonicalized()
12657 case AMDGPUISD::FP_TO_FP16: in isCanonicalized()
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| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | LegalizeFloatTypes.cpp | 1001 case ISD::FP_TO_FP16: // Same as FP_ROUND for softening purposes in SoftenFloatOperand()
1056 assert(N->getOpcode() == ISD::FP_ROUND || N->getOpcode() == ISD::FP_TO_FP16 || in SoftenFloatOp_FP_ROUND()
1067 if (N->getOpcode() == ISD::FP_TO_FP16 || in SoftenFloatOp_FP_ROUND()
2359 return ISD::FP_TO_FP16; in GetPromotionOpcode()
2582 case ISD::FP_TO_FP16: in PromoteFloatResult()
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| H A D | SelectionDAGDumper.cpp | 402 case ISD::FP_TO_FP16: return "fp_to_fp16"; in getOperationName()
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| H A D | LegalizeDAG.cpp | 1002 case ISD::FP_TO_FP16: in LegalizeOp()
3719 case ISD::FP_TO_FP16: in ExpandNode()
3725 TLI.isOperationLegalOrCustom(ISD::FP_TO_FP16, MVT::f32)) { in ExpandNode()
3732 DAG.getNode(ISD::FP_TO_FP16, dl, Node->getValueType(0), FloatVal)); in ExpandNode()
4791 case ISD::FP_TO_FP16: { in ConvertNodeToLibcall()
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| H A D | LegalizeIntegerTypes.cpp | 173 case ISD::FP_TO_FP16: in PromoteIntegerResult()
487 return DAG.getNode(ISD::FP_TO_FP16, dl, NOutVT, GetPromotedFloat(InOp)); in PromoteIntRes_BITCAST()
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| H A D | SelectionDAG.cpp | 5924 case ISD::FP_TO_FP16: in getNode()
6525 case ISD::FP_TO_FP16: in FoldConstantArithmetic()
6530 (void)V.convert(Opcode == ISD::FP_TO_FP16 ? APFloat::IEEEhalf() in FoldConstantArithmetic()
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| H A D | DAGCombiner.cpp | 1968 case ISD::FP_TO_FP16: return visitFP_TO_FP16(N); in visit()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Sparc/ |
| H A D | SparcISelLowering.cpp | 1700 setOperationAction(ISD::FP_TO_FP16, MVT::f32, Expand); in SparcTargetLowering()
1702 setOperationAction(ISD::FP_TO_FP16, MVT::f64, Expand); in SparcTargetLowering()
1704 setOperationAction(ISD::FP_TO_FP16, MVT::f128, Expand); in SparcTargetLowering()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/CSKY/ |
| H A D | CSKYISelLowering.cpp | 121 ISD::FREM, ISD::FCOPYSIGN, ISD::FP16_TO_FP, ISD::FP_TO_FP16}; in CSKYTargetLowering()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
| H A D | HexagonISelLowering.cpp | 1810 setOperationAction(ISD::FP_TO_FP16, MVT::f32, Expand); in HexagonTargetLowering()
1811 setOperationAction(ISD::FP_TO_FP16, MVT::f64, Expand); in HexagonTargetLowering()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Mips/ |
| H A D | MipsISelLowering.cpp | 467 setOperationAction(ISD::FP_TO_FP16, MVT::f32, Expand); in MipsTargetLowering()
469 setOperationAction(ISD::FP_TO_FP16, MVT::f64, Expand); in MipsTargetLowering()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/WebAssembly/ |
| H A D | WebAssemblyISelLowering.cpp | 144 setOperationAction(ISD::FP_TO_FP16, T, Expand); in WebAssemblyTargetLowering()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/LoongArch/ |
| H A D | LoongArchISelLowering.cpp | 184 setOperationAction(ISD::FP_TO_FP16, MVT::f32, Expand); in LoongArchTargetLowering()
221 setOperationAction(ISD::FP_TO_FP16, MVT::f64, Expand); in LoongArchTargetLowering()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/VE/ |
| H A D | VEISelLowering.cpp | 221 setOperationAction(ISD::FP_TO_FP16, FPVT, Expand); in initSPUActions()
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| /freebsd/contrib/llvm-project/llvm/include/llvm/Target/ |
| H A D | TargetSelectionDAG.td | 565 def fp_to_f16 : SDNode<"ISD::FP_TO_FP16" , SDTFPToIntOp>;
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| /freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/ |
| H A D | RISCVISelLowering.cpp | 544 setOperationAction(ISD::FP_TO_FP16, MVT::f32, Custom); in RISCVTargetLowering()
592 setOperationAction(ISD::FP_TO_FP16, MVT::f64, Custom); in RISCVTargetLowering()
6735 case ISD::FP_TO_FP16: { in LowerOperation()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/ |
| H A D | PPCISelLowering.cpp | 222 setOperationAction(ISD::FP_TO_FP16, MVT::f64, Expand); in PPCTargetLowering()
225 setOperationAction(ISD::FP_TO_FP16, MVT::f32, Expand); in PPCTargetLowering()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/ARM/ |
| H A D | ARMISelLowering.cpp | 1484 setOperationAction(ISD::FP_TO_FP16, MVT::f64, Expand); in ARMTargetLowering()
1490 setOperationAction(ISD::FP_TO_FP16, MVT::f32, Expand); in ARMTargetLowering()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86ISelLowering.cpp | 434 for (auto Op : {ISD::FP16_TO_FP, ISD::STRICT_FP16_TO_FP, ISD::FP_TO_FP16, in X86TargetLowering()
32408 case ISD::FP_TO_FP16: in LowerOperation()
57473 if (N->getOperand(0).getOpcode() != ISD::FP_TO_FP16) in combineFP16_TO_FP()
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